LCE-780308-EM User`s Manual (Preliminary)
Contents
1. 15 LCE 780308 EM User s Manual With the LCE 780xxx EM daughter board on a stable surface connect the motherboard to the daughter board by gently applying pressure on the mating connectors Avoid applying pressure on the plastic cover You should feel and hear the connectors on the motherboard and daughter board snap together Apply pressure on the motherboard For a secure connection replace the screws threading them up through the daughter board into the spacers on the motherboard 3 3 Connect Probe Cables to User Target Make sure that power for the user target is off Connect the other end of the probe or ribbon cable to the user target Refer to Chapter 4 for pin assignments for both connectors Reconnect the AC power adapter to the LCE 78K0 16 LCE 780308 EM User s Manual 3 4 Connect LCE K0 System to Host Computer Connect the LCE K0 system to the host computer with a 25 pin male to male parallel cable included with the motherboard Rear side of the LCE 78K0 Host PC Bi directional Parallel Cable 3 5 Power On Sequence When applying power to the systems connected above follow the sequen2. GC GK ERA Boo A LL BA ao PO E 74 L 60 1 602 PO IE a S It 167 200 Es 10 irs 2AVBB E 28 Il 12 68 VDDNote4 9 13 68 VDDNote4 10 EE A T AE EA A APS ARES LE Zi E AE gt ee iS ie gt AAA EA polo Nr gt E ES IT 8 e gt IG ET 51 P37 26 41 a 2 AA EAT rr L 385 E RA E A ESTAS Nr 167885 EST PEA E E E ee ee po O Ns 88 BB GE 2 Fe 1 Nt rs eee il A ES A O A E PSA ee ee ee eee 80 PIANI 45 31 1 P15 ANI5 46 32 Target Signal X1 XT1 P07 AVSS RESET AVREFO AVREF1 P20 P21 P22 n C n c n c P40 ADO P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P60 P61 P62 P63 P64 RD P65 WR P66 WAIT P67 ASTB n c n c P120 P121 P122 P123 P124 P125 P126 P127 P130 ANOO P131 ANO1 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 N o LCE 780308 EM User s Manual J4 Pin Target Pin Target Signal J5Pin Target Pin Target Signal GC GK GC GK 47 P16 ANI6 P56 A14 48 P17 ANI7 P57 A15 49 33 VSSwoez 49 GND Notes 50 71 IC Note 2 50 GND Note 6 Note 1 P4 pins marked Note 1 carry signals not used for 80 pin devices do not connect to target Note 2 VSS and IC on the target pins are connected to GND on the LCE 780308 EM Note 3 X2 and XT2 on the target are not connected on the LCE 780308 EM Note 4 VDD on the target is connected to UVDD on the LCE 780308 EM on both P4 pin 9 and P4 pin
3. 106 48 105 49 112 50 111 25 LCE 780308 EM User s Manual 4 5 J2 Probe 80 Pin Assignments NP 80GC and NP 80GK Target Pin Number J2 Pin Number Target Pin Number J2 Pin Number 102 101 106 105 112 111 26
4. 4 will either connect or disconnect mask option pull up resistors to the P60 P63 signals Setting a switch to the ON position will connect the pull up resistor and setting it to OFF will disconnect the resistor Note that if the ID78K0 LCE software has set the corresponding software controlled switch to ON the pull up resistor will be connected regardless of the setting of the hardware switch Under normal operation all SW1 switches should be set to OFF so as not to interfere with the operation of the software controlled switches in the ID78K0 LCE software Table 2 4 2 SW1 Settings for P60 P63 Mask Options Port Bit Sw1 Switch setting Port Setting Switch P60 SW1 1 Off P60 has no pull up On P60 has 39K pull up to VDD P61 SW1 2 Off P61 has no pull up On P61 has 39K pull up to VDD P62 Sw1 3 Off P62 has no pull up On P62 has 39K pull up to VDD P63 SW1 4 Off P63 has no pull up On P63 has 39K pull up to VDD 10 LCE 780308 EM User s Manual 2 5 Using P07 XT1 As Input From Probe The devices emulated by the LCE 780308 EM board have an input pin named P07 XT1 or XT1 P07 This pin can be used either as a parallel input read as bit 7 of port PO or as the XT1 subclock source The ID78K0 LCE program has a Mask Option setting for port P07 XT I setting it as either P07 input port or XT1 subclock This option setting has no effect The actual probe pin for PO7 XT1 can be used as eit
5. Optional An emulation probe is optional This is another method of connecting to the user target provided a conversion socket adapter is installed on the target Select the probe best suited for your target device package For target devices in the 80 pin plastic OFP package GC suffix or 80 pin plastic TOFP package GK suffix an appropriate probe and socket adapter to accept the probe should be used These are the NP 80GC and NP 80GK probes For connection of these probes to the LCE 780308 EM connector J2 should be used this connector is labelled PROBE 80 For target devices in the 100 pin plastic LQFP package GC suffix or 100 pin plastic QFP package GF suffix an appropriate probe and socket adapter to accept the probe should be used These are the NP 100GC and NP 100GF probes For connection of this probe to the LCE 780078 EM connector J1 should be used this connector is labelled PROBE 100 Table 2 3 1 Emulation Probe and Socket Example Target Emulation Probe Conversion Device Socket Adapter uPD780058GC NP 80GC EV 9200GC 80 connected to J2 uPD780058GK NP 80GK EV TGK 080SBW connected to J2 uPD780308GC NP 100GC EV TGC 100SDW connected to J1 uPD780308GF NP 100GF EV 9200GF 100 connected to J1 Please refer to Chapter 4 for pin assignments LCE 780308 EM User s Manual 2 4 P60 P63 Pull Up Resistor Mask Options The uPD78054 and uPD780058 subseries target
6. this case AVSS in the target system should be connected to target ground 13 LCE 780308 EM User s Manual Table 2 6 4 JP6 Settings for AVSS JP6 Setting AVSS Connection Open AVSS on probe JP6 1 to JP6 2 GND on LCE 780308 EM and AVSS on probe factory setting 14 LCE 780308 EM User s Manual CHAPTER 3 INSTALLATION This chapter explains how to connect the LCE 780308 EM to the LCE 78K0 and the user target system and start operation of the LCE KO system 3 1 Connect Probe Cables to LCE 780308 EM Connect the probe or the ribbon cables to the respective connectors on the LCE 780308 EM Ribbon Cables Emulation Probe 3 2 Connect LCE 780308 EM to LCE 78K0 Turn off the power from the LCE 78K0 motherboard Remove the AC power adapter from the J1 power input on the LCE 78K0 motherboard At the end of the LCE 78K0 with the J3 and J4 connectors remove the two screws at the bottom of the stand offs as shown
7. 10 this signal is used for sensing target voltage but does not supply power to the target Note 5 J5 pins marked n c are not connected Note 6 J5 pins marked GND are connected to GND on the LCE 780308 EM 21 LCE 780308 EM User s Manual 4 3 J1 Probe 100 Pin Assignments NP 100GC Target Pin 100GC J1 Pin Number Target Pin 100GC J1 Pin Number 1 4 2 3 3 8 4 7 5 14 6 13 7 18 8 17 9 22 10 21 11 28 12 27 13 92 14 91 15 98 16 97 17 102 18 101 19 106 20 105 21 112 22 111 23 116 24 115 25 87 26 88 27 83 28 84 29 77 30 78 31 73 32 74 33 69 34 70 35 63 36 64 37 61 38 62 39 65 40 66 41 71 42 72 43 75 44 76 45 79 22 LCE 780308 EM User s Manual Target Pin 100GC 46 47 48 49 50 J1 Pin Number 42 Target Pin 100GC 96 J1 Pin Number 80 85 86 89 90 23 LCE 780308 EM User s Manual 4 4 J1 Probe 100 Pin Assignments NP 100GF Target Pin 100GF J1 Pin Number Target Pin 100GF J1 Pin Number 1 6 2 5 3 33 4 34 5 37 6 38 7 43 8 44 9 47 10 48 11 51 12 52 13 57 14 58 15 59 16 60 17 55 18 56 19 49 20 50 21 45 22 46 23 41 24 42 25 35 26 36 27 31 28 32 29 4 30 3 31 8 32 7 33 14 34 13 35 18 36 17 37 22 38 21 39 28 40 27 41 92 42 91 43 98 44 97 24 LCE 780308 EM User s Manual Target Pin 100GF J1 Pin Number Target Pin 100GF J1 Pin Number 45 102 46 101 47
8. 22 P33 23 33 ee se 23 19 47 P34 24 P35 25 40 68 s 2 21 49 P36 26 41 69 S9 26 22 50 P37 27 P25 28 P27 29 P26 30 P70 31 P71 32 P72 33 P90 S31 34 49 77 str 34 62 90 P91 S30 35 50 78 ste 35 61 89 P92 S29 36 51 79 s19 36 60 88 P93 S28 37 52 80 S20 37 59 87 P94 S27 38 53 81 s21 38 58 86 P95 S26 39 P96 S25 40 P97 S24 41 P10 42 P11 43 P12 44 P13 45 P14 33 46 29 57 VLC1 46 5 P15 OO OO N OQ O AI OO Nh gt LCE 780308 EM User s Manual J3 Pin Target Pin Target Pin Target Signal J4 Pin Target Pin Target Pin Target Signal 100GC 100GF 100GC 100GF 47 VLC2 47 6 34 Pie 48 BIAS P17 49 99 27 AVSS VSSO Note 2 50 78 6 IC Note 2 50 12 40 VSS1 Note 2 Note 1 P4 pins 7 and 8 carry signals not used for 100 pin devices do not connect to target Note 2 VSSO VSS1 and IC on the target pins are connected to GND on the LCE 780308 EM Note 3 X2 and XT2 on the target are not connected on the LCE 780308 EM Note 4 VDDO and VDD1 on the target are both connected to UVDD on the LCE 780308 EM this signal is used for sensing target voltage but does not supply power to the target 19 LCE 780308 EM User s Manual 4 2 J4 J5 Probe 80 Ribbon Cable Pin Assignments J4 Pin CO N On B Oo Rho gt Target Pin Target Signal J5 Pin Target Pin GC GK
9. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
10. ce below 1 Turn on the host computer system 2 Turn the power switch on the LCE 78K0 motherboard to the ON position This will cause the green LED to turn on indicating power is being supplied to the system 3 Turn on power to the user target system 4 Run the ID78K0 LCE debugger on the host PC 3 6 Power Off Sequence and Disconnect When turning power off and disconnecting follow the reverse sequence 1 Turn power off to the user target system 2 Turn the power switch on the LCE 78K0 motherboard off 3 Disconnect the LCE KO system from the host PC 4 Disconnect the AC adapter from the LCE KO system 5 Disconnect the LCE KO system from the user target 17 LCE 780308 EM User s Manual CHAPTER 4 CONNECTOR PIN ASSIGNMENTS 4 1 J3 J4 Probe 100 Ribbon Cable Pin Assignments J3 Pin Target Pin Target Pin Target Signal J4 Pin Target Pin Target Pin Target Signal 100GC 100GF 100GC 100GF 8 TE MS EN 85 48 EGO 8 9 xmpo 2 860 14 Po P02 P03 24247 fie 482 TOOME 55 380 ae 7 804 9 37 AVREF 6 90 18 P05 Ee Tie A CE ECO Ed NE ESTA E 987 T EE1US58 8 2 ee 69 9 P8zs37 9 8 36 VDDO Note4 10 68 0 Passas 10 82 10 VDD1 Notes 11 P110 12 665 47 P85S34 12 92 20 PTN 13 P112 14 P113 15 P114 16 26 64 COM J aef o aa P15 175288 10600 k 280 M ST 1 987 PTG 18 33 6 58 8 98 205265 1 PA 19 P30 20 P31 21 P32
11. devices emulated by the LCE 780308 EM board have factory programmable mask options allowing pull up resistors to be attached to the lower four bits of Port 6 P60 through P63 These ports are open drain N channel I O ports and can be configured as open drain outputs by omitting the pull up resistor mask option These optional pull up resistors are provided on the LCE 780308 EM board and can be connected or disconnected to the appropriate P60 P63 signals emulating the mask options The mask option pull up resistors can be switched in or not by using either the ID78K0 LCE debugger software or by using the SW1 hardware switch In normal operation the ID78K0 LCE debugger would be used to control this option and the SW1 hardware switches would all be set to OFF 2 4 1 Setting P60 P63 Mask Options with ID78K0 LCE Software The factory programmable mask options can be emulated by setting ID78K0 LCE debugger to turn on or off appropriate software controllable switches to connect or disconnect on board pull up resistors to P60 P63 These switches should be set for the mask options desired in the final target chip The software controlled switches are turned on or off using the Mask Options dialog box in the ID78K0 LCE debugger From the Options menu choose the Mask Options menu item The Mask Options dialog box will be displayed Select the desired port bit from the drop down list box select the desired setting ON or OFF and click the Set butt
12. erospace equipment submarine cables nuclear reactor control systems and life support systems Standard quality grade devices are recommended for computers office equipment communication equipment test and measurement equipment machine tools industrial robots audio and visual equipment and other consumer products For automotive and transportation equipment traffic control systems anti disaster and anti crime systems it is recommended that the customer contact the responsible NECEL salesperson to determine the reliability requirements for any such application and any cost adder NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death If customers wish to use NECEL devices in applications not intended by NECEL customers must contact the responsible NECEL salespeople to determine NECEL s willingness to support a given application LCE 780308 EM User s Manual CHAPTER 1 GENERAL INFORMATION The LCE 780308 EM is an emulation board or daughter board for the LCE K0 development system supporting NEC s uPD780058 uPD78054 uPD78064 and uPD780308 sub series of 8 bit single chip microcontrollers By combining this daughter board with the LCE 78K0 motherboard these sub series can be emulated efficiently The LCE 780308 EM is shipped with the following contents LCE 780308 EM daughter board User s manual Two 50 pin ribbon cable
13. esas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equip
14. ground AVSS and reference voltage AVREFO and AVREF1 inputs Normally these analog voltage inputs are connected in the target system with AVSS connected to VSS and AVDD connected to VDD and with AVREFO and AVREF1 connected to a voltage references which may also be VDD The jumpers on the LCE 780308 EM allow these analog voltage inputs to be connected to on board voltage sources in case these inputs are unconnected in the target system The diagram below shows the pin numbering for these jumpers Je Jrara 14 moles 12 123 Figure 2 6 1 Analog Jumper Pin Numbering 2 6 1 JP1 AVDD Jumper Options JP1 is a two position jumper for AVDD It allows AVDD on the peripheral emulator to be connected either to the AVDD input from the probe default or to VDD on the LCE 780308 EM AVDD is used only for the uPD78054 and uPD780058 subseries for the uPD78064 and uPD780308 subseries AVDD should be connected to VDD Table 2 1 JP1 Settings for AVDD JP1 Setting AVDD Connection JP1 2 to JP1 1 VDD on LCE 780308 EM JP1 2 to JP1 3 AVDD on probe factory setting 12 LCE 780308 EM User s Manual 2 6 2 JP2 AVREFO Jumper Options JP2 is a three position jumper arranged in a T shape for AVREFO It allows AVREFO on the peripheral emulator to be connected to AVREFO on the probe default to ground or to the AVDD pin on the peripheral emulator which may be AVDD or VDD as selected with JP1 For the uPD78064 a
15. her P07 or XT1 regardless of the Mask Option setting However the LCE 78K0 motherboard does have an option allowing either a standard on board 32KHz clock or the input from the probe pin P07 XT 1 to be supplied to the P07 XT1 input of the peripheral emulator device In order to use the probe input as either P07 or XT1 the ID78K0 LCE configuration dialog must have the Subclock option set to User rather than 32KHz Chip Name uPD Internal ROM RAM Internal ROM jaz K Byte Restore Project Internal RAM 1024 Byte fa nep Clock Voltage Peripheral Break 1 Mask Main 5 MHz z intemal Break Sub User y Taaa Non Break Cancel addi M RESET m Memory Attribute Mapping Address Add Emulation ROM y ag Delete di Figure 2 5 1 ID78K0 LCE Configuration Dialog Box When the 32 KHz option is selected in the Configuration dialog the on board 32 KHz clock source is connected to PO7 XT1 Reading port PO in this configuration will result in an indeterminate value for bit 7 11 LCE 780308 EM User s Manual 2 6 Jumper Settings for Analog Voltage Inputs The target devices emulated by the LCE 780308 EM have analog voltage inputs to A D converters ANIO to ANI7 In addition the uPD78054 and uPD780058 subseries also have analog outputs from D A converters ANOO and ANO1 These analog inputs and outputs require separate power AVDD
16. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Ren
17. ment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation Characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain
18. nd uPD780308 subseries AVREFO is equivalent to the AVREF pin If it is desired to connect AVREF to VDD for these devices connect JP1 so that AVDD is connected to VDD Table 2 6 2 JP2 Settings for AVREFO JP2 Setting AVREFO Connection JP2 2 to JP2 1 AVDD as selected by JP1 JP2 2 to JP2 3 GND JP2 2 to JP2 4 AVREFO on probe factory setting 2 6 3 JP3 AVREF1 Jumper Options JP3 is a three position jumper arranged in a T shape for AVREF1 It allows AVREF1 on the peripheral emulator to be connected to AVREF1 on the probe default to ground or to the AVDD pin on the peripheral emulator which may be AVDD or VDD as selected with JP1 AVDD is used only for the uPD78054 and uPD780058 subseries for the uPD78064 or uPD780308 subseries AVREF1 should be jumpered to either GND or VDD selected for AVDD with JP1 Table 2 6 3 JP2 Settings for AVREF1 JP3 Setting AVREFI Connection JP3 2 to JP3 1 AVDD as selected by JP1 JP3 2 to JP3 3 GND JP3 2 to JP3 4 AVREFI on probe factory setting 2 6 4 JP6 AVSS Jumper Options JP6 is a two pin jumper for AVSS AVSS on the peripheral emulator is always connected to AVSS on the probe When JP6 is inserted default AVSS is connected to ground providing a closer ground reference for AVSS For normal design AVSS would always be connected to the ground or VSS pins of the target device Removing JP6 will disconnect AVSS from ground on the LCE 780308 In
19. oducts or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics ENESAS User s Manual LCE 780308 EM Emulation Board Preliminary Document No U18142EU1VOUMOO0 1st edition Preliminary Version 10 26 01 2001 NEC Electronics Inc All rights reserved Printed in U S A LCE 780308 EM User s Manual No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc NECEL The information in this document is subject to change without notice All devices sold by NECEL are covered by the provisions appearing in NECEL s Terms and Conditions of Sales only including the limitation of liability warranty and patent provisions NECEL makes no warranty express statutory implied or by description regarding information set forth herein or regarding the freedom of the described devices from patent infringement NECEL assumes no responsibility for any errors that may appear in this document NECEL makes no commitments to update or to keep current information contained in this document The devices listed in this document are not suitable for use in applications such as but not limited to aircraft control systems a
20. on The appropriate software controlled switch will be turned on or off Mask Option Pin group name Help Option name Set ON Restore e Figure 2 4 1 ID78K0 LCE Mask Option Dialog Box Note the ID78K0 LCE Mask Option dialog box also has an entry to set P07 XTI as either P07 or XT1 This setting actually has no effect See the section below on setting P07 XTI LCE 780308 EM User s Manual Table 2 4 1 ID78K0 LCE Settings for P60 P63 Mask Options Port Bit ID78K0 LCE Option Port Setting Mask Option Setting P60 P60 OFF P60 has no pull up ON P60 has 39K pull up to VDD P61 P61 OFF P61 has no pull up ON P61 has 39K pull up to VDD P62 P62 OFF P62 has no pull up ON P62 has 39K pull up to VDD P63 P63 OFF P63 has no pull up ON P63 has 39K pull up to VDD The settings for the Mask Options may be saved in an ID78K0 LCE project file and reloaded so it will not be necessary to set the Mask Options manually every time ID78K0 LCE is started However it is also possible to set the hardware switch SW I to switch in pull up resistors for P60 P63 Note that if either the software switch or the hardware switch is on the pull up resistor is connected In order to not have pull up resistors connected to the P60 P63 bits both the software and hardware switches must be off 2 4 2 Setting P60 P63 Mask Options with SW1 Hardware Switches The SW1 switches SW 1 1 through SW1
21. pin female to female cables that connect the LCE K0 system to the user target One end of the ribbon cables connects to the dual row male shrouded headers with latching levers on the daughter board either J3 and J4 or J4 and J5 and the other connects to matching connectors on the user target Devices supported by the LCE 780308 EM board fall into two categories 80 pin devices in either a GC footprint 14 x 14 mm QFP or a GK footprint 12 x 12 mm TQFP or 100 pin devices in either a GC footprint 14 x 14 mm LQFP or GF footprint 14 x 20 mm QFP In order to emulate 80 or 100 pins two ribbon cables are necessary to carry the device signals These ribbon cables are included with the daughter board The side of the ribbon cable that has a red stripe is pin 1 To emulate 80 pin devices the ribbon cables are connected to J4 and J5 these connectors carry all signals necessary for emulation of 80 pin devices The legend PROBE 80 is marked on the board next to these connectors Please refer to Table A 1 in Chapter 4 for pinouts of the Probe 80 ribbon cables To emulate 100 pin devices the ribbon cables are connected to J3 and J4 these connectors carry all signals necessary for emulation of 100 pin devices The legend PROBE 100 is marked on the board next to these connectors Please refer to Table A 2 in Chapter 4 for pinouts of the Probe 100 ribbon cables LCE 780308 EM User s Manual 2 3 J1 and J2 Emulation Probe Connectors
22. s CD ROM containing debugger assembler compiler device files and documentation 1 1 Basic Configuration Parameter Description Subseries Supported Target Devices uPD780058 subseries uPD780053GC uPD780053GK uPD780054GC uPD780054GK uPD780055GC uPD780055GK uPD780056GC uPD780056GK uPD780058GC uPD780058GK uPD78054 subseries uPD78052GC uPD78052GK uPD78053GC uPD78053GK uPD78054GC uPD78054GK uPD78055GC uPD78055GK uPD78056GC uPD78056GK uPD78058GC uPD78058GK uPD78064 subseries uPD78062GC uPD78062GF uPD78063GC uPD78063GF uPD78064GC uPD78064GF uPD780308 subseries uPD780306GC uPD780306GF uPD780308GC uPD780308GF Clock supply Internal Installed on the motherboard External Pulse input Low voltage compatible At least 2V LCE 780308 EM User s Manual 1 2 LCE KO System Configuration The LCE KO system configuration is as shown below The system consists of a host PC running the ID78K0 LCE debugger communicating through the PC s LPT1 parallel port via a standard parallel cable to the combination of LCE 78K0 motherboard plus LCE 780308 EM daughter board For connection to a target system either a pair of 50 pin ribbon cables or the combination of an NEC probe plus socket adapter can be used Debugger ID 78K0 LCE amp Device File A Host PC with Windows DF78K0 J 95 98 NT Straight Through Parallel Cable sold separately Motherboard Power adap
23. s and probes and Chapter 4 for pin assignments of these connectors D7 is an LED which is used to indicate that power is applied to the target system JP1 JP2 JP3 and JP6 are jumpers for analog voltages They allow the optional connection of analog signals AVDD AVREFO AVREF1 and AVSS to power ground or reference voltages provided on the LCE 780308 EM board when these analog voltages are not provided in the user target system JP4 is provided for optional on board connection of LCD display voltage divider resistors In normal operation the voltage divider for LCD display voltages should be located on the user target system and JP4 should be left unconnected SW 1 is a dip switch for enabling or disabling pull up resistors on the P60 P63 input pins to emulate mask options of the target device These mask option pull up resistors are also switched in or not by software controlled switches under control of the ID78K0 LCE debugger In normal operation the switches on SW1 should all be set to the OFF position P1 is a connector for programming PLD logic on the LCE 780308 EM It is used only for factory programming and should be left unconnected in normal operation P2 is a connector for an external trigger input to the LCE KO system P3 and P4 are the connectors for the motherboard The motherboard connects on top of the daughter board LCE 780308 EM User s Manual 2 2 J3 J4 J5 Ribbon Cables The ribbon cables are two 50
24. ter sold separately LCE 78K0 sold separately LCE 780308 EM Daughter Board Probe NP 80GC NP 80GK NP 100GC or NP 100GF 2 Ribbon ua cables X sold separately Conversion Socket EV 9200GC 80 for NP 80GC probe EV TGK 080SBW for NP 80GK probe EV TGC 100SDW for NP 100GC probe EV 9200GF 100 for NP 100GF probe sold separately LCE 780308 EM User s Manual CHAPTER 2 COMPONENTS This chapter introduces the main components of the LCE 780308 EM daughter board unit 2 1 Daughter Board Layout 13 J2 T 70 o PROBE 100 2 e 4 gt 50 117 119 9 0 L PROBE 100 5 1 49 PROBE POWER NEC etctronics Inc O D7 LCE 780308 EM JP6_ JP3 me nr E P2 Ut o 1 Figure 2 1 1 LCE 780308 Top Layout LCE 780308 EM User s Manual This is a drawing of the top of the LCE 780308 EM board this side will face upward in the assembled system Ul is a uPD78P0308 device and U2 is a uPD78P054 device Together these two devices provide emulation of the peripheral devices such as parallel ports serial ports timers LCD drivers etc for the supported 78K0 devices J1 J2 J3 J4 and J5 are connectors to the user target system These connectors contain all the pins available on the emulated device J1 and J2 are KEL connectors for device probes while J3 J4 and J5 are dual row male shrouded headers with latching levers for the ribbon cables Please see the section below about ribbon cable
25. use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics pr
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