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PowerPC 7457 RISC Microprocessor PC7457 - Digi-Key

1. fel 1160 enss1 A1u3 z enss A1u3 9 enss 2 A1u3 p Geet Ydd anss 49 anss YA 13 01 anand 09 60 68110 190 6 0 9050 q 11 33 62 SHS suononisu 119 96 aime NINN eea wn X yoyedsiq z HI 3 8702 LHE UO 90080 0006 euy IWal uaweabeuey 19110 8 9 9080 a19 1 3 82 06 Water Lape avlay 2e ai wopeus 1 ODOT 184018 jun Bulsseoo1g Du Inn 39019 Aue HS pon 21 MM ae 191090 9109 910700 9586 SU NWN 00110 1501 anand 0010119 pun uononysul 91893 12011001 un 0011916100 suonon jsu p 1 82 Ze T AIMEL 5345D HIREL 07 06 2 General Parameters AMEL Table 2 1 provides a summary of the general parameters of the PC7457 Table 2 1 Device Parameters Parameter Description Technology 0 13 um CMOS nine layer metal Die size 9 1 mm x 10 8 mm Transistor count 58 million Logic design Fully static Packaged PC7447 surface mount 360 ceramic ball grid array CBGA PC7457 surface mount 483 ceramic ball grid array CBGA HiTCE CBGA Core power supply 1 3V 500 mV DC nominal or 1 1V 50 mV nominal see Recommended Operating Conditions on page 12 I O power supply 3 Overview 1 8V 5 DC or 2 5V 5 for recommended operatin
2. e 4 6 8 0 4 6 8 8 CODDDDQDDODO0000000000 Jaa 56666661 0000000000000000600000 w CODD000000000000000000l v 0000000000000000000006 u 0000000000000000000000 t CODDDDDDDDDDDODOOO OOOO lp 0000000000000000000000 p 0000000000000000000000 N C000000000000000000000 m 1 27 BSC CODDDDDDDDDODOOOOO OOOO IL C000000000000000000000 le a O00000000000000 0600600l E 125 CODDDDDD0D000000000 0000 lH 0000000000000000000000 4 E es Moss Ees 84 00000000000000000000600 D CODDDDOODDDDDDNDOOO OOOO lc 00000000000006000000 B bOODDOODOODDOOOOOO OOOO IA 0 3 10 15 C gt CH 14 Substrate Capacitors for the PC7457 483 HCTE ROHS Compliant Figure 12 1 shows the connectivity of the substrate capacitor pads for the PC7457 483 HCTE All capacitors are 100 nF AMEL a 5345D HIREL 07 06 AMEL Figure 14 1 Substrate Bypass Capacitors for the PC7457 483 HCTE Pad Number A1 CORNER a e C1 1 C2 1 C3 1 C4 1 C5 1 06 1 C42 C52 C6 2 C24 1 C7 2 7 1 es eno f voo oo ovo ee eno D voo C18 1 C17 1
3. Table 7 6 Effect of L3OHCR Settings on L3 Bus AC Timing Output Valid Time Output Hold Time Parameter Parameter Field name Affected Signals Value Symbol Change Symbol Change Unit Notes 0000 0 0 4 0001 50 50 L3AOH 2 24 tL3CHOV L3CHOX 3_CNTL 0 1 0b10 100 100 0011 150 150 00000 0 0 4 00001 50 50 5 0b010 i 100 100 8 All signals latched LAGHOY t by SRAM 0b011 L3CHDV 150 L3CHOX 150 6 L3CLKn_OH ito tL3CLDV L3CHDX 0b100 200 130 200 5 L3_CLKn 0b101 250 250 6 ps 0b110 300 300 5 0b111 350 350 5 00000 0 0 4 0b001 50 50 0b010 100 100 L3_DATA n n 7 00011 13010 150 tL3CHDX 150 L3DOHn i L3_DP n 8 0b100 L3CLDV 200 L3CLDX 200 0b101 250 250 0b111 350 350 0b111 350 350 Notes 1 Refer to the PC7450 RISC Microprocessor Family User s Manual for specific information regarding L3OHCR See Table 7 7 on page 29 and Table 7 8 on page 31 for more information Default value 7 2 3 Guaranteed by design not tested or characterized 4 5 Increasing values of L3CLKn_OH delay the L3_CLKn signal effectively decreasing the output valid and output hold times of all signals latched relative to that clock signal by the SRAM see Figure 7 6 on page 30 and Figure 7 8 on page 32 7 2 4 2 L3 Bus AC Specifications for DDR MSUG2 SRAMs When using DDR MSUG2 SRAMs at the L3 interface the parts should be connected as shown
4. Notes 1 Dimensioning and tolerancing per ASME Y14 5M 1994 2 Dimensions in millimeters 3 Top side A1 corner index is a metallized feature with various shapes Bottom side A1 corner is designated with a ball miss ing from the array AMEL s 5345D HIREL 07 06 AMEL 12 Substrate Capacitors for the PC7457 483 HCTE Figure 12 1 shows the connectivity of the substrate capacitor pads for the PC7457 483 HCTE All capacitors are 100 nF Figure 12 1 Substrate Bypass Capacitors for the PC7457 483 HCTE Pad Number A1 CORNER Ge ee ae l C1 1 C2 1 C3 1 C4 1 C4 2 C24 1 C7 2 7 1 C9 1 C23 1 C22 2 C23 2 C24 2 C8 2 C8 1 C22 1 C11 1 C10 1 C20 1 C21 1 C12 2 C11 2 C10 2 C9 2 C19 2 C20 2 C21 2 C19 1 C12 1 C18 2 C17 2 C16 2 C152 C142 C13 2 I C18 1 C17 1 C16 1 C15 1 C141 C13 1 44 PC7457 VE mg DC 71 57 13 Mechanical Dimensions for the PC7457 483 HCTE ROHS compliant Figure 13 1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457 483 HCTE package Figure 13 1 Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457 483 HCTE Package 2X Capacitor Region A1 CORNER 10 2
5. Termination 4 SHDO SHDI BVSEL Processor HIT BMODE 0 1 Status Control PMON_IN DBG PMON_OUT Data Arbitration DTI 0 3 SYSCLK DRDY PLL_CFG 0 3 2 PLL_EXT Clock Control D 0 63 EXT_QUAL Data Transfer DP 0 7 CLK_OUT TCK Data TA TDI Transfer TEA TDO Test Interface Termination JTAG TMS TRST VDD AVDD GND GVpp Notes 1 For the PC7457 there are 19 L3_ADDR signals L3 _ADDR 0 18 2 For the PC7447 and 1 7457 there are 5 PLL_CFG signals PLL_CFG 0 4 10 PC7457 ee mg DC 71 57 5 Detailed Specification This specification describes the specific requirements for the microprocessor PC7457 in compli ance with Atmel standard screening 6 Applicable Documents 1 MIL STD 883 Test methods and procedures for electronics 2 MIL PRF 38535 Appendix A General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein 6 1 Design and Construction 6 1 1 Terminal Connections Depending on the package the terminal connections are as shown in Recommended Operat ing Conditions on page 12 and Figure 4 1 on page 10 6 1 2 Absolute Maximum Ratings Symbol Characteristic Maximum Value Unit Voo Core supply voltage 0 3 to 1 60 V AVoo PLL supply voltage 0 3 to 1 60 v OVpo 9 BVSEL 0 0 3 to 1 95 V Processor bus supply voltage OVpp 9 BVSEL HRESET or OVpp 0 3 to 2 7 V
6. Supports parity on cache and tags Configurable core to L3 frequency divisors 64 bit external L3 data bus sustains 64 bit per L3 clock cycle e Separate memory management units MMUs for Instructions and data 52 bit virtual address 32 or 36 bit physical address Address translation for 4 Kbyte pages variable sized blocks and 256M bytes segments AMEL 7 5345D HIREL 07 06 AMEL Memory programmable as write back write through caching inhibited caching allowed and memory coherency enforced memory coherency not enforced on a page or block basis Separate IBATs and DBATs eight each also defined as SPRs Separate instruction and data translation lookaside buffers TLBs Both TLBs are 128 entry two way set associative and use LRU replacement algorithm TLBs are hardware or software reloadable that is on a TLB miss a page table search is performed in hardware or by system software Efficient data flow Although the VR LSU interface is 128 bits the L1 L2 L3 bus interface allows up to 256 bits The L1 data cache is fully pipelined to provide 128 bits cycle to or from the VRs L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache As many as eight outstanding out of order cache misses are allowed between the L1 data cache and L2 L3 bus As many as 16 out of order transactions can be present on the MPX bus Store merging for mu
7. Q O O O O O Notes 1 Dimensioning and tolerancing per ASME Y14 5M 1994 2 Dimensions in millimeters gt W Capacitor Region 1 0 35 Times Pom mn wax 1 27 BSC fee ESN ETS e fe CEE 3 Top side A1 corner index is a metallized feature with various shapes Bottom side A1 corner is designated with a ball miss ing from the array 5345D HIREL 07 06 AMEL 41 AMEL 10 Substrate Capacitors for the PC7457 483 CBGA Figure 10 1 shows the connectivity of the substrate capacitor pads for the PC7457 483 CBGA All capacitors are 100 nF Figure 10 1 Substrate Bypass Capacitors for the PC7457 483 CBGA Pad Number A1 CORNER Ge ee ae l C1 1 C2 1 C3 1 C4 1 C4 2 C24 1 C7 2 7 1 C9 1 C23 1 C22 2 C23 2 C24 2 C8 2 C8 1 C22 1 C11 1 C10 1 C20 1 C21 1 C12 2 C11 2 C10 2 C9 2 C19 2 C20 2 C21 2 C19 1 C12 1 C18 2 C17 2 C16 2 C152 C142 C13 2 I C18 1 C17 1 C16 1 C15 1 C141 C13 1 42 PC7457 NN mg DC 71 57 11 Mechanical Dimensions for the PC7457 483 HCTE Figure 11 1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457 483 HCTE package Figure 11 1 Mechanical
8. Bus SYSCLK Frequency Bus to Core Core to VCO 33 3 50 66 6 75 83 100 133 167 PLL_CFG 0 4 Multiplier Multiplier MHz MHz MHz MHz MHz MHz MHz MHz 01000 2x 2x 10000 3x 2x 667 10100 4x 2x 1333 667 835 10110 5x 2x Ve EM 100 733 919 10010 5 5x 2x 1466 1837 600 800 1002 11010 SS 1200 1600 2004 650 866 1086 01010 ar x 1300 1730 2171 700 931 1169 00100 Ta 2x 1400 1862 2338 623 750 1000 1253 00010 KX ax 1245 1500 2000 2505 600 664 800 1064 11009 Ox ax 1200 1328 1600 2128 638 706 850 1131 ou Es ox 1276 1412 1700 2261 600 675 747 900 1197 44131 e 1200 1350 1494 1800 2394 633 712 789 950 1264 OIO Se ES 1266 1524 1578 1900 2528 AMEL e 5345D HIREL 07 06 AMEL Table 15 1 PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts Continued Example Bus to Core Frequency in MHz VCO Frequency in MHz Bus SYSCLK Frequency Bus to Core Core to VCO 33 3 50 66 6 75 83 100 133 167 PLL_CFG 0 4 Multiplier Multiplier MHz MHz MHz MHz MHz MHz MHz MHz 10191 10x 2x SC SC esd Se 19901 e om 1 11 SC Bie 1 W 2x SE SE Be Ge 90990 Je SS Wee Se FEH EH e 2x Be 1 1 Bee Ke Ge SES Rees ES Bee ees ane Ge Bo Ha 13K 2x aa Bee SCH Geer one bes CS Wee Ge 6 Ke wane a e 700 933 1050 1162 1400 1866 21
9. HRESET Am tMVRH gt EH Mode Signals AMEL 2 5345D HIREL 07 06 Figure 7 3 AMEL Figure 7 3 provides the input output timing diagram for the PC7457 Input Output Timing Diagram SYSCLK VM VM VM gt lt taXKH tAVKH gt gt lt IXKH tIVKH gt All Inputs ge zua ai tKHAX gt lt KHDV gt lt tKHDX gt lt tkHOV t All Outputs SS GE ARTRY SHDO SHD1 tKHOE gt All Outputs Except TS ARTRY SHDO SHD1 lt tKHTSV gt lt tKHOZ IKHTSPZ tKHARPZ 7 2 3 Note VM Midpoint Voltage OVpp 2 L3 Clock AC Specifications The L3_CLK frequency is programmed by the L3 configuration register core to L3 divisor ratio See Table 15 1 on page 47 for example core and L3 frequencies at various divisors Table 7 4 on page 25 provides the potential range of L3_CLK output AC timing specifications as defined in Figure 7 4 on page 26 The maximum L3_CLK frequency is the core frequency divided by two Given the high core fre quencies available in the PC7457 however most SRAM designs will be not be able to operate in this mode using current technology and as a result will select a greater core to L3 divisor to provide a longer L3_CLK period for read and write access to the L3 SRAMs Therefore the typi cal L3_CLK frequency shown in Table 7 4 is considered to be the practical ma
10. Note tigcupy and t 3c py as drawn here will be negative numbers that is output valid time will be time before the clock edge 30 PC7457 ee 5345D HIREL 07 06 mg PO7457 Inputs VM VM VM VM VM L3_ECHO_CLK 0 1 2 3 tL3DXEL gt iL3DVEL gt 4 13 5 gt L3 Data and Data Parity Inputs tL83DXEH gt Notes 1 and hanne as drawn here will be negative numbers that is input setup time will be time after the clock edge 2 VM Midpoint Voltage GVpp 2 7 2 5 L3 Bus AC Specifications for PB2 and Late Write SRAMs When using PB2 or Late Write SRAMs at the L3 interface the parts should be connected as shown in Figure 7 8 on page 32 These SRAMs are synchronous to the PC7457 one L3_CLKn signal is output to each SRAM to latch address control and write data Read data is launched by the SRAM synchronous to the delayed L3_CLKn signal it received The PC7457 needs a copy of that delayed clock which launched the SRAM read data to know when the returning data will be valid Therefore L3 ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the PC7457 inputs L8_ECHO_CLKO and L3_ECHO_CLK2 respec tively Thus L8_ECHO_CLKO and L3_ECHO_CLK2 are phase aligned with the input clock received at the SRAMs The PC7457 will latch the incoming data on the rising edge of L3_ECHO_CLKO and L3_ECHO_CLK2 Table 7 8 provides the L3 bus interface AC timing spec ifications for the confi
11. t update the count register CTR or link register LR are often removed from the instruction stream 4 PC7457 me 5345D HIREL 07 06 mg DC 4 57 5345D HIREL 07 06 Eight entry link register stack to predict the target address of Branch Conditional to Link Register BCLR instructions Four integer units 105 that share 32 GPRs for integer operands Three identical lUs 1U1a IU1b and IU1c can execute all integer instructions except multiply divide and move to from special purpose register instructions IU2 executes miscellaneous instructions including the CR logical operations integer multiplication and division instructions and move to from special purpose register instructions Five stage FPU and a 32 entry FPR file Fully IEEE 754 1985 compliant FPU for both single and double precision operations Supports non IEEE mode for time critical operations Hardware support for denormalized numbers Thirty two 64 bit FPRs for single or double precision operands Four vector units and 32 entry vector register file VRs Vector permute unit VPU Vector integer unit 1 VIU1 handles short latency AltiVec integer instructions such as vector add instructions vaddsbs vaddshs and vaddsws for example Vector integer unit 2 VIU2 handles longer latency AltiVec integer instructions such as vector multiply add instructions vmhaddshs vmhraddshs and vmladduhm for example Vector floating point unit VFPU Thr
12. in Figure 7 6 Outputs from the PC7457 are actually launched on the edges of an internal clock phase aligned to SYSCLK adjusted for core and L3 frequency divisors L8_CLKO and L3_CLK1 are this internal clock output with 90 phase delay so outputs are shown synchronous to L3_CLKO and L3_CLK1 Output valid times are typically negative when referenced to L3_CLKn because the data is launched one quarter period before L3_CLKn to provide adequate setup time at the SRAM after the delay matched address control data and L8_CLKn signals have propagated across the printed wiring board Inputs to the PC7457 are source synchronous with the CQ clock generated by the DDR MSUG2 SRAMs These CQ clocks are received on the L3_ECHO_CLKn inputs of the PC7457 28 PC7457 ee 5345D HIREL 07 06 mg DC 4 5 7 An internal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal receiving latches This delayed clock is used to capture the data into these latches which comprise the receive FIFO This clock is asynchronous to all other processor clocks This latched data is subsequently read out of the FIFO synchronously to the processor clock The time between writing and reading the data is set by the using the sample point settings defined in the L3CR register Table 7 7 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9 assuming the timing relationships shown
13. Added specifications for 1267 MHz devices removed specs for 1300 MHz devices Changed recommendations regarding use of L3 clock jitter in AC timing analysis in Section L3 Clock AC Specifications on page 24 the L3 jitter is now fully comprehended in the AC timing specs and does not need to be included in the timing analysis AMEL s7 5345D HIREL 07 06 mg DC 71 57 Table of Contents 5345D HIREL 07 06 i Om A Go D 10 11 12 13 14 15 Features Ee 1 Description WEE 1 ONIN ERE EEE RS PEN SS Ba 2 oe Diagram ENE EEE EN NEN tenants 3 General Parameters 4 4 Signal Description E 10 Detailed Specification ccccsccccssescnncessnsssnnnnssssssssenssnensnsenaaeneaanaasensenens 11 Applicable E E 11 6 1 Design and Construction 11 6 2 Thermal Characteristics 13 Electrical Characteristics sesicesssssssnsienssasesncconsasvsnavesataxcistnnsasasavesasvonsssunes 19 7 1 Static Characteristics 2233 28225522 22232 53 22 2222822222 23222253232 22022 02229428322 32222523 19 7 2 Dynamic Characteristics 20 Preparation TOF DCMU LE 36 8 1 WE 36 8 2 Package Parameters for the PC7457 483 CBGA and A93HCTE 36 M
14. C16 1 C15 1 C141 C13 1 C23 1 C22 2 C23 2 C24 2 C8 2 C8 1 C22 1 C9 1 C20 1 C21 1 C12 2 C11 2 C10 2 C9 2 C11 1 C10 1 C12 1 C19 2 C20 2 C21 2 C19 1 C18 2 C17 2 C16 2 C152 C142 C13 2 46 PC7457 NN mg PO7457 15 System Design Information This section provides system and thermal design recommendations for successful application of the PC7457 15 1 Clocks The following sections provide more detailed information regarding the clocking o fthe PC7457 15 1 1 Core Clocks and PLL Configuration The PC7457 PLL is configured by the PLL_CFG 0 4 signals For a given SYSCLK bus fre quency the PLL configuration signals set the internal CPU and VCO frequency of operation The PLL configuration for the PC7457 is shown in Table 15 1 for a set of example frequencies In this example shaded cells represent settings that for a given SYSCLK frequency result in core and or VCO frequencies that do not comply with the 1 GHz column in Table 7 2 on page 20 Note that these configurations were different in some earlier PC7450 family devices and care should be taken when upgrading to the PC7457 to verify the correct PLL settings for an application Table 15 1 PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts Example Bus to Core Frequency in MHz VCO Frequency in MHz
15. FPR rename buffers 16 VR rename buffers Dispatch unit Decode dispatch stage fully decodes each instruction Completion unit The completion unit retires an instruction from the 16 entry completion queue CQ when all instructions ahead of it have been completed the instruction has finished execution and no exceptions are pending Guarantees sequential programming model precise exception model Monitors all dispatched instructions and retires them in order Tracks unresolved branches and flushes instructions after a mispredicted branch Retires as many as three instructions per clock cycle e Separate on chip L1 Instruction and data caches Harvard Architecture 32 Kbyte eight way set associative instruction and data caches Pseudo least recently used PLRU replacement algorithm 32 byte eight word L1 cache block Physically indexed physical tags Cache write back or write through operation programmable on a per page or per block basis 5345D HIREL 07 06 mg DC 71 57 Instruction cache can provide four instructions per clock cycle data cache can provide four words per clock cycle Caches can be disabled in software Caches can be locked in software MESI data cache coherency maintained in hardware Separate copy of data cache tags for efficient snooping Parity support on cache and tags No snooping of instruction cache except for icbi instruction Data cache
16. GV pp L3VSEL HRESET 0 3 to 1 65 V GVpp L3 bus supply voltage L3VSEL 0 0 3 to 1 95 V GVpp L3VSEL HRESET or GVpp 0 3 to 2 7 V Vy Processor bus 0 3 to OVpp 0 3 V Vy Input voltage L3 bus 0 3 to GVpp 0 3 V Vin JTAG signals 0 3 to OVpp 0 3 V Terme Storage temperature range 55 to 150 C Notes 1 Functional and tested operating conditions are given in Recommended Operating Conditions on page 12 Absolute max imum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the device 2 Caution Vpp AVpp must not exceed OVpp GVpp by more than 1V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences 3 Caution OVpp GVpp must not exceed Vpp AVpp by more than 2V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences 4 BVSEL must be set to 0 such that the bus is in 1 8V mode 5 BVSEL must be set to HRESET or 1 such that the bus is in 2 5V mode 6 L3VSEL must be set to HRESET inverse of HRESET such that the bus is in 1 5V mode 7 L3VSEL must be set to 0 such that the bus is in 1 8V mode 8 L3VSEL must be set to HRESET or 1 such that the bus is in 2 5V mode 9 Caution Vin must not exceed OVpp or GVpp by more than 0 3V at any time
17. Pin Number Active 1 0 I F Select INT J6 Low Input BVSEL L1_TSTCLK H4 High Input BVSEL L2_TSTCLK J2 High Input BVSEL L8VSEL A4 High Input N A L3ADDRI 18 0 1 Sie SC e SC F22 G22 H20 RIG J18 H22 J20 High Output L3VSEL L3_CLK 0 1 V22 C17 High Output L3VSEL L3_CNTL 0 1 L20 L22 Low Output L3VSEL AA19 AB20 U16 W18 AA20 AB21 AA21 T16 W20 U18 Y22 R16 V20 W22 T18 U20 N18 N20 N16 N22 M16 M18 M20 oid VE S Et A18 G14 E15 C16 A17 A16 C15 G13 C14 A14 E13 C13 G12 A13 E12 C12 L3DP 0 7 AB19 AA22 P22 P16 C20 E16 A15 A12 High UO L3VSEL L3_ECHO_CLK 0 2 V18 E18 High Input L3VSEL L3_ECHO_CLK 1 3 P20 E14 High UO L3VSEL LSSD_MODE 9 F6 Low Input BVSEL MCP B8 Low Input BVSEL No Connect A8 A11 B6 B11 11 D11 D3 D5 E11 E7 2 11 G2 H9 N A B3 C5 C7 C10 D2 E3 E9 F5 G3 G9 H7 J5 K3 L7 M5 N3 OVpp P7 R4 T3 U5 U7 U11 U15 V3 V9 V13 Y2 Y5 Y7 Y10 Y17 N A Y19 AA4 AA15 PLL_CFG 0 4 A2 F7 C2 D4 H8 High Input BVSEL PMON_IN E6 Low Input BVSEL PMON_OUT B4 Low Output BVSEL QACK K7 Low Input BVSEL QREQ y1 Low Output BVSEL SHD 0 1 L4 L8 Low UO BVSEL SMI G8 Low Input BVSEL SRESET Gi Low Input BVSEL SYSCLK D6 Input BVSEL TA N8 Low Input BVSEL TBEN L3 High Input BVSEL TBST B7 Low Output BVSEL TCK J7 High Input BVSEL TDI E4 High Input BVSEL TDO H1 High Output BVSEL TEA T1 Low Input BVSEL 39 5345D HIREL 07 0
18. a stable Vpp and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence Figure 7 1 provides the SYSCLK input timing diagram Figure 7 1 SYSCLK Input Timing Diagram SYSCLK VM Midpoint Voltage OVpp 2 tSYSCLK AMEL 21 AMEL 7 2 2 Processor Bus AC Specifications Table 7 3 provides the processor bus AC timing specifications for the PC7457 as defined in Fig ure 7 10 on page 33 and Figure 7 2 on page 23 Timing specifications for the L3 bus are provided in section L3 Clock AC Specifications on page 24 Table 7 3 Processor Bus AC Timing Specifications at Recommended Operating Conditions see page 12 All Speed Grades Min Symbol Parameter Von 51 10 Von 1 3V Input setup times tuki A 0 35 AP 0 4 2 0 1 8 ta D 0 63 DP 0 7 2 0 1 8 tives AACK ARTRY BG CKSTP_IN DBG DTI 0 3 GBL 2 0 1 8 TT 0 3 QACK TA TBEN TEA TS EXT_QUAL PMON_IN SHD 0 1 tuven BMODE 0 1 BMODE 0 1 BVSEL L3VSEL Input hold times tac A 0 35 AP 0 4 tox D 0 63 DP 0 7 tixkH AACK ARTRY BG CKSTP_IN DBG DTI 0 3 GBL TT 0 3 QACK TA TBEN TEA TS EXT_QUAL PMON_IN SHD 0 1 tius BMODE 0 1 BMODE 0 1 BVSEL L3VSEL Output valid time
19. as specified in Recommended Operating Conditions on page 12 AMEL 2 Figure 7 4 13 CLK_OUT Output Timing Diagram tL3_CLK tL3CcR tL3CF tCHCL L3_CLKO VM VM VM y L3_CLK1 VM VM VM VM tL3cSKW1 For PB2 or Late Write L3_ECHO_CLK1 T VM VM VM VM tLacskw2 L3_ECHO_CLK3 VM VM VM VM ir tlacskw2 7 2 4 L3 Bus AC Specifications The PC7457 L3 interface supports three different types of SRAM source synchronous double data rate DDR MSUG2 SRAM Late Write SRAMs and pipeline burst PB2 SRAMs Each requires a different protocol on the L3 interface and a different routing of the L3 clock signals The type of SRAM is programmed in L8CR 22 23 and the PC7457 then follows the appropriate protocol for that type The designer must connect and route the L3 signals appropriately for each type of SRAM Following are some observations about the L3 interface e The routing for the point to point signals L3_CLK 0 1 L3DATA 0 63 L3DP 0 7 and L3_ECHO_CLK 0 3 to a particular SRAM must be delay matched e For 1M byte of SRAM use L3_ADDR 16 0 L3_ADDRI 0 is LSB e For 2M bytes of SRAM use L3_ADDR 17 0 L3_ADDR 0 is LSB No pull up resistors are required for the L3 interface e For high speed operations L3 interface address and control signals should be a T with minimal stubs to the two loads data and clock signals should be point to point to their single load Figure 7 5 shows the AC
20. in a system To preserve correct power down operation QACK should be merged via logic so that it also can be driven by the PCI bridge 53450 11 1 07 06 PC7457 Figure 15 3 JTAG Interface Connection Notes 5345D HIREL 07 06 Mm Pon From Target SRESET Board Sources HRESET 5 el 2 Kl H 9 COP Connector Physical Pin Out Se ke o OD I a Q Sak ol i I 10k L RUN STOP normally found on pin 5 of the COP header is not implemented on the PC7457 Connect pin 5 of the COP header to OVpp with a 10 kQ pull up resistor Key location pin 14 is not physically present on the COP header Component not populated Populate only if debug tool does not drive QACK Populate only if debug tool uses an open drain type output and does not actively deassert QACK If the JTAG interface is implemented connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part If the JTAG interface is not implemented connect HRESET from the target source to TRST of the part through a OQ isolation resistor Though defined as a No Connect it is a common and recommended practice to use pin 12 as an additional GND pin for improved signal integrity AMEL 5 AMEL 16 Definitions 16 1 Life Support Applications These products are not designed for use in life support appliances devices or systems where malfunction of these products can r
21. including during power on reset 10 Vin may overshoot undershoot to a voltage and for a maximum duration as shown in Figure 6 1 AMEL 1 5345D HIREL 07 06 AMEL 6 1 3 Recommended Operating Conditions Recommended Value Symbol Characteristic Min Max Unit Voo Core supply voltage 1 3V 50 mV or 1 1V 50 mV PLL supply voltage 1 3V 50 mV or 1 1V 50 mV V OVep BVSEL 0 1 8V 5 V Processor bus supply voltage OVpp BVSEL HRESET or OVpp 2 5V 5 V GVpp L3VSEL 0 1 8V 5 V GVpp L3 bus supply voltage L3VSEL HRESET or GVpp 2 5V 5 V GVpp L3VSEL HRESET 1 5V 5 V Vin Processor bus GND OVpp V Vin Input voltage L3 bus GND GVpp V Vin JTAG signals GND OVpp V Ty Die junction temperature 55 125 90 Notes 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed 2 This voltage is the input to the filter discussed in Section PLL Power Supply Filtering on page 50 and not necessarily the voltage at the AVpp pin which may be reduced from Vpp by the filter 3 HRESET is the inverse of HRESET Figure 6 1 Overshoot Undershoot Voltage OVpp GVpp 20 OVpp GVpp 5 OVpp GVpp VIH VIL GND 1 GND 0 3V GND 0 7V Lk Notto exceed 10 of tsyscLk le The PC7457 provides several I O voltages to support both compatib
22. s Thermal Interface TT EE Material Printed Circuit Board Thermal Interface Materials A thermal interface material is recommended at the package lid to heat sink interface to mini mize the thermal contact resistance For those applications where the heat sink is attached by spring clip mechanism Figure 6 3 shows the thermal performance of three thin sheet thermal interface materials silicone graphite oil floroether oil a bare joint and a joint with thermal grease as a function of contact pressure The use of thermal grease significantly reduces the interface thermal resistance That is the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint Often heat sinks are attached to the package by means of a spring clip to holes in the printed circuit board see Figure 15 2 on page 52 Therefore the synthetic grease offers the best ther mal performance considering the low interface pressure and is recommended due to the high power dissipation of the PC7457 Of course the selection of any thermal interface material depends on many factors thermal performance requirements manufacturability service tem perature dielectric properties cost etc AMEL 15 AMEL Figure 6 4 Thermal Performance of Select Thermal Interface Material i i Silicone Sheet 0 006 in ST j H Bare Joint L i i i i O Floroether Oil Sheet 0 007 in O Graphi
23. supports AltiVec LRU and transient instructions Critical double and or quad word forwarding is performed as needed Critical quad word forwarding is used for AltiVec loads and instruction fetches Other accesses use critical double word forwarding e Level 2 L2 cache interface On chip 512 Kbyte eight way set associative unified instruction and data cache Fully pipelined to provide 32 bytes per clock cycle to the L1 caches A total nine cycle load latency for an L1 data cache miss that hits in L2 PLRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis 64 byte two sectored line size Parity support on cache e Level 3 L3 cache interface not implemented on PC7447 Provides critical double word forwarding to the requesting unit Internal L3 cache controller and tags External data SRAMs Support for 1 2 and 4M bytes MB total SRAM space Support for 1 or 2 MB of cache space Cache write back or write through operation programmable on a per page or per block basis 64 byte 1 MB or 128 byte 2 MB sectored line size Private memory capability for half 1 MB minimum or all of the L3 SRAM space for a total of 1 2 or 4 MB of private memory Supports MSUG2 dual data rate DDR synchronous Burst SRAMs PB2 pipelined synchronous Burst SRAMs and pipelined register register Late Write synchronous Burst SRAMs
24. test load for the L3 interface Figure 7 5 AC Test Load for the L3 Interface Output OVpp 2 In general if routing is short delay matched and designed for incident wave reception and min imal reflection there is a high probability that the AC timing of the PC7457 L3 interface will meet the maximum frequency operation of appropriately chosen SRAMs This is despite the pessimis tic guard banded AC specifications see Table 7 6 on page 28 Table 7 7 on page 29 and Table 7 8 on page 31 the limitations of functional testers described in Section L3 Clock AC Specifications on page 24 and the uncertainty of clocks and signals which inevitably make worst case critical path timing analysis pessimistic 26 PC7457 NN 5345D HIREL 07 06 mg DC 457 More specifically certain signals within groups should be delay matched with others in the same group while intergroup routing is less critical Only the address and control signals are common to both SRAMs and additional timing margin is available for these signals The double clocked data signals are grouped with individual clocks as shown in Figure 7 6 on page 30 or Figure 7 8 on page 32 depending on the type of SRAM For example for the MSUG2 DDR SRAM see Figure 7 6 L3DATA 0 31 L3DP 0 3 and L3_CLK 0 form a closely coupled group of outputs from the PC7457 while L3DATA 0 15 L3DP 0 1 and L3_ECHO_CLK 0 form a closely cou pled group of inputs The PC7450 RISC Microprocessor
25. the calcu lation of sample points and thus is specified here 2 This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling edge at the L8CLK n pins 3 This specification is the delay from a rising or falling edge of L8_ECHO_CLK n to data valid and ready to be sampled from the FIFO 7 2 4 1 Effects of L3OHCR Settings on L3 Bus AC Specifications The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register L3OCHR Each field controls the timing for a group of signals The AC timing specifications presented herein represent the AC timing when the register contains the default value of 0x0000_0000 Incrementing a field delays the associated signals increasing the output valid time and hold time of the affected signals In the special case of delaying an L3_CLK signal the net effect is to decrease the output valid and output hold times of all signals being latched relative to that clock signal The amount of delay added is summarized in Table 7 6 on page 28 Note that these set tings affect output timing parameters only and don t impact input timing parameters of the L3 bus in any way AMEL 27 5345D HIREL 07 06 AMEL
26. 00 2324 750 1000 1125 1245 00011 15x 2x 1500 2000 2250 2490 11011 16x 2x 1600 2132 2400 00001 17x 2x Gen 2264 00101 18x 2x Bee 1 2400 00111 20x 2x 2000 01001 21x 2x D Bech 01101 24x 2x Dec Ke 11101 28x 2x Be 00110 PLL bypass PLL off SYSCLK clocks core circuitry directly 11110 PLL off PLL off no core clocking occurs Notes 1 PLL_CFG 0 4 settings not listed are reserved 2 The sample bus to core frequencies shown are for reference only Some PLL configurations may select bus core or VCO frequencies which are not useful not supported or not tested for by the PC7455 See Clock AC Specifications on page 20 for valid SYSCLK core and VCO frequencies 48 PC7457 ee mg PO7457 3 4 15 1 2 L3 Clocks In PLL bypass mode the SYSCLK input signal clocks the internal processor directly and the PLL is disabled However the bus interface unit requires a 2x clock to function Therefore an additional signal EXT_QUAL must be driven at one half the frequency of SYSCLK and offset in phase to meet the required input setup Iw and hold time tx see Table 7 3 on page 22 The result is that the processor bus frequency is one half SYSCLK while the internal processor is clocked at SYSCLK frequency This mode is intended for factory use and emulator tool use only Note The AC timing specifications given in this document do
27. 13 T12 W12 AB12 R12 AA13 AB11 Y12 V11 T11 l R11 W10 T10 W11 V10 R10 U10 AA10 U9 V7 T8 AB4 Y6 DJ0 63 AB7 AA6 Y8 AA7 W8 AB10 AA16 AB16 AB17 Y18 AB18 High VO BVSEL Y16 AA18 W14 R13 W15 AA14 V16 W6 AA12 V6 AB9 AB6 R7 R9 AA9 AB8 W9 DBG V1 Low Input BVSEL DP 0 7 AA2 AB3 AB2 AA8 8 W5 U8 AB5 High UO BVSEL DRDY 76 Low Output BVSEL DTI 0 3 P2 T5 U3 6 High Input BVSEL EXT_QUAL 89 High Input BVSEL GBL M4 Low UO BVSEL A22 B1 B5 B12 B14 B16 B18 B20 C3 C9 C21 D7 D13 15 D17 D19 E2 E5 E21 F10 F12 14 F16 19 G4 G7 G17 G21 H13 H15 H19 H5 J3 J10 J12 J14 J17 J21 K5 K9 11 K13 GND K15 K19 L10 L12 L14 L17 L21 M3 M6 M9 M11 M13 M19 N A N10 N12 N14 N17 N21 P3 P9 P11 P13 P15 P19 R17 R21 T13 T15 T19 T4 T7 T9 U17 U21 V2 V5 V8 V12 V15 V19 W7 W17 W21 Y3 Y9 Y13 Y15 Y20 AA5 AA17 AB1 AB22 B13 B15 B17 B19 B21 D12 D14 D16 D18 D21 E19 F13 F15 GVpp F17 F21 G19 H12 H14 H17 H21 J19 K17 K21 L19 M17 M21 N A N19 P17 P21 R15 R19 T17 T21 U19 V17 V21 W19 Y21 HIT K2 Low Output BVSEL HRESET A3 Low Input BVSEL 38 PC7457 _ _ Sse 5345D HIREL 07 06 mg DC 71 57 Table 8 1 Pinout Listing for the PC7457 483 CBGA and HCTE Packages Continued Signal Name
28. 15 C W AMEL 13 AMEL 6 2 2 Package Thermal Characteristics for HCTE Table 6 3 provides the package thermal characteristics for the PC7457 HCTE Table 6 3 Package Thermal Characteristics for HCTE Package Value Characteristic Symbol PC755 HCTE Unit Junction to bottom of balls 3 9 C W Junction to ambient thermal resistance natural ei convection four layer 2520 board RO wa Kee GIW Junction to board thermal resistance R Jg 7 6 C W Notes 1 Simulation no convection air flow 2 Per JEDEC JESD51 6 with the board horizontal 6 2 3 Internal Package Conduction Resistance For the exposed die packaging technology shown in Table 6 1 on page 13 the intrinsic conduc tion thermal resistance paths are as follows e The die junction to case actually top of die since silicon die is exposed thermal resistance The die junction to ball thermal resistance Figure 15 3 on page 55 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed circuit board Figure 6 2 C4 Package with Heat Sink Mounted to a Printed Circuit Board External Resistance Radiation Convection A Heat Sink gt lt Thermal Interface Material n Die Package Internal Resistance Die Junction lt Package Leads Printed Circuit Board L External Resistance Radiation Convection Note the internal v
29. 22 200 182 166 154 143 133 125 1050 525 420 350 300 263 233 191 191 175 162 150 140 131 11005 550 440 367 314 275 244 200 200 183 169 157 147 138 11505 575 460 383 329 288 256 209 209 192 177 164 153 144 1200 600 480 400 343 300 267 218 218 200 185 171 160 150 1250 638 500 417 357 313 278 227 227 208 192 179 167 156 1300 650 520 433 371 325 289 236 236 217 200 186 173 163 Notes 1 The core and L3 frequencies are for reference only Note that maximum L3 frequency is design dependent Some examples may represent core or L3 frequencies which are not useful not supported or not tested for the PC7457 see L3 Clock AC Specifications on page 24 for valid L8_CLK frequencies and for more information regarding the maximum L3 frequency Not all core frequencies are supported by all speed grades see Table 7 2 on page 20 for minimum and maximum core fre quency specifications 5345D HIREL 07 06 ATMEL 1 15 1 3 AMEL System Bus Clock SYSCLK and Spread Spectrum Sources Spread spectrum clock sources are an increasingly popular way to control electromagnetic inter ference emissions EMI by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements These clock sources intentionally add long term jitter in order to diffuse the EMI spectral content The jitter specification given in Table 7 2 on page 20 considers short term cycle to cycle jitt
30. 5 55645555855 5 5 858 10 0 0 0000 P0 01210 EE 383886 3 S16 6 65555855854 M 8555556656 E EE 6555656856 OOO OO OU ue 616 00 0000 664 ROOD TOTO TOTO Oe 5 46566 885856 8553 681 5 6 NG 1355556545 1018 S TOO OOOUOO VO OO E DO O00 OO OD 00000 WCCO E C S 6 8 Ee KCN NCCES 6858 45588538588 O S 6 EE ge 2 218 O19 6 85858585858 61S 3 9 E Figure 8 2 Side View of the CBGA and HCTE Packages Substrate Assembly Encapsulant 3 PAAR 90290290 29292929 AMEL Pinout of the PC7457 483 CBGA and HCTE Package as Viewed from the Top 37 AMEL Table 8 1 Pinout Listing for the PC7457 483 CBGA and HCTE Packages Signal Name Pin Number Active UO I F Select E10 N4 E8 N5 C8 R2 A7 M2 A6 M1 A10 U2 N2 P8 M8 W4 A 0 35 N6 U6 R5 Y4 P1 P4 R6 M7 N7 AA3 U4 W2 W1 W3 V4 High BVSEL AA1 D10 J4 G10 D9 AACK U1 Low Input BVSEL AP 0 4 L5 L6 J1 H2 G5 High Wo BVSEL ARTRY T2 Low UO BVSEL AVDD B2 Input N A BG R3 Low Input BVSEL BMODEO C6 Low Input BVSEL BMODE1 C4 Low Input BVSEL BR K1 Low Output BVSEL BVSEL O G6 High Input N A cle R1 Low Output BVSEL CKSTP_IN F3 Low Input BVSEL CKSTP_OUT K6 Low Output BVSEL CLK_OUT N1 High Output BVSEL AB15 T14 R14 AB13 V14 U14 AB14 W16 AA11 Y11 U12 W13 Y14 U
31. 6 AMEL AMEL Table 8 1 Pinout Listing for the PC7457 483 CBGA and HCTE Packages Continued Signal Name Pin Number Active 1 0 I F Select TEST 0 5 9 B10 H6 H10 D8 F9 F8 Input BVSEL TEST 6 AQ Input BVSEL TMS K4 High Input BVSEL TRST 16 C1 Low Input BVSEL ER P5 Low Wo BVSEL TSIZ 0 2 L1 H3 D1 High Output BVSEL TT 0 4 F1 F4 K8 A5 E1 High UO BVSEL WII L2 Low Output BVSEL v J9 J11 J13 J15 K10 K12 K14 L9 L11 L13 L15 M10 M12 8 8 N A SR M14 N9 N11 N13 N15 P10 P12 P14 VDD_SENSE 0 1 G11 J8 N A Notes 1 OVpp supplies power to the processor bus JTAG and all control signals except the L3 cache controls L8CTL 0 1 GVpp supplies power to the L3 cache interface L3ADDR 0 17 L3DATA 0 63 L3DP 0 7 L8_ECHO_CLK 0 3 and L3_CLK 0 1 and the L3 control signals L3_CNTL 0 1 and Vp supplies power to the processor core and the PLL after filtering to become AV pp For actual recommended value of Vj or supply voltages see Recommended Operating Conditions on page 12 2 Unused address pins must be pulled down to GND 3 These pins require weak pull up resistors for example 4 7 kQ to maintain the control signals in the negated state after they have been actively negated and released by the PC7457 and other bus masters 4 This signal selects between MPX bus mode asserted and 60x bus mode negated and will be sampled at HRESET going hi
32. Dimensions and Bottom Surface Nomenclature for the PC7457 483 HCTE Package Capacitor Region A1 CORNER Miimeters om mn MAX fas f oes e Los 093 10 2 ES CO FD CO O O O O O 000000000000000 e 1 27 BSC 29550 000000000000000 i 29 BSC Ip 125 A 10 35 amp 00000000000 000000000 O OO OO OO PWOUMNOAICATZ de Se E E O O OO O O O O O
33. Family User s Manual refers to logical settings called sam ple points used in the synchronization of reads from the receive FIFO The computation of the correct value for this setting is system dependent and is described in the PC7450 RISC Micro processor Family User s Manual Three specifications are used in this calculation and are given in Table 7 5 on page 27 It is essential that all three specifications are included in the calculations to determine the sample points as incorrect settings can result in errors and unpredictable behavior For more informa tion see the PC7450 RISC Microprocessor Family User s Manual Table 7 5 Sample Points Calculation Parameters Symbol Parameter Max Unit tac Delay from processor clock to internal_L3_CLK 3 4 13 0 tco Delay from internal_L3_ CLK to L3_CLK n output pins 3 ns teci Delay from L3_ECHO_CLK n to receive latch 3 ns Notes 1 This specification describes a logical offset between the internal clock edge used to launch the L3 address and control signals this clock edge is phase aligned with the processor clock edge and the internal clock edge used to launch the L38_CLK n signals With proper board routing this offset ensures that the L8_CLK n edge will arrive at the SRAM within a valid address window and provide adequate setup and hold time This offset is reflected in the L3 bus interface AC timing specifications but must also be separately accounted for in
34. Features 3000 Dhrystone 2 1 MIPS at 1 3 GHz e Selectable Bus Clock 30 CPU Bus Dividers up to 28x e 13 Selectable Core to L3 Frequency Divisors e Selectable MPx 60x Interface Voltage 1 8V 2 5V Selectable L3 Interface of 1 8V or 2 5V Pp Typical 12 6W at 1 GHz at Von 1 3V 8 3W at 1 GHz at Vpp 1 1V Full Operating Conditions Nap Doze and Sleep Modes for Power Saving Superscalar Four Instructions Fetched Per Clock Cycle 4GB Direct Addressing Range Virtual Memory 4 Hexabytes 257 64 bit Data and 36 bit Address Bus Interface Integrated L1 36 KB Instruction and 32 KB Data Cache Integrated L2 512 KB 11 Independent Execution Units and Three Register Files Write back and Write through Operations e fiyr Max 1 GHz 1 2 GHz to be Confirmed 1 Max 133 MHz 166 MHz Description The PC7457 is implementations of the PowerPC microprocessor family of reduced instruction set computer RISC microprocessors This document describes pertinent electrical and physical characteristics of the PC7457 The PC7457 is the fourth implementation of the fourth generation G4 microproces sors from Freescale The PC7457 implements the full PowerPC 32 bit architecture and is targeted at networking and computing systems applications The PC7457 con sists of a processor core a 512 Kbyte L2 and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface The core is a hig
35. PLL must be followed on exiting the deep sleep state mg DC 71 57 Thermal management facility provides software controllable thermal management Thermal management is performed through the use of three supervisor level registers and a PC7457 specific thermal management exception Instruction cache throttling provides control of instruction fetching to limit power consumption Performance monitor can be used to help debug system designs and improve software efficiency In system testability and debugging features through JTAG boundary scan capability e Testability LSSD scan design IEEE 1149 1 JTAG interface Array built in self test ABIST factory test only e Reliability and serviceability Parity checking on system bus and L3 cache bus Parity checking on the L2 and L3 cache tag arrays ATMEL 5345D HIREL 07 06 AMEL 4 Signal Description Figure 4 1 PC7457 Microprocessor Signal Groups L3_ADDR 17 0 1 L3 DATA 0 63 L3 Cache BR L3_DP 0 7 Address Data Address SE Note L3 cache interface is not supported Arbitration BG L3_VSEL in the PC7441 PC7445 or the PC7447 L3_CLK 0 1 A 0 35 L3_ECHO_CLK 0 3 L3 Cache Address r Clock Control Transfer AP 0 4 L3_CNTL 0 1 TS INT TT 0 4 SMI TBST MCP Address TSIZ 0 2 SRESET Interrupts Resets Transfer Ze o Attributes GBL PC7457 HRESET WT CKSTP_IN Cl CKSTP_OUT TBEN AACK QREQ Address ARTRY QACK Transfer
36. Parity Inputs L3 Data and Data Note VM Midpoint Voltage GVpp 2 Figure 7 10 AC Test Load Output OVpp 2 7 2 6 IEEE 1149 1 AC Timing Specifications Table 7 9 provides the IEEE 1149 1 JTAG AC timing specifications as defined in Figure 7 12 through Figure 7 15 on page 35 Table 7 9 JTAG AC Timing Specifications Independent of SYSCLK at Recommended Operating Conditions see Recommended Operating Conditions on page 12 Symbol Parameter Min Max Unit Lo TCK frequency of operation 0 33 3 MHz Low TCK cycle time 30 ns TCK clock pulse width measured at 1 AN 15 ns Le and tr TCK rise and fall times 0 2 ns trast TRST assert time 25 ns AMEL 3 5345D HIREL 07 06 AMEL Table 7 9 JTAG AC Timing Specifications Independent of SYSCLK at Recommended Operating Conditions see Recommended Operating Conditions on page 12 Continued Symbol Parameter Min Max Unit Input Setup Times tov Boundary scan data 4 ns tivJH TMS TDI 0 Input Hold Times toa Boundary scan data 20 ns nm TMS TDI 25 Valid Times 1 Boundary scan data 4 20 ns tput hold ti S a Ge E olg dee TBD TBD JLDX oundary scan data TBD TBD Luc TDO TCK to output high impedance tips E Boundary scan data 3 19 ns tyLoz TDO 3 9 Notes 1 All outputs are measured from the midpoint voltage of the falling rising edge of TCLK to the midpoint of the sig
37. al operation strong pull up and pull down resistors 1 kQ or less are recommended to configure these signals in order to protect against erroneous switching due to ground bounce power supply noise or noise coupling 52 PC7457 ee 5345D HIREL 07 06 mg DC 4 57 During inactive periods on the bus the address and transfer attributes may not be driven by any master and may therefore float in the high impedance state for relatively long periods of time Because the PC7457 must continually monitor these signals for snooping this float condition may cause excessive power draw by the input receivers on the PC7457 or by other receivers in the system It is recommended that these signals be pulled up through weak 4 7 kQ pull up resistors by the system or that they may be otherwise driven by the system during inactive peri ods of the bus The snooped address and transfer attribute inputs are A 0 35 AP 0 4 TT 0 4 Cl WT and GBL If extended addressing is not used A 0 3 are unused and must be pulled low to GND through weak pull down resistors If the PC7457 is in 60x bus mode DTI 0 3 must be pulled low to GND through weak pull down resistors The data bus input receivers are normally turned off when no read operation is in progress and therefore don t require pull up resistors on the bus Other data bus receivers in the system how ever may require pull ups or that those signals be otherwise driven by the system during inactiv
38. apacitors receive their power from sep arate Vpp OVpo GV po and GND power planes in the PCB utilizing short traces to minimize inductance These capacitors should have a value of 0 01 or 0 1 uF Only ceramic surface mount technology SMT capacitors should be used to minimize lead inductance preferably 0508 or 0603 orienta tions where connections are made along the length of the part Consistent with the recommendations of Dr Howard Johnson in High Speed Digital Design A Handbook of Black Magic Prentice Hall 1993 and contrary to previous recommendations for decoupling Freescale microprocessors multiple small capacitors of equal value are recommended over using multiple values of capacitance In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vpp GVpp and OVpp planes to enable quick recharging of the smaller chip capacitors These bulk capacitors should have a low equivalent series resistance ESR rat ing to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 330 HF AVX TPS tantalum or Sanyo OSCON 15 4 Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropri ate signal level Unused active low inputs should be tied to OVpp Unused active high inputs should be connected to GND Al
39. ata will typically follow the edge of L3_ECHO_CLKn as shown in Figure 7 7 For consistency with other input setup time specifications this will be treated as negative input setup time 4 ts cux 4 is one fourth the period of L3_CLKn This parameter indicates that the PC7457 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling or falling and rising edges of L3_ECHO_CLKn at any frequency 5 All output specifications are measured from the midpoint voltage of the rising or for DDR write data also the falling edge of L3_CLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50Q load see Figure 7 5 on page 26 6 For DDR the output data will typically lead the edge of L8_CLKn as shown in Figure 7 7 on page 30 For consistency with other output valid time specifications this will be treated as negative output valid time 7 ts cux 4 is one fourth the period of L3_CLKn This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90 Therefore there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period starting three fourths of a clock prior to the edge on which the SRAM will sample it and ending one fourth of a clock period after t
40. been designed in the chip to minimize the effect of static buildup However the following handling practices are recommended Devices should be handled on benches with conductive and grounded surfaces Ground test equipment tools and operator Do not handle devices by the leads Store devices in conductive foam or carriers e Avoid use of plastic rubber or silk in MOS areas Maintain relative humidity above 50 if practical Package Parameters for the PC7457 483 CBGA and 483 HCTE The package parameters are as provided in the following list The package type is 29 x 29 mm 483 lead ceramic ball grid array CBGA and HCTE Package outline 29 mm x 29 mm Interconnects 483 22 x 22 ball array 1 Pitch 1 27 mm 50 mil Minimum module height Maximum module height 3 22 mm Ball diameter 0 89 mm 35 mil Coefficient of thermal expansion 6 8 ppm C CBGA 12 3 ppm C HCTE CBGA Figure 8 1 shows the pinout of the PC7457 483 CBGA and HCTE packages as viewed from the top surface Figure 8 2 shows the side profile of the CBGA and HCTE packages to indicate the direction of the top surface view mg DC 4 57 5345D HIREL 07 06 Figure 8 1 Surface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 OD OO OOO EE 1855535856 6 O S 6 6 2 65665855386 BEEN E E E 000000 PER EEN GE EE 2 DEE EE NMHC HONCHO 4 4 83
41. combinations thereof Everywhere You Are and others are registered trade marks or trademarks of Atmel Corporation or its subsidiaries PowerPC is a registered trademarks of IBM Company Other terms and product names may be trademarks of others 5345D HIREL 07 06
42. e periods by the system The data bus signals are D 0 63 and DP 0 7 If address or data parity is not used by the system and the respective parity checking is disabled through HIDO the input receivers for those pins are disabled and those pins don t require pull up resistors and should be left unconnected by the system If all parity generation is disabled through HIDO then all parity checking should also be disabled through HIDO and all parity pins may be left unconnected by the system The L3 interface does not normally require pull up resistors 15 7 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals The TRST signal is optional in the IEEE 1149 1 specification but is provided on all processors that implement the PowerPC architecture While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals more reliable power on reset performance will be obtained if the TRST signal is asserted during power on reset Because the JTAG interface is also used for accessing the common on chip processor COP function simply tying TRST to HRESET is not practical The COP function of these processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor with some additional status moni
43. easonably be expected to result in personal injury Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale 17 Ordering Information XX 7457 y XXX y nnn N x Product Part Temperature Package Screening Max Internal Application Revision Code Identifier Range Ty Level Processor Speed Modifier 1 Level G CBGA M 55 C 125 C 01 7 U Upscreening 933 MHz V 40 C 110 C GHY HiTCE CBGA 1000 MHz ROHS compliant Blank standard N 1 1V 50 mV Notes 1 For availability of the different versions contact your local Atmel sales office 2 The letter X in the part number designates a Prototype product that has not been qualified by Atmel Reliability of a PCX part number is not guaranteed and such part number shall not be used in Flight Hardware Product changes may still occur while shipping prototypes 56 PC7457 NN mg DC 71 57 18 Document Revision History Table 18 1 provides a revision history for this hardware specification Table 18 1 Document Revision History Revision Number Date Substantive Change s D 03 06 Remove PC7447 Modification Table 6 1 on page 13 and ordering information Updated document to new Atmel template Updated section numbering and changed ref
44. echanical Dimensions for the PC7457 483 CBGA 1s ssssccsessseeeseeee 41 Substrate Capacitors for the PC7457 483 CBGA eessen 42 Mechanical Dimensions for the PC7457 483 HCTE s sccsessssesseeee 43 Substrate Capacitors for the PC7457 483 HCTE ssscccccsssscsssssssssesseees 44 Mechanical Dimensions for the PC 7457 483 HCTE ROHS compliant 45 Substrate Capacitors for the PC7457 483 HCTE ROHS Compliant 45 System Design Information sssssssssssssssssnmnnnnnnnnnnnnnnnnnssssssnnssssssss 47 15 1 ESE ST 6 47 15 2 PLL Power Supply Filtering uee eens 50 15 3 Decoupling Recommendations 51 15 4 Connection Recommendations 51 15 5 Output Buffer DC Impedance 51 AMEL AMEL 15 6 Pull up Pull down Resistor Requirements Ee 52 15 7 JTAG Configuration Signals 53 18 06111 E 56 16 1 Life Support Applications 56 17 Ordering 1110 6 sss TSS sles 56 18 Document Revision History 5SSESEERSEEEEEEEEEEEEEEEEEEEEEEREEEEEEEEEEEEEEEE EEN 57 Table Of Contents EE i 5345D HIREL 07 06 AIMEL T 7 Atmel Corporation Atmel Operations 2325 Orchard Parkway Memory RF Automotive San Jose CA 95131 USA 2325 Orchard Parkway Theresienstrasse 2 Tel 1 408 441 0311 San Jose CA 95131 USA Postfach 3535 Fax 1 408 487 2600 Tel 1 408 441 0311 74025 Heilbronn Germa
45. ee stage load store unit LSU Supports integer floating point and vector instruction load store traffic Four entry vector touch queue VTQ supports all four architected AltiVec data stream operations Three cycle GPR and AltiVec load latency byte half word word vector with one cycle throughput Four cycle FPR load latency single double with one cycle throughput No additional delay for misaligned access within double word boundary ATMEL s AMEL Dedicated adder calculates effective addresses EAs Supports store gathering Performs alignment normalization and precision conversion for floating point data Executes cache control and TLB instructions Performs alignment zero padding and sign extension for integer data Supports hits under misses multiple outstanding misses Supports both big and little endian modes including misaligned little endian accesses e Three issue queues FIQ VIQ and GIQ can accept as many as one two and three instructions respectively in a cycle Instruction dispatch requires the following Instructions can be dispatched only from the three lowest IQ entries IQ0 IQ1 and 2 A maximum of three instructions can be dispatched to the issue queues per clock cycle Space must be available in the CQ for an instruction to dispatch this includes instructions that are assigned a space in the CQ but not in an issue queue Rename buffers 16 GPR rename buffers 16
46. er only and the clock generator s cycle to cycle output jitter should meet the PC7457 input cycle to cycle jit ter requirement Frequency modulation and spread are separate concerns and the PC7457 is compatible with spread spectrum sources if the recommendations listed in Table 20 are observed Table 15 3 Spread Specturm Clock Source Recommendations at Recommended Operating Conditions see page 12 Parameter Min Max Unit Notes Frequency modulation 50 kHz ER Frequency spread 1 0 12 Notes 1 Guaranteed by design 2 SYSCLK frequencies resulting from frequency spreading and the resulting core and VCO fre quencies must meet the minimum and maximum specifications given in Table 7 2 on page 20 It is imperative to note that the processor s minimum and maximum SYSCLK core and VCO frequencies must not be exceeded regardless of the type of clock source Therefore systems in which the processor is operated at its maximum rated core or bus frequency should avoid violat ing the stated limits by using down spreading only 15 2 PLL Power Supply Filtering 50 PC7457 The AVpp power signal is provided on the PC7457 to provide power to the clock generation PLL To ensure stability of the internal clock the power supplied to the AVpp input signal should be fil tered of any noise in the 500_kHz to 10 MHz resonant frequency range of the PLL A circuit similar to the one shown in Figure 9 1 using surface moun
47. erence from part number specifications to addendums Added Rev 1 2 devices including increased L3 clock max frequency to 250 MHz and improved L3 AC timing Table 6 2 on page 13 Added CTE information Table 7 2 on page 20 Modified jitter specifications to conform to JEDEC standards changed jitter specification to cycle to cycle jitter instead of long and short term jitter changed jitter bandwidth recommendations Table 7 7 on page 29 Deleted note 9 and renumbered Table 7 8 on page 31 Deleted note 5 and renumbered Table 8 1 Revi t c 06 2005 able 8 1 on page 38 Revised note 6 Added Section 15 1 3 System Bus Clock SYSCLK and Spread Spectrum Sources on page 50 Section 15 2 PLL Power Supply Filtering on page 50 Changed filter resistor recommendations Recommend 102 resistor for all production devices including production Rev 1 1 devices 400Q resistor needed only for early Rev 1 1 devices Table 18 1 Reversed the order of revision numbers Section 15 1 1 on page 47 Corrected note regarding different PLL configurations for earlier devices all PC7457 devices to date conform to this table Section 15 6 on page 52 Added information about unused L3_ADDR signals HCTE package information Preliminary specification o site release subsequent to preliminary specification B site Motorola changed to Freescale Figure 7 3 on page 22 Corrected pin lists for input and output AC timing to correctly show HIT as an output only signal B 11 2004
48. ersus external package resistance Heat generated on the active side of the chip is conducted through the silicon then through the heat sink attach material or thermal interface material and finally to the heat sink where it is removed by forced air convection Because the silicon thermal resistance is quite small for a first order analysis the temperature drop in the silicon may be neglected Thus the thermal interface material and the heat sink con duction convective thermal resistances are the dominant terms 14 PC7457 ee 5345D HIREL 07 06 mg DC 71 57 6 2 4 6 2 5 5345D HIREL 07 06 Thermal Management Information This section provides thermal management information for the ceramic ball grid array CBGA package for air cooled applications Proper thermal control design is primarily dependent on the system level design the heat sink airflow and thermal interface material To reduce the die junction temperature heat sinks may be attached to the package by several methods spring clip to holes in the printed circuit board or package and mounting clip and screw assembly see Figure 15 2 on page 52 however due to the potential large mass of the heat sink attachment through the printed circuit board is suggested If a spring clip is used the spring force should not exceed 10 pounds Figure 6 3 Package Exploded Cross sectional View with Several Heat Sink Options Heat Sink CBGA Package Heat Sink Clip
49. g conditions This section summarizes features of the PC7457 implementation of the PowerPC architecture Major features of the PC7457 are as follows High performance superscalar microprocessor As many as 4 instructions can be fetched from the instruction cache at a time As many as 3 instructions can be dispatched to the issue queues at a time As many as 12 instructions can be in the instruction queue IQ As many as 16 instructions can be at some stage of execution simultaneously Single cycle execution for most instructions One instruction per clock cycle throughput for most instructions Seven stage pipeline control Eleven independent execution units and three register files Branch processing unit BPU features static and dynamic branch prediction 128 entry 32 set four way set associative branch target instruction cache BTIC a cache of branch instructions that have been encountered in branch loop code sequences If a target instruction is in the BTIC it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache Typically a fetch that hits the BTIC provides the first four instructions in the target stream 2048 entry branch history table BHT with two bits per entry for four levels of prediction not taken strongly not taken taken and strongly taken Up to three outstanding speculative branches Branch instructions that don
50. gh 5 This signal must be negated during reset by pull up to OVpp or negation by HRESET inverse of HRESET to ensure proper operation 6 See Table 6 1 on page 13 for bus voltage configuration information If used pull down resistors should be less than 250Q 7 Internal pull up on die 8 Ignored in 60x bus mode 9 These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode 10 These input signals for factory use only and must be pulled down to GND for normal machine operation 11 Power must be supplied to GVpp even when the L3 interface is disabled or unused 12 It is recommended that this test signal be tied to HRESET however other configurations will not adversely affect performance 13 These input signals are for factory use only and must be pulled up to OVpp for normal machine operation 14 These signals are for factory use only and must be left unconnected for normal machine operation 15 This pin can externally cause a performance monitor event Counting of the event is enabled via software 16 This signal must be asserted during reset by pull down to GND or assertion by HRESET to ensure proper operation 17 These pins are internally connected to Vpp They are intended to allow an external device to detect the core voltage level present at the processor core If unused they must be connected directly to Vpp or left unconnected 40 PC7457 REENEN 5345D HIREL 07 06 mg DC 71 57 9 Mechanical Dime
51. guration shown in Figure 7 8 assuming the timing relationships of Figure 7 9 and the loading of Figure 7 5 on page 26 Table 7 8 L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Conditions see page 12 All Speed Grades Symbol Parameter Min Max Unit traces liner L3_CLK rise and fall time 0 75 ns 3 Setup times Data and parity 3 0 1 ns tL3DXEH Input hold times Data and parity 0 7 ns tiscupy Valid times Data and parity 2 2 5 ns tiscHov Valid times All other outputs 1 8 ns tL3cHDX Output hold times Data and parity 1 4 ns tlacuox Output hold times All other outputs 1 0 ns Kaemgs L3_CLK to high impedance Data and parity 3 0 ns 130102 L3_CLK to high impedance All other outputs 3 0 ns Notes 1 Rise and fall times for the L3_CLK output are measured from 20 to 80 of GVpp 2 Timing behavior and characterization are currently being evaluated 3 All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L8_ECHO_CLKn see Figure 7 7 on page 30 Input timings are measured at the pins 4 All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50Q load
52. h performance superscalar design supporting a double precision floating point unit and a SIMD multimedia unit The memory storage subsystem sup ports the MPX bus interface to main memory and other system resources The L3 interface supports 1 2 or 4M bytes of external SRAM for L3 cache and or private memory data For systems implementing 4M bytes of SRAM a maximum of 2M bytes may be used as cache the remaining 2M bytes must be private memory Note that the PC7457 is a footprint compatible drop in replacement in a PC7455 application if the core power supply is 1 3V AMEL T 7 PowerPC 7457 RISC Microprocessor PC7457 Rev 5345D HIREL 07 06 AMEL Screening CBGA Upscreenings Based on Atmel Standards e Full Military Temperature Range 55 C 125 0 Industrial Temperature Range T 40 C 411050 HCTE Package for the 7457 G suffix CBGA 483 Ceramic Ball Grid Array GH suffix HITCE 483 Ceramic Ball Grid Array PC7457 Microprocessor Block Diagram Block Diagram Figure 1 1 1 mg DC 71 57 usnd 8 10 ajqeyiene aq Wu Aue 007909 990109 6 0 Dou 911 99 97970 1701980 UL SOLUS 0 JO 810 090 0000 8 10 UNS 9590170991 91909 97970 Ysnd pue 9790 170198 au 2 sng e isi aaea sng sse ppy 691 0 10 Z S t 99124 90 UO pajuaw ajdu jou S 908 91 1 9080 7 SUL 19910 6 79 16 96 WHS leux Awed 118 8 Joyeinunooy sng IO Ing L 3 EEL cuonuaneyul Il DH ysng doous
53. he edge it will be sampled AMEL 2 5345D HIREL 07 06 AMEL 8 Assumes default value of L3OHCR See Effects of L3OHCR Settings on L3 Bus AC Specifications on page 27 for more information 9 L3 I O voltage mode must be configured by L3VSEL as described in Table 6 1 on page 13 and voltage supplied at GVpp must match mode selected as specified in Recommended Operating Conditions on page 12 Figure 7 6 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs Figure 7 6 Typical Source Synchronous 4M bytes L3 Cache DDR Interface L3ADDR 18 0 SRAM 0 PC7457 4 SA 18 0 L3_CNTL 0 S hi L3_CNTL 1 5 Denotes L3_ECHO_CLK 0 Receive SRAM CQ to PC7457 L3DATA 0 15 L3DP 0 1 Aligned Signals L3_CLK 0 L3DATA 16 31 L3DP 2 3 L3_ECHO_CLK 1 Denotes Transmit PC7457 to SRAM Aligned Signals SRAM 1 SA 18 0 81 82 CO L3ECHO_CLK 2 L3DATA 32 47 L3DP 4 5 D 0 17 L3_CLK 1 we L3DATA 48 63 L3DP 6 7 D 18 35 L3_ECHO_CLK 3 CO Note 1 Oras recommended by SRAM manufacturer for single ended clocking Figure 7 7 shows the L3 bus timing diagrams for the PC7457 interfaced to MSUG2 SRAMs Figure 7 7 L3 Bus Timing Diagrams for L3 Cache DDR SRAMs Outputs L3_CLK 0 1 VM k tL3CHOZ gt L3CHOX ADDR 13017 lt tL3CLDV tL8CHDV gt le gt tL3CLDZ L3DATA WRITE tL3CHDX gt ee
54. ility with existing systems and migration to future systems The PC7457 core voltage must always be provided at nominal 1 3V see Recommended Operating Conditions on page 12 for actual recommended core voltage Voltage to the L3 I Os and processor interface I Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 6 1 The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the nega tion of the signal HRESET The output voltage will swing from GND to the maximum voltage applied to the OVpp or GVpp power pins 12 PC7457 ie 5345D HIREL 07 06 mg DC 4 57 Table 6 1 Input Threshold Voltage Setting BVSEL Processor Bus Input L3VSEL L3 Bus Input Threshold is Signal Threshold is Relative to Signal Relative to Notes 0 1 8 0 1 8V 23 HRESET Not available HRESET 1 5V 2 4 HRESET 2 5V HRESET 2 5V 1 2 5V 1 2 5V 2 Notes 1 Notimplemented on PC7447 2 Caution The input threshold selection must agree with the OVpp GVpp voltages supplied See notes in Absolute Maximum Ratings on page 11 3 If used pull down resistors should be less than 25042 4 Applicable to L3 bus interface only HRESET is the inverse of HRESET 6 2 Thermal Characteristics 6 2 1 Package Characteristics Table 6 2 Package Thermal Characteristics Value PC7447 PC7457 Symb
55. in Figure 7 7 and the loading shown in Figure 7 5 on page 26 Table 7 7 L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions see page 12 All Speed Grades Symbol Parameter Min Min Max Max Unit 1308 tiscr L3_CLK rise and fall time 0 75 0 75 ns i t 14 t 14 13 tLaoveL Setup times Data and parity 1 070 ns p 8 t 4 t 4 13 80 Happ Input hold times Data and parity 2 Ce iea ns La 4 rh tiscupv 130 00 Valid times Data and parity 050 ns id times 5 7 8 1 304 4 8 tiscuk 4 tLscHov Valid times All other outputs 0 65 0 65 ns 130106 30 04 Output hold times Data and 08110 5 6 7 8 13 4 1 4 ns 0 60 0 50 1 44 1 44 13010 Output hold times All other outputs 050 050 ns Ge 8 4 8 1 4 130 02 L3_CLK to high impedance Data and parity 0 60 0 60 ns KEEN 8 130 04 8 130 14 10102 L3_CLK to high impedance All other outputs 0 65 0 65 ns Notes 1 Rise and fall times for the L3_CLK output are measured from 20 to 80 of GVpp 2 For DDR all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris ing or falling edge of the input L8_ECHO_CLKn see Figure 7 7 on page 30 Input timings are measured at the pins 3 For DDR the input d
56. ise within the electronic cabinet An electronic cabinet inlet air temperature T may range from 30 to 40 C The air temperature rise within a cabinet T may be in the range of 5 to 10 C The thermal resistance of the thermal interface material Ri is typically about 1 5 C W For example assuming a Ta of 30 C a Tr of 5 C a CBGA package Rg jo 0 1 and a typical power consumption P4 of 18 7W the following expression for T is obtained Die junction temperature Tj 30 C 5 C 0 1 C W 1 5 C W Osa x 18 7W 16 PC7457 ee 5345D HIREL 07 06 mg DC 4 57 5345D HIREL 07 06 For this example a Rk value of 2 15 C W or less is required to maintain the die junction temper ature below the maximum value of Recommended Operating Conditions on page 12 Though the die junction to ambient and the heat sink to ambient thermal resistances are a com mon figure of merit used for comparing the thermal performance of various microelectronic packaging technologies one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three dimensional heat flow The final die junction operating temperature is not only a function of the component level thermal resistance but the system level design and its operating conditions In addition to the component s power consumption a number of factors affect the final operating die junction temperat
57. l NC no connect signals must remain unconnected Power and ground connections must be made to all external Von OVpp GVpp and GND pins in the 7457 If the L3 interface is not used GVpp should be connected to the OVpp power plane and L3VSEL should be connected to BVSEL the remainder of the L3 interface may be left unterminated 15 5 Output Buffer DC Impedance The PC7457 processor bus and L3 I O drivers are characterized over process voltage and temperature To measure ZO an external resistor is connected from the chip pad to OVpp or GND Then the value of each resistor is varied until the pad voltage is OVpp 2 see Figure 10 1 on page 42 The output impedance is the average of two components the resistances of the pull up and pull down devices When data is held low SW2 is closed SW1 is open and RN is trimmed until the voltage at the pad equals OVpp 2 RN then becomes the resistance of the pull down devices When data is held high SW1 is closed SW2 is open and RP is trimmed until the voltage at the pad equals OVpp 2 RP then becomes the resistance of the pull up devices RP and RN are designed to be close to each other in value Then ZO RP RN 2 AMEL s 5345D HIREL 07 06 AMEL Figure 15 2 Driver Impedance Measurement RN SW2 Pad e Data GJ SW1 RP OGND Table 15 4 summarizes the signal impedance results The impedance increases with junction temperature and is relatively unaffected b
58. ltiple store misses to the same line Only coherency action taken address only for store misses merged to all 32 bytes of a cache block no data tenure needed Three entry finished store queue and five entry completed store queue between the LSU and the L1 data cache Separate additional queues for efficient buffering of outbound data such as castouts and write through stores from the L1 data cache and L2 cache Multiprocessing support features include the following Hardware enforced MESI cache coherency protocols for data cache Load store with reservation instruction pair for atomic memory references semaphores and other multiprocessor operations e Power and thermal management 1 6V processor core The following three power saving modes are available to the system Nap Instruction fetching is halted Only those clocks for the time base decrementer and JTAG logic remain running The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ QACK processor system handshake protocol Sleep Power consumption is further reduced by disabling bus snooping leaving only the PLL in a locked and running state All internal functional units are disabled Deep sleep When the part is in the sleep state the system can disable the PLL The system can then disable the SYSCLK source for greater system power savings Power on reset procedures for restarting and relocking the
59. maximum operating junction temperature see Recommended Operating Conditions on page 12 while running an entirely cache resident contrived sequence of instructions which keep all the execution units maximally busy 4 Doze mode is not a user definable state it is an intermediate state between full power and either nap or sleep mode As a result power consumption for this mode is not tested 7 Electrical Characteristics 7 1 Static Characteristics Table 7 1 provides the DC electrical characteristics for the PC7457 Table 7 1 DC Electrical Specifications see Recommended Operating Conditions on page 12 Nominal Bus Symbol Characteristic Voltage Min Max Unit Vh 1 5 GVpp x 0 65 GVpp 0 3 V Vin Input high voltage all inputs including SYSCLK 1 8 OVpp GVpp x 0 65 OVpp GVpp 0 3 V Vin 2 5 1 7 OVpp GVpp 0 3 V VS 1 5 0 3 GV pp x 0 35 V Vu Input low voltage all inputs including SYSCLK 1 8 0 3 OV p5p GVpp x 0 35 V VL 2 5 0 3 0 7 V 23 Input leakage current Vin GVpp OVpp 30 HA rei ASN High impedance off state 8 8 30 UA Leakage current Vin GVpp OVpp Von 1 5 OVpp GV pp 0 45 V Vou Output high voltage lop 5 mA 1 8 OVpp GVpp 0 45 V Von 2 5 1 8 V Vo 1 5 0 45 V VoL Output low voltage Io 5 mA 1 8 0 45 V VoL 2 5 0 6 V 6 Capacitance L3 interface 7 9 5 pF Vin OV f 1 MHz All o
60. nal in ques a Pon 34 tion The output timings are measured at the pins All output timings assume a purely resistive 50Q load see Figure 7 11 Time of flight delays must be added for trace lengths vias and connectors in the system TRST is an asynchronous level sensitive signal The setup time is for test purposes only Non JTAG signal input timing with respect to TCK Non JTAG signal output timing with respect to TCK Guaranteed by design and characterization Figure 7 11 provides the AC test load for TDO and the boundary scan outputs of the PC7457 Figure 7 11 Alternate AC Test Load for the JTAG Interface Output OVpp 2 Note VM Midpoint Voltage OVpp 2 mg DC 71 57 Figure 7 13 TRST Timing Diagram VM TRST vM 1 trrst Note VM Midpoint Voltage OVpp 2 Figure 7 14 Boundary scan Timing Diagram TCK Boundary Data Inputs Boundary tput Data Valid Data Outputs Output Data Vali Boundary Data Outputs Output Data Valid Note VM Midpoint Voltage OVpp 2 Figure 7 15 Test Access Port Timing Diagram TCK a EEN TDO Output Data Valid TDO Output Data Valid Note VM Midpoint Voltage OVpp 2 AMEL 5 5345D HIREL 07 06 8 1 8 2 36 AMEL Preparation for Delivery Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge Input protection devices have
61. not apply in PLL bypass mode In PLL off mode no clocking occurs inside the PC7455 regardless of the SYSCLK input The PC7457 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock frequency of the PC7457 The core to L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits of the L8CR register Generally the divisor must be chosen according to the frequency supported by the external RAMs the frequency of the PC7457 core and timing analysis of the circuit board routing Table 15 2 shows various example L3 clock frequencies that can be obtained for a given set of core frequencies Table 15 2 Sample Core to L3 Frequencies Core Frequency MHz 2 2 5 3 3 5 4 4 5 5 5 5 6 6 5 7 7 5 8 500 250 200 167 143 125 111 100 91 83 77 71 67 63 533 266 213 178 152 133 118 107 97 89 82 76 71 67 550 275 220 183 157 138 122 110 100 92 85 79 73 69 600 300 240 200 171 150 133 120 109 100 92 86 80 75 650 325 260 217 186 163 144 130 118 108 100 93 87 81 666 333 266 222 190 167 148 133 121 111 102 95 89 83 700 350 280 233 200 175 156 140 127 117 108 100 93 88 733 367 293 244 209 183 163 147 133 122 113 105 98 92 800 400 320 266 230 200 178 160 145 133 123 114 107 100 866 433 347 289 248 217 192 173 157 145 133 124 115 108 933 467 373 311 266 233 207 187 170 156 144 133 124 117 1000 500 400 333 285 250 2
62. nput signals I reach the valid state V relative to the SYSCLK reference K going to the high H state or input setup time And toy symbolizes the time from SYSCLK K going high H until outputs O are valid V or output valid time Input hold time can be read as the time that the input signal 1 went invalid X with respect to the rising clock edge KH note the position of the reference and its state for inputs and output hold time can be read as the time from the rising edge KH until the output went invalid OX 3 tevscux is the period of the external clock SYSCLK in ns The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in ns of the parameter in question 4 According to the bus protocol TS is driven only by the currently active bus master It is asserted low then precharged high before returning to high impedance as shown in Figure 7 3 on page 24 The nominal precharge width for TS is 0 5 x that is less than the minimum tsysc x period to ensure that another master asserting TS on the following clock will not con tend with the precharge Output valid and output hold timing is tested for the signal asserted Output valid time is tested for precharge The high impedance behavior is guaranteed by design 5 Guaranteed by design and not tested 6 According to the bus protocol ARTRY can be driven by multiple bus masters through the clock period immediately foll
63. ns tkr te SYSCLK rise and fall time 1 1 1 1 ns 20 PC7457 NN 5345D HIREL 07 06 mg DC 71 57 Maximum Processor Core Frequency 867 MHz 1000 MHz 1200 MHz 1267 MHz Voo 1 3V Voo 1 3V Vbo 1 3V Voo 1 3V Symbol Characteristic Min Max Min Max Min Max Min Max Unit el 4 SYSCLK duty cycle measured at OVpp 2 40 60 40 60 40 60 40 60 SYSCLK SYSCLK jitter 150 150 150 150 ps Internal PLL relock time 100 100 100 100 us Notes 1 Caution The SYSCLK frequency and PLL_CFG 0 4 settings must be chosen such that the resulting SYSCLK bus fre quency CPU core frequency and PLL VCO frequency don t exceed their respective maximum or minimum operating frequencies Refer to the PLL_CFG 0 4 signal description in Core Clocks and PLL Configuration on page 47 for valid PLL_CFG 0 4 settings 2 Assumes lightly loaded single processor system 3 Rise and fall times for the SYSCLK input measured from 0 4V to 1 4V 4 Timing is guaranteed by design and characterization 5 This represents total input jitter short term and long term combined and is guaranteed by design 6 The SYSCLK driver s closed loop jitter bandwidth should be less than 1 5 MHz at 3 dB 7 5345D HIREL 07 06 Relock timing is guaranteed by design and characterization PLL relock time is the maximum amount of time required for PLL lock after
64. nsions for the PC7457 483 CBGA Figure 9 1 provides the mechanical dimensions and bottom surface nomenclature for the PC7457 483 CBGA package Figure 9 1 Mechanical Dimensions and Bottom Surface Nomenclature for the PC7457 483 CBGA Package A1 CORNER 10 2 O OO O O O O O O O O O O O O O O O O O Q O O
65. ny Fax 1 408 436 4314 Tel 49 71 31 67 0 Fax 49 71 31 67 2340 Regional Headquarters Microcontrollers Bios 2325 Orchard Parkway 1150 East Cheyenne Min Blvd Atmel Sarl San Jose CA 95131 USA Colorado Springs CO 80906 USA Tel 1 408 441 0311 Tel 1 719 576 3300 Route des Arsenaux 41 Fax 1 408 436 4314 Fax 1 719 540 1759 Case Postale 80 CH 1705 Fribourg La Chantrerie Biometrics Imaging Hi Rel MPU Switzerland BP 70602 High Speed Converters RF Datacom Tel 41 26 426 5555 44306 Nantes Cedex 3 France Avenue de Rochepleine EE Tel 33 2 40 18 18 18 BP 123 Asia Fax 33 2 40 18 19 60 38521 Saint Egreve Cedex France Room 1219 Tel 33 4 76 58 30 00 ASIC ASSP Smart Cards Fax 33 4 76 58 34 80 Chinachem Golden Plaza 77 Mody Road Tsimshatsui Zone Industrielle 13106 Rousset Cedex France East Kowloon Tel 33 4 42 53 60 00 Hong Kong Fax 33 4 42 53 60 01 Tel 852 2721 9778 Fax 852 2722 1369 1150 East Cheyenne Min Blvd Japan Colorado Springs CO 80906 USA P Tel 1 719 576 3300 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Fax 1 719 540 1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license e
66. ol Characteristic CBGA CBGA Unit Roya Junction to ambient thermal resistance natural convection 22 20 C W Roya Junction to ambient thermal resistance natural convection four layer 2s2p board 14 14 C W Rosma Junction to ambient thermal resistance 200 ft min airflow single layer 1s board 16 15 C W Rena Junction to ambient thermal resistance 200 ft min airflow four layer 2s2p board 11 11 C W Ross Junction to board thermal resistance 6 6 C W Rose Junction to case thermal resistance lt 0 1 lt 0 1 C W Coefficient of thermal expansion 6 8 6 8 ppm C Notes 1 See Thermal Management Information on page 15 for more details about thermal management 5345D HIREL 07 06 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board tempera ture ambient temperature airflow power dissipation of other components on the board and board thermal resistance Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal Per JEDEC JESD51 6 with the board horizontal Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the calculated case temperature The actual value of Rc for the part is less than 0
67. owing AACK Bus contention is not an issue because any master asserting ARTRY will be driving it low Any master asserting it low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of AACK The nominal precharge width for ARTRY is 1 0 tsysc x that is it should be high imped ance as shown in Figure 7 3 on page 24 before the first opportunity for another master to assert ARTRY Output valid and output hold timing is tested for the signal asserted The high impedance behavior is guaranteed by design 7 According to the MPX bus protocol SHDO and SHD7 can be driven by multiple bus masters beginning the cycle of TS Tim ing is the same as ARTRY that is the signal is high impedance for a fraction of a cycle then negated for up to an entire cycle crossing a bus cycle boundary before being three stated again The nominal precharge width for SHDO and SHD1 is 1 0 The edges of the precharge vary depending on the programmed ratio of core to bus PLL configurations 8 BMODE 0 1 and BVSEL are mode select inputs and are sampled before and after HRESET negation These parameters represent the input setup and hold times for each sample These values are guaranteed by design and not tested These inputs must remain stable after the second sample See Figure 7 2 on page 23 for sample timing Figure 7 2 Mode Input Timing Diagram
68. s A 0 35 AP 0 4 D 0 63 DP 0 7 AACK ARTRY BR Cl CKSTP_IN DRDY DTI 0 3 GBL HIT PMON_OUT QREQ TBST TSIZ 0 2 TT 0 3 TS SHD 0 1 WT tkHav ty DV tkHov Output hold times A 0 35 AP 0 4 D 0 63 DP 0 7 AACK ARTRY BR Cl CKSTP_IN DRDY DTI 0 3 GBL HIT PMON_OUT QREQ TBST TSIZ 0 2 TT 0 3 TS SHD 0 1 WT SYSCLK to output enable ns SYSCLK to output high impedance all except TS ARTRY SHDO SHD1 ns repz 8 SYSCLK to TS high impedance after precharge lari Harp Maximum delay to ARTRY SHDO SHD1 precharge erg 3 5 6 7 _ SYSCLK to ARTRY SHDO SHD1 high impedance after ARRA precharge tsyscLk Notes 1 Allinput specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig nal in question All output timings assume a purely resistive 509 load see Figure 7 10 on page 33 Input and output timings are measured at the pin time of flight delays must be added for trace lengths vias and connectors in the system 22 PC7457 ee mg PO7457 2 The symbology used for timing specifications herein follows the pattern of t ignan state reterence state for inputs and treference state signal state for outputs For example huen symbolizes the time i
69. see Figure 7 7 5 Assumes default value of L3OHCR See Effects of L3OHCR Settings on L3 Bus AC Specifications on page 27 for more information AMEL 1 5345D HIREL 07 06 AMEL Figure 7 8 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs Figure 7 8 Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface PC7457 Denotes Receive SRAM L3_ADDR 16 0 L3_CNTL 0 gt SA 16 0 ss L3_CNTL 1 L3_ECHO_CLKI0 L3_DATA 0 15 L3_DP 0 1 DW to PC7457 Aligned Signals L3_CLK 0 DQ 0 17 GND K GND L38_DATA 16 31 L3_DPI 2 3 gt 18 36 Gvpo 2 1 L3_ECHO_CLK 1 Denotes Transmit SRAM 1 SA 16 0 ss L3_ECHO_CLK 2 Sw PC7457 to SRAM Aligned Signals L3_DATA 32 47 L8_DP 4 5 DQ 0 17 GND L3_CLK 1 K GND L3_DATA 48 63 L3_DP 6 7 DQ 18 36 GVpp 2 1 L3 ECHO OLK Note 1 Oras recommended by SRAM manufacturer for single ended clocking 32 PC7457 NN mg DC 457 Figure 7 9 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs Figure 7 9 L3 Bus Timing Diagrams for Late Write or PB2 SRAMs Outputs L3_CLK 0 1 VM VM L3_ECHO_CLK 1 3 tL3CHOV gt lt gt lt tL3CHOX ADDR L3_CNTL tL8CHDV gt lt gt lt tL3CHDX L3DATA WRITE tL3CHDZ Inputs L3_ECHO_CLK 0 2
70. stem The actual maximum SYSCLK frequency for any application of the PC7457 will be a function of the AC timings of the PC7457 the AC timings for the system controller bus loading printed circuit board topology trace lengths and so forth and may be less than the value given in Table 7 2 Table 7 2 Clock AC Timing Specifications See Recommended Operating Conditions on page 12 Maximum Processor Core Frequency 600 MHz 867 MHz 1000 MHz Voo 51 1 Vpp 1 1V Von 1 1V Symbol Characteristic Min Max Min Max Min Max Unit 1 Processor frequency 500 600 500 867 500 1000 MHz Bee VCO frequency 1000 1200 1000 1733 1000 2000 MHz een GE SYSCLK frequency 33 167 33 167 33 167 MHz leven SYSCLK cycle time 6 30 6 30 6 30 ns tkr tke SYSCLK rise and fall time 1 1 1 ns 14191905 SYSCLK duty cycle measured at OVpp 2 40 60 40 60 SYSCLK jitter 150 150 ps Internal PLL relock time 100 100 us Maximum Processor Core Frequency 867 MHz 1000 MHz 1200 MHz 1267 MHz Von 1 3V Von 1 3V Von 1 3V Von 1 3V Symbol Characteristic Min Max Min Max Min Max Min Max Unit foore Processor frequency 600 867 600 1000 600 1200 600 1267 MHz 1 00 VCO frequency 1200 1733 1200 2000 1200 2400 1200 2534 MHz 12150 SYSCLK frequency 33 167 33 167 33 167 33 167 MHz leven SYSCLK cycle time 6 30 6 30 6 30 6 30
71. stem based on the 0 025 square post 0 100 centered header assembly often called a Berg header The con nector typically has pin 14 removed as a connector key There is no standardized way to number the COP header shown in Figure 15 1 consequently many different pin numbers have been observed from emulator vendors Some are numbered top to bottom then left to right while others use left to right then top to bottom while still others number the pins counter clockwise from pin 1 as with an IC Regardless of the numbering the signal placement recommended in Figure 15 1 is common to all known emulators The QACK signal shown in Figure 15 1 is usually connected to the PCI bridge chip in a system and is an input to the PC7457 informing it that it can go into the quiescent state Under normal operation this occurs during a low power mode selection In order for COP to work the PC7457 must see this signal asserted pulled down While shown on the COP header not all emulator products drive this signal If the product does not a pull down resistor can be populated to assert this signal Additionally some emulator products implement open drain type outputs and can only drive QACK asserted for these tools a pull up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool Note that the pull up and pull down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both
72. synojsed 7 0627 91970 81016 27 0191914 27 99709 8101S 91089008 2 1019 00101 150 Joyeinwnooy sng 01 anano 2 0 6 anand 1 01589 snes 508 snjelg 671916 spej 9790 91019 sng LL enano 1 00 eur 91 6 20 1 5 91 6 20 0 49018 au 990900 O71 anand 0807 7 eo Ge 03108000 9090 7 19011000 90090 21 09610 91 0219 S saw 0807 DH DH DH 28 1910 sng waysis 1916 9079 110010 N 18 82 HUN zuun Hun 19091 19091 9100190 10109 101091 10109 SSI 807 99106 0919 60 Joen ysnd 11 yun 11106 1100 zuun Bunpou slaying slaying 196910 19091 ng weu y 9 ose 0600 weu y 9 weu y OU uonels unge 0018 6 00 8 9 0018 2959 uopenas y all Eve alld Hd 0018 1092 13 00181 2 810189 Id YA 0018 999 00181 9599 00 8 999 i yoojo 9 010 00107 16 1099A 99 0 0 dn 599 60 0018 1959
73. t capacitors with minimum effective series inductance ESL is recommended The circuit should be placed as close as possible to the AVpp pin to minimize noise coupled from nearby circuits It is often possible to route directly from the capacitors to the AVpp pin which is on the periphery of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint without the inductance of vias Figure 15 1 PLL Power Supply Filter Circuit 4000 VDD Mrr AVDD 2 2 uF 2 2 uF l Low ESL surface mount capacitor GND Previous revisions of this document required a 400Q resistor for Rev 1 1 Rev B devices instead of the 10462 resistor shown above All production devices require a 1042 resistor For more information see the PC7450 Family Chip Errata for the PC7457 and PC7447 5345D HIREL 07 06 mg DC 71 57 15 3 Decoupling Recommendations Due to the PC7457 dynamic power management feature large address and data buses and high operating frequencies the PC7457 can generate transient power surges and high fre quency noise in its power supply especially while driving large capacitive loads This noise must be prevented from reaching other components in the PC7457 system and the PC7457 itself requires a clean tightly regulated source of power Therefore it is recommended that the sys tem designer place at least one decoupling capacitor at each Von OVpp and GVpp pin of the PC7457 It is also recommended that these decoupling c
74. te Oil Sheet 0 005 in Synthetic Grease 1 5 SE TiS SE er ad EE Torr fees eee SES ct N 1 au E L i i i i ee i 4 x L i j i i i iea 1 J o i i 1 i 1 i E L 1 1 1 1 1 e EE E 1 1 1 1 4 1 S bs BS E a Gee 1 1 1 N ee Akt e a Ee aa 1 1 1 1 E L Be _ z Oe bp ei 1 E H 5 oO Q 0 0 t t t t t t t 0 10 20 30 40 50 60 70 80 Contact Pressure psi 6 2 5 1 Heat Sink Selection Example For preliminary heat sink sizing the die junction temperature can be expressed as follows Ty T T Rosc Pan Rosa x Pa where T is the die junction temperature T is the inlet cabinet ambient temperature T is the air temperature rise within the computer cabinet Rec is the junction to case thermal resistance Reint is the adhesive or interface material thermal resistance Rosa is the heat sink base to ambient thermal resistance P is the power dissipated by the device During operation the die junction temperatures T should be maintained less than the value specified in Recommended Operating Conditions on page 12 The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature r
75. te and is 0 9 mm thick It can also be modeled as a collapsed volume using orthotropic material properties 0 034W m x K in the xy plane direction and 3 8W m x K in the direction of the z axis ATMEL 17 Figure 6 5 AMEL Recommended Thermal Model of PC7447 and PC7457 Bump and Underfill Solder and Air Side View of Model Not to Scale Bump and Underfill x Substrate Side View of Model Not to Scale Power Consumption Table 6 4 Power Consumption for PC7457 Processor CPU Frequency Full Power Mode 600 MHz 1000 MHz 1000 MHz 1200 MHz Unit Core Power Supply 1 1 1 1 1 3 1 3 Typical 5 3 8 3 15 8 17 5 Ww Maximum 7 9 11 5 22 0 24 2 W Nap Mode Typical 1 3 1 3 5 2 5 2 Ww Sleep Mode Typical 1 2 1 2 EN EN W Deep Sleep Mode PLL Disabled Typical 1 1 1 1 5 0 5 0 W Notes 1 These values apply for all valid processor bus and L3 bus ratios The values do not include I O supply power OVpp and GVpp or PLL supply power AVpp OVpp and GVpp power is system dependent but is typically lt 5 of Vpp power Worst case power consumption for AVpp lt 3 mW 2 Typical power is an average value measured at the nominal recommended VDD see Rec ommended Operating Conditions on page 12 and 65 C while running the Dhrystone 2 1 benchmark and achieving 2 3 Dhrystone MIPs MHz mg DC 4 57 3 Maximum power is the average measured at nominal Vpp and
76. ther inputs 8 0 pF Notes 1 Nominal voltages see Recommended Operating Conditions on page 12 for recommended operating conditions 1 2 For processor bus signals the reference is OVpp while GVpp is the reference for the L3 bus signals 3 Excludes test signals and IEEE 1149 1 boundary scan JTAG signals 4 The leakage is measured for nominal OVpp GVpp and Noe or both OVpp GVpp and Vpp must vary in the same direction for example both OVpp and Von vary by either 5 or 5 5 Capacitance is periodically sampled rather than 100 tested 6 Applicable to L3 bus interface only AMEL 19 5345D HIREL 07 06 AMEL 7 2 Dynamic Characteristics This section provides the AC electrical characteristics for the PC7457 After fabrication func tional parts are sorted by maximum processor core frequency as shown in section Clock AC Specifications and tested for conformance to the AC specifications for that frequency The pro cessor core frequency is determined by the bus SYSCLK frequency and the settings of the PLL_CFG 0 4 signals Parts are sold by maximum processor core frequency See Ordering Information on page 59 7 2 1 Clock AC Specifications Table 7 2 provides the clock AC timing specifications as defined in Figure 7 1 and represents the tested operating frequencies of the devices The maximum system bus frequency Leck given in Table 7 2 is considered a practical maximum in a typical single processor sy
77. toring signals The COP port requires the ability to indepen dently assert HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button switches then the COP reset signals must be merged into these signals with logic The arrangement shown in Figure 15 1 allows the COP port to independently assert HRESET or TRST while ensuring that the target can drive HRESET as well If the JTAG interface and COP header will not be used TRST should be tied to HRESET through a OQ isolation resistor so that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during power on While Freescale recommends that the COP header be designed into the system as shown in Figure 15 1 on page 50 if this is not possible the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations ATMEL s3 5345D HIREL 07 06 54 AMEL The COP header shown in Figure 15 1 adds many benefits breakpoints watchpoints register and memory examination modification and other standard debugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed The COP interface has a standard header for connection to the target sy
78. ure airflow board population local heat flux of adjacent components heat sink effi ciency heat sink attach heat sink placement next level interconnect technology system air temperature rise altitude etc Due to the complexity and the many variations of system level boundary conditions for today s microelectronic equipment the combined effects of the heat transfer mechanisms radiation convection and conduction may vary widely For these reasons we recommend using conju gate heat transfer models for the board as well as system level designs For system thermal modeling the PC7447 and PC7457 thermal model is shown in Figure 6 2 on page 14 Four volumes will be used to represent this device Two of the volumes solder ball and air and substrate are modeled using the package outline size of the package The other two die and bump and underfill have the same size as the die The silicon die should be mod eled 9 64 x 11 x 0 74 mm with the heat source applied as a uniform source at the bottom of the volume The bump and underfill layer is modeled as 9 64 x 11 x 0 69 mm or as a collapsed vol ume with orthotropic material properties 0 6W m x K in the xy plane and 2W m x K in the direction of the z axis The substrate volume is 25 x 25 x 1 2 mm PC7447 or 29 x 29 x 1 2 mm 7457 and this volume has 18W m x 0 isotropic conductivity The solder ball and air layer is modeled with the same horizontal dimensions as the substra
79. will be system dependent See L3 Clock AC Specifica 5345D HIREL 07 06 tions on page 24 for an explanation that this maximum frequency is not functionally tested at speed by Freescale The minimum L3 clock frequency and period are fsyscLk and tsvscLk respectively The nominal duty cycle of the L3 output clocks is 50 measured at midpoint voltage Maximum possible skew between L3_CLKO and L3_CLK1 This parameter is critical to the address and control signals which are common to both SRAM chips in the L3 Maximum possible skew between L3_CLKO and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLKS3 for PB2 or Late Write SRAM This parameter is critical to the read data signals because the processor uses the feedback loop to latch data driven from the SRAM each of which drives data based on L8_CLKO or L3_CLK1 Guaranteed by design and not tested The input jitter on SYSCLK affects L3 output clocks and the L3 address data and control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L3 timing analysis The clock to clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or thermal effects This is also comprehended in the AC timing specifications and need not be considered in the L3 timing analysis L3 WO voltage mode must be configured by L3VSEL as described in Table 6 1 on page 13 and voltage supplied at GVpp must match mode selected
80. ximum in a typical system The maximum L3_CLK frequency for any application of the PC7457 will be a function of the AC timings of the PC7457 the AC timings for the SRAM bus loading and printed circuit board trace length and may be greater or less than the value given in Table 7 4 24 PC7457 ee 5345D HIREL 07 06 mg DC 4 57 Note that SYSCLK input jitter and L8_CLK 0 1 output jitter are already comprehended in the L3 bus AC timing specifications and do not need to be separately accounted for in an L3 AC timing analysis Clock skews where applicable do need to be accounted for in an AC timing analysis Freescale is similarly limited by system constraints and cannot perform tests of the L3 interface on a sock eted part on a functional tester at the maximum frequencies of Table 7 4 Therefore functional operation and AC timing information are tested at core to L3 divisors which result in L3 frequen cies at 250 MHz or lower Table 7 4 L3_CLK Output AC Timing Specifications at Recommended Operating Conditions see page 12 All Speed Grades Symbol Parameter Min Typical Max Min Typical Max Unit fis ck L3 clock frequency 200 250 MHz ts ok L3 clock cycle time 5 4 ns 1010 13 ck L3 clock duty cycle 50 50 Ge 13333373333 Ge om fm fe L3 clock jitter 75 75 ps Notes 1 The maximum L3 clock frequency and minimum L3 clock period
81. xpress or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life 2006 Atmel Corporation All rights reserved Atmel logo and
82. y bus voltage Table 15 4 Impedance Characteristics with Vpp 1 5V OVpp 1 8V 45 Tj 5 85 C Impedance Processor bus Typical Maximum 31 51 32 44 Q 15 6 Pull up Pull down Resistor Requirements The PC7457 requires high resistive weak 4 7 KQ pull up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7457 or other bus masters These pins are TS ARTRY SHDO and SHD1 Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device operation For the PC7447 360 BGA the pins that must be pulled up to OVDD are LSSD_MODE and TEST 0 3 the pins that must be pulled down to GND are L1_TSTCLK and TEST 4 For the PC7457 483 BGA the pins that must be pulled up to OVDD are LSSD_MODE and TEST 0 5 the pins that must be pulled down are L1_TSTCLK and TESTI 6 The CKSTP_IN signal should likewise be pulled up through a pull up resistor weak or stronger 4 7 1 kQ to prevent erroneous assertions of this signal In addition the PC7457 has one open drain style output that requires a pull up resistor weak or stronger 4 7 1 KO if it is used by the system This pin is CKSTP_OUT If pull down resistors are used to configure BVSEL or L3VSEL the resistors should be less than 250Q Because PLL_CFG 0 4 must remain stable during norm

PowerPC 7457 RISC Microprocessor PC7457 - Digi-Key

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