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1. Bit Symbol Description Access Reset Value 7 5 Unused always reads as 0 4 0 PAR_ERR4 Parity Error R 0 3 PAR ERR3 1 Parity Error at the last data transmission 2 PAR_ERR2 0 No error at the last data transmission 1 PAR_ERR1 0 PAR_ERRO Figure 4 4 Parity Error Status Register 4 7 Read Error Status Register The Read Error Status Register is a byte wide read only register The register indicates that a read error was detected at the last data transmission A read error is only issued for channels which operate in Listen only Mode Reasons for a read error are e The number of data bits set in the Control Register does not match the actual data word length e Only a partial transmission was received this can happen when the mode is switched and a transmission is in progress on the observed SSI interface If more data bits are received than expected Read Error will be 1 and the Ready bit will be 0 If less data bits are received than expected Read Error will be 1 and the Ready bit will stay 1 This register is cleared automatically with the IP_RESET signal Bit Symbol Description Access Reset Value 7 5 Unused always reads as 0 4 RD_ERR4 Read Error R 0 3 RD ERR3 1 Datais invalid because of an error during the last transmission 2 RD_ERR2 0 Data OK 1 RD_ERR1 This bit is only valid for channels in L2. 1998 2007 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 18 TEINS S TECHNOLOGIES Issue Description Date 1 0 First Issue May 2004 1 1 Change of Control Register description September 2004 1 2 New address TEWS LLC September 2006 1 3 New Board Revision August 2007 1 4 Amended missing reset register values Read Error clarification November 2007 TIP115 User Manual Issue 1 4 Page 3 of 18 TEWS amp TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION ooccccccscisciceieceinseevececeneinsecnnwewewenereresnnasewawewevenereuetanaeweweweces 6 2 TECHNICAL SPECIFICATION wicscssscsssccscassicncccssatcasesatcnacaseasecsssatscacawaacecdsssadeasadancncsces 7 3 ID PROM CONTENTS viviisisissesiseissstcnsnidsnessiisaaeneucisrarseiuniunabisensieninsnenncsntuaciiaseiusuiaaadei 8 A IP ADDRESSING oo sicie Aaaa EAER 9 GAN UO Re E ue DEE 9 42 C ntr l ROGISUCN E 10 4 3 Data Word LOW Register ccsseseeeceeeeeeeee seen seen neee seen neeeee ee neeeeeegseeeeeegseneeeenseeneeeasenneesasesneneenseenenes 11 4 4 Data Word High Register ccccsccccsseeeeeesseeeeeeneeeeeeenneeneeeenneeeeeegseeeeeegseeeaeenseenaeeasenneneaseeneneeeeeenenes 11 4 5 Ready Status Register ccccccccseccseeeseeeeeseeeeeneeeseeeeeneeeeeeaeeeseeeenseeeeeeeesaeseseeeeeseeesscaesaseeeenseeeeeas 11 4 6 Parity Error Status ReGister ccccscccseeceseeeeeeeee ene e
3. 0x04 DATAHO Data Word High Register Channel 0 16 R 0x06 CONT1 Control Register Channel 1 16 R W 0x08 DATAL1 Data Word Low Register Channel 1 16 R W Ox0A DATAH1 Data Word High Register Channel 1 16 R 0x0C CONT2 Control Register Channel 2 16 R W Ox0E DATAL2 Data Word Low Register Channel 2 16 R W 0x10 DATAH2 Data Word High Register Channel 2 16 R 0x12 CONT3 Control Register Channel 3 16 R W 0x14 DATAL3 Data Word Low Register Channel 3 16 R W 0x16 DATAH3 Data Word High Register Channel 3 16 R 0x18 CONT4 Control Register Channel 4 16 R W Ox1A DATAL4 Data Word Low Register Channel 4 16 R W 0x1C DATAH4 Data Word High Register Channel 4 16 R 0x21 READY Data Ready Status Register 8 R 0x23 PAR_ERR Parity Error Status Register 8 R 0x25 RD_ERR Read Error Status Register 8 R 0x27 INTSTAT Interrupt Status Register 8 R W 0x29 INTENA Interrupt Enable Register 8 R W 0x2B INTVEC Interrupt Vector Register 8 R W 0x2D CONVERT _ Start Convert CHO CH4 Register 8 WwW TIP115 User Manual Issue 1 4 Figure 4 1 TIP115 Register Set Page 9 of 18 TEWS amp TECHNOLOGIES 4 2 Control Register The Control Register is used to program the operation mode clock speed Standard SSI Interface Controller only parity the data encoding of the SSI encoder and the number of data bits coming from the serial absolute encoder Each of the five SSI interfaces can be configured independently of the other by the corresponding Control Register This register is cl
4. SSI Data word length Programmable from 1 bit to 32 bit Interrupts IP interrupt 0 for all 5 SSI channels 2 registers and one Interrupt Vector for individual interrupt handling Interface Connector 50 conductor flat cable Power Requirements 50mA typical 5V DC no load Physical Data Temperature Range Operating 0 C to 70 C Storage 45 C to 125 C MTBF 480000 h Humidity 5 95 non condensing Weight 25g TIP115 User Manual Issue 1 4 Figure 2 1 Technical Specification Page 7 of 18 3 ID PROM Contents TEWS amp TECHNOLOGIES Address Function Contents 0x01 ASCII T 0x49 0x03 ASCII P 0x50 0x05 ASCII A 0x41 0x07 ASCII C 0x43 0x09 Manufacturer ID 0xB3 0x0B Model Number 0x3A 0x0D Revision 0x10 0x0F Reserved 0x00 0x11 Driver ID Low Byte 0x00 0x13 Driver ID High Byte 0x00 0x15 Number of bytes used 0x0D 0x17 CRC 0x77 0x19 Version 10 0x0A TIP115 User Manual Issue 1 4 Figure 3 1 ID PROM Contents Page 8 of 18 4 IP Addressing 4 11 O Addressing The complete register set of the TIP115 is accessible in the I O space of the IP TEWS amp TECHNOLOGIES Address Symbol Description Size Bit Access 0x00 CONTO Control Register Channel 0 16 R W 0x02 DATALO Data Word Low Register Channel 0 16 R W
5. CLKout CH4 CLKIN4 SSI CLKin CH4 24 CLK4 SSI CLKout CH4 ug Donotconnect 25 GND Ground Do not connect Figure 6 1 Pin Assignment I O Connector The pins marked with Do not connect are occupied with active RS422 line driver outputs which are reserved for internal use To avoid contentions leave this pins open TIP115 User Manual Issue 1 4 Page 18 of 18
6. read only register This register indicates that the data transfer between the encoder is completed and the position data can be read When the position data was read the Ready Status Bit is reset to 0 The Ready Status Bit is set after every data transmission even if a parity or a read error was issued Bit Symbol Description Access Reset Value 7 5 Unused always reads as 0 4 RDY4 Ready Bit R 1 3 RDY3 1 Data Ready set after every completed transmission 2 RDY2 In Standard SSI Interface Controller Mode Ready Bit 0 indicates a transmission in progress 1 RDY1 In Listen only Mode the Ready Bit is set to 0 when a 0 RDYO transmission is in progress or the data word was read Figure 4 3 Ready Status Register TIP115 User Manual Issue 1 4 Page 11 of 18 TEWS amp TECHNOLOGIES 4 6 Parity Error Status Register The Parity Error Status Register is a byte wide read only register The register indicates that a parity error is detected at the last data transmission If no parity error is detected at the last data transmission the status register bit is set to 0 During a transmission the parity error bit is not valid The parity error status is updated only if the parity enable bit of the corresponding channel is set to 1 Otherwise the parity status is read as 0 This register is cleared automatically with the IP_RESET signal
7. IEN SZ The Embedded I O Company TECHNOLOGIES TIP115 5 Channel SSI Interface with Listen Only Mode Version 1 0 User Manual Issue 1 4 November 2007 D75115800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com TIP115 10 5 Channel SSI Interface with Listen Only Mode TIP115 User Manual Issue 1 4 TEWS amp TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set
8. bit is set to 1 1 INTENA1 0 Interrupt disabled 0 INTENAO Figure 4 7 Interrupt Enable Register 4 10 Interrupt Vector Register The Interrupt Vector Register is a byte wide read write register It is cleared automatically with the IP_RESET signal Interrupt vector is loaded by software TIP115 User Manual Issue 1 4 Page 13 of 18 TEWS amp TECHNOLOGIES 4 11 Start Convert CHO CH4 Register The Start Convert Register is a byte wide write only register It is used to start the data transmission for all SSI channels simultaneously If the clock rate is set to 0x00 in a Control Register the corresponding SSI channel don t start the data transmission Only channels in SSI Interface Controller Mode will start a transmission TIP115 User Manual Issue 1 4 Page 14 of 18 5 Operation Modes TEWS amp TECHNOLOGIES 5 1 Standard SSI Interface Controller In this mode the channel operates as standard SSI Interface Controller Setup the SSI Interface Controller in the Control Register Set the clock rate the number of data bits and the data word encoding Note that the parity and the zero bit are not included in the data word length A data transfer is initiated through a write to the Data Word Low or the Start Convert Register The SSI Interface Controller will generate a clock burst on which the absolute encoder returns its positional data The SSI Controller receives the positional data performs a Gray cod
9. e to binary conversion when the data word encoding is set to Gray Code and checks if enabled the parity The end of the data transfer is indicated by the Ready bit and if enabled an interrupt will be issued Then the positional data can be read in the Data Word Registers Absolute Encoder TIP115 SSI Interface Controller CLKO 3 CLOCK p bo CLKO 4 CLOCK DATAO D DATA d bh DATAO 2 DATA Pepe Sia et oe a a Deter ie I a i O EEE Figure 5 1 Wiring Example Channel 0 SSI Interface Controller Mode In this mode the Read Error always reads as 0 TIP115 User Manual Issue 1 4 Page 15 of 18 TEWS amp TECHNOLOGIES 5 2 Listen only Mode In Listen only Mode the channel listens to an existing SSI interface to observe its data transfer It takes both the SSI clock and data as inputs Setup the Control Register according to the observed SSI interface Set the number of data bits and the data word encoding Note that the parity and the zero bits are not included in the data word length The Clock rate setting in the Control Register is don t care the Clock rate of the observed SSI interface will be detected automatically A data transfer is initiated by the observed SSI Interface Controller The positional data will be received and a Gray code to binary conversion and a parity check will be performed if enabled The end of the data tra
10. eared automatically with the IP_RESET signal Bit Symbol Description Access Reset Value 15 Unused always reads as 0 14 Mode 1 Listen only Mode R W 0 0 Standard SSI Interface Controller 13 BC5 Number of Data Bits R W 0 12 BC4 Bits are used to program the number of bits of the serial 11 BC3 absolute encoder It can be read and written by software The data bits can be programmed in the range from 1 to 32 10 BC2 BC5 BCO 0x01 to 0x20 means 1 to 32 bit 9 BC1 BC5 BC0 0x00 not used 8 BCO BC5 BC0O 0x21 to 0x3F not used 7 Coding Data word coding R W 0 1 Gray Code The data word is converted into binary code 0 Binary Code 6 Zero Bit Parity Bit with Zero Bit controls the clock cycles R W 0 1 two additional clock cycles 0 one additional clock cycle are provided to get the parity bit 5 Even Controls the parity detection R W 0 Odd 1 odd parity 0 even parity This bit is only useful if bit 4 is set to 1 4 Parity Encoder with parity If encoder provides a parity bit R W 0 1 detect parity errors 3 CR3 Clock Rate for encoder serial clock speed R W 0 2 CR2 The clock can be programmed in steps of 1us in the range of 1 to 15 A value of 0 for the clock rate will stop the operation 1 CRI of the SSI interface 0 CRO The Listen only Mode will ignore the Clock Rate setting in this mode the Clock Rate will be det
11. ected automatically Figure 4 2 Control Register Note that a value of 0x00 for BC5 BCO is not used and will result an invalid SSI Data A value from 0x21 to 0x3F will also result an invalid SSI Data because of the limited 32 bit input shift register of the TIP115 TIP115 User Manual Issue 1 4 Page 10 of 18 TEWS amp TECHNOLOGIES 4 3 Data Word Low Register The serial data of the encoder is shifted into the word wide registers Data Word Low and Data Word High The Data Word Low Register holds the least significant word of the 32 bit shift register In Standard SSI Interface Controller a write access to the Data Word Low Register Channel X initiates a data transfer from the encoder independently of the other channels This register is cleared automatically with the IP_RESET signal The data register may not contain valid data if the serial data transfer is in progress the corresponding ready bit is read as 0 4 4 Data Word High Register The serial data of the encoder is shifted into the word wide registers Data Word Low and Data Word High The Data Word High Register holds the most significant word of the 32 bit shift register This register is cleared automatically with the IP_RESET signal The data register may not contain valid data if the serial data transfer is in progress the corresponding ready bit is read as 0 4 5 Ready Status Register The Ready Status Register is a byte wide
12. ee eeeeeseeeseeeeeaeesaeeseeeseaeesaeesaeesaesaeseaeeeaeeeaeee 6 FIGURE 2 1 TECHNICAL SPECIFICATION AAA 7 FIGURE 3 1 41D PROM CONTENTS ees gereterguergeresgeeseg ees aeaa ae lasati Ad eEdEE geen geegu 8 FIGURE 4 1 TIP115 REGISTER SEI EE 9 FIGURE 4 2 CONTROL REGISTERS is eieupEgte ies ceeddin dae denier eE Ea TETT 10 FIGURE 4 3 READY STATUS REOGIGTER eee cece cece ecee ere cee cee ceeeeaeeeaeseaeseaesseeeseeeseeeeeaeeeaeesneeenaeeaaes 11 FIGURE 4 4 PARITY ERROR STATUS REGISTER AA 12 FIGURE 4 5 READ ERROR STATUS REGISTER cece cene cere eene seer eeeeeeeaeseaeseeeeseeeseeeseaeeeaeesaaeeaaeeaaes 12 FIGURE 4 6 INTERRUPT STATUS REGISTER wiicwiiecsiecineinliv neve viecin edie NN ENEE Ed 13 FIGURE4 7 INTERRUPT ENABLE REGISTER sii tewateieviean cn aaiue e yane ERE AAN a VERE Naa 13 FIGURE 5 1 WIRING EXAMPLE CHANNEL 0 SSI INTERFACE CONTROLLER MODE ee 15 FIGURE 5 2 WIRING EXAMPLE CHANNEL 0 LISTEN ONLY MODE ccc cecceeceeeeeeeeeeeeeseeeeeeneeeaaes 16 FIGURE 5 3 MODE BEHAVIOR DIFFERENCES AAA 17 FIGURE 6 1 PIN ASSIGNMENT WO CONNECTOR AA 18 TIP115 User Manual Issue 1 4 Page 5 of 18 TENSES TECHNOLOGIES 1 Product Description The TIP115 is an IndustryPack compatible module for motion control applications The TIP115 offers five independent channels Each of these channels can be operated as a standard SSI interface controller or in a Listen only Mode The standard SSI interface controller outputs a clock b
13. eseeeeeseeeeseeeeneeeeeeeeeeseaeseaeeeenseeeseeesaseaeseesneeneas 12 4 7 Read Error Status Register cccccssccsseeesseeeeeseeeseeeeeseeeeeseseseaeenseeeeneeeescaesaseeeenseeeseeeseseaeeneeeeeseas 12 4 8 Interrupt Status ReGister cccccccseccsseeeeeseeeseeeeesneeeeseeeeneeseseeeenseeeeeeesesaeseseeeeneneeseueseseeeeenseeeseas 13 4 9 Interrupt Enable Register scccccseseeesseeeeeeneeeeeeenneeeeeeenseeeeeegseeeeeenseeeeeedseeeeeenseenaeeeseeeeeneeseeenes 13 4 10 Interrupt Vector REGIStCM cccceeeeeceseeeeeeeeeeeeeenneee seen neeeee ee neeeeeegseeeeeegseeeeeenseeneeeaseneenseseeeeneenseenenes 13 4 11Start Convert CHO CH4 Register ccsecceceeeceseeeeeeeeeeeeeeeeeeescaeseseeeeeeeeeescaesaseeeeneeeesenesaseaeeaseeeeees 14 5 OPERATION EBEN 15 5 1 Standard SSI Interface Controller cccceeecesceeseeeeeeeeeeeeeee sce seseeeeeeeeeescaeseneeeeneeeeseaesaseaeseeeeenees 15 5 2 Listen only MOde i iscicscccecccscesece tec cice cate cdsned eect cecoccec estes eencueetceis sdaevanwasentuevedes iadaaa iaaa aaae dia daaa 16 5 3 Mode behavior differences cccssccseeeeeseeeeeeeeeseeeeeeeeeeesaeeeseaeenseeeeeeeeesaeseseeeeneeeeseaeseseaeeneeeeeneas 17 6 PIN ASSIGNMENT UO CONNECTOR oo cecccceseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneees 18 TIP115 User Manual Issue 1 4 Page 4 of 18 TEWS amp TECHNOLOGIES Table of Figures FIGURE 1 1 BLOCK DIAGRAM eee eee eee e eee eae ca ae sae eeae s
14. isten only Mode 0 RD_ERRO For channels in SSI Interface Controller Mode this bit will always read 0 Figure 4 5 Read Error Status Register TIP115 User Manual Issue 1 4 Page 12 of 18 4 8 Interrupt Status Register The Interrupt Status Register is a byte wide read write only register TEWS amp TECHNOLOGIES The interrupt status is updated only if the interrupt enable bit of the corresponding channel is set to 1 Otherwise the interrupt status is read as 0 This register is cleared automatically with the IP_RESET signal Bit Symbol Description Access Reset Value 7 5 Unused always reads as 0 4 INTSTAT4 Interrupt Status R W 0 3 INTSTAT3 1 Data Ready Interrupt 2 we a oie t stat ite a 1 to th o quit the interrupt status write a 1 to the 1 INTSTAT1 corresponding bit 0 INTSTATO Figure 4 6 Interrupt Status Register 4 9 Interrupt Enable Register The Interrupt Enable Register is a byte wide read write register The register controls the data ready interrupt of the channel 0 to channel 4 This register is cleared automatically with the IP_RESET signal Bit Symbol Description Access Reset Value 7 5 Unused always reads as 0 4 INTENA4 Interrupt Enable R W 0 3 INTENA3 1 Data Ready Interrupt enabled An interrupt will be issued when a transmission completes S E and the READY status
15. nsfer is indicated by the Ready bit and if enabled an interrupt Then the positional data can be read in the Data Word Registers Reading the Data Word Registers will reset the Ready bit to 0 Absolute Encoder TIP115 Listen Only DATAS 27 lt q DATAS 28 lt lt o DATAO 1 i T Woes acne EE SSI Interface Controller P DATAO 2 T Se EE CLOCK CLOCK DATA DATA Figure 5 2 Wiring Example Channel 0 Listen only Mode In this mode the Clock rate setting in the Control Register is ignored the Clock rate will be detected automatically Writes to the Data Word Low and the Start Convert Register are also ignored for channels in this mode In case of a partial transmission a read error will be issued in the Read Error Status Register To detect read errors the width of the first SSI Clock pulse is measured to detect the clock rate This clock rate is multiplied by 4 and used as initial value for a watchdog timer Every new received bit resets the watchdog timer until either the programmed data word length is reached successful read or a timeout occurs read error In case of a timeout the Read Error bit is set to 1 TIP115 User Manual Issue 1 4 Page 16 of 18 Reasons for a read error are e The number of data bits set in the Control Register does not match the actual size of the transmission e Only a pa
16. rtial transmission was monitored this can happen when the mode is switched and a TEWS amp TECHNOLOGIES transmission is in progress on the observed SSI interface will be issued for the first reading 5 3 Mode behavior differences case of a SSI communication in progress when the mode is switched to Listen only a read error Standard SSI Interface Mode Listen only Mode Control Register Control Register fully used Bit 14 MODE is set to 0 Clock rate setting in Control Register is don t care Bit 14 MODE is set to 1 Ready Register Ready bit 0 during transmission Ready bit 0 during transmission or when the data word was read Read Error Read Error bit is always 0 Read Error bit is set to 1 ona Register erroneous transmission Connections Connect SSI Data with DATA inputs Connect SSI Clock with CLK inputs Connect SSI Data with DATA inputs Connect SSI Clock with CLKIN inputs Data Transfer Start Data transfer is initiated through a write to the Data Word Low or Start Convert Register Data transfer is initiated from external SSI Interface Controller Figure 5 3 Mode behavior differences TIP115 User Manual Issue 1 4 Page 17 of 18 TEWS amp TECHNOLOGIES 6 Pin Assignment I O Connector Pin Signal Comment Pin Signal Comment 6 7 8 23 CLK4 SSI
17. urst to the absolute encoder and receives the returned positional data The SSI interface controller operates with a programmable clock rate from 1us to 15us and programmable data word length from 1 bit to 32 bit In Listen only Mode the channel listens to an existing SSI interface to observe its data transfer It takes both the SSI clock and data as inputs In Listen only Mode the channel also has a programmable data word length from 1 bit to 32 bit the SSI clock rate of the observed SSI interface can be in the range of ius to 15yus In both modes the data word can be encoded in binary or in Gray code and with odd even or no parity The data inputs are galvanically isolated by high speed optocouplers The level of the input and output signals is RS422 5x Standard SSI Interface Listen Only Figure 1 1 Block Diagram TIP115 User Manual Issue 1 4 Page 6 of 18 TEWS amp TECHNOLOGIES 2 Technical Specification IP Interface Interface Single Size IndustryPack Logic Interface compliant to ANSI VITA 4 1995 ID ROM Data Format UO Space Used with no wait states Memory Space Not used Interrupts Only INTREQO is used DMA Not supported Clock Rate 8 MHz Module Type Type SSI Interface 5 independent channels SSI CLK Output Differential driver RS422 SSI Data Input Optically isolated differential input SSI Clock Rate Programmable from 1us to 15us
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