Intel EN80C196KC20 datasheet
Contents
1. d 5 temm Input Series Resistance _ NOTES LSB as used here has a value of approximately 20 mV See Embedded Microcontrollers and Processors Handbook for A D glossary of terms 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz Multiplexer Break Before Make is guaranteed Resistance from device pin through internal MUX to sample capacitor These values may be exceeded if pin current is limited to 2 mA Applying voltages beyond these specifications will degrade the accuracy of all channels being converted All conversions performed with processor in IDLE mode NOOB 20 ntel 8XC196KC 8XC196KC20 EPROM SPECIFICATIONS OPERATING CONDITIONS DURING PROGRAMMING 4 Ambient Temperature During Programming Vcc Programming Voltage 12 25 12 75 EA Pin Voltage 12 25 12 75 Fosc Oscillator Frequency During Auto and Slave MHz Mode Programming Fosc Oscillator Frequency During 16 0 MHz Run Time Programming 8XC196KC Fosc Oscillator Frequency During 20 0 MHz Run Time Programming 8XC196KC20 NOTES 1 Vcc and should nominally be at the same voltage during programming 2 Vpp and Vea must never exceed the maximum specification or the device be damaged 3 Vss and ANGND should nominally be at the same potential OV 4 Load c2. Us f ees 4 oe oem om 16 ntel 8XC196KC 8XC196KC20 EXTERNAL CLOCK DRIVE 8XC196KC20 Oscillator Period Tux mm mew 1 Tx Fam l s EXTERNAL CLOCK DRIVE WAVEFORMS 270942 21 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS EXTERNAL 8XC196KC CLOCK INPUT clock driver XTAL2 8XC196KC no connect XTAL2 Quartz Crystal 270942 41 270942 42 NOTE NOTE Keep oscillator components close to chip and use Required if TTL driver used short direct traces to XTAL1 XTAL2 and Vss When Not needed if CMOS driver is used using crystals C1 C2 20 pF When using ceramic resonators consult manufacturer for recommended cir cuitry AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS i TIMING REFERENCE TEST POINTS lt V ue T LORD 22 POINTS 270942 22 270942 23 Testing inputs driven at 2 4V a Logic 1 and 0 45V for For Timing Purposes a Port Pin is no Longer Floating when a a Logic 0 Timing measurements are made at 2 0V for a Logic 150 mV change from Load Voltage Occurs and Begins to Float 71 and 0 8V for a Logic 0 when 150 mV change from the Loaded oL Level occurs 15 mA 17 E 8 196 8 196 20 ntel EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by T for tim
3. MAX is now specified at 15 ns was formerly unspecified The Tj vy and Tj specifications were removed These specifications not required in high speed systems designs Added EXTINT PO 7 errata to Errata section The following are the important differences between the 001 and 002 versions of data sheet 270942 Express and Commercial devices are combined into one data sheet The Express only data sheet 270794 001 is obsolete Removed KB KC feature set differences pin definition table and SFR locations and bitmaps Added programming pin function to package drawings and pin descriptions Changed absolute maximum temperature under bias from 0 C to 70 to 55 C to 125 C Replaced specification with and 4 specifications Added specification for NMI pulldown resistors Added maximum hold latency table Added external oscillator and external clock circuit drawings Changed Clock Drive and Tx xx Min spec to 20 ns Fixed Serial Port specification Added 8 and 10 bit mode A D operating conditions tables opecified operating range for sample and convert times Added specification for voltage on analog input pin Put operating conditions for EPROM programming into tabular format 25
4. Memory Determined by EA 2080H Reserved Must contain FFH 207FH Note 5 205EH PTS Vectors 205DH 2040H Upper Interrupt Vectors 203FH 2030H ROM OTPROM Security Key 202FH 2020H Reserved Must contain FFH 201FH Note 5 201AH Reserved Must Contain 20H 2019H Note gt Reserved Must contain FFH 2017H Note 5 2014H Lower Interrupt Vectors 2013H 2000H Port 3 and Port 4 1FFFH 1FFEH External Memory 1FFDH 0200 488 Bytes Register RAM Note 1 01FFH 0018H CPU SFR s Notes 1 4 0017H 0000H NOTES 1 Code executed in locations 0000H to O1FFH will be forced external 2 Reserved memory locations must contain OFFH unless noted 3 Reserved SFR bit locations must contain O 4 Refer to 8XC196KC User s manual for SFR descriptions 5 WARNING Reserved memory locations must not be written or read The contents and or function of these lo cations may change with future revisions of the device Therefore a program that relies on one or more of these locations may not function properly 8 196 8 196 20 BUSWIDTH ALE ADV C 7 PMODE 3 EXTINT ACH7 L CLKOUT co P0 6 PMODE 2 ACH6 L1 P0 2 ACH2 o L P0 0 ACHO LT P0 1 ACH1 gt P0 3 ACH3 5 1 P0 5 P3 0 ADO 0 0 4 P3 1 AD1 ANGND P3 2 AD2 fu P3 3 AD3 Vex P3 4 AD4 EXTINT PROG P2 2 68 PIN PLCC P3 5 AD5 RESET P3 6 AD6 RXD PALE P2 1 P3 7 AD7 TXD
5. 8 196 8 196 20 DESCRIPTIONS Continued Symbol Ports 3 and 4 H H B PMODE OLD LDA REQ ALE ROG Name and Function 8 bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Bus Hold input requesting control of the bus Bus Hold acknowledge output indicating release of the bus Bus Request output activated when the bus controller has a pending external memory cycle Determines the EPROM programming mode A low signal in Auto Programming mode indicates that programming is in process A high signal indicates programming is complete Cummulative Program Output Verification Pin is high if all locations have programmed correctly since entering a programming mode A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode indicates that ports 3 and 4 contain valid programming address command information input to slave A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid programming data input to slave A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode indicates the byte programmed correctly Auto Increment Active low input signal indicates that the auto increment mode is enabled Auto Increment will allow reading or writing of sequential EPROM locations without address transactions acros
6. RESET and XTAL1 2 Violating these specifications in Reset may cause the part to enter test modes 3 Commercial specifications apply to express parts except where noted 4 QBD Quasi bidirectional pins include Port 1 P2 6 and P2 7 5 Standard Outputs include ADO 15 RD WR ALE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4 TXD P2 0 and RXD in serial mode 0 The specification is not valid for RESET Ports 3 and 4 are open drain outputs 6 Standard Inputs include HSI pins READY BUSWIDTH RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 7 Maximum current per pin must be externally limited to the following values if VoL is held above 0 45V or Voy is held below Vcc 0 7 on Output pins 10 mA on quasi bidirectional pins self limiting on Standard Output pins 10 mA 8 Maximum current per bus pin data and control during normal operation is 3 2 mA 9 During normal non transient conditions the following total current limits apply Active Mode Current in Reset 8XC196KC H 2 o H EN a N M eS N alalal8lol gt ojoj Port 1 P2 6 29 mA is self limiting HSO P2 0 RXD RESET lol 29 mA 26 mA P2 5 P2 7 WR BHE loi 13 mA 11 mA ADO AD15 52 mA 52 mA RD ALE INSTtCLKOUT lo 13 mA 13 mA 10 ntel 8XC196KC 8XC196KC20 270942 17 Icc 4 13 x Frequency 9
7. at the end of the topside tracking number topside tracking number consists of nine characters and is the second line on the top side of the device Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following are differences between the 270942 006 datasheet and the 270942 005 datasheet 1 Package prefix variables have changed Variables are now indicated by an x The following are differences between the 270942 004 and 270942 005 datasheets 1 Removed Word Addressable Only from Port and 4 in Table 2 2 Renamed PVAL to CPVER Removed yy and Gy from the waveform diagrams 4 Added HSI MODE divide by eight and IPD hump to 8XC196KC errata The following are important differences between the 270942 002 and 270942 004 data sheets 1 NMI during PTS QBD port glitch and Divide HOLD READY erratas were fixed and have been removed from the data sheet The HSI errata is also removed as this is now considered normal operation 2 Combined 16 and 20 MHz data sheets Data sheet 270924 001 20 MHz is now obsolete 3 Added 80 lead SQFP package pinout 4 Added documentation for CLKOUT disable bit 5 0jA for package was changed to 55 C W from 42 C W 6 0jc for QFP package was changed to 16 C W from TBD C W 7 Tsam MIN in 10 bit mode was changed to 1 0 us from 3 0 pus 8 TsA
8. mA Icc 3 50 Frequency 9 mA 1 25 Frequency 5 mA lipLE Typ 0 88 x Frequency mA NOTE Frequencies below 8 MHz are shown for reference only no testing is performed Figure 7 Icc and vs Frequency AC CHARACTERISTICS For use over specified operating conditions Test Conditions Capacitive load on all pins 100 pF Rise and fall times 10 ns Fosc 16 MHz The system must meet these specifications to work with the 80C196KC Symbol units TYLYH No upper limit Tuvx TAVDV Address Valid to Input Data Valid 3 Tosc 55 TRLDV RD Active to Input Data Valid w NOTES 1 If max is exceeded additional wait states will occur 2 If wait states are used add 2 where number of wait states 11 E 8 196 8 196 20 ntel AC CHARACTERISTICS Continued For user over specified operating conditions Test Conditions Capacitive load on all pins 100 pF Rise and fall times 10 ns Fosc 16 MHz 80 196 will meet these specifications Symbol Description Max Unis Notes _ Frequency XTAL1 8 96 8 16 MHz Note Frequency XTAL1 8 196 20 Note 1 xraL 8 196 62 5 20 EMO CLKOUTFatng 5 _ Tuch AtEFalinpEdgeto CLKOUTRising 20 15 CydeTme 4Tosc Tav Address Setup to ALEFalingEdge Tos
9. 96 8 196 20 Z P3 0 ADO L P3 1 AD1 5 2 02 P3 3 AD3 P3 4 AD4 L P3 5 AD5 L P3 6 AD6 P3 7 AD7 P4 0 AD8 I P4 1 AD9 L P4 2 AD10 L P4 3 AD1 1 P4 4 4D12 L1 P4 5 AD13 L P4 6 AD14 P4 7 AD15 P2 3 T2CLK J o rw J Al o RD ALE ADV INST BUSWIDTH CLKOUT XTAL2 XTAL 1 ZI P2 4 T2RST AINC BHE WRH Z WR WRL 80 PIN SQFP L P2 5 PWM O L P2 7 T2CAPTURE PACT 87 196 N OO CO RR TOP VIEW M LOOKING DOWN ON N C L P2 6 T2UP DN CPVER ACH3 P0 3 COMPONENT SIDE ZI P1 7 HOLD ACH 1 PO 1 OF PC BOARD P1 6 HLDA ACHO PO 0 L P1 5 BREQ 2 2 ACH6 PMODE 2 P0 6 ACH7 PMODE 3 P0 7 41 7 1 5 0 5 C4 5 1 0 5 ACH4 PMOD 0 P0 4 RXD PALE P2 1 L3 TXD PVER P2 0 PWM 1 P1 3 PWM 2 P1 4 270942 44 Figure 6 80 SQFP Package ntel 8XC196KC 8XC196KC20 PIN DESCRIPTIONS Symbol Name and Function Main supply voltage 5V Digital circuit ground OV There are multiple Vss pins all of which must be connected VREF Reference voltage for the A D converter 5V Vpgr is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function ANGND Reference ground for the A D converter Must be held at nominally the same potential as Vs
10. ER CONTROL SIGNALS 16 piles TIMER 2 TIMER 1 ALTERNATE FUNCTIONS 270942 1 2 EXTERNAL CLOCK 1 2 INTERNAL CLOCK ENABLE CLKOUT 1 DISABLE CLKOUT 0 DISABLE 1 ENABLE 270942 45 NOTE RSV Reserved bits must be Figure 2 8XC196KC New SFR Bit CLKOUT Disable intel PROCESS INFORMATION This device is manufactured on PX29 5 or PX29 9 a CHMOS III process Additional process and reliabili ty information is available in the Intel Quality System Handbook http developer intel com design quality quality htm Device Speed No Mark 16 MHz 20 20 MHz KC Product Family CHMOS Technology Program Memory Options O CPU only 3 ROM 7 OTPROM Note 1 Package Type Options Temperature and Burn in Options 270942 43 1 EPROMs are available as One Time Programmable OTPROM only Figure 3 The 8XC196KC Family Nomenclature Table 1 Thermal Characteristics Package m PLCC 35 C W 13 C W sscw All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operation conditions and application See the Intel Packaging Handbook order number 240800 for a description of Intel s thermal impedance test methodology 8XC196KC 8XC196KC20 Table 2 8XC196KC Memory Map External Memory or I O OFFFFH 06000H Internal ROM OTPROM or External
11. M MIN in 8 bit mode was changed to 1 0 us from 2 0 us 9 lj 4 specification for port 2 0 was renamed lj 2 10 2 is changed to TBD from 6 mA 11 MAX is changed to 200 uA from 100 uA 12 test condition changes to Vij 2 4V from Viy 5 5V 13 Vuys is changed to 300 mV from 150 mV 14 TYP at 16 MHz is changed to 65 mA from 50 mA 15 MAX at 16 MHz is changed to 75 mA from 70 mA 16 Icc TYP at 20 MHz is changed to 80 mA from 60 mA 17 MAX at 20 MHz is changed to 92 mA from 86 mA 18 TYP at 16 MHz is changed to 17 mA from 15 mA 19 MAX at 16 MHz is changed to 25 mA from 30 20 pg at 20 MHz is changed to 21 mA from 15 mA 21 lipuLg MAX at 20 MHz is changed to 30 mA from 35 mA 22 1 TYP at 16 MHz is changed to 8 uA from 15 uA 23 Ipp MAX at 16 MHz is changed to 15 uA from TBD 24 Ipp TYP at 20 MHz is changed to 8 uA from 18 uA 25 Ipp MAX at 20 MHz is changed to 15 uA from TBD 26 MAX is changed to Tosc 45 ns from Tosc 50 ns 27 Ti L Ax MIN is changed to Tosc 35 ns from Tosc 40 ns 28 MIN is changed to 5 ns from 10 ns 29 TRHax MIN is changed to Tosc 25 ns Tosc 30 ns 30 is changed to 15 ns from 10 ns 31 MAX is changed to 20 ns from 15 ns 34 ntel 8XC196KC 8XC196KC20 32 33
12. PVER P2 0 P4 0 AD8 P1 0 P4 1 AD9 P1 1 P4 2 AD10 P1 2 TOP VIEW P4 3 AD11 PWM1 P1 3 P4 4 AD12 PWM2 P1 4 Component Side P4 5 AD13 PC Board HSI 0 xd P4 6 AD14 HSI 1 P4 7 AD15 1 2 0 4 P2 3 T2CLK 8XC196KC 8 196 C CN WRL WR HOLD P 1 7 HLDA P1 6 T2UP DN CPVER P2 6 BREQ P 1 5 1 3 0 5 PWMO P2 5 O T2RST AINC P2 4 0 T2CAPTURE PACT P2 7 D 270942 2 Figure 4 68 Lead PLCC Package 8 196 8 196 20 1 5 2 2 L P3 4 AD4 P3 5 AD5 L P3 7 AD7 L P4 0 AD8 P4 1 AD9 P4 2 AD10 P4 3 AD11 P4 4 AD12 L P4 5 AD13 L P4 6 AD14 P4 7 AD15 CA e e AD1 P3 1L 1 ADO P3 0 RD E ALE ADV INST BUSWIDTH CLKOUT XTAL2 XTAL 1 P2 3 T2CLK Vss READY P2 4 T2RST AINC BHE WRH WR WRL P2 5 PWMO P2 7 T2CAPTURE PACT 80 QFP 2 3 4 5 6 7 8 9 8 196 VIEW Looking Down on Component Side of PC Board HSO 2 P2 6 T2UP DN CPVER P1 7 HOLD P1 6 HLDA P1 5 BREQ HSO 1 HSO 0 HSO 5 HSI 3 3 0 3 1 1 0 ACH2 P0 2 ACH6 PMODE 2 P0 6 ACH7 EXTINT PMODE 3 P0 7 N C ACH5 1 P0 5 ACH4 PMODE 0 P0 4 Vss HSO 4 HSI 2 CO RXD PALE P2 1L TXD PVER P2 0 PWM1 P1 3 PWM2 P1 4 270942 40 Figure 5 8XC196KC 80 QFP Package 8 1
13. TA OUT ADDRESS 270942 20 Buswidth Timings CLKOUT TeLGX MIN BUSWIDTH 270942 35 14 ntel 8XC196KC 8XC196KC20 HOLD HLDA Timings Symbol Notes Then HOD setup 7 45 Noe CLKOUTLowtoHLDALow 15 5 m CLKOUTLowtoBREQLow 5 15 m Tharaz HiDALowtoAddressFoat asf Thaisz HUDA Low to INST WR Weakly Driven 20 ms Taman CLKOUTLowtoHLDAHgh 5 15 m Toms CLKOUTLowtoBREQHgh 5 15 m HiDAHightoAddressNolongerFloat 15 ms Taney High to INST WR vaid 10 15 ms Tom CLKOUTLowtoALEHgh 8 15 m NOTE 1 To guarantee recognition at next clock DC SPECIFICATIONS IN HOLD Description We Weak Pullups on ADV RD SOK 250K Vcc 5 5V Vin 0 45V WR WRL BHE Weak Pulldowns on 10K SOK Vcc 5 5V Vin 2 4 ALE INST 15 E 8 196 8 196 20 CLKOUT HOLD MEE ir TCLBRL HALAZ cry Ce _ HALBZ THAHBY Weakly Driven Inactive TeLLH Weakly Driven Inactive ADY weakly driven Start of strongly driven ADY and ALE 270942 36 Maximum Hold Latency Bus Cycle Tye Internal Execution 1 5 States EXTERNAL CLOCK DRIVE 8XC196KC Parameter
14. X 3 KR X 5 7 gt gt gt XvaLIOX 270942 24 18 ntel 8XC196KC 8XC196KC20 A to D CHARACTERISTICS The A D converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF 10 BIT MODE A D OPERATING CONDITIONS Symb Descpio TA Ambient Temperature Commercial Temp 0 o SemeTme 19 x59 Fose Oscilator Frequency XCT96KC 80 160 MHz Fose Oscilator Frequency xC196KC20 80 200 MHz NOTE ANGND and Vss should nominally be at the same potential 0 00V 1 The value of AD TIME is selected to meet these specifications 10 BIT MODE A D CHARACTERISTICS Over Specified Operating Conditions Typical 1 Maximum Units Notes Resolution 1024 1024 Levels 10 Bits 691 Differential Non Linearity Error Channel to Channel Matching Temperature Coefficients Offset 0 009 Full Scale 0 009 Differential Non Linearity 0 009 Off Isolation Feedthrough Vcc Power Supply Rejection 1 2 Voltage on Analog Input Pin 6 DC Input Leakage 9 80 Sampling Capacitor 1 LSB as used here has a value of approxiimately 5 mV See Embedded Microcontrollers Processors Handbook for A D glossary of terms 1 These values are expected for most p
15. apacitance during Auto and Slave Mode programming 150 pF AC EPROM PROGRAMMING CHARACTERISTICS PROG High to Next PALE Low PALE High to PROG Low PROG High to Next PROG Low NOTE 1 This specification is for the Word Dump Mode For programming pulses use the Modified Quick Pulse Algorithm See user s manual for further information 21 8 196 8 196 20 ntel DC EPROM PROGRAMMING CHARACTERISTICS NOTE Do not apply Vpp until Vcc is stable and within specifications and the oscillator clock has stabilized or the device may be damaged EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE TAVLL ADDR COMMAND DATA ADDR COMMAND TLLAX TPHVL 270942 27 P3 0 must be high 1 SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT ADDR ADDR 2 ADDR COMMAND VER BITS WD DUMP VER BITS WD DUMP TSHLL TPLDV TPHDX TPHDX 270942 28 NOTE P3 0 must be low 0 22 intel SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT PORTS 3 4 ADDR COMMAND 8XC196KC 8XC196KC20 RESET DATA ADDR 2 DATA ADDR a 8XC196KB TO 8XC196KC DESIGN CONSIDERATIONS 1 Memory 8XC196KC has 512 bytes of RAM SFRs and optional 16K of ROM OTPR OM The extra 256 bytes of RAM will reside in locations 100H 1FFH and
16. arts at 25 C but are not tested or guaranteed 2 DC to 100 KHz Multiplexer Break Before Make is guaranteed Resistance from device pin through internal MUX to sample capacitor These values may be exceeded if the pin current is limited to 2 mA Applying voltages beyond these specifications will degrade the accuracy of all channels being converted All conversions performed with processor in IDLE mode 10 T3 3 dz t1 5 B 60 B 6 InputSeriesResistance 750 i SS 19 se NO 8 196 8 196 20 8 BIT MODE A D OPERATING CONDITIONS Symo Description mn Unt T Aroen Temperature Commercial Temp 0 _ Tm x Oscilator Frequency xGI96KC 160 _ Oscilator Frequency 200 MHz _ NOTE ANGND and Vss should nominally be at the same potential 0 00V 1 The value of AD TIME is selected to meet these specifications 8 BIT MODE A D CHARACTERISTICS Over Specified Operating Conditions a Absolute Error asmen 9 308 E 3 Non tneariyEror gt 1 1 88 Matching Oz t9 Temperature Coefficients Offset 0 003 LSB C Full Scale 0 003 LSB C Differential Non Linearity
17. c 15 Tuax Address Hold after ALE Falling Edge Tosc 35 Tum ALE Faling Edge to RD Falling Edge Tosc 30 o RBlowwassessfot ALE Fling Ege to WR ating age Tose Taw KOUT Loo 3m m LTow Data Stable toWRRising Edge 23 Crenn 5 WRlowPeriod 9 Oat Ha ater INST after WRRisingEdge beeisHOLDaferWRReno Tos 30 Note BRE NST afer R RisingEage v beeisHOLDaferRDReng Tos 25 re Note NOTES 1 Testing performed at 8 MHz However the device is static by design and will typically operate below 1 Hz 2 Assuming back to back bus cycles 3 8 Bit bus only 4 If wait states are used add 2 Tosc N where N number of wait states 12 ntel 8XC196KC 8XC196KC20 System Bus Timings CLKOUT TRLCL TLHLH ae TRLDV D TAVLL TLLAX TIMY L TwLwH TWHLH TwHax TovwH ADDRESS OUT X DATA OUT ADDRESS BHE INST VALID ADDRESS OUT 270942 18 13 H 8XC196KC 8XC196KC20 j ntel READY Timings One Wait State CLKOUT TLHLH 4 Tose IDIM TwewH 2 Tose I 2 ADDRESS QUT DA
18. e The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions Signals L ALE AD H High A Address BR BREQ L Low B BHE R RD V Valid C W WR WRH WRL X Longer Valid D DATA X XTAL1 Z Floating G Buswidth Y READY H HOLD Q Data Out HA HLDA AC CHARACTERISTICS SERIAL PORT SHIFT REGISTER MODE SERIAL PORT TIMING SHIFT REGISTER MODE MODE 0 Serial Port Clock Period BRR gt 8002 Serial Port Clock Falling Edge 4 Tosc 50 4 Tosc 50 to Rising Edge BRR gt 8002H Serial Port Clock Period BRR 8001H Serial Port Clock Falling Edge 2 50 2 50 to Rising Edge BRR 8001H _ Output Data Setup to ClockRisingEdge 27096 50 Output Data Hold after Clock Rising Edge 27056 50 Next Output Data Valid after Clock Rising Edge 2 Toso 50 Towx Input Data Setup to ClockRisingEdge Toso 50 T upx Input Data Hold after ClockRisingEdge 01 Txmaz LastClockRisingto Output Float WAVEFORM SERIAL PORT SHIFT REGISTER MODE ns ns ns ns ns ns ns ns ns Toc ns SERIAL PORT WAVEFORM SHIFT REGISTER MODE MODE 0 Tux I If U U U U U a HY gt X X K
19. escription V V IH Input High Voltage on XTAL 1 Input High Voltage on RESET Output Low Voltage in RESET on P2 5 Note 2 Output High Voltage Standard Outputs Input High Voltage Note 1 0 2 Vcc 1 0 E 8 196 8 196 20 ntel DC CHARACTERISTICS Over Specified Operating Conditions Continued Symbol Description 7 Typ Mex Units TestConditions Output High Voltage Quasi bidirectional Outputs V mA Logical 1 Output Current in Reset on P2 0 Do not exceed this or device may enter test modes Logical 0 Input Current in Reset on P2 0 Maximum current that must be sunk by external device to ensure test mode entry BD Vin 0 45V Logical 1 Input Current Maximum current that external device must source to initiate NMI Input Leakage Current Std Inputs Input Leakage Current Port 0 1 to 0 Transition Current QBD Pins NEN 2772 NN Logical 0 input Curent QBD Pins E E T Vin Vcc 2 4V Ports 3 and 4 in Reset XTAL1 16 MHz Voc Vpp VREF 9 9V XTAL1 20 MHz Voc Vpp VREF 5 5V XTAL1 16 MHz Voc Vpp VREF 5 5V XTAL1 20 MHz Voc Vpp VREF 9 9V Voc Vpp Vngr 5 5V Voc Vpp Vngr 9 9V 5 5V Vin 4 0V pepo Active Mode Current in Reset 8XC196KC20 Idle Mode Current 8XC196KC Idle Mode Current 8 196 20 ep PowedownModeCuren NOTES 1 All pins except
20. intel 8XC196KC 8XC196KC20 COMMERCIAL EXPRESS CHMOS MICROCONTROLLER 87C196KC 16 Kbytes of On Chip OTPROM 83C196KC 16 Kbytes ROM 80C196KC ROMless 16 and 20 MHz Available m Dynamically Configurable 8 Bit or 488 Byte Register RAM 16 Bit Buswidth Register to Register Architecture Full Duplex Serial Port m 28 Interrupt Sources 16 Vectors High Speed Subsystem Peripheral Transaction Server 16 Bit Timer 1 4 us 16 x 16 Multiply 20 MHz 16 Bit Up Down Counter with Capture 2 4 us 32 16 Divide 20 MHz 3 Pulse Width Modulated Outputs Powerdown and Idle Modes m Four 16 Bit Software Timers Five 8 Bit I O Ports 8 or 10 Bit A D Converter with 16 Bit Watchd M Sample Hold NU PNE m HOLD HLD Bus Protocol Extended Temperature Available OTPROM One Time Programmable Version The 80 196 16 bit microcontroller is a high performance member of the MCS 96 microcontroller family The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM 16 and 20 MHz operation and an optional 16 Kbytes of ROM OTPR Intel s CHMOS process provides a high performance processor along with low power consumption The 87C196KC is an 80C196KC with 16 Kbytes on chip OTPROM The 83C196KC is an 80C196KC with 16 Kbytes factory programmed ROM In this document the 80C196KC will refer to all products unless otherwise stated Four high speed capture inputs are provided to record times when event
21. s Timing for the return from powerdown circuit This pin also supplies the programming voltage on the EPROM device XTAL1 Input of the oscillator inverter and of the internal clock generator XTAL2 Output of the oscillator inverter CLKOUT Output of the internal clock generator The frequency of CLKOUT is 1 the oscillator frequency RESET Reset input and open drain output BUSWIDTH Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 a 16 bit bus cycle occurs If BUSWIDTH is a 0 an 8 bit cycle occurs If CCR bit 1 is a 0 the bus is always 8 bit bus A positive transition causes a vector through 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select External Access EA equal high causes memory accesses to locations 2000H through 5FFFH to be directed to on chip ROM E PROM EA equal to low causes accesses to those locations to be directed to off chip memory Also used to enter programming mode Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a signal to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during e
22. s occur Six high speed outputs are available for pulse or waveform generation The high speed output can also generate four software timers or start an A D conversion Events can be based on the timer or up down counter With the commercial standard temperature option operational characteristics are guaranteed over the tem perature range of 0 to 4 70 C With the extended Express temperature range option operational charac teristics are guaranteed over the temperature range of 40 C to 85 C Unless otherwise noted the specifi cations are the same for both options See the Packaging information for extended temperature designators Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTELCORPORATION 2004 July 2004 Order Number 270942 006 8 196 8 196 20 Veer ANGND FREQUENCY REFERENCE CLOCK GEN BYTES OPTIONAL A D REGISTER 16 KBYTES CONVERTER RAM INTERRUPT ROM OTPROM 24 BYTES CONTROLLER CPU SFR T6 t MEMORY CONTROLL
23. s the PBUS for each read or write intel ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Blas ein tiri erre ens 55 to 125 Storage Temperature 65 to 150 Voltage On Any Pinto 55 0 5V to 7 0V 1 Voltage from EA or Vpp to Vss 13 00V Power 1 5W 2 NOTE 1 This includes Vpp and EA on ROM or CPU only devices 2 Power dissipation is based on package heat transfer lim itations not device power consumption OPERATING CONDITIONS 8XC196KC 8XC196KC20 NOTICE This is a production data sheet It is valid for the devices indicated in the revision history The specifications are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex fended exposure beyond the Operating Conditions may affect device reliability Ambient Temperature Under Bias Commercial Temp Ambient Temperature Under Bias Extended Temp 40 ANGND Analog Ground Voltage Oscillator Frequency 8XC196KC Oscillator Frequency 8XC196KC20 NOTE 1 ANGND and Vss should be nominally at the same potential DC CHARACTERISTICS Over Specified Operating Conditions Symbol D
24. the extra 8K of ROM OTPROM will reside in locations 4000H x5FFFH These locations are external memory on the 8 196 The CDE pin on the KB has become a Vss pin on the KC to support 16 20 MHz operation EPROM programming The 8XC196KC has a dif ferent programming algorithm to support 16K of on board memory When performing Run Time Programming use the section of code in the 8XC196KC User s Guide 4 VALID VALID FOR P1 270942 29 ONCE Mode Entry The ONCE mode is entered on the 8XC196KC by driving the TXD pin low on the rising edge of RESET The TXD pin is held high by a pullup that is specified by log4 This Pullup must not be overridden or the 8XC196KC will enter the ONCE mode During the bus HOLD state the 8 196 weakly holds RD WR ALE BHE and INST in their inactive states The 8XC196KB only holds ALE in its inactive state A RESET pulse from the 8XC196KC is 16 states rather than 4 states as on the 8XC196KB i e a watchdog timer overflow This provides a longer RESET pulse for other devices in the system 8XC196KC ERRATA 1 Missed EXTINT on 7 The 80C196KC20 could possibly miss EXTINT on 7 See techbit 0893 HSI MODEdivide by eight See Faxback 2192 IPD hump See Faxback 2311 23 E 8 196 8 196 20 ntel DATA SHEET REVISION HISTORY This data sheet is valid for devices with H L or M
25. xternal memory accesses Read signal output to external memory RD is activated only during external memory reads Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes Bus High Enable or Write High output to external memory as selected by the CCR BHE will go low for external writes to the high byte of the data bus WRH will go low for external writes where an odd byte is being written BHE WRH is activated only during external memory writes Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory or for bus sharing When the external memory is not being used READY has no effect Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 HSI 3 Two of them HSI 2 and 1 3 are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSI 3 HSO 4 and HSO 5 Two of them HSO 4 5 5 are shared with the HSI Unit 8 bit high impedance input only port These pins can be used as digital inputs and or as analog inputs to the on chip A D converter 8 bit quasi bidirectional I O port 8 bit multi functional port All of its pins are shared with other functions in the 80C196KC Pins 2 6 and 2 7 are quasi bidirectional
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