µPD78081(A), 78082(A)
Contents
1. 780208 82 K to 60 K 780228 48 60 K 78044 82 K to 48K uPD78044F 16 40 780308 48 60 K 3ch time division UART 1 57 2 0 V uPD78064B 32 K 2ch UART 1ch uPD78064 16K to 32K IEBus uPD78098B 40Kto 60K 2ch ich ich ich 8ch 2ch 3ch UART 1ch 69 2 7 Available supported uPD78098 32 K to 60 K Meter 780973 24 K to 32K 2ch UART 1ch Note 10 bit timer 1 channel NEC OVERVIEW OF FUNCTION Part Number Internal ROM uPD78081 A 78082 A 78081 uPD78082 A 8 Kbytes 16 Kbytes memory Internal high speed RAM 256 bytes 384 bytes Memory space 64 Kbytes General registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks Minimum instruction execution time On chip minimum instruction execution time selective function 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us at main system clock of 5 0 MHz Instruction set ports 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test boolean operation BCD adjustment etc Total CMOS input CMOS A D converter 8 bit resolution x 8 channels Serial interface 3 wire serial I O UART mode selectable 1 channel Timer 8 bit timer event counter 2 channels2. 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SCK2 high low level widths tkH2 tkL2 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V SI2 setup time to SCK27 Voo 2 0 to 5 5 V SI2 hold time from SCK27 SO2 output delay time from SCK24 100 pF Note Von 2 0 to 5 5 V SCK rise fall time tre tF2 Note C is the load capacitance of SO2 output line 33 NEC uPD78081 A 78082 A Electrical specifications of 78081 and 78082 A 7 11 c UART mode Dedicated baud rate generator output Parameter Conditions Transfer rate 4 5 lt lt 5 5 V 78 125 2 7 V lt lt 4 5 V 39 063 2 0 V lt Voo lt 2 7 V 19 531 9 766 d UART mode External clock input Parameter Conditions ASCK cycle time 4 5 lt lt 5 5 V 2 7 V lt lt 4 5 V 2 0 lt Voo lt 2 7 V ASCK high low level tkHs tkLs 4 5 lt 00 lt 5 5 widths 2 7 V lt Vpp 4 5 V 2 0 lt Voo lt 2 7 V Transfer rate 4 5 lt lt 5 5 V 2 7 lt Vpp 4 5 V 2 0 lt Voo lt 2 7 V ASCK rise fall time tra tes 34 NEC uPD78081 A 78082 A Electrical specifications of uPD78081 A and 78082 A 8 11 AC Timing Test Points excluding X1 Input 0 8 0 8 Test poin
3. 14 5 PERIPHERAL HARDWARE FUNCTIONS 15 5 41 LICINIUS 15 5 2 canstdssevedevasisviversdasassddensaneaveusuieueuaseaveuvinavsiveinanvescavansasenese 16 53 Timer Event Counter cierran niu ex sna Snc amet n Eo SKAXRERRNNRN anas 16 5 4 Clock Output Control Circuil nicer terroir 18 5 5 Buzzer Output Control Circuit 18 5 6 JA D GORVOFter ERA R RR PUR 19 5 7 Serial Interface sss rie rais ianua Ea wa RR ra a wa ra CE E SERERE SER EN AN ERR AN DRE BER E ERE DR 20 6 INTERRUPT FUNCTIONS eg Ee axes aou duhcauecesauanesudeaaudesaswesuusedddesesssnustwesweenden 21 STANDBY FEUNGTION 5 iie QU IIT 24 8 IZ i Mleem 24 9 r cadrilesxyehkj gmeec 25 10 ELECTRICAL SPECIFICATIONS eere eere nnn nn hannis auda sas aa R44 44 Sa ERAN RRR R4 EAR nnmnnn nada 28 11 PACKAGE DRAWINGS 49 12
4. Guaranteed Range Operation 1 2 3 4 5 6 Power Supply Voltage Voo V NEC uPD78081 A 78082 A Electrical specifications of 78081 2 5 10 2 Serial Interface Ta 40 to 125 C 5 V 10 a 3 wire serial I O mode SCK2 Internal clock output Parameter Conditions SCK cycle time 1 000 SCK2 high low level tkcvi 2 100 widths SI2 setup time 150 to SCK27 SI2 hold time from SCK21 SO2 output delay time C 100 pF Note from SCK21 Note C is the load capacitance of SCK2 and SO2 output lines b 3 wire serial mode SCK2 External clock input Parameter Conditions SCK2 cycle time SCK2 high low level widths SI2 setup time to SCK2T SI2 hold time from SCK2T SO2 output delay time C 100 pF Note from SCK21 SCK2 rise fall time tro tre Note C is the load capacitance of SO2 output line 43 NEC Electrical specifications of 78081 2 6 10 c UART mode Dedicated baud rate generator output uPD78081 A 78082 A d UART mode External clock input Parameter ASCK cycle time tkcy3 Conditions ASCK high low level widths tkL3 44 Transfer rate ASCK rise fall time tna tra NEC uPD78081 A 78082 A El
5. 78081 A 7808204 FIP and IEBus are trademarks of NEC Corporation MS DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation HP9000 Series 300 HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS is a trademark of Sun Microsystems Inc NEWS and NEWS OS are trademarks of Sony Corporation The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from
6. 0 3 to 0 3 0 3 to 0 3 0 3 to 0 3 Input voltage 0 3 to 0 3 Output voltage 0 3 to 0 3 Analog input voltage P10 to P17 Analog input pins AVss 0 3 to AVner 0 3 Output current high Per pin 10 Total of P10 to P17 P50 to P54 P70 to P72 15 P100 P101 Total of to P30 to P37 P55 to P57 15 Output current low Per pin Peak value 30 r m s value 15 Total of P50 to P54 Peak value r m s value 70 Total of P55 to P57 Peak value r m s value 70 Total of P10 to P17 P70 to P72 Peak value 50 P100 P101 r m s value 20 Total of P01 to P03 P30 to P37 Peak value 50 r m s value 20 Operating ambient temperature 40 to 125 Storage temperature 65 to 150 Note The r m s value should be calculated as follows r m s value Peak value x Duty Caution If the absolute maximum rating of even one of the above parameters is exceeded the quality of the product may be degraded The absolute maximum ratings are therefore the rated values that may if exceeded physically damage the product Be sure to use the product with all the absolute maximum ratings observed Permissible Pin Sink Current Characteristics with Overvoltage Applied Pending Capacitance Ta 25 C Vss 0 ume smi est eos e we ui Input capacitance f 1 MHz Unmeasured pins returned
7. IE 78078 R EM Emulation board common to the 78078 Subseries EP 78083GB R Emulation probe for the 78083 Subseries EV 9200G 44 Socket mounted on the target system board prepared for 44 pin plastic QFP SM78K0 Notes 5 6 7 System simulator common to the 78K 0 Series ID78KO Notes 4 5 6 7 Integrated debugger for the IE 78000 R A SD78K 0 Notes 1 2 Screen debugger for the IE 78000 R DF78083 Notes 1 2 5 6 7 Device file used for the 78083 Subseries Notes 1 Based on PC 9800 Series MS DOS 2 Based on IBM PC AT and its compatibles PC DOS IBM DOS V MS DOS 3 Based on HP9000 Series 300 HP UX 4 Based on HP9000 Series 700 HP UX SPARCstation SunOS and EWS4800 Series EWS UX V 5 Based on PC 9800 Series MS DOS Windows m Based on IBM PC AT and its compatibles PC DOS IBM DOS MS DOS Windows 7 Based on NEWS NEWS OS V Remarks 1 Please refer to the 78K 0 Series Selection Guide U11126E for information on the third party development tools 2 Use the RA78K 0 CC78K 0 SM78KO0 ID78K0 and SD78K 0 in combination with the DF78083 52 NEC uPD78081 A 78082 A Real Time OS 78 Notes 1 2 3 4 OS used for the 78K 0 Series Fuzzy Inference Development Support System FE9000 Note 1 200 Note 5 Fuzzy knowledge data input tool FT9080 Note 1 F T9085 Note 2 Translator FI78KQ Notes 1 2 Fuzzy inferen
8. P30 to P37 P50 to P57 P70 to P72 P100 P101 RESET X1 X2 Input leak current low P00 to P10 to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 RESET Output leak current high Vout Output leak current low Vout 0 V Software pull up resistance 20V P01 to to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 Remark Unless otherwise specified alternate function pin characteristics are the same as port pin characteristics 30 NEC Electrical specifications of 78081 and 78082 A 4 11 DC Characteristics Ta 40 to 85 C 1 8 to 5 5 V Parameter Supply current Nete 1 Test Conditions 5 0 MHz crystal oscil lation operating mode 2 5 MHz 12 Voo 5 0 V 10 Note4 uPD78081 A 78082 A 3 0 V 10 Note 5 2 0 10 Note 5 5 0 MHz crystal oscil 5 0 V 10 4 lation operating mode 3 0 10 Notes 5 0 MHz Nete3 5 0 MHz crystal oscil 5 0 V 10 lation HALT mode Voo 3 0 V 10 fxx 2 5 MHz Nete 2 0 V 10 5 0 MHz crystal oscil 5 0 V 10 lation HALT mode 3 0 V 10 fxx 5 0 MHz Nete3 STOP mode 5 0 V 10 3 0 V 10 2 0 V 10 Notes 1 Not including AVrer and cur
9. 1 channel 3 wire serial I O UART mode 1 channel Timer 3 channels Supply voltage 1 8 to 5 5 V APPLICATION FIELDS Controllers for automobile electronic control systems gas detector circuit breakers various types of safety equipment etc In addition to the 78081 A and 78082 A this Data Sheet also describes the PD78081 A2 Unless otherwise specified however the 78081 and 78082 A are used throughout this Data Sheet as the representative products and their descriptions also apply to the uPD78081 A2 The information in this document is subject to change without notice Document No U12436EJ1VO0DS00 1st edition Date Published July 1997 N Printed in Japan NEC Corporation 1997 NEC uPD78081 A 78082 A ORDERING INFORMATION Part Number Package uUPD78081 GB A xxx 3B4 44 pin plastic QFP 10 x 10 mm uPD78081 GB A xxx 3BS MTX 44 pin plastic QFP 10 x 10 mm 78082 3 4 44 pin plastic QFP 10 x 10 mm 78082 44 pin plastic QFP 10 x 10 mm 78081 2 3 4 44 plastic QFP 10 x 10 mm Note Under planning Caution 78081 and 78082GB A have two kinds of package Refer 11 PACKAGE DRAWINGS Please consult NEC s sales representative for the available package Remark xxx indicates ROM code suffix QUALITY GRADE Special Please refer to Quality Grades on NEC Semiconductor De
10. Input Input output uPD78081 A 78082 A Function Port 0 Input only After Reset Shared by 4 bit input output port Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software P10 to P17 P30 to P34 P37 Input output Input output Port 1 8 bit input output port Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software Note Port 3 8 bit input output port Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software ANIO to ANI7 P50 to P57 Input output Port 5 8 bit input output port Can drive up to seven LEDs directly Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software Input output Port 7 3 bit input output port Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software SI2 RxD SO2 TxD SCK2 ASCK Input output Port 10 2 bit input output port Input output is specifiable bit wise When used as the input port it is possible to connect a pull up resistor by software 5 Note When P10 ANIO to P17 ANI7 pins are used as the analog inputs for the A D converter set the port 1 to the in
11. A xxx 3B4 78081 GB A2 xxx 3B4 44 PIN PLASTIC 1110 detail of lead end La NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 15 mm 0 006 inch of A 13 6 0 4 0 535 0 017 its true position T P at maximum material condition 0 008 B 10 0 0 2 0 394 0 008 C 10 0 0 2 0 394 0 008 Remark The shape and material of ES versions are the same as 0 017 those of mass produced versions D 13 6 0 4 0 535 0 016 F 1 0 0 039 G 1 0 0 039 0 004 H 0 35 0 10 0 014 0 005 0 15 0 006 J 0 8 T P 0 031 T P 0 008 K 1 8 0 2 0 071 0 009 0 009 L 0 8 0 2 0 031 0 008 0 10 0 004 M 0 15005 0 006 0 003 N 0 10 0 004 P 2 7 0 106 Q 0 1 0 1 0 004 0 004 R 5 5 5 5 S 3 0 MAX 0 119 MAX P44GB 80 3B4 3 49 NEC uPD78081 A 78082 A 78081 78082GB A xxx 3BS MTX 44 PIN PLASTIC 1110 detail of lead end S Q NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0 16 mm 0 007 inch of A 13 240 2 0 520 9 008 its true position T P at maximum material condition 0009 0 008 B 10 0 0 2 0 394 0 009 0 008 C 10 0 0 2 0 3947 97009 0 008
12. Data retention power supply voltage Data retention power Voppr 4 5 V supply current Release signal set time Oscillation stabilization Release by RESET 217 fx wait time Release by interrupt request Note Note combination with bits to 2 OSTSO to OSTS2 of oscillation stabilization time select register OSTS selection of 2 2 and 2 4 fxx to 2 fxx is possible Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Data Retention Timing STOP mode release by RESET Internal reset operation 1 HALT mode lt 0 STOP mode gt lt Operating mode Data retention mode STOP instruction execution RESET Data Retention Timing Standby release signal STOP mode release by interrupt request signal HALT mode ra STOP mode gt lt gt gt Operating mode Data retention mode 4 STOP instruction execution Standby release signal interrupt request lt lt 47 NEC Electrical specifications of 78081 2 10 10 Interrupt Request Input Timing INTP1 to INTP3 RESET Input Timing tras M RESET 48 uPD78081 A 78082 A NEC uPD78081 A 78082 A 11 PACKAGE DRAWINGS 78081 3 4 78082GB
13. Name SD78K 0 Screen Debugger Introduction uPD78081 A 78082 A Document No Japanese EEU 852 English U10539E PC 9800 Series MS DOS Based Reference U10952J SD78K 0 Screen Debugger Introduction EEU 5024 EEU 1414 IBM PC AT PC DOS Based Reference Documents Related to Embedded Software User s Manual Document Name 78K 0 Series OS MX78K0 Fuzzy Knowledge Data Input Tools U11279J U11279E Document No Japanese U12257J EEU 829 English EEU 1438 78K 0 78 and 87AD Series Fuzzy Inference Development Support System Translator 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU 862 EEU 858 EEU 1444 EEU 1441 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Other Documents Document Name IC Package Manual EEU 921 EEU 1458 Document No Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Electrostatic Discharge ESD Test MEM 539 Guide to Quality Assurance for Semiconductor Devices C11893J MEI 1202 Microcomputer Product Series Guide Caution The contents of the documents listed above are subject to change without prior notice
14. RECOMMENDED SOLDERING CONDITIONS 51 APPENDIX A DEVELOPMENT TOOLS 52 APPENDIX B RELATED DOCUMENTS 54 NEC 1 PIN CONFIGURATION Top View 44 pin plastic QFP 10 x 10 mm 78081 3 4 xxx 3BS MTX Nete xxx 3B4 A xxx 3BS MTX 78081 2 3 4 uPD78081GB uPD78082GB uPD78082GB A A z lt O P10 ANIO O AVss AV REF Voo O X1 X2 O IC o RESET NC uPD78081 A 78082 A P12 ANI2 O 1 O POS INTP3 P13 ANIS O 2 PO2 INTP2 P14 ANI4 O 3 PO1 INTP1 P15 ANI5 4 o P16 ANI6 O 5 P37 P17 ANI7 O 6 P36 BUZ P72 ASCK SCK2 7 P35 PCL P71 TxD SO2 o 8 P34 P70 RxD SI2 o 9 o P33 P101 TI6 TO6 1 o P32 P100 TI5 TO5 O NC Note Under planning Cautions 1 P500 P510 P520 P53 0 P54 Vss O P550 P560 P570 P300 Connect IC Internally Connected pin directly to Vss P31 2 Connect to 3 4 Connect AVss pin to Vss Connect NC Non connection pin to Vss for noise protection It can be left open NEC ANIO to ANI7 ASCK AVDD AVREF AVss BUZ IC INTP1 to INTP3 NC to P10 to P17 P30 to
15. bus Vector table address generator Priority control circuit Interrupt request IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag Interrupt mask PR Priority specification flag 23 NEC uPD78081 A 78082 A 7 STANDBY FUNCTION The standby function intends to reduce current consumption It has the following two modes HALT mode Inthis mode the CPU operation clock is stopped The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode STOP mode In this mode oscillation of the main system clock is stopped All the operations performed onthe main system clock are suspended and power consumption becomes extremely small Figure 7 1 Standby Function Main system clock operation STOP instruction HALT instruction Interrupt request Interrupt request HALT mode Supply of clock to CPU is stopped although clock is generated STOP mode Oscillation of the main system clock is stopped 8 RESET FUNCTION There are the following two reset methods External reset by RESET pin nternal reset by watchdog timer runaway time detection 24 NEC uPD78081 A 78082 A 9 INSTRUCTION SET 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4
16. potential as Vss Do not connect the ground pattern through which a high current flows Do not extract signals from the oscillation circuit 40 NEC uPD78081 A 78082 A Electrical specifications of 78081 2 3 10 DC Characteristics Ta 40 to 125 5 V 10 Parameter Test Conditions Input voltage high P10 to P17 P30 to P32 P35 to P37 P50 to P57 to P33 P34 P70 to P72 P100 P101 RESET X1 X2 Input voltage low P10 to P17 P30 to P32 P35 to P37 P50 to P57 POO to P33 P34 P70 to P72 P100 P101 RESET X1 X2 Output voltage high 1 mA lou 100 uA Output voltage low P50 to P57 15 mA P01 to P10 to lo 1 6 mA P17 P30 to P37 P70 lot 400 uA to P72 P100 P101 Input leak current high Vin to to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 RESET X1 X2 Input leak current low to P10 to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 RESET X1 X2 Output leak current high Vout Output leak current low Vout 0 V Software pull up resistance Vn 0V P01 to P03 P10 to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 Supply current Note 1 7 0 MHz crystal oscillation operating mode 3 5 MHz Notes 2 3 5 0 MHz crystal oscillation operating mode 2 5 MHz Notes 2 3 7 0 MHz crystal oscillatio
17. processes once Preheating temperature 120 C or below package surface tem perature WS60 00 1 Pin partial heating Pin temperature 300 C or below Time 3 seconds or below per device side Cautions 1 Use of more than one soldering method should be avoided except for the pin partial heating method 2 Because production of the PD78081GB A xxx 3BS MTX and 78082GB A xxx 3BS MTX is still in a planning stage their soldering conditions are pending 51 NEC uPD78081 A 78082 A APPENDIX A DEVELOPMENT TOOLS The following development tools are available to support development of systems using the 78081 and 78082 A Language Processing Software RA78K 0 Notes 1 2 3 4 Assembler package common to the 78K 0 Series CC78K 0 Notes 1 2 3 4 C compiler package common to the 78K 0 Series DF78083 Notes 1 2 3 4 Device file used for the 78083 Subseries CC78K 0 L Notes 1 2 3 4 PROM Writing Tools PG 1500 C compiler library source file common to the 78K 0 Series PROM programmer PA 78P083GB Programmer adapter connected to the PG 1500 PG 1500 Controller Notes 1 2 Debugging Tools IE 78000 R Control program for the PG 1500 In circuit emulator common to the 78K 0 Series 78000 In circuit emulator common to the 78K 0 Series for integrated debugger IE 78000 R BK Break board common to the 78K 0 Series
18. serial interface channel synchronous with the clock The serial interface channel 2 operates in the following two modes e 3 wire serial mode Starting bit MSB LSB switching possible Asynchronous serial interface UART mode On chip dedicated baud rate generator Figure 5 7 Serial Interface Channel 2 Block Diagram Internal bus Receive buffer register RXB SIO2 Direction control circuit Transmit shift register TXS SIO2 Transmit control RxD SI2 P70 circuit INTST TxD SO2 P71 C INTSER INTSR INTCSI2 Baud rate generator SCK output control circuit 4 ASCK SCK2 P72 lt gt to fxx 210 20 NEC uPD78081 A 78082 A 6 INTERRUPT FUNCTIONS Interrupt functions include three types and thirteen sources as shown below Non maskable 1 Maskable 11 Software 1 Table 6 1 List of Interrupt Sources Note 1 Interrupt Default Type Priority Interrupt Source Internal Trigger External Non INTWDT Overflow of watchdog timer when the watchdog Internal maskable timer mode 1 is selected Maskable INTWDT Overflow of watchdog timer when the interval timer mode is selected INTP1 Pin input edge detection External INTP2 INTP3 INTSER Occurrence of serial interface channel 2 UART Internal reception error INTSR Completion of serial interface channel 2 UART reception IN
19. to 0 V capacitance f 1 MHz P01 to to P17 P30 to Unmeasured pins P37 P50 to P57 P70 to P72 returned to 0 V P100 P101 Remark Unless otherwise specified alternate function pin characteristics are the same as port pin characteristics 39 NEC Electrical specifications of 78081 2 2 10 uPD78081 A 78082 A Main System Clock Oscillator Characteristics Ta 40 to 125 C 5 V 10 Test Conditions MIN Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency fx Note 1 Oscillation stabilization time Note 2 External clock X1 input frequency fx Note 1 uPD74HCUOA X1 input high low level widths txu tx Notes 1 Onlytheoscillator characteristics are shown Forthe instruction execution time referto AC Characteristics 2 Time required for oscillation to stabilize after a reset or the STOP mode has been released Caution When using oscillation circuit of the main system clock wire the portion enclosed in broken lines in the figure as follows to avoid adverse influence on the wiring capacitance Keep the wiring length as short as possible Do not cross the wiring over other signal lines Do not route the wiring in the vicinity of lines through which a high fluctuating current flows Always keep the ground point of the capacitor of the oscillation circuit at the same
20. 5 Port 7 Port 10 32 Total 33 Table 5 1 Functions of Ports Port Name Pin Name Function POO Input only P01 to Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software P10 to P17 Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software P30 to P37 Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software P50 to P57 Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software LED can be driven directly up to 7 pins Port 7 P70 to P72 Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software Port 10 P100 P101 Input output port Input output can be specified bit wise When used as an input port on chip pull up resistor can be used by software 15 NEC uPD78081 A 78082 A 5 2 Clock Generator Main system clock generator is incorporated It is possible to change the minimum instruction execution time 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us at main system clock frequency of 5 0 MHz Figure 5 1 Clock Generator Block Diagram Prescaler x19 5 o 2 Clock to peripheral x20 o
21. D 13 2 0 2 0 520 0 009 1 0 0 039 G 1 0 0 039 0 08 0 003 H 0 37 009 0 015 9 097 0 16 0 007 9 0 8 T P 0 031 T P K 1 6 0 2 0 063 0 008 0 009 L 0 8 0 2 0 03175 998 0 06 0 002 M 0 177568 0 00775 003 N 0 10 0 004 P 2 7 0 106 Q 0 125 0 075 0 005 0 003 7 7 R 397 32 8 3 0 0 119 S44GB 80 3BS 50 NEC uPD78081 A 78082 A 12 RECOMMENDED SOLDERING CONDITIONS uPD78081 A and 78082 A should be soldered and mounted under the conditions recommended in the table below For detail of recommended soldering conditions refer to the information document Semiconductor Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended below consult our sales representative Table 12 1 Surface Mounting Type Soldering Conditions uPD78081GB A ooo 3B4 44 pin plastic QFP 10 x 10 mm uPD78082GB A ooo 3B4 44 pin plastic QFP 10 x 10 mm uPD78081GB A2 xxx 3B4 44 pin plastic QFP 10 x 10 mm Soldering Method Infrared reflow Soldering Conditions Package peak temperature 235 C Reflow time 30 seconds or below at 210 C or higher Number of reflow processes 3 max IR35 00 3 VPS Package peak temperature 215 C Reflow time 40 seconds or below at 200 C or higher Number of reflow processes 3 max VP15 00 3 Wave soldering Solder temperature 260 C or below Flow time 10 seconds or below Number of flow
22. DATA SHEET MOS INTEGRATED CIRCUIT uPD78081 A 78082 A NEC 8 BIT SINGLE CHIP MICROCONTROLLER DESCRIPTION The uPD78081 78082 A are members of the uPD78083 Subseries of the 78K 0 Series microcontrollers These products are produced with a more stringent quality assurance program than that of the 78081 and 78082 standard models NEC classifies these products as special products by quality grade Besides a high speed high performance CPU these microcontrollers have on chip ROM RAM ports 8 bit resolution A D converter timer serial interface interrupt control and other peripheral hardware The uPD78P083 A including a one time PROM version which can operate in the same power supply voltage range as a mask ROM version and various development tools are available The details of the functions are described in the following User s Manuals Be sure to read the documents before starting design 78083 Subseries User s Manual IEU 1407 78K 0 Series User s Manual Instructions IEU 1372 FEATURES nternal ROM and RAM Program Memory Data Memory Package Part Number ROM Internal High speed RAM 78081 8 Kbytes 256 bytes 44 pin plastic QFP 10 x 10 mm 78082 16 Kbytes 384 bytes Minimum instruction execution time can be changed from high speed 0 4 us to low speed 12 8 ports 33 8 bit resolution A D converter 8 channels Serial interface
23. Make sure to use the latest edition when starting design U11416J NEC MEMO 56 uPD78081 A 78082 A NEC uPD78081 A 78082 A MEMO 57 NEC uPD78081 A 78082 A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input level
24. P37 P50 to P57 P70 to P72 Analog Input Asynchronous Serial Clock Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock Internally Connected Interrupt from Peripherals Non connection Porto Port Port3 Port5 Port7 P100 P101 PCL RESET RxD SCK2 12 02 TI5 6 TO5 TO6 TxD Vss X1 X2 uPD78081 A 78082 A Port10 Programmable Clock Reset Receive Data Serial Clock Serial Input Serial Output Timer Input Timer Output Transmit Data Power Supply Ground Crystal Main System Clock NEC 2 BLOCK DIAGRAM P100 TI5 TO5 8 bit TIMER EVENT COUNTER 5 P101 TI6 TO6 SI2 RxD P70 SO2 TxD P71 SCK2 ASCK P72 ANIO P10 to ANI7 P17 AV pb AVss AV REF INTP1 P01 to BUZ P36 PCL P35 8 bit TIMER EVENT COUNTER 6 WATCHDOG TIMER SERIAL INTERFACE 2 A D CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL ng 78K 0 CPU ROM CORE RAM Vss PORT 0 PORT 1 PORT 3 PORT 5 PORT 7 PORT 10 00002027 SYSTEM CONTROL Remark The internal ROM and internal high speed RAM capacities depend on the product 1 078081 78082 A P01 to P10 to P17 P30 to P37 P50 to P57 P70 to P72 P100 P101 RESET X1 X2 NEC 3 PIN FUNCTIONS 3 1 Port Pins Pin Name Input Output
25. PUSH POP DBNZ HL byte laddr16 HL B addr16 1st Operand HL C laddr16 PSW DE Note Exceptr A 25 NEC uPD78081 A 78082 A 2nd Operand HL byte laddr16 HL B addr16 1st Operand HL C HL HL byte HL B HL C X C 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand laddr16 1st Operand MOVW Note sfrp saddrp laddr16 SP Note Only when rp BC DE HL 26 NEC 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR 2nd Operand sfr bit 1st Operand saddr bit PSW bit uPD78081 A 78082 A HL bit addr16 sfr bit saddr bit PSW bit HL bit 4 Call instructions Branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ 2nd Operand laddr16 1st Operand Basic instruction laddr11 addr5 addr16 Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 27 NEC uPD78081 A 78082 A 10 ELECTRICAL SPECIFICATIONS Electrical specifications of 78081 and 78082 A 1 11 Absolute Maximum Ratings Ta 25 C Parameter Test Conditions Ratings Supply volta
26. Positive power supply Ground potential Internal connection Connect directly to Vss Does not internally connected Connect to Vss It can be left open 11 NEC uPD78081 A 78082 A 3 3 Pin Circuits and Recommended Connection of Unused Pins The input output circuit type of each pin and recommended connection of unused pins are shown in Table 3 1 For the input output circuit configuration of each type refer to Figure 3 1 POO Table 3 1 Input Output Circuit Type of Each Pin Input Output Circuit Type Input Recommended Connection for Unused Pins Connect to Vss P0O1 INTP1 PO2 INTP2 Input output Connect to Vss via a resistor individually P10 ANIO to P17 ANI7 P30 to P32 P33 P34 P35 PCL P36 BUZ P37 P50 to P57 P70 SI2 RXD P71 SO2 TxD P72 SCK2 ASCK P100 TI5 TO5 P101 TI6 TO6 Input output Connect to or Vss via a resistor individually RESET AV REF AVss IC NC 12 Connect to Vss Connect to Connect to Vss Connect directly to Vss Connect to Vss It can be left open NEC uPD78081 A 78082 A Figure 3 1 Pin Input Output Circuits Schmitt triggered input with hysteresis characteristic pullup enable mun um mE un ae TT i input enable IN OUT en
27. TCSI2 Completion of serial interface channel 2 3 wire transfer INTST Completion of serial interface channel 2 UART transmission INTAD Completion of A D conversion INTTM5 Generation of matching signal of 8 bit timer event counter 5 INTTM6 Generation of matching signal of 8 bit timer event counter 6 Software BRK Execution of BRK instruction Notes 1 Default priority is the priority order when several maskable interrupt requests are generated at the same time 0 is the highest order and 9 is the lowest order 2 Basic configuration types A to D correspond to A to D in Figure 6 1 21 NEC uPD78081 A 78082 A Figure 6 1 Interrupt Function Basic Configuration 1 2 A Internal non maskable interrupt Internal bus Interrupt Priority Vector table request control address circuit generator Standby release signal B Internal maskable interrupt Internal bus Vector table address generator Priority control circuit Interrupt request Standby release signal C External maskable interrupt Internal bus Priority control External interrupt mode register INTMO INTM1 Vector table Interrupt Edge address request detector generator Standby release signal 22 NEC uPD78081 A 78082 A Figure 6 1 Interrupt Function Basic Configuration 2 2 D Software interrupt Internal
28. U11802E Assembly Language U11801J U11801E Structured Assembly Language U11789J U11789E CC78K Series C Compiler Operation EEU 656 EEU 1280 Language EEU 655 EEU 1284 CC78KO0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K 0 C Compiler Application Note Programming Know how EEA 618 EEA 1208 CC78K Series Library Source File U12322J PG 1500 PROM Programmer U11940J EEU 1335 PG 1500 Controller PC 9800 Series MS DOS Based EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Based EEU 5008 U10540E IE 78000 R U11376J U11376E 78000 010057 U10057E IE 78000 R BK EEU 867 EEU 1427 78078 0107759 010775 78083 EEU 5003 EEU 1529 SM78KO System Simulator Windows Based Reference U10181J U10181E SM78K Series System Simulator External Part User Open Interface Specifications U10092J U10092E ID78KO Integrated Debugger EWS Based Reference U11151J ID78KO Integrated Debugger PC Based Reference U11539J U11539E ID78KO0 Integrated Debugger Windows Based Guide U11649J U11649E Caution The contents of the documents listed above are subject to change without prior notice Make sure to use the latest edition when starting design 54 NEC Documents Related to Development Tools User s Manual 2 2 Document
29. Watchdog timer 1 channel Timer output 2 8 bit PWM output Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz at main system clock of 5 0 MHz Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz at main system clock of 5 0 MHz Vectored Maskable Internal 8 external 3 interrupt Non maskable Internal 1 sources Software 1 Supply voltage 1 8 5 5 V Operating ambient temperature Ta 40 to 85 C Package 44 pin plastic QFP 10 x 10 mm Caution The supply voltage and other parameters of the 78081 2 differ from those of the other models For details refer to DIFFERENCES BETWEEN 4PD78081 A AND 78081 A2 NEC uPD78081 A 78082 A CONTENTS 1 PIN CONFIGURATION Top 7 2 BLOCK DIAGRAM 9 A 10 31 POF A A 10 3 2 PINS 11 3 3 Pin Circuits and Recommended Connection of Unused Pins 12 4 MEMORY SPAGE
30. able Pm IN OUT output x disable 777 4 pullup enable H P ch data 1 1 gt gt p ch 1 0 IN OUT output disable EN ch P ch Comparator uu 7 N ch ARTT voltage input 1 enable 13 NEC uPD78081 A 78082 A 4 MEMORY SPACE The memory of the 78081 and 78082 is shown in Figure 4 1 Figure 4 1 Memory Map Data space Internal high speed RAM Net memory mmmmH mmmmH 1 FFFFH Special function registers SFR 256 x 8 bits FFOOH FEFFH General purpose registers FEEOH 32 x 8 bits FEDFH nnnnH Program area 1000H OFFFH CALLF entry area 0800H 07FFH Use prohibited Program area 0080H nnnnH 1 007FH nnnnH CALLT table area 0040H Program g Internal ROM Note 003FH memory space Vector table area 0000H oa Note The internal ROM and internal high speed RAM capacities depend on the product See the following table 14 Internal ROM Last Address Internal High speed RAM Start Address Part Number nnnnH mmmmH 78081 78082 NEC uPD78081 A 78082 A 5 PERIPHERAL HARDWARE FUNCTIONS 5 1 Ports Input output ports are classified into two types e CMOS input P00 1 e CMOS input output P01 to Port 1 Port Port
31. ais 100 pin uPD780228 ra The I O and FIP C D of the 78044 were enhanced Display output total 48 80 pin HPD78044H N ch open drain input output was added to the 78044 Display output total 34 80 pin Basic subseries for driving FIP Display output total 34 LCD drive 100 pin SIO of the 78064 was enhanced and ROM and RAM were expanded 100 pin EMI noise reduction version of the 78064 100 pin Basic subseries for driving LCDs On chip UART IEBus supported 80 pin EMI noise reduction version of the uPD78098 80 pin The IEBus controller was added to the uPD78054 Meter control 80 pin 7 uPD780973 On chip automobile meter driving controller driver LV 64 pin 7 On chip PWM output LV digital code decoder Hsync counter Note Under planning NEC uPD78081 A 78082 A The following table shows the differences among subseries functions ROM i bit 10 bit 8 bi Serial Interface MIN Subseries Name Capacity 8 bi bi Value Control wPD78075B 32 K to 40K 3ch UART 1ch uPD78078 48 60 K 1 78070 1 780058 24 60 K 3ch time division UART 1ch 78058 48 60 K Sch UART 1ch 1 78054 16 K to 60 K uPD780034 8 K to 32 Sch UART 1ch uPD780024 time division 3 wire 1ch 78014 2ch uPD78018F 8 60 K uPD78014 uPD780001 1ch uPD78002 Available ch CAE 1ch
32. ce module FD78K0 Notes 1 2 Fuzzy inference debugger Notes 1 Based on PC 9800 Series MS DOS 2 Based on IBM PC AT and its compatibles PC DOS IBM DOS MS DOS 3 Based on HP9000 Series 300 HP UX 4 Based on HP9000 Series 700 HP UX SPARCstation SunOS and EWS4800 Series EWS UX V 5 Based on IBM PC AT PC DOS IBM DOS MS DOS Windows Remark Please refer to the 78K 0 Series Selection Guide U11126E for information on the third party development tools 53 NEC APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document Name 78083 Subseries User s Manual uPD78081 A 78082 A Document No Japanese U12176J English IEU 1407 78081 78082 A Data Sheet U12436J This document 7 Data Sheet U12175J U12175E 78K 0 Series User s Manual Instructions U12326J IEU 1372 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 78083 Subseries Special Function Register Table IEM 5599 78K 0 Series Application Note Fundamental III Documents Related to Development Tools User s Manual 1 2 Document Name RA78K Series Assembler Package Operation IEA 767 U10182E Document No Japanese EEU 809 English EEU 1399 Language EEU 815 EEU 1404 RA78K Series Structured Assembler Preprocessor RA78KO Assembler Package Operation EEU 817 U11802J EEU 1402
33. ectrical specifications of uPD78081 A2 7 10 AC Timing Test Points excluding X1 Input 0 8 0 8 DING Be est points 0 2 Vov Clock Timing Voo 0 2 V X1 Input 0 4 V TI Timing TI5 16 45 NEC Electrical specifications of 78081 2 8 10 Serial Transfer Timing 3 wire serial I O mode SCK2 512 502 tkcy1 2 uPD78081 A 78082 A UART mode external clock input ASCK gt tkL1 2 2 tre 2 2 tksn 2 lt Input data A D Converter Characteristics TA 40 to 125 C AVpp 5 V 106 AVss Vss 0 V Parameter Resolution Conditions Overall error Note 4 5 V lt AVrer Conversion time tconv 23 8 Sampling time 12 fxx Analog input voltage Vian AVss Reference voltage AVREF 4 5 Resistance between AVrer and AVss 4 Note Overall error excluding quantization error 1 2158 It is indicated a ratio to the full scale value Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 46 NEC uPD78081 A 78082 A Electrical specifications of 78081 2 9 10 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 125 C Parameter Conditions
34. ge 0 3 to 7 0 0 3 to 0 3 0 3 to 0 3 0 3 to 40 3 Input voltage 0 3 to 0 3 Output voltage 0 3 to 0 3 Analog input voltage P10 to P17 Analog input pins AVss 0 3 to AVaer 0 3 Output current high Per pin 10 Total of P10 to P17 P50 to P54 P70 to P72 15 P100 P101 Total of PO1 to P30 to P37 P55 to P57 15 Output current low Per pin Peak value 30 r m s value 15 Total of P50 to P54 Peak value 100 r m s value 70 Total of P55 to P57 Peak value 100 r m s value 70 Total of P10 to P17 P70 to P72 Peak value 50 P100 P101 r m s value 20 Total of P01 to P03 P30 to P37 Peak value 50 r m s value 20 Operating ambient temperature 40 to 85 Storage temperature 65 to 150 Note The r m s value should be calculated as follows r m s value Peak value x Duty Caution If the absolute maximum rating of even one of the above parameters is exceeded the quality of the product may be degraded The absolute maximum ratings are therefore the rated values that may if exceeded physically damage the product Be sure to use the product with all the absolute maximum ratings observed Capacitance Ta 25 C Voo Vss 0 ume Input capacitance f 1 MHz Unmeasured pins returned to 0 V capacitance f 1 MHz to to P17 P30 to Unmeasured p
35. gram fxx fxx 2 fxx 2 fxx 23 fxx 2 fxx 25 fxx 2 H fxx 2 Output control circuit Synchronization circuit PCL P35 Selector 5 5 Buzzer Output Control Circuit This circuit can output clocks of the following frequencies that can be used for driving buzzers 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz at main system clock frequency of 5 0 MHz Figure 5 5 Buzzer Output Control Circuit Block Diagram 29 5 2 0 Output control BUZ P36 D circuit fxx 2 18 NEC uPD78081 A 78082 A 5 6 A D Converter The A D converter consists of eight 8 bit resolution channels A D conversion can be started by the following two methods Hardware starting Software starting Figure 5 6 A D Converter Block Diagram Series resistor string po AV ANIO P10 TE i ve 1 1 REF ANI1 P11 Sample amp hold circuit TE ANI2 P12 m 5 5 oltage comparator 001 ANI3 P13 g L 9770 d T do 4 1 at ANI4 P14 IL Ks 5 15 TE ANIG P16 X T AVss ANI7 P17 Successive approximation EM register SAR Edge Control gt INTP3 A D conversion result register ADCR Internal bus 19 NEC uPD78081 A 78082 A 5 7 Serial Interface There is one on chip
36. hardware fex 2 22 STOP 5 Standby 8 control CPU clock E circuit fceu 5 3 Timer Event Counter There are the following three timer event counter channels 8 bit timer event counter 2 channels Watchdog timer 1 channel Table 5 2 Types and Functions of Timer Event Counters 8 bit Timer Event Counter 5 6 Watchdog Timer Type Interval timer 2 channels 1 channel External event counter 2 channels Function Timer output 2 outputs PWM output 2 outputs Square wave output 2 outputs Interrupt request 2 16 NEC uPD78081 A 78082 A Figure 5 2 8 Bit Timer Event Counter 5 6 Block Diagram 8 bit compare register gt INTTMn 2 29 Output aodio TO9 PtoorTI5 2 8 bit timer register n circuit TO6 P101 TI6 xx 9 TMn TI5 P100 TO5 0 TI6 P101 TO6 n 5 6 Figure 5 3 Watchdog Timer Block Diagram Prescaler fxx fxx fxx fxx 25 26 27 INTWDT maskable interrupt request RESET 8 bit counter Selector INTWDT non maskable interrupt request 17 NEC uPD78081 A 78082 A 5 4 Clock Output Control Circuit This circuit can output clocks of the following frequencies 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz at main system clock frequency of 5 0 MHz Figure 5 4 Clock Output Control Circuit Block Dia
37. in the vicinity of lines through which a high fluctuating current flows Always keep the ground point of the capacitor of the oscillation circuit at the same potential as Vss Do not connect the ground pattern through which a high current flows Do not extract signals from the oscillation circuit 29 NEC Electrical specifications of uPD78081 A and 78082 A 3 11 DC Characteristics Ta 40 to 85 C 1 8 to 5 5 V Parameter Input voltage high Test Conditions P10 to P17 P30 to P32 P35 to P37 P50 to P57 P71 2 7 to 5 5 V uPD78081 A 78082 A 0 7 0 8 to P33 P34 P70 P72 P100 P101 RESET 2 7 to 5 5 V 0 8 0 85 X1 X2 2 7 to 5 5 V 0 5 Input voltage low P10 to P17 P30 to P32 P35 to P37 P50 to P57 P71 2 7 to 5 5 V to P33 P34 P70 P72 P100 P101 RESET 2 7 to 5 5 V X1 X2 2 7 to 5 5 V Output voltage high 4 5 to 5 5 V 1 mA 100 uA Output voltage low P50 to P57 2 0 to 4 5 V lo 10 mA 4 5 to 5 5 V lo 15 mA P01 to to P17 P30 to P37 P70 to P72 P100 P101 4 5 to 5 5 V lo 1 6 mA lo 400 uA Input leak current high Vin to P10 to P17
38. ins P37 P50 to P57 P70 to P72 returned to 0 V P100 P101 Remark Unless otherwise specified alternate function pin characteristics are the same as port pin characteristics 28 NEC uPD78081 A 78082 A Electrical specifications of 78081 and 78082 A 2 11 Main System Clock Oscillator Characteristics Ta 40 to 85 C 1 8 to 5 5 Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency fx Note 1 Test Conditions Oscillation voltage range Oscillation stabilization time Note 2 After came to MIN of oscillation voltage range Crystal resonator External clock uPD74HCUO4 Oscillation frequency fx Note 1 Oscillation stabilization time Note 2 X1 input frequency fx Note 1 4 5 to 5 5 V X1 input high low level widths tx Notes 1 Only the oscillator characteristics are shown For the instruction execution time refer to AC Characteristics 2 Time required for oscillation to stabilize after a reset or the STOP mode has been released Caution Whenusing the oscillation circuit of the main system clock wire the portion enclosed in broken lines in the figures as follows to avoid adverse influence on the wiring capacitance Keep the wiring length as short as possible Do not cross the wiring over other signal lines Do not route the wiring
39. ion Main System Clock fxx fx Operation 60 Operation 10 S Guaranteed X Operation 5 Range 5 Guarantee m A Range 2 0 9 5 1 0 0 5 0 4 1 2 3 4 5 6 1 2 3 4 5 6 Power Supply Voltage V Power Supply Voltage V 32 NEC Electrical specifications of 78081 and 78082 A 6 11 2 Serial Interface TA 40 to 85 C 1 8 to 5 5 V a 3 wire serial I O mode SCK2 Internal clock output Parameter SCK2 cycle time Conditions 4 5 lt Voo lt 5 5 V uPD78081 A 78082 A 2 7 V lt lt 4 5 V 2 0 V lt Voo lt 2 7 V 3 200 4 800 SCK2 high low level widths 4 5 to 5 5 V tkcvi 2 50 tkcvi 2 100 SI2 setup time to SCK27 4 5 V lt Voo lt 5 5 V 100 2 7 V lt Voo lt 4 5 V 150 2 0 V lt Voo lt 2 7 V 300 400 SI2 hold time from SCK27 400 SO2 output delay time from SCK2L Note C is the load capacitance of SCK2 and SO2 output lines b 3 wire serial mode SCK2 External clock input Parameter SCK2 cycle time C 100 pF Note Conditions 4 5 V lt Voo lt 5 5 V
40. ipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M4 96 5
41. n HALT mode 3 5 MHz Nete2 5 0 MHz crystal oscillation HALT mode 2 5 MHz STOP mode Notes 1 Notincluding AVner and AVpp currents or port currents including current flowing into on chip pull up resistors 2 fx 2 operation when oscillation mode selection register OSMS is set to 3 High speed mode operation when processor clock control register PCC is set to 00H Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 Unless otherwise specified alternate function pin characteristics are the same as port pin characteristics 41 NEC Electrical specifications of 78081 2 4 10 AC Characteristics 1 Basic Operation Ta 40 to 125 C 5 V 10 Parameter Cycle time minimum instruction execution time Test Conditions fxx fx 2 Note uPD78081 A 78082 A TI5 TI6 input frequency TI5 TI6 input high low level widths tri Interrupt request input high low level widths TINTH INTL RESET low level width tRsL Note When oscillation mode selection register OSMS is set to OOH Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 42 Main System Clock fxx fx 2 Operation Cycle Time Tcv zs Tcv vs
42. omputers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 800 366 9782 Fax 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1 Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 253 831 1 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 719 2377 Fax 02 719 5951 NEC do Brasil S A Sao Paulo SP Brasil Tel 011 889 1680 Fax 011 889 1689 J96 8 59
43. put mode The on chip pull up resistor is automatically disabled 10 NEC 3 2 Non port Pins Pin Name Input Output uPD78081 A 78082 A Function External interrupt request input by which the active edge rising edge falling edge or both rising and falling edges can be specified After Reset Shared by P03 Input Serial interface serial data input P70 RxD Output Serial interface serial data output P71 TxD Input Output Serial interface serial clock input output P72 ASCK Input Asynchronous serial interface serial data input P70 SI2 Output Input Asynchronous serial interface serial data output Asynchronous serial interface serial clock input 71 502 P72 SCK2 Input External count clock input to 8 bit timer TM5 External count clock input to 8 bit timer TM6 P100 TOS P101 TO6 TO6 Output 8 bit timer TM5 output 8 bit timer TM6 output P100 TI5 P101 TI6 PCL Output Clock output for main system clock trimming P35 BUZ Output Buzzer output P36 ANIO to ANI7 Input A D converter analog input P10 to P17 AV REF Input A D converter reference voltage input A D converter analog power supply Connected to AVss A D converter ground potential Connected to Vss RESET System reset input Main system clock oscillation crystal connection
44. rents or port currents including current flowing into on chip pull up resistors fx 2 operation when oscillation mode selection register OSMS is set to fxx 2 fxoperation when oscillation mode selection register OSMS is set to 01H High speed mode operation when processor clock control register PCC is set to 00H Low speed mode operation when processor clock control register PCC is set to 04H oP en Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 31 NEC uPD78081 A 78082 A Electrical specifications of 78081 and 78082 A 5 11 AC Characteristics 1 Basic Operation Ta 40 to 85 C 1 8 to 5 5 V Parameter Test Conditions Cycle time fxx fx 2 Note t 2 7 to 5 5 V minimum instruction execution time fxx fx Note 2 3 5 V lt Voo lt 5 5 V 2 7 V lt lt 3 5 V TI5 TI6 4 5 to 5 5 V input frequency TI5 TI6 input high 4 5 to 5 5 V low level widths Interrupt request input high 2 7 to 5 5 V low level widths RESET low level width Voo 2 7 to 5 5 V Notes 1 When oscillation mode selection register OSMS is set to OOH 2 When OSMS is set to 01H Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Tcv vs Tcv vs Main System Clock fxx fx 2 Operat
45. s of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Produc 58 tion process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed imme diately after power on for devices having reset function NEC uPD78081 A 78082 A Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host c
46. ts 0 2 ax ud 0 2 Clock Timing MIN X1 Input Vis MAX TI Timing TI5 TI6 35 NEC uPD78081 A 78082 A Electrical specifications of 78081 and 78082 A 9 11 Serial Transfer Timing 3 wire serial I O mode tkcy1 2 e tkL1 2 tkH1 2 at a tre 2 SCK2 tsik1 2 tksi1 2 lt lt 12 02 UART mode external clock input ASCK A D Converter Characteristics Ta 40 to 85 C AVpp Voo 1 8 to 5 5 V AVss Vss 0 V Parameter Conditions Resolution Overall error Note 2 7 V AVner 1 8 V lt AVrer lt 2 7 V Conversion time 2 0 lt lt 55V 19 1 1 8 V lt AVop lt 2 0 V 38 2 Sampling time 12 fxx Analog input voltage Vian AVss Reference voltage AVREF 1 8 Resistance between AVner and AVss Rarer 4 Note Overall error excluding quantization error 1 2LSB It is indicated as a ratio to the full scale value Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 36 NEC uPD78081 A 78082 A Electrical specifications of 78081 and 78082 A 10 11 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Parameter Conditions Data retention power supply voltage Data retention power 1 8 V suppl
47. use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based ona customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equ
48. versions of the uPD78078 100 pin 7 lt Serial I O of the 78078 was enhanced and only selected functions are provided 80 pin uPD780058 uPD780058Y Ne 5 Serial I O of the 78054 was enhanced EMI noise reduction version 80 pin PD78058F uPD7B05GF Y EMI noise reduction version of the 78054 80 pin 7 UART and D A converter were added to the 78014 and I O was enhanced 64 pin 22 HPD780034 D780034Y 7 An A D converter of the 780024 was enhanced 64 pin 7 uPD780024 uPD780024Y Serial I O of the 78018 was enhanced EMI noise reduction version 64 pin 77 uPD780141 i MPG __ noise reduction version of the 78018 64 pin uPD78018F 78018 Low voltage 1 8 V operation versions of the 78014 with several ROM and RAM capacities available 64 pin An A D converter and 16 bit timer were added to the 78002 64 pin uPD780001 An A D converter was added to the 78002 64 pin uPD78002 Basic subseries for control 42 44 uPD78083 On chip UART capable of operating at a low voltage 1 8 V _ Inverter control 64 pin nPD780964 An A D converter of the 780924 was enhanced 64 pin uPD780924 On chip inverter control circuit and UART EMI noise reduction version FIP drive 100 pin P0780208 The I O and FIP C D of the PD78044F were enhanced Display output total 53
49. vices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications DIFFERENCES BETWEEN 4PD78081 AND 78082 AND 78081 AND 78082 A m Part Number uPD78081 78082 uPD78081 A 78082 A Quality grade Standard Special Package 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm 44 pin plastic QFP 10 x 10 mm DIFFERENCES BETWEEN 78081 AND 78081 A2 Part Number uPD78081 A uPD78081 A2 Supply voltage 1 8 5 5 V Voo 5 V 10 Minimum instruction execution 0 4 us at 5 MHz 0 57 us at 7 MHz time Operating ambient temperature Ta 40 to 85 C Ta 40 to 125 C Remark In addition to the above parameters the supply current also differs For details refer to 10 ELECTRICAL SPECIFICATIONS NEC uPD78081 A 78082 A 78K 0 SERIES DEVELOPMENT The following shows the 78K 0 Series products development Subseries names are shown inside frames ff Products in mass production gt Products under development Y subseries products are compatible with 12C bus Control 100 pin EMI noise reduction version of the 78078 100 pin uPD78078 1 078078 A timer was added the 78054 and the external interface function was enhanced 100 pin uPD78070A uPD78070AY ROM less
50. y current Release signal set time Oscillation stabilization Release by RESET 2 7 fx wait time Release by interrupt request Note Note In combination with bits 0 to 2 OSTSO to OSTS2 of oscillation stabilization time select register OSTS selection of 2 2 fxx and 2 4 fxx to 2 fxx is possible Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Data Retention Timing STOP mode release by RESET Internal reset operation 1 HALT mode 1 m STOP mode ee a Operating mode Data retention mode STOP instruction execution RESET Y Data Retention Timing Standby release signal STOP mode release interrupt request signal HALT mode STOP mode gt 4 Operating mode Data retention mode A tSREL gt STOP instruction execution Standby release signal interrupt request 37 NEC Electrical specifications of 78081 and 78082 A 11 11 Interrupt Request Input Timing INTP1 to INTP3 RESET Input Timing 38 uPD78081 A 78082 NEC uPD78081 A 78082 A Electrical specifications of 78081 2 1 10 Absolute Maximum Ratings Ta 25 C Parameter Test Conditions Ratings Supply voltage 0 3 to 7 0
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