Technical Information Manual
Contents
1. is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 6 NPO CHO THRESHOLD CHO IN CH1 THRESHOLD CH1 IN LOCAL TRG 0 LOCAL TRG 1 TRIGGER Coinc lev 1 TRIGGER Coinc lev 0 Fig 3 14 Local trigger relationship with Coincidence level 3 5 2 Trigger distribution The OR of all the enabled trigger sources after being synchronised with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel GPO connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal Data transfer capabilities The board can be accessed by using software drivers and libraries developed by CAEN Single 16 32 register read write cycles multi read cycles and block transfers are supported by the provided library please consult the relevant documentation for details Sustained readout rate is up to 60 MB s for optical l2. Channel Enable Mask 0x8120 r w Bit reserved 1 Channel 3 enabled 1 Channel 2 enabled Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 40 CAEN is fe PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 1 0 Channel 1 disabled 1 Channel 1 enabled EN 0 Channel O disabled 1 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running 4 25 ROC FPGA Firmware Revision 0x8124 r Bt Function X9 31 16 Revision date in Y M DD format Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 4 26 Downsample Factor 0x8128 r w This register allows to set N sampling frequency will be divided by N 1 Downsampling is enabled via Acquisition Control register see 8 4 17 4 27 Event Stored 0x812C r Bit Function This register contains the number of events currently stored in the 31 0 Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 4 28 Board Info 0x8140 r Bit 1 FUNGtiOn J 23 16 Number of channels DT5724 0x04 DT5724A 0x02 15 8
3. Acquisition RUN allows to RUN STOP Acquisition 00 REGISTER CONTROLLED RUN MODE 01 GPI CONTROLLED RUN MODE 10 GPI GATE MODE 11 reserved Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected Bits 1 0 descritpion 00 REGISTER CONTROLLED RUN MODE multiboard synchronisation via S IN front panel signal RUN control start stop via set clear of bit 2 GATE always active Continuous Gate Mode or Downsample Mode Continuous Gate Mode can be used only if Channel gate mode see 4 12 is set in Window Mode Downsample Mode can be used prior DOWNSAMPLE FACTOR register see S 4 26 valid setting 0 01 GPI CONTROLLED RUN MODE Multiboard synchronisation via GPI front panel signal GPl works both as SYNC and RUN START command GATE always active Continuous Gate Mode or Downsample mode Continuous Gate Mode Gate always active to be used only if Channel Gate Mode CHANNEL Configuration Register is set to Window Mode Downsample Mode it is set via DOWNSAMPLE ENABLE and a value 70 at DOWNSAMPLE FACTOR register 10 GPI GATE MODE Mutltiboard synchronisation is disabled GPI works as Gate signal set clear of RUN STOP bit 4 18 Acquisition Status 0x8104 r Board ready for acquis
4. Fig 3 5 Zero Suppression based on the amplitude NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 21 CAE NO is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 NPO 3 4 1 3 Zero Length Encoding ZLE Zero Length Encoding allows to transfer the event in compressed mode discarding either the data under the threshold set by the User positive logic or the data over the threshold set by the User negative logic With Zero length encoding it is also possible to set Nigx LOOK BACK the number of data to be stored before the signal crosses the threshold and or Nirwo LOOK FORWARD the number of data to be stored after the signal crosses the threshold see 4 3 In this case the event of each channel has a particular format which allows the construction of the acquired time interval Total size of the event total number of transferred data Control word stored valid data if control word is good Control word stored valid data if control word is good The total size is the number of 32 bit data that compose the event including the size itself The control word has the following format Bit jFuncion 1 0 skip en 3020 o O 20 0 stored skipped words If the control word type is good then it will be followed by as many data as those
5. N N4 Ns words with samples over threshold 3 If the algorithm works in positive logic and Niek 0 N lt Nyrwo lt Ns then the readout event is N s 3 control words 1 size Skip N Good N No N3 Na Ni Fwp N words with samples over threshold Skip Ns Nyrwo 4 If the algorithm works in positive logic and NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 26 CAEN s for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 N lt Niek Ni Nirwp 0 Fig 3 11 Example with positive logic and overlapping Ni BK then the readout event is N s N 4 4 control words 1 size Skip Ni NiBk Good N Ni BK No N 2 words with samples over threshold Good N 4 N3 Na N 4 words with samples over threshold Skip N5 N B In this case there are two subsequent GOOD intervals 5 If the algorithm works in positive logic and 0 lt Niek lt Ni Nirwp lt Ns Niek Nyrwo 2 N3 then the readout event is N s Ni 4 control words 1 size Skip N NiBk Good N s Niek N2 Niewo N words with samples over threshold Good N Ns Nyrwo Na Nyrwo N 4 words with samples over threshold Skip Ns Nyrwo N B In this case there are two subsequent GOOD intervals These examples are reported w
6. NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 43 CAEN is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 5 Installation 5 1 Power ON sequence To power ON the board follow this procedure 1 connect the 12V dc power supply to the DT5724 2 power up the DT5724 5 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration 5 3 Firmware upgrade The DT5724 firmware is stored onto on board non volatile memory CAEN provides a firmware upgrade tool that can be used with either USB or optical link paths Please download the software package application notes and user manual available at http www caen it nuclear product php mod DT5724 then follow the instructions for installation and usage WARNING in case of programming failures the board hosts a backup image of factory firmware Please contact CAEN at support frontend caen it for instuctions in order to restore the backup image Once the board is successfully powered with backup firmware the standard firmware image can be reprogrammed NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 44
7. zero length encoding ZLE 0011 full suppression based on the amplitude ZS AMP Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 36 CAE NO Is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 13 4 14 4 15 4 16 NPO 15 8 reserved 7 0 Analog monitor disabled 1 Analog monitor enabled 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local trigger either on channel over or under threshold see S 4 3 and 4 6 0 Memory Random Access 1 Memory Sequential Access 3 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled reserved 0 Trigger Overlapping Not Enabled 1 1 Trigger Overlapping Enabled Allows to handle trigger overlap see 3 3 2 0 Window Gate 1 Single Shot Gate Allows to handle samples validation see S 3 3 1 This register allows to perform settings which apply to all channels It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following S 4 13 and S 4 14 Default value is Ox10 Channel Configuration Bit Set 0x8004 w Bits set to 1 means that the corresponding bits in the Channel 7 0 Configuration register are set t
8. 53 2 Acquisition Triggering Samples and Events sees nnne 16 ROSA MEME GIC OUR ZUR bab dela pik l a de l e ed e e ek l kipa e ak e io et a ap a a ek ka ai ee 18 3 3 3 I CIE SPU CC OE EE EE EE a a kk OE RE OE OE ki a a ka pasa HORE 18 de Heide oes diya bata n ei oto pa NE a ei ke 18 NG NNN 18 oa TN 18 3 3 4 Memory FULL NNN eeddie 20 3A ZERO SUPPRESSION eds ee se Se at eo a a a dri ee e koe e lta Z N ae EG Ge ai 20 3 4 1 Zero Suppression Algor hm decis Ned ek atio obe Se se Eng Reb rods ME e eda EG be es EE ge dako sida ae ord ta Pope ask Unas 20 3 4 1 1 Full Suppression based on the integral of the signal eeeesseeesessseeeeeeeeeeeeneen nnne 20 3 4 1 2 Full Suppression based on the amplitude of the signal ee RE Ee ee AR RR EE ee ee ee 20 41 Zero TR Ava t aM Un euer a Bor SEE G l en REM RU datio E a R 22 3 4 2 Zero Suppression Example iii ee ee esee hne ee ee ee ee hne ess ee ee neis ee ee ee Ee ee sse ee 24 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 3 CAEN Is for Discos PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 9 TRIGGER MANAGEMENT sparre ENE E ae does vas RNEER ka 28 3 5 1 Loes 28 VL TENNE 29 502 TESE REE EEE s n Dan S 30 3 6 DATA TRANSFER CAPABILITIES eesssssssvsssssssssssssssssssssssssssssssnsssssssssssssnsnsssssnssssssnn
9. ZS AMP bits 20 0 allow to set the number Ns of subsequent samples which must be found over under threshold depending on the used logic necessary to validate the event if this field is set to 0 it is considered 1 With Zero length encoding ZLE bit 31 16 allows to set read Ni Bk the number of data to be stored before the signal crosses the threshold bit 15 0 allows to set read Ni rwp the number of data to be stored after the signal crosses the threshold see 3 4 and S 4 12 Channel n Threshold 0x1n80 r w Bit 13 0 Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth couples of samples at least local trigger is delayed of Nth quartets of samples with respect to input signal This register allows to set Vth LSB input range 14bit see also S 3 5 1 Channel n Over Under Threshold 0x1n84 r w Bit 11 0 Number of Data under over Threshold Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth quartets of samples at least local trigger is delayed of Nth quartets with respect to input signal This register allows to set Nth see also S 3 5 1 Filename Number of pages Page CAE NO is for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MU
10. indicated in the stored skipped words field if the control word type is skip then it will be followed by a good control world unless the end of event is reached IMPORTANT NOTE the maximum allowed number of control words is 62 14 for piggy back release 0 6 and earlier therefore the ZLE is active within the event until the 14 transition between a good and a skip zone or between a skip and a good zone All the subsequent samples are considered good and stored The following figure shows an example of Zero Length Encoding the algorithm has positive logic CHO CH3 are enabled for acquisition therefore the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 3 3 3 for data format details Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 20 CAEN Tools far Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 Settings CH Enable Mask OxF Channel Configuration bits 19 16 0x2 ZLE mode Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 0x0 Channel n Z8 THRES bit 31 0 Channel n Z8 THRES bits 13 0 Threshold Channel n Z8 NSAMP bits 31 16 NIfwd Channel n Z8 NSAMP bits 15 0 Nibk Threshold rt Threshold a ttt ty LITILILILLLLLLILTLTS FJ JJ TE Seven ATITIITII L LI
11. DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 2 5 Other components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Colour _ Function 0 0 0 0 0 00 O NM j gren Standard selection for CLK GPO TRG IN GPL 4 USB green Data transfer activity n PLL LOCK The PLL is locked to the reference clock PLL BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL_LOCK LED is turned off green RUN bit set see 4 18 Triggers are accepted Triggers are accepted 4 DRDY Event data depending on acquisition mode are present in the Output Buffer BUSY All the buffers are full NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 13 Tools far Discovery n Document type User s Manual MUT PRELIMINARY Title Revision date Revision Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 Technical specifications table Table 2 3 Mod DT5724 technical specifications Desktop module 154x50x164 mm WxHxD Weight 680 gr 4 channels MCX 50 Ohm Single ended Input range 2 25 Vpp Bandwidth 40 MHz Programmable DAC for Offset Adjust x ch adjustment range 1 125V Resolution 14 bit Sampling rate 10 to 100 MS s simultaneously on each channel multi board synchronization Three operating modes PLL mode internal reference 50 MHz loc oscil
12. User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampling trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an external via front panel signal or an internal via local oscillator source in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway DT5724 uses an integrated phase locked loop PLL and clock distribution device AD9520 It is used to generate the sampling clock for ADCs SAMP CLKO SAMP CLK1 and trigger logic synchronization clock TRG CLK Both clocks can be generated from the internal oscillator or from external clock input CLK IN By default board uses the internal clock as PLL reference REF CLK External clock can be selected by register access AD9520 configuration can be changed and stored into non volatile memory AD9520 configuration change is primarly intended to be used for external PLL reference clock frequency change DT5724 locks to an external 50 MHz clock with default AD9520 configuration Please contact CAEN support
13. frontend caen it for more information and configuration tools Refer also to AD9520 data sheet for more details http www analog com UploadedFiles Data Sheets AD9520 pdf 3 2 1 Trigger Clock TRG CLK signal has a frequency equal to 72 of SAMP CLK therefore a 2 samples uncertainty occurs over the acquisition window 3 3 Acquisition Modes 3 3 1 Acquisition run stop The acquisition can be started in two ways according to Acquisition Control register Bits 0 setting see S 4 17 setting the RUN STOP bit bit 2 in the Acquisition Control register bits 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE driving GPI signal high bit O of Acquisition Control must be set to 1 GPI CONTROLLED RUN MODE eH acquisition is stopped either resetting the RUN STOP bit bit 2 in the Acquisition Control register bit O of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE driving GPI signal low bit O of Acquisition Control set to 1 GPI CONTROLLED RUN MODE 3 3 2 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to storea Trigger Time Tag TTT the value of a 32 bit counter which steps on with the sampling clock and represents a time reference NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 16 CAEN PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724
14. into the Configuration RAM where it is available for readout NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 34 CAEN PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 3 4 4 4 5 4 6 NPO 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 35 Channel n ZS THRES 0x1n24 r w Bt 1 1 3 Functin X A4MV 31 0 Positive Logic 1 Negative Logic Threshold Weight used in Full Suppression based on the integral 30 only 0 Fine threshold step Threshold Z8 THRES 29 0 1 Coarse threshold step Threshold Z8 THRES 29 0 64 With Full Suppression based on the integral the 30 LSB value represents the value depending on bit 30 to be compared with sum of the samples which compose the event and see if it is over under threshold depending on the used logic 29 0 With Full Suppression based on the amplitude the 14 LSB represent the value to be compared with each sample of the event and see if it is over unedr threshold depending on the used logic With Zero Length Encoding the 14 LSB represent the value to be compared with each sample of the event and see if it is good or skip type see 8 3 4 and 8 4 12 4 4 Channel n ZS NSAMP 0x1n28 rw a stst lt CSsts n ZS NSAMP 0x1n28 r w With Full Suppression based on the amplitude
15. maximum number of samples per block NS 512K Nblocks Smaller Ni oc values can be achieved by writing the number of locations Nioc into the Custom Size register see S 4 16 Nioc 0 means default size events i e the number of memory locations is the maximum allowed Nioc N1 with the constraint O N1 72NS means that one event will be made of 2 N1 samples 3 3 3 Event structure An event is structured as follows Header 4 32 bit words Data variable size and format The event can be readout either via USB or Optical Link data format is 32 bit long word therefore each long word contains 2 samples 3 3 3 1 Header It is composed by four words namely Size of the event number of 32 bit long words Bit24 data format 0 normal format 1 Zero Length Encoding data compression method enabled Channel Mask 71 channels participating to event ex CH2 and CH3 participating Ch Mask OxC this information must be used by the software to acknowledge which channel the samples are coming from Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see S 4 16 Trigger Time Tag It is a 32 bit counter 31 bit count 1 overflow bit which is reset as acquisition starts and is incremented at each sampling clock hit It is the trigger time reference 3 3 3 2 Samples Stored samples data from masked channels are not read 3 3 3 3 Event format ex
16. of trigger and readout rate causes a memory full situation all acquisition buffers are used and they have not been read yet In order to exploit the maximum readout rate allowed by the communication path USB or optical link it is suggested to perform block transfer read cycles of at least N X data with N set to its maximum value whether possible READOUT EVENTS BUFFERS Block size 1024 bytes Slave Terminated Transfer Flag enabled Block Transfer BLT size 16384 bytes N 4 Fig 3 15 Example of block transfer readout Optical Link and USB access The board houses a USB2 0 compliant port providing a transfer rate up to 30 MB s and a daisy chainable Optical Link able to transfer data at 80 MB s the latter allows to connect up to eight DT5724 to a single Optical Link Controller a standard PC equipped with the PCI card CAEN Mod A2818 The A2818 is a 32 bit 33 MHz PCI card the communication path uses optical fiber cables as physical transmission line see S 1 1 A new type of PCle communication card A3818 with up to four optical links will be soon available contact infoQcaen it Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 3 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 AY2705 and AY2720 have a duplex connector on the A2818 side and two simplex connectors on
17. signal does not exceed the programmed threshold for Ns subsequent data at least Ns is programmable see S 4 4 It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the signal does not remain under the programmed threshold for Ns subsequent data at least The following figure shows an example of Full Suppression based on the amplitude of the signal the algorithm has positive logic CHO CH3 are enabled for acquisition therefore Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 20 CAEN Q PRELIMINARY Tools far Discovery Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 3 3 3 for data format details Settings Channel Configuration bits 19 16 0x3 Z8 AMP mode CH Enable Mask OxF Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 0x0 Channel n Z8 THRES bit 31 0 Channel n Z8 THRES bits 13 0 Threshold Channel n Z5 NSAMP bits 31 0 Ns Threshold Threshold Threshold OUTPUT DATA 31 30 29 28 27 26 25 24 23 2221 2019 18 1716 1511413 12111098 71615413 2 1 0 0HO VIVG
18. the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher The Optical Link allows to perform read Single data transfer and Block transfers and write Single data transfer operations See also the web page http www caen it nuclear product php mod A2818 Control Register bit 3 see 4 30 allows to enable the module to broadcast an interrupt request on the Optical Link a bit mask see Libraries Demos and Software tools documentation allows to enable the corresponding A2818 s to propagate the interrupt on the PCI bus as a request from the Optical Link is sensed The module can be accessed either via Optical Link or USB USB and Optical Link simultaneous access is anyway not recommended The following diagram shows how to connect DT5724 modules to the Optical Link Link PC side digitizer side BdNum 0 A2818 H EU DT57XX 0 0 PC side 1 1 N Fig 3 16 Optical Link daisy chain 3 8 1 Software tools CAEN provides Libraries Demos and Software tools for Windows and Linux The packages developed so far include Libraries for National Instruments LabVIEW and C C Demo programs in source code C C Windows and Linux and as a starting point for the development of user specific applications Software Tools firmware upgrade Module configuration Windows 2000 XP Vista and Linux supported NPO Filename Number of pages P
19. 33 Interrupt Event Number OxEF18 r w INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 4 34 Block Transfer Event Number OXEF1C r w This register contains the number of complete events which has to Hom be transferred via Block Transfer see S 3 7 4 35 Scratch OxEF20 r w ig 1 0 Scratch to be used to write read words for test purposes 4 36 Software Reset OXEF24 w ig 1 0 A write access to this location allows to perform a software reset 4 37 Software Clear OXEF28 w B 31 0 A write access to this location clears all the memories NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 42 CAEN is fe PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 38 Flash Enable OxEF2C r w Bit Function AJ440 Y O 0 Reserved for Firmware upgrade tool 4 39 Flash Data OxEF30 r w Bit 31 4 Funtin J 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 4 40 Configuration Reload OxEF34 w Function J 31 0 A write access to this register causes a software reset a reload of Configuration ROM parameters and a PLL reconfiguration
20. 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 increment the EVENT COUNTER see 4 26 fill the active buffer with the pre post trigger samples whose number is programmable via Post Trigger Setting register see S 4 22 the Acquisition window width is determined via Buffer Organization register setting see S 4 15 then the buffer is frozen for readout purposes while acquisition continues on another buffer Table 3 1 Buffer Organization 0x00 pK 001 2 5E m 4 JD8 amp K gt mm 18 MK gt An event is therefore composed by the trigger time tag pre and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see figure below EVENT n EVENT n 1 EVENT n 2 Recorded Not Recorded TRIGGER PRE POST ACQUISITION WINDOW Overlapping Triggers Fig 3 3 Trigger Overlap A A trigger can be refused for the following causes acquisition is not active memory is FULL and
21. 81 IC R W ee ees ee see esse sees ee ee ee nennen nn enm enne nennen nennen nis 40 4 24 CHANNEL ENABLE MASK 0X8120 R W ee ees ee esse ee see ee nene He ee see ee ee nennen nenne ne nre rese en sn aenean nes 40 4 25 ROC FPGA FIRMWARE REVISION 0X8124 R L 000t0eeoteeooureooooeooooooooooeooooeooooeooooueoooneoouneoooooooooneoooneoonuo 4 4 26 DOWNSAMPLE FACTOR 0X8128 R W ese ee see ee see ee ee He eene he enhn nennen nenne nh ee rh e ihren rese ae eese se ee 4 4 27 EVENTSTURBPETU XOT OC Bee Ge e Ute ent on Meade E DRE QUEM ORO caede EXER ORDERS RUD DUNS Opi E 4 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REV0 DOC 44 4 CAEN Is fos PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 28 BOARD INFO OTO TI RE OE RE AO OE OE OE AE OE AE EE 4 4 29 EVENT NONSENS 4 4 30 CONTROL OME FOO Bes ones Sone ee ee oe EEEE oe ee ee edam ams konbe a Sau kannal 4 4 3 TT ENN 42 4 32 INTERRUPT STATUS ID OPPE R W eden 42 4 33 INTERRUPT EVENT NUMBER OXEFI8 R W esse see sees sees ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 42 4 34 BLOCK TRANSFER EVENT NUMBER OXEFIC R W 000teeoetooooooooooooeoouooooneoooeoooooooneoooeoouoooonooooeooooooenee 42 4 35 INN 42 4 36 SOFTWARE RESET OXEF NN 42 4 37 SOFTWARE CLBAR XEE2S Wees dese aid oti kes ies ee ta tea s droit ay ee ata pasa l atis Ge para asa s
22. EL ees sesse ee ss see ee ee ee ee ee ee ee ee ee ees ee ee ee ee ee ee ee ee ee ee ee 30 FIG 3 15 EXAMPLE OF BLOCK TRANSFER READOUT esse ees esse ees se ese ee ee ee ee ees ee ee ee ee ee see ee ee ee de ee ee ee de ee ee 3 NNN 32 LIST OF TABLES TABLE 1 1 AVAILABLE ITEMS soseer onse dn eie bri and de ka jo ede mm dkr ee ie ed en sa kra ie ee se oe de ant E 8 TR ROVER 13 TABLE 2 3 MOD DT5724 TECHNICAL SPECIFICATIONS rrrrrrnnnnnnrrrnnnnnnrrnnnnnnerrnnnnnnnernnnnnnennnnnnnnenrnnnnnnennnnnnnnnenennnnnee 14 TABLE 3 1 BUFFER ORGANIZATION 17 TABLE 4 1 ADDRESS MAP FOR THE MODEL DT5724 ees esse ee ese ee ee ee see ee ee ee ee ee enn ee ee ee ee eek ee ee enne sna nes 33 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL DT5724 esses ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 34 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 6 CAE NO is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 1 General description NPO 1 1 Overview 3 caen Desktop Digitizer ka or Fig 1 1 Mod D5724 Desktop Waveform Digitizer The Mod DT5724 is a 4 Channel 14 bit 100 MS s Desktop Waveform Digitizer with 2 Vpp dynamic range on single ended MCX coax input connectors The 2 Channel version Mod DT5724A is a
23. ELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 2 Technical specifications 2 1 Packaging and Compliancy The unit is a Desktop module housed in a 154x50x164 mm alloy box 2 2 Power requirements The module is powered via the external AC DC stabilized 230Vac 12Vdc 1 4A power supply Alpha Elettronica Nr SW18 12 60 CDZ Nr 97894 2 3 Front and Back Panel ES a O CAEN Desktop Digitizer O L F3 a eU Fig 2 1 Mod DT5724 front panel SPARE LINK Fig 2 2 Mod DT5724 back panel NPO Filename Number of pages 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 CAEN Q Tool ver PRELIMINARY ds for Discover Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 2 4 External connectors 2 4 1 ANALOG INPUT connectors CHO Fig 2 3 MCX connector Function Analog input single ended input dynamics 2 25Vpp Zin 50Q Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER 2 4 2 CONTROL connectors Function TRG IN External trigger input NIM TTL Zin 50Q Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors GND o CLK Q CLK Oo Fig 2 4 AMP CLK IN Connector Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdi
24. H 1 010 SAMPLE N 2 CH 1 SIZE CONTROL WORD 0 0 SAMPLE 1 CH 3 0 0 SAMPLE 0 CH 3 Gere O CONTROL WORD a 0 0 SAMPLE N 1 CH 3 0 0 SAMPLE N 2 CH 3 Fig 3 4 Event Organization NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 19 CAE NO Is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 3 4 Memory FULL management 3 4 Bit5 of Acquisition Control register see S 4 16 allows to select Memory FULL management mode In Normal Mode the board becomes full whenever all buffers are full see 8 4 15 otherwise Always one buffer free mode it is possible to always keep one buffer free board becomes full whenever N 1buffers are full with N nr of blocks see 8 4 15 In Normal Mode the board waits until one buffer is filled since FULL status is exited whether the trigger is overlapped or not The board exits FULL status at the moment which the last datum from the last channel participating to the event is read In Always one buffer free mode one buffer cannot be used therefore it is NOT POSSIBLE with this mode to set Buffer Code to 0000 see 8 4 15 but this allows to eliminate dead time when FULL status is exited Zero suppression The board implements three algorithms of Zero Suppression and Data Reduction Full Suppression based on t
25. IFICATIONS je 10 2ds PACKAGING AND COMPLIANCY E ee Re ee l EE ee ese dii ee ed a e ra ee ei eo oe 10 2 2 POWERREOUIREMENTS osse sse esse sees ee se ese ee ee ede ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee Gee ee ee ee ee ee pae 10 2 9 IBRONT AND BACK PANEL se ini ese Sesde Es GN oe FRE aw li ia oi kte if PRESE eN QUA ee Ge de eN EE csi ei aa ee 10 24 BEXPERNALCONNEGCEOBS ae 11 2 4 1 ANALOG INPUT connector S e w sasinay a li l Fes eb anko oka a ek rak la Ge ge EG Ee e ka Ge a A a Dr kok Il 2 4 2 CONTROL oe os ee ei sede es Ge ee ee ek ee GE si lat so a ae l N Re ks ll 2 4 3 ADC REFERENCE CLOCK connectors ees sees see see ee ss ees see ee see ee ee ee ee ee eek dee ee ee tese ee ee Il 2 4 4 DATO 00 RT 11 2 4 5 OP LINK COANCCION ae 12 2 4 6 TSG RR AR EE EE EE EE EE EE OE N bo a tn ban tt 12 2 4 7 NTN 12 2 4 6 YOUN OSI PWE NE tr ya EE RE ER EE OR en 12 2 5 OTHER COMPONENTS si osse sessies ie eke eend be ee ee me sieke ee fay eks kai Gee eo ke ee ee eine kte ke kol ra ie 13 251 DISplQYS EE EE OE OE EE N eN 13 TECHNICAL SPECIEICATIONS TABLE eie Ge er ed Ge Ge Ge Gee at ee EG ee eo a ja 14 3 FUNCTHONAL DESCRIPTION Gu note sesse teen seta down din De eke se eie ttn at oog nos sa SVO ELI Ge NR FER cola be ee END tal 15 ATE OG TING Wasco EE EE EE IE 15 22 URD Neve SUD n UE sU Ee Cede udo ek ie ee ie de 15 Ad DIU S MEE IE EE OE EE ENE EO 16 Js COIS diie MODES EN NE EE EE AE ra ae OE EE OE EE ONE N N 16 TAN oe RR 16
26. INARY Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 Functional description 3 1 Analog Input Input dynamic is 2 25Vpp Zin 50 2 A 16bit DAC allow to add up to 1 125V 5V with high range input DC offset in order to preserve the full dynamic range also with unipolar positive or negative input signals The input bandwidth ranges from DC to 40 MHz with 2nd order linear phase anti aliasing low pass filter T MCX Positive Unipolar Input ANN 42 25 DAC FSR 50 ANN 1 125 FPGA 0 l Negative Unipol 2 25 DAC 0 nipolar Bipolar DAC FSR 2 Fig 3 1 Input diagram 3 2 Clock Distribution AD9520 CLK IN l gt Phase MEZZANINES Detector s CHO INTCLK 0 CH1 Acquisition amp Memory Control SyncB EE ER e Logic TRG IN o l Trigger amp Sync Local Bus LOCAL BUS Local Bus Interface Interface OSCCLK dMllll l2 22222222222222222222222222222222 2222 2 2 2 2 2 22 2 2 2 2 2 2 2 TT TT TT OTTO TT TT TEE FPGA ROC Fig 3 2 Clock distribution diagram Number of pages Page NPO Filename 44 15 00100 09 5724x MUTx 00 DT5724 REVO DOC CAEN PRELIMINARY Document type Title Revision date Revision
27. Memory size code DT5724 0x01 7 0 Board Type DT5724 0x00 4 29 Event Size 0x814C r Bt 1 0 funcion 31 0 Nr of 32 bit words in the next event 4 30 Control OxEFOO r w Interrupt mode Bit Reserved must be set to 0 Release On Register Access RORA 6 Reserved must be set to O Reserved must be setto 0 lt lt lt Reserved must be set to 0 Reserved must be set to 1 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 41 CAEN Is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 0 interrupt disabled 1 7 interrupt enabled 3 2 1 Reserved Reserved must be set to 0 Interrupt request can be removed by accessing this register and disabling the active interrupt level 4 31 Status OxXEFO4 r 0 Slave Terminated Transfer Flag no terminated transfer 1 Slave Terminated Transfer Flag one transfer has been terminated by DT5724 unsupported register access or block transfer prematurely terminated in event aligned reaout 0 The Output Buffer is not FULL 1 The Output Buffer is FULL 0 No Data Ready 1 Event Ready 4 32 Interrupt Status ID OxEF14 r w This register contains the STATUS ID that the module places on the 31 0 data stream during the Interrupt Acknowledge cycle 4
28. NELENABLEMASK jnaxo RW X X RocFPGAFIRMWAREREVSION mem R BOWNSAMPLE FACTOR bes RW X X bewrsromp bee kR X X X eono be QR bewrsu bewe k X X X comma eo Mw Xx saus es k INTERRUPTSTATUSIO pera RW X INTERRUFTEVENTNUNBER ner fw X X BLTEVENTNUMBER pemo fw X X sara ee RwX X swReser ee W Swag oo w I NPO 00100 09 5724x MUTx 00 Filename Number of pages Page DT5724 REVO DOC 44 33 CAEN is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 REGISTER NAME ADDRESS MODE H RES S RES CLR FLASHENABLE e wj Fasora oe RW X GONFIGURATIONRELOAD ne Mmm CONFIGURATIONROM eoor R I 4 2 Configuration ROM 0xF000 0xF088 r The following registers contain some module s information they are D32 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model DT5724 Description Address Content OxF000 sernum1 j OxF080 S sernumO OxF084 VCXO type OxFO88 0x00 AD9520 3 These data are written into one Flash page at Power ON the Flash content is loaded
29. Pi An Technical Information Manual Revision n 0 15 March 2010 MOD DT5724 4 CHANNEL 14 BIT 100 MS S DIGITIZER MANUAL REV 0 NPO 00100 09 5724x MUTx 00 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation C CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products CAEN fy for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 TABLE OF CONTENTS 1 GENERAL DESCRIPTION eeue sie neces yo f cee Ree Dee o ex Ge eie ie VOR UN EG lk a deed dk GN do n Se ede 7 ble DERN AE RE EE 7 12 BDOT DIER a E ae kaj iii t ti kok apt e a tk k AAEE ay a ala ee ee t EE 9 Z TECHNICAL SPEC
30. RESSION BASED ON THE AMPLITUDE eene nnn ee ee ee ee ee ee ee sess sensns n nnn nnn n nennen ee AN FIG 3 6 ZERO LENGTH ENCODING SAMPLES STORAGE esse sesse sees ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee dee AR RE ee ee ee ee 23 bo ZERO SUPPRESSION EXAMPLE ets osse ese es Ne ta t p n ode t ee ee l e y oe ee EE a lt pan 24 FIG 3 8 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ni BK NLEWD sesse sesse sesse see see ee ee ee ee ee ee ee ee 24 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 5 CAEN Q Tools for Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 FIG 3 9 EXAMPLE WITH NEGATIVE LOGIC AND NON OVERLAPPING Ni BK Nr pwp esse esse ees see see ee ee ee sees ee ee ee ee ee ee ee ee ee 25 FIG 3 10 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ny BK ees ees ees ees sees see sees see nennen ee ee ee ee 26 FIG 3 11 EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING Ny BK ese esse esse sees sees see see se ee ee ee ee se ee see ee ee ee ee ee ee 2 FIG 3 12 BLOCK DIAGRAM OF TRIGGER MANAGEMENT ees esse esse ees es ee ees ee ee ee ee ee een ee ee ee ee ee nnne se etes se ee ee ee 28 FIG 3 13 LOCAL TRIGGER GENERATION ees sees ss sees ee ee ee ee ee ee ee ee ee eek ee ee ek ee ee ee ee ee ee ee ee ee ee 29 FIG 3 14 LOCAL TRIGGER RELATIONSHIP WITH COINCIDENCE LEV
31. T Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 7 4 8 4 9 4 10 4 11 4 12 NPO Channel n Status 0x1n88 r Bit FUNction J J 1 trying to free a number of buffers too large Channel n DAC see 4 10 Busy 2 1 Busy 0 DC offset updated Memory empty 0 Memory full Channel n AMC FPGA Firmware 0x1n8C r Bit Funcdin gt 31 16 Revision date in Y M DD format Firmware Revision X Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0x7612103 Channel n Buffer Occupancy 0x1n94 r 10 0 Occupied buffers 0 1024 Channel n DAC 0x1n98 r w 15 0 DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1 125V 1 125V range low range or in the 1V 8V range high range see also S 3 1 When Channel n Status bit 2 is set to 0 DC offset is updated see S 4 7 Channel n ADC Configuration 0x1n9C r w 15 0 T B D This register allows to pilot the relevant ADC signals See the LTC2208CUP 14 ADC 14BIT data sheet for details Channel Configuration 0x8000 r w Allows to select Zero Suppression algorithm 0000 no zero suppression default 19 16 0001 full suppression based on the integral ZS INT 0010
32. acquisition on the relevant channel such signal is propagated to the central logic which produces the global trigger which is distributed to all channels see S 3 2 1 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 28 CAEN PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 Nth Nth 4samples lt gt Nth 4samples 4samples 1 THRESHOLD CHO IN Local Trigger CHO Channel Configuration register 6 0 Local Trigger CHO Channel Configuration register 6 1 Fig 3 13 Local trigger generation 3 5 1 1 Trigger coincidence level It is possible to set the minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal If for example Trigger Source Enable Mask see 4 20 bits 3 0 F all channels enabled and Local trigger coincidence level 1 bits 26 24 whenever an enabled channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 3 0 mask The following figure shows examples with Local trigger coincidence level 1 and 7 O NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 20 CAEN
33. age 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 32 CAEN foals ror ETET HVET Document type User s Manual MUT Title Mod DT5724 4 Channel 14bit 100MS s Digitizer Revision date 15 03 2010 PRELIMINARY Revision 0 4 Board internal registers The following sections will describe in detail the registers accessible via software in D32 mode content 4 1 Registers address map Table 4 1 Address Map for the Model DT 5724 REGISTERNAME ADDRESS MODE M RESIS RESGUR EVENT READOUT BUFFER oowoo X X X ramen zs THES ooa RW x al Ghamneln zs nsa peus RW X x ohameln THRESHOLD peo RW X x ChameTMEOVERUNDERTHRESHOLD pea RW X x ChanmelnstaTus pee R x Channel n AMG FPGA FIRMWARE REVISION pec R Channel nBUFFER OCCUPANCY Jora RR X X X remeno fotos ew Ghannelm ADC CONFIGURATION eme fam X x CHANNEL CONFIGURATION oao RW X x CHANNEL GONFIGURATION BIT SET oeoa iw X X CHANNEL CONFIGURATION BIT CLEAR 0008 w X X BUFFER ORGANIZATION ove fw X X customs eo RwX X ACQUISITION GONTROL bewo fam X x acausinonstas bee k Swmocn bes Mm TRIGGER SOURCE ENABLE MASK oeo RW X x FRONT PANEL TRIGGER OUTENABLE MASK peo RW X x FOSTTRIGGERSETING fem RW X x FRONT Pane vo GONTROL eno fw X X GHAN
34. aint aw 42 4 38 FLASH ENABLE OXEF2E R W unne vi okay ee ee venant ana eny de ank a it neat Ge rbd Eae aa n rRNT 43 4 39 OR EA DATA KODE F SOU TI T fie ta eka RE N an ka n a at N ai pe al s 43 4 40 CONFIGURATION RELOAD OXEF34 W 000teteeeeeoeseooseooooeoooeooeeoooeoooeoouoeoooeooonoooeoooeoooneouoeooooooooooooeoooo 43 m UNSPALELATION EE E ne ti pei aa aa pa e pan in pesi QUEMA pa e sa a e pa eka vie ra aaa MV pe bi five n NE seen 44 POOR NR 44 FOR EK vie ME OE OR OR EO A AA Iae TENN SEU TOI de EE EE N m AA LIST OF FIGURES FIG 1 1 MOD D5724 DESKTOP WAVEFORM DIGITIZER eese ee ee ee ee ee ee ee ee ee ee ee ee ee ee 7 FIG 1 1 MOD D5724 BLOCK DIAGRAM assesseer dee apis ti epe ka is s oi oe tk anj ee s ee ena re 9 FIG 2 1 MOD DTS AERONT Na 10 Ig e 2 2 MOD DT 5724 BACK PANEL E n 10 NE CON NE FO f EE EE OE OR ENE NE OE N OE NE N GE NE AR EE NEE least 11 FG AAN CLK ING EIT 11 EEG OPTICE C ON NE TOR asses litt bo ap al a ot ot et n tt SE l a oto n lo aj n ata ot IS ap a oi 12 FG 5 1 INPUT DIAGRAM e fiti tid aktif ak f id ll a l va l l ap a ee a a e ak Ra e e 15 FIG 2 CLOCK DISTRIBUTION DIAGRAM asie sneeu biin aaa ll la ala tir lis ral l el rl OE Gee Ek lt kl td 15 FIG 3 3 TRIGGER 8 VI EN PH 17 FIG 34 EVENT ORGANIZATION c 19 FIG 3 5 ZERO SUPP
35. amples The event format is shown in the following figure case of 3 channels enabled with Zero Length Encoding disabled and enabled respectively Filename Number of pages Page CAEN Tools far Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 ZERO LENGHT ENCODING disabled 31 30 29 28 27 2625 24 23 22212011918 17 16 15 14 13 1211 10 9 81716154 3 2 110 00 SAMPLE 1 CHI O 00 SAMPLE 0 CH O 0 0 SAMPLE 3 CH 0 00 SAMPLE 2 CH 0 gt e O aie 0 0 SAMPLE N 1 CH O 00 SAMPLE N 2 CH 0 0 0 SAMPLE 1 CH 3 00 SAMPLE 0 CH 3 00 SAMPLE 3 CH 3 00 SAMPLE 2 CH 3 9 e e O o 00 SAMPLE N 1 CH 3 0 0 SAMPLE N 2 CH 3 ZERO LENGHT ENCODING enabled 31 30 29 28 27 26 25 24 23 222120 19 18 17 16 15 14 131211109 87 6 543210 SIZE CONTROL WORD olo SAMPLE 1 CH 1 0 0 SAMPLE 0 CH 1 oo O CONTROL WORD ar 0 0 SAMPLE N 1 C
36. d 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled EN 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 3 enable the channels to generate a TRG OUT front panel signal on GPO output as the digitised signal exceeds the Vth threshold see S 3 5 1 Bit0 enables ChO to generate the TRG OUT bit1 enables Chi to generate the TRG OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG OUT SW TRIGGER ENABLE bit 31 enables the board to generate TRG OUT see S 4 19 Post Trigger Setting 0x8114 r w 31 0 Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Npost PostTriggerValue 4 ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA this value is constant but the exact value may change between different firmware revisions Front Panel VO Control 0x811C r w Bit FUNction O 15 2 0 panel output signals GPO enabled u 17 panel output signals GPO enabled in high impedance 0 GPI GPO TRG IN are NIM VO Levels 1 GPI GPO TRG IN are TTL VO Levels
37. e ee ee ee ee ee ee ee ee ee 36 4 10 CHANNEL N DAC OX1N98 R W ee ees esse see ee ee ee hn eee nennen ee ee ee rese rh e nisi se ense e e ese ae enar ns 36 4 11 CHANNEL N ADC CONFIGURATION 0X 1N9C R W ees sees sees ee se ee ee ee nnnm e nnne nennen ee ee ee 36 4 12 CHANNEL CONFIGURATION 0X8000 R W ee ees ees see ee ee ee ee nnne ee ee ee nenne nn ern serene nnns 36 4 13 CHANNEL CONFIGURATION BIT SET 0X8004 W ee ee ee ee ese ee see ee nee Henne nennen nennen nnne nnns 37 4 14 CHANNEL CONFIGURATION BIT CLEAR 0X8008 W ees ee ese ee see ee see eene nennen nennen nennen ns 37 4 15 BUFFER ORGANIZATION OX800C R W ees esse ee sees see ee ene Henne ee ee enhn nene nne rsen ee ee ee ee ee 37 4 16 CUSTOM SIZE LS IB AN 37 4 17 ACQUISITION CONTROL OX8100 R W ees ee ee ee e nemen nemen nnne enne nnne enr e rns ee ee 38 4 18 ACQUISITION STATUS 0X8104 RR ee ee see ee ee nene nemen nn enne ee nn en nh en ee ee se enar sena 38 4 19 SOFTWARE TRIGGER 0X8 1 OSW oer Se ses et ha ee o eau ee Vk Sena EG get 8 si ee Na ERE a Y VEA Sonn kb e RUE YE Ren E ETE VE 30 4 20 TRIGGER SOURCE ENABLE MASK 0X810C R W ee ees see ee see ee ese ee Henne nenne enhn nennen seen rre nan 30 4 21 FRONT PANEL TRIGGER OUT ENABLE MASK 0X81 10 R W ee ees ee see ee see ee see ee ee ee ee ee ee ee ee ee ee ee 40 4 22 POST TRIGGER SETTING OX8114 R W ees ees ee see see ee nenne eene nennen ne nhe ee ee senes enun 40 4 23 FRONT PANEL I O CONTROL 0X
38. efore it is possible to connect up to 8 ADC modules to an A2818 Optical Link Controller or 32 modules to an A3818 4 channel version Filename Number of pages Page 7 00100 09 5724x MUTx 00 DT5724 REVO DOC AA CAEN is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 CAEN provides also for this model a Digital Pulse Processing firmware for Physics Applications This feature allows to perform on line processing on detector signal directly digitized Table 1 1 Available items NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 8 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 1 2 Block Diagram FRONT PANEL x4 channels AMC FPGA ADC amp MEMORY CONTROLLER BUFFERS o ea zl C O O hul ROC FPGA Readout control Optical link control USB interface control Trigger control External interface control Fig 1 1 Mod D5724 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 9 CAEN is for Discove PR
39. ek Nirwo No Niek Nyrwo lt Na der M ER NLFWD N LBK Nica OT Nia Fig 3 9 Example with negative logic and non overlapping Ni gx Nurwp then the readout event is Ny N s N s 5 control words 1 size Good N N Ni FwD N4 words with samples under threshold Skip N Niewo Niek Good N s Niek Ns Nyrwo N words with samples under threshold Skip Na Niewo Niek Good N Ni BK Ns N s words with samples under threshold In some cases the number of data to be discarded can be smaller than N gk and Nirwo 1 If the algorithm works in positive logic and Ni S Niek lt N3 Nirwp 0 Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 23 CAEN Q Tools for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 A Fig 3 10 Example with positive logic and non overlapping Ni BK then the readout event is N N2 N 5 control words 1 size Good N t N N4 No words with samples over threshold Skip Ns NiBk Good N 4 Ni BK Na N A words with samples over threshold Skip N5 2 If the algorithm works in positive logic and Niek 20 Ns lt Nyrwo lt N3 then the readout event is N s N Ns 5 control words 1 size Skip N Good N s N2 NLEWD N words with samples over threshold Skip Ns Nyrwo Good Ny
40. ff 1100 Mechanical specifications AMP 3 102203 4 AMP MODUII 2 4 4 Digital l O connectors Function e GPI programmable front panel input NIM TTL Zin 50Q NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 11 CAEN Is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 e GPO programmable front panel output NIM TTL Zin 50Q used as output for trigger propagation Mechanical specifications 00 type LEMO connectors 2 4 5 Optical LINK connector LINK TX red wrap RA black wrap Fig 2 5 LC Optical Connector Mechanical specifications LC type connector to be used with Multimode 62 5 125um cable with LC connectors on both sides Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s daisy chainable 2 4 6 USB Port Mechanical specifications B type USB connector Electrical specifications USB 2 0 and USB 1 1 compliant 2 4 7 12V External Mechanical specifications RAPC722X SWITCHCRAFT PCB DC Power Jack Electrical specifications 12V DC Input 2 4 8 Spare Link Mechanical specifications 3M 7610 5002 connector NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 12 CAEN is for Discove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod
41. he integral of the signal ZS INT Full Suppression based on the signal amplitude ZS AMP Zero Length Encoding ZLE The algorithm to be used is selected via Configuration register see S 0 and its configuration takes place via two more registers CHANNEL n ZS THRES and CHANNEL n ZS NSAMP When using ZS AMP and ZS ZLE algorithms it must be noticed that that one datum 32 bit long word contains 2 samples therefore depending also on trigger polarity settings of bit31 of Channel n Z8 THRES register threshold is crossed if Positive Logic one datum is considered OVER threshold if at least one sample is higher or equal to threshold Negative Logic one datum is considered UNDER threshold if at least one sample is lower than threshold 3 4 1 Zero Suppression Algorithm NPO 3 4 1 1 Full Suppression based on the integral of the signal Full Suppression based on the integral of the signal allows to discard data from one channel if the sum of all the samples from this channel is smaller than the threshold set by the User see 4 3 It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the sum of all the samples from that channel is higher than the threshold set by the User see S 4 3 3 4 1 2 Full Suppression based on the amplitude of the signal Full Suppression based on the signal amplitude allows to discard data from one channel if the
42. id mmmmmmmm ME EE EE EN EN EN N OUTPUT DATA 31 3029 28 27 26 25124 23 22 21 20 19 1817 16 15 14 13 12 11 1098 7 65413210 Channel Mask 0x5 0HO VIVG Fig 3 6 Zero Length Encoding samples storage NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 23 CAEN Q Tools far Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 3 4 2 Zero Suppression Examples If the input signal is the following Fig 3 7 Zero Suppression example If the algorithm works in positive logic and Nigk lt Ni Nirwp lt Ns Nisx Nyrwo lt N3 Fig 3 8 Example with positive logic and non overlapping Ni gx Nyrwp then the readout event is N s Ni 5 control words 1 size Skip N NiBk Good N s Niek N Niewo N 2 words with samples over threshold Skip Ns Niewp Niek Good Ni Nigk Na Niewo N 4 words with samples over threshold Skip Ns Nyrwo NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 24 CAEN Q is for Discover PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 NPO If the algorithm works in negative logic and Ni
43. ink using block transfers and up to 30 MB s for a USB 2 0 link using block transfers as well Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 30 CAEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 7 3 8 NPO Events readout Event readout is done by accessing the Event Readout Buffer see S 4 1 a FIFO First In First Out memory that can be accessed into the 0x0000 OxOFFC address space Data transfer is always aligned to the programmed number N of events let X the size of the event expected or read from dedicated register f the event size is known a read cycle equal to N X will return all data without interruptions Ifthe number of data read from the Event Readout Buffer is higher than N X transfer will be terminated anyway by DT5724 at the end of N X data Ifthe event size X is unknown for example in case of overlapping triggers there are two cases data transfer x N X all data will be returned data transfer gt N X only N X data will be returned Once an event is read the corrisponding acquisition buffers are available to store new data During readout the board can continue to store events in memory up to the maximum number of programmed buffers available the acquisition process is therefore dead timeless event storage is only interrupted if the combination
44. ith positive logic the compression algorithm is the same also working in negative logic NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 2T CAEN Q Tools far Discovery PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 3 5 Trigger management All the channels in a board share the same trigger this means that all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Memory Buffers GPO TRG OUT f TRG IN e GGE bey Acquisition Logic Digital Thresholds Local Bus Interface Fig 3 12 Block diagram of Trigger management 3 5 1 Local channel auto trigger Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold ramping up or down depending on register settings and remains under or over threshold for Nth quartets of samples at least Nth is programmable The Vth digital threshold the edge type and the minimum number Nth of couples of samples are programmable via register accesses see 4 3 and S 4 6 actually local trigger is delayed of Nth quartets of samples with respect to the input signal N B the local trigger signal does not start directly the event
45. ition PLL and ADCs are synchronised correctly 0 not ready 8 1 ready This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 38 CAEN is fe PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 PLL Status Flag see S 2 5 1 0 PLL loss of lock 7 1 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see S 0 PLL Bypass mode see 2 5 1 0 No bypass mode 1 Bypass mode 5 Clock source 0 Internal 1 External EVENT FULL itis setto 1 as the maximum nr of events to be read is reached EVENT READY it is set to 1 as at least one event is available to readout 0 RUN off uu 1 0 4 19 Software Trigger 0x8108 w Bt Function 4 20 Trigger Source Enable Mask 0x810C r w Bit 31 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enabled 26 24 Local trigger coincidence level default 0 23 4 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 Channel 1 trigge
46. lator PLL mode external reference on CLK IN Jitters100ppm PLL Bypass mode Ext clock on CLK IN drives directly ADC clocks Freq 10 250 MHz CLK IN AMP Modu ID AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available Jitter lt 100ppm TRG IN LEMO 50 Ohm NIM TTL GPI GPO LEMO 50 Ohm NIM TTL 512K sample ch Multi Event Buffer Programmable event size and pre post trigger Divisible into 1 1024 buffers Readout of Frozen buffer independent from write operations in the active buffer ADC data storage Common Trigger TRG IN External signal Software from USB or Optical Link Self trigger Internal threshold auto trigger Daisy chain trigger propagation among boards using GPO 32bit 8ns 34s range Allows data alignment and consistency across multiple DT5724 modules CLK IN allows the synchronization to a common clock source GPI ensures Trigger time stamps and start acquisition times alignment USB2 0 and USB1 1 compliant Up to 30 MB s transfer rate CAEN proprietary protocol up to 80 MB s transfer rate with Optical Link Controller Mod A2818 A3818 Firmware can be upgraded via Optical Link or USB interface General purpose C and LabView Libraries Demo and Software Tools for Windows and Linux Voltage range 12 10 Vdc NPO 00100 09 5724x MUTx 00 Filename Number of pages Page DT5724 REVO DOC 44 14 CAEN PRELIM
47. lso available The DC offset adjustment x 1 125V range on each channel by 16bit DACs allows a right sampling of a bipolar Vin 1 125V up to a full positive Vin 0 2 25V or negative Vin 0 2 25V analog input swing without losing dynamic resolution The module features a front panel clock In and a PLL for clock synthesis from internal external references The data stream is continuously written in a circular memory buffer When triggered the FPGA writes further N samples for the post trigger and freezes the buffer that can be read via USB or optical link The acquisition can continue dead timeless in a new buffer Each channel has a SRAM memory buffer 512 kSamples ch divided in buffers of programmable size 1 1024 The readout from USB or Optical link of a frozen buffer is independent from the write operations in the active circular buffer ADC data storage Zero suppression and data reduction algorithms allow substantial savings in data amount readout and processing rejecting samples smaller than programmable thresholds DT5724 supports multi board syncronization an external reference clock can be distributed to all modules CLK IN and a common input GPI can be used to synchronize all ADC sampling clocks and events trigger time tag DT5724 houses USB 2 0 and optical link interfaces USB 2 0 allows data transfers up to 30 MB s The Optical Link supports transfer rate of 80 MB s and offer daisy chain capability Ther
48. o 1 Channel Configuration Bit Clear 0x8008 w l Configuration register are set to 0 Buffer Organization 0x800C r w Bit BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the table in 3 3 2 A write access to this register causes a Software Clear see 4 37 This register must not be written while acquisition is running Custom Size 0x8020 r w Bit 23 Funcdin gt 0 Custom Size disabled 31 0 Nioc z0 Number of memory locations per event 1 location 2 samples This register must not be written while acquisition is running Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC AA 37 CAEN is fe PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 17 Acquisition Control 0x8100 r w Bit Function 0 Normal Mode default board becomes full whenever all buffers are full see S 4 15 1 Always keep one buffer free board becomes full whenever N 1buffers are full N nr of blocks see 8 4 15 0 DOWNSAMPLE DISABLED 4 1 DOWNSAMPLE ENABLED allows to enable disable downsampling whose factor is set via Downsample Factor register see 4 26 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 3 3 2 0 Acquisition STOP 2 1
49. r enabled EN 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 3 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold see S 3 5 1 BitO enables ChO to generate the trigger bit enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal for example if bit 3 0 F all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 3 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 4 19 NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 39 CAE NO Is for Otscove PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 4 21 4 22 4 23 4 24 NPO Front Panel Trigger Out Enable Mask 0x8110 r w Bt Function J 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enable
50. snnnsnnnnnssssnnssnnsnnnnnnnnnnnse 30 Dele EVENTS READOUT ed 31 3 6 OPTICAL LINK AND USB ACCESS osse bean oni Een eg Eua ep eee See is k bibon ee ee bed ree Ee kte n san MR Ee ee ee Es EE 3l 3 6 1 SONE HO ERROR ENE ENE A A E A pe cos ee N 22 4 BOARD INTERNAL REGISTERS 02200eoeoooeseaooosaaooosaanoooaaooooaonoeouonosouonosouososouonosononosononosenososenososonososonose 33 4 1 REGISTERS ADDRESS MAP P ee 33 4 2 CONFIGURATION ROM OXFOOO OXFO8S8 RR ee ee sees see ee ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee nns 34 4 3 CHANNELNZS THRES OXIN24 R W esse see sesse se ee ese ee ee se dee see nen nnne ee se dee ee ee se a sh aa snae etna eran sees 35 4 4 CHANNELNZS NSAMP OXINZ28 R W ee esse see see ee ee ees see ee ee ee ee ee ee ee ee ee ee senes sna ee ee ee 35 4 5 CHANNEL N THRESHOLD OX1N80 R W ee ees see se see see ees see ee ee ee ee ee ee dee ee ee ee ee ee ee ee ee ee ee dee ee 35 4 6 CHANNEL N OVER UNDER THRESHOLD OXINSA R W ees ee see ee see ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 35 4 7 CHANNEL N STATUS OXINBBIR ees ees sees see ees ee ee ee ee nh ee ee ee ee ee ee ee ee ee ee ee ee dee ee 36 4 8 CHANNEL N AMC FPGA FIRMWARE OXIN8C R ee ees ees see ee see ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 36 4 9 CHANNEL N BUFFER OCCUPANCY OXINOA R ee ese ese see ee see ee see ee ee ee ee ee ee e
51. therefore there are no available buffers the required number of samples for building the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect NPO Filename Number of pages Page 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 17 A GOD VEN is for PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod DT5724 4 Channel 14bit 100MS s Digitizer 15 03 2010 0 NPO 00100 09 5724x MUTx 00 DT5724 REVO DOC 44 18 to the RUN ACQUISITION command see 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout 3 3 2 1 Custom size events It is possible to make events with a number of Memory locations which depends on Buffer Organization register setting see S 4 15 smaller than the default value One memory location contains two ADC samples and the maximum number of memory locations Nioc is therefore half the
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