μPD720114
Contents
1. Consecutive 4 Transitions N x tPERIOD txJR1 Paired Transitions N x tPERIOD bun Data Sheet S17462EJ4VODS 25 NEC uPD720114 Figure 2 16 Low full speed Disconnect Detection D D Vinz min gt fppis Device Disconnect Disconnected Detected Figure 2 17 Full high speed Device Connect Detection D A oc C LM AL cc TT EE Pia Vss ed gt DCNN Device Connect Connected Detected Figure 2 18 Power on and Connection Events Timing Hub port Attatch detected ad Reset recovery power OK time Hub port AA 2401V pu NN USB system software Wane reads device speed Vin min a Viu p ANE ES pe mm Td GNE E ss I DE Ati tRSTRCY taTTDB 26 Data Sheet S17462EJ4VODS NEC uPD720114 3 PACKAGE DRAWINGS e uPD720114GA 9EU A 48 PIN PLASTIC TQFP FINE PITCH 7x7 detail of lead end S NOTE ITEM MILLIMETERS Each lead centerline is located within 0 10 mm of A its true position T P at maximum material condition 9 010 2 7 010 2 7 010 2 9 010 2 0 75 0 75 I O TNOO w 0 05 0 22 9 04 0 10 0 5 T P 1 0 0 2 0 5 0 03 0 1770 07 0 08 1 010 1 0 1 0 05 o 4 a 1 27 MAX 0 25 T P C A Vv DIO UZ lt IT A a Data Sheet S17462EJ4V0DS 0 6 0 15 P48GA2. NEC uPD720114 Timing Diagram Figure 2 11 Hub Differential Delay Differential Jitter and SOP Distortion ee Upstream _ Crossover Cable 50 Point of Port of Hub FOIE Initial Swing E A A O S A Vss AL 50 Point of Downstream Hub Delay Downstream Hub Delay Initial Swing Port of Hub Downstream Port of Hub Downstream tHDD1 tHDD2 E EEDEN EE NT EG HEER H EE NIE VEE n A A Downstream Hub Delay with Cable B Downstream Hub Delay without Cable Downstream Crossover Port of Hub Point Vss NE E Port Hub Delay o Upstream om End of Cable pii Vss LLL D C Upstream Hub Delay with or without Cable Upstream end of cable Upstream port Downstream port ma N EPA Receptacle Function Downstream signaling Upstream signaling D Measurement Points Hub Differential Jitter tHDJ1 tHDDx J tHpox K or tuppx K tuppx J Consecutive Transitions tHDJ2 tHDDx J tHDDx J or tHDox K tupDx K Paired Transitions Bit after SOP Width Distortion same as data jitter for SOP and next J transition trsor tHDDx next J tappx SOP Low speed timings are determined in the same way for tLHDD tLDHJ1 tLDJH2 tLUHJ1 tLUJH2 and tLsor Data Sheet S17462EJ4VODS 23 NEC PD720114 Figure 2 12 Hub EOP Delay and EOP Skew Upstream End of P dis Point of Initial Swing Upstr
3. C Reflow time 60 seconds or less IR60 107 3 220 C or higher Maximum allowable number of reflow processes 3 Not Exposure limit 7 days 10 to 72 hours pre backing is required at 125C afterwards Flux Rosin flux with low chlorine 0 2 Wt or below recommended Caution Non heat resistant trays such as magazine and taping trays cannot be baked before unpacking Pin temperature 300 C or below Heat time 3 seconds or less per each side of the device Flux Rosin flux with low chlorine 0 2 Wt or below recommended Note The Maximum number of days during which the product can be stored at a temperature of 5 to 25 C and a relative humidity of 20 to 65 after dry pack package is opened Data Sheet S17462EJ4VODS 29 NEC uPD720114 MEMO 30 Data Sheet S17462EJ4VODS NEC uPD720114 NOTES FOR CMOS DEVICES D VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vu MAX and Vin MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that a
4. Figure 2 5 Receiver Measurement Fixtures Test Supply Voltage USB s EG os o9 n O CH 2 O O OO Coo 08 SR Ber o 969 FIO O O D c c O O Ka O Am D Outputs of a High Speed Differential Data Generator Q 2 gt o Q 143 Q Data Sheet S17462EJ4V0DS 14 NEC uPD720114 Power Consumption Power Consumption The power consumption under the state without suspend All Notes 1 2 3 e1 Not the poris do not connect to any function l Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under the state without suspend Note 2 The number of active ports is 2 Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under the state without suspend Note 2 The number of active ports is 3 oe Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under the state without suspend Note 2 The number of active ports is 4 39 Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under unplug and the hub in idle Note 3 state The power consumption under plug Vsus ON and the hub in Note 4 suspend state e Ports available but inactive or unplugged do not add to the power consumption The powe
5. 50 9EU 1 27 NEC PD720114 R e uPD720114GA YEU A 48 PIN PLASTIC TQFP FINE PITCH 7x7 HD D detail of lead end 36 25 t 37 24 E HE 48 13 1 12 3 UNIT mm ZE d ITEM DIMENSIONS D 7 00 0 20 E 7 00 0 20 ZD HD 9 00 0 20 b oO X DI S HE 9 00 0 20 A 1 20 MAX A A1 0 1040 05 A2 A2 1 00 0 05 A3 0 25 b 0 22 0 05 c 0 14870 032 i 1 L 0 50 l Lp 0 60 0 15 a y S AT L1 1 00 0 20 0 d e 0 50 NOTE X 0 08 Each lead centerline is located within 0 08 mm of y 0 08 its true position at maximum material condition ZD 0 75 ZE 0 75 P48GA 50 YEU 28 Data Sheet S17462EJ4VODS NEC uPD720114 4 RECOMMENDED SOLDERING CONDITIONS The wPD720114 should be soldered and mounted under the following recommended conditions For soldering methods and conditions other than those recommended below contact an NEC Electronics sales representative For technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html e LPD720114GA 9EU A 48 pin plastic TQFP Fine pitch 7 x 7 e uPD720114GA YEU A 48 pin plastic TQFP Fine pitch 7 x 7 Soldering Method Soldering Conditions Symbol Infrared reflow Partial heating method Peak package s surface temperature 260
6. data jitter See Figure 2 4 Figure 2 9 Hub delay variation range tHSHDV 5 high Bit speed times Note Excluding the first transition from the Idle state Data Sheet S17462EJ4VODS 19 NEC PD720114 3 4 Hub Event Timings Time to detect a downstream facing port tDCNN connect event Figure 2 17 Awake hub 2 5 2000 f Suspended hub 2 5 12000 Time to detect a disconnect event at a hub s topis 2 0 2 5 downstream facing port Figure 2 16 Duration of driving resume to a downstream tDRSMDN port only from a controlling hub Time from detecting downstream resume to tURSM rebroadcast Duration of driving reset to a downstream torsT Only for a SetPortFeature facing port Figure 2 18 PORT_RESET request Time to detect a long K from upstream turLk p Time to detect a long SEO from upstream turiseo 10000 Duration of repeating SEO upstream for tURPSEO m Bit low full speed repeater times Inter packet delay for high speed of tHSIPDSD packets traveling in same direction times Inter packet delay for high speed of tHSIPDOD Bit packets traveling in opposite direction times Inter packet delay for device root hub tHSRSPIPD1 192 Bit response with detachable cable for high times speed Time of which a Chirp J or Chirp K must be tFILT 2 5 us continuously detected filtered by hub or device during Reset handshake Time after end of device Chirp K by which tWTDCH 100 us hub must start driving first Chirp K in the hub s chi
7. will wait after start of SEO on upstream before beginning the high speed detection handshake Time a hub operating in high speed will wait twTREV 3 0 3 125 ms after start of SEO on upstream before reverting to full speed Time a hub will wait after reverting to full twrRsTHS speed before sampling the bus state on upstream and beginning the high speed will wait after start of SEO on upstream before reverting to full speed Minimum duration of a Chirp K on upstream ka from a hub within the reset protocol Time after start of SEO on upstream by tUCHEND which a hub will complete its Chirp K within the reset protocol Time between detection of downstream chip bet and entering high speed state Time after end of upstream Chirp at which twrFs hub reverts to full speed default state if no downstream Chirp is detected Data Sheet S17462EJ4VODS 21 NEC uPD720114 Figure 2 9 Transmit Waveform for Transceiver at DP DM Level 1 400 mV Differential OV CENE SEP dE Point 1 i Differential y rd po poemon ep mo mp o pm ds eo li Trs 400 mV Level 2 Differential Unit Interval 0 100 Figure 2 10 Transmitter Measurement Fixtures Test Supply Voltage USB To 50 Q Inputs of a Connector High Speed Differential Nearest Oscilloscope or 50 Q Device Outputs of a High Speed Differential Data Generator 22 Data Sheet S17462EJ4VODS
8. DATA SHEET MOS INTEGRATED CIRCUIT uPD 20114 The wPD720114 is a USB 2 0 hub device that complies with the Universal Serial Bus USB Specification Revision 2 0 and works up to 480 Mbps USB 2 0 compliant transceivers are integrated for upstream and all downstream poris The uPD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1 1 ECOUSB Series USB 2 0 HUB CONTROLLER compliant device or when the upstream port is connected to a USB 1 1 compliant host Detailed function descriptions are provided in the following user s manual Be sure to read the manual before designing uPD720114 User s Manual S17463E FEATURES e Compliant with Universal Serial Bus Specification Revision 2 0 Data Rate 1 5 12 480 Mbps e High speed or full speed packet protocol sequencer for Endpoint 0 1 e 4 Max downstream facing ports e Low power consumption 10 yA when hub in idle status 149 mA when all parts run in HS mode e All downstream facing ports can handle high speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps transaction e Supports split transaction to handle full speed and low speed transaction on downstream facing ports when Hub controller is working in high speed mode e One Transaction Translator per Hub and supports four non periodic buffers e Supports self powered and bus powered mode e Supports individual or global over current detection and individual or ganged power c
9. DS NEC APLL ALL TT CDR DPC DP n PHY EPO EP1 F TIM Frame Timer FS REP OSB 2 5V REG SERDES SIE 2H UP PHY UPC uPD720114 Generates all clocks of Hub Translates the high speed transactions split transactions for full low speed device to fulllow speed transactions ALL TT buffers the data transfer from either upstream or downstream direction For OUT transaction ALL TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high speed to full low speed For IN transaction ALL TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full low speed to high speed Data amp clock recovery circuit Downstream Port Controller handles Port Reset Enable Disable Suspend and Resume Downstream transceiver supports high speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps transaction Endpoint O controller Endpoint 1 controller Manages hub s synchronization by using micro SOF which is received at upstream port and generates SOF packet when full low speed device is attached to downstream facing port Full low speed repeater is enabled when the 4PD720114 are worked at full speed mode Oscillator Block On chip 2 5V regulator Serializer and Deserializer Serial Interface Engine SIE controls USB2 0 and 1 1 protocol sequencer Upstream Transceiver supports hi
10. ce Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels VO settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or VO pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state m
11. e electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1
12. eam Crossover Port of Hub Cable Point Extended Vss N SEE A Fe FAT 34 E Downstream Downstream PortofHub TT Port of Hub A Downstream EOP Delay with Cable B Downstream EOP Delay without Cable Downstream e Port of Hub 7 7 77 Extended Vss X Upstream Port Crossover OF e in WS ii Point End of Cable Extended Vss C Upstream EOP Delay with or without Cable EOP Delay tFEOPD tEOPy tHDDx teory means that this equation applies to teor and teor EOP Skew IFHESK teoP TEOP Low speed timings are determined in the same way for tLeoPD and tLHESK 24 Data Sheet S17462EJ4VODS NEC uPD720114 Figure 2 13 USB Differential Data Jitter for Low full speed trerioo gt Crossover Differential DE cii Points s Data Lines Consecutive Transitions N x tPERIOD bon Paired Transitions N x tPERIOD txDJ2 Figure 2 14 USB Differential to EOP Transition Skew and EOP Width for Low full speed tPERioD Ton Crossover Crossover Point Extended Differential FEO Point Data tines gt Diff Data to SEO Skew ik N x tPERIOD txDEOP 7 Source EOP Width treort ILEOPT ka Receiver EOP Width tFEOPR lLEOPR Figure 2 15 USB Receiver Jitter Tolerance for Low full speed trerioo gt Differential Data Lines
13. ection for an external bus Data Sheet S17462EJ4VODS NEC PD720114 2 2 Terminology Terms Used in Absolute Maximum Ratings Power supply voltage Voss Indicates voltage range within which damage or reduced reliability will not VDD33REG result when power is applied to a Vpo pin Input voltage Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin Output voltage Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin Output current Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into an output pin Vi Vo Operating temperature Indicates the ambient temperature range for normal logic operations Storage temperature Tag Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device Terms Used in Recommended Operating Range Power supply voltage Vpp3s Indicates the voltage range for normal logic operations to occur when Vss 0 VDD33REG V High level input voltage Indicates the voltage applied to the input pins of the device which indicates the high level state for normal operation of the input buffer f a voltage that is equal to or greater than the Min value is applied the input voltage is guaranteed as high l
14. evel voltage Low level input voltage Indicates the voltage applied to the input pins of the device which indicates the low level state for normal operation of the input buffer f a voltage that is equal to or less than the Max value is applied the input voltage is guaranteed as low level voltage Hysteresis voltage Indicates the differential between the positive trigger voltage and the negative trigger voltage Input rise time i Indicates allowable input rise time to input signal transition time from 0 1 x Voo to 0 9 x Vop Input fall time i Indicates allowable input fall time to input signal transition time from 0 9 x Voo to 0 1 x Vpp 8 Data Sheet S17462EJ4VODS NEC uPD720114 Terms Used in DC Characteristics Off state output leakage current Indicates the current that flows into a 3 state output pin when it is in a high impedance state and a voltage is applied to the pin Output short circuit current Indicates the current that flows from an output pin when it is shorted to GND pins Input leakage current Indicates the current that flows into an input pin when a voltage is applied to the pin Low level output current Indicates the current that flows to the output pins when the rated low level output voltage is being applied High level output current Indicates the current that can flow out of an output pin in the high level state without reducing the output voltage below the specified Vou A negative current i
15. gh speed 480 Mbps full peed 12 Mbps transaction Upstream Port Controller handles Suspend and Resume Data Sheet S17462EJ4V0DS NEC uPD720114 PIN CONFIGURATION TOP VIEW e 48 pin plastic TQFP Fine pitch 7 x 7 uPD720114GA 9EU A lt R gt uPD720114GA YEU A an o D PasAS BEES se ee ee ook bE O X ER O X XX CO 0 O Xo 0O Q 48 47 46 45 44 43 42 41 40 39 38 37 VDD250UT O 1 C O Vss VSsREG O 2 o DP4 LED4 O 3 o DM4 LED3 O 4 O VDD25 LED2 O 5 O DP3 LED1 O 6 O DM3 GREEN O 7 O VDD33 AMBER O 8 O DP2 VDD33 O O DM2 X1 O O Vss X2 O O DP1 VDD25 O O DM1 13 14 15 16 17 18 19 20 21 22 23 24 BUS BO TEST O RREF O AVss R O AVoo O AVss O AVDD O VDD33 O DMU O DPU O Vss O Vpp25 O 4 Data Sheet S17462EJ4VODS NEC uPD720114 e um e m fu vw ua we s amen o we e oe e om e we a ow Ju we 4 es Remark AVss R should be used to connect RREF through 1 precision reference resistor of 2 43 kQ Data Sheet S17462EJ4VODS 5 NEC PD720114 1 PIN INFORMATION Level FEE E E De o E E ESS 1 aovsermitinp iow E SE gere oen 0 ussorimnio __ IN wen wo usos TN wu wo ussormaro TAN row O usos IN mss rav sema Ponerse me AO arog O Retrencereitorcommecion O m Lr imum iu sse CSB 42 4 2 3 3 V Schmitt 3 3 V Schmitt input Port s over current status Ports over current status input PPB 4 1 3 3 V output input Port s power supply control ou
16. ime period Remark The active period of the CSB pin is in effect only when the PPB pin is ON There is a delay time of approximately 4 ms duration at the CSB pin CSB pin operation region Data Sheet S17462EJ4VODS 17 NEC PD720114 USB Interface Block 1 4 Low speed Electrical Characteristics Rise time 10 to 90 tn G 200pFto6o0pr ME Fall time 90 to 10 aa ia cio e sr am Low speed data rate Average bit rate 1 149925 1 1850075 Mbps Downstream facing port source jitter total including frequency tolerance Figure 2 13 To next transition tDDJ1 25 ns For paired transitions tDDJ 14 14 ns Downstream facing port differential receiver jitter total including frequency tolerance Figure 2 15 To next transition TUJR1 152 152 ns For paired transitions tuJr2 200 200 Receiver SEO interval of EOP Receiver SEO interval of EOP Figure 2 14 2 14 ma Width of SEO interval during differential prm Der 210 Hub differential driver jitter EE ZN cable 45 ns 15 ns 45 ns For paired transitions tLuHJ2 Figure 2 11 2 11 Hub EOP delay relative to tubo Figure 2 12 ke Full speed Electrical Characteristics C 50 pF 4 20 ns Rs 36 9 C 50 pF 4 20 ns Rs 36 9 Differential rise and fall time matching trr trr om 111 11 Full speed data rate Average bit rate 11 9940 12 0060 Note Excluding the first transition from the Idle state Downst
17. ing See Figure 2 4 levels Output Levels for High speed High speed idle state High speed data signaling high High speed data signaling low Chirp J level different signal Chirp K level different signal 12 Data Sheet S17462EJ4VODS NEC uPD720114 Figure 2 1 Differential Input Sensitivity Range for Low full speed Differential Input Voltage Range Differential Output Crossover Voltage Range 1 O 0 0 0 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 Input Voltage Range Volts Figure 2 2 Full speed Buffer Vou lou Characteristics for High speed Capable Transceiver Vpp 3 3 Vpo 2 8 Vpp 2 3 VpD 1 8 VbD 1 3 VpD 0 8 Vpo O 3 VDD lour MA Vour V Figure 2 3 Full speed Buffer Voi lo Characteristics for High speed Capable Transceiver 80 60 40 lour MA 20 Data Sheet S17462EJ4VODS 13 PD720114 NEC Figure 2 4 Receiver Sensitivity for Transceiver at DP DM 400 mV Differential Level 1 A AAA Ann nn A An o N is EE EN OG oint 3 OV Differential k 2 Poin Z Point 1 a empo ome pe mom Eo fr a EER pr ds Hal ee RE EN Ed EER EA EG q T T d 1 AA A o A A A A As A AA be ee es es q 2 2l224 p k k EA Tea pram e TEER 400 mV Differential Level 2 100 Unit Interval 0
18. itt buffer 10 Data Sheet S17462EJ4VODS NEC uPD720114 DC Characteristics Vppss 3 14 to 3 46 V Ta 0 to 70 C Control Pin Block Off state output Off state output leakage current current Vo Vppas Vpp2s or Vss ee Low level output current 3 3 V low level output current 3 mA Vor 0 4 V 3 3 V low level output current 12 mA Vor 0 4 V High level output current 3 3 V high level output current 3 MA Von 2 4 V 3 3 V high level output current 12 Von 2 4 V mA Input leakage current 3 3 V buffer Vi Voo or Vss 5 0 V buffer Vi Voo or Vss Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI Data Sheet S17462EJ4VODS 11 NEC PD720114 USB Interface Block Output pin impedance ZHSDRV Includes Rs resistor V Termination voltage for upstream facing w 8s port pullup full speed Input Levels for Low full speed green vote w a v DEER ar ae vo iame o o uw vo Duone common mode argo vor Late ne Output Levels for Low full speed High level output voltage Low level output voltage Output signal crossover point voltage Input Levels for High speed High speed squelch detection threshold Vhssa 100 150 mV differential signal High speed disconnect detection VHspsc 525 625 mv threshold differential signal High speed data signaling common VHscM 50 500 mv mode voltage range High speed differential input signal
19. n internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Vpo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device S PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS devi
20. ndicates current flowing out of the pin Data Sheet S17462EJ4VODS 9 NEC PD720114 2 3 Electrical Specifications Absolute Maximum Ratings Input output voltage 3 3 V input output voltage 3 0 V lt Vppas 3 6 V 0 5 to 44 6 Vi Vo lt Vooss 1 0 V 5 V input out voltage 3 0 V Vppas 3 6 V 0 5 to 46 6 Vi Vo lt Vppas 3 0 V Output current lo 3 mA 10 lo 12 mA Operating temperature temperature Mo N NN TN 00370 0 to 70 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation Recommended Operating Ranges Operating voltage VoossVoossee VDD33REG 3 3 V for Vppss pins KUN 30 346 46 High level input voltage 3 3 V High level input voltage 2 0 Vpp33 6 0 V High level input voltage 2 0 5 5 Low level input voltage 3 3 V Low level input voltage 0 8 5 0 V Low level input voltage 0 8 Hysteresis voltage 5 V Hysteresis voltage 3 3 V Hysteresis voltage Input rise time Normal buffer Schmitt buffer Input fall time Normal buffer Schm
21. ontrol e Supports downstream port status with LED e Supports non removable devices by l O pin configuration e Support Energy Star for PC peripheral system e On chip Rpu Rpd resistors and regulator for core logic e Use 30 MHz crystal e 3 3 V power supply The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information Document No S17462EJ4V0DS00 4th edition The mark lt R gt shows major revised points Date Published June 2007 NS O NEC Electronics Corporation 2005 Printed in Japan NEC PD720114 ORDERING INFORMATION Part Number Package Remark uPD720114GA 9EU A 48 pin plastic TQFP Fine pitch 7 x 7 Lead free product lt R gt uPD720114GA YEU A 48 pin plastic TQFP Fine pitch 7 x 7 Lead free product BLOCK DIAGRAM To Host Hub downstream Upstream facing port CDR SERDES facing port DP 1 PHY Downstream facing port 1 To Hub Function TT upstream facing port DP 2 PHY Downstream facing port 2 To Hub Function DP 3 PHY Downstream facing port 3 To Hub Function X1 X2 NE DP 4 PHY Downstream facing port 4 19 En ee upstream facing port E i NI upstream facing port upstream facing port L p HSO L v dd 2 Data Sheet S17462EJAVO
22. r consumption depends on the number of ports available and actively operating If the PD720114 is locally powered and the upstream facing port is unplugged uPD720114 goes into suspend state and downstream facing port Vsus goes down If the upstream Veus in OFF state the power consumption is same as Pw unr Data Sheet S17462EJ4VODS 15 NEC PD720114 AC Characteristics Vpp33 3 14 to 3 46 V TA 0 to 70 C Pin capacitance Input capacitance Voo 0 V Ta 25 C Output capacitance fc 1 MHz VO capacitance Unmeasured pins returned to 0 V System Clock Ratings Clock Clock Duty cycle cycle tour Remarks 1 Recommended accuracy of clock frequency is 100 ppm 2 Required accuracy of X tal is including initial frequency accuracy the spread of X tal capacitor loading supply voltage temperature and aging etc System Reset Timing Figure 2 6 System Reset Timing trst SYSRSTB 16 Data Sheet S17462EJ4VODS NEC uPD720114 Over current Response Timing Over current response time from CSB low toc 4 5 ms to PPB high Figure 2 7 Figure 2 7 Over current Response Timing CSB 4 1 PPB 4 1 Figure 2 8 CSB PPB Timing 4 ms 4 ms 4ms 4 ms at at m Il gd Up port D line PPB pin output Output cut off CSB pin input Port power EE E Overcurrent supply ON inrush current Jeneiatien Bus power Up port connection CSB detection CSB active Self power Power supply ON delay t
23. ration and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment hom
24. ream facing port To next transition tLDHJ1 For paired transitions Dous Upstream facing port To next transition tLUHJ1 Rise time 10 to 90 Fall time 90 to 10 e TI TI T JJ h 8 Data Sheet S17462EJ4VODS NEC uPD720114 2 4 Full speed Electrical Characteristics Continued Consecutive frame interval jitter No clock adjustment Ti oe om Source jitter total including frequency tolerance Figure 2 13 To next transition toy 3 5 For paired transitions tDJ2 44 0 Source jitter for differential transition to SEO iudi transition Figure 2 14 Receiver jitter Figure 2 15 To Next Transition TURI 18 5 18 5 For Paired Transitions tur2 Source SEO interval of EOP Figure 2 14 mob oT 160 Receiver SEO interval of EOP Figure 2 14 Width of SEO interval during differential tFST transition Hub differential data delay Figure 2 11 with cable tHDD1 without cable tHDD2 Hub differential driver jitter including cable Figure 2 11 To next transition tHDJ1 For paired transitions tHDy2 2 11 High speed Electrical Characteristics aie wie pe O 89 om sera ETE Microframeinteval interval usem 124 1249375 1250625 0625 Consecutive microframe interval difference tHSRFI 4 high speed times Data source BEE See Figure 2 9 Receiver Receiver jitter tolerance 0 tolerance See Figure 2 4 Hub data delay without cable tHsHDD 36 high speed 4 ns times Hub data Hub
25. rp sequence Time for which each individual Chirp J or tDCHBIT 40 AS Chirp K in the chirp sequence is driven downstream by hub during reset Time before end of reset by which a hub tDCHSEO 100 500 us must end its downstream chirp sequence Time from internal power good to device tSIGATT pulling D beyond Viuz Figure 2 18 Debounce interval provided by USB system taTTDB software after attach Figure 2 18 Maximum duration of suspend averaging tsusavel interval Period of idle bus before device can initiate tWTRSM resume 20 Data Sheet S17462EJ4VODS NEC uPD720114 4 4 Hub Event Timings Continued Resume recovery time tRSMRCY Remote wakeup is 10 ms enabled Time to detect a reset from upstream for tDETRST 10000 non O speed capable devices Reset recovery time Reset recovery time Figure 2 18 2 18 bere Inter packet delay for full speed tiPD times Inter packet delay for device response with tRSPIPD1 detachable cable for full EC SetAddress Setaddress completion time time tOSETADOR Time to complete standard request with no tDRQCMPLTND data Time to deliver first and subsequent except tDreTDATA last data for standard request Time to deliver last data for standard tDRETDATAN request Time for which a suspended hub will see a tFiLTSEO US continuous SEO on upstream before beginning the high speed detection handshake Time a hub operating in non suspended full twrasrrs 2 5 3000 ms speed
26. tput or hub configuration input VBUSM NON 5 V tolerant Schmitt input Upstream Vsus monitor si Upstream Vos monitor AMBER 3 3V output input Amber colored LED control output or port indicator select GREEN 3 3V output Green colored LED control output or port indicator select LED 4 1 3 3V output input LED indicator output show downstream port E a or Removable Non removable select TEST 3 3 V Schmitt 3 3 V Schmitt input Test Testsignal sid VDD250UT On chip 2 5 V regulator output it must have a 4 7 uF or greater capacitor to VssreG Vos 3 3 V VDD VDD33REG 3 3 V Vpofor on chip 2 5 V regulator input it must have a 4 7uF or greater capacitor to VssreG Voos 2 5 V Vpo EESTO EIE RE EE e eX KET e m O p PT wa E Y TO ET vr Remark 5 V tolerant means that the buffer is 3 V buffer with 5 V tolerant circuit 6 Data Sheet S17462EJ4VODS NEC uPD720114 2 ELECTRICAL SPECIFICATIONS 2 1 Buffer List e 2 5 V Oscillator interface XI X2 e 5V tolerant Schmitt input buffer CSB1 VBUSM e 3 3 V Schmitt input buffer CSB 4 2 BUS B SYSRSTB TEST e 3 3 V lo 12 mA output buffer GREEN e 3 3 V input and 3 3 V lo 3 mA output buffer PPB 4 1 LED 4 1 e 3 3 V input and lo 12 MA output buffer AMBER e USB2 0 interface DPU DMU DP 4 1 DM 4 1 RREF Above 5 V refers to a 3 V input buffer that is 5 V tolerant has 5 V maximum input voltage Therefore it is possible to have a 5 V conn
27. ust be judged separately for each device and according to related specifications governing the device Data Sheet S17462EJ4VODS 31 NEC uPD720114 ECOUSB is a trademark of NEC Electronics Corporation e The information in this document is current as of June 2007 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such producis No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product ope
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