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DK900 User Manual

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1. 43 Appendix E Source code for C51 startup UART1 47 DK900 Development Kit Introduction Congratulations on purchasing ST DK900 Development kit The DK900 110V or 220 Volt version is a low cost kit for evaluating the PSD9xx family of FLASH Programmable System Devices The kit is extremely versatile and can be used in several different modes In it s simplest mode it can be used to demonstrate the PSD9xx s capability of JTAG In System Programmability ISP After ISP is accomplished the DK900 can be set up to update the program while the MCU is running called In Application Programming IAP And lastly 8051 family users can utilize the DK900 as an evaluation platform for code development Regardless of how much development work is done on the DK900 it functions as an extremely low cost complete JTAG ISP programmer for the PSD9xx family A couple of definitions In System Programming ISP A JTAG interface IEEE 1149 1 compliant is included on the PSD enabling the entire device to be rapidly programmed while soldered to the circuit board MAIN FLASH BOOT FLASH the PLD all configuration areas This requires no MCU participation so the PSD can be programmed or reprogrammed anytime anywhere even while completely blank The MCU is completely bypassed In Application Programming IAP Since two independent FLASH memory arrays
2. PAS GND PA3 5 7 GND PB3 5 7 GND GND PD2 PB3 ES XH 99 Polarity of RESET pin of J1 could be chosen by setting of JP8 a Battery power connector and re charging circuit When using re chargeable battery as power source you can use the prepared charging circuit in this kit To use this charging circuit assemble a diode with register that has proper value Recommended battery is NiCD 10 8V Do not use charging circuit to Manganese Lithium or NiMH batteries b Other power source input connector To use other power sources SMPS Transformer a connector is prepared in this kit Recommended power source is AC DC adapter over 9V output can be AC or DC c Re charging circuit for Vstby Battery When using re chargeable battery as Vstby source you can use prepared normal charging circuit in this kit To use this charging circuit assemble a diode with register that has proper value Recommended battery is NiCD 3 6V Do not use charging circuit to Manganese Lithium or NiMH batteries d Connection between this Eval kit with PC You need a null modem serial cable and use PSDload in Windows95 98 NT as host application The kit baud rate is fixed at 19200bps 32 m m I ap BE 51 251 XRAM gt n wu EXPANSION 33
3. Setting Of MCUs M Setting of MCU RESET polarity 7 8 2222 4 420 1 0 600000030001 010 000000 Connection of PHILIPS 8051XA s Low addresses A0 A3 JP6 Connection of 80251 s control signals for each mode PSEN RD WR JP5 PSD SRAM Battery Backup Enable Disable 9 tette tenete tenete tenete tete PSD s power consumption measurement point JP7 32Kbyte SRAM Expansion 62256 68257 System expansionconnectors J 1 12 13 eee iere cea ene e tege aee e eee er deterrere ic Appendix B Development Board Schematic and parts list 33 h EINE ITUR T Serial Port SchermatiG 3 3 3 2 3 _ 23 _ Power Supply Schematic Eval Board Appendix C FlashLINK Users 37 2 lt lt 2 lt 2 lt 22 ___ _ 3 22 23 2 _ ______ Operating considerations FLASHlink pinouts Loop back connector schematic Appendix D Source code for C51 8032
4. HIE rrr BEE Ibat charge 5 3 6 0 6 3 Vstby Rcharge 100005 PCT 51XA A0 A3 TERRVBATON RESET PDO ALE 01 _ RESET POL PB lt IL RES D ee L vac _ Tuc p 080 ICC 1 T zPEEPPEPI sEREREPE IL TOOUFIB 3V POWER PINS P3 0 RXD P3 1 TXD PSA NTT 03400 P3 51 Appendix B Development Board Schematic and parts list Main Schematic ER P30 e IL lt _ lt gt not inserted 5 Factory setting using copper trace on board Serial Port Schematic MAX232C 1uF 16V C8 1uF 16V CONNECTOR DB9 34 Power Supply Schematic Rcharge 1 4148 Rcharge Vdc Vbat 0 6 Ibat charges D5 D6 1N4001 1N4001 D8 D7 1N4001 1N4001 C11 35 Eval Board Parts List No description 032 MCU 40MHz PLCC socket PLCC socket 2P PLCC V regulator IA7805P eset comparator KIA7045P IMC74HCI4AN ICL232CPE 1 0592MHz 100 09 7K 1 8W 1 8W 70 1 8W IGF06S10K IN 4148RL part number Q ty 05906321 4P PLCC 32 Driver rystal lock resister array 0 1 esister esister otentiometer iode switching ode rectifier IN 4002RL ectrolytic capacitor 1uF 50V 1050 ectrolytic capacitor 10uF 16V C10U16V ectrolytic capacitor 470uF
5. b The stack must be located in the identical locations in both code bundles As an overview consider this What the microcontroller needs from the memory is really pretty simple The memory needs to provide the sequential instructions for the task at hand The microcontroller generates the address and the memory provides the instruction Then the microcontroller executes that instruction This occurs over and over again If a jump needs to occur the microcontroller provides a new address to the memory Same with a subroutine return the microcontroller gets the return address from the stack PSDload example code bundles Following are the code bundles used with the DK900 Development Kit This code is available from the Coded Example under the Tools submenu within PSDsoft Express As mentioned before to get the latest check the web at www st com psm archive U8c9 10x zip C level source code for UART8032 U8p9 10x zip Psd code for UART8032 _ U8c9a10x zip Sample app for uart download uart1 U8c9b10x zip Sample app for uart download uart2 Table2 Software included with Development Board U8c9 10x This is the C level source code used for ISP download earlier in the document This includes full uart functionality e U8p9 10x This is the psd design files that match with the above ISP code e U8c9a10x This is the C level source code used for IAP described earlier in this document uart1 e Uart2
6. code in FSO the next time we power up This flag is non volatile so that if power is removed the system knows how it s desired to power up Cycle power to the unit We have embedded code running in the initialization routine to detect the state of Nvswap and to write that value into the PAGE register msb at power up If it s 0 the code bundle residing in CSBOOTO 1 continues to run If it s 1 we perform the memory manipulations depicted in the next three figures For purposes of this exampk let s assume NVswap indicating the desire to execute from the MAIN FLASH memory First we write to the VM virtual memory register in the PSD a value of 0x06 This action moves the MAIN FLASH area 50 57 into program space as shown in the following figure At this point the code residing in CSBOOTO 1 is still running 19 Execute from NOTHING MAPPED COMMON MEMORY ACROSS ALL PROGRAM PAGES CSBOOT1 CSBOOTO PROGRAM SPACE PAGE 1 PAGE 2 NOTHING MAPPED CSBOOT1 CSBOOTO DATA SPACE PAGE X NOTHING MAPPED NOTHING MAPPED CSBOOT1 CSBOOTO Figure 21 Memory positions after step 2 of memory swap Next we write to the PAGE register to the swap bit location a value of 1 This action changes the system location where the code appears to the microcontroller moving FSO to 0x0000 and CSBOOT to 0x8000 as shown below After this write operation is complete the very next instruction is fetched from FSO Execution continues f
7. Observe in the lower pane the JTAG activities that occur while programming your device m Watch the board mounted display When the download is completed the Development Board will boot automatically showing the displays below This display will sequence one time ending with the last screen PSDload Test This is the screen that needs to be active for the following IAP demo Note that the serial cable should not be plugged in during this ISP exercise DK 900 Eval B d SP Download as Sucessful Please cycle power t see PSDI Test Figure 5 Eval Board Displays for ISP If you power off on the board you will see that the display will resequence confirming that the program and all configuration information are stored in the PSD s non volatile FLASH Memory 0 For better understanding of the program you may want to examine 1 System memory map in the memory map section later in this document 2 PSDsoft Express project 3 file source code included to see how the executing code was configured Step By Step Instructions for IAP Demo a b d Now let s perform an In Application Programming IAP Disconnect the FlashLINK programmer and close PSDsoft Express Connect the serial cable to the serial port on the PC and the Dsub connector on the eval board Note that this cable is a null modem cable F F Once the eval board displays PSDload Test proceed to the next step Invoke PSDload on the PC At invo
8. The entered text will be encapsulated within a PSDstep protocol message and sent to the target system m Figure 14 Application Specific Command PSDload User Defined In the window type RET in upper case and press OK Observe the display on the eval board now shows the PSDload Test banner on the upper line This display indicates that the original CSBOOT resident code is running again You can do some other functions from PSDload like Write to Display to further verify the original program is again active For an explanation of the details that allow this to occur see Using DK900 as a Development Platform later in this manual This concludes the IAP demonstration These activities illustrate how a new code bundle can be downloaded over the serial channel and invoked remotely from PSDload with a serial command Also how another serial command can be used to return to the original code pre IAP code Good job Using DK900 as a Development Platform for 8051 MCU users Concept The ST DK900 Development Board provides the following capabilities e Demonstrate design concepts early optimizing time to market e Jump start user application with proven framework hardware and software e Substitute for user target system until target prototypes are available e Gives instant platform for testing ISP and demonstration e Allows programming the PSD using included Flashlink cable General Board Description The DK9
9. wing EQU statements the initialization of memory eset can be defined ute start address of IDATA memory is always 0 the length of IDATA memory in bytes OH the absolute start address of XDATA memory the length of XDATA memory in bytes OH the absolute start address of PDATA memory the length of PDATA memory in bytes Notes The IDATA space overlaps physically the DATA and BIT areas of 8051 C PU At minimum the memory space occupied from the C51 2 run time routines must be set to zero Reentrant Stac The following functions and Stack Space fo IBPSTACK EQU 0 IBPSTACKTOP EQU Stack Space fo XBPSTACK EQU 0 XBPSTACKTOP EQU Stack Space fo PBPSTACK EQU 0 PBPSTACKTOP EQU k Initilization EQU statements define the stack pointer for reentrant initialized it r reentrant functions in the SMALL model set to 1 if small reentrant is used OFFH 1 set top of stack to highest location l r reentrant functions in the LARGE model set to 1 if large reentrant is used OFFFFH 1 set top of stack to highest location l r reentrant functions in the COMPACT model set to 1 if compact reentrant is used OFFFFH 1 set top of stack to highest location l nition for Using the Compact Model with 64 KByte xdata RAM Page Defi The following variables The EQU PPAGE H in the li nker invocati EENAB
10. 13 0 025 POSTS ON 0 1 CENTERS TERR TDO Connector reference Molex 70247 1401 12 X 11 GND TCK Recommended ribbon cable for quick 10 K 9 connection FlashLink adapter to end product GND TMS Samtec HCSD 07 D 06 00 01 S N BU Digike MEK 14065 ND RST VCC 6 B Note TDI is a signal source on the Flashlink TSTAT TDI and a signal destination on the target 4 3 board CNTL GND TDO is a signal destination on the 2 B 1 FlashLink and a signal source on the TRST JEN target board Figure 30 Pinout for FlashLink Adapter and Target System 39 FlashLink Adapter Conncetor recommended buffering TERR PSD8XXF 13 gt optional rH 8 recommended 8 Any JTAG Device in all ground pins are ByPass Mode connected together inside flashlink assembly straight through ribbon cable 2 row 7 position System Reset JTAG Chaining Example Circuitry PSD8XXF PSD8XXF and other JTAG compatible devices COTTET um e Figure31 JTAG Chaining Example 40 SOLDERING PAD PATTERN ND 518 ACKN 0810 grey DB12 black 6815 orgt DB white FRAME GND DRAIN WIRE R41
11. 16V C470U16V lectrolytic capacitor 100uF 6 3V C100U6 3V eramic capacitor 18pF C18 ceramic capacitor 39pF C39 onolithic capacitor 0 1uF 50V 104 ED green 3nm BL B2141 3D power switch slide 3P eset switch IP 2 pin header IP 14 pin header LCD side IP 14 pin connector PCB side B 9 connector C JACK x2 pin ribbon cable w male con 150mm X2 pin connector angle 6 oo TS C 8 d n olt nut 2 6 mm x 16mm for LCD nti static bag 170 mm x 300 mm ox 110 mm x 150 mm x 24 mm CD module tandoffs for PCB board CB board 8 No 6 ES 16 lt 0 3 gt 8 3 gt 36 Appendix C FlashLINK Users Manual Features e Allows PC parallel port to communicate with PSD9xx via PSDsoft Express Provides interface medium for JTAG communications Supports basic IEEE 1149 1 JTAG signals TCK TMS TDI TDO Supports additional signals to enhance download speed TERR TSTAT Can be used for programming and or testing Wide power supply range of 2 7 to 5 5v Pinout independent with target side flying leads e Convenient desktop packaging allows varying applications desk lab or production Synchronous JTAG interface allows speeds as fast as pc can drive Overview Flashlink is a hardware interface from a standard PC parallel port to one or more PSD9xx devices located within
12. 4 7K 74 240 74 05 036 o 5 gt 744C0 00 832 5 9 USE 7420 11 aa O 01UF 625 c FOR 02 N TRSIN FlashLink Schematic Document Number FlashLink Date Monday July 26 1999 Eheet 70247 1401 MOLEX 4l Loop back connector schematic to flash link assy 1 2 3 4 5 6 T 8 9 PC output PC intput signal signal 14 pin dual row 0 025 sq receptacle polarized same as cable 5 ITSTAT TERR Figure 32 Loop Back Tester Passive FLASHlink PC connector line ACKN ERRN PAP 42 Appendix D Source code for C51 startup UART8032 Modified from original Keil source code for memory swapping This file is p Copyright c STARTUP A51 To translate t 51 STARTUP link the mo following 8151 invocatio BL51 your User defined P art of the C51 Compiler package 1988 1997 Keil Elektronik GmbH and Keil Software Inc This code is executed after processor reset his file use A51 with the following invocation 51 dified STARTUP OBJ file to your application use the ns object file list STARTUP OBJ controls With the follo at processor the absol DATAL OH H s DATASTART EQU DATALE EQU OH gt gt Ne DATASTART EQU DATALE EQU OH gt ower On Initialization of Memory
13. FS0 The new memory contents contained a completely different set of code that picked up immediately It sounds like a stretch but really isn t PSDload address translation When a download occurs the downloaded hexfile contains addresses appropriate for execution that in this case is 0x0000 0x3 fff for 150 We download this data to 0x8000 BFFF If the addresses are in low memory how does the data get in high memory PSDload does an address translation on every data byte in the hexfile that is it changes the addresses according to the download destination of 0x8000 BFFF using the following equation Destination address hex file address destination base execution base For this 8031 family example code exe hex file is 0x0123 dest base 0x8000 exe base 0x0000 Download destination 123 8000 0 0x8123 While this equation may look like overkill for this example it allows transparent PSDload operation to an MCU that boots to high memory Now that we ve described this level of operation lets take a bit closer look at the detailed sequence that occurs between steps 2 and 3 that is as the memory is swapped 21 Micro level You might ask how can this happen without knowledge ofthe microcontroller You might be wondering how can this all happen with the microcontroller running full speed It all happens due to the chip select decoding Here are the equations that control the memory map before after and during the
14. MOV IE 0 diable all interrupts MOV DPTR PSD8XX_regtOEZ2h VM register MOV A 06h both MAIN and BOOT CODE OVX QDPTR A MOV DPTR PSD8XX_regt OEOh PAGE register MOV A 00h SWAP 0 UNLOCK 0 PAG MOVX DPTR A P now works in boot flash MOV MOV MOVX DP DPTR PSD8xx_regtOE2h 2 A 12h TR A VM register BOOT CODE MAIN DATA space 48 MOV SP STACK 1 CALL PSDload_init CALL PSDload LUMP STARTUP2 7 execute Cstartup of BOOT Set SWAP and EXECUTE main flash EXE MAIN MOV IE 0 diable all interrupts MOV DPTR PSD8XX_reg 0E2h VM register MOV A 06h both MAIN and BOOT CODE SPACE MOVX DPTR A MOV DPTR PSD8XX_reg 0EOh PAGE register MOV A 80h SWAP 1 UNLOCK 0 PAGE 0 MOVX DPTR A P now works in main flash MOV DPTR PSD8xx_ reg 0E2h VM register MOV A 0Ch BOOT DATA MAIN CODE space MOVX GDPTR A LJMP 5 2 execute Cstartup of MAIN This location will hold execution source EXECUTE SOURCE OxFF execute boot flash 0x00 execute main flash CSEG 70h PUBLIC EXECUTE SOURC EXECUTE SOURCE DB 0 SOURCE 0 autorun in next startup EXTRN CODE psd init RSEG 515 STARTUPI1 pORCKCKCkCkCkckckckc
15. TCK signal in the ribbon cable These lines are not needed foruse with the flying lead cable that is why the flying lead cable has only 12 of 14 wires populated FLASHIink pinouts There is no standard JTAG connector Each manufacturer differs ST has a specific connector and pinout for the FlashLink programmer adapter The connector scheme on the FlashLink adapter can accept a standard 14 pin ribbon connector 2 rows of 7 pins on 0 1 centers standard keying or any other user specific connector that can slide onto 0 025 square posts The pinout for the FlashLink adapter connector is shown in figure 4 A standard ribbon cable is good way to quickly connect to the target circuit board If a ribbon cable is used then the receiving connector on the target system should be the same connector type with the same pinout as the FlashLink adapter shown in Figure 4 Keep in mind that the JTAG signal TDI is sourced from the FlashLink adapter and should be routed on the target circuit card so that it connects to the TDI input pin of the PSD device Although the name TDI infers Data In by convention it is an output from FlashLink and an input to the PSD device Also keep in mind that the JTAG signal TDO is an input received by the FlashLink adapter and is sourced by the PSD device on the output pin Use Figures 1 2 3 and 6 as a guide ST ENHANCED JTAG ISP CONNECTOR DEFINITION VIEW LOOKING INTO FACE OF SHROUDED MALE CONNECTOR 48
16. This is the C level source code used for IAP described earlier in this document uart2 23 A detailed look at the example implementation The previous example uses two code bundles UART8032 C and UARTI Note that UART2 C is essentially the same as UARTI for the purposes of this discussion The discussion will take the same course as the previous demos and explain what occurs behind the scenes Let s take a walk through the code to see how it works For purposes of this discussion the code is broken into three components as listed below 1 Toplevel flow charts for UART8032 C and UARTI C 2 level flow for return from main memory execution 3 Detailed flows for startup a51 for the UART8032 C and UARTI c Top level functional flow Let s start with the top level flows As an aside the main action occurs in the startup a51 file but lets leave that till last Notice the symmetry between UART8032 C and UARTI C They are identical except the test and check for run execution source that is in UART8032 C but not in UARTI C Now let s see what keeps execution in UART8032 in the BOOT area The value of the variable source base 0x70 resides the FSO segment that on a new part is Oxff since it s erased This value indicates to execute from BOOT FLASH As you can see the if statement in this case is false so execution continues from the BOOT area That is exe main is not executed So when UART8032 C boots the if sta
17. a target PC board as shown below This interface cable allows the PSD to be exercised for purposes of programming and or testing PSDsoft Express is the source for driving FlashLINK Flying lead cable Mates with FlashLink 112 wires Target PC parallel 1 adapter device Ee 9 6 inches gt Figure 28 Typical FLASHlink application Operating considerations Operating power for FlashLINK is derived from the target system in the range of 2 7 to 5 5 v Compatibility over this voltage range is ensured by the design of FlashLINK No settings are involved On a cautionary note it is recommended that the target system be powered with a well regulated and stable source of power which is energized at the final value of Vcc It is not recommended that the input voltage be varied using the verneer on a regulated power supply as this may cause the internal FlashLINK IC s 74VHC240 to misoperate toward the lower end of the supply range Each FLASHLink is packaged with a six inch flying lead cable for maximum adaptability a ribbon cable requires the use a certain connector on the target assembly This flying lead cable mates to the FlashLink adapter on one end and has loose sockets on the other end to slide onto 0 025 square posts on the target assembly 37 PIN SIGNAL DESCRIPTION Type Flashlink is IEEE 1149 1 Signal EJTAG ST EHANCED JTAG Enables JTAG pins on PSD8XXF optional OC 100K J
18. even though the MAIN FLASH is initially unpopulated fs0 7 CSIOP is the base of the register band used to communicate with the PSD using the microcontroller Program gt 2 3 PAGE 2000 27FF CSBOOT1 empty 8k 300 3FF LCD CSBOOTO R CSIOP 8k empty 8031 regs 8031 boots from here Memory Map Figure 15 Memory Map of Eval Board Getting started with a PSDload Since you ve done this before in the previous step by step demo section we ll start with PSDload being active establish a baseline communxations write something to the display by selecting the Action submenu and then Write Display A dialog will pop up allowing you to enter text After you have completed the message click on the Write button PSDload will send out the message After the message has been received the development board responds by displaying the message and sending a response back to PSDload This response prompts PSDload to display an operation completed dialog to the user on the PC All transactions between PSDload and the development board use this handshaking scheme to maintain continuity of the communications link A few reads and writes Now let s do a few read write operations We want to be careful in the selection of the address that we re writing to so we won t interfere with the execution of the present application Do a read memory of RSO at location 2700h with a length of 40h by selecting the command from the pulldown m
19. fly to another Certainly there is more setup detail involved described later under Micro level but this is the essential procedure for any system containing program and data space 1 Power up system with default memory map swap 0 PAGE register msb VM 0x12 2 Write VM register 0x06 3 Write swap 1 PAGE register msb 4 Write VM 0x0C These steps are further depicted graphically in the following 4 figures 18 Here s the memory map at power up Note that we are executing from CSBOOTO0 1 and that MAIN FLASH is in data space During the download the complete new executable including the vector table is copied into FSO During this time the swap bit in the PAGE register is 0 and the VM register is 0x12 DEFAULT SETTINGS SWAP 0 SWAP is one page bit UNLOCK 0 UNLOCK is one page bit Main Flash is initially in data space NVM setting EEPROM is initially in program space NVM setting ACTIONS Power up Boot from CSBOOTO CSBOOT1 Program if needed and verify 8 Flash segments in data space with 8031 UART PROGRAM SPACE DATA SPACE PSEN RD PAGEX NOTHING MAPPED Execute from here COMMON H NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED 4000 MEMORY ACROSS ALL CSBOOT1 DATA PAGES CSBOOTO SYSTEM RAM amp SYSTEM RAM I O SYSTEM RAM amp 0 SYSTEM RAM 8 I O Figure 20 Memory map at power up NVswap 0 Now let s set a flag NVswap to indicate we want to run
20. registers are already worked out for your convenience The code placement issues are serviced in the file itself with conventional CSEG at statements resulting in no linker directives being needed For STEP 2 flag indicating desire to jump from BOOT memory to main memory Nvswap or source the described flag should be set after the downloaded code is successfully transferred and validated Then after the system 15 rebooted the new location is automatically delivered Depending on your application this element can be either volatile or non volatile The motivation to use a non volatile method is that the desired boot source can be carried through a power outage Ifa volatile medium is acceptable in your application a convenient holder for this variable is the internal PSD ram For STEP 3 method to tell the system of desire to return from main memory to BOOT memory the method can be conveyed to the software by virtually any means from a simple mechanical switch or for remote operation via some communications medium Once this is done the ret boot is run manipulating the VM and PAGE register to the desired states and rebooting the system The code content and positioning after the initialization code startup a51 need have no correlation between the two applications That is the linker can be allowed to handle post initialization code without ill effects to the desired swapping operation This element eases the creation of compatib
21. the byte is read and the following action is taken based on it s value if source OxFF then the execution proceeds from BOOT area If source 00 then execution proceeds from MAIN FLASH These are depicted below Condensed and partial flow for startup a51 ret boot exe main 0 0 06 Wmain code space boot in code space PAGE 0x80 main flash exe IE 0 VM 0x06 main in code space boot in code space PAGE 0x0 boot flash exe VM 0X0C main in code space boot in data space VM 0x12 main in data space boot in code space startup2 Figure 27 Partial flow startup a51 25 You may notice in the top level discussion that the two above routines ret boot and exe main are called from differing positions in the code While this is common practice for a subroutine we do not want to return from these routines as a subroutine normally would return The desired operation at the invocation of either of these routines is to precipitate a system reset This allows desired memory swap to occur bringing the new code into execution position How to create your own app for UART Download Typically getting a single application to run is relatively straightforward as the linker and user make sure all references are resolved when the executable file is created Setting up your application for UART download takes only alittle more coordination between the two executable files specifically in the area o
22. transition For clarity we ll only consider the segments of interest for this application whichare 150 and CSBOOTO 1 Certainly the same techniques apply with paging when using the remaining FLASH segments CSBOOTO address gt h0000 amp address lt h1FFF amp swap address gt hCO000 8 address gt hDFFF amp swap CSBOOT address gt h2000 amp address lt h3FFF amp swap address gt hEO00 amp address gt hFFFF amp swap 50 address gt h8000 amp address lt hBFFF amp swap address gt h0000 amp address lt h3FFF amp swap The above equation tells us that fs0 can show up in either of two places 0x0 0x3FFF or 0x8000 0xBFFF The choice of which location is used is based on the variable swap a single bit in the PAGE register msb The swap bit is the most significant bit of the PAGE register 0 The PAGE register is 0 at power up So if swap 0 at power up then 150 must appear at 8000 and CSBOOTO is at 0 0 1 CSBOOTI is at 0x2000 3FFF Code executes from CSBOOTO CSBOOT1 This is the original memory map presented in Figure 20 Program Data Memory Memory CSBOOT1 8k CSBOOTO 8k FFFF CSBOOT1 8k CSBOOTO 8k 8031 boots from here 8031 boots from here swap 0 VM gt 0x12 swap 1 VM 0x0C Figure 24 Segment positions with swap and VM values 22 After the memory
23. 00 Development Board is specific to the 8051 microcontroller family The board contains an empty socket for the PSD9xx which can be populated with the included PSD9xx family component Downloading to the Development Board Executable code can be downloaded to the Development Board two different ways via the JTAG ISP or via the UART IAP Both methods are described and demonstrated in the Step by Step demos for ISP and IAP earlier in this manual The ISP programming can program all elements within the PSD PLD MAIN FLASH secondary FLASH memory and all configuration elements using the 2x7 connector That is all internal PSD components can be programmed via this channel The IAP method uses a standard null modem PC serial cable F F and PSDload PC software downloaded from the web as well as the UART ofthe installed 8032 This method allows only data and executable code to be downloaded over a PC serial link This method is not restricted in destination to the PSD The destination can be any resources on the Eval Board itself PSD components or the external SRAM SRAM not supplied user must solder in standard 32Kx8 SRAM if you desire more SRAM than is contained in the PSD PSDload a win95 98 NT compatible application for the PC administers the PC side ofthe serial link JTAG ISP The PSD813F JTAG interface provides the capability of programming all memory within the PSD PLD configuration MAIN and secondary FLASH memory and BOOT area
24. 44 CALL PSDload init CALL PSDload LUMP STARTUP2 7 execute Cstartup of BOOT Set SWAP and EXECUTE main flash EXE MAIN MOV IE 0 diable all interrupts MOV DPTR PSD8XX_regt 0E2h VM register MOV A 06h both MAIN and BOOT CODE SPACE MOVX GDPTR A MOV DPTR PSD8XX_reg 0E0h PAGE register MOV A 80h SWAP 1 UNLOCK 0 PAGE 0 MOVX GDPTR A 7 now works in main flash MOV DPTR PSD8xx_ reg 0E2h VM register MOV DATA MAIN CODE space MOVX DPTR A LJMP STARTUP2 execute Cstartup of MAIN This location will hold execution source EXECUTE SOURCE OxFF execute boot flash 0x00 execute main flash CSEG 70h PUBLIC EXECUTE SOURC EXECUTE SOURCE DS 1 pORCKCKCkCkCkckckckckckckckckckckckckckckckckckckckckckck ckckckckckckckckckckckckckckckckckckckck ck ckckckckckckckckckckckckckckckck KKK KKK KKK EXTRN CODE psd init C_C51STARTUP STARTUPI1 pORCKCKCkCkCkckckckckckck ck ckckckckckckckckckckckckckckck ckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckck ck ckckckckck KKK KKK KKK When port is used to generate latched address out for external data memories port A must be initialize befor ntering variable initialztion as followings LCALL psd init pORCKCKCKCKCkckckck
25. LFE EQU Q 0 EQU statements defin th on must conform with the PPAGE number xdata page used for pdata control used set to 1 if pdata object are used define PPAGE NAME C_C51STARTU STACK RSEG DS 1 EXTRN PUBLIC CSEG C STARTUP LJMP INT VECTOR C STARTUP SEGM SEGMENT ENT IDA STACK CODE C STAR C STARTUP AT 0 STARTUP1 S AT HERE CODI TA T pORCKCKCKCkCkckckckckckckckckckckckckckckckckckckckck ck ck ckckckckckckckckckckckckck ck ckckckckckckckckckckckckckckckckckckckckckckckck ck ckck ck ckokock Followings are some routines for SWAP and EXTRN CSEG PUBLIC Retu fro MOV MOV OVX MOV MOV MOVX P now works in boot flash x MOV MOV MOVX MOV EXTRN XDATA PSD8XX reg EXECUTE CODE PSDload init PSDload AT 33h RET BOOT EXE MAIN m main flash to boot flash IE 0 diable all interrupts DPTR PSD8XX_reg 0E2h VM register A 06h both MAIN and BOOT CODE SPACE DPTR A DPTR PSD8XX_regt OEOh PAGE register A 00h SWAP 0 UNLOCK 0 PAGE 0 DPTR A DPTR PSD8xx_regtOEZ2h A 12h QDPTR A SP STACK zi register BOOT CODI E MAIN DATA space
26. TAG reset on target optional per 1149 1 OC 10K Signal ground Ee Generic control signal optional C 100K JTAG serial data input 6 TSTAT EJTAG programming status optional VDC Source from target 2 7 5 5 VDC 8 RST Target system reset recommended C 10K TMS mode select Signal ground JTAG clock Signal ground JTAG serial data output EJTAG programming error optional Notes 1 Boldsignals are required connections 2 all signal grounds are connected inside FlashLink adapter 3 OC open collector pulled up to Vcc inside FlashLink adapter Not supported initially by PSDsoft 5 The target device must supply Vcc to the FlashLink Adapter 2 7 to 5 5 VDC 15mA max 5 5V A Figure 29 Pin descriptions for FlashLink adapter assembly 14 signals may not be needed for a given application Here s how they break down 6 Core signals that must be connected TDI TDO TMS TCK Vcc GND 2 Optional signals for enhanced ISP Option 3 flow control TSTAT TERRY 1 Optional signal to control multiplexing of the JTAG signals JEN 1 Recommended signal to allow FlashLink to reset target system during and after ISP RST 1 Optional IEEE 1149 1 signal for JTAG chain reset TRST 1 Optional generic control signal from FlashLink to target system CNTL 2 Two additional ground lines to help reduce EMI if a ribbon cable is used These ground lines sandwich the
27. USER MANUAL DK900 Development Kit For PSD9xxF Family of Flash PSDs ky DK900 CONTENTS m Please see next pages January 2002 1 3 DK900 DEVELOPMENT KIT For PSD9xxF Family of Flash PSDs Rev 1 10 Contents fe PSDsoft Express Point and Click Windows based Development Software from web PSD9xxF Sample DK900 Eval Board FlashLINK JTAG In System Programmer ISP Ribbon and Flying Lead JTAG cables for FlashLINK PSDload WIN95 98 NT based software for from web Serial cable for PSDload CDROM Data Book Software and Videos 110V or 220V Power supply fe fe fe fe fe fe fe fe Detailed Descriptions Step By Step Instructions for ISP Demo a B Pe Step By Step Instructions for LAP D6mo oie ettet rer eers evonet b ode e pes d be yo EO Re E Reese 8 Using DK900 as a Development Platform for 8051 MCU users 12 eoim General Board Descriptions uen e nter n net Downloading to the Development Board JTAG ISP PC Software is de UART Support PSDload oneri rtp tee Definition of Terms ise eese tene Serial Interface s iss PSD Architectures FunCtionSs A
28. Va lable sissies ooo rre d ute dee eee reci eene t a A D DE eR Rer a Memory i p 15 Getting started witha PSDload s e etre 15 Actew reads esee eerte eee tee em eee 15 DOWilad e 17 How does this swapping stuff work anyway 18 Macro oer eee ere f tes t 7 PSDload address translation 6 _ _ ___ _ _______ ____ _ ___ _ PSDload example code bundles a 54 23 A detailed look at the IAP example implementation 24 Top level functional How ieu oris me ie e eee epa leporem e qt acess n prevede ee 24 Detailed flow startup a eee eere eter te an evo aem 25 How to create your own app for UART 00 0 26 27 Application NOTES 5 5 ssa NRR RS RSEN RD NIS 27 _______ 3 _ _ lt lt lt lt 3 _ _ _ ___ ___ _ _ _ _ _ _ Appendix A Jumper configuration on DK900 eval
29. XBP 1 4LOW XBPSTACKTOP IF PBPSTACK 0 C PBP C_PBP LOW PBPSTACKTOP 5 5 1 C START 50 DK900 USER MANUAL Table 1 Document Revision History Date Rev Description of Revision Na Document written in the WSI format DK900 DK900 Development Kit For PSD9xxF Family of Flash PSDs Front page and back two pages in ST format added to the PDF file Any references to Waferscale WSI EasyFLASH and PSDsoft 2000 updated to ST ST Flash PSD and PSDsoft Express 30 Jan 2002 1 1 3 2 3 DK900 USER MANUAL For current information on PSD products please consult our pages on the world wide web www st com psm If you have any questions or suggestions concerning the matters raised in this document please send them to the following electronic mail addresses apps psd st com for application support ask memory st com for general enquiries Please remember to include your name company location telephone number and fax number Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publica
30. You ve already done this in the earlier demo portion of this document so lets dig a bit deeper to see what makes it all work See the following section 17 How does this swapping stuff work anyway Macro level First let s take a look at how the memory map changes during the transitional operations from one executable code bundle to the other Internal PSD resources PAGE and VM registers are used to affect this change in addition to the PLD equations described We will also use a non volatile resource to carry through a power off condition This resource will be called NVswap and can consist of any of the following spare non volatile segment in the PSD board level switch etc The VM virtual memory register is specific to 8031 family devices and allows the PSD memory resources to be controlled between program space and data space This register located at 0 2 can be set to a non volatile initial value using PSDsoft Express and thereafter can be read or written by the microcontroller This register is volatile The PAGE register csiop 0xE0 8 bits is traditionally used to control memory paging but we also use it to control memory addresses as presented to the microcontroller using 1 or more bits This register can be read or written by the microcontroller The initial value of the PAGE register is 0 at power up and is the register is volatile Following is a step by step procedure to boot from one code and change on the
31. are included in the PSD the MCU can execute code from one memory while erasing and programming the other Robust product firmware updates in the field are possible over any communication channel CAN Ethernet UART 1850 etc using this unique architecture In this case all code is updated through the MCU What s Included Hardware PSDOxx FLASH PSD Programmable System Device see www st com psm for data sheet PSD913F2 IMb MAIN FLASH 128kx8 256Kb BOOT FLASH 32kx8 16Kb SRAM 2kx8 or PSD934F2 2Mb MAIN FLASH 256kx8 256Kb BOOT FLASH 32kx8 64Kb SRAM 8kx8 Eval Demo Board with 8032 MCU LCD Display JTAG and UART ports for ISP IAP FlashLINK JTAG ISP Programmer uses PC s parallel port Null Modem serial cable Female Female Power Supply What No Software e assure latest version download from our website note item 3 contains 3 components zipped together 1 PSDsoft Express Point and Click Windows programming development software This will install to it s own directory MCU Selection by manufacturer and part number Graphical definition of pin functions e creation of memory map e JTAG ISP Programming 2 PSDload Windows 95 98 NT based UART download software This will also install to it s own directory e n Application Programming e Performs erase fill read write upload and download of PSD e All functions performed through MCU s UART channel 3 U809_10x zip contains the following ar
32. cation of PSDload most buttons will be greyed out indicating no communications as shown below Figure 6 Initial PSDload invocations screen no comm File Open Find the file as follows DK900 psd This is a configuration file for PSDload that s been constructed for this demo containing the particulars of the design Observe the buttons become active colorful when this file is selected indicating the communications port is properly configured Ifthe button colors do not appear change the comm port while retaining 19 2K baud using the Select Communications submenu or the Comm Port hot button In this case you will also be prompted for the mmf file from the same directory Do not leave this step until you ve achieved active buttons as shown below Figure 7 Initial PSDload invocations screen with comm As well as the active buttons notice that the main window is now populated with the active design The entries are effectively the equations used to determine the memory map This information is entered in PSDsoft Express during the design phase of the project e Doa Write To Display using the Action Write Display submenu or the LCD Display hot key Type something in the dialog press OK and see if it comes up on the eval board display If it does you ve successfully established commu nications between the PC and eval board If this doesn t work check the following l cableis plugged in 2 cable is of correct type straight
33. chived zipped components Please place them in the indicated directories under PSDExpress Create PSDExpress DK900 directory e U809c10x zip Demo ISP executable program for the eval board DK900 uart80_c U809p10x zip psd file for above DK900 uart80_p e Uartl_c zip Demo IAP executable program for the eval board DK900 uartl_c e 2 c zip Another demo program DK900 uart2_c At this point you should have the following files in the PSDExpress DK900 directory Iap 80Ex mmf Iap 80Ex obj 80Ex psd Uartl hex Uart2 hex These are all the files that are needed for the demo s in this manual The remaining archives are source information from which these files were constructed Detailed Descriptions 2 line x 16 char LCD Display Power Switch DC Power Input Pads for additional SR AM UART Serial Port Programming Port 8032 MCU Socket for PSD9xx Jumpers to configure supplied for 80251 or 51XA Expansion MCUs Ports Figure 1 DK900 Development Board Display A two line by 16 character LCD display is included on the Development Board Power switch left position is on UART Serial Port male Connected to MCU serial port used for In Application Programming IAP 8032 MCU Low cost MCU 80251 or P51XA can be substituted see Appendix A 44 pin PLCC Socket for PSD9xx Blank PSD9xx is supplied user installs and performs initial JTAG ISP JTAG programming Port Used in conjunction with FlashLINK programmer
34. ckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckck KK KK KKK KK KK STARTUP2 IF IDATALEN lt gt 0 MOV RO IDATALEN 1 CLR A IDATALOOP MOV RO A 45 DJNZ ENDIF RO IDATALOOP IF XDATALEN lt gt 0 MOV MOV IF LOW MOV ELSE MOV ENDIF CLR XDATALOOP INC DJNZ DJNZ ENDIF DPTR XDATASTART R7 LOW XDATALEN XDATALEN lt gt 0 R6 HIGH XDATALEN 1 R6 HIGH XDATALEN A MOVX DPTR A DPTR R7 XDATALOOP R6 XDATALOOP IF PPAGEENABLE lt gt 0 MOV ENDIF P2 PPAGE IF PDATALEN lt gt 0 MOV MOV CLR PDATALOOP INC DJNZ ENDIF EXTRN DATA MOV ENDIF EXTRN DATA MOV MOV ENDIF EXTRN DATA MOV ENDIF MOV LJMP END RO PDATASTART R7 LOW PDATALEN A MOVX RO A RO R7 PDATALOOP IF IBPSTACK lt gt 0 C IBP C_IBP LOW IBPSTACKTOP IF XBPSTACK lt gt 0 C XBP XBPSTACKTOP C_XBP 1 LOW XBPSTACKTOP IF PBPSTACK lt gt 0 C PBP C PBP 4LOW PBPSTACKTOP 5 5 1 C START 46 Appendix E Source code for C51 startup UART1 Modified from original Keil source code for memory swapping This file is part of the C51 Compiler package Copyright c 1988 1997 Keil Elektronik GmbH and Keil Software Inc STARTUP A51 This code is executed after processo
35. contortions are completed swap 1 and VM 0C We end up with the memory map on the right with fs0 in low program memory and CSBOOT in high data memory Note the values for swap and VM that cause this to occur The location where the vector table is located is generally referred to as the execution location in this document That is this is where code needs to reside so that the microcontroller can find it easily This method of hardware relocation is very convenient due to the integrated components within the PSD Alternative methods use software relocation to accomplish the same task There are a few more items involved in the seamless transition from one code bundle to the other using this method These elements can be totally controlled by the linker and are listed below a location of certain code in the BOOT memory must be located identically to the same code in the MAIN FLASH memory Due to this constraint the code that does the swap and VM writes is located in the c51_ startup routine and used in all code bundles This is needed since the microcontroller doesn t know anything about the memory swap it just keeps on generating addresses After the instruction that writes to the PAGE register the microcontroller generates the next sequential address The code fetch from this next address in memory 2 must be the same as if it were occurring from memory 1 This results in the microcontroller executing seamlessly without knowledge of the swap
36. d system application The FLASH region is erased by sector or bulk entire FLASH and programmed byte by byte The EEPROM region does not require erase and may be written by byte or by page Which technology resides in the BOOT area depends on the device you have chosen For example the F1 has EEPROM in the BOOT area Functions Available Along with the standard windows controls of save open gt new k close and help serial port controls the following are available These functions are can be accessed either from a pull down menu Action or from the shown hot keys Function Description _ Erase Erase FLASH by segment or bulk Fil 1 Fill area Download PE Download new file to memory Upload Upload file frommemory Read e Read area restricted to 160 bytes Write display Write to display on dev board Reset board gs Resetdevelopmentboard User data Encapsulate user specific commands file entry Enter hex file to be downloaded Describe User interface aid memory usage Table 1 PSDload Commands 14 Memory Map Before we really get started using PSDload we should be familiar with the system memory map Recall that all PSDload operations occur by using addresses in this map The application is set up to take advantage of the entire memory space of the 9xx using paging techniques
37. enu 15 You will observe the following dialog box First click on RSO in the lefthand box The start address in hex will automatically be populated for you by the application Now enter the length and click OK Read Memory Figure 16 Read Memory dialog in PSDload A dialog will pop up with the contents of the memory in both hex left side and asc formats right side as shown below Read Memory Data 00002700 95 Figure 17 Read Memory Data in PSDload The contents appear random as this is volatile memory and has not been cleared Now do a write of the same locations You ll see the same box come up as PSDload always does a read prior to a write but now the box is editable You can edit in either the hex display or the asc display and the conversion happens automatically as shown below Try typing your name or something into the ASC field You will notice the hex bytes changing as you type 16 Write Memory Data x 00002700 79 6F 75 72 20 6E 61 6D 65 20 68 65 72 65 D5 ED your name here 00002710 33 18 F9 35 B2 45 B2 BB 54 Al 87 6B 41 3 5 00002720 17 EO ES F4 8B 2 29 08 55 05 54 j U T 00002730 E7 8E OF FF CO 10 FF 38 Z5 D4 51 8C D4 DF 85 2 Cancel Figure 18 Write Memory Data dialog in PSDload Click Write After the response read it again to see if it s really there Cycle power and reread The fact that the informa
38. f code placement and the linker Typically no code changes are required First a quick review of what we re trying to do We are attempting to smoothly transition fromone running application to another The microcontroller will initiate the action but be substantially unaware of its occurrence We are going to accomplish this by manipulation of the code memory presented to the microcontroller Certainly this will take some coordination between the two applications but probably not as much as you might initially think To make things easier we ll do this critical transition just after a system reset as described detailed look at the IAP example implementation section earlier in this document This reset can be initiated either through software or hardware means based on the method s available in your system You can tailor the scheme as described earlier in this document or utilize the key generic elements listed below 1 Startup routine placed identically in both applications 2 Flag indicating desire to jump from BOOT memory to main memory The demo uses the variable source described in the previous section 3 Method to tell system of desire to return from main memory to BOOT memory The demo uses the User Defined command ASP with an argument of RET described in the previous section When using a PSD we recommend the use of our startup a51 routines or an equivalent included in the code bundles The specifics of the VM and PAGE
39. for ISP Reset Button For resetting the MCU and PSD Pads for additional SRAM The resident PSD9xx contains either 2KB or 8KB SRAM This site is for additional SRAM Step By Step Instructions for ISP Demo a b c d e h Go to ST website www st com psm and select Development Tools from the top menu then go to the DK900 Kit Download both PSDload and PSDsoft Express note you will be asked to fill out a form for PSDsoft Express so that a password can be immediately emailed to you Install both programs on your PC running Windows 95 98 NT Plug the blank PSD9XX device into the Eval board socket Plug the FlashLINK Programmer into your PCs parallel port and plug in the ribbon cable to the JTAG port on the eval board for help see the Appendix C FlashLINK manual Note that the serial cable should not be plugged in during this ISP exercise Plug in power supply and turn on power Notice that the LCD display is blank because the PSD is blank Run PSDsoft Express Here is the initial screen if no project is open PSDsoft Specify Project Eg Choose one Open an existing project Create new project Cancel Figure 2 Opening screen upon PSDsoft Express invocation Use cancel at this point since all we need to do is program the PSD and there is no need to create a project Later in the Using the DK900 as a development platform a further tutorial is given on using PSDsoft Express with the Eval B
40. hich vary within each family and between the families These encompass the following memory types EPROM FLASH EEPROM SRAM and registers Generically these memory blocks are termed a memory region The PSD913 contains 128kx8 FLASH 32kx8 FLASH and 2 8 sram PSDLoad must be aware of how these regions map into the system memory as all operations occur based on addresses associated with the system memory The system memory map is determined using the development tool PSDsoft Express This information is provided in the form of a mmf file automatically generated from PSDsoft Express and requested by PSDload at invocation PSDload utilizes this information to portray the system memory map to the user and construct commands to send to the Eval Board Since the system memory map is utilized to achieve the download the PLD within the PSD must have been programmed prior to a serial download attempt PLD programming is accomplished via either the interface or with a conventional parallel programmer both of which are external to PSDstep PSDload 13 Note that the addressing scheme used by PSDload is a different addressing scheme than is used by PSDPro parallel programmer and or FLASHlink PSDload uses the system addresses that is the addresses generated by the microcontroller in the system and correlated by the linker PSDsoft Express and FLASHlink use direct addresses flat 24 bit memory space that are independent of the PLD and the en
41. its be connected to Port A of PSD9xxF2 through JP6 Default 8031 32 of JP6 pins not connected PSD9xxF2 Latched address out function for 8031 Families Port A Port B 80SIXA Addrss 74 Address 11 8 251 mode Address 11 8 Address 15 12 Address 3 0 Address 7 4 Address 3 0 Address 7 4 For more details see FLASH PSD9xxF2 data sheet Reference 9 3 Microcontrollers Bus Interface 9 4 I O Ports 29 Connection of 80251 s control signals for each mode PSEN RD WR JP5 Reference 9 3 Microcontrollers Bus Interface a 16 bits address mode 8031 compatible mode Default setting no need to change jumpers 251 RD 251 PSEN 251P1 7 1 O O 9 2 CNTL2 9 2 CNTL1 9xxF2 Port D2 b 17 bits address mode PSEN and WR will be used as control signals RD pin will out A16 251 Al6 RD 251 PSEN 251 P1 7 4 T OO Quo OO 9 2 CNTL2 9 2 CNTL1 9 2 Port D2 c 18bit address mode PSEN and WR will be used as control signal RD and P1 7 will out A16 and Al7respectively CNTL2 and PD2 of PSD9xxF2 will be used as general PLD input to decode internal external resources 251 AIG RD 251 PSEN 251 17 7 22182421 T lt Que j 9 2 CNTL2 9 2 9xxF2 Port D2 30 PSD SRAM Battery Backup Enable Disable JP9 Default setti
42. ity However the capability is also applicable to the OTP family of PSD s note that in circuit programming is not available due to the OTP families EPROM base Definition of Terms A few term definitions will ease the understandability of the document a PSDLoad is the windows interface running on the PC b PSDStep is the protocol used to communicate between the PC and the Evaluation board Simple Test and Evaluation Protocol Serial Interface The connection from the PC to the evaluation board is via a standard 9 pin null modem cable The communications parameters are 8 data bits 1 stop bit and no parity The interface uses simple three wire TX Rx and GND RS 232 with full duplex operations Flow control is accomplished via software handshaking incorporated into the protocol this is not XOFF The baud rate of PSDload is selectable from 4 8k to 56k but the 8032 board is presently restricted to 19 2kbaud Software flow control is used in order to minimize the master slave physical connections Each command sent from PSDload is intended to elicit a response from the Evaluation Board This handshake is used to verify a valid receipt of the transaction Two methods exist to terminate this handshake if it should become disrupted for any reason the first is a hot key inside PSDload and the second is a communications timeout parameter entered on comm screen PSD Architecture The PSD contains several different blocks of memory w
43. kckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckckck ck ckckckckckckck ck ckckckckckckckckckckckckckck When port is used to generate latched address out for external data memories port A must be initialize befor ntering variable initialztion as followings E LCALL psd init pORCECKCKCKCk kckckckckckckckckckckckckckckckckckckckckckckckck ck ck ckckckckckckckckckck ck kck ck ck ckckckckckckckckckckckckckckck ck ck KKK KKK KKK STARTUP2 IF IDATALEN lt gt 0 49 MOV CLR IDATALOOP DJNZ ENDIF RO IDATALEN 1 A MOV RO A RO IDATALOOP IF XDATALEN lt gt 0 MOV MOV IF LOW MOV ELSE MOV ENDIF CLR XDATALOOP INC DJNZ DJNZ ENDIF DPTR XDATASTART R7 LOW XDATALEN XDATALEN lt gt 0 R6 HIGH XDATALEN 1 R6 HIGH XDATALEN A OVX QDPTR A DPTR R7 XDATALOOP R6 XDATALOOP IF PPAGEENABLE 0 MOV ENDIF IF PDATALEN lt gt 0 MOV MOV CLR PDATALOOP INC DJNZ ENDIF EXTRN DATA MOV ENDIF EXTRN DATA MOV MOV ENDIF EXTRN DATA MOV ENDIF MOV LJMP END P2 PPAG RO PDATASTART R7 4LOW PDATALEN A MOVX RO A RO R7 PDATALOOP IF IBPSTACK lt gt 0 C IBP C_IBP LOW IBPSTACKTOP IF XBPSTACK lt gt 0 C XBP XBPSTACKTOP
44. le applications as all the critical code placement is handled within a single file startup a51 26 References IEEE Std 1149 1 1990 IEEE Test Access Port and Boundary Scan Architecture PSDSoft Express User Manual Flashlink User Manual Application notes 054 JTAG Information 067 Design Turorial for 8032 PSDOXXF 27 Appendix 28 Appendix A Jumper configuration on DK900 eval board Setting of MCUs Power pins JP1 PIN12 JP2 PIN1 JP3 PIN34 JP4 PIN23 Some 8031 32 series use pins 1 12 23 and 34 ofthe PLCC package as additional power input pins You can set proper power to these pins with these jumpers Typical setting of several MCUs INTEL WINBOND DALLAS PHILIPS SIEMENS INTEL 80C31 32 W78C3x DS803x0 8051XA 80C511 3 80C251 L Close VCC Close vssy Close VSS ee ee 055 12559 23 2 55 Default 8031 32 Setting of MCU RESET polarity JP8 MCU RESET polarity can be chosen using this jumper 1 2 Active HIGH reset 2 3 Active LOW reset Typical setting of several MCUs INTEL WINBOND DALLAS PHILIPS SIEMENS INTEL JP8 80C31 32 W78C3x DS803x0 8051XA 80C511 3 80C251 Default 8031 32 Active HIGH reset 1 2 Connection of PHILIPS 8051XA s Low addresses 0 JP6 In the case of PHILIPS 8051X low address A0 A3 should be connected to Port A PA0 PA3 of PSD9xxFx See PSD9xxF2 data sheet These low address b
45. n process During the download you ll observe the character changing between the following V and A change from one character to the next occurs with each new packet received by the eval board When the download is complete you will see the following PS DI oad downl oad Figure 11 Eval Board display for download complete Next observe the results of the checksum calculation covering the entire downloaded contents as shown below Of course this was a successful download This particular display does not persist so watch the display intently PSDI oad test checksum good Figure 12 Eval Board display for checksum validation 10 i Now click the reset button Mi and observe the eval board display The program you just downloaded will boot showing the displays listed below now per f or me d a ee t he new program Clu uM NE GOOD JOB X Figure 13 Eval Board display sequence for In Application Programming IAP You can cycle power or press the reset button again to see that this code also persists in non volatile FLASH memory i J Now let s renvoke the original program that was runnign prior to IAP download Using PSDload press the User defined button dialog will pop as below Application Specific Command XI This submenu allows new commands to be validated That is new actions can be implemented in target code and actuated via commands sent from here
46. ng of this jumper is ON close but a battery should be connected to use this function and FLASH PSD9xxF2 should be re programmed with a new configuration that PC2 configured to Vstby input in PSDsoft Express Device Config Other To program a new configuration download PSDsoft Express design file and 8031 sources from ST web site www st com and modify them PSD s power consumption measurement point JP7 Two pins of this jumper are already connected To measure PSD s power consumption connect DMM to these two pins after cutting pre connected pattern jumper measured PSD s current will be 166 PSD Ice PSD Ic I O ports MCU Bus leakage Ic This measurement could be different from result of calculation according to formula in data sheet To measure correct value make sure all of other terms should be zero 32Kbyte SRAM Expansion 62256 68257 a 8051XA mode Use a upper location marked as XA 14 12 WR PA7 A7 A13 6 A6 A8 PAS 5 1 A9 4 4 PB3 A11 A3 PB6 RAM OE A2 PB2 A10 1 5 RAM CS 0 11 07 4 0 A10 D6 AS DI 9 5 A6 D2 A8 D4 7 03 14 12 WR PAT A7 A13 1716 A6 PAS 5 A9 PA4 4 3 PB6 RAM PA2 A2 A10 PAI 1 PBS RAM CS 0 AD7 ADO AD6 ADI ADS AD2 AD4 AD3 31 System expansion connectors J1 J2 J3 Others J1 8031 JP3 78C33 1 2 12 PSD9xxF2
47. ntrant is used XBPSTACKTOP EQU OFFFFH 1 set top of stack to highest locationtl Stack Space for reentrant functions in the COMPACT model PBPSTACK EQU 0 set to 1 if compact reentrant is used PBPSTACKTOP EQU OFFFFH 1 set top of stack to highest locationt tl Page Definit io EQU statements defin th g followin E riables T the linke EQU T F C_C51STARTUP he de as EQU PPAGE nvocation 0 0 define PPAGE SEGM ENT CODI ER 25 5 EG MENT IDATA RSEG DS 1 25 EXTRN COD PUBLIC CSEG 2 STARTUP LJMP STA INT VI ECTORS A ACK F 2 START C STARTUP 0 RTUP1 T HE must conform with the PPAGE xdata page set to 1 if pdata object are used number n for Using the Compact Model with 64 KByte xdata RAM used for pdata control used C STARTUP pORCKCKCKCKCkckckckckckckckckckckckckckckckck ckckckckckckckckckckckckckckckckckckckckckckckckckckck ckckckckckckckckckckckck ck ck KAKA KKK Followings are some routines for SWAP and EX EXTRN XDATA PSD8XX reg EXTRN CODE PSDload init PSDload CSEG AT 33h PUBLIC RET BOOT EXE MAIN Return from main flash to boot flash RET BOOT
48. oard for development In the Design Flow shown below click on the ST JTAG ISP Bottom row of boxes left side PSD soft Express Dessgn Flow Window Hob Design Flow Figure 3 PSDsoft Express flow Clicking on this box yields the JTAG Operations Single device dialog shown below Operations Single Device Step 1 Select Programming flle and PSD Select lai der and fe Select dence Step 2 Specify JTAGHSP operation and conditions Select operatore Select PSO Select d JTAG pins to use cn Other lt man ten Dick to specifisd 156 apeiaicn gt gt Execute Step 3 Save or retrieve JTAGASP setup Specly Hot der and enorme to save the 2900 His 1 TAG JSP seston or eere 3 prado semen Sas Select bolder and fle Browse Log Mode Click bow to record cession infomation in the bog fle pla ES Cerri 200 Express 61 w alesic C IC Inc Reserved DATE 00 29 2000 080512 gt Hw Setup Reset 122 Figure 4 PSDsoft Express Operations dialog i InStep 1 select folder and file browse to find under DK900 obj j select device box should be filled in for you k InStep 2 click Execute 1
49. r reset translate this file use A51 with the following invocation A A51 STARTUP A51 To link the modified STARTUP OBJ file to your application use the following BL51 invocation BL51 your object file list STARTUP OBJ controls User defined Power On Initialization of Memory With the following EQU statements the initialization of memory at processor reset can be defined the absolute start address of IDATA memory is always 0 IDATAL EQU OH the length of IDATA memory in bytes XDATASTART EQU OH the absolute start address of XDATA memory XDATALE EQU OH the length of XDATA memory in bytes PDATASTART EQU OH the absolute start address of PDATA memory PDATALEN EQU OH the length of PDATA memory in bytes Notes IDATA space overlaps physically the DATA and BIT areas of 8051 CPU At minimum the memory space occupied from the C51 E run time routines must be set to zero Reentrant Stack Initilization The following EQU statements define the stack pointer for reentrant functions and initialized it Stack Space for reentrant functions in the SMALL model IBPSTACK EQU 0 set to 1 if small reentrant is used IBPSTACKTOP EQU OFFH 1 set top of stack to highest locationt tl Stack Space for reentrant functions in the LARGE model XBPSTACK EQU O set to 1 if large ree
50. rom FSO until the next time the system is powered down CSBOOT3 CSBOOT2 CSBOOT1 Execute from CSBOOTO COMMON MEMORY ACROSS ALL PROGRAM Figure 22 PROGRAM SPACE PAGE 1 PAGE2 CSBOOT3 CSBOOT3 CSBOOT2 CSBOOT2 CSBOOT1 CSBOOT1 DATA SPACE PAGE X CSBOOT3 CSBOOT2 CSBOOT1 CSBOOTO NOTHING MAPPED SYSTEM RAM amp I O Memory locations after step 3 of memory swap 20 As a final step the CSBOOT area is moved to data space so it can be written This is accomplished by another write to the VM register of a value of 0 0 ACTIONS Move EEPROM to data space Set VM bit EE DATA 1 clear VM bit EE CODE 0 This is the final form of the memory map Original boot code in EESO EES1 can be modified by the MCU only if the unlock bit is set to 1 to prevent inadvertant writes unlock bit is a page register bit PROGRAM SPACE DATA SPACE PAGE 1 PAGE 2 PAGE X CSBOOT3 CSBOOT2 NOTHING MAPPED CSBOOT1 IF unlock 1 Execute CSBOOTO from gt here 8 IF unlock 1 COMMON MEMORY ACROSS ALL PROGRAM PAGES NOTHING MAPPED SYSTEM RAM amp I O Figure 23 Memory locations after final step of memory swap With the NVswap bit set this sequence will occur every time power is applied As a short review let s talk about what just transpired We booted from one memory CSBOOT then at full speed and without the awareness of the microcontroller we changed that memory to
51. s This interface can also be used to program a completely blank component as JT AG enabled is the default PSD state See Application Note 54 054 for further description on our CD or website atwww st com psm The LCD will be non operational during JTAG ISP since the MCU is not operating During this interval the PSD is not connected to the MCU bus ST provides a FlashLINK programmer to facilitate this programming operation The FlashLINK programmer connects the PC parallel port to the Eval Board JTAG connector and is driven by PSDsoft Express the PSD development tool 12 PC Software UART Support PSDload PSDload is a PC application WIN95 98 NT which allows serial communications between the PC and the ST series of Development Boards This application utilizes the microcontroller UART on the target system side and a standard serial PC channel The protocol utilizes commands to perform the following functions on the resident PSD and potentially other Eval Board resources Read and write registers memory Erase and fill memory areas Write to the LCD display Download files from the PC to the target system any system area Program the downloaded file into the PSD memory in circuit MAIN or BOOT areas Upload files from the PSD or development board resources Reset the target system UY pap The primary target of this interface is FLASH based PSD s from the standpoint of in circuit programmabil
52. tement is not true and execution remains in the BOOT area This is the state after the ISP download and before IAP download If power is cycled the code always does executes from the BOOT area 8032 c flow startup init psd init UART1 C flow startup init psd init run execution source V check execution source source check not necessary if source 0 M exe main PSDload init main init comm parameters init comm parameters lcd Figure 25 Top Level flows UART8032 C and UARTI C The next thing that occurs is the download UARTI C code is downloaded via the serial channel to FSO MAIN FLASH area At this point no functional changes are observed on the display The new code is resident in FSO but not active As a component of this download the value of source has changed to 00 Now when the Reset command is issued from PSDload the if statement in UART8032 C flow is true and the routine exe main executes This changes the values of the VM and PAGE register to enable the main area to execute and clears out the stack so that UARTI C can continue to run These details are discussed later Note that in UARTI C flow there is no source check That is run execution source is not included This is because the manipulations required for MAIN FLASH to run have already been taken care of since the variable source 00 Now the UART1_C code is running as evidenced by
53. the display Note that in this code only a subset of the serial functionality is included ASP and RST This limitation was pursued in order to make UARTI C able to be compiled with the evaluation version of the Keil compiler 2k exe 24 Now all we need to do is regain execution from the BOOT area code Following is the top level flow that results in the return to BOOT memory execution that is the issue of the ASP instruction User Defined from PSDload with an argument of RET The routine ret boot causes the VM and PAGE register manipulations allowing the BOOT area to regain control 1 C flow serial if ASP RET ret boot Figure 26 Flow to return to BOOT memory execution As you can observe from the above discussion the manipulations at the top level to accomplish the traditional boot loader function using hardware techniques are straightforward Detailed flow startup a51 Now that the top level flow has been discussed lets turn out attention to the startup a51 routine This module contains the code that manipulates the VM and PAGE registers that allows the boot loader to relinquish and regain control In addition other necessary details are handled such as stack manipulation Appendix E and F include the source startup a51 files from each of these bundles The only differing element between these files is the byte EXECUTION SOURCE UART8032 declares this as storage only while UARTI sets this byte to 0 At boot
54. through 3 correct comm port is selected f Selectaction download observing the Download Segments dialog The following screen will appear Download 5 Quick Tips Step 1 Select download destination This is the system memory map location where the serial transfer places the code This is not the location from which execution occurs m Select Download Destination s a csboot b csbootl b eslcd cslcd b Figure 8 Download Segments dialog PSDload Selecting the download destination Step 1 to be fs0_a Behind the scenes 150 b will automatically be selected as the execution location Click OK g Now Download Selection Summary screen below pops up The intent is to validate the settings chosen in the last screen You should see 150 a as the download destination and 150 b as the execution location Click Download to start the process or back to change Download Selection Summary The following Segments were selected and will be downloaded to the non executable Destination Destination Location Executable Location Source File a fs b D PSDexpress DKS00 U art hex Press Download to continue or Back to return Figure 9 Download Summary screen h Observe the progress bar at the bottom of the PSDload window for activity Also observe the display on the eval board as follows Figure 10 Eval Board display for download i
55. tion is now gone confirms that the area was SRAM Now let s repeat these operation using FLASH The dialogs are the same except for the FLASH selection so they won t be repeated Since the FLASH memory is not used in the application yet no harm will be done Select Write Memory and in the write dialog select fs7 which stars at 0 000 Read 40h bytes of the area You will notice that instead of the random characters you observed in the above example using SRAM you now get Oxff in all locations This is because the FLASH is blank Type in something and click write Now do a read to see if it s there Type in something else of lesser length than above and read it back again You will notice that the entire first message is gone This is because the FLASH was erased prior to the last write Two methods exist to erase FLASH by sector or by bulk the whole thing In this case the bulk erase is used You can also cycle power on the target to see that the information is held in non volatile form Also try ERASE which only works on the non volatile areas When you re ready to do a download one the operations that s needed is the selection ofthe hex file This screen is available from the Action submenu or the Fite button After exiting this screen the selected hex file shows up in the main mmf display Hex File Selection x Memory Select Name Lox Figure 19 Hex File Selection screen PSDload Download
56. tion supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2002 STMicroelectronics All Rights Reserved STMicroelectronics group of companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com TA 3 3

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