AD7878JP - Analog Devices
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1. AD7878 Table IV TMS32010 TMS32020 Interface Connections ed panonnonaonnnnn 28 Pin Cerdip Q 28 ToDo oUU ooo ooo lee a aS amd ih Y 28 Pin Ceramic DIP D 28 PIU PLATED IN AcconDance WTH MANU M 3880 REQUIREMENTS DC Signal Connect TMS32010 TMS32020 Contact No Mnemonic Signal Signal 1 RW RW 2 STRE STRB 3 DMRD 4 DMWR 5 TS cs 6 READY READY 7 RESET RESET RESET 8 ALFL INT INT 9 ADDO PAO A0 10 CLK CLKOUT CLKOUT2 u DB10 D10 D10 12 DB11 Di DIL 13 DBS D8 D8 14 DB9 D9 D9 15 DB6 D6 D6 16 DB7 D7 D7 17 DB4 D4 D4 18 DE5 D5 D5 19 DB2 D2 D2 20 DB3 D3 D3 21 DBO bo Do 22 DBI DI DI 23 5V 5V 5V 24 5V 5V 5V 25 GND GND GND 26 GND GND GND OUTLINE DIMENSIONS Dimensions shown in inches and mm 28 Pin Plastic DIP N 28 Oar a A 1 ih CEE e i s PEA a ie a a wee PLATED KOVAR OR ALLOY 42 16 S 28 Terminal PLCC P 28A HS 28 Terminal LCCC E 28A Analog Devices reserves the right to ship either cerdip or ceramic hermetic REV A C1204a 1 5 97 PRINTED IN U S A2. DATA REGISTERENABLE CS OWWR CLKIN Figure 8 Basic Write Operation AD7878 Extended Read Write Operation As described earlier a read write operation to the AD7878 can cause spurious on chip transients Should these transients occur while the track hold is going from track to hold mode it may result in an incorrect value of Vry being held by the track hold amplifier Because the CONVST input has asynchronous capa bility a read write operation could occur while CONVST is low The AD7878 allows the read write operation to occur but has the facility to disable its three state drivers so that there is no data bus activity and hence no transients while the track hold goes from track to hold Writing a logic 0 to DB5 DISO of the status control register prevents the output latches from being enabled while the AD7878 BUSY signal is low If a microprocessor read write operation can occur during the BUSY low time the BUSY should be gated with CS of the AD7878 and this gated signal used to stretch the instruction cycle using DMACK ADSP 2100 READY TMS32020 or DTACK 68000 When CONVST goes low the AD7878 acknowledges it by bringing BUSY low on the next rising edge of CLK IN With a logic 0 in DBS the AD7878 data bus cannot now be enabled If a read write operation now occurs the BUSY and CS gated signal drives the microprocessor into a WAIT state thereby extending the read write operation BUSY goes high on th
3. tral content of the input signal Hence the parameters for which the AD7878 is specified include SNR Harmonic Distortion inter modulation Distortion and Peak Harmonics These terms are dis cussed in more detail in the following sections Signal to Noise Ratio SNR SNR is the measured signal to noise ratio at the output of the ADC The signal is the rms magnitude of the fundamental Noise is the rms sum of all the nonfundamental signals excluding dc up to half the sampling frequency ff 2 SNR is dependent upon the number of quantization levels used in the digitization process the more levels the smaller the quantization noise The theoretical signal to noise ratio for a sine wave input is given by SNR 6 02 N 1 76 dB a where N is the number of bits Thus for an ideal 12 bit con verter SNR 74 dB The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the Vix input which is sampled at a 100 kHz sampling rate A Fast Fourier Transform FFT plot is generated from which the SNR data can be ob tained Figure 10 shows a typical 2048 point FFT plot of the AD7878KN with an input signal of 25 kHz and a sampling frequency of 100 kHz The SNR obtained from this graph is 72 6 dB It should be noted that the harmonics are included in the SNR calculation pur rarouency sete SAMPLE FREQUENCY ote ENR aeae Figure 10 AD7878 FFT Plot Effective Number
4. IN The propagation of data words down the FIFO is also synchronous with this clock As a result a read operation to obtain data from the FIFO must also be synchronous with CLK IN to avoid Read Write conflicts in the FIFO i e reading from FIFO Loca tion 0 while it is being updated This requires that the micro processor clock and the AD7878 CLK IN are derived from the same source INTERNAL COMPARATOR TIMING The ADC clock which is applied to CLK IN controls the suc cessive approximation A D conversion process This clock is internally divided by four to yield a bit trial cycle time of 500 ns min CLK IN 8 MHz clock Each bit decision occurs 25 ns after the rising edge of this divided clock The bit decision is latched by the rising edge of an internal comparator strobe sig nal There are 12 bit decisions as in a normal successive ap proximation routine and one extra decision that checks if the input sample is out of range In a normal successive approxima tion A D converter reading data from the device during conver sion can upset the conversion in progress This is due to on chip transients generated by charging or discharging the databus concurrent with a bit decision The scheme outlined below and shown in Figure 4 describes how the AD7878 overcomes this problem The internal comparator strobe on the AD7878 is gated with both DMRD and DMWR so that if a read or write operation occurs when a bit decision is about
5. V AGND to DGND 0 3 V to Vpp 0 3 V Vixto AGND 15 Vito 15 V Pam vono V REF OUT to AGND lt 0 to Vpp a High Z to Vow b High Z to Vor Digital Wop to VGN CLK IN DMWR DMRD RESET Figure 1 Load Circuits for Access Time TS CONVST ADDO 0 3 V to Vpn 0 3 V Digital Outputs to DGND Ww ALFL BUSY 0 3 V to Vpn 0 3 V Data Pins m DB11 DB0 siah eain ridi 0 3 V to Vpn 0 3 V Operating Temperature Range Den Den J K L Versions lt 0 C to 70 C A B Versions 25 C to 835 C a 2 10pF 10pF S Version 55 C to 125 C Storage Temperature Range 65 C to 150 C Vv Lead Temperature Soldering 10 sec 300 C DOND DGND Power Dissipation Any Package to 75 C 1000 mW a Voto High Z b Va to High 2 Derates above 75 C by 10 mWi C Stresses above those listed under Absolute Maximum Ratings may cause perma Figured sue Create tor Opit Float Daly nent damage to the device These are stress rating only functional operation of the device at these or any other conditions aboye those indicated in the operational sections ofthis specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD7878 features proprietary ESD protection circuitry perman
6. offset of the op amp driving the analog input of the AD7878 while the input voltage is 1 2 LSB below ground The trim procedure is as follows apply a voltage of 0 73 mV 1 2 LSB at V and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000 Gain error can be adjusted at either the first code transition ADC negative full scale or the last code transition ADC positive full scale The trim procedures for both cases are as follows REV A AD7878 Positive Full Scale Adjust Apply a voltage of 2 9978 V FS 2 3 2 LSBs at V Adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111 Negative Full Scale Adjust Apply a voltage of 2 9993 V FS 2 1 2 LSB at V and ad just R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001 INPUT RANGE 23V vio Rt 10k s002 Ra 10k ADDITIONAL PINS OMITTED FOR CLARITY Figure 17 AD7878 Full Scale Adjust Circuit MICROPROCESSOR INTERFACING The AD7878 high speed bus timing allows direct interfacing to DSP processors Due to the complexity of the AD7878 internal logic only synchronous interfacing is allowed This means that the ADC clock must be the same as or a derivative of the pro cessor clock Suitable processor interfaces are shown in Figures 18 to 21 AD7878 ADSP 2100 TMS32010 TMS32020 All three interfaces use an external timer for con
7. provided that Nyquist criterion is obeyed The throughput rate must take into account ADC CONVST pulse width ADC conversion time and the track hold amplifier acquisition time The time required for each of these tasks is shown in Table II for a selection of DSP proces sors Since the ADC clock has to be synchronized to the micro processor dock the conversion time depends on the micro processor used In addition time must be allowed for reading data from the AD7878 If this task is performed during the track hold amplifier acquisition period then it does not impact the overall throughput rate However if the read operations occur during a conversion they may stretch the conversion time and reduce the track hold amplifier acquisition time The track hold amplifier requires a minimum of 2 is to operate to specification The time required to read from the AD7878 depends on the number of FIFO memory locations to be read and the software organization As an example consider an application using the ADSP 2100 and the AD7878 with a throughput rate of 100 kHz The time required for the ST pulse and the ADC conversion is 7 375 ps This leaves 2 625 us for the track hold acquisition time and for reading the ADC both operations occurring in parallel The ADSP 2100 when operating from a 32 MHz clock has an instruction cycle of 125 ns and an interrupt re sponse time of 500 ns This allows adequate time to perform 16 read operations within the tim
8. the device during conversion 8 reads from the FIFO and 8 reads from the status control register It also has the potential to write once to the status control register If these ano msa i OLE h u u a Figure 4 Operational Timing Diagram 6 REV A AD7878 17 16 read plus 1 write operations all occur during troy time periods the conversion time will slip by 17 CLK IN cycles Therefore if read or write operations can occur during tow periods it means that the conversion time for the ADC can vary from 7 is to 9 12 us assuming 8 MHz CLK IN This calcula tion assumes there is a slippage of one CLK IN cycle for each read or write operation INITIATING A CONVERSION operation with ADDO low accesses data from the FIFO while a read with ADDO high accesses data from the status control register Conversion is initiated on the AD7878 by asserting the CONVST input This CONVST input is an asynchronous input indepen dent of either the ADC or DSP clocks This is essential for applica tions where precise sampling in time is important In these applica tions the signal sampling must occur at exactly equal intervals to minimize errors due to sampling uncertainty or jitter In these cases the CONVST input is driven from a tamer or some precise clock source On receipt of a CONVST pulse the AD7878 acknowl edges by taking the BUSY output low This BUSY output can be used to ensur
9. to be made the bit decision point is deferred by one CLK IN cycle In other words if DMRD or DMWR goes low with CS low at any time during the CLK IN low time immediately prior to the comparator strobing edge tow of Figure 4 the bit trial is suspended for a clock cycle This makes sure that the bit decision is latched at a time when the AD7878 is not attempting to charge or discharge the data bus thereby ensuring that no spurious transients occur internally near a bit decision point The decision point slippage mechanism is shown in Figure 4 for the MSB decision Normally the MSB decision occurs 25 ns after the fourth rising CLK IN edge after CONVST goes high However in the timing diagram of Figure 4 CS and DMRD or DMWR are low in the time period t o prior to the MSB deci sion point on the fourth rising edge This causes the internal comparator strobe to be slipped to the fifth rising clock edge The AD7878 will again check during a period tow prior to this fifth rising clock edge and if the CS and DMRD or DMWR are still low the bit decision point will be slipped a further clock cycle The conversion time for the ADC normally consists of the 13 bit trials described above and one extra internal clock cycle during which data is written from the SAR to the FIFO For an 8 MHz input clock this results in a conversion time of 7 s However the software routine servicing the AD7878 has the potential to read 16 times from
10. up to 500 pA to an external load AD7878 TEMPERATURE INTERNAL COMPENSATION 3V REF Vas ADDITIONAL PINS OMITTED FOR CLARITY Figure 14 AD7878 Reference Circuit The maximum recommended capacitance on REF OUT for normal operation is 50 pF If the reference is required for use external to the AD7878 it should be decoupled with a 200 Q resistor in series with a parallel combination of a 10 pF tantalum capacitor and a 0 1 pF ceramic capacitor These decoupling components are required to remove voltage spikes caused by the internal operation of the AD7878 TRACK AND HOLD AMPLIFIER The track and hold amplifier on the analog input of the AD7878 allows the ADC to accurately convert an input sine wave of 6 V peak peak amplitude to 12 bit accuracy The input bandwidth of the track hold amplifier is much greater than the Nyquist rate of the ADC even when operated at its minimum conversion time The 0 1 dB cutoff frequency occurs typically at 500 kHz The track hold amplifier acquires an input signal to 12 bit accuracy in less than 2 s The operation of the track hold amplifier is transparent to the user The track hold amplifier goes from its tracking mode to its hold mode at the start of conversion on the rising edge of CONVST and returns to track mode at the end of conversion 10 ANALOG INPUT Figure 15 shows the AD7878 analog input The analog input range is 3 V into an input resistance of typic
11. 100kHz SAMPLE SIZE 7E6 CODES Ta 250 NORMALIZED CODE OCCURRENCE Toza Ey 2072 7095 cone Figure 13 AD7878 Histogram Plot AD7878 CONVERSION TIMING The track and hold on the AD7878 goes from track to hold mode on the rising edge of CONVST and the value of Viy at this point is the value which will be converted However the conversion actually sorts on the next rising edge of CLK IN after CONVST goes high If CONVST goes high within ap proximately 30 ns prior to a rising edge of CLK IN that CLK IN edge will not be seen as the first CLK IN edge of the con version process and conversion will not actually start until one CLK IN cycle later As a result the conversion time from CONVST to FIFO update will vary by one clock cycle de pending on the relationship between CONVST and CLK IN A conversion cycle normally consists of 56 CLK IN cycles assuming no read write operations which corresponds to a 7 As conversion time If CONVST goes high within 30 ns prior to a rising edge of CLK IN the conversion time will consist of 57 CLK IN cycles i e 7 125 ps This effect does not cause track hold jitter INTERNAL REFERENCE The AD7878 has an on chip temperature compensated buried Zener reference see Figure 14 that is factory trimmed to 3 V 1 Internally it provides both the DAC reference and the de bias required for bipolar operation The reference output is available REF OUT and is capable of providing
12. 3 V 25 Vss Analog negative supply voltage 5 V 5 26 TONVST Convert Start Logic input A low to high transition on this input puts the track hold into its hold mode and starts conversion The CONVST input is asynchronous to CLK IN and independent of CS DMWR and DMRD 27 RESET Reset Active low logic input A logic low sets the words in FIFO memory to 1000 0000 0000 and resets the ALFE output and status control register 28 CLKIN Clock Input TTL compatible logic input Used as the clock source for the A D converter The mark space ratio of this clock can vary from 35 65 to 65 35 PIN CONFIGURATIONS DIP PLCC LCCC 2 im RHI z E va a Fae ve wor 5 va m m aaa eL iai fal merour x ae ee ah ae SEO RE Blom same m G 5 ee aoe BS cote om ag REV A AD7878 ORDERING GUIDE Signal Data Temperature to Noise Access Package Model Range Ratio Time Options AD7878JN_ 0 C to 70 C 70 dB 57 ns AD7878AQ 25 C to 85 C 70dB 57 ns AD7878SQ_ 55 C to 125 C 70 dB 57 ns AD7878KN 0 C to 70 C 72 dB 57 ns AD7878BQ 25 C to 85 C 72dB 57ns AD7878LN 0 C to 70 C 72 dB 41 ns AD7878SE 55 C to 125 C 70dB 57ns AD7878JP_ 0 C to 70 C 704B 57ns AD7878KP 0 C to 70 C 72 dB 57 ns AD7878LP_ 0 C to 70 C 724B 4ns NOTES To order MIL STD 883 Class B processed parts ad
13. ACQUISITION BOARD Figure 23 shows the AD7878 in a data acquisition circuit that will interface directly to either the ADSP 2100 TMS32010 or the TMS32020 The corresponding printed circuit board PCB layout and silkscreen are shown in Figures 24 to 26 The only additional component required for a full data acquisi tion system is an antialiasing filter There is a component grid provided near the analog input on the PCB which may be used for such a filter or any other conditioning circuitry To facilitate this option a wire link labelled LK1 on the PCB is required on the analog input track This link connects the input signal to either the component grid or directly to the buffer amplifier driving the AD7878 analog input Microprocessor connections to the PCB can be made by either of two ways 1 96 contact 3 ROW Eurocard connector 2 26 contact 2 ROW IDC connector The 96 contact Eurocard connector is directly compatible with the ADSP 2100 Evaluation Board Prototype Expansion Con nector The expansion connector on the ADSP 2100 has eight decoded drip enable outputs labelled ECES to ECET ECE6 is used to drive the AD7878 CS input on the data acquisition board To avoid selecting onboard RAM sockets at the same time LK6 on the ADSP 2100 board must be removed In addi tion the expansion connector on the ADSP 2100 has four inter REV A rupts labelled EIRQS to EIRQO The AD7878 ALFL output connects to EIRQO The AD7878 and A
14. ANALOG LC MOS Complete 12 Bit DEVICES 100 kHz Sampling ADC with DSP Interface AD7878 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete ADC with DSP Interface Comprising Track Hold Amplifier with 2 ps Acquisition Time ano merour vn ve ve 6 G 7 ps A D Converter 3 V Zener Reference 8 Word FIFO and Interface Logic 72 dB SNR at 10 kHz Input Frequency Interfaces to High Speed DSP Processors e g cOnVET I ADSP 2100 TMS32010 TMS32020 mae FLT alla 41 ns max Data Access Time aooo I Low Power 60 mW typ ao APPLICATIONS O contaot sentiren Digital Signal Processing we Speech Recognition and Synthesis own Spectrum Analysis DO T aon High Speed Modems alr sae eR seater a7a78 DSP Servo Control ser cumin GS gt TopurrERS GENERAL DESCRIPTION aS The AD7878 is a fast complete 12 bit A D converter with a 0 9 amp versatile DSP interface consisting of an 8 word first in first out FIFO memory and associated control logic The FIFO memory allows up to eight samples to be digitized before the microprocessor is required to service the A D con verter The eight words can then be read out of the FIFO at maximum microprocessor speed A fast data access time of 41 ns allows direct interfacing to DSP processors and high speed 16 bit microprocessors PRODUCT HIGHLIGHTS 1 Complete A D Function with DSP Interface The A
15. D REV A AD7878 Establish a single point analog ground star ground separate from the logic system ground at Pin 22 AGND or as dose as possible to the AD7878 as shown in Figure 22 Connect all other grounds and Pin 7 AD7878 DGND to this single analog ground point Do not connect any other digital grounds to this analog ground point Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC so make the foil width for these tracks as wide as possible The use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise The circuit layouts of Figures 25 and 26 have both analog and digital ground planes which are kept separated and only joined to gether at the AD7878 AGND pin NOISE Keep the input signal leads to Vry and signal return leads from AGND Pin 22 as short as possible to minimize input noise coupling In applications where this is not possible use a shielded cable between the source and the ADC Reduce the ground circuit impedance as much as possible since any poten tial difference in grounds between the signal source and the ADC appears as an error voltage in series with the input signal ane d Hea p HHH PH Vos AGND Vss Vec DGN DIGITAL SurPCY aw c ANALOG REUNA picrrat AD7878 cRcUTRY Figure 22 Power Supply Grounding Practice DATA
16. D7878 provides the complete function for digitizing ac signals to 12 bit accuracy The part features an on chip track hold on chip reference and 12 bit A D converter The additional feature of an 8 word FIFO reduces the high soft ware overheads associated with servicing interrupts in DSP An on chip status control register allows the user to program the processors effective length of the FIFO and contains the FIFO out of range FIFO empty and FIFO word count information 2 Dynamic Specifications far DSP Users The AD7878 is fully specified and tested for ac parameters The analog input of the AD7878 has a bipolar range of 3 V including signal to noise ratio harmonic distortion and The AD7878 can convert full power signals up to 50 kHz and is intermodulation distortion Key digital timing parameters fully specified for dynamic parameters such as signal to noise are also tested and specified over the full operating tempera ratio and harmonic distortion ture range The AD7878 is fabricated in Linear Compatible CMOS 3 Fast Microprocessor Interface LC MOS an advanced mixed technology process that com Data time of 41 ns is the fastest ever achieved in a bines precision bipolar circuits with low power CMOS logic monolithic A D converter and makes the AD7878 compat The part is available in four package styles 28 pin plastic and ible with all modern 16 bit microprocessors and digital hermetic dual in line package DIP l
17. DSP 2100 data lines are aligned for left justified data transfer The 26 way IDC connector contains all the necessary contacts for both the TMS32010 and TMS32020 There are two switches on the data acquisition board that must be set to en able the appropriate interface configuration see Table III The interface connections for the TMS32010 32020 and IDC signal contact numbers are shown in Table IV and Figure 23 Note the AD7878 CS input must be decoded from the address bus prior to the AD7878 evaluation board for the TMS320XX interfaces Connections to the analog input Vry and the CONVST input are made via two BNC sockets labelled SKT1 and SKT2 on the silkscreen If the CONVST input is derived from either the microprocessor or ADC clock the effects of clock noise cou pling will be reduced Table III AD7878 PCB Switch Settings SWITCH SETTING Microprocessor sw1 sw2 ADSP 2100 A A TMS32010 B A TMS32020 B B POWER SUPPLY CONNECTIONS The PCB requires two analog supplies and one 5 V digital sup ply Connections to the analog supplies are made directly to the PCB as shown on the silk screen in Figure 24 The connections are labelled V and V and the range for both of these supplies is 12 V to 15 V Connection to the 5 V digital supply is made through either of the two microprocessor connectors The 5 V and 5 V analog power supplies required by the AD7878 are generated from two voltage regulators on the V and
18. E Setup Time o o o ns min CS to DMRD REGISTER ENABLE Hold Time te 4s 60 60 ns min DMRD Pulse Width 50 50 50 is max t 16 16 16 ns min ADDO to DMRD REGISTER ENABLE Setup Time t o o o ns min ADDO to DMRD REGISTER ENABLE Hold Time te 41 57 57 ns min Data Access Time after DMRD tho 5 5 5 ns min Bus Relinquish Time 4s 45 45 ns max ti 42 a2 55 ns min REGISTER ENABLE Pulse Width 50 50 50 is max ta 20 20 30 ns min Data Valid to REGISTER ENABLE Setup Time ts 10 10 10 ns min Data Hold Time after REGISTER ENABLE ue a 57 57 ns min Data Access Time after BUSY tueser 2 CLKIN Cycles 2CLKIN Cycles 2CLKINGycles min RESET Pulse Width NOTES Timing Specifications in bold print are 100 production tested All other times are sample tested at 25 C to ensure compliance All input signals are specified with t f 5 ns 10 to 90 of 5 V and timed from a voltage level of 1 6 V ty and tya are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0 8 V or 2 4 V uo is defined as the time required for the data lines to change 0 5 V when loaded with the circuits of Figure 2 Specifications subject to change without notice pi ABSOLUTE MAXIMUM RATINGS T 425 C unless otherwise stated Vpn to DGND 0 3 Vto 7V pen pen Vee to DGND 0 3 Vto 7V T Vs to DGND 0 3 Vto 7V Sek Z 50pF 50pF Tooti Veo resci 0 3 V to 0 3
19. V power supply inputs IC3 and IC4 in Figure 23 COMPONENT LIST IC1 AD711 Op Amp 1C2 AD7878 Analog to Digital Converter 13 MC78L05 5 V Regulator Ic4 MC79L05 5 V Regulator IC5 74HC00 Quad NAND Gate IC6 74HC04 Hex Inverter 1C7 74HC02 Quad NOR Gate SWI Single Pole Double Throw sw2 Double Pole Double Throw LKI Wire Link for Analog Input Cl C3 C5 C7 C9 C11 C13 C15 C2 C4 C6 C8 C10 C12 C14 C16 10 pF Capacitors 0 1 pF Capacitors RI R2 10 KQ Resistors SKT1 SKT2 BNC Sockets SKT3 26 Contact 2 Row IDC Connector SKT4 96 Contact 3 Row Eurocard Connector Not required for ADSP 2100 Interface 13 AD7878 ADSP 2100 CONNECTOR s ani cs as 427 823 an DIGITAL GND SPEEDBLOC CONNECT NO t 25 26 mon aa z i Figure 23 Data Acquisition Circuit Using the AD7878 oL 00000000000000 ecco ooooooo oo000 0000000000000000 e000 o 0000000000000000 0000000000000000 ooo0o0000 ocoo0o w CHD F AD7878 BOARD C14 C13 C12C11 i RR SKT4 k ia Ics Ics ooooooo 0000550 su CLLLLLLLLLLILIJ sea era ooooooo gif 1 B a oo00ce CS R2 RI Figure 24 PCB Silkscreen for Figure 23 14 REV A
20. ally 15 kQ The designed code transitions occur midway between successive integer LSB values i e 1 2 LSB 3 2 LSBs 5 2 LSBs FS 3 2 LSBs The output code is 2s complement binary with 1 LSB FS 4096 6 V 4096 1 46 mV The ideal input output transfer function is shown in Figure 16 AD7878 TmAcKHOLD AMPLIFIER INPUTRANGE av Yw 75o INTERNAL COMPARATOR Tsa To iNTERNAL SV REF ADDITIONAL PINS OMITTED FOR CLARITY Figure 15 AD7878 Analog Input oureur coe omom on no eoi a i 000 010 ae i 00 00 i5 i 2 C 000 000 i T j 25 Causa maom i mno 1 1 eS i 7 tse 100 001 ie 100 000 VSB 3095 pp a Vw INPUT VOLTAGE Figure 16 Input Output Transfer Function OFFSET AND FULL SCALE ADJUSTMENT In most Digital Signal Processing DSP applications offset and full scale error have little or no effect on system performance Offset error can always be eliminated in the analog domain by ac coupling Full scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC Some applications may require that the input signal span the full analog input dynamic range and accord ingly offset and full scale error will have to be adjusted to zero Where adjustment is required offset must be adjusted before full scale error This is achieved by trimming the
21. ch word can also be determined and the analog input adjusted accordingly before returning to the main program Note there is no need to check the out of range status if the analog input is always assured to be within range 12 Number of Clock Cycles ADSP 2100 TMS32010 TMS32020 Non Applicable 2 ps min 2 ps min 2 ps min 2min 250 ns min 400 ns min 400 ns min 57 max 7 125 js max 11 14 ps max 11 14 ps max NOTES TADSP 2100 Clock Frequency 2TMS320XX Clock Frequency APPLICATION HINTS Good printed circuit board PCB layout is as important as the overall circuit design itself in achieving high speed A D perfor mance The AD7878 is required to make bit decisions on an LSB size of 1 465 mV To achieve this the designer has to be conscious of noise both in the ADC itself and in the preceding analog circuitry Switching mode power supplies are not recom mended as the switching spikes will feed through to the com parator causing noisy code transitions Other concerns are ground loops and digital feedthrough from microprocessors These factors influence any ADC and a proper PCB layout that minimizes these effects is essential for best performance LAYOUT HINTS Ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible Take care not to run any digital track alongside an analog signal track Guard screen the analog input with AGN
22. d 883B to part number Contact our local sales office for military data sheet Analog Devices reserves the right to ship either ceramic D 28 packages or cerdip Q 28 hermetic packages E Leadless Ceramic Chip Carrier N Plastic DIP P Plastic Leaded Chip Carrier Q Cerdip Available to 883B processing only STATUS CONTROL REGISTER The status control register serves the dual function of providing control and monitoring the status of the FIFO memory This register is directly accessible through the data bus DB11 DB0 with a read or write operation while ADDO is high A write operation to the status control register provides control for the ALFL output bus interface and FIFO counter reset This is normally done on power up initialization The FIFO memory address pointer is incremented after each conversion and com pared with a preprogrammed count in the status control regis ter When this preprogrammed count is reached the ALFL output is asserted if the ENAF control bit is set to zero This ALFL can be used to interrupt the microprocessor after any predetermined number of conversions between 1 and 8 The status of the address pointer along with sample overrange and ALFL status can be accessed at any time by reading the status control register Note reading the status control register does not cause any internal data movement in the FIFO memory Status information for a particular word should be read from the status reg
23. e second rising edge of CLK IN after CONVST goes high The AD7878 data outputs are now enabled and the microprocessor is released from its WAIT state allowing it to complete its read write operation to the AD7878 The microprocessor cycle time for the read write operation is extended by the CONVST pulse width plus two CLK IN peri ods worst case This is the maximum length of time for which BUSY can be low Assuming a CONVST pulse width of two CLK IN periods and an 8 MHz CLK IN the instruction cycle is extended by 500 ns maximum Figure 9 shows the timing diagram for an extended read operation In a similar manner a write operation will be extended if it occurs during a CONVST pulse For processors that cannot be forced into a WAIT state writing a logic 1 into DB5 of the status control register allows the out put latches to be enabled while BUSY is low In this case BUSY still goes low as before but it would not be used to stretch the read write cycle and the instruction cycle continues as normal see Figures 6 and 8 PAN AP ase w ta J cle paris tps ay ge eee fo aooo tek wm Ca Figure 9 Extended Read Operation AD7878 DYNAMIC SPECIFICATIONS The AD7878 is specified and 100 tested for dynamic perfor mance specifications rather than for traditional de specifications such as Integral and Differential Nonlinearity These ac specifi cations provide information on the AD7878 s effect on the spec
24. e budget allowed Table II AD7878 Throughput Rate CONVST Conversion TIH Acquisition Pulse Width Time i Time ADDITIONAL PINS OMITTED FOR CLARITY Figure 21 AD7878 MC68000 Interface Typical AD7878 Microprocessor Operating Sequence After power up or reset the status control register is initialized by writing to the AD7878 This enables the ALFL output if required for a microprocessor interrupt and sets the effective word length of the FIFO memory The processor now executes the main body of the program while waiting for an ADC interrupt This interrupt will occur when the preprogrammed number of samples are collected in the FIFO memory The interrupt ser vice routine first interrogates DB5 FOOR of the status control register to determine if any sample in the FIFO memory is out of range If all data samples are valid then the program pro ceeds to read the FIFO memory If on the other hand at least one sample is out of range then an overrange routine is called There are many actions that can be taken by the out of range routine the selection of which is application dependent One option is to ignore all the current samples residing in the FIFO memory reinitialize the status control register and return to the main body of the program Another option is to check the indi vidual out of range status of each word in the FIFO memory and to discard the invalid ones The underrange or overrange status of ea
25. e no bus activity while the track hold goes from track to hold mode see Extended Read Write section The CONVST input must stay low for at least two CLK IN periods The track hold amplifier switches from the track to hold mode on the rising edge of CONVST and conversion is also initiated at this point The BUSY output returns high after the CONVST input goes high and the ADC begins its successive approximation routine Once conversion has been initiated another conversion start should not be attempted until the full conversion cycle has been completed Figure 5 shows the taming diagram for the conversion start In applications where precise sampling is not critical the CONVST pulse can be generated from a microprocessor WR or RD line gated with a decoded address different from the AD7878 CS address Note that the CONVST pulse width must be a minimum of two AD7878 CLK IN cycles TRACK TO HOLD alt i TRANSITION ausY Figure 5 Conversion Start Timing Diagram READ WRITE OPERATIONS The AD7878 read write operations consist of reading from the FIFO memory and reading and writing from the status control register These operations are controlled by the CS DMRD DMWR and ADDO logic inputs A description of these operations is given in the following sections In addition to the basic read write operations there is an extended read write operation This can occur if a read write operation occurs during a CONVST pulse Thi
26. eadless ceramic chip signal processors carrier LCCC or plastic leaded chip carrier PLCC REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its Use nor for any infringements of patents or other rights of third parties One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A which may result from its use No license is granted by implication or Tel 617 329 4700 World Wide Web Site http www analog com otherwise under any patent or patent rights of Analog Devices Fax 617 326 8703 Analog Devices Inc 1997 AD7878 SPECIFICATIONS Won 5 V 5 Vee 45V 5 Vss 5V 5 AGND DGND OV fex 8 MHz All Specifications Tun to Tuay unless otherwise noted J A K L B s Parameter Versions Versions Version Units Test Conditions Comments DYNAMIC PERFORMANCE Signal to Noise Ratio SNR 25 C 70 72 70 dB min Vix 10 kHz Sine Wave fsampue 100 kHz Tun to Tmax 70 7 70 dB min Typically 71 5 dB for 0 lt Vy lt 50 kHz Total Harmonic Distortion THD 80 80 78 dB max Vin 10 kHz Sine Wave fsampre 100 kHz Typically 86 dB for 0 lt Viy lt 50 kHz Peak Harmonic or Spurious Noise 80 80 78 dB max Vin 10 kHz fsampre 100 kHz Typically 86 dB for 0 lt Vry lt 50 kHz Intermodulation Distortion IMD Second Ord
27. ent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING amaa SENSITIVE DEVICE REV A AD7878 PIN FUNCTION DESCRIPTION Number Mnemonic Function 1 ADDO Address Input This control input determines whether the word placed on the output data bus during a read operation is a data word from the FI the FIFO while a logic high selects the contents of the register see Status Control Register section RAM or the contents of the status control register A logic low accesses the data word from Location 0 of 2 Ts Chip Select Active low logic input The device is selected when this input is active 3 DMWR Dam Memory Write Active low logic input DMWR is used in conjunction with CS low and ADDO high to write data to the status control register Corresponds to DMWR ADSP 2100 RAW MC68000 TMS32020 WE TMS32010 4 DMRD Data Memory READ Active low logic input DMRD is used in conjunction with CS low to enable the three state output buffers Corresponds directly to DMRD ADSP 2100 DEN TMS32010 5 BUSY Active Low Logic Output This output goes low when the ADC receives a CONVST pulse and remains low until the track hold gone into its hold mode The three state drivers of the AD7878 can be disabled while the BUSY signal is low see Extended READ WRITE sectio
28. er Terms 80 78 dB max fa 9 kHz fb 9 5 kHz fsamp e 50 kHz Third Order Terms 80 78 dB max fa 9 kHz fb 9 5 kHz fsampre 50 kHz Track Hold Acquisition Time 2 2 fis max See Throughput Rate Section DC ACCURACY Resolution 12 12 12 Bits Minimum Resolution for Which No Missing Codes are Guaranteed 12 12 12 Bits Relative Accuracy 41 2 tia 41 2 LSB yp Differential Nonlinearity 12 12 12 LSBryp Bipolar Zero Error 6 6 6 LSB max Positive Full Scale Error 6 6 6 LSB max Negative Full Scale Error 6 6 6 LSB max ANALOG INPUT Input Voltage Range 3 43 3 Volts Input Current 550 550 550 uA max REFERENCE OUTPUT REF OUT 3 3 3 Vnom REF OUT Error 25 C 10 10 10 mV max Tur to Tmax 15 15 15 mV max Reference Load Sensitivity AREF OUT AD 41 41 1 mV max Reference Load Current Change 0 A 500 pA Reference Load Should Not Be Changed During Conversion LOGIC INPUTS Input High Voltage Vinn 24 24 24 Vmin Veo 5 V 5 Input Low Voltage Vist 08 08 408 Vmax Voc 5 V 5 Input Current Ing 10 10 10 pA max Vin 0 to Vec Input Capacitance Cry 10 10 10 pF max LOGIC OUTPUTS Output High Voltage Vou 42 7 27 427 Vimin Tsource 40 HA Output Low Voltage Vor 04 04 04 Vmax Tonic 1 6 mA DB11 DB0 Floating State Leakage Current 10 f io 10 HA max Floating State Output Capacitance 15 15 15 15 pF max CONVERSION TIME 7 7125 7 7 125 7 7 125 ps min ps max Assuming No External Read W
29. evels 0 to 7 has to be encoded onto the IPL2 IPL0 inputs This is achieved with a 74148 encoder in Figure 21 interrupt Level 1 is taken for example purposes only The MC68000 places this inter rupt level on address bits A3 to A1 at the start of the interrupt service routine Additional logic is used to decode this interrupt level on the address bus and the FC2 FCO outputs to generate a VPA signal for the MC68000 This results in an autovectored interrupt the start address for the service routine must be loaded into the appropriate auto vector location during initial ization For further information on the 68000 interrupts con sult the 68000 User s Manual 11 AD7878 The MC68000 AS and R W outputs are used to generate sepa rate DMWR and DMRD inputs for the AD7878 As with the three interfaces previously described WAIT states are inserted if a read write operation is attempted while the track hold amplifier is going from the track to the hold mode cock INPUT ee ax ASA a2 aa ADORESS BUS w5 E Tada mmm messooo vea DBD convST cox Fea a AD7878 oTa ao 78188 ois Data sus 5 pe xr RESET THROUGHPUT RATE The AD7878 has a maximum specified throughput rate sample rate of 100 kHz This is a worst case test condition and specifi cations apply for reduced sampling rates
30. his bit indicates that at least one sample in the FIFO memory is out of range Writing a 0 to this bit prevents the data bus from becoming active while BUSY is low regardless of the state of CS and DMRD DB4 FEMP FIFO Empty Read Only Reading a 1 indicates there are no samples in the FIFO memory When the FIFO is empty the internal ripple down effects of the FIFO are disabled and fur ther reads will continue to access the last valid data word in Location 0 DB3 SOOR Sample out of Range Read Only Reading a 1 indicates the next sample to be read is out of range i e the sample in Location 0 of the FIFO DB DB0 FCN2 FCN0 FIFO Word Count Read Only The value read from these bits indicates the number of samples in the FIFO memory For example reading 011 from these bits indicates that Location 0 through Location 3 contains valid data Note reading all 0s indicates there is either one word or no word in the FIFO memory in this case the FIFO Empty determines if there is no word in memory FCN2 is the most significant bit Table I Status Control Bit Function Description BIT LOCATION DBi1 DB10 DB9 DBs DB7 DBs pBs pBs DB DB2 DBI DBO STATUS INFORMATION READ ALFL AFC2 AFCO FEMP SOOR FCN2 FCN1 FCNo CONTROL FUNCTION WRITE X AFC2 AFCO x x x x x RESET STATUS 1 o o 1 o o o o X DON T CARE REV A AD7878 INTERNAL FIFO MEMORY The inter
31. input Frequencies SIGNAL AMPUTUDE 38 g Figure 12 AD7878 IMD Plot Histogram Plot When a sine wave of a specified frequency is applied to the Viy input of the AD7878 and several million samples are taken it is possible to plot a histogram showing the frequency of occur rence of each of the 4096 ADC codes If a particular step is wider than the ideal 1 LSB width then the code associated with that step will accumulate more counts than for the code for an ideal step Likewise a step narrower than ideal will have fewer counts Missing codes are easily seen in the histogram plot because a missing code means zero counts for a particular code Large spikes in the plot indicate large differential nonlinearity Figure 13 shows a histogram plot for the AD7878KN with a sampling frequency of 100 kHz and an input frequency of 25 kHz For a sine wave input a perfect ADC would produce a cusp probability density function described by the equation where A is the peak amplitude of the sine wave and p V is the probability of occurrence at a voltage V The histogram plot of Figure 13 corresponds very well with this cusp shape The ab sence of large spikes in this plot indicates small dynamic differ ential nonlinearity the largest spike in the plot represents less than 1 4 LSB of DNL error The AD7878 has no missing codes under these conditions since no code records zero counts INPUT FREQUENCY 10KHz SAMPLE FREQUENCY
32. ister before the data word is read from the FIFO memory STATUS CONTROL REGISTER FUNCTION DESCRIPTION DB11 ALFL Almost Full Flag Read only This is the same as Pin 6 ALFL output status A logic low indicates that the word count in the FIFO memory has reached the preprogrammed count in bit locations DB10 DB8 ALFL is updated at the end of conversion DB10 DBS8 AFC2 AFC0 Almost Full Word Count Read Write The count value deter mines the number of words in the FIFO memory which will cause ALFL to be set When the FIFO word count equals the programmed count in these three bits both the ALFL output and DB11 of the status register are set to a logic low For ex ample when a code of 011 is written to these bits ALFL is set when Location 0 through Location 3 of the FIFO memory contains valid data AFC2 is the most significant bit of the word count The count value can be read back if required DB7 ENAF Enable Almost Full Read Write Writing a 1 to this bit disables the ALFL output and status register bit DB11 DB6 FOVRIRESET FIFO Overrun RESET Read Write Reading a 1 from this bit indicates that at least one sample has been discarded because the FIFO memory is full When the FIFO is full i e contains eight words any further conversion results will be lost Writing a 1 to this bit causes a system RESET as per the RESET input Pin 27 DBs FOORIDISO FIFO Out of RANGE Disable Outputs Read Write Reading a 1 from t
33. m nor n is equal to zero For example the second order terms include fa fb and fa fb while the third order terms include 2fa fb 2fa fb fa 2fb and fa 2fb Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used the second and third order terms are of different significance The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified separately The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms am plitude of the fundamental expressed in dBs Intermodulation distortion is calculated using an FFT algorithm but in this case the input consists of two equal amplitude low distortion sine waves Figure 12 shows a typical IMD plot for the AD7878 Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum up to FS 2 and excluding de to the rms value of the fundamental Normally the value of this specification will be determined by the largest harmonic in the spectrum but for parts where the harmonics are buried in the noise floor the largest peak will be a noise peak REV A
34. n This is achieved by writing a logic 0 to DB5 DISO of the status control register Writing a logic 1 to DB5 of the status control register allows data to be accessed from the AD7878 while BUSY is low 6 ALL FIFO Almost Full A logic low indicates that the word count i e number of conversion results in the FIFO memory has reached the programmed word count in the status control register ALFL is updated at the end of each conversion The ALFL output is reset to a logic high when a word is read from the FIFO memory and the word count is less than the preprogrammed word count It can also be set high by writing a logic 1 to DB7 ENAF of the status control register 7 DGND Digital Ground Ground reference for digital circuitry V Digital supply voltage 5 V 5 Positive supply voltage for digital circuitry DBI Data Bit 11 MSB Three state TTL output Coding for the data words in FIFO RAM is twos complement 10 15 DB10 DB5 Data Bit 10 to Data Bit 5 Three state TTL inpuv outputs 16 19 DB4 DB1 Data Bit 4 to Data Bit 1 Three state TTL outputs 20 DBO Data Bit 0 LSB Threc state TTL output 21 Von Analog positive supply voltage 5 V 5 22 AGND Analog Ground Ground reference for track hold reference and DAC 23 REF OUT Voltage Reference Output The internal 3 V analog reference is provided at this pin The external load capability of the reference is 500 pA 24 Vw Analog Input Analog input range is
35. nal FIFO memory of the AD7878 consists of eight memory locations Each word in memory contains 13 bits of information 12 bits of data from the conversion result and one additional bit which contains information as to whether the 12 bit result is out of range or not A block diagram of the AD7878 FIFO architecture is shown in Figure 3 siaii LOCATON T LOCATON S LOCATIONS LOCATION Fg ADDRESS PANTER WeaTions LOCATON LOCATION 7 gi ee TOEATION T Abo BMRG OAR Cs Figure 3 Internal FIFO Architecture The conversion result is gathered in the successive approxima tion register SAR during conversion At the end of conversion this result is transferred to the FIFO memory The FIFO ad dress pointer always points to the top of memory which is the uppermost location containing valid data The pointer is incre mented after each conversion A read operation from the FIFO memory accesses data from the bottom of the FIFO Location 0 On completion of the read operation each data word moves down one location and the address pointer is decremented by one Therefore each conversion result from the SAR enters at the top of memory propagates down with successive reads until it reaches Location 0 from where it can be accessed by a micro processor read operation The transfer of information from the SAR to the FIFO occurs in synchronization with the AD7878 input clock CLK
36. of Bits The formula given in 1 relates the SNR to the number of bits Rewriting the formula as in 2 it is possible to get a measure of performance expressed in effective number of bits N The effective number of bits for a device can be calculated directly from its measured SNR _SNR 1 76 6 02 2 REV A AD7878 Figure 11 shows a typical plot of effective number of bits versus frequency for an AD7878KN with a sampling frequency of 100 kHz The effective number of bits typically falls between 11 7 and 11 85 corresponding to SNR figures of 72 2 and 73 1 dB 20 SAMPLE FREQUENCY 100kHz EFFECTIVE NUMBER OF BITS Ta 25C INPUT FREQUENCY kHz ad Figure 11 Effective Number of Bits vs Frequency Harmonic Distortion Harmonic Distortion is the ratio of the rms sum of harmonics to the fundamental For the AD7878 Total Harmonic Distortion THD is defined as VEETEE PES ES 6 THD 20log 7 i where V3 is the rms amplitude of the fundamental and V2 Vs Vi V5 and V are the rms amplitudes of the second to the sixth harmonic The THD is also derived from the FFT plot of the ADC output spectrum Intermodulation Distortion With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 etc Intermodulation terms are those for which neither
37. rite Operations 7 9 250 7 9 250 7 9 250 us min ps max Assuming 17 External Read Write Operations See Internal Comparator Timing Section POWER REQUIREMENTS Vov 5 5 5 V nom 5 for Specified Performance Veo 5 5 5 V nom 5 for Specified Performance Vss 5 5 5 Vnom 5 for Specified Performance Iov 13 13 13 mA max CS DMWR DMRD lee 100 100 100 HA max Cs DMWR DMRD Tis 6 6 6 mA max TS DMWR DMRD Power Dissipation 95 5 95 5 95 5 mW max Typically 60 mW NOTES Temperature range as follows J K L versions 0 C to 70 C A B versions Viy 3 V See Dynamic Specifications section SNR calculation includes distortion and noise components Measured with respect to the Internal Reference 25 C wo 85 C S For capacitive loads greater than 50 pF a series resistor is required see Internal Reference section Sample tested 25 C to ensure compliance Specifications subject to change without notice 55 C wo 125 C REV A AD7878 TIMING CHARACTERISTICS m V 5 Vec 5V 5 Vss 5 V 5 Limit at Tums Tuax Limit at Tums Tuax Limit at Tuns Tmax Parameter L Grade 0 K A B Grades S Grade Units Conditions Comments A 65 65 75 ns max CLK IN to BUSY Low Propagation Delay u 65 65 75 ns max CLK IN to BUSY High Propagation Delay 5 2 CLKIN Cycles 2 CLKIN Cycles 2 CLKIN Cycles min CONVST Pulse Width te o o 0 ns min CS to DMRD REGISTER ENABL
38. s extended read write is intended for use with microproces sors that can be driven into a WAIT state and the scheme is recommended for applications where an external timer controls the CONVST input asynchronously to the microprocessor read write operations Basic Read Operation Figure 6 shows the timing diagram for a basic read operation on the AD7878 CS and DMRD going low accesses data from either the status control register or the FIFO memory A read REV A ln m ommo ty ta bs pas ta ADDO ono je of jeto N Figure 6 Basic Read Operation Basic Write Operation A basic write operation to the AD7878 status control register consists of bringing CS and DMWR low with ADDO high In ternally these signals are gated with CLK IN to provide an internal REGISTER ENABLE signal see Figure 7 The pulse width of this REGISTER ENABLE signal is effectively the overlap between the CLK IN low time and the DMWR pulse This may result in shorter write pulse widths data setup times and data hold times than those given by the microprocessor The timing on the AD7878 timing diagram of Figure 8 is there fore given with respect to the internal REGISTER ENABLE signal rather than the DMWR signal REGISTER ENABLE li Aa Neel EQUIVALENT CCT ONLY ASSUME Ons PROP DELAY STATUSICONTROL g REGISTER pert 080 28 vso AD7878 Figure 7 DMWR Internal Logic REGISTER ENABLE
39. version control allowing the ADC to sample the analog input asynchronously to the microprocessor The AD7878 ALFL output interrupts the processor when the FIFO preprogrammed word count is reached The processor then reads the conversion results from the AD7878 internal FIFO memory a p busy food en Bata nus 5 Figure 18 AD7878 ADSP 2700 Interface REV A ew Figure 19 AD7878 TMS32020 Interface The interfaces to the ADSP 2100 and the TMS32020 gate the AD7878 CS and the BUSY to provide a signal which drives the processor into a wait state if a read write operation to the ADC is attempted while the ADC track hold amplifier is going from the track to the hold mode This avoids digital feedthrough to the analog circuitry The TMS32020 does not have separate RD and WR outputs to drive the AD7878 DMWR and DMRD inputs These are generated from the processor STRB and R W outputs with the addition of some logic gates Figure 20 AD7878 TMS32020 Interface AD7878 M CC8000 This interface also uses an external timer for conversion control as described for the previous three interfaces It is discussed separately because it needs extra logic due to the nature of its interrupts The MC68000 has eight levels of external interrupt When interrupting this processor one of these l
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