hardwaresoftware00mcca - Calhoun: The NPS
Contents
1. 1 II PACED DATA ACQUISITION SYSTEM DESCRIPTION J A GENERAL DESCRIPTION 13 B SYSTEM SOFTWARE 2 5 l RTE IVB Operating System 15 2 System Test and Operation Program l6 C SYSTEM HARDWARE uy Hewlett Packard 21 MX Computer 7 2 Hewlett Packard 5610 A A D Converter 18 3 PACER 19 III CHANGES TO PACER HARDWARE 20 IV CHANGE TO ACQUISITION SOFTWARE 22 A METHODS OF INPUT OUTPUT 22 B INCORPORATION OF DMA 29 V RESULTS 24 A LINEARITY TEST 24 B AUTO LOCK ON TEST 25 25 VI CONCLUSIONS AND RECOMMENDATIONS 2 APPENDIX A HARDWARE DESIGN DETAILS 43 APPENDIX B SOFTWARE DETAILS 47 APPENDIX C PACED DATA ACQUISITION USERS MANUAL 61 LIST OF REFERENCES 68 TA DAS 11581 2 222200000 69 EI NETT LIST Or TABLES o 29 38115 121721 120 EEE Cena SSO2. mmer Pp RSEN 1 H nn 2 SLTOA gt LNdLNO 42 APPENDIX A HARDWARE DESIGN DETAILS A l INTRODUCTION The PLL circuit is shown in detail in Figure 4 A list ing of component values is found in Table III TWO Separate PLL circuits were designed and incorporated into the hardware one foreach of two frequency ranges This was done in order to cover a very large total frequency range while maintaining fast response to changes in frequency Ref 7 In the following sections the design procedure which was fol lowed is documented A 2 DIGITAL PHASE LOCK LOOP CMOS DESIGN The CD4046 digital PLL requires four areas of external design Ref 7 1 Selecting the timing capacitor Ci which determines the center of the operating frequency range 2 Selecting the values of Ro 211 ato of Ry to 3 which determine the upper and lower bounds of the lock range 3 Selecting the ratios of R4 to Rg 3 to C5 and their values which contribute to determine the damping ratio and settling time of the second order feedback loop 43 4 Interfacing the CMOS integrated circuit design with the TTL integrated circuits already in the PACER These areas are detailed in the following sections Timing Capacitor In the following discussion figures and pages are quoted with respect t
3. 30 30 MS RSE SIDA CER eea a PAER OMI Program A2D 65 0 E 2 et v2 FIGURES Paced Data Acquisition System Components B Schematic of PACER 52 Original and Revised PACER Circuits 004046 PLE Circuit Detail 34 EXEC CALL Flow Diagram 35 PACER Test Chassis 36 PACER Front Panel 3 7 Pulse Trains at Counter Bl for Analog amp Digital PLL Circuits 7727727227777 358 Paced I O Request Flow Diagram 39 Data Acquisition and Test Equipment 40 Ramp Test Data from Original PACER 41 Ramp Test Data from Revised PACER 42 Data Acquisition and Test Equipment 66 9 Connections Tor Test Data Acquisition 67 LIST OF SYMBOLS AND ABBREVIATIONS SYMBOLS A Driver Amplifier B counter Comparator F Buffer Amplifier AND gate L 255211206721125 Flop D Delay Flip Flop Inverter 175 PACER I O controller port llo EY 1 1 7 9 controller port ABBREVIATIONS A D Analog to Digital I O Output RTE Real Time Executive l Rev Once per Revolution IBI Once per Blade Passage PLL Phase Lock Loop CMOS Complementa
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5. 0 naing tius was 13 Re TT lt gt gt gt gt Z ENP Ie 2 gt a e IS 5 OC Nr CTOS 3X x X 160 EORMATCASX gt gt gt END OF RUNS 7 END SURR ONE 5 CICHAN LAVG TSURV IMODE TPAIR CIPOSI 1 N ee ee ee e 9 1 s DATA ACQISITION 5 TNE REAL SRYPT C256 DIMENSTON IFUFF 99 TIME S NU CALL EXEC CLE TTIME WRITE 4 90 CS 6 90 08 40 THES IS TEST 12 RUN UN JULIAN A Pru 14 7 6 15 EQ 1 GO TO 120 SINGLE POINT ACQUISITION IRCADESPSAXCTIPATR 1 17 IE 1 EQ GO T 100 5 1000008 400 CALL EXEC 3 19 CALL EXEC 1 49 TRPM 4 y EO DEO CALL FXEG 4 20 IRUFE N LCHAN 0 DO 110 i 4 TAUG 10 RRUEF SRE E LOOT I22 32768 PTDATA RION F T AVI 0 TO 195 Q t t t t t 8 9 98 9 8 Q q 9 9 5 9 t 9 Q 18 9 b t SURVEY ACROSS BLADE PAIR 65201 1511100 LN Ir TDEES EO D C TO 125 0 1 0 5 11 J 1 27 42 PORES ss 4 3 DO 140 171 256 BL 7236 KCI
6. 4 ern o Omr r 0 cm T 0 mv OF 6 odTXuae o SS E lt wt CN pra Ce Ca 0 gt gt gt 040002222220 02022222202522o02a JOL x IJ2 00 JG Z OI IFO OO 230 Lun 20 3723 0 262 F en O X 3 3 wv a lt lt gt tn CO 2 ar Qa TORN OC ZML in Od OTE bebe IE Q J O 00305 4 e 0 OCAZ3 HACEN DO HOJI TOON DA c 00 O 0302 TOON ORS 0Jro TIN ON C eR TOSIN 0 0 2 0 ES POS P 00 00 00 00 0250 0200205520061060 02 OO OO c ett 7 aM oi AV O O O 5 O c5 O 2 C 5 OO 00 c5 C2 OO OO OO O 2 C5 c5 O O 60 APPENDIX C PACED DATA ACQUISITION USERS MANUAL The two sections of this Appendi
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9. Digital PLL Circuits 38 VIVO 1v11910 a y 019 6 160 MOTAI a23sanbay O I pooed U89 90413 135 110107 32 OV1d 2 111109 13S 30730 31 Q v am 6 10 In 0 AJONIN 32 313 3 14083 3ZV WI LINI 31 1 JOS ANOS 39 20301010177 155 pue 11 Ol 33151 J ere lt w w a F h yo Uoc J3NOLLIONOO 1VNOIS 5 vg a or ret vo m are U31101d VU Me 4341 8 021161 E 9 e eo ae JOLVIINIO VNOIS VNIARO3 L 27 O 211 HdOVd 11151130 353 eJeq 35837 dwey 371116 3 SLNNOD 0111901 363 g 6 g 8 g 9 g B 2 D 7 0 0 ot STOA Ladino 3557 41 211093 pesrAeM 11033 eJeq 35253 duey 12 20D ES SLNNOD NOILISOI 43 BZT pert 6 2 8 9 0 2 8 0 9 0 0 pa II TO ms a al a TDL TO Te II IT ta TI o ZIEL p al 2 rr A gt er gt 5 x DAA AAA gt un IA AAA eee mo Se ean way 9 o mM mm s m m a mn
10. HARDWARE AND SOFTWARE IMPROVEMENTS TO A PACED DATA ACQUISITION SYSTEM FOR TURBOMACHINES Anthony MeCarville NAVAL POSTGRADUATE SCHOOL Monterey California ESS HARDWARE AND SOFTWARE IMPROVEMENTS TO A FACED DATA ACQUISITION SYSTEM FOR TURBOMACHINES by Patrick Anthony McCarville June 1981 Thesis Advisor R P Shreeve Approved for public release distribution unlimited SECURITY CLASSIFICATION OF THIS PAGE When Data Entared REPORT DOCUMENTATION PAGE 2 GOVT ACCESSION NO READ INSTRUCTIONS BEFORE COMPLETING FORM 5 TYPE OF REPORT amp PERIOO COVERED Master s Thesis 4 TITLE and Subtitle Hardware and Software Improvements to a Paced Data Acquisition System for une P 2 uurb5bomachines ORMING ORG REPORT NUMBER 7 AUTHOR a 6 CONTRACT OR GRANT NUMBER e Patrick Anthony McCarville 9 PERFORMING ORGANIZATION NAME AND ADORESS 10 PROGRAM ELEMENT PROJECT TASK AREA WORK UNIT NUMBERS 12 REPORT DATE June 1 3 69 Naval Postgraduate School Monterey California 93940 CONTROLLING OFFICE NAME AND ADDRESS Naval Postgraduate School Monterey California 93940 it 13 NUMBER OF PAGES 18 SECURITY CLASS of thia report MONITORING AGENCY MAME ADORESS II dilferent from Controlling Office Naval Postgraduate School Monterey California 93940 Unclassified Sa 5861 ASSIFICATION DOWNGRADI
11. CNTRL 50 RTON RECT 1 62 14 3 2 7 2 5 2 6 ABR LOA ANN SZA JMP CUL LOA RSS LOA JMP LOA 824 JMP CLR JMP PELA FQT6 I ANN Foro I RIZVA REJCT R 4 2 T 772 1 FQT8 I DC PTON LDA Po STA C270 JMP 2 PACER ENTER 10 SECTION 0 T 0 5 6 COMTROL WORD TSNLATE REQUEST TYPE INPUT YES DOIT CONTROL PES Y Ast T F WRITE TN DEVICE NOT 6 FREOR PETURN TN TOC NO SUBFUMTION BITS SET GET CONTROL WORD TSSLATE SUBFUNETTON RITS ANY SET FETT eas 6 CONTROL NN CLEAR DEVTCF ANA RETURN IMMEDIATE COMPLETION 4 SKIP LOAD OF ERROR FOME 2 RAM CONTRO PE IECT ERROR 2 Ne Tm OG PEQUFST GET RUFFFR LENGTH CHECK TF A NORMAL PROCESS 1 WORN WILL BE TNPL YES 8 TRANSMISSION LOG RETURN TO INC TATS SECTION AOJUST ANOPESS STUFF INTO CONTINUATOR RETURN ENTES CONTINUATOR SECTION PAGF NARO 2057 AWR Bw AYSY AAR nante 08 5 RAKA 0055 AAR AGRI naa AWAY AA 71 72 20735 07 4 72 7 5 e 7 6 2077 7 2070 AWA ARI 24224 4 aoas anag 2 A RQ AAGA aea 34 2 506453 e IPO A w 40054 anag 30407 6 5 AWAY A 8 1 1 1 5 2 1 3 ated NIAS 616 i7 nina 9 0117 manj HAY NORMAL RF
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13. 8 TNR SC 9 I INSTPUCTTONS SETI NOP CPA mp TOR STA ANA TA ADA RTA TOR STA STA MP PIn 1 PIO LIA Pad 8 1 9 Jo R1100 1 Raran 1 9 1 4 SETIO 1 GET ALACF NUMBER 1 lt lt lt lt lt DERUG ENTRY POINT gt gt gt gt NUTR TO Was CE TURN ON DEVICE ADJUST FFTIIRN TO P 2 COMTINUATIDN RETURN TN CIC RET RPM FROM PACFR GET RPM RUFFFR ANDRESS NERUG ENTRY POTMT gt gt gt gt gt STUFF INTO USER RUFF R SET ASA ALL IS WELL RETURN PONE SE Rei TRANSMISSTON LOG 1 WORA TNPUT CLEAR DEVICE DEDUSN TA CIC COMPLETE FNTRY TO SUBRONTINE SO TN DEVICE CHFCK IF CONFIGUREN YES MYPASSOCPNFTIGUPATION SAVE CURRENT 170 CHANNEL NIIMRER COMBINE LIA WITH 1 0 STORFE MAKE OTA INSTRUCTION STORF PAKE 376 CoOL YS 5811617 ION STORF IT MAKE CLC INSTRUCTION STORF IT AMO RETURN FROM SURRDUTIME 56 PAGE 21114 2112 ALIS 11 1195 04 07 A118 419 1 5221 122 3 124 2125 2126 42127 128 7 1 29 ALIG 51 1 2 1 353 134 2 1 x5 2135 ay 17 A138 133 ALAC 1 4 1 51 2 2143 4 145 1 0147 1148 x O ESRMNES TnTAL 2 0 4 Hay CONSTANTS STNRIGE LINKS AAAAN AANH 1 2 AAAA metas 0 4 AAYAS ADALAR 2127 1 mri 1 2 2114 28 1 5 2
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15. and the system test and operation FORTRAN program which may be modified at any time by the user operating in the RTE IVB system Operating System The RTE IVB Software Operating System is generated and can be regenerated by the System Manager in a process which configures the System for the particular set of I O devices which the computer must address Ref 3 RTE IVB permanently resides on disc and is automatically loaded when the system is turned on It consists of a collection of soft ware modules which perform system resource management operator requests for utility programs FORTRAN compiler file editor etc and user program scheduling for time sharing Ref 4 RTE IVB is visible to the user through interaction at the terminal It allows multi programming through its scheduling modules so that more than one user s program may be active at a time The input output I O drivers are a set of modules in the RTE IVB System They are the software routines which control the input and output communication between the user s program and addressed peripheral devices The drivers enable efficient use of peripherals which act at different speeds by allowing one or more fast I O requests to be 15 i processed while waiting for a request from a slow peripheral device to be completed A driver written for the PACER DVR 70 and a driver written for the A D converter DVR 56 are part of RTE IVB and are listed in Appendix
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17. paced data acquisition is included DD Form 1473 II RAR OPER AA 14 6 1 SECURITY CLASSIFICATION OF PaGE When Data Entered Approved for public release distribution unlimited Hardware and Software Improvements to a Paced Data Acquisition System for Turbomachines by Patrick Anthony McCarville Lieutenant Commander United States Navy B S University of New Mexico 1972 Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN AERONAUTICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL June 1981 ABSTRACT 2 19 of the phase lock loop synchronizing circuits and of the method of input output communication used in a synchronized data sampling system are reported A device known as PACER which used an analog phase lock loop for syn chronization and produced a non linear set of synchronizing pulses was modified to use a CMOS digital phase lock loop resulting in a linear set of pulses The associated program ming which controlled the data acquisition process and sequencing Was changed to use the direct memory access feature of the System computer This enabled data from high response pressure transducers mounted in a turbomachine to be taken once every rotor revolution rather than once every ten revolutions A user s manual for paced data acquisition is included I 11 OE CONTENTS Ite INTRODUCTION
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19. the 562N PLL and the new CMOS digital PLL circuits It can be seen that the new circuitry produces symmetric and evenly spaced pulses while the old PLL circuit does not A linear ramp test signal was input to the A D converter On analog channel 0 The PACER test portion of program A2D was run calling for a survey across the simulated blade pair The test was repeated for the old and new PLL circuits Figures and 12 show the output results from the PACER 24 using the old and new PLL circuits respectively The appar ent bending of the ramp test signal when seen as the graphed output from the old PLL method is due to the inherent non IUE UrIty of the 562N PLL The strict linearity of the 5 PLL circuit was noted LOCK ON TEST The new CMOS digital PLL requires no lock on procedures as did the 562N PLL Ref 1 Tests were run to confirm that while varying the blade passing frequency the new PLL remained in a locked on condition It was shown that within the design range of the PLL circuitry any variation of blade passing frequency RPM was followed without error by the digital phase lock loop Two separate PLL circuits were ded each one covering a range of blade passing frequencies One 1 1 now covers the range from 250 Hz to 2 5 KHz The other covers the higher range from 3 KHz to 11 1 KHz The reasons for this division are explained in Appendix A TEST OF ACQUISITION TIME Usin
20. 00009 ELKS R 0000 AA2D 5 2 2 2 eJ 0 0 5 2 2 FA 2 e Rh gt gt II gt A x P 54 uU e 0 gt tel gt E H 1 e u M 04 lt wees E 12 os W s 4 LL O O gt Q x e 2 O 2 1 AE o J a a uJ s D I gt i a e wo e TO tn gt a Lu a UJ H lt uJ 0 lt e uJ lt O gt 00 3 Ul a gt o on lt uJ CZ e lt M lt 2 zi u T D ao lt gt 7A e uU tu ce t s ma D 0 gt lt F HH O na EE zi 3 lt E n ie iJ wt 2 a e M 0 a 4 ale O 0 L m p C aw gt LU e nm A gt Tel Lu uJ e H Qa
21. DMA l 100 L77200 JO 0115 sec 0161 sec 20116 30105 1 60 17 400 100 2 3 20 7 500 Sl 008 5 0125 3 4 20 8 000 45 OOS 0225 5 gt 00 30 000 951 20 072 j 20113 b 6 500 2 SHOVE 9 50 211112 019 1 After DMA l 100 13 100 398 00 397 00398 2 100 1 0 0 4 4 3 100 87900 750 0075 200515 i 100 307 0 010 218 20 012 2002 Table III Components Used in PACER COMPONENT SCHEMATIC NUMBER VALUE OR TYPE NO li l Sora Low Board R1 10 4 7 K0 Resistors R2 100 KQ 100 KQ R3 1 Mo 1 MQ R4 39 KQ 47 KQ R5 117 12 5 R6 KS 12 KS R7 10 0 12 K Capacitors Cl 5000 SoHo DE E Counter SUL 74193 Hatch Etnu L8 475 Comparator CEI ENE C4 9324 AND Gate 157 US 7408 Inverter TI IZ 7404 Buffer PISCU ES N4050B Driver A Staru A4 7417N Phase Lock Loop PLL CD4046 30 537112110010102 ua3SAS 00131517 53 2320 peoegd 7 226 XWIC asa 2 02 Q V Andino 1 viva 606 AHOW 3M 1 VIVO 4 3 4 oz 0 E P gt WVHOOHd NIVW m eee ee ee 5 i 0 2 _ u31Nnoo Nat r 5 130 Di U3NOILIONOO TWNOIS ANNINHW3L t43 LNI Jd Ola 4 890103130 O10Hd 351 2110291 JO 213 755 c SANTA 073 30 0 Nau ZI 30 1
22. Data Acquisition Manual Once logged on mount cartridge 28 Turn on the plotter and select the desired pen Call up the Acquisition Fortran Program A2D with the command RP A2D Run the program with the command RU A2D The interactive program will prompt the user for responses The responses are explained in the prompts which are given at the terminal The prompts are as follows a System test or data run enter J b Simulated blade pair to survey enter any number 1 8 c Is test set up ready if yes enter 1 if no enter f 62 Ecer prompt E is answered yes and if the test 0 is successful the plotter will plot the same ramp Signal that was set on the oscilloscope in C l l step 4 Fig 12 The linearity and smooth ness of the ramp signal indicate the degree to which data acquired under pacer control agree with the analog data input to the A D converter TEST DATA ACQUISITION In order to acquire paced data from the compressor or other pP rig the following steps should be followed with the equipment shown in Fig C l C 2 1 Procedure 1 2 Cables to the PACER from the optical timing wheel on the test machine should be connected as shown Iza 776231127126 5231215011062 Input connec tions to the A D converter at the A D junction box Turn on the A D converter Turn on the signal Conditioner Log on the 21MX computer following directions in the TPL Data Acquisition User s
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24. Software Drivers 1 5 The drivers DVR 70 and DVR 56 are copyrighted by the Hewlett Packard Company 1978 Approval for repro duction granted by Hewlett Packard 22 May 1981 The driver flow chart in 5 2 1 is a simplified diagram which shows the basic process for a typical driver DVR 70 contains a series of steps which pass IBLADE output and a section which receives IRPM inputs The initiator section first outputs IBLADE to the PACER After that control is returned to the Central Interrupt Controller to await the PACER interrupt signal indicating it has IRPM ready to output When the interrupt occurs the completion section of DVR 70 is entered and IRPM is passed 47 Bok 56 on the other hand has only the input function to complete It accomplishes this task as the standard driver indicated in the flow chart B 2 1 The beginning of DVR 56 configures the DMA feature of the RTE IVB Ref 2 B 1 ACQUISITION FORTRAN PROGRAM A2D See following pages 48 1 1 Program A2D Flowchart ADTES ENTER BLADE PAIR TO SURVEY PROMPT USER FOR PARAME TER ACQUIRE TEST DATA AT EACH POSITION IBLADE CONVERT SINARY TO DECIMAL PLOT EACH DATA SAMPLE vs POSITION RETURN TAK amp DATA AT 256 POINTS ACROSS PAIR SELECTED TAKE DATA AT DESIRED POINT OUTPUT DATA RETURN 49 Program A2D Listing STE 00004 IS ON CR00028 USING
25. XINIC q v TD sandra 0 3 66 TRANSDUCER OUTPUT CABLES OO 3 0 BOX OO co 0 0O O 0 0 000000 IG A D INPUT LINES p m JO OPTICAL SIGNAL CONDITIONER JCT BOX Figure C2 Cable Connections for Test Data Acquisition 67 10 B LIST OP REFERENCES West J C Digital Programmable Timing Device for EE Response Instrumentation in Rotating Machines M S A E Thesis Naval Postgraduate School Monterey fornia 1976 Hewlett Packard Reference Manual HP21MX Computer Series HP02108 90002 June 1976 meeerarth 5 Na introductory Guide for Users of RTE IV TPL Technical Note 79 01 TPL Monterey California N79 Hewlett Packard Reference Manual RTE IVB Programmer s Reference Manual HP92068 90004 January 1980 Hewlett Packard Operating and Service Manual Analog 011 Converter 5610A 05610 91999 January 1972 mre Catalog Signetics Corporation Copyright 1977 Encaster D CMOS Cookbook Howard W Sams amp Co Inc E977 RCA Solid State Databook COS MOS Digital Integrated enui ts SSD 203B Copyright 1973 kancaster Ds TTL Cookbook Howard W Sams 8 Co Inc 1974 Hewlett Packard Reference Manual RTE FORTRAN IV Refer ence Manual HP92060 90023 March 1980 Hewlett Packard Programming and Operating Manual RTE Operating System Drivers Wr
26. lt der Lo Jee ye T lt 1l Wry ZA oJ ND IL E ENS OTE T t9 ru wcll Sanaa nem t oz IUE ers ada een OM tee 333 2222 QOM ILLI 3 4 Lea 2 UO UL OOOO lt lt lt O gt gt lt lt lt lt lt 4 lt O lt gt lt lt lt lt lt x lt Lu gt ME LAE ILS EI ETSI ed 3 L Lu 500 un o o coco Clos lt LA A wv 00 ANMTNOR DA gt Uo P O ON O TINDKR O lt I UNO 00000000 PE 000900 00 000009 0000 0000 000 9 OQ c OOOO 1 4 at O O O O CO O O lt lt lt gt S 2 52 5 1 3 Program A2D Parameter Listing CHANL ICHAN AVERG IAVG SURVE
27. to sixteen different channels and under computer controlled multiplexing converts to a 10 bit binary data output With an input conversion aperture of 50 nanoseconds rapidly changing signals 100 KHz can be converted accurately The HP 5610A can operate in one of Six modes as described in Reference 5 Currently the paced data acquisition system uses the random access mode in which a specific channel is sampled on receipt of a command word and an encode command pulse from the 21 MX computer The command word tells the A D converter which mode of opera tion to use and which channel number to sample The encode command pulse triggers the data conversion to start 2 usec later The data conversion itself is finished in a total time of 10 usec Using computer issued encodes which is the mode required for paced data the sample cycle time is 20 usec Hence data can be converted at rates of up to 50 000 samples per seconds depending on how rapidly each successive command word is received The other mode which is used only for non paced data is the Free Run Random Access mode In this mode the com mand word is required as before but no encode command is 18 Geeececa from the computer The A D converter simply converts data as fast as it can 100 000 samples per second on the ected channel This mode is not addressed further in this DoDort 3 PACER A schematic of the PACER is shown in Figure 2 In its original form a detailed descript
28. 7 2 4 0049 AAKA 2051 7 52 AASS ank4 205 202 421 annoa 2 Pacer Driver DVR 70 05 5 NAM 0 79 NPGS RPACE RTE DRIVER SEV 729724 3 35 AM SE 4 10698 JDM FNT IG AAE OT I FOR NAVAL POSTGRADUATE SCHODU MOTEREY CA AUTHOR SET 005 NEFLY SANTA CLARA 4 3 99 6 9 886 THTS WTE DRIVEP MILL 0 A RLADF NUMBER TO THF PACED ANN PETUPN THE RPM VALUE CALLING SEQUFNCES CALL T LU 1 6 TBLADED NIIMRER OF PACER PAUL 4 c fN OU r1 2 7 AG Nr ANANS mno 0 7 0 11 ern 7 20144 5 0011 20017 Agron mana 00022 606 55 NEAD REQUEST aan 24 anans 8 6 mna27 SETUP NAF 0 ea 32 AANNAM 66 14516555 Oe 2010559 21n6 22572 30 2521259 2 2 5 2 2 6 LU CEN TALADE EEC CAT LUN T 0 es IOGICAL e RETURNED RPM FROM PACER 3 V NOR MAI NORMAL THPUT CRFAN 0 NNP IMMED COMPLETION PATER RLADF NUMBER 16 BIT INTECFR gt gt gt gt gt CLEAR CANTRnL ON NOP ISA LOA AND CPA IMP CPA JMO LDA IMP EMR CLFAP CONTPOL E1655 2121 0 1 2 2562 1 ESIR 6 21 62 265 1 0 AR 181687 08 2 2 9 AAR AAA 250179 COMTINHATOR TO RETURN
29. 9 PEARS auicm aprena 7 7 AN Aaa 37772 aN Eaz II A AWAY a pP IQ SC LIA P AS 1 R2 0 MASK R1 0 2 4 FSU EQU OCT EQU ETA PEF CCT DET ACT ACT BET NET nor MIET CT IEYIT 1 1 2 37099 4 77777 190 1199 47 8 35 AM FRY 4 0 1978 CURPENT I 0 SFLFCT CODE VALUE DIMMY SELECT CODE INPUT FROM DEVTCF INSTPUCTTON RETURN POINT IN 1 10 SFCTI N MASKUOFF BIT 15 RASE PAGF 60 0 15 AREA NEFINITIONS 155 VIREN MIRRI 0 2 TEN 1 4 55 CIRKA 7 MIEJA 21 71 02 21771 21772 175 01774 7 t FOTI PUT2 FATS 4 EDT HOTE 077 POTS Fr 9 2 0 EDT Fo0T1 1 4 EO TIS NIE FQ Ful EQU FoI EG EQU ent FQ en FO ECU EI Fon FQ EQU Eg ENN f 6568 9 02 3 14 15 16 7 08 A 2 82 DEFINE STAPT OF COMM AREA a RTE ASMA 02067 1621 1x 2 A D Driver DVR 56 B2 ADVRS amp T 00003 IS ON CR00002 USING 00024 BLKS R 0000 gt 5 P HAN ICODE E DRIVER E A a 1 ER S 5 TO LJ ul a Q 0 WOW ty JUNE 7 1 Wu T O m OC coc OO OE FE An itl le mw ANGANnODAMAY 2 4 XL D WAHA LD ORY m tn
30. B Test and Operation Program The system test and operation program A2D is a FORTRAN program written and used in the course of the present work A listing and flow diagram are given in Appendix B Program A2D converts the user s requests which are entered at the terminal to the parameters required by the RTE IVB I O drivers It is an interactive program consisting of two parts The first part a system test subroutine ADTES is entered if the user wants to carry out a test of the paced data acquisition system simply to ensure that all components are operating correctly The second part Subroutine RPACE is executed if paced data is to be acquired from a test rig Both the test and operation portions of A2D use the FORTRAN statement CALL EXEC to enter the appropriate driver The CALL EXEC statement with its accompanying parameters transfers control from the FORTRAN program to the assembly language driver for the device requested A simplified flow of the CALL EXEC routine is shown in Figure 5 The driver initiates the input or output task as specified in the parameters which it received If the task is for output after the task is initiated control may return to the calling FORTRAN program or another user s program the task l6 requires input then control may be passed to another pro eam but not back to the calling program since the calling program must have an input value to continue ex
31. Manual Call the Acquisition Fortran Program A2D by using the command RP A2D Then run the program by issuing the command RU A2D The interactive program will prompt the user for the following a System Test or Data Run enter 1 b Test number enter integer C Do you wish prompting Yes enter 1 no enter J From this point on the program prompts are self explanatory 5 At the completion of the data acquisition the data values are printed out as shown in Table C I 6 The final prompt will ask if another run is desired m2 Data Storage The survey data acquired in the program A2D is contained in the data memory locations SRUPT J where l 256 The program A2D may be modified to output the data as desired by the user or to pass the data to a user written subroutine for analysis 64 Paced Data Output from Program A2D Table C 1 RUN ON JULIAN DATE 149 1 1 5 THIS IS TEST SURVEY DATA PACED uc oe ht PO Un EN O PFS lt GU em Od em r 3 i RS AN Ole 229 r lt t Unir TE on Chun S Ae R 4 CFA O FF COD lt TD MMS cas ee O OS CU EN So AG Gi AM VIP OR
32. NG Approved for public release distribution unlimited 116 OISTRIBUTION STATEMENT of thia Report 17 DISTRIBUTION STATEMENT of the abetract entered in Block 20 if different Report 16 SUPPLEMENTARY NOTES 19 KEY wOROS Continue on reverse aide if naceesary end identify by block number Programmable synchronized sampling digital phase lock loop direct memory access 20 ABSTRACT Continue on reverse side if necessary and identify by block number Modification of the phase lock loop synchronizing circuits and of the method of input output communication used in a syn chronized data sampling system are reported A device known as PACER which used an analog phase lock loop for synchronization and produced a non linear set of synchronizing pulses was modified to use a CMOS digital phase lock loop resulting in a linear set of pulses The associated programming which controlled the data DD ee 1473 EDITION or t NOV ss is OBSOLETE Page 1 1 SECURITY CLASSIFICATION OF THIS PAGE When Data Entered sr rsradr aassxJL OOOO ecuwm v CLASSIFICATION OF Twist PAGE Nore Enteros acquisition process and sequencing was changed to use the direct memory access feature of the system computer This enabled data from high response pressure transducers mounted in a turbomachine to be taken once every rotor revolution rather than once every ten revolutions A user s manual for
33. Od SWOT roro roro roro UBRSTSTEHS 8 C E N N R R 6 DURS fics CJ CI LIZ CIOS IQ 0 2 OO HH Ze u R t o lt ADDRESS 0 URE INSTRUCTIONS CONVERTER TO INITIATION SECTION 10 SAVE I CONF IG A D m NOC ootz OS MN 0 TX 4 n T ro er A F OOOOCOCCQOCHWumomoorr onmomnoumuwuomoomumo eee NOH 11 4 Tee OORT 4 4 4 z lt 4 4 gt gt n lt x lt lt gt gt COCO lt cz lt lt lt lt X lt lt lt AT gt ON SECTION E u 3 lt 4 3 3 3 9 9 9 3 o 0 C ul c Ec 63 m OH tu Tm ZL O C D N O tc 6 lt N QUEST CHECK r 41 uii quo UCT DMA CONTROL WORD ec CT To 40 0 6 AU Or GAES 92 2 J 2 022 CO UL Cry YD t UU 0000 lt J 00 gt y l
34. PATR 4 474256 LOFFS L00000F GALL 3 19 GALL EXEC 1 19 TRPM 4 TELADEO CALL EXEC 1320 TRUFE N CHAN 0 RRUFF 0 1 DO 1 40 1 N 430 REUFEERBUEF E LUAT CIMUEE 1 32768 DATA RRUFI I AVG 140 SRUPICI DATA 8 9 6 9 9 9 o 08 9 9 9 t 59 Po b 9 o 9 9 9 9 9 5 9 t 9 9 9 9 Q 9 9 9 5 OUTPUT TARLES PRINT WRITE 6 346 46 EDRHATC 7 23X PACED SURVEY URIE 140 SRU PT 148 FORMATC BUDX EB 7 450 RPM 60 CTIRPMX 114004 WRITE 6 445 RP 165 FORMAT CA 20x COMPRES 3SOR RPM FOR THIS RUN WAS CO TA 999 95 WRIIE 6 196 TPOSTT 1PAIR PTDATA 196 C THE DATA VALUE FOR POSITION 13 OF I2 16 10 7 5010 150 999 RETURN FND SUBROUTINE ADTESCTGCRB TEST OF THE PACED DATA ACQUISITION SYSTEM MMON IRPM IMENSIUN I 4 9 9 eee Q Q 9 9 0909 Q ee 9 9 9 0 0 0 o 9 9 CCRC192 21 5 e gt P EN ADE PAIR e e 5 9 9 9 b 0 1 zp lt e amp C323 35 lt ED EU ps Lu XI Pul gt zi wom gt gt 0 o ut n IZ lt v eS Lu un 6 c lt OJ Lu lt c gt en I e 2 0 Ad C N m a WI wo 00 cec 2 Ao c EE x
35. SA II ON G gt pm Ar Por ON OK 1 a e gt e 5 lt lt rim UIID s OO lt O ec Gr tc T HUC OC OO G Ln C BGS MO US ero OO 0 0 2 0 ou TOO YT N L 2 G O Tr DDN T N LAO Oj GG Ur c rt OO DLP SUD C OLN OE SONO 0 CrU 2 eo CU Ge IS SNS SO DADO e sy OSD NSS evo r DONO ON A a gt COTTA MA ou uo LA MG AME SMO Que Ui COO GO re ON AL LI IO UN lt eU TN CIN lt G OU COD m C TCI CO L CILIA GOR G POT ODOR O OCI O O QJ N i ee eS ds Te UN DA T OS TOO ON lt OR SN SMT OD BOLI r ni IFO T LS ec mTUu tgo T 7 OLA o gt gt gt LI gt lt e gt o 0 00 J G GO Ln 3
36. TI RN TO INC NAW AEN 2 0 4 0 2 25 I EXIT ICA JMP COMTTNIIAT N COMPLETION 5 apn 7 maman nana 2 apaa 56 NAPAR apnana AR 55 2 2121129 02 2 8 1271774 127 22 78 MOP JSA LOA ANA SZA JMP STA 157 JMP 1 70 1 SECTION SETIO 0111 MASK T Ze C70 6 77 8235 AM EI pr 1978 A ALL IS WELL RETURN TO TOC ENTES CONT COMETGURE 1 0 CHECK FOR SPURTONS RENUFST LIST POINTER IS A RFQUEST IN PROGRESS YEST GCE O0 TT NN ZFRO TIME OUT CLOCK AQJUST RFTIIRN TO P 2 CONTINUATION RETURN TO CIC OUTPUT CANTRALL WOON NUMBER 2 AR AANA auasn CAAS 7 3 AN 3754 02955 ARAKA DANS A 2 n 02 sonas 1672 move LOA n msna NOD IGP 1 OTA 2 str a3A 0 150 157 1250550 IMP SFCTION massa LIA 165556 L DR AYPANAL 4 NOP 1 72 21 STA 1 2 CLA MAR AMA ER 57 CUT 1250359 JMP 4 AATAS 066 nans ARI7A 2 Y 6 7 2 ann 7 3A 40075 ARA7A 00277 216 RAIAT ANO A 05210298 125040 1721229 5 6 672 2 1 0 7 5221 0720519 1321158 7259 a72nA25 126 26 8 6 0 9 1 SC sC C 670 6 EQT7 I
37. TRAN and system assembly lan guage drivers Finally Appendix C is a step by step system users manual for paced data acquisition 12 IEMLLOACHPNSDAIACACQUISITION SYSTEM DESCRIPTION E GENERAL DESCRIPTION Components of the system are shown schematically in Iure and details of the circuits including the modifica tions made in the present work are shown in Figures 2 4 The PACER acts as a secondary controller on the interface between the Hewlett Packard HP 21 MX computer and the A D converter Referring to Fig l in a normal not paced data taking sequence the 21MX would call on the A D converter to take an analog data sample convert it to digital and output it to the computer memory Since the computer program execution cannot be synchronized to the rotation of the machine shaft the data sample would be from a random unidentified posnt In a paced data acquisition sequence the PACER provides the timing control to the 21MX computer After the 21 MX computer passes a word IBLADE to the PACER defining the desired position the PACER acts as an intermediary It inter cepts the computer command to the A D converter tells the computer that the A D converter is in the process of acquiring the data then sends a command pulse to the A D converter at a time synchronized to the desired position in the cycle of the rotation of the machine 15 the Sequence of events for paced data acquisition using software devel
38. Y ISURV MODE IMODE PAIR IPAIR POSI IPOSIT SSHSET IOFFS IRPM IBLADE PUE N2 RBUFF PTDATA DATA SRVPT IGCB The A D analog input channel to be sampled The number of samples per position to be averaged Survey single position selection Paced free run normally 1l The pair of passages selected The position within the pair of passages To start the survey later than position 1 within the pair passages Entered as of 256 See Table I See Table The name of the set of digital data storage locations Test number that date Floating point data storage The data value at the selected point The array holding the data surveyed control block graphics package usage nonaccessible SOFTWARE DRIVERS 2 DB JAPYD MOTA 6 8 SUVMCdVH S3 INCOW N QAI 3193 MM 235 JWOD is 00 035 108 LNOO 0 3 iva BP 3 1dndd3LNI 970 HAG 1 1N39 3NOQ 00 x 18 1539 6 H3OVd i 18 15 935 d 109 LNOO lyvis LINI T HAG TWO 23 3 24 PAGF ANA AYA Anas AMD 0 0 65 APTA 2020755 2 0 8 2 2 4 2 4 BOY 14 32125 A01 3 2 0 1 4 4 AN 5 6 7 A 2 0 2 2 1 a022 2 3 2 2 7 2 5 2265 0027 ANDA 62 aptae ANA 1 ABRE 3 NALS ABAS AARH 20137 AAIR AAAS AAAA ADA ARAZ 643 4 4 5 72 4
39. atisfactory overall loop response was attained A 2 4 Interfacing Due to the extremely high input and output impedances of CMOS integrated circuits an interfacing buffer was needed between the CMOS PLL output from pin 3 and the TTL counter Bl input to pin 5 Fig 2 Also interface drivers were needed between the outputs of TLL counters Bl0 and B2 and the inputs to the CMOS PLL at pins 14 and 3 respectively The buffer between PLL pin 4 and counter Bl pin 5 simply required wiring one of the unused buffers which were part of the N4050B Hex buffer chip already in the PACER Since the N4050B used a 5 VDC supply the required transition from PLL 15V logic level to the counter 5v logic level was made Madero transition from the TTL 5v logic level of counters 210 and B2 outputs to the required PLL input NE Ns greater than 77 for logic 1 two 7417N TTL drivers 45 were used with 12 KQ pull up resistors on their outputs This gave a high logic level of 157 and a low state current drain on the drivers of only 1 25 ma each well within their capability Ref 9 46 APPENDIX B SOFTWARE DETAILS This Appendix contains the following materials ACQUISITION FORTRAN PROGRAM A2D Ref 10 Dl Program Flow Chart 2 Program A2D Listing B 1 3 Program A2D Parameter Listing SOFTWARE DRIVERS Ref ll See Note 1 E 2 1 Flow Chart B 2 2 Pacer Driver DVR 70 E23 A D Driver DVR 56 Notes on
40. coo e a Y gt GO oO a tL 5 2 eoo zv m e 2 24 ul 3 ul a e FX tJ UJ 0 me Qui roc E a A e lt LE E CJ Ll O OLIN LJ E a zou Ono lt AM Oo ody y a 9 60 c lt EQ Or Z 6 PA gt gt mo Ww ul E Eo et Zrr O lt uou 0 ul br 4 w EL gt COLE HTA 0 gt Jr O Ze E AN Qa T e e T ccm c m XI gt A lt A 22 2 3 XI e uno Q amp O FHS a lt E E OrE Z YE gt AT Hm W un 4A c f AANA Z Z A Aa DA DWAL ulzul Nr Q Out GM 2 02 DD un t Fr mZ ST ION 2 ul e e Oe Os ES CUIT La X bbe Ful O FA 1 X wer oO gt o CO 2 6 2 5 a una ul 2 2 Aa uj u Zon CH D Za QUA Oc a S gt O lt OXe om in O ul WIN AUN NN Er lt k hL mul A gt T ul a 3 DLS mei OO u Gui TEJA 6 noO mk E C mx a U O mar 320 C lt c 2x 300 3 0 a C e a O a e e Aa ce it FA HO O c nO N A A Ji ao o lt 2 AMO AAU gt X e QQ Fo 0 a
41. e PACER linearity eliminate manual lock on procedures and increase speed following range A change in acquisition software was used to increase the rate at which data could be taken The change in PACER hardware consisted of replacing the original analog 562 phase lock loop with a CMOS digital phase lock loop and eliminating the discrete components forming the coupling circuit in the PLL feedback path The change to acquisition software involved use of the DMA direct memory 1 access feature of RTE IVB system software Ref 2 which is incorporated in the I O driver written for the PACER As a result of the hardware and software changes which were made all of the limitations described above were elim inated The improvement in PACER performance was verified using test programs and rotating machine signal simulation circuits which enabled controlled test techniques to be employed In the following section of this report a description of the entire paced data acquisition system is given Section III describes the changes made to PACER hardware and the effects of those changes while Section IV describes the change to acquisition software In Section V the results of the changes are verified with a report of the system tests Sec tion VI lists conclusions and recommendations or further System development Appendix A contains detailed hardware circuit design figures and Appendix B details the software programs both acquisition FOR
42. ecuting This permits efficient use of the computer s time which is essen tial for multi programming while waiting for a slow peripheral device to complete its cycle of operation C SYSTEM HARDWARE The hardware devices used in paced data acquisition are the HP 21MX computer with printer its magnetic disc plotter and terminal the HP 5610A A D converter and the PACER 1 Hewlett Packard HP 21 MX Computer The HP 21 MX is a Micro programmable mini computer having 128 machine instructions and 32K of logical main frame memory In the present configuration a 20 megabyte capacity disc and disc operating system are an integral part of the system detailed description of the computer is given in Reference 2 An important feature which is typical of computers of this size is the input output structure With a limited number of relatively slow I O devices to be serviced the computer can communicate with all devices through a single port known as the I O bus Each device requires its own I O interface on the bus The interface acts as a filter and ensures that output information is received only by the device designated to receive it and that input information is put 1 on the bus from only one device at a time The I O software drivers control the I O hardware interfaces by commands to Ber turn on or turn off 2 Hewlett Packard HP 5610A A D Converter The HP 5610A analog to digital converter accepts analog data input on up
43. g the software methods used in Reference 1 a short test program calling for a specified number of data samples to be taken was run Clock time accurate to 1 millisec was recorded by the program just before the first sample and just after the last sample of data was acguired The lapsed time 39 6 total acquisition was output It was shown that up to 10 revolutions of the machine rotor where required for each data sample to be taken 25 After changing to the DMA software method described in section IV similar tests were run The results of these tests are shown in Table II It was noted that the interval between samples was reduced to less than one revolution of the machine rotor 26 VI CONCLUSIONS AND RECOMMENDATIONS The desired improvements in the paced data acquisition system were achieved namely 1 The speed of acquisition of successive data samples Was increased to enable data to be sampled on every revolution 2 The correlation between the position recorded for a paced data sample and the physical position of the probe with respect to the rotor at acquisition was significantly improved through an improvement in the linearity and stability of the PLL and associated 510111 3 The manual adjustments previously required for each small range of RPM were entirely eliminated by the reported hardware modifications With the present hardware and software the PACER operates as fast as is possible given
44. ion of the internal Operation is given in Ref 1 The PACER consists of two major sections an RPM counting section and a synchronized command pulse section The RPM counting section contin uously counts the number of 250 KHz time base pulses that occur between the once per revolution pulses received from the test rig This number of counts is available as an out put IRPM from the PACER on every revolution cycle The synchronized command pulse section is the heart of the PACER It uses a phase lock loop to generate 256 pulses within each pair of blade passages i e 128 pulses from blade 1 to blade 2 and 128 pulses from blade 2 to blade 3 the same time these pulses are counted and compared with the programmed data conversion location speci fied in IBLADE When the comparison is true a command to the A D converter A D Device Command is generated Thus a command to convert a data sample is synchronized with a desired position of the rotation rotor in the machine 13 III CHANGES TO PACER HARDWARE In order to determine the cause of the non linearity in the PACER a test chassis was built to provide easy access four circuit boards and to allow modifications to be attempted without interference to the working unit The test chassis is shown in Figure 6 It is electrically iden tical to the system PACER shown in Figure 7 and uses the same four circuit boards Using the test PACER with an oscilloscope i
45. iting Manual HP92200 93005 May 1978 68 INITIAL DISTRIBUTION LIST NO 6 Technical Information Center Cameron Station Alexandria Virginia 22314 1 1512327 Code 0142 Naval Postgraduate School Monterey CA 93940 Department Chairman Code 607 Department of Aeronautics Naval Postgraduate School Monterey CA 93940 Erector Turbopropulsion Laboratory Code 67Sf Naval Postgraduate School Monterey CA 93940 LCDR J C West 6229 Hanley 0015 Christi TX 2 Turbopropulsion Laboratory Code 67 Naval Postgraduate School Monterey CA 93940 Dr Gerhard Heiche Naval Air Systems Command Code AIR 310 Department of the Navy 755111216623 D C 20360 DBE A D Wood Office of Naval Research Eastern Central Regional Office 666 Summer Street Boston MA 02210 LCDR P A McCarville 5151 Alton Dr Lemon Grove CA 92045 59 Copies T5 Thesis M166 qe 15 MeCarville Hardware and soft ware improvements to a paced data acquisi tion system for turbo machines thesM1666 Hardware and software Improvements to 8 TIT 3 2768 002 12313 5 DUDLEY KNOX LIBRARY
46. o Reference 8 the main source for design information To begin the design a value of R2 was chosen within the limits listed on page 228 of Ref 8 The value of Cl was approximated using figure 5 b of Ref 8 The value was then readjusted after testing to compensate for the effects of the following component values m 2 RI R2 The chosen frequency range fmax fmin was used to enter figure c of Ref 8 The ratio R1 R2 was obtained from the data in that figure using the design value of the supply voltage to the PLL Knowing the ratio Rl R2 and the value of R2 selected in section A 2 1 the value of Rl was obtained 1 3 R3 R4A C2 The design of the loop low pass filter was a trial and error iterative process because of effects from the counting cuits Bl and B2 present in the loop Ref 7 The RC time constant of R3 and C2 determined the settling time of the loop while the ratio of R3 to R4 determined the damping KAEO 44 The nominal values found in Reference 7 were used initially and then these were adjusted to obtain what was considered to be the best loop response to changes in the input frequen Cy Loop response time was found by putting small but rapid perturbations on the test frequency then noting the time to regain phase lock on By balancing the response time required to be as fast as possible against the settling time resulting from the loop damping ratio at a minimum to maintain stability across the frequency range a s
47. oa Qa crore ME 7 eu LIN lt gt AO CIO CJ p n Uu LA J No NL a Tor o lt 60 An O e ro o o lt Ne 0 ern WARES m e t lt e et wt A et TND 0 un DINO O gt OO O O ACM TINOK ORO ACM TUN OND Ro ACI 09 OO OHI 0 ANSeS ACIM rto ODO DO NIN O gt lt 2 92 re tore gt gt N et 00000000090 0023000000 S So OS p 2 5 p O 5 55 5 55 5 55 55 5 6 G O 5 O O 56 O O S 52 S S S eS cp o Op 25 5 5 O 5 O 5 5 5 5 5 5 O 555 5 S O gt O G O lt 20 mE 03400 01 0 1112 4 11 Gun unit ours 0 un L PM imn 4 Un 0 5 uu Wie fj
48. oped in the present work is as follows 1 6 The user enters the main program which was written to be used for system testing or for data acquisition The main program prompts the user for information regarding the rotor position s desired at which to start taking data points This information defines the integer IBLADE The main program calls the PACER passes IBLADE to the PACER and receives rotation speed IRPM from the PACER Control then returns to the main program The main program calls the A D converter telling it to take a number of data samples N at the desired point When complete control is returned to the main program If a survey of positions for example across a pair of blade passages has been programmed using a DO loop the main program repeats steps 2 and 3 incrementing IBLADE each time until the loop is finished When all data have been taken and stored in the com puter memory the main program converts the digital data which are binary whole numbers to decimal values scaled appropriately to the 1 0 volt range of the A D converter As programmed it then outputs that data to the desired peripheral s i e the 1 plotter or terminal 14 SYSTEM SOFTWARE The software used in the data acquisition should be viewed as consisting of two separate parts the RTE IVB operating system which is generated in house following standard pro cedures supplied by Hewlett Packard
49. rst designed and built in a bread board configuration in 1976 by James C West as described in Refer ence 1 U S patent no 4 181 962 was issued for the PACER on January 1 1980 The present hardware configuration of PACER involves minor but important changes which improve its performance and are documented in this report The original PACER made it difficult for the typical user to acquire accurate data in a reasonable amount of time for the following three reasons 1 The timing pulses generated within PACER were not always spaced linearly in time between blade pair 10 synchronizing pulses This resulted in data which in some cases was subtly distorted and in other Cases appeared to have noise riding on it 2 The range over which the PACER could follow rotor RPM changes and remain synchronized was limited to ence 152 ENC initial RPM at which the PACER was set to take the data This required re peated and somewhat involved manual adjustment of an RPM lock on procedure to acquire data at different speeds 3 The rate at which data could be taken was limited below the desired rate This meant that rather than being able to sample data on every revolution of the rotor the system was only capable of taking data once every 8 to 10 revolutions depending on RPM The methods used to improve the performance of the PACER fall into two areas hardware and software Hardware changes were used to improv
50. ry Metal Oxide Semiconductor ETL Transistor Transistor Logic DMA Direct Memory Access DCPC Dual Channel Port Controller TP Test Point ACKNOWLEDGEMENT To my thesis advisor Dr Raymond P Shreeve goes my sincere appreciation for his steadfast moral and technical support Without his timely and intuitive guidance this project would not have culminated in the results reported herein secondly to Mr Jack King goes credit for the fine workmanship resulting in the circuits built and tested for this report His expertise in the field of electronics was invaluable aid in the completion of this work Finally to Mr Alan McGuire goes my gratitude for his most professional work in the drawings and figures completed eer this report ee ION The device described herein and referred to as the PACER is part of a computer controlled data acquisition system in use at the Turbopropulsion Laboratory at the U S Naval Post EMduate School It is an electronic interface unit built of solid state and integrated circuit components The PACER was designed to allow the acquisition of data from high response transducers mounted in the case of rotating machines to be synchronized with respect to rotor position Using the PACER me analog to digital conversion of the data from a particular transducer can be programmed to occur at any position of the rotor with respect to the transducer independent of rotor Speed The PACER was fi
51. t gt lt TINY VAL ON ERROR RATION z OR DIG MODE u PER N rto INT E OBE 0 5 mu 1 RES ORD 7 1 311 234 IMAZJZ3N tD H HO 230 ZOCO gt Z erro LOTIT CT os ua mM HN JOSE JOP 3 T 1 0 0J 9 OO OMIM Op DO OHM UA TIn 00 0 O TIN OD O CJro gt COO HIM 9 OD 20200000 O ue aaa roro to prO ST lt r t lt UN IA LOLA LIL ANA unun O O OO III DS 5 O O OO gt C gt CO O 2 gt Occ 5 p ca O 2 6 2509 1096 3000060000 6 5 5 O O 5 SO 5 5 5 0 5 5 57 5 O O 5 5 55 5 O 5 O C OO S CO 5 5 c o 28 PS 0 A3 AS eo X lt 10 mz TA e Lu O ocoo
52. t was possible to examine the wave forms at E point in the PACER circuit In so doing it was found that even with the lock on procedure recommended in Reference 1 the output pulses from the PLL 256 Fo 2 were not always linearly spaced between the beginning and end of the input pulses Fo 2 This non linearity is seen in the oscillo scope traces shown in Figure 8 which shows the signal at counter Bl counter Bl the pulse frequency is 1 32 of the output frequency of the PLL which allows the non linearity to be obvious to the eye It was further noted that a devi ation of as little as 3 from the ideal 270 phase relation called for in Reference 1 caused non linear spacing and excessive unsteadiness jitter of the pulses into counter Bl These problems were inherent in the 562N PLL when used with digital waveforms because an analog phase comparator Mas used in that particular circuit Ref 6 20 A CD4046 CMOS PLL was therefore chosen to replace the 562N The 024046 uses a digital phase comparator to main tain lock Ref 7 and is specifically designed to operate with digital waveform inputs as are found in the PACER appli cation It also permits with proper associated component design operation over an extremely wide frequency range by so called frequency tracking without loosing lock The changes which were made in the PLL and associated circuitry are shown in Figure 3 Both the PLL and the dis crete component co
53. the constraint that the 21 MX computer operates always in the interrupt mode for all I O Operations If the need arises to survey across a blade pair on one resolution and the computer can be dedicated to the single task of acquiring paced data then the non interrupt mode of 21 MX I O processing could be used This change would eliminate other users during the paced data program operation It would require that the drivers DVR56 and DVR 0 to be rewritten in assembly language and loaded into the RTE IVB operating system by the system manager It is noted however that the maximum data rate of 100 000 samples per sec cannot be exceeded using the present A D converter 28 Table I CALL EXEC Parameters To call the PACER DVR70 CAE eee LU IRPM LEN IBLADE Parameter Meaning Limits Value 1 I O 1 LU device reference number 19 IRPM RPM timing counts returned N A LEN number IRPM of words passed D IBLADE data position indicator 0 35 584 To clear the PACER CALL EXEC 3 LU Parameter Meaning Limits Value 3 Clear the device 3 IU as above 19 TO call the A D DVR56 San FC SEDET IBUF N ICHAN ICODE Parameter Meaning Limits Value L I O 1 TORT device reference number 20 NBUFF data storage array name dimension 256 N number of samples 1 9 ICHAN input channel number 0 15 TEODE mode of A D operation 0 7 29 Table II Data Acquisition Times Run Number Samples RPM Time Time Rev Time Sample Before
54. upling circuits were changed The replace E the old coupling circuits with CMOS to TTL 4050B Buffer and TTL to CMOS 7417 Drivers with pull up resistors matching devices was necessary because of the special require ments of the CMOS PLL with regard to interfacing Ref 7 The detailed circuitry of the CD4046 CMOS PLL is shown in Figure 4 Specific details of the components are given in Appendix A 21 IV CHANGE TO ACQUISITION SOFTWARE A METHODS OF INPUT OUTPUT The two methods available under RTE IVB for input and output are the standard method and Direct Memory Access DMA In both methods the software driver controls the initiation and completion of the I O request Figure 9 is a Schematic representation of the hardware and software involved in an I O request in the paced data acquisiton process The standard I O method requires that the software driver be entered for each data sample taken In contrast the DMA I O method uses the dual channel port controller option of the 21 MX computer to bypass the requirement to return to the driver for each new data sample Ref 2 Thus by using DMA the time involved in executing the software driver for each sample is saved B INCORPORATION OF DMA The system software was changed so that DMA was used for the A D I O process The DCPC option was added to the system in 1977 The driver DVR56 was subsequently modified by Hewlett Packard to permit DMA for I O operation
55. with the A D converter The use of the DMA feature required only that the proper parameters be specified in the CALL EXEC state ment for the A D converter Table I lists the parameters 22 with their meanings for the CALL EXEC statements used to call the A D converter and the PACER through the drivers DVR56 and DVR70 respectively The parameter N which is passed in the call to driver DVR56 sets up the DMA option in the 21 MX I O interface logic through the Dual Channel Port Controller DCPC The program A2D was written so as to use the DMA feature flow chart listings and param eters used in program A2D and the drivers DVR56 and DVR70 are given in Appendix B 23 Woe RESIDES Tests were run to verify the linearity of the new CMOS PLL circuitry to demonstrate the automatic lock on feature and to determine the speed at which data was acquired The tests were run using the test pulse generation circuit on Eumeunrt board 4 of the PACER This circuit provides an electronically produced simulation of the l Rev and l Blade pulses that would ordinarily be received from the test rig The test set up for the tests is shown in Figure 10 An external signal generator was used to provide the driving Signal to the pulse generating circuit at the desired blade passing frequency Appendix C gives detailed procedures for performing a simulation test run LINEARITY TEST Figure 8 shows a comparison of PLL output pulses from
56. x describe the use of program A2D for both C 1 System Verification and C 2 Test Data Acquisition SYSTEM VERIFICATION In order to verify the complete paced data acquisition system software and hardware the following steps should be followed using the equipment shown in Fig C l Procedure A WaveTek 142 signal generator or equivalent should be used to drive the test pulse feature of the PACER 1 Connect the sync output of the signal generator to the sync input on the PACER panel Fig 7 2 Connect the 50 QR output of the WaveTek to the A D analog channel to be tested normally 0 and to the oscilloscope O Turn on the A D converter 4 Set the WaveTek panel switches to produce a ramp voltage of 1 volt maximum peak amplitude from the SOE EID 5 On the PACER front panel connect the jack marked BL INPUT to the jack marked BL OUTPUT Do 6l 6 10 the same for the jacks marked REV INPUT and REV OO LD OT Make sure PACER ON switches are in the ON position Ensure that the Card 3 with the frequency range encompassing the blade passing frecuency set on the WaveTek generator is installed in the PACER If necessary remove the front panel air vent and replace Card 3 with the proper range card Card 3 is shown in Figure 7 Turn on the PACER power switch and verify that the red pilot lamp is lit on the front panel Log on the 21MX computer following the directions in the TPL
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