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SCANIO-280LV User`s Manual

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1. TAACT74 NET J1 27 21 4 DATA 8 21 FEZPR NET Ji 28 22 D3 SE DATA 9 G3 a NET Jt 46 LI e 9 NET J1 43 NET J1 29 23 2 DATA A 23 Q2 2 NET J1 47 za Di q Di aq di CLK RP1 14 1 14 11 TO TDI TDO TDI TDO Aes e e d ats NET J1 44 2 2 74BCTE374 2 x 2 748CT8374 P2 E e 3 iE 3 3 i TDO E sei TDI 4 NET J1 32 NET J1 34 een TMS 7 4 Hemd 1 TOK E NET J1 31 9 8 NET J1 33 12 1 conto ua USC USD TAACT125 TAACT 125 Figure 4 1 Schematic of an Example Unit Under Test Application Example with ScanPlus TPG Description of the Unit Under Test In the example shown in Figure 4 1 above only nets DATA 0 DATA 8 are fully testable The outputs from buffers U2 and U4 the inputs to Ul and U3 which connect to either non boundary scan logic or the edge connector cannot be tested using boundary scan techniques under normal circumstances since there is only one boundary scan cell on each net With the use of the SCANIO 280LV the visibility of the boundary scan chain can be expanded to include these nets TAP Connection and Termination The TAP is designed to be compatible with the Corelis standard TAP and contains 4 signals TCK TMS TDO and TDI The TRST signal pin 1 on the standard TAP connector is left unconnected since the boundary scan chips on the target board do not contain this signal All 5 even pins are connected to ground Note that each signal is terminated with a 1K Ohm resistor in order to minimize signa
2. 2 7 Mating ConneCtOE 2 14 CHAPTER 3 PROVIDED SOFTWARE esse nnn nnn nnn nn nnn nnn nn 3 1 What s onthe Disk i isssisisiin 3 1 Executing Selftest with ScanPlus Runner esssenesnvvenvennseneennnennseneennennnennnennnennennnennesnnennnennnennennennneennsennnensennnennnenneee 3 2 Infrastructure Tetis ER ER UO eb er OH erai 3 2 Interconnectiand Buswire Tests 2 6 seo PD TORO I OH OT eor Gath ODORE te 3 4 Using the SCANIOTM280LV Eiles enero ne ne oen eo este sr costas sas o as ves co seen Fe roe ERE aaa ea e Pa PE ae Foe o aea ene sita a eR E veau sa 3 5 Boundary Scan Topology eer NR ROTG Nr eR 3 5 Boundary Scan Description Language BSDL nana enne aa nana nana 3 5 Netlist Edit El p qe CHR Ren OE URS 3 6 Netlist eere ac ade 3 6 CHAPTER 4 APPLICATION EXAMPLE WITH SCANPLUS TPG 4 1 Introduction irent tte re eere eX Cor oes esos setae eu dV ev Penetra Estes Cenas eeu e i eU eve T avus o bea dias rere a tout ee dice ina css atos isa ie s 4 1 Description of the Unit Under Test eresnvsnnvennvennennvennesnnvenneennsenennneennnenennnennennnennennnennnennennnennnenennnenennnnnnennnennnenneee 4 2 TAP Connection and Termination poteci cete cai etre eese ua as wane a seas cul eed eee aca sinto 4 2 SCANIO M280LV Interface aeos eo Xs A see s in eee 4 2 Generating Test Vectors
3. 57 J457 ASIC2 98 58 J458 ASIC2 99 59 J4 59 ASIC2 100 60 GND Table 2 6 J4 Connector Pin Assignment SCANIO 280LV Installation 2 11 PIN Signal ASIC Pin PIN Signal ASIC Pin 1 J5 1 ASIC1 187 J5_2 ASIC1 188 3 J5_3 ASIC1 190 J5_4 ASIC1 192 5 GND J5 6 ASIC1 193 7 J5 7 ASIC1 194 J5_8 ASIC1 195 9 J5_9 ASIC1 196 10 GND 11 J511 ASIC1 197 12 J5_12 ASIC1 198 13 J5 13 ASIC1 199 14 J5 14 ASIC1 201 15 GND 16 J516 ASIC1 202 17 J5 17 ASIC1 203 18 J5 18 ASIC1 204 19 J5 19 ASIC1 205 20 GND 21 J5_21 ASIC1 206 22 J5_22 ASIC1 3 25105235 ASIC1 4 24 J5 24 ASIC1 6 25 GND 26 J5 26 ASIC1 7 27 J5 27 ASIC1 8 28 J5 28 ASIC1 9 29 J529 ASIC1 10 30 GND 31 J531 ASIC1 11 32 J5_32 ASIC1 12 33 J533 ASIC1 13 34 J5 34 ASIC1 15 35 GND 36 J5 36 ASIC1 16 37 J5 37 ASICLI7 38 J5 38 ASIC1 18 39 J5 39 ASIC1 19 40 GND 41 J5 AL ASIC1 20 42 15 42 ASIC1 21 43 15243 ASIC1 22 44 1544 ASIC1 24 45 GND 46 J5 46 ASIC1 25 47 J5_47 ASIC1 26 48 J5 48 ASIC1 27 49 J5 49 ASIC1 28 50 GND 51 Jxzst ASIC1 29 52 18 52 ASIC1 31 53 15259 ASIC1 33 54 J5 54 ASIC1 34 55 GND 56 J5 56 ASIC1 35 BT 1557 ASIC1 36 58 J558 ASIC1 37 59 J5_59 ASIC1 38 60 GND Table 2 7 J5 Connector Pin As
4. Disk SCANIO 280LV User s Manual Ensure all materials listed are present and free from visible damage or defects before proceeding If anything appears to be missing or damaged contact Corelis at the number listed on the front cover immediately Introduction To ensure reliable operation of the SCANIOTM 280LV it is important that it is connected properly to both the boundary scan tester and the unit to be tested If the design incorporates the recommended connectors and pin assignments then all connections are made with simple 1 1 cables Figure 2 1 shows the cable connections between the JTAG controller the SCANIO 280LV and the target UUT SCANIO 280LV Installation 2 1 40 Pin to Corelis 10 Pin 1 1 PCI 1149 1 or a PC 1148 1 100F Boundary Scan Controller SCANIO 280LV TAP Out pn 60 Pin 1 1 10 Pin 1 1 Cable I O Connector TARGET Figure 2 1 Connections Between JTAG Controller SCANIO 280LV and UUT Setting the Interface Voltage Before connecting to the boundary scan controller or the target Unit Under Test UUT it is necessary to set the interface voltage The Adjust rotary switch sets the interface voltage of the TAP and I O pins to voltages between 2 0V and 3 4V Use a small screwdriver to set the interface voltage The voltage appears on the LEDs The SCANIO 280LYV retains the set voltage interface value when powered on and off however it is better to check
5. NET J1 8 NET J1 9 Figure 4 3 Netlist Edit File for Example Design Creating Test Vectors The files necessary for creating boundary scan tests are on the distribution disk in the directory Example Copy these files over to the hard drive Double click on ScanPlusTPG Select New Test Step Select Interconnect Use the add button to add the files JDB net Scanio amp JDB top and Scanio amp JDB edt Select Generate Save the test step as Scanio amp JDB Interconnect The main window should now look like Figure 4 4 Buswire and infrastructure tests can similarly be generated by selecting the appropriate button To fully test the example board cluster test vectors which Application Example with ScanPlus TPG 4 5 stimulate the non boundary scan components and compare the response to expected values An explanation of this is beyond the scope of this User s Manual but can be found in the Corelis ScanPlus TPG User s Manual ScanPlusTPG Scanio amp JDB Interconnect tst Deja Netlist File C VSCANIO 280LVYExampleyJDB net Topology File C YSCANIO 280LVYVExampleyScaniosJDB top Constraint File Netlist Edit File C SCANIO 280LV Example ScaniosJDB edt Merge Pin Library Figure 4 4 ScanPlus TPG Test Step Application Example with ScanPlus TPG
6. in a single test plan that includes the infrastructure test Please follow these steps STEP1 STEP2 STEP3 STEP4 STEP5 STEPG6 STEP7 STEPS STEP9 STEP10 STEP11 Connect the 5V power supply to the SCANIOT 280LV Make sure no target is connected to the SCANIO 280LV then power it up by turning on the Power Switch Set the interface voltage by using a screwdtiver to rotate the adjust switch All three selftests can be run at any voltage Connect one end the TAP cable to the boundary scan controller and the other end to TAP In Connector on the SCANIO 280LV Connect a 60 pin 1 1 cable between J1 and J2 Connect a 60 pin 1 1 cable between J3 and J4 Connect a 60 pin 1 1 cable between J5 and J6 Double click on the ScanPlus Runner Icon Select File New Test Plan Click on the Add button and add Selftest_Infrastructure_inf cvf Selftest_Interconnect_ic and Selftest_Buswite_bus cvf in that order Select OK Select Ser up Controller then select the boundary scan controller being used and set the frequency to 10MHz Select Run Test The test should run and pass Figure 3 2 shows the results of running these tests ScanPlus Runner Untitled lolx File Setup Diagnostics View Help Test Steps Selftest Infrastructure inf cvf Passed Selftest_Interconnect_ic cvf Passed Selftest Buswire bus cvf Passed Test Status r Test Statistics s TE Toit 3 Passed Runs Run Test Close
7. must be added to the DEVICES section of the topology file in order from TDI to TDO Therefore U1 U2 U3 and U4 are added to the topology file in that order as shown in Figure 4 2 Application Example with ScanPlus TPG 4 3 Date I File I Engineer Company July 12 1999 K May Corelis Inc Scanio amp JDB top BOARD CHAIN chainl TDI TDO TDO TDI TMS TMS TCK TCK DEVICES ASICI ASIC280LV BSD ASIC2 ASIC280LV BSD Ul 74BCT8374 U2 74BCT8374 U3 74BCT8374 U4 74BCT8374 END DEVICES END CHAIN POFP208 POFPZ208 DW PACKAGE DW PACKAGE DW PACKAGE DW PACKAGE Boundary Scan topology file for the SCANIO 280 amp JTAG DEMO NO NO NO NO NO NO Figure 4 2 Example Topology File Using the Netlist Edit File The netlist edit file is used for making modifications to netlists In the case of the SCANIO 280LV the digital I O pins must be added to the target netlist On SCANIO 280LV disk a netlist edit file Scanio edt is provided Because the net names for the connectors in edit file match the net names in the target schematic the netlist edit can be used for merging the two netlists However the Scanio edt file contains nets for all of the SCANIO 280LV connectors our design only uses pins 1 47 therefore the netlist edit file must be truncated to only contain the used nets Each line in the netlist edit file adds a digital I O pin to the netlist of the target board Figure 4 3
8. the interface voltage by viewing the LEDs before connecting to a target board as an incorrect voltage setting may damage some targets Connecting to the JTAG Controller The SCANIOTM 280LV is connected to the JTAG controller via connector TAP In Table 2 1 shows the pin assignment for the TAP In connector The TAP In connector is the Corelis standard connector and can be connected to the Corelis controllers PCI 1149 1 or PC 1149 1 100F using a 40 pin to 10 pin 1 1 cable and can be connected to the other Corelis controllers with the cable provided with them SCANIO 280LV Installation 2 2 Pin SigmaName NO Description GND E GND God GND mad TNS MEMES O E SCS GND DO EC Table 2 1 TAP In Connection List Target TAP Connection Connect the target TAP to the TAP Out connector of the SCANIO 280LV The TAP Out connector has presence detect logic that will detect the UUT board and will include the UUT in the scan chain Figure 2 2 shows a diagram of this configuration If the target system has no boundary scan logic and no TAP do not connect anything to TAP Out Table 2 2 shows the connection list for the TAP Out connector Pin Signal Name WO Description GND Gm GND Ep GND fom fon fom GND O E Table 2 2 TAP Out Connection List SCANIO 280LV Installation 2 3 SCANIO 280LV PCI 1149 1 PC 1149 1 100F PCMCIA NET 1149 1 Boundary Scan Controllers or ANY IEEE
9. to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED CORELIS SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE EXCLUSIVE REMEDIES THE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER S SOLE AND EXCLUSIVE REMEDIES CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for Corelis products For assistance contact your nearest Corelis Sales and Service Office RETURN POLICY No items returned to CORELIS for warranty service or any other reason shall be accepted unless first authorized by CORELIS either direct or through its authorized sales representatives All returned items must be shipped pre paid and clearly display a Returned Merchandise Authorization RMA number on the shipping carton Freight collect items will NOT be accepted Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise RMA s can only originate from CORELIS If authorization is granted an RMA number will be forwarded
10. to the customer either directly or through its authorized sales representative Table Of Contents CHAPTER 1 PRODUCT OVERVIEW eeeeeeeeeeeeeeeennnnnn nennen nnn n nnn nnn 1 1 INtroducii Oresa TR 1 1 Features of the SCANTOIM280L Vs ces Q 1 1 288 Individually Controlled I O Signals eee anna cane nennen enne nnns 1 2 Adjustable Voltage Interfaces s siehe bee assis pensa re od Beati ede cdas 1 3 Daisy Chaining the T ADS aiite OD PEOEDRERIB EURO ta a til ab Hee e a eiie ad 1 3 el DA NAS tie AAA A 1 3 CHAPTER 2 SCANIO 280LV INSTALLATION uuunrnvvvnnnnnnnnnnnnnnnvvnnnnnnnnnnnnnnnnennnnnnnnnn 2 1 Introduction isa sta ae 2 1 Setting the Interface A MUI 2 2 Connecting to the JTAG Controller senvvnnvrnnvennvennvennvennnnneenneennennennnennnennnennnennennnennnennnennneenneenenennennnennennnennnennesnneee 2 2 Target TAP Connection ass session sesocseautestoessesesssocsesdsenseseseossvcscssesasdousesines A ree eU bine Ted od 2 3 Target TAP Design e EEE 2 4 Target TAP Schematics 2 5 Daisy Chaining the SCANIO W 280EN 4 eeu eere oet eee tan eta ene ne epe ed eet ere eo eain eee un e LE DES apelo case Jupan use dia 2 5 Digital I O Test Connection p
11. with ScanPlus TPG esnssenesevernneennesnnenennnennnennnennnennennnennnvnnnennennnennnennneennvennennnennnenneenneee 4 2 Example Topology File sem noe de o ee ede ve aee ipie adi 4 3 Using the Netlist Edit File eee eie een dean t 4 4 Creating Test Vectors aces ri caca dei te Arti a 4 5 Table of Figures Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 SCANIO 280LV Block Diagram eese nennen nennen ener ae 1 2 Connections Between JTAG Controller SCANIO 280LV and UUT eee 2 2 TAP Connection Between SCANIO 280LV and UUT reennennrnnnnnnennnnnennrnrenserrnnvesnrrnsrsrensessrrversarneersenser 2 4 Standard TAP connector top view nenea eene nre etnies 2 4 TAP Connector Schemaltics s Ed FU inet Fee anda Mage He be Reb noa a al 2 5 TAP Connection for Two Daisy Chained SCANIO 280LVs and a UUT sss 2 6 60 pin Connector Pin Numbering esee eee eerte trente reete reete 2 7 ScanPlus Runner Infrastructure Test aan enne trente entren eerie rent 3 3 ScanPlus Runner Interconnect and Buswire Test nana 3 4 Topology File Scanio top nenea nana anna iei i oi aie nana na 3 5 Neilist Edit PileSCaWo edt von eso enduro dor ttr e eite a une aa tina at i da roe tit e 3 6 Schematic of an Example Unit Under Test cena anna ea aan nana eee 4 1
12. 1149 1 Compliant Controller TDI TDO ASIC1 EERIE UNIT UNDER TEST Figure 2 2 TAP Connection Between SCANIO 280LV and UUT Target TAP Design The TAP contains 5 signals TCK TMS TDO TDI and optionally TRST It also contains ground signal s The Corelis recommended standard TAP connector is shown in Figure 2 3 and is widely regarded as the industry standard Note that each signal is terminated with resistor in order to minimize signal cross talk in the interface cable and maximize noise immunity The connector on the user s target should have the standard flat cable compatible pinout Below is the top view of the target 10 pin connector header 0 100 x 0 100 spacing TRST 1 I K 2 GND TDI 3 R XN 4 GND TDO 5 l K 6 GND TMS 71 3 M8 GND TCK 9 X mM 10 GND Figure 2 3 Standard TAP connector top view SCANIO 280LV Installation 2 4 The following are two 3M brand part numbers for the above connector Both are 0 100 x 0 100 headers one with and one without latch ejector Note that there are many other manufacturers who would have similar parts as well 3M Part Number Description 30310 6002HB Straight header 10 pin 4 wall with center notch 3793 5602UG Latch Ejector Straight header 10 pin 4 wall with notch Target TAP Schematics The typical schematics of the target TAP connector and the recommended termination resistors are shown in Figure 2 4 The 1K pull up resistors can be connect
13. 123 NET J1 21 Figure 3 4 Netlist Edit File Scanio edt Netlist A partial Telesis format netlist Scanio net is provided with the SCANIO 280LV The netlist shows the connectivity between the digital I Os and the connectors on the SCANIO 280LV It can be used for reference or to generate a selftest for the stand alone SCANIO 280LV board Provided Software 3 6 Chapter 4 Application Example with ScanPlus TPG Introduction To assist in the application of the SCANIOTM 280LV this chapter provides an example of using the SCANIO 280LYV to test the interconnects of an edge connector that is connected to boundary scan compatible buffers and some non boundary scan logic The example UUT is an actual board that 1s available through Corelis sales ask for the JTAG Demo Boatd Figure 4 1 shows a partial schematic for the example given in this chapter P1 NET J1 1 b NET 12 NET JI 3 3 NET J14 USA i NET 44 1 1 E NET J1 6 NET 12 3
14. 142 42 J1 42 ASIC1 144 43 J1 43 ASIC1 145 44 J1 44 ASIC1 146 45 GND 46 J1 46 ASIC1 147 47 J1 47 ASIC1 148 48 J1 48 ASIC1 149 49 Ji 49 ASIC1 150 50 GND 51 JI_5i ASIC1 151 52 1 52 ASIC1 153 53 J153 ASIC1 154 54 J1_54 ASIC1 159 55 GND 56 J1 56 ASIC1 160 57 J157 ASIC1 161 58 J1_58 ASIC1 162 59 J1_59 ASIC1 163 60 GND Table 2 3 J1 Connector Pin Assignment SCANIO 280LV Installation PIN Signal ASIC Pin PIN Signal ASIC Pin 1 J2 1 ASIC2 101 2 J22 ASIC2 102 3 J2 3 ASIC2 108 4 J2 4 ASIC2 109 5 GND 6 J2 6 ASIC2 110 7 J2 7 ASIC2 111 8 J2 8 ASIC2 112 9 J2 9 ASIC2 113 10 GND 11 J211 ASIC2114 12 922 12 ASIC2 115 13 J213 ASIC2 117 14 J2 14 ASIC2 118 15 GND 16 J216 ASIC2 119 17 J217 ASIC2 120 18 1218 ASIC2 121 19 J2 19 ASIC2 122 20 GND 21 J221 ASIC2 123 22 J2_22 ASIC2 124 23 J2_23 ASIC2 126 24 J2 24 ASIC2 128 25 GND 26 2 26 ASIC2 129 27 J2_27 ASIC2 130 28 J2_28 ASIC2 131 29 J2_29 ASIC2 132 30 GND 31 J231 ASIC2 133 32 J2_32 ASIC2 135 33 12 33 ASIC2 136 34 J2_34 ASIC2 137 35 GND 36 J236 ASIC2 138 37 J237 ASIC2 139 38 J2 38 ASIC2 140 39 J2 39 ASIC2 141 40 GND 41 J2 41 ASIC2 142 42 J2 42 ASI
15. C2 144 43 J2 43 ASIC2 145 44 J2 44 ASIC2 146 45 GND 46 J2 46 ASIC2 147 47 J2 47 ASIC2 148 48 J2 48 ASIC2 149 49 J2 49 ASIC2 150 50 GND 51 J251 ASIC2 151 52 J2_52 48102155 53 J2 53 ASIC2 154 54 J2 54 ASIC2 159 55 GND 56 J2 56 ASIC2 160 57 J2 57 ASIC2 161 58 J2 58 ASIC2 162 59 J2 59 ASIC2 163 60 GND Table 2 4 J2 Connector Pin Assignment SCANIO 280LV Installation PIN Signal ASIC Pin PIN Signal ASIC Pin 1 J21 ASIC1 39 J2 ASIC1 40 3 J23 ASIC1 42 J3_4 ASIC1 43 5 GND J3 6 ASIC1 44 7 PE ASIC1 45 J3_8 ASIC1 46 9 J9 ASIC1 47 10 GND 11 J3 11 ASIC1 48 12 J312 ASIC1 49 13 J313 ASIC1 55 14 J3 14 ASIC1 56 15 GND 16 J316 ASIC1 57 TT JAY ASIC1 58 18 J3 18 ASIC1 58 19 J3 19 ASIC1 60 20 GND 21 13 21 ASIC1 61 22 1 J322 ASIC1 62 23 J3_23 ASIC1 64 24 J3_24 ASIC1 65 25 GND 26 J3 26 ASIC1 66 27 J3_27 ASIC1 67 28 1328 ASIC1 68 29 J3_29 ASIC1 69 30 GND 31 J331 ASIC1 70 32 13 32 ASIC1 71 33 J3 33 ASIC1 73 34 J3 34 ASIC1 76 35 GND 36 J3 36 ASIC1 77 37 J3 37 ASIC1 78 38 J3 38 ASIC1 79 39 J3_39 ASIC1 80 40 GND 41 J341 ASIC1 81 42 J3_42 ASIC1 84 43 J3_43 ASIC1 86 44 J3 44 ASIC1 67 45 GND 46 J3 46 ASIC1 88 47 J3_47 ASIC1 89 48 J3 48 A
16. CORELIS SCANIO 280LV SCANIO 280LV Boundary Scan Based Digital Tester User s Manual CORELIS SCANIO 280LV SCANIO 280LV Boundary Scan Based Digital Tester User s Manual Copyright 1999 2002 Corelis Inc 12607 Hiddencreek Way erritos CA 90703 2 C 146 Telephone 562 926 6727 Fax 562 404 6196 Preface PRINTING HISTORY New editions are complete revisions of the manual Update packages which are issued between editions contain additional and replacement pages to be merged into the manual by the customer The dates on the title page change only when a new edition is published A software code may be printed before the date this indicates the version of the software product at the time the manual or update was issued Many product updates and fixes do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual updates Edition 1 July 1999 Edition 2 November 2001 Edition 3 June 2002 GENERAL NOTICE Information contained in this document is subject to change without notice CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing performance or use of material contained in this manual This document contains proprietary information which is protected by copyright All rights rese
17. Example Topology File nouta ti it Dam ut a dota oett i Dana o 4 4 Netlist Edit File for Example Design nana nana aan nana nana 4 5 ScanPlus EP GTCStSICD sc is e a Utada ds e o erre eee ee encres aq dd rd da dns 4 6 Table of Tables Table 2d TAP In Connection LASA ce ata ada A eere dee es tondeuse eee tera 2 3 Table 2 2 TAP Out Connection List dias eet rte a deser eee vede ins 2 3 Table 2 3 JI Connector Pin Assignm it ualet rire aaa aa eund teo eb eee s eua es eed one a eta 2 8 Table 2 4 J2 Connector Pin Assignment esee eene ea ae aan ae aa aaa nana eee a 2 9 Table 2 5 J3 Connector Pin Assignment esses netten trennen rerit aan nana enne 2 10 Table 2 6 J4 Connector Pin Assignment eese eene anna aan nana nana 2 11 Table 2 7 J5 Connector Pin Assignment eese tentent eene rennen nana enne 2 12 Table 2 8 J6 Connector Pin Assignment esee eet eene eet anna anna tree eerte enne 2 13 Table 2 9 Mating Connectors for the SCANIO M280L V esee e ennemi eres 2 14 Table 2 10 Mating TAP Connector for PCI 1149 1 and PC 1149 1 100F sse 2 14 Chapter 1 Product Overview Introduction The SCANIOTM 280LV Digital Tester module provides a low cost alternative to traditional stimulus response digital testing Through the use of boundary scan technology the SCANIOTM 280LV module provides a total of 288 fully bidirectional test channels with virtually unlimi
18. Figure 3 2 ScanPlus Runner Interconnect and Buswire Test Provided Software 3 4 Using the SCANIO 280LV Files The SCANIO 280LV has four files that describe its functionality Scanio top Scanio net Scanio edt and Scanio bsd These files can also be used as inputs to the Corelis ScanPlus software Boundary Scan Topology The scan chain for the SCANIOT 280LV is described in the topology file Scanio top shown in Figure 3 3 below The file shows that the SCANIO 280LV contains two boundary scan devices in order from TDI to TDO that are referenced as ASIC1 and ASIC2 These two devices are described by BSDL file ASIC280LV BSD and they are 208 pin PQFP devices When a second boundary scan UUT is connected to the SCANIOT 280LV via the TAP Out connector it follows the SCANIOT 280 in the boundary scan chain To create a new topology file desctibing the whole system simply add the boundaty scan components of the UUT to the Scanio top file after ASIC2 Chapter 4 contains a complete application example Date July 12 1999 Engineer K May Company Corelis Inc File Scanio top I Boundary Scan topology file for the SCANIO 280LV CHAIN chainl TDI TDO TDO TDI TMS TMS TCK TCK DEVICES ASIC1 ASTC280LV BSD POFP208 NO ASIC2 ASIC280LV BSD POFP208 NO END DEVICES END CHAIN Figure 3 3 Topology File Scanio top Boundary Scan Description Language BSDL The BSDL file for the two boundaty scan com
19. NET J17 2 H NET J1 8 9 7AACTOO ET NET tti U6B NET J1 12 4 12 NET J1 13 6 NET J1 36 Ja NET J1 14 5 5 NET J1 16 NET Jt 4 18 NET Ji 17 NET Ji 8 SANTOS Ei NET Ji 18 UBC 48 NET J1 19 ut ue 9 1 1 8 NET J1 37 20 CLK Jar 21 a 24d oc NEG 24d oc NEG n 22 NET Ji 23 NAND1 OUT 15 10 DATA O 15 10 NAND2 IN2 2 NET J1 24 NET J1 7 16 DB Q8 9 DATA 1 16 D8 8 9 NAND3 INT TAAGTOD 24 NET JT 8 17 07 Q7 8 DATA T 17 or Q7 8 NAND3 INZ USD 254 DE 06 D Q6 E NET J1 26 NET Ji 9 o Q6 7 DATAS FI IEE di 6 7 NAND4 INT 12 NET Ji 27 NET JI 11 20 5 DATA 4 E 20 Q5 5 NANDA INZ 11 NET J1 38 x NET J1 28 NET J1 12 21 Pa Q3 4 DATAS 21 Di Bia 13 d NET Ji 29 NET J1 13 22103 3 DATAS cn alo EJ NET J1 14 23 2 DATAT 23 S za 20 Here Dia Dit NET Ji 32 TDO 14 11 14 1 2 NET Ji 33 TOU SIDO TOF mo NET J1 39 34 2 X 748CT8374 2 74BCT8374 35 4 E E e NET J1 36 x NET J1 37 F NET J138 NET J1 39 TMS H 2d TCK E I PEL NET 4 NET Ji 42 ae NET J1 43 FI NET J1 d E ner 41 46 NET J1 47 NET J1 16 d Ex NET J1 17 piss NET J1 18 TA sort TAACT74 51 pase d alt fran 53 X 54 X CLK 55 Hx 56 PX NET 1 21 210 amp 0 EL 57 X 58 px NET Ji 22 ap i i fer 60 Las CLK CLK NET J1 19 Bad oc NEG 24d OC NEG lt 15 10 15 10 NAND2 IN1 en 16 22 So i 15 28 Q8 9 Fri DATA NET J1 23 17 ag 17 Q7 8 FFI CLK vec NET J1 24 19108 0817 19 D8 Q6 L7 FFi PR uz 9 NET J1 26 fF 20125 05 5 Fro OL D4 Q4 x D
20. SIC1 90 49 J3 49 ASIC1 91 50 GND 51 J351 ASIC1 92 52 15 32 ASIC1 93 53 J353 ASIC1 95 54 J3 54 ASIC1 96 55 GND 56 J3 56 ASIC1 97 57 3_57 ASIC1 98 58 J358 ASIC1 99 59 J3 59 ASIC1 100 60 GND Table 2 5 J3 Connector Pin Assignment SCANIO 280LV Installation 2 10 PIN Signal ASIC Pin PIN Signal ASIC Pin 1 J4 1 ASIC2 39 J42 ASIC2 40 3 4_3 ASIC2 42 J4 4 ASIC2 43 5 GND J4 6 ASIC2 44 7 J47 ASIC2 45 4_8 ASIC2 46 9 J49 ASIC2 47 10 GND 11 JA 11 ASIC2 48 12 J4 12 ASIC2 49 13 J413 ASIC2 55 14 J414 ASIC2 56 15 GND 16 J4 16 ASIC2 57 TT J417 ASIC2 58 18 J418 ASIC2 58 19 J419 ASIC2 60 20 GND 21 JA 21 ASIC2 61 22 1422 ASIC2 62 23 J4 23 ASIC2 64 24 14 24 ASIC2 65 25 GND 26 J4 26 ASIC2 66 27 J427 ASIC2 67 28 J4_28 ASIC2 68 29 J4 29 ASIC2 69 30 GND 31 J431 ASIC2 70 32 14232 ASIC2 71 33 J4 33 ASIC2 73 34 J4 34 ASIC2 76 35 GND 36 J4 36 ASIC2 77 37 JA 37 ASIC2 78 38 J4 38 ASIC2 79 39 JA 39 ASIC280 40 GND 41 JA41 ASIC2 81 42 J4 42 ASIC2 84 43 J4 43 ASIC2 86 44 J4 44 ASIC2 67 45 GND 46 J4 46 ASIC2 88 47 J4 47 ASIC289 48 J4 48 ASIC2 90 49 J4 49 ASIC2 91 50 GND 51 J451 5162 92 52 J452 ASIC2 93 53 J453 ASIC2 95 54 J4 54 ASIC2 96 55 GND 56 J456 ASIC2 97
21. acteristics Symbol Parameter Conditions MIN MAX UNIT e qe no ge els VCC Sel 2 5V interface 23 Pepe per Vy High Level Input Voltage 1 7 5 75 V Vi Low Level Input Voltage 0 5 0 8 V Vs 3 0V VCC Ion 8mA DC 2 4 V Ij47 0 1mA DC VCC 02 V 2 3V VCC I54 7 1004A DC 2 1 V Ion 1mA DC 2 0 V lou 2mA DC 1 7 V Vor 3 0V VCC I 78mA DC 045 V L 0 1mA DC 0 2 V 2 3V VCC 1 1004A DC 0 2 V Ij 7 1mA DC 0 4 V Ip 2mA DC 0 7 V Lo ru nq 10 f 10 pa Note It is recommended that no more than 50 of the outputs on any of the following two I O groups be subjected to the maximum current limits specified above at any one time Groupl J1 J3 J5 Group2 J2 J4 J6 Product Overview I O Connectors JTAG Connector TAP In 10 pin IDC 3M part no 3793 6302 or equivalent JTAG Connector TAP Out 10 pin IDC 3M part no 3793 6302 or equivalent I O Connectors J1 J6 60 pin IDC 3M part no 3372 6302 or equivalent Power Requirements From External Power Supply 5 Volts 3 0 Amp Maximum Operating Environment Temperature 0 C to 55 C Relative Humidity 10 to 90 non condensing Storage Environment Temperature 40 C to 85 C Product Overview 1 5 Chapter 2 SCANIO 280LV Installation The SCANIO 280LV product consists of the following components SCANIO 280LV Hardware 5V External Power Supply SCANIO 280LV Software
22. d for testing Each of these 280 channels can be independently programmed as input output or tri state high impedance To create a test system these test connectors need to be connected to the unit under test using a set of ribbon cables Figure 2 6 shows the way that the connectors are numbered To assist in the building of these cables Table 2 3 through Table 2 8 show the pin assignments for connectors J1 to J6 Figure 2 6 60 pin Connector Pin Numbering SCANIO 280LV Installation 2 7 PIN Signal ASIC Pin PIN Signal ASIC Pin 1 Ji_1 ASIC1 101 yi2 ASIC1 102 3 J1 3 ASIC1 108 J14 ASIC1 109 5 GND J1_6 ASIC1 110 7 Ji_7 ASIC1 111 J1 8 ASIC1 112 9 J1 9 ASIC1 113 10 GND 11 J111 ASIC1 114 12 J1_12 ASIC1 115 13 J1 13 ASIC1 117 14 J1 14 ASIC1 118 15 GND 16 J1 16 ASIC1 119 17 J1 17 ASIC1 120 18 J1_18 ASIC1 121 19 J1_19 ASIC1 122 20 GND 21 J1_21 ASIC1 123 22 J1_22 ASIC1 124 23 J1_23 ASIC1 126 24 J1 24 ASIC1 128 25 GND 26 Ji 26 ASIC1 129 27 Ji 27 ASIC1 130 28 J1_28 ASIC1 131 29 J1_29 ASIC1 132 30 GND 31 J131 ASIC1 133 32 J1_32 ASIC1 135 33 J1 33 ASIC1 136 34 J1 34 ASIC1 137 35 GND 36 J1_36 ASIC1 138 37 J1_37 ASIC1 139 38 J1 38 ASIC1 140 39 J1 39 ASIC1 141 40 GND 41 J1 41 ASIC1
23. d to TAP In connector on the SCANIO 280LV STEP5 Double click on the ScanPlus Runner Icon STEPG Select File New Test Plan STEP7 Click on the Add button and add Selftest Infrastructure inf cvf STEP8 Select OK STEP9 Select Ser up Controller then select the boundary scan controller being used and set the frequency to 10MHz STEP10 Select Run Test The test should run and pass Figure 3 1 shows a passing infrastructure test Provided Software 3 2 ScanPlus Runner Untitled of x File Setup Diagnostics View Help Test Steps t TestStepName O Rests Selftest Infrastructure inf cvf Test Status m Test Statistics Sto TE ou TG 3 0 Passed Runs Run Test Close Figure 3 1 ScanPlus Runner Infrastructure Test Provided Software Interconnect and Buswire Tests The interconnect and buswite tests verify that all 288 digital I Os of the SCANIOT 280LV are fully functional These tests are completed without a target attached To test all of the I Os three 3 60 pin 1 1 cables must be connected between pairs J1 and J2 J and J4 and J5 and J6 to establish interconnectivity between the connectors Note that this test not only tests the SCANIO 280LV digital I Os but also tests the connectivity of the 60 pin 1 1 cables If you ate using 60 pin 1 1 cables to connect to your tatget this is a good way to vetify that the cables are good The interconnect and buswire tests will be run
24. e nets and pins of a target board In such cases where the CAD system is unable to generate a Telesis or standard Allegro compatible Netlist file an optional utility is used to convert the standard CAD Netlist EDIF HDL etc to the Telesis format 2 BSDL files bsd The BSDL files are required for all boundary scan components that are used in the particular design The BSDL files are available from the original manufacturers of each particular boundary scan component The BSDL file for the components of the Application Example with ScanPlus TPG 4 2 SCANIO 280LV is ASIC280LV bsd and can be found on the disk provided with the this product 3 Topology file top This file provides information about the scan chain ordering and physical characteristics of the JTAG compatible devices on the target board Use the provided Scanio280 top topology file as a starting point then add the devices on your target board to it See the example below 4 Constraint file con This file allows the user to set nets to specified logic levels and specify other constraints that need to be maintained when generating test vectors for the target board This file is useful for user target boards that contain both boundary scan and non boundary scan components For such cases enable signals chip selects etc are required to remain in a particular state for the duration of the test in order to prevent the non boundary scan components from interfering wi
25. ed to any Vcc supply with nominal voltage between 2 5V to 5 0V Recommended resistor values are 5 Target Board To all Boundary Scan Devices To TDI of 1st Device in the chain From TDO of last Devices in chain To all Boundary Scan Devices To all Boundary Scan Devices Figure 2 4 TAP Connector Schematics Daisy Chaining the SCANIO 280LV The TAP Out port can be used to daisy chain multiple SCANIO 280LV modules together to form a high pin count digital test system A straight ten contact socket connector to socket connector flat cable can be used to connect adjacent SCANIO 280LV modules Connect the TAP Out from the first SCANIO 280LV module to the TAP In on the second module Repeat this until all modules are daisy chained Connect the UUT to the TAP Out of the last SCANIO 280LV Figure 2 5 show the TAP connections for two daisy chained SCANIO 280LV modules and a target UUT SCANIO 280LV Installation 2 5 Corelis PCI 1149 1 or PC 1148 1 100F Boundary Scan Controller 40 Pin to 10 Pin 1 1 SCANIO 280LV 10 Pin 1 1 Cable 10 Pin 1 1 Cable E I O Connector TARGET Figure 2 5 TAP Connection for Two Daisy Chained SCANIO 280LVs and a UUT SCANIO 280LV Installation Digital I O Test Connection Each SCANIO 280LV contains six 60 pin connectors which provide the digital I O channels use
26. es Corelis MSelftestNSelftest Infrastructure inf cvf ScanPlus Runner to execute test VSelftest STD 1149 1 1994 1994 IEEE 1149 1 VHDL Package Executing Selftest with ScanPlus Runner The SCANIO 280LV comes with three 3 compact vector format selftest files Selftest Infrastructure inf cvf Selftest Interconnect ic cvf Selftest Buswire bus cvf In order to execute these files you need Corelis ScanPlus Runner test execution software and a Corelis Boundary Scan controller such as the PC 1149 1 100F or PCI 1149 1 with cable To complete all three tests three 3 sixty pin 1 1 cables are necessary to provide loopback on the digital I O signals Infrastructure Test The infrastructure test verifies that a good TAP connection is being made between the controller and the SCANIO 280LV It also verifies that the boundary scan infrastructure of the two ASICs on the SCANIOT 280LV is fully functional The infrastructure test requires a Corelis boundary scan controller a SCANIOT 280LV unit and a cable to connect the two Please follow these steps STEP1 Connect the 5V power supply to the SCANIOT 280LV STEP2 Make sure no target is connected to the SCANIOT 280LV then power it up by turning on the Power Switch STEP3 Set the interface voltage by using a screwdriver to rotate the adjust switch All three selftests can be run at any voltage STEP4 Connect one end of the TAP cable to the boundary scan controller and the other en
27. l cross talk in the interface cable and maximize noise immunity SCANIO 280LV Interface Connector Pl on the example schematic is the interface with the SCANIO 280LV The net names on Pl were chosen to be the same as the net names for the J1 connector in the SCANIO 280LV netlist enabling easy netlist merging for Automatic Test Pattern Generation If board space permits it is recommended to used 60 pin 0 100 x 0 100 connectors with pinouts compatible with the SCANIO 280LV This allows easy connection with 1 1 cables The following is the 3M brand part number for the above connector with latch ejector 3M Part Number Description 3372 6302 Straight header 60 pin 4 wall with center notch Sometimes the SCANIO 280LYV is used to test a particular connector on a design which is not the same connector as used on the SCANIO 280LV This will work too the cable is just more complicated Generating Test Vectors with ScanPlus TPG In order to generate test vectors for a system with the SCANIO 280LV and UUT using the Corelis ScanPlus TPG it is necessary to collect create certain files It is advised to create a test design directory and to place all files in the same directory A list of the various required input files is contained in this section All files contain plain ASCII text which can be generated or changed with any editor 1 Netlist file net This file is generated by the user s CAD system and describes all of th
28. nals Each I O has a boundary scan input cell output cell and control cell associated with it Each pin can individually be set to read only write only or read and write simultaneously Product Overview 1 2 Adjustable Voltage Interfaces The voltage level of the I O and TAP interfaces is controlled by the adjust rotary switch and can be set to any voltage between 2 0V and 3 4V in increments of 0 10V The SCANIO 280LV has been characterized at 2 5V and 3 3V and has not been tested at the other voltage levels The I O and TAP interfaces are 5V tolerant at all voltage levels Daisy Chaining the TAPs The TAP In and a TAP Out connectors are used to daisy chain the TAPs of one or more boards Typically the SCANIO 280LV is connected in series with the boundary scan target The SCANIO 280LV also can be used in stand alone mode or several SCANIO 280LVs can be daisy chained together along with a target SCANIO 280LV Specifications Size and Form Factor Dimensions 9 580 x 7 453 x 0 792 Number of Test Points 288 per module expandable to more lines by connecting multiple modules in series Test Point Configurations Supported Each test point is individually programmable as input output or bidirectional Bypass Capability Either of the two blocks of 144 points may be bypassed on the ASICs Maximum ASIC Test Clock TCK Frequency Maximum TCK Frequency 10MHz Product Overview 1 3 I O and TAP Signals DC Char
29. ors needed to make cables for the JTAG connector and the I O port connectors Table 2 10 shows the mating 40 pin TAP connector for the PCI 1149 1 and the PC 1149 1 100F Reference Description Manufacturer Part Number TAP In 10 pin 100 x 100 3M 3473 6610 TAP Out Wiremount Socket Strain Relief 3M 3448 3010 J1 J6 60 pin 100 x 100 3M 3334 6660 Wiremount Socket Strain Relief 3M 3448 3060 Table 2 9 Mating Connectors for the SCANIO 280LV Reference Description Manufacturer Part Number P1 40 pin 100 x 100 3M 3417 6640 Wiremount Socket Strain Relief 3M 3448 3040 Table 2 10 Mating TAP Connector for PCI 1149 1 and PC 1149 1 100F SCANIO 280LV Installation 2 14 What s on the Disk The disk contains the following files Chapter 3 Provided Software Filename Description TM 7 ASIC280LV bsd BSDL file for the SCANIO 280LV boundary scan components Scanio edt Netlist edit file for use with Corelis ScanPlus tools Partial netlist shows connection of the digital I Os of the Scanio net two boundary scan components Boundary scan topology file for use with Corelis Scanio top ScanPlus tools Shows the scan chain from TDI to TDO of the SCANIO 280LV VExampleY 74bctB374 BSDL file for SN74BCT8374 boundary scan chips on example Unit Under Test Example ASIC280LV bsd BSDL file for the SCANIOT 280LV boundary scan components Exam
30. ple JDB net Telesis format netlist of example UUT Example Scanio amp JDB edt Netlist edit file for example UUT and SCANIO 280LV Example Scanio amp JDB top Topology file showing scan chain for example UUT and SCANIO 280LV Example STD_1149_1_1990 1990 IEEE 1149 1 VHDL Package Example STD_1149_1_1994 1994 IEEE 1149 1 VHDL Package Selftest ASIC280LV bsd BSDL file for the SCANIO 280LV boundary scan components Selftest Scanio top Boundary scan topology file for use with Corelis ScanPlus tools Shows the scan chain from TDI to TDO of the SCANIO 280LV Selftest Scanio net Partial netlist shows connection of the digital I Os of the two boundary scan components Selftest ScanioLoopBack edt Netlist edit file that merges connectors J1 with J2 J3 with J4 and J5 with J6 for use with ScanPlus TPG for loopback test pattern generation Selftest Selftest_Buswire_bus cvf Selftest buswire test vector file Requires Corelis ScanPlus Runner to execute test Must connect 60 pin 1 1 cables from J1 to J2 from J3 to J4 and from J5 to JO Selftest Selftest_Interconnect_int cvf Selftest interconnect test vector file Requires Corelis ScanPlus Runner to execute test Must connect 60 pin Provided Software 3 1 Filename Description 1 1 cables from J1 to J2 from J3 to J4 and from J5 to J6 Selftest infrastructure test vector file Requir
31. ponents on the SCANIO 280LYV is supplied on the software disk ASIC280LV bsd is used as an input file for the Corelis ScanPlus software or other Automatic Test Pattern Generator The BSDL file can also be used as a reference for people who are writing their own boundary scan test software The BSDL gives description of the component pinout signal names boundary scan register and boundary scan instructions that are supported Provided Software 3 5 Netlist Edit File The netlist edit file is used by the Corelis ScanPlus TPG tools to add digital I O signals of the SCANIO 280LV to the netlist of the UUT To use this file without modification the UUT netlist must define the same signal names as the netlist edit file Figure 3 4 shows part of the netlist edit file scanio edt for the SCANIO 280LV The edit file shows the connectivity between the SCANIO 280LV ASICs and the connectors The naming convention for the nets is Net Connector Name PinNumber Line one indicates that ASIC1 pin 101 is connected to connector J1 pin 1 Chapter 4 gives a complete example on how to use the edit file and how to label nets the UUT netlist add node ASIC1 101 NET Ul 1 add node ASIC1 114 NET J1 11 add node ASIC1 115 NET J1 12 add node ASIC1 117 NET J1 13 add node ASIC1 118 NET J1 14 add node ASIC1 119 NET J1 16 add node ASIC1 120 NET J1 17 add node ASIC1 121 NET J1 18 add node ASIC1 122 NET J1 19 add node ASIC1 102 NET J1 2 add node ASIC1
32. rved No part of this document may be reproduced ot translated to other languages without the prior written consent of CORELIS CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS PRODUCT WARRANTY This CORELIS product has a warranty against defects in material and workmanship for a period of 90 days from date of shipment During the warranty period CORELIS will at its option either repair or replace products that prove to be defective For warranty service or repair this product must be returned to a service facility designated by CORELIS Outside CORELIS service travel areas warranty service will be performed at the Buyer s facility only upon CORELIS prior agreement and Buyer shall pay CORELIS round trip travel expenses For products returned to CORELIS for warranty service the Buyer shall prepay shipping charges to CORELIS and CORELIS shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to CORELIS from another country CORELIS warrants that its software and firmware designated by CORELIS for use with an instrument will execute its programming instructions when propetly installed on that instrument CORELIS does not warrant that the operation of the instrument software or firmware will be uninterrupted or error free The foregoing warranty shall not apply
33. shows the netlist edit file for the example design Application Example with ScanPlus TPG add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node add node ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI ASI Cl cl cl cl C1 C1 cl cl C1 Ci Ci cl cl C1 cl cl C1 cl cl cl cl C1 Ci cl cl cl cl C1 C1 CL cl EL C1 C1 cl 101 114 115 CI 118 119 120 121 Cl 102 23 124 126 128 129 130 131 132 108 133 135 136 137 138 139 140 141 109 Cis 144 145 146 147 148 110 111 112 113 117 122 142 NET J1 1 NET J1 11 NET J1 12 NET J1 13 NET J1 14 NET J1 16 NET J1 17 NET J1 18 NET J1 19 NET J1 2 NET J1 21 NET J1 22 NET J1 23 NET J1 24 NET J1 26 NET J1 27 NET J1 28 NET J1 29 NET J1 3 NET J1 31 NET J1 32 NET J1 33 NET J1 34 NET J1 36 NET J1 37 NET J1 38 NET J1 39 NET J1 4 NET J1 41 NET J1 42 NET J1 43 NET J1 44 NET J1 46 NET J1 47 NET J1 6 NET J1 7
34. signment SCANIO 280LV Installation 2 12 PIN Signal ASIC Pin PIN Signal ASIC Pin 1 JO 1 ASIC2 187 6_2 ASIC2 188 3 J6 3 ASIC2 190 JO 4 ASIC2 192 5 GND JO 6 ASIC2 193 7 J6 7 ASIC2 194 J6_8 ASIC2 195 9 J6_9 ASIC2 196 10 GND 11 J6 11 ASIC2 197 12 J6 12 ASIC2 198 13 J6 13 ASIC2 199 14 J6 14 ASIC2 201 15 GND 16 J6 16 ASIC2 202 17 J6 17 ASIC2 203 18 J6 18 ASIC2 204 19 J6 19 ASIC2205 20 GND 21 J6_21 ASIC2 206 22 J6 22 ASIC2 3 23 J6_23 ASIC2 4 24 J6 24 ASIC2 6 25 GND 26 J6 26 ASIC2 7 27 J6 27 ASIC2 8 28 J6 28 ASIC2 9 29 6 29 ASIC2 10 30 GND 31 J6_31 ASIC2 11 32 J6_32 ASIC2 12 33 J6_33 ASIC2 13 34 J6 34 ASIC2 15 35 GND 36 J6 36 ASIC2 16 37 J6 37 ASIC2 17 38 J6 38 ASIC2 18 39 J6 39 ASIC219 40 GND 41 J6 41 ASIC220 42 J6 42 ASIC2 21 43 J6 43 ASIC222 44 J6 44 ASIC2 24 45 GND 46 J6 46 ASIC2 25 47 J6 47 ASIC226 48 J6 48 ASIC2 27 49 J6 49 ASIC2 28 50 GND 51 J6 5T ASIC2 29 52 J6_52 ASIC2 31 53 J653 ASIC2 33 54 J6 54 ASIC2 34 55 GND 56 J6 56 ASIC2 35 57 T6257 ASIC2 36 58 J6 58 ASIC2 37 59 J6 59 ASIC2 38 60 GND Table 2 8 J6 Connector Pin Assignment SCANIO 280LV Installation 2 13 Mating Connectors Table 2 9 shows the mating connect
35. ted memory depth per pin The module uses boundary scan gate arrays to add control and visibility to connectors traces and logic that are otherwise untestable using boundary scan techniques The SCANIOTM 280 combined with a boundary scan controller such as the Corelis PCI 1149 1 PC 1149 1 100F or Net 1149 1 operates as a traditional bed of nails test system except access to the stimulus and response I Os is accomplished using boundary scan technology Each pin can be individually configured as an input output or tri state Blocks of 144 I O channels can be bypassed using the boundary scan bypass command thus reducing the number of channels to fit the number of UUT I O s Reducing the number of I O channels reduces test times which can be important in time critical test applications Features of the SCANIO 280LV The SCANIO 280LV is built around two fully boundary scan compliant chips and supports 288 individually controllable digital I O The TAP and digital I O are 5V tolerant and their interface voltage can be configured to interface with 2 5V 3 3V or 5 0V systems The SCANIO 280LV can be daisy chained on a single TAP to other SCANIOTM 280LVs or targets Figure 1 1 shows a block diagram of the SCANIO 280LV Product Overview 1 1 TAP OUT Figure 1 1 SCANIO 280LV Block Diagram 288 Individually Controlled I O Signals The SCANIO 280LV contains two ASICS each with 144 individually controlled I O sig
36. th the boundaty scan tests This file is not necessary for the example presented here 5 Netlist Edit file edt This file allows the user to manipulate the netlist with a series of modification instructions without having to make changes to the original netlist file The SCANIO 280LV comes with a netlist edit file that is used to merge the SCANIO 280LV netlist with the target netlist 6 Cluster SDF file sdf A text file that is one of two files used specifically for cluster testing The SDF file which conforms to the TSSI file format specifies a list of nets which will be tested in the cluster Cluster tests are used to test non boundary scan components such as U6 in example schematic in Figure 4 1 Please see your ScanPlus TPG user s manual for a more detailed description and example of cluster testing 7 Cluster SLF file slf A text file that is one of two files used specifically for cluster testing The SLF file which conforms to the TSSI file format provides a list of test vectors which specify patterns to be applied to vatious nets and levels to sense from other nets on the cluster Example Topology File To create a new topology file describing the whole system simply add the boundary scan components of the target UUT to the provided Scanio top file atter ASIC2 Connecting the UUT to the TAP Out connector of the SCANIO 280LV adds the UUT to the end of the scan chain The boundary scan components on the target board

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