TMC304(TEG3) User`s Manual
Contents
1. RMODE 20r3 20 fn If RSTART is asserted outside of this safety area it is not guaranteed that the readout will start from the next cycle User can identify the start of reading by checking RRUN signal or synchronize the RSTART signal to CLK signal if necessary Teh Clock high time of PLL clock RMODE 0 or 1 or RCLK RMODE 2 or 3 e RMODE 0 8 1 Tch mmm en bm my PLL Clock 4 D T m T1 RSTART EZA RRUN RE RPz Rx5 Fx5 ZSG L W s T11 Ta o H Rxy Fx SS T10 RMODE 2 8 3 RMODE 2 or 3 RMODx RRUN RCLK DCHx RE Rxy Fxy RPz Rx5 Fx5 ZSG L T11 WS Readout Timin 0 To Readout System Reset System Clock CSR Select Read Write Address Bus Data Bus Level2 Buffer CH3 CH2 CH1 CHO Write Start Readout Trigger 43 3V RME To Readout Syst em Reset System Clock CSR Select Read Write Address Bus e Dat a Bus CO 7 TMC304 CIO g Data Bus RPO 6 an RA1 Rao lt Data Bus RO 5 A Jwa pt jes Data Bus FO 5 bik en CH2 Be Data Read CH1 a Data Strobe CHO 6800pF Write Start Exapmles of signal connections2. WR setup time ja T RA WR holdtime ERE pie Le CIO setup time 00 T6 Clo holdtime 30 TI T2 T3 T4 T5 T6 RAO 1 WR CS CIOO 7 CSR Write Cycle Timing Diagram RAO 1 WR CS T1 T5 T6 CIOO 7 e Input Recording Timing TI WSTART safety area starttiming po po 15 ns T2 WSTART safety area end timing J Tur ns T3 WRUNasserttimng ae 71 ns T4 WRUN negatetiming J29 73 Lol T5 Input recording timing fAebitwah TAL Lol If WSTART is asserted outside of this safety area it is not guaranteed that the input recording will start from the next cycle User can identify the start of recording by checking WRUN signal or synchronize the WSTART signal to CLK signal if necessary Input Recording Timing PLL cicok WSTART WRUN m REZ E E ME A Write Strobe Kai oo a E N KO poe Internal Signal e Readout Timing RSTART safety area start timing RMODE Oor1 Un RSTART safety area end timing RMODE Oor1 03 ns T5 RE assert to data line enable time LI 34 95 f ns RE negate to data line disable time Ian 102 ns ZSG L a e oi EMA T9 Rx5 Fx5 pulse width C LL Tcm08 Teh 23 ns TIO WS assert to data changetime LL os 33 ns TI WS pulsewidth Teho Tehs04 ns TI3 RCLK high pulse width Tch RMODE 20r3 5 Co T14 RCLKeycletime
3. OEH GL OZA SL OZYSL OL4 SL OLH 0 004 S04 0 00H SOU 9 0dy SM INTRODUCTION A Fine Time Measurement The measurement of the fine time is based on a 32 tap ring oscillator as shown in Fig 1 The circuit of the ring oscillator is modified to generate even number of egualy spaced timing signals and named Asymmetric Ring Oscilator 1 The frequency of the oscillator is stabilized with a PLL Phase Locked Loop circuit The level of the external signal is stored to latches at every Rising Edge Data Falling Edge Data 128W x 6b DPM 128W x 6b DPM Latch 8 Encoders Fig 1 TMC core circuit PIN DESCRIPTION I Input DI Differential Input O Normal Output TO Three State Output PU with internal pull up resistor PD with internal pull down resistor negative logic TMC pins e EDCLK I When this signal is High level CLKP CLKN pins are connected to a differential input receiver When this signal is Low level the CLKP pin is connected to a single ended input buffer and the CLKN is disconnected from the internal circuit e CLKP CLKN DI System clock inputs In a differential input mode CLKP act as a non inverting input and CLKN act as a inverting input In a single end mode CLKP pin is used as the clock input e DIV4 I Divide by 4 selection When this signal is high the internal oscillation clock is divided by 4 before the phase comparator of the PLL Thus the internal clock frequency has 4 time
4. TMC304 TEG3 User s Manual Yasuo Arai KEK National Laboratory for High Energy Physics 1 1 Oho Tsukuba Ibaraki 305 Japan araiy Okekvax kek jp http www atlas kek jp araiy Ver 1 5 Jan 17 2002 Chip designed in 1994 TMC304 previous name TMCTEG3 is a low power and high resolution multi hit Time to Digital Converter chip Input signals are digitized at TMC Time Memory Cell circuits in clock period 32 0 78 ns 40MHZz time bin The 32 bits of digitized data is then encoded into a hit bit and 5 bit data and stored in memories The memory is dual port memory so write and read can be performed at the same time and there is no dead time for data conversion There are 128 words of dual port memories and the chip can store 2 56 us to 12 8 us data depend on the system clock frequency If user wants to suppress zero data at the output signal correspond to the hit tag bit can be used as a strobe signal to next level buffer To stabilize the internal delay element PLL circuit is used User can select 10 50 MHz system clock x1 mode or 2 5 12 5 MHz clock x4 mode There are 4 Control and Status Registers CSR s which can be read and write from 8 bit CSR bus TMC304 chip has 4 input channels e Least Time Count e Time Resolution e Integral Linearity Error e Differential Linearity Error e Stability e System Clock Frequency e No of Channels e Recording depth e Double Hit Resolution e Readout mode e Data format
5. Voltage 3 0 to 3 6 V 0 to 70 C e DC Characteristics C Vig input High Vate Cd no input Low idee o o OH High Level Output RRUN WRUN ROSC Voltage IOH 4 mA B4 All Signals except above IOH 8 mA B8 All Signals except above IOH 8 mA B8 Ipps Quiescent Device VIN VDD or Vss Current V I IL O O V Low Level Output RRUN WRUN ROSC Voltage IOH 4 mA B4 3 state Output Leakage Current L Z IOL mA 3 0 VOH VDD V 2 5 2 0 1 5 1 0 0 5 Fig 1 Output High Level Current Characteristic VDD 3 3V Ta 25 C typ 0 5 1 0 1 5 2 0 2 5 VOL V Fig 2 Output Low Level Current Characteristic VDD 3 3V Ta 25 C typ 3 0 0 0 Vu HOI AC Characteristics VDD 3 3 V Ta lt 25 C ROSC WRUN RRUN Cload z 25 pF All other output signals Cload 50 pF e Clock Signal Characteristics L4 Differential clock amplitude AV T3 CLK rise and fall rate EDOKH TAL TAH CLK duty factor EDCLK H 06 10 14 External clock and PLL clock phase offset DIV4 1 1 External clock and PLL clock phase offset DIV4 0 n and PLL clock and PLL clock Clock Waveforms 1 f0 e EDCLK Low CLKP 0 8V TI e EDCLK High Vcenter Ta Clock Offsets CLK ove TA TO po a YO CLK DIV4 L gt a 16 PLL clock A pe x Tal Se X ZON EC ao internal ke Noi om n azil ER ROSC output e CSR Access Timing Symbol Characteristics JL Mi RA
6. e Supply Voltage e Process e Power Dissipation e Package Test Circuits MAIN FEATURES 0 6 3 1 ns bit RMS 250 ps 40 MHz lt 80 ps 40MHz lt 60 ps 40MHz 3 0 3 6 V 0 70 C 10 50 MHz x1 mode 2 5 12 5 MHz x4 mode 4 Channels 128 clock cycle 2 56 12 8 us 25 32 ns i Synchronous read mode individual channel zero suppress ii Synchronous read mode all channel zero suppress iii Asynchronous read mode 4 channel access iv Asynchronous read mode 1 channel access dual edge encode hit tag 5 bit 3 3 V 3 0 3 6V 0 5 um CMOS Sea of Gate 50 mW Channnel 40MHz Input 1MHz 0 5 mm lead pitch 144 pin plastic QFP Ring Oscillator NMOS and PMOS transistors W A SELE S66L WEIDE YIOJA ESJILTOEONWL dije e Zo L L L je on ke NENIL dENIL 4 NENIL deNIL a NENIL dLNIL aa NONILdONIL es pa LNDA H ier L OWY SO AM 0010 yoda PSs e lake ee lee le soa NS dMTD V O41U09 LISIY OSI WER ma Me 8 Ala DO OWLY AE EN MIOLM OSOH WISIN IS L l I I I I I l l I l I I Ga noo nov OSOINN l Na dn SOEN 9 1INOOU I l l I I I l I I I I l I I I l l eyo cyo Lyo 19 Ul0d M o4u09 LYVLISM UM MNHM Nda POM gzi X NA ZL EEN JOUOD L OGOWY NOHH 4 o11U09 au EE A EE EECH 4 indino riba OHDJA GL 0eJ SL
7. hould be stopped when reading RMODE 3 is an asynchronous read mode In the asynchronous mode data recording should be stopped when reading The data readout is done for each channel selected by DCHO and DCHI Readout timing is controlled by RCLK e DCHI O I These signals select readout channel when readout mode is 3 e RCLK I This signal is used to control the data readout timing in the asynchronous read mode RMODE or 3 e ZSG I This signal controls the timing characteristics of the hit tag outputs Rx5 Fx5 When this signal is asserted the hit tag outputs become pulsed output and can be used to strobe non zero data When this bit is negated the hit tag outputs has same timing characteristics as other data line e WSTART I This signal starts write cycle of the TMC e WRUN O This signal indicates the start of the write cycle in the TMC This is a synchronized signal with the system clock e RSTART I This signal starts readout cycle of the dual port memory e RRUN O This signal indicates the start of the readout cycle of the dual port memory This is a synchronized signal with the system clock e VGNO VGN3 O These pins are outputs of PLL loop filter and must be connected to external capacitors of 6800 pF e SFI SF2 I Selection of the PLL loop filter value These pins should be connect to Vdd e WS O Write strobe signal This signal can be used as a strobe signal of the data Rxy F
8. lue CSRO Miscellaneous control e NRPSYN read write Disable synchronous count up of the read pointer with write pointer When NRPSYN O the read pointer is incremented synchronous to the system clock when write cycle started If the NRPSYN 1 this automatic count up is inhibited e ENRPUP read write Enable automatic count up of the read pointer after asynchronous readout When ENRPUP 1 and in asynchronous read mode RMODE 2 or 3 the read pointer is incremented after negation of the RCLK Following bits are used to test chip Normal user should not set these bits e F R read write Test data select 0 rising edge 1 falling edge e TCHO 1 read write Test channel select TCH TCH1 TCHO e MTEST Memory Test select When this bit is set output of the Test Data Register TDR is connected to the input of the DPM and the input of TDR is connected to the output of encoder logic selected by TCH bits and F R bit e SHIFT Enable Shift In Out When this bit is set the value of the SIN bit is shifted into the encode register which is selected by CH bits at the end of CSR3 read write operation read write CSRI Read Pointer Register e RPR read write Read Pointer Register This is a 7 bit loadable up counter which outputs are connected to the read addresses of the Dual Port Memory DPM The read pointer is set through this register and read back present value of the
9. read pointer CSR2 Write Pointer Register e WPR read write Write Pointer Register This is a 7 bit up loadable up counter which outputs are connected to the write addresses of the Dual Port Memory DPM The write pointer is set through this register and read back present value of the write pointer CSR3 Test Data Register This register is used to test chip Normal user should not set this register e TDR read write Test Data Register e SIN read write Serial Input bit e SOUT read only Serial output bit Data Encoding Scheme Digitized data at TMC circuit is encoded before the write operation to the dual port memory The data encoding scheme is shown in the following table Bit position at which the data is changed from 0 to 1 is encoded in the rising edge data and bit position of 1 to 0 is encoded in the falling edge data Hit tag bit shows the existence of those transition In addition to the transition encoding user can get all 0 or all 1 information by taking the encoded data at no hit tag This may help more understanding of the signal behavior Rising Edge Rx5 1 Rx4 0 Comment i Encoded edge at 0 1 edge at 1 2 edge at 2 3 edge at 3 4 edge at 30 31 edge at 31 0 Fx4 0 Comment Encoded all 1 edge at 0 1 edge at 1 2 edge at 2 3 edge at 3 4 edge at 30 31 edge at 31 0 d d no rising edge u u no falling edge x don t care TMC304 Pin Assignment
10. s Signal Name io CIO evs o ewe Z jo Signal Name WE 28 am 30 TIN2P vs lt A 6p 68 WTCLD ROSC zob t rs A DEE mij VDD Ila 120 VDD movo 137 RPO mvo S negative logic Test Signals leave open P ZO O ig ase aja ue OZ MZZ0 G4 ele An Se SABA ONG SR Coots HEN Os sa SAS NSN SGT SOVS ISOSJOG We OO DT L TT des Mm vss m 109 Ges 1STROSC o gt ROSC GH mm ka VV TCL K CHI DCH R33 WTCEN vss ken VSS oo vss m WRUN zma id VDD mwn VDD R12 Fa Toshiba EL TC180G26HS besen DIV4 CS P 01019423 xx z e JAPAN UR RSTART DN W oN d SH SF2 WEE SC EDCLK fo GLKP mmm F03 Kb RPO RP1 mmm FO1 RP2 bes F00 VDD a VOD HN wm E cl mm NMOSD ples 37 NMOSG RPO mmm MONN EE x ARE og Fi Za Zanza Sue Ob Zu SY sin loh 8 SSS SS 8856585 STOMA 29 GBS SO 00 OF OO OO GP rrr rr Sr a azz 220422 ZZEDDO gt 5500 GO DON 8 EE ERT FEFE soc n c non connection Test Signals leave open TMCTEGS3 Pin Assignment Top View 95 2 22 Y Arai A SH z AN b T o S20 Q OFP144 Shrink 144 pin Plastic Flat Package unit mm e Maximum Ratings IN in npr Curen id stoma TSTG Storage Temperature 40 to 125 C e Recommended Operating Condition Vs s 0V Parameter DC Supply
11. s higher frequency of the system clock e RESET I This input pin is used to reset all the internal circuit When RESET is asserted internal registers and circuit are initialized The PLL circuit does not be affected in the reset operation when DIV4 is low When divide by 4 mode is selected DIV4 High phase lock is lost at the reset e CIO0 CIO7 L TO These I O pins are data lines for control bus which read and write the CSR registers e CS I This signal is a strobe signal for the control bus eRAO 1 I These pins are used as address line to the control bus e WR I This pin is a Read Write select signal in the control bus ED I When this signal is High level TINxP TINxN x 0 3 pins are connected to a differential input receiver When this signal is Low level the TINxP pin is connected to a single ended input buffer and the TINXN pin is disconnected from internal circuit e TINOP TIN3P TINON 3N DI I Inputs for time measuring signals In differential input mode TINxP act as a non inverting input and TINXN act as a inverting input In single end mode TINXxP is used for the input of clock e Rxy x 0 3 y 0 5 TO These signals are output of rising edge data The x denotes channel number and the y denotes bit number Bit 0 to 4 indicate encoded data and bit 5 indicates a hit tag Timing characteristic of the bit 5 is controlled by ZSG signal and user can select pulse or level output The
12. three state output buffer is controlled by a RE signal e Fxy x 0 3 y 0 5 TO These signals are output of falling edge data The x denotes channel number and the y denotes bit number Bit 0 to 4 indicate encoded data and bit 5 indicates a hit tag Timing characteristic of the bit 5 is controlled by ZSG signal and user can select pulse or level output The three state output buffer is controlled by a RE signal e RPO RP6 TO These pins provide the Read Pointer value with synchronous to the Rxy and Fxy The three state output buffer is controlled by RE signal e RE I This input controls the three state output buffers of Rxy Fxy and RPO 6 When RE is asserted those output buffers are enabled as shown below When RE is negated those output has high impedance enabled 3 RMODE RMODI RMODO RMODE O is a synchronous read mode and data will appear at the output at every clock cycle Each channel has its own hit tag bit RMODE 1 is almost same as the RMODEO but the RO5 indicates ORed signal of all 4 channel hit tag of the rising edge The F05 indicates ORed signal of all 4 channel hit tag of the falling edge In addition the R15 indicates ORed signal of all 4 channel hit tag of both rising and falling edge All other Rx5 signals have same value as in the RMODE 0 RMODEZ2 is an asynchronous read mode and all 4 channel data are read out simultaneously controlled by RCLK In the asynchronous mode data recording s
13. xy and RPO 6 Test purpose pins expert only Following pins are used for test purpose Normal user can leave those pins open e DN O PLL down signal UP O PLL up signal e ROSC O TMC ring oscillator clock output You can check internal clock signal throgh this pin when TSTROSC pin is connected to high level There is a PLL circuit for each channel and you can select the channel by DCHO 1 signals as shown below ISTROSC DCHI DCHO ROSC pee ii aje 0 fl ON ih CHO PIT led odgo Chat PLL Clock po Ch PLL Clock Ch3 PLL Clock obisko eee ee E e TSTROSC I PD Enable oscillator test When this signal is asserted PLL oscillator output select by DCHO and 1 is connected to ROSC pin In addition the selected signal is also supplied to the read pointer to check the frequency e ENRO I PU Enable radiation test ring oscillator ROOUT O Ring oscillator output for radiation damage test e WTCEN I PD WTCLK enable e WTCLK I PD Write test clock e NMOSG NMOSD PMOSG PMOSD COM Test transistor connections Each pis has input protection circuit CSR Registers CSR registers bit assignment SEE NE ME NEC MM ME MM NE MN NEC ECH MNA NE SHIFT MTEST NRPSYN ENRPUP TCHI TCHO E R R W 0 RWO RWO RWO RWO R W 0 RWO RWO Read Pointer register RPR R W 0 EE R W 0 SIN Test Data Register TDR RO R W 0 R W 0 R W x Readable Writeable Initial va
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