Home

eZ80190 Development Kit User Manual - Digi-Key

1. eZ80F91 Development Kit User Manual 62 E ik U Ya R6 4ok Ferrite Core U10 CS2 sty yoo lar CS_EX_IN M_TIPC 2 FL DIS 4 FL DIS 1 ESCH 5 5 hoz MEM CEN q eH MEM CEN3 xx H 5H i Voa MEM_CEN4 L215 m oHe vos L gt gt L_RD x 343 4 ae 19 7 vos 24 MEN PY Aly e H res jW Aaa Oy 28 2 Dis FL SIDACTOR P3100SB Ruta J20 EE S 314 Ho Vog m MU 2 28 EX_FL_DIS 1 EX FL DIS Sla Hus 14 M RING V VDD 22V10AILCC p ND Ou C3 C4 10K R7 0 001uF 0 001uF GND l2 CH 5 CT3 6 cre U13 9 1 SCL 1 16 VDD Kr ie 12 CTO TRIGA Sat L SDA 2 En We i8 GRE B LRR gt MRESET OVERR N mux o enp 16 h b hop B Ds MINA MUX SEL L SH 19 TRIG2 Pin2 5 MONTS M OUT A 2 51 D3 ED r c4 r rr BIG wes MIN C M OUT B LL s 3p Lan NM Ine Sl E e 1 GND MIN D M_OUT_C N 15 a A a 3 A i GND M_ouT_D 2 Ke CT DEI EN Ping PCA8550 Morea 74HCT374 GND a A a A DiS 1 Moto NERIN AN 11 E r4 4 r4 nem J CS0 CS0 Set AN2 2 A Est 9 8 GND 12 41 m 4 p r m
2. PBO ec cS_EX_JN MEM Cu MEM CEN2 MEM CENS OD00000 R10 0 Op j RI1 lr Die PBI PB2 SDA GND M00 DIS P MWAIT Dm CS3 GND EM_D7 EM Dei S EM DA EM D3 EM D2 EM DT ND PC Di PC6 DCDI PCS SRI Fe Dip PC3 CTSI PC2 RISI PCI_RXD1 PCO_TXD1 Ed RESET 6ND oo loo dis oo o o 5 1mm gt rs 165 1 mm 157 5 mm 167 6 mm Figure 5 Physical Dimensions of the eZ80 Development Platform UM014103 0803 PRELIMINARY Functional Description eZ80190 Development Kit User Manual 10 Diog Operational Description The eZ80 Development Platform can accept any eZ809 core based modules provided that the module interfaces correctly to the eZ80 Development Platform The purpose of the eZ80 Development Platform is to provide the application developer with a tool to evaluate the features of the eZ80190 device and to develop an application without building additional hardware eZ80190 Module Interface The eZ80190 Module interface provides easy an connection for the eZ80190 Module This interface is designed to fit future eZ80 modules and user developed modules using current eZ80 devices The eZ80190 Module interface consists of two 50 pi
3. User Manual Z Table 5 CPU Bus Connector J8 Signal Pin Function Direction A 0 7 3 10 Address Bus Low Byte Output A 8 15 13 20 Address Bus High Byte Output A 16 23 23 30 Address Bus Upper Byte Output RD 33 Read Signal Output RESET 35 Push Button Reset Output BUSACK 37 CPU Bus Acknowledge Signal Output NMI 39 Nonmaskable Interrupt Input D 0 7 43 50 Data Bus Bidirectional CS 0 3 53 56 Chip Selects Output MREQ 57 Memory Request Output WR 34 Write Signal Output INSTRD 36 Instruction Fetch Output BUSREQ 38 CPU Bus Request signal Input PHY 40 Clock output of the CPU Output Note All of the signals except BUSACK and INSTRD are driven by low voltage CMOS technology LVC drivers UO Functionality The eZ80 Development Platform provides additional functionality featur ing general purpose port an LED matrix a modem reset and two user trig gers These functions are memory mapped with an address decoder based on the Generic Array Logic GAL22IV 10D U15 device manufactured by Lattice Semiconductor and a bidirectional latch U16 Additionally U15 is used to decode addresses for access to the 7x5 LED matrix UM014103 0803 PRELIMINARY Operational Description 23 24 eZ80190 Development Kit User Manual Diog Table 6 lists the memory map addresses to registers that allow access to the above functions The register at address 800000h controls general pur pose por
4. 48 List of Tables PRELIMINARY UM014103 0803 eZ80190 Development Kit Introduction User Manual ZInp The eZ80190 Development Kit provides a general purpose platform for evaluating the capabilities and operation of ZiLOG s eZ80190 micropro cessor The eZ80F91 Development Kit features two primary boards the eZ80 Development Platform and the eZ80190 Module This arrange ment provides a full development platform when using both boards It can also provide a smaller sized reference platform with the eZ80190 Module as a stand alone development tool Kit Features The key features of the eZ80190 Development Kit are eZ80 Development Platform Up to 2MB fast SRAM 12ns access time Embedded Modem Socket with a U S Telephone Line Interface PC EEPROM DC Configuration Register GPIO Port and Memory Headers LEDs including a 7x5 LED matrix Jumpers Two RS232 connectors Console Modem 9VDC Power Connector RS485 connector JTAG Debug Interface ZiLOG Debug Interface ZDI ZiLOG Developer Studio II and the eZ80 C Compiler 1 The eZ80 Development Platform s RS485 and JTAG functions are not supported on the eZ80190 device UM014103 0803 PRELIMINARY Kit Features 2 eZ80190 Development Kit User Manual Diog e780190 Module eZ80190 device operating at 50 MHz 1 MB Flash Memory 512KB SRAM 10BaseT Ethernet Interface Real Time Clock with Battery Back Up e ZPAKII Debug
5. wire MOD_DIS nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 if any of the signals is Low Flash on the Module will be disabled if nDIS FL is High UM014103 0803 PRELIMINARY General Array Logic Equations eZ80190 Development Kit User Manual 77 Lig 4 wire nEXP EN nCS0 0 amp A7 0 amp A6 1 expansion module Flash enabled if this is 0 wire nDIS FL nFL DIS nEXP_EN nFL_DIS wire nDIS FL nFL DIS amp nEXP EN if either of them is 0 Flash is disabled assign nCS EX nEX FL DIS nEXP EN nEX FL DIS assign nL RD nmemen1 20 nmemen2 0 nmemen3 0 nmemen4 0 aE M EN 20 nCS EX 0 assign nmemen4 nCS2 0 K A7 A6 A5 A4 A3 5 h17 assign nmemen3 nCS2 0 K A7 A6 A5 A4 A3 5 h16 assign nmemen2 nCS2 0 K A7 A6 A5 A4 A3 5 h15 assign nmemenl nCS2 0 K A7 A6 A5 A4 A3 5 h14 assign nEM_EN nCS2 0 amp A7 A6 A5 A4 A3 A2 A1 A0 8 h80 endmodule U15 Address Decoder define anode 8 h00 define cathode 8 h01 def ine latch 8 h02 FOR ez809 Development Platform Rev B General Array Logic Equations PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Z ZInp This PAL generates signals that control Expansion Module access LED and the general purpose port
6. 3 4 CS EX is decoded in the CS2 memory space and is Application module located in the address range A00000h A7FFFFh addressing 5 6 CS_EX is decoded in the CS2 memory space and is Application module located in the address range A80000h AFFFFFh addressing 7 8 CS EX is decoded in the CS2 memory space and is Application module located in the address range B00000h B7FFFFh addressing UM014103 0803 PRELIMINARY Operational Description 40 eZ80190 Development Kit User Manual Zik Jumper J20 The J20 jumper connection controls the selection of the external chip select in the external application module When the shunt is placed the external chip select signal CS EX is disabled See Table 23 Table 23 J20 EX FL DIS Shunt Status Function Affected Device IN The jumper for EX FL DIS is IN The chip select on the application module is disabled OUT The jumper for EX FL DIS is OUT The chip select on the application module is enabled Connectors A number of connectors are available for connecting external devices such as the ZPAKII emulator PC serial ports external modems the con sole and LAN telephone lines J6 and J8 are the headers or connectors that provide pin outs to connect any external application module such as ZiLOG s Thermostat Applica tion Module Connector J6 The J6 connector provides pin outs to make use of GPIO functionality Connector J8 The J8 connector provides pin outs to access
7. This device is a GAL22LV10 5JC 5ns tpd or equivalent with Package 28 pin PLCC module 192 em pal nDIS EM nEM EN AO Al A2 A3 A4 A5 A6 A7 nRD DCD nWR nMEMRQ nIORQ nEM_RD nEM_WR nAN_WR nCT_WR nDIS_ETH UM014103 0803 PRELIMINARY General Array Logic Equations 79 eZ80190 Development Kit User Manual Z Diog input nEM AO Al A2 A3 24 A5 A6 A7 nIORQ nRD DCS nWR nMEMRQ Ei Zi output nEM RD nEM WR nCT WR nAN WR nDIS ETH synthesis nDIS EM synthesis loc P3 syn syn syn syn syn syn syn syn syn syn syn syn syn syn thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis synthesis synthesis synthesis synthesis parameter anode 8 h00 parameter cathode 8 h01 parameter latch 8 h02 General Array Logic Equations loc P4 loc P5 loc P6 loc P10 loc P11 loc P12 loc P13 loc P27 loc P26 locs P2 loc P7 Loc P25 loc P9 loc P16 loc P17 loc P18 loc P19 loc P20 loc P21 PRELIMINARY CS3 for CS9800 UM014103 0803 UM014103 0803 eZ80190 Development Kit User Manual Zi Tiig wire 7 0 address A7 A6 A5 A4 A3 A2 A1 A
8. nEM_EN enables Development Platform LED and the general purpose port nDIS FL disables E N ET Module Flash when Low nL RD enables local data bus to be read by CPU nmemenl nmemen2 nmemen3 nmemen4 input nFL DIS HRZ SU nCs2 A7 A6 A5 A4 A3 A2 Al AO nEX_FL_DIS input 7 0 A General Array Logic Equations upper part of syn syn syn syn syn syn syn syn syn syn syn syn thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis loc P4 loc P5 loc P3 was 23 loc P6 loc P7 loc P9 loc P10 loc P11 loc P12 loc P13 loc P16 loc P2 Address Bus of 190 A23 A7 A22 A6 A21 A5 A20 A4 A19 A3 A18 A2 A17 A1 A16 A0 PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Zi ZInp output nCS EX synthesis loc P17 enables memory on the Expansion Module nmemenl synthesis loc P18 enables memory on the Development Platform nmemen2 synthesis loc P19 nmemen3 synthesis loc P20 nmemen4 synthesis loc P21 nEM EN synthesis loc P24 enables LED and the general purpose port nDIS FL synthesis loc P25 nL RD synthesis loc P23 wire nCS EX nmemenl nmemen2 nmemen3 nmemen4
9. ZiLOG eZ80190 Development Kit User Manual PRELIMINARY UM014103 0803 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com eZ80190 Development Kit User Manual Z Diog This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2003 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized
10. Thermostat Demo Application Note ANO104 on zilog com PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual za 55 UMO014103 0803 PRELIMINARY ZPAKII eZ80190 Development Kit User Manual 56 Diog ZDS II ZiLOG Developer Studio II ZDS II Integrated Development Environ ment is a complete stand alone system that provides a state of the art development environment Based on the Windows Win98SE NT4 0 SP6 Win2000 SP2 WinXP user interfaces ZDS II integrates a language sensitive editor project manager C Compiler assembler linker librarian and source level symbolic debugger that supports the eZ809 CPU For more information about using and configuring ZDS II please refer to the ZiLOG Developer Studio II eZ80 User Manual UM0123 ZDS Il PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual AP ZInp Troubleshooting Overview Before contacting ZiLOG Customer Support to submit a problem report please follow these simple steps If a hardware failure is suspected con tact a local ZiLOG representative for assistance Cannot Download Code If you are unable to download code to RAM using ZDS make sure to press and release the Reset button on the eZ80 Development Platform prior to selecting Build Debug Reset Go in ZDS No Output on Console Port The eZ80190 Development Kit is shipped with a Flash Loader utility that is loaded in the protected boot sector of Flash memor
11. Interface Tool 4 port 10BaseT Ethernet hub e eZ809 Software and Documentation CD ROM Hardware Specifications Table 1 lists the specifications of the eZ80 Development Platform Table 1 eZ80 Development Platform Hardware Specifications Operating Temperature 20 C 5 C Operating Voltage 9 VDC eZ80 Development Platform Overview The purpose of the eZ80190 Development Kit is to provide the developer with a set of tools for evaluating the features of the eZ80 family of devices and to be able to develop a new application before building appli cation hardware The eZ80 Development Platform is designed to accept a number of application specific modules and eZ80 based add on mod ules including the eZ80190 Module which features an Ethernet MAC a Real Time Clock and the eZ80190 microprocessor with a fast Multiply Accumulate unit Introduction PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Tiig 3 When attached to the eZ80 Development Platform the eZ80190 Module can operate in stand alone mode with Flash memory or interface via the ZPAKII debug interface tool to a host PC running ZiLOG Developer Stu dio II Integrated Development Environment ZDS IDE software If the user s eZ80 application demands Internet connectivity and or a network connection the eZ80190 microprocessor can serve web pages over a TCP IP network allowing easy system monitoring and control and effortless processor
12. Liga eZ80 Development Platform Hardware Specifications 2 eZ809 Development Platform Peripheral Bus Connector Identification JP11 0 0 eee eee KK KK 12 eZ80 Development Platform I O Connector Identification JP21 0 KK KK KK KK KK KK KK eee 17 GPIO Port Connector Jo 21 CPU Bus Connector J8 u uuuueuuaanaanaan aea 23 LED and Port Emulation Addresses 24 LED Anode General Purpose Port Output Control IX uj PE 24 General Purpose Port Data Register LL 25 Bit Access to the LED Cathode Modem and Triggers 26 Connector JS xy ex es ARE N e Ra ana e 9 29 Connector JO etie RES kul nk tea cia AG ee 29 Connector JI 30 J3 DIS EM bea teehee eae da ede dg 35 J7 Flash WE 5 ds dae eo aah ils eR ERR bee 35 JII DIS FL i i s4 lt k a ee eee 36 J12 5VDC 3 3VDC for an Embedded Modem 36 dq T 37 J15 RS485_1_EN kk kk KK KK KK KK KK KK KK KK KK Ke 37 J16 RS485 2 EN 4 al A 0 iett eee 38 KE WEE 38 JIS RT 2 i 2 ues e kb bee eda hee d 39 JI9 EX SEL 24 eset ede a waye an a 39 J20 BX FE DIS ri eR etes 40 PRELIMINARY List of Tables xi eZ80190 Development Kit User Manual xii Tika Table 24 PC Addresses oo Waa kk kk kK kK KK KK KK Kn 41 Table 25 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads 42 Table 26 Ethernet Connector Pin Assignments
13. United States only Connecting the modem outside of the U S requires modification eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diipa 31 eZ80 Development Platform Memory Memory space on the eZ80 Development Platform consists of onboard SRAM and additional footprints Onboard SRAM The eZ80 Development Platform features 512KB SRAM at U20 This SRAM provides the basic memory requirement for small applications development This SRAM is in the address range B80000h BFFFFFh Additional SRAM The amount of eZ80 Development Platform memory can be extended if required by adding SRAM devices U19 U18 and U17 provide this capa bility However the user should be aware that additional SRAM must be installed in the following order 1 U19 address range 800000h B7FFFFh 2 U18 address range A80000h AFFFFFh 3 U17 address range A00000h A7FFFFh If SRAM memory is installed in a different order than the above sequence SRAM will not be contiguous unless the user is able to change the address decoder U10 Memory access decoding is performed by this address decoder implemented in the Generic Array Logic device GAL22LV 10D U10 Memory Map A memory map of the eZ80 CPU is illustrated in Figure 10 Flash mem ory and SRAM on the eZ80190 Module are addressed when CSO and CST are active Low SRAM on the eZ80 Development Platform is addressed when CS2 is active Low The eZ80190 M
14. code updates The address bus data bus and all eZ80190 Module control signals are buffered on the eZ80 Development Platform to provide sufficient drive capability A block diagram of the eZ80 Development Platform and the eZ80190 Module is shown in Figure 1 UM014103 0803 PRELIMINARY eZ80 Development Platform Overview eZ80190 Development Kit User Manual Z 4 Diog Peripheral Device Signals Ethermet Module Interface RS232 0 Console SRAM 512 KB up to 2 MB RS232 1 Modem RTC with Battery eZ80190 and Module Address Decoder Application Module Headers Figure 1 eZ80 Development Platform Block Diagram with eZ80190 Module Introduction PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual y o Tiig Figure 2 is a photographic representation of the eZ80 Development Plat form segmented into its key blocks as shown in the legend for the figure xx Ti TE a Y 1 Hr E i TI Key to blocks A E A Power and serial communications D Application module interfaces B eZ80190 Module interface E General Purpose Port and LED with address C Debug interface decoder Figure 2 The eZ80 Development Platform UM014103 0803 PRELIMINARY eZ80 Development Platform Overview eZ80190 Development Kit User Manual Diog Figure 3 is a photographic representation of the eZ80190 Module seg mented into its key blocks as shown in the legend for
15. eZ80 CPU and the eZ809 Development Platform Jumpers The eZ80 Development Platform provides a number of jumpers that are used to enable or disable functionality on the platform enable or disable optional features or to provide protection from inadvertent use Jumper J2 The J2 jumper enables disables IrDA transceiver functionality When the shunt is placed IrDA communication is disabled This jumper does not perform any functions when the eZ80190 Module is installed eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Ap ZInp Jumper J3 The J3 jumper connection controls the mode of the general purpose port and communication with the 7x5 LED When the shunt is placed the general purpose port is disabled See Table 13 Table 13 J3 DIS EM Shunt Status Function Affected Device In Application Module Communication with 7x5 LED and Port emulation Hardware Disabled circuit is disabled Out Application Module Communication with 7x5 LED and the general Hardware Enabled purpose port circuit is enabled Jumper J7 The J7 jumper connection controls Flash boot loader programming When the shunt is placed overwriting of the Flash boot loader program is enabled See Table 14 Table 14 J7 FlashWE Shunt Status Function Affected Device Out The Flash boot sector of the eZ80190 Flash boot sector of the eZ80190 Module is write protected Module In The Flash boot sector of the e
16. gt CON_DIS gt gt MOD_DIS a o 5244 PHI 2 c D PH 293 T TTT T TQ74LVT125 TQ74LVT125 GND SR RD AN4 4 5 2 ba S amp Dis 0 WR rd d rd rh r J19 SDA ns 5 7 CS EX IN 2 1 2 8 EX SDA uc T8 By ieee C82 ER 74HCT374 j be 4 A 4 4 A gt gt DIS_IRDA SMEM CENS e 2 VDD GND 6 CS3 cs3 X U B VDD EX_SEL Re LTP 757 TQ74LVT125 10K R10 R11 R12 10K 10K 10K U15 2 GND DIS_EM 1 a 17 EM RD EVER iu voo HE EM WE EM D7 su 12 UO EM De MN A0 5 19 CT WR E 13 1 02 EM D5 o o 5 PBO TO 8 M5 a uos 2 AN WR EM D4 WE Z 5 Wou H21 gt gt DIS_ETH EM_D3 SW PUSHBUTTON A2 e O5 EM D2 A5 Hr vos H E EM D1 EEN Ad 18 1 07 6 EM DO o o gt gt PB1_T1_I 12 jo vos 28 BS 13J 10 uos H2 A SW PUSHBUTTON MEMRQ gt 16 41 28 VDD A IORQ e EM_WR_OE 413 24 VDD Iw IORQ X 2 CLK I0 GND f 3 OEAB vcc o 9 gt gt PB2_SS Our OEBA END 2 SW PUSHBUTTON 22V10AILCC 0 ND u z ce Cep VDD a GERE Ou GND 7ALCX543 SO GND UM014103 0803 Figure 17 ez80 Development Platform Schematic Diagram 2 of 5 PRELIMINARY 23 0 D 7 0 oa gt A MEM CEN1 MEM CEN2 MEN CENS3 MEM CENA MEM CENT E 2 RD RD RZJ m VDD VDD GND UM014103 0803 MEM CEN 6 OB 0 1uF MEM CEN2 6 A17 NC vono LS AN NC vovi p22 E Pap Gur OE vsso Lost AS7C34096 PRELIMINARY MEM_CEN3 6 EZ 14 VDD
17. host using a unique 48 bit address called its Ethernet address or Media Access Control MAC address MAC addresses are usually represented as six colon separated pairs of hex digits e g 6 0 20 11 ac 85 The first three bytes e g 6 0 20 are the manufacturer s code which can be used to identify the manufacturer The last three bytes are the unique station ID or serial number for the interface This station ID is unique and is associated with a particular Ethernet device The Data Link layer s protocol specific header specifies the MAC address of the packet s source and destination When a packet is sent to all hosts broadcast a special MAC address ff ff ff ff ff ff is used MAC addresses uniquely identify each node in a network at the Media Access Control layer the lowest network layer that directly interfaces with the physical media e g twisted pair wires Troubleshooting PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diipa 59 On a Local Area Network or other network the MAC address is the com puter s unique hardware number On an Ethernet LAN the MAC address is the same as an Ethernet address When it is connected to the Internet a computer or host as the Internet protocol considers it a correspondence table relates the Internet Protocol IP address to the computer s physical MAC address on the LAN IP Address An IP address is a 32 bit number that identifies each sender or receiver of i
18. the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected directly to the eZ80F91 device UM014103 0803 PRELIMINARY Operational Description 17 eZ80190 Development Kit User Manual 18 ies Table 3 eZ80 Development Platform UO Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 19 PD6 Bidirectional 20 GND 21 PD5 Bidirectional Yes 22 PD4 Bidirectional Yes 23 PD3 Bidirectional Yes 24 PD2 Bidirectional Yes 25 PD1 Bidirectional Yes 26 PDO Bidirectional Yes 27 TDO Input Yes 28 TDI ZDA Output Yes 29 GND 30 TRIGOUT Input High 31 TCK ZCL Output Yes 32 TMS Output High Yes 33 RTC_Vpp 34 EZ80CLK Input Yes 35 SCL Bidirectional Yes 36 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected directly to the eZ80F91 device eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit 1 User Manual Table 3 eZ80 Development Platform UO Connector Identification
19. zero wait states CS1_CTL chip select CS1 is set to 08h no wait states Flash Memory The Flash Boot Loader application code and user configuration data are held permanently in Flash memory Internal RAM The eZ80190 MCU features 8 KB of zero wait state internal SRAM This internal RAM can be mapped anywhere in the 16MB address space in the address range E000h FFFFh Reset Generator The onboard Reset Generator Chip is connected to the eZ80190 Reset input pin It performs reliable Power On Reset functions generating a reset pulse with a duration of 200ms if the power supply drops below 2 93 V This reset pulse ensures that the board always starts in a defined condition The RESET pin on the I O connector reflects the status of the RESET line It is a bidirectional pin for resetting external peripheral com ponents or for resetting the eZ80190 Development Kit with a low imped ance output e g a 100 Ohm push button eZ80190 Module PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual AP za Real Time Clock The onboard real time clock can function when the system power supply is down An onboard capacitor GoldCap or external accumulator battery serves as a standby power supply The M41T11 Real Time Clock included on the eZ80190 Module contains Binary Coded Decimal BCD counting registers for Seconds Minutes Hours Day Month Year it also contains a Century bit and 56 bytes of backed up RAM The fu
20. 0 assign nEM WR nDIS EM 1 amp nWR 0 amp nEM EN assign nEM RD nDIS EM 1 amp nRD 0 amp nEM EN assign nAN WR nDIS EM 1 amp nWR 0 amp nEM EN assign nCT WR nDIS EM 1 amp nWR 0 amp nEM EN de assign nDIS ETH nCS endmodule PRELIMINARY amp address latch amp address latch amp address anode amp address catho General Array Logic Equations eZ80190 Development Kit User Manual 81 Diog General Array Logic Equations PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diipa 82 Customer Feedback Form If you note any inaccuracies while reading this User Manual please copy and complete this form then mail or fax it to ZILOG see Return Information below We also welcome your suggestions eZ80190 Development Kit Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Customer Information Name Country Company Phone Address Fax City State Zip E Mail Return Information ZiLOG System Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the prob
21. 0803 eZ80190 Development Kit User Manual List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 UM014103 0803 Tiig eZ809 Development Platform Block Diagram with eZ80190 Module 4 The eZ809 Development Platform 5 The eZ80190 Module 6 Basic eZ809 Development Platform Block Diagram 8 Physical Dimensions of the eZ809 Development Platform 9 eZ80 Development Platform Peripheral Bus Connector Pin Configuration JP1 WW KK RR KK KK KK 11 eZ80 Development Platform I O Connector Pin Configuration JP2 0 0 eee eee eee 16 Trigger Pins J21 and Di 28 Embedded Modem Socket Interface J1 J5 and J9 29 Memory Map of the eZ809 Development Platform and eZ80190 Module KK KK KK KK KK KK KK KK KK KK 32 Physical Dimensions of the eZ80190 Module 45 eZ80190 Module Top Layer esses 46 eZ80190 Module Bottom Layer 47 9VDC Universal Power Supply Components 52 Inserting a New Plug Configuration 53 eZ809 Development Platform Schematic Diagram d B P PP ors liek 3 9 i l i3 a p 3 a 3V3236NW 61 eZ80 Development Platform Schematic Diagram Dama EE Seta kies Crp bode d H 62 eZ80 Development Platform Schematic Diagram HI OLD cc
22. 4 function as status indicators for an optional modem This section describes each LED and the LED matrix device Data Carrier Detect The Data Carrier Detect DCD signal at D1 indicates that a good carrier signal is being received from the remote modem RX The RX signal at D2 indicates that data is received from the modem Data Terminal Ready The Data Terminal Ready DTR signal at D3 informs the modem that the PC is ready TX The TX signal at D4 indicates that data is transmitted to the modem Push Buttons The eZ80 Development Platform provides user controls in the form of push buttons These push buttons serve as input devices to the eZ80 Ethernet Device device The programmer can use them as necessary for application development All push buttons are connected to the general purpose port pins UM014103 0803 PRELIMINARY Operational Description 34 eZ80190 Development Kit User Manual Diog PBO The PBO push button switch SW1 is connected to bit 0 of the general purpose port This switch can be used as the port input if required by the user PB1 The PB1 push button switch SW2 is connected to bit 1 of the general purpose port This switch can be used as the port input if required by the user PB2 The PB2 push button switch SW3 is connected to bit 2 of the general purpose port This switch can be used as the port input if required by the user RESET The Reset push button switch SW4 resets the
23. 49 MATA MA3 ss SGL 6 vec 2x 3 4 D2 ss MATS wo 7 MATS MAF aM v SCL 4 SCH amp 5 e IRR MATS a 14 GND MAS 1345 s 1 GND Eg Sp m Bi Ze UM ZZ VAT MS dB Y 2 mE DIS MOD 1 12 DS CON MATT 19 20 s MAT 17 A8 Y8 MWAIT 13 14 OND MM 21 22 H gsnp DIS IRDA ATOM EARCH MA5 MAT T uan 2 GND Die GND L ES 15 16 DIS ETH 23 24 DIS FL 39 i19E veo GND is GND DIS_ETB MAH 25 gt VDD K DIS_FL 20E GND MA22 MAZ3 Esc 2 A ERER LST 8 2 Me e T4LVC244A HEADER 2 EM_D5 25 26 22PD5 DSRO MDT 33 34 MDZ Hs a EM_D4 27 28 lt PD4_DTRO MDT 35 36 MDE MAB EM_D3 29 30 33PD3 CTSO MDS 37 38 GND WAS A1 vi FLASHWE EM_D2 a1 3 lt PD2_RTSO 39 40 4 A2 Y2 t EM_D1 33 34 22PD1 RXDO emm 41 42 TER ER Bian Y3 J E GND 35 36 GND lt lt PD0_TXDO GND 43 44 mE o e 2 A4 Y4 U21 por RK 37 38 PET MOSI MWR 45 46 INSTRD MATS 15 Y HEADER 2 pis dek 39 40 PBG MISO SBUSACK 4r 45 BUSREQ MATS 15 8 M_CS0 2 23 cso PESTS O 49 50 MATE Ha v NCC A1 Yi PC5_DSRKC PETTA O AB om mes Ha y2 H2 cs PC4_DTR1X PETS Header 25x2 ORG 4 A3 va H CS2 PC3 CTS EK RI Ra ER MEN LR ior SI x ok p2 OK La 10E vcc A Y4 IORQ Leg lt PET TI LR PB7_MOSI PB6 MISO 20E GND WR H Y5 18 MER L RXD TO xis PRS T5 O 1 L PB4 T4 O ARD 8 A e PCO_TXD1 gt PBOTO ypp PES SCK 3 4 Ges vob TALVC2A4 EU A YT RD PELTII 3 5 6 PBU TUT MIR a ya H EBS GND 7 8 PCT RM us 19449 vo H PHI PCEDCDI 9 10 PC5 DSRT Ato Y10 DTR 1 42 PEF CTS ELS TEZE ae aa n ge loei vec itum 99 POH Tt 15 16
24. 59 0603 x ETHIRQ nx cu X 35 Sao t 50 DIS_ETH o device addresses 00300h bis 0030Fh ETHRD SE ENR ETHWR DIS_ETH DIS_ETH cua SD 0 7 SA 0 3 22 2 ETHIRQ mE sees SLEEP ACTIVE ACUE E UM014103 0803 eZ80F91 Development Kit User Manual Z Liat 69 R8 x co ATO 9 CAN Lt ofA 10k Dual LED assembly 1 Naa pene i o l right angle grn grn R9 R10 9 0 C N 5 Oli IN G j Z lt HNN 100 100 3YOvYoY DO aan8aaaag z gozr289osaqdq223 LD1 0603 0603 od As lt DDD tru ul green OZ ZZ ZZ Z T L Q0 __ LANLED LANLED KK SD9 ala A ous LANLED Poo LINKLED upper LED SD8 ul Q LINKLED HCO Pos pp MEMW XTAL2 22 Y1 2 MEMR lt XTAL1 LS 20 000 MHz LINKLED A INTRQ2 ul Avss 2 HC49 lower LED INTRQ1 ul AVDD H22 gt 5682F5 5 INTRQO U7 AVSS 95 R12 LED5682F lOCS16 RES MEMCS16 RXD j 22 S 4k99 1 INTRQ3 RXD j 2 0603 ESD protecti SHBE CS8900A CQ3 AVDD m gt protection array SAO avss F824 ep SA1 TxD L SA2 TQFP100 TXD 56 SA3 Avss SA4 AVDD L t SA5 DO 2 SA6 DO LZ SA7 CL L SA8 c LS SA9 Dr SA10 Dis H2 SA11 BSTATUS HC1 D SEED REFRESH gt SLEEP int Pull Up LCDA15C 6 SA12 D TEST p8 SO8 150 Ec I GND GND o go o 89 rge T a u GEET TXD TD CASE o00086585800099 90o0o0oob8o00oot lt l dd Led ol d Nd lt Ra99
25. 92999992 SER c4 100nF ETHRD ETHWR 0603 HFJ11 1041 E A E E S E E 2 RXDE HALOFASTJACK cs x ce 100nF SDJ 0 7 0603 100nF TX lt gt 1 through hole m en geo e ud S ji oe lt gt vaa Solder pad SP plane or place near RX lt gt 6 do not big trace VDD vss LANLED U GND do not stuff Figure 24 eZ80190 Module Schematic Diagram 4 of 8 Ethernet Module PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual Ap tiie _ CAL SD 0 7 ns SA O 3 D o 7G 2L Am 23 A2 RD mei WR QE OEAB LEAB CEAB OEBA LEBA CSETH LEBA 74LCX543 TSSOP24 ETHRD ETHRD CS3 CS3 CSETH CLK_OUT CLK OUT Ss ETHWR CSETH P 41 LE o oE 74LCX573 TSSOP20 U5B U6C 74LCX32 TSSOP14 CSETH P USC TALCXOA TSSOP14 2 CLK_OUT 3 oy ETHWR CSETH CSETH2D 10 TALCX32 TSSOP14 CL ol 74LCX74 V3 3 TSSOP14 T4LCX74 TSSOP14 VDD V3 3 V3 3 VSS EE GND Figure 25 eZ80190 Module Schematic Diagram 5 of 8 Ethernet Module Logic UM014103 0803 PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual ziana 71 power supervisor V3 3 C7 100nF 0603 R18 2k2 0603 b RESET RESET RESET open drain C8 MAX6328UR29 10nF SOT 2343 0603 alternative Maxim MAX6802UR29D3 real time clock Go
26. CU features 8KB of internal SRAM in the address range E000h FFFFh and 1KB of MACC RAM in the address range DC00h UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 32 Diog DFFFh Internal RAM can be mapped anywhere in the 16MB address space in 64KB steps DC00h FFFFh to DCOOh FFFFFFh The software included in the eZ80190 Development Kit assumes internal RAM in the range E000h FFFFh for the interrupt vector table This range overlaps the address range assigned to Flash memory CS0 on the eZ80190 Module Note The Ethernet controller located on the eZ80190 Module is mapped as an T O device at address 300h It uses CS3 FFFFFFh DFFFFFh SRAM Memory up to 2 MB CS1 C7FFFFh Ethernet Module C00000h SRAM BFFFFFh ww Board B80000h SRAM 512 KB Expansion SRAM Memory up to 1 5 MB CS2 80FFFFh 800000h 7FFFFFh Expansion Module Flash Memory up to 4 MB 400000h 3FFFFFh CS0 8 MB Flash Memory Up to 4 MB 000000h Ethernet Module OFFFFFh ke MB on Figure 10 Memory Map of the eZ80 Development Platform and eZ80190 Module eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diga 33 The LED matrix and the general purpose port circuitry are mapped in the address range 800000h 80ffffh The CS2 chip select should be driven Low to select the LED matrix or general purpose port LEDs As stated earlier LEDs D1 D2 D3 and D
27. Customer Support For additional troubleshooting solutions see ZDS Online Help For valuable information about hardware and software development tools visit ZILOG Customer Support online Download the latest released ver sion of ZiLOG Developer Studio Get the latest software updates from ZiLOG as soon as they are available Troubleshooting PRELIMINARY UM014103 0803 eZ80F91 Development Kit User Manual Schematic Diagrams eZ80 Development Platform Figures 16 through 20 present the schematics of the eZ809 Development Platform DO NOT USE J6 17 AND J6 35 MAG 1 2 MAO ut u2 MA H A MAS GND VDD MAO 2 4 5 SDA B MAS 5 6 MAT MAT rae YI GND i 0 SDA vcc MATS T a MAS MAZ e v2 VDD evpc gt gt 2V P 1 2 MATS 9
28. ILOG s new eZ80 product family The module also con tains a battery and an oscillator in support of the onboard Real Time Clock RTC The eZ80190 Module can also be used as a stand alone development tool when provided with an external power source Physical Dimensions The footprint of the eZ80190 Module PCB is 63 5 mmx 78 7 mm With an RJ 45 Ethernet connector the overall height is 25 mm See Figure 11 eZ80190 Module PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Zi Tiig O gt J 5 O U7 IRH E DON Ooo eo EE te n 25539 rna HI 78 7 mm me ef S opo 0 IW sts Ul oo ITT PCA 99C0877 001 IR ca gg U12 o o dn 28 Y2 BIS en oo Figure 11 Physical Dimensions of the eZ80190 Module eZ80190 ETHERNET MODULE COPYRIGHT ZiLOG XTOOLS 2002 UM014103 0803 PRELIMINARY Functional Description eZ80190 Development Kit User Manual K 46 Diog Figure 12 illustrates the top layer silkscreen of the eZ80190 Module MADE IN U S A S Bg O o U7 HIHHH c27B Ji R12 Ba mmm REEE 2 c2200 2 R16 QN n 7 l DI CH ARE Tum E sg IN Im WU Gore U1 Dis R500 IHH U4 PCA 99C0877 001 eZ80190 ETHERNET MODULE COPYRIGHT ZiLOG XTOOLS 2002 000000000000 RN1 Figure 12 eZ80190 Module Top Layer eZ80190 Module PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diipa 47 Figure 13 illustrates the bottom layer silkscreen of
29. JP2 Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 37 SDA Bidirectional Yes 38 GND 39 FlashWE Output Low No 40 GND 41 CS3 Input Low Yes 42 DIS IrDA Output Low No 43 RESET Bidirectional Low Yes 44 WAIT Output Pull Up 10KO Low Yes 45 Vpp 46 GND 47 HALT SLP Input Low Yes 48 NMI Output Low Yes 49 Vpp 50 Reserved Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 The Power and Ground nets are connected directly to the eZ80F91 device Almost all of the connectors signals are received directly from the CPU Four input signals in particular offer options to the application developer by disabling certain functions of the eZ80190 Module These four inputs are UM014103 0803 PRELIMINARY Operational Description 20 eZ80190 Development Kit User Manual Tio Disable Ethernet DIS ETH Disable Flash DIS FL Flash Write Enable FlashWE Disable IrDA DIS IIDA not used These four signals are described below Disable Ethernet When active Low the DIS ETH output signal disables the EMAC from responding to CPU requests As a result additional input output or mem ory devices can be used in the CS3 address space The logic that disables the Ethernet signal is listed in Appendix A on page 74 Disable Flash When active Lo
30. Module However this functionality is available in other eZ809 devices Jumper J15 The J15 jumper connection controls the selection RS485 circuit along with UARTO When the shunt is placed the RS485 circuit is enabled See Table 18 RS485 functionality will be available in future eZ80 devices Table 18 J15 RS485 1 EN Shunt Status Function Affected Device In The RS485 circuit is enabled on UARTO IrDA UARTO CONSOLE The UARTO CONSOLE interface and IrDA are interface RS485 interface disabled Out The RS485 circuit is disabled on UARTO IrDA UARTO CONSOLE interface RS485 interface Note To enable the RS485 circuit the corresponding IrDA RS232 circuit must be disabled UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 38 Diog Jumper J16 The J16 jumper connection controls the selection of the RS485 circuit However UART1 MODEM interface and the socket modem interface are disabled if the RS485 circuit is enabled When the shunt is placed the RS485 circuit is enabled See Table 19 Table 19 J16 RS485_2_EN Shunt Status Function Affected Device In The RS485 circuit is enabled on UART1 The UART1 MODEM interface UART1 MODEM interface and the Socket Socket Modem Interface and Modem interface are disabled RS485 interface Out The RS485 circuit is disabled on UART1 UART1 MODEM interface Socket Modem Interface and RS485 interface Jumper J17 The J17 jumper connecti
31. No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights UM014103 0803 PRELIMINARY eZ80190 Development Kit User Manual K zung HI Safeguards The following precautions must be observed when working with the devices described in this document Z N Caution Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD UM014103 0803 PRELIMINARY Safeguards eZ80190 Development Kit User Manual IV Tika UM014103 0803 Table of Contents Safeguards List of Figures List of Tables Introduction Kit Features Hardware Specifications eZ80 Development Platform Overview eZ809 Development Platform Functional Description Physical Dimensions Operational Description eZ80190 Module Interface Application Module Interface UM014103 0803 I O Functionality Embedded Modem Socket Interface eZ80 Development Platform Memory JUMP OTS 4n oves trece emere Connectors Console JAVA KK KK KK KK Modem PC Devices DC Characteristics eZ80190 Module Functional Description Physical Dimensions Operational Description PRELIMINARY eZ80190 Development Kit User Manual Table of Contents eZ80190 Development Kit User Manual VI Iii Ethernet Media Access Controller 48 eZ80190 Module Memory 50 Reset Generator 50 Real Time Clock onted debt s23 ine Ge GER ia Re 51 YC Bus Software Emulation e 51 DC Characteristi
32. O VDD1 VSS0 VSS1 AS7C34096 Figure 18 eZ80 Development Platform Schematic Diagram 3 of 5 eZ80F91 Development Kit User Manual iw 63 MEM_CEN4 6 oi VRD vooo L ch Ach 22 oco Op vsso A9 DND ves E28 T eZ80F91 Development Kit User Manual 64 E iL GND 9VDC Y ovpc U23 LMZBOSC TO220 0 5A U22 D o 4 tin our 5V VCC gt gt vcc 21 RXE160 m 8 v J10 2 L c1 v HEADER 5 J13 D6 E 0 1 Cav C16 C17 A CH SS O1F 0 1uF VES S26 T bj RESET C 1 c22 PDO T0 elt Trout H Per PWRJACK NE S 9 O 22 RESET GND 13 ra T20UT LAD d ae U25 1 __RTS0_ PD2 RTSQ K T3OUT RTSO 22 a 2 3 av vo ms CON gt FORCEOFF E 4 VIN vour D vob Vbi _ _ S 4 GND RAA 23 FORCEON INVALID j 21 10K 20 R20UTB LT1086 3 3 TO220 Dues R15 12 pour Sun LA 18 amp esou Rain 3 SND C29 PD3 CTS0 17 RsoUT
33. PD7 RIO MATS 8 2 v2 OE2 GND POS DCDO 17 18 GND MATS g AS M C34 VDD GND PD5_DSRO 19 29 PD TR MAZOT 11 5 va 74LVC827 SO 0 1uF Po cto 21 22 PDZ RTSU MT gje Ys PDI RDO 23 24 PDO_TXDO MA22 15 Ye TDO 25 26 TDI MAST TAT YN GND 27 28 TRIGOUT a Ye GND 9 W GND TCK 29 20 TMS mE AS 3 12 AS VDD RTC VDD M g MPH GND tan 10E vcc ATO Se de ATi SCL 2 x GND 20E GND vcc d A12 A13 SDA GE e A15 R3 FLASRWE 37 38 74LVC244A VDD d GND s 3 GND 10K M CS3 As DIS IRDA 3 23 24 ate Ei 43 44 MWAIT Header 3 A18 A19 VDD GND A20 25 28 AZ HALT SLP ed NMT nZ 2 x AB o VD 3 31 3 RO meer S 3 Ee Header 25x2 Eid u7 35 36 INSTRD van MDO BUSACK 22 37 38 PH BUSREQ YEP aw HEADER2 MDT 2 Jao NMI GND 39 40 GND PHI MDZ Ha i is E Hs D4 LO D5 MD5 TM D6 4 M D7 ZDI MD6 81 8 ND 51 52 B INTERFACE cd 9 a7 e ZS 56 8 EX FS MRD qe DIR vec He MEMRO pp 58 GNDK amp IORQ GND TDI LRH RJ 0E GND Di Header 30x2 Header 3x2 74LVC248 80 ip 0 1uF VDD gt gt MD 7 0 VDD CTT MDO E vcc MDZ U9A ok vec 3 7 HIK reser p1 pm GND 3 is GND K L2 i 1 4 2 VDD TC74LVCOB RE UA J A Z 2 GND P1 GND TDI TR in TDO 1 2 4 A 2 TC74LVT125 TCK 3 T GND c 5 6 Tx A8 TVCC_RESETn E a TMS 1 2 HEADER9 HEADER 32 VDD 1 12 PRSTn MODEM CONNECTORS E TRIGOUT con 7x2 Figure 16 ez80 Development Platform Schematic Diagram 1 of 5 UM014103 0803 PRELIMINARY
34. RELIMINARY Changing the Power Supply Plug 54 eZ80190 Development Kit User Manual Likog ZPAKII ZPAKII is a debug tool used to develop and debug hardware and soft ware It is a networked device featuring an Ethernet interface and an RS232 console port ZPAKII is shipped with a preconfigured IP address that can be changed to suit the user on a local network For more informa tion about using and configuring ZPAK II please refer to the ZPAKII Debug Interface Tool Product User Guide PUGO0015 and the eZ80190 Development Kit Quick Start Guide QS0004 ZDI Target Interface Module JTAG The ZDI Target Interface Module provides a physical interface between ZPAKII and the eZ80 Development Platform The TIM module supports ZDI functions For more information on using the TIM module or ZDI please refer to the eZ80190 Development Kit Quick Start Guide QS0004 and the eZ80190 Module Product Specification PS0191 Connector P1 is the JTAG connector on the eZ80 Development Plat form JTAG will be supported in the next offering of eZ80 products Application Modules ZPAKII ZiLOG offers the Thermostat Application module which can be used for evaluating and developing process control and simple I O applications The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters For additional reading about the Thermostat application please see the Java
35. Z80190 Flash boot sector of the eZ80190 Module is enabled for writing or Module overwriting UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 36 Diog Jumper J11 The J11 jumper connection controls access to the Flash memory device When the shunt is removed access to the Flash device is disabled pre vented See Table 15 Table 15 J11 DIS FL Shunt Status Function Affected Device OUT All access to Flash on the eZ80190 Flash on eZ80190 Module Module is disabled IN Flash on the eZ80190 Module is Flash on eZ80190 Module enabled Jumper J12 The J12 jumper connection controls the selection of a 5 V or 3 VDC power supply to the embedded modem if an embedded modem is used See Table 16 Table 16 J12 5VDC 3 3VDC for an Embedded Modem Shunt Status Function Affected Device 1 2 5VDC is provided to power the embedded modem Embedded modem 2 3 3 3VDC is provided to power the embedded modem Embedded modem eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Ar Diga Jumper J14 The J14 jumper connection controls the polarity of the Ring Indicator See Table 17 Table 17 J14 RI Shunt Status Function Affected Device 1 2 The Ring Indicator for UART1 is inverted UART1 2 3 The Ring Indicator for UART1 is not inverted UART1 For jumpers J15 J18 RS485 functionality is not available on the eZ80190
36. ads on RD WR IORQ MREQ DO D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 14 z Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued eZ801900100ZCO Pin Symbol Signal Direction Active Level Signal 31 CS0 Input Low Yes 32 CS1 Input Low Yes 33 CS2 Input Low Yes 34 DO Bidirectional Yes 35 D1 Bidirectional Yes 36 D2 Bidirectional No 37 D3 Bidirectional Yes 38 D4 Bidirectional Yes 39 D5 Bidirectional Yes 40 GND 41 D7 Bidirectional Yes 42 D6 Bidirectional Yes 43 MREQ Bidirectional Low Yes 44 IORQ Bidirectional Low Yes 45 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected directly to the e2801900100ZCO device Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisf
37. ake of simplicity Table 4 GPIO Port Connector J6 Signal Pin Function Direction Notes SCL 5 12C Clock Bidirectional SDA 7 PC Data Bidirectional MOD DIS 9 Modem Disable Input If a shunt is installed between pins 6 and 9 the modem function on the eZ80 Development Platform is disabled MWAIT 13 WAIT signal for Input This signal does not perform a the CPU function on the eZ80190 Module EM DO 15 GPIO Bit 0 Bidirectional CS3 17 Chip Select 3 of Output This signal is also present on the CPU the J8 EM D 7 1 21 23 25 Port A Bit 7 1 Bidirectional 27 29 31 33 Note All of the signals are driven directly by the CPU UM014103 0803 PRELIMINARY Operational Description 22 eZ80190 Development Kit User Manual Iii Table 4 GPIO Port Connector J6 Continued Signal Pin Function Direction Notes Reserved 35 PC 7 0 39 41 43 Port C Bit 7 0 Bidirectional 45 47 49 51 53 ID_ 2 0 6 8 10 eZ80 Output Development Platform ID CON_DIS 12 Console Disable Input If a shunt is installed between pins 12 and 14 the Console function on the eZ80 Development Platform is disabled Reserved 16 18 PD 7 0 22 24 26 Port D Bit 7 0 Bidirectional 28 30 32 34 36 PB 7 0 40 42 44 Port B Bit 7 0 Bidirectional 46 48 50 52 54 Note All of the signals are driven directly by the CPU eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit
38. an estimate of the average current requirement when different combinations of these application modules are plugged in to the eZ80 Development Platform The measurements of current that are shown in Table 25 are for the user s reference These values can vary depending on the type of application that is developed to run with the platform Table 25 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads Current Platform Modules Configurations Requirement mA Status eZ80 Development Platform and 173 When connected only to a eZ80190 Module power supply and when no program is running eZ80 Development Platform eZ80190 174 Module and Modem Module When connected only to a power supply and when no program is running eZ809 Development Platform e280190 195 Module and Thermostat Application Module When connected only to a power supply and when no program is running eZ80 Development Platform e280190 203 Module Modem Module and Thermostat Application Module When connected only to a power supply and when no program is running ez80 Development Platform and 325 eZ80190 Module When the LED demo is running eZ80 Development Platform eZ80190 325 Module and Modem Module When the LED demo is running eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Zi Tiig Table 25 DC Current Charac
39. and J9 Table 10 Connector J5 Pin Symbol Description 1 M TIP Telephone Line Interface TIP 2 M RING Telephone Line Interface RING Table 11 Connector J9 Pin Symbol Description 1 MRESET Reset active Low 50 100 ms Closure to GND for reset 3 GND Ground UM014103 0803 PRELIMINARY Operational Description 29 30 eZ80190 Development Kit User Manual Diog Table 11 Connector J9 6 D1 DCD indicator can drive an LED anode without additional circuitry 7 D2 RxD indicator can drive an LED anode without additional circuitry 8 D3 DTR indicator can drive an LED anode without additional circuitry 9 D4 TxD indicator can drive an LED anode without additional circuitry Table 12 Connector J1 Pin Symbol Description 2 MOD_DIS Modem disable active Low 4 Vcc 5 VDC or 3 3 VDC input 24 GND Ground 25 PC4_DTR1 DTR interface TTL levels 26 PC6 DCD1 DCD interface TTL levels 27 PC3_CTS1 CTS interface TTL levels 28 PC5 DSR1 DSR interface TTL levels 29 PC7 RI Ring Indicator interface TTL levels 30 PCO TXD1 TxD interface TTL levels 31 PC1 RXD1 RxD interface TTL levels 32 PC2_RTS1 RTS interface TTL levels Components P4 T1 C3 C4 and U11 provide the phone line interface to the modem On the eZ80 Development Platform LEDs D1 D2 D3 and D4 function as status indicators for this optional modem The phone line connection for the modem is for the
40. cs Luca eeu HED SE e raria ec 51 Flash Loader Vtility pepersensssscrssvrkkesanpi kiy a nEaN 52 Mounting the Module 52 Changing the Power Supply Plug 52 EE wa RE ade a ka a ela e he O E 54 ZDI Target Interface Module 0 0 KK KK KK KK KK KK KK 54 ME EE 54 Application Module 54 ZPAK L g i ss siha n k nr o rea em an dee We Ro obe ay dk 55 MES EE 56 ZDS T sy IRI tha ME K k MEDS ee K a dee ES 56 Troubleshooting i bee eee pee b ex 57 OVerVieW ceder La RES Ohne dia chased aise ake 57 Cannot Download Code AWK KK KK RR KK KK KK KK KK KK KK 57 No Output on Console Po 57 IrDA Port Not Working I 58 Difference Between EMAC and IP Address 58 Media Access Control MAC 58 IP AddEesS os set e e ce dee EACH RU ee 59 Contacting ZiLOG Customer Support 60 Schematic Diagrams 0 0 cece KK KK KK KK KK KK KK KK kk kk k 61 eZ809 Development Platform 0 000002 eee eee 61 eZ80190 Module 66 Appendix A si x w ka s weise l k k n bi DESEE l ken ee ERE e 74 General Array Logic Equations W K KK KK KK KK KK KK 74 U10 Address Decoder a kk kK KK RR KK KK KK KI KK KK KK KK 74 Table of Contents PRELIMINARY UM014103 0803 UM014103 0803 U15 Address Decoder Customer Feedback Form PRELIMINARY eZ80190 Development Kit User Manual zung VI Table of Contents eZ80190 Development Kit User Manual vill Lika Table of Contents PRELIMINARY UM014103
41. e UM014103 0803 PRELIMINARY eZ80190 Module Figures 21 through 28 present the schematics of the eZ80190 Module x1 eZ80F91 Development Kit User Manual Z z Lb 66 R13 ETHIRQ e EIS PD4 PA 0 7 XIN 3 Sy orti D DS m 0603 SLEEP SLEEP 1 PD 50 000MHz 3 3V OR R14 SG 710 0603 ACTIVE PD6 ACTIVE B SI IN PAD 7 0603 don stuff TIFE BEE E PCI 7 212528 WR 0009 75 WR 50292 TEST PC7 RD 9552 pcriR Ce PB RD aa 3 PE See PP d CSIDSR1 H pos A E o S csp a RES BCAIDTRI 11 po3 e Ea pep swvcrs 3 pc2 7 PDL CS0 gt FLASH PCZISCKA RTS4 a 44 DUU 7 PD O 7 CS1 RAM U1 PC1 SDA1 MOSM RxD1 poo A CS2 gt ext 10 PCOISCL1 MISO1 TxD1 ar C93 7 ETH VDD e Ppg7 ZDA 5 za D Cea eZ80190 zeL___ za A 0 23 A 0 23 eo PBS N TOPi E E 551 N BUSREQ G ZDA N BUSREQ er BUSACK _ BUSACK E RESET PB 9 Z MREQ MREQ JNSTRD CLK OUT RESET RESET CLK OUT IOREQ P ki JNSTRD S INSTRD gt DAT e HALT pu L 1k 0603 R30 NMI don t on NMI stuff 0603 Wenn IICSDA PAZ A OR R32 l li wert 0603 PAG C18 c19 c20 place caps close IICSCL 1nF 1nF 1nF to pins 97 8 38 48 OR R33 0603 0603 0603 0603 L UM014103 0803 Figure 21 eZ80190 Module Schematic Diagram 1 of 8 CPU PRELIMINARY Schematic Diagrams eZ80F91 Developme
42. e ba hn 4 bA Wa ie piso tate ed boas 63 eZ80 Development Platform Schematic Diagram HA OLD in band aay hae u9 k n pauper teo gee eek 64 PRELIMINARY List of Figures eZ80190 Development Kit User Manual Diog Figure 20 eZ809 Development Platform Schematic Diagram 5 of 5 RS 485 Cable SK KK RR KK KK KK KK 65 Figure 21 eZ80190 Module Schematic Diagram 1 of 8 CPU 66 Figure 22 eZ80190 Module Schematic Diagram 2 of 8 36 Pin SRAM Device 0 0 ce KK KK eee eee 67 Figure 23 eZ80190 Module Schematic Diagram 3 of 8 NOR Flash Device si s h a ke E RE a av Ka a 68 Figure 24 eZ80190 Module Schematic Diagram 4 of 8 Ethernet Module KK KK KK KK KK KK KK KK KK eee 69 Figure 25 eZ80190 Module Schematic Diagram 5 of 8 Ethernet Module Logic KK KK KK KK KK 0005 70 Figure 26 eZ80190 Module Schematic Diagram 6 of 8 Ethernet Module Peripherals KK 71 Figure 27 eZ80190 Module Schematic Diagram 7 of 8 Headers 72 Figure 28 eZ80190 Module Schematic Diagram 8 of 8 Power Supp 73 List of Figures PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual K List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 UM014103 0803
43. elopment Kit User Manual fii R 73 common power plane no power supply on board Input VDD V3 3 3 3V 5 Power Pmax tbd common ground plane Ptyp tbd Current Imax tbd Ityp thd PCB1 eZ80190 ethernet module board 98CXXXX XXX U6D 7ALCXO4 TALCX32 TSSOP14 TSSOP 14 U6E unused gates TALCXOA TSSOP14 U6F i TALCXOA TSSOP14 Figure 28 eZ80190 Module Schematic Diagram 8 of 8 Power Supply UM014103 0803 PRELIMINARY Schematic Diagrams eZ80190 Development Kit User Manual ZInp 74 Appendix A General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro vided by the U10 and U15 General Array Logic GAL devices U10 Address Decoder FE define idle 2 b00 define statel 2 5b01 define state2 2 b11 define state3 2 b10 FOR ez809 Development Platform Rev B This PAL generates 4 memory chip selects module 192 decod UM014103 0803 nCS_EX Enables Extension Module s Memory when Low nFL DIS when Low WEB Module Flash is disabled nDIS_FL 0 when High nDIS FL depends upon state of nmemenXx ncso A7 A23 A6 A22 A5 A21 A4 A20 A3 A19 A2 A18 Al A17 AO A16 PRELIMINARY General Array Logic Equations 75 eZ80190 Development Kit User Manual K ZInpe nCS2 when LOW nEX_FL_DIS disables Flash on the expansion module
44. green LEDs a Link LED and a LAN LED that are located adjacent to each other on the eZ80190 Module A steady LAN LED top indicates received link pulses from the Ethernet A flashing Link LED bottom indicates Traffic RX or TX on the LAN Ethernet Connector The eZ80190 Module is equipped with an RJ 45 connector that features integrated magnetics transformer common mode chokes The remain ing pins on the onboard RJ 45 connector are not connected An RJ 45 loopback connector can be used to verify the correct operation of the Receiver and the Transmitter Pin assignments for the RJ 45 Ether net connector are shown in Table 26 Table 26 Ethernet Connector Pin Assignments Pin Function TX TX RX RX 9 c N gt eZ80190 Module PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Tiig 49 To connect the eZ80190 Module directly to another host e g to a per sonal computer a crossover cable must be used The EMAC can be additionally protected by placing an ESD protection array on the module at U8 This array can be either of the LCDA15C 6 Semtech or ESDA25B1 ST Microelectronics devices GPIO Pins for Enabling LAN Activity Sleep Interrupt GPIO input bit PD4 serves as an active High interrupt input for the EMAC s INTRQO output GPIO output bit PD7 can be used to place the EMAC into SLEEP mode When pulling SLEEP PD7 Low after enabling HWStandbyE and HWSleepE modes the chip dra
45. ion of the port See Table 8 Table 8 General Purpose Port Data Register Bit Function 7 6 5 4 3 2 1 0 GPIO DO GPIO D1 X GPIO D2 X GPIO D3 X GPIO D4 X GPIO D5 X GPIO D6 X GPIO D7 X Z N Caution Reading from the general purpose port can damage the drivers used for the general purpose port and memory The port can however be used for writing data UMO014103 0803 PRELIMINARY Operational Description 26 eZ80190 Development Kit User Manual Diog LED Matrix The one 7x5 LED matrix device on the eZ80 Development Platform is a memory mapped device that can be used to display information such as programmed alphanumeric characters For example the LED display sample program that is shipped with this kit displays the alphanumeric message eZ80 To illuminate any LED in the matrix its respective anode bit must be set to 1 and its corresponding cathode bit must be set to 0 Bits 0 6 in Table 7 are LED anode bits They must be set High 1 and their corresponding cathode bits bits 0 4 in Table 9 must be set Low 0 to illuminate each of the LED s respectively Bit 7 in Table 7 does not carry any significance within the LED matrix It is used for the general purpose port as a control bit Table 9 indicates the multiple register functions of the LED cathode modem and triggers This table shows the bit configuration for each cath ode bit Bits 5 6 and 7 do not carry any significance w
46. ithin the LED matrix These three bits are control bits for the modem reset Trig and Trig2 functions respectively Table 9 Bit Access to the LED Cathode Modem and Triggers Bit 4 Function 7 6 5 4 3 2 1 0 Cathode Row 5 Cathode Row 4 X Cathode Row 3 X Cathode Row 2 X eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual 27 Table 9 Bit Access to the LED Cathode Modem and Triggers Continued Bit Function 7 6 5 4 3 2 1 0 Cathode Row 1 X MRESET X Trig 1 X Trig 2 X An LED display sample program is shipped with the eZ80190 Develop ment Kit Please refer to the eZ80190 Development Kit Quick Start Guide QS0004 or to the Tutorial section in the ZiLOG Developer Studio II eZ80 User Manual UM0123 Modem Reset The Modem Reset signal MRESET is used to reset an optional socket modem This signal is controlled by bit 5 in the register shown in Table 9 The MRESET signal is available at the embedded modem socket interface J9 Pin 1 Setting this bit Low places the optional socket modem into a reset state The user must pull this bit High again to enable the socket modem Reference the appropriate documentation for the socket modem to reset timing requirements More information about this signal is provided in the next section User Triggers Two general purpose trigger output pins are provided on the eZ80 Development Platf
47. ld Cap C9 R19 0 1F v33 GOLDCAP SD V a 10 SP dG RTC _VDD 100nF TMM BAT 41 0603 MNMELF AK R20 Co RIC VDD OR 0603 Y2 0S CO S T OUT V3 3 32 B8kH L M 41T11M 6 R23 XTAL3 SO 8 150 ICSCL Tasch VDD lk seid 12C bus address vss p DO u D1 x 0603 GND Figure 26 eZ80190 Module Schematic Diagram 6 of 8 Ethernet Module Peripherals UM014103 0803 PRELIMINARY Schematic Diagrams A 0 23 QLL D O 7 DIO 7 connector 1 eZ80F91 Development Kit connector 2 R24 EZ80CLK 33 0603 place near eZ80 output PHI ZCL RTC_VDD IICSCL IICSDA FLASHWE CS3 RESET BUSREQ Header 30x2 peripheral bus R26 2o connector 0603 R29 10k 0603 NOTUSED1 R27 10k 0603 10k 0603 WIT e a B ESI reson QE ucscL B CLK OUT CLK OUT DS FLASH ZDIS FLASH FLASHWE TLASHWE Rre vbp CC BIG OD vom a ERR Pcpo 7 QAL PD o 7 e ER PA 0 7 ERR DIS_ETH UIS_ETH RESET RESET Ro wr WR D Joco OREQ E WMREQ MREQ UE INSTRD INSTRD 9 HALT By ALT aa EE BUSACK B uwen DN ZDA ZDA Ser 8 ZCL V3 3 V3 3 EXT GND EXT GND UM014103 0803 Figure 27 eZ80190 Module Schematic Diagram 7 of 8 Headers PRELIMINARY Header 30x2 IO connector User Manual Z fii 72 EZ80CLK NOTUSED1 NC Pin 50 open to be keyed Schematic Diagrams eZ80F91 Dev
48. lem Attach additional pages as necessary UM014103 0803 PRELIMINARY Customer Feedback Form
49. llows the user to program application code into Flash memory Please refer to the External Flash Loader Product User Guide PUG0012 for more details Mounting the Module When mounting the eZ80190 Module onto the eZ80 Development Plat form check its orientation to the platform to ensure a correct fit Pin 11 of JP1 on the eZ80190 Module must align with pin 1 of JP1 on the eZ809 Development Platform Pin 11 of JP2 on the eZ80190 Module must align with pin 1 of JP2 on the eZ80 Development Platform etc Changing the Power Supply Plug The universal 9VDC power supply offers three different plug configura tions and a tool that aids in removing one plug configuration to insert another as shown in Figure 14 Figure 14 9VDC Universal Power Supply Components eZ80190 Module PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Diipa 53 To exchange one plug configuration for another perform the following steps 1 Place the tip of the removal tool into the round hole at the top of the current plug configuration 2 Press down to disengage the keeper tab and push the plug configura tion out of its slot 3 Select the plug configuration appropriate for your location and insert UM014103 0803 it into the slot formerly occupied by the previous plug configuration Push the new plug configuration down until it snaps into place as indicated in Figure 15 Figure 15 Inserting a New Plug Configuration P
50. lly charged 0 1 F GoldCap bridges power outages with a maximum of 4 hours The GoldCap in contrast to a battery or an accumulator offers an advantage in that service replacement is not necessary The C address of the RTC is DOh for Writes and D1h for Reads Details about the internal registers of the M41T11 Real Time clock can be found on the ST Microelectronics website www st com IC Bus Software Emulation The eZ80190 device contains two powerful master slave mode DC bus controllers The DC data SDA and clock SCL pins on PD1 PDO and PC1 PCO GPIO are multiplexed with the UART and SPI functions To use DC bus operation in parallel with console and modem I O the module IICSCL IICSDA pins on connector JP2 can be linked to PA7 IICSDA and PA6 IICSCL of the eZ80190 device In this case an C master mode software emulation is necessary to access C devices Using PA7 PA6 or PCI PCO for IICSDA IICSCL is resistor selectable on the eZ80190 Module DC Characteristics As different combinations of application modules are loaded onto the eZ80 Development Platform current requirements change Please see Table 25 on page 42 to reference current consumption values for these different modules UM014103 0803 PRELIMINARY Real Time Clock eZ80190 Development Kit User Manual 52 Diog Flash Loader Utility The Flash Loader utility resides in the boot sector of Flash memory located on the eZ80190 Module The Flash Loader utility a
51. ly to the e2801900100ZCO device Additional note external capacitive loads on RD WR IORQ MREQ DO D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Tiig Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued eZ801900100ZCO Pin Symbol Signal Direction Active Level Signal 16 GND 17 A2 Bidirectional Yes 18 A1 Bidirectional Yes 19 A11 Bidirectional Yes 20 A12 Bidirectional Yes 21 A4 Bidirectional Yes 22 A20 Bidirectional Yes 23 A5 Bidirectional Yes 24 A17 Bidirectional Yes 25 DIS_ETH Output Low No 26 DIS_FLASH Output Low No 27 A21 Bidirectional Yes 28 Vpp 29 A22 Bidirectional Yes 30 A23 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected directly to the e2801900100ZCO device Additional note external capacitive lo
52. memory and other control signals eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual AZ Af ZInp Console Connector P2 is the RS232 terminal which can be used for observing the console output P2 can be connected to a PC running a HyperTerminal program if required Modem Connector P3 provides a terminal for connecting an external modem if used with the eZ80190 Development Kit IC Devices The two UC devices on the eZ80 Development Platform are the U2 EEPROM and the U13 Configuration register The EEPROM provides 16KB of memory The Configuration register provides access to control the configuration of an application specific function at the Application Module Interface Neither device is utilized by the eZ80190 Development Kit software The user is free to develop proprietary software for these two devices The addresses for accessing these devices are listed in Table 24 Table 24 EC Addresses Device Bit 7 6 5 4 3 2 1 0 EEPROM U10 1 0 1 0 0 Ai A0 RW Configuration Register U13 1 0 0 1 1 1 0 RW Note EEPROM address bits AO and A1 are configured for Os DC Characteristics Understanding proper DC current requirements for the eZ80 Develop ment Platform when application modules are plugged into it is very UM014103 0803 PRELIMINARY I2C Devices 42 eZ80190 Development Kit User Manual Diog important for developing applications This section provides
53. n receptacles JP1 and JP2 which are described in the next pages Peripheral Bus Connector JP1 Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the 50 pin header located at position JP1 on the eZ80 Development Plat form Table 2 describes the pins and their functions eZ80 Development Platform PRELIMINARY UM014103 0803 GND EXT DIS ETH HEADER 25X2 IDC50 eZ80190 Development Kit User Manual AP ZIR 2 INS TRD BUSREQ Figure 6 eZ80 Development Platform Peripheral Bus Connector Pin Configuration JP1 UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 12 Ces Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 eZ801900100ZCO Pin Symbol Signal Direction Active Level Signal 1 A6 Bidirectional Yes 2 AO Bidirectional Yes 3 A10 Bidirectional Yes 4 A3 Bidirectional Yes 5 GND 6 Vpp 7 A8 Bidirectional Yes 8 AT Bidirectional Yes 9 A13 Bidirectional Yes 10 A9 Bidirectional Yes 11 A15 Bidirectional Yes 12 A14 Bidirectional Yes 13 A18 Bidirectional Yes 14 A16 Bidirectional Yes 15 A19 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected direct
54. nformation that is sent in packets across the Internet An IP address contains two parts the identifier of a particular network on the Internet and an identifier of the particular device which can be a server or a workstation within that network On the Internet itself that is between the router that moves packets from one point to another along the route only the network part of the address is examined Relationship of the IP Address to the Physical Address The machine or physical address used within an organization s local area networks can be different than the IP address coming from the Internet The most typical example is the 48 bit Ethernet address TCP IP includes the Address Resolution Protocol ARP that lets the administrator create a table that maps IP addresses to physical addresses The Ethernet MAC address of the ZPAKII When connecting the ZPAKII serial port to a PC running HyperTerminal hold the space bar and reset the ZPAKII When HyperTerminal prompts with eZ80 gt enter e to display the MAC address UM014103 0803 PRELIMINARY Difference Between EMAC and IP Address eZ80190 Development Kit User Manual 60 Tio Resolving IP Address Subnet Mask Conflicts For running demos properly the ZPAKII IP address and subnet mask must be properly configured Please follow the instructions provided in the eZ80190 Development Kit Quick Start Guide QS0004 to set up and run the demos on ZDS II Contacting ZiLOG
55. nt Kit User Manual Z ziape 67 A18 G A20 DIO 7 AD A16 D 0 7 Al 4 ATS A2 4 A14 DOE A211 A22 A23 AS A13 A 0 23 GSRAM RD not used here DO 2 D7 D1 7 o D6 2 8 CS1 CSRAM 0 CS1 Be Ps 9 x 4k7 p De SIP10 Ro Q2 WR 4 A11 A12 4 AB WR AQ A10 WRO A6 6 AT A4 OAS AT 7 o A19 512kx8 fast SRAM S0J36 400 AS7C34096 10JC VDD C1 100nF VSS 0603 Figure 22 eZ80190 Module Schematic Diagram 2 of 8 36 Pin SRAM Device UM014103 0803 PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual AR tiie LES U3 44 Intel Type AO DFLASHO 2 or T N DFLASH1 Ne DFLASH2 e eer DFLASH3 Nera DFLASH4 N25 15 DFLASH5 15 oy a DFLASH6 e NAT DFLASH7 z c2 Kaa CSFLASH CS 100nF 6 0603 WR CSFLASH NARA RESFLASH Koa coe R5 024 300 NAI 4 VPP C gt Kaisa p OR 0903 A20 A20 A21 used for 16 32Mbi t Fl ash Pi n37 N C for AMbit E Flash 1Mx8 3 3V TSOP40 20MM EES MT28FO008B3VG Dim 3 Dlo A 0 23 410 22 A22 A23 not used here UGA CS0 RD Q CSFLASH DIS_FLASH FLASH_EN WR WRG 74LCX32 R6 TSSOP14 csom St 40k e V3 3 0603 DIS_FLASH DIS_FLASH ve vss PEST RESET RESFLASH GND FLASHWE FLASHWE FLASHWE Note Must be pulled Low PERA externally for programming TSSOP14 Figure 23 eZ80190 Module Schematic Diagram 3 of 8 NOR Flash Device UM014103 0803 PRELIMINARY Schematic Diagrams L 3284 R11 BU S 2
56. on controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 20 Table 20 J17 RT 1 Shunt Status Function Affected Device In The Termination Resistor for RS485 1 is IN RS485 interface Out The Termination Resistor for RS8485 1 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Zi Diga Jumper J18 The J18 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 21 Table 21 J18 RT_2 Shunt Status Function Affected Device In The Termination Resistor for RS485 2 is IN RS485 interface Out The Termination Resistor for RS8485 2 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line Jumper J19 The J19 jumper connection selects the range of memory addresses for the external chip select signal CS_EX to the application module See Table 22 Table 22 J19 EX_SEL Shunt Status Function Affected Device 1 2 CS EX is decoded in the CSO memory space and is Application module located in the address range 400000h 7FFFFFh addressing
57. orm Labeled J21 Trig2 and J22 Trig1 these pins allow the user a way to trigger external equipment to aid in the debug of the system See Figure 8 for trigger pin details UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 28 Diog J21 J22 S L Ground OT J o1 L Trigger output OT 101 Trig2 Trig1 Figure 8 Trigger Pins J21 and J22 Bits 6 and 7 in Table 9 are the control bits for the user triggers If either bit is a 1 the corresponding Trig1 and Trig2 signals are driven High If either bit is 0 the corresponding Trig1 and Trig2 signals are driven Low Embedded Modem Socket Interface The eZ80 Development Platform features a socket for an optional 56K modem a modem is not included in the kit The tested modem for this eZ80190 Development Kit is a Conexant socket modem part number SF56D SP Information about this modem and its interface is available in the SmartSCM SocketModem data sheet Doc No 101522D from www con exant com Connectors J1 J5 and J9 provide connection capability The modem socket interface provided by these three connectors is shown in Figure 9 Tables 10 through 12 identify the pins for each connector The embedded modem utilizes UARTI which is available via the Port C pins eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual K ZInp Figure 9 Embedded Modem Socket Interface J1 J5
58. ran 5 C180 CONSOLE ka GREEN PD1_RXDOK 16 RaouT Rain L RXDO HE M 18 gasour pa L DB9 Female 3 E OK GND 9 LZ gt gt DIS_0 o MAXS245CAl RS485 1 EN R17 ji 10K c21 VDD E U26 PD1 RXDO so vwc Yee 01 209R ppo caz Dr U24 PD2 RTSO 3 pe ALS 0 1uF 120 SR Gus g v HZ cf 8 PDO TXDO 5 1 r rev_ 415 GND 4 24 c vH 2 P4 ca obi i oe DS1487 1 H Soe 1 r j o gt RTA GND a 5 Lo xm Pco_TxD H TiN Tour Tot U27 T DTR1 Pap PC4 DTR 18 T2lN T2our H9 PC1_RXD1 so vec 5 9 8 PC2 RTS19 2 TaIN aour 1L RTST 24 RE B bL con8 Ka MOD DIS A FORCEOFF PO2 RTS 2 DE A HS Ri m y FORCEON INVALID 21 POH 4 pi oup LBA GND jie 120 tok RH B 20 Roum PC5 DSRKK 32 1 R10UT Run DSR1 B ni E 1 DCD1 1 gt J14 RI1_NB 18 5 RI1 DSRT 6 RH B 1 ony BAV RXDI 2 59 J16 CH RIE 2 pca_crs 11 R3OUT Rain CTS eh RT 2 a Lo d 16 1 RXD1 CIS1 8 1 Header 3 PC1 Ep RAQUT Rein DIR141 2 gt gt DIS_1 La Den R o as pce_pcp lt paour RSIN D RH Bra e o J MODEM RS485 2 EN 2 EE DB9 Male o MAX3245CAI UM014103 0803 Figure 19 eZ80 Development Platform Schematic Diagram 4 of 5 PRELIMINARY eZ80F91 Development Kit User Manual Like 65 MATES WITH AMP 749268 1 P1 REEL E LENGTH 5 WIRES 28 AWG Figure 20 ez80 Development Platform Schematic Diagram 5 of 5 RS 485 Cabl
59. ripheral Power Down Register UO Connector JP2 Figure 7 illustrates the pin layout of the eZ80 Development Platform s I O Connector in the 50 pin header The I O Connector is located at position JP2 on the eZ809 Development Platform Table 3 describes the pins and their functions UM014103 0803 PRELIMINARY Operational Description 16 eZ80190 Development Kit User Manual K Diog PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PCO PD6 PD5 PD3 PD1 TDO GND_EXT TCK RTC_VDD IICSCL IICSDA ELASHWE CS3 RESET V3 3 EXT TDI TRIGOUT TMS EZ80CLK GND EXT DIS IRDA WAIT GND EXT NMI HEADER 25X2 IDC50 Figure 7 eZ80 Development Platform UO Connector Pin Configuration JP2 eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Table 3 eZ80 Development Platform UO Connector Identification JP2 Digs Pin Symbol Signal Direction Active Level eZ80F91 Signal 1 PB7 Bidirectional Yes 2 PB6 Bidirectional Yes 3 PBS Bidirectional Yes 4 PB4 Bidirectional Yes 5 PB3 Bidirectional Yes 6 PB2 Bidirectional Yes 7 PB1 Bidirectional Yes 8 PBO Bidirectional Yes 9 GND 10 PC7 Bidirectional Yes 11 PC6 Bidirectional Yes 12 PC5 Bidirectional Yes 13 PC4 Bidirectional Yes 14 PC3 Bidirectional Yes 15 PC2 Bidirectional Yes 16 PC1 Bidirectional Yes 17 PCO Bidirectional Yes 18 PD7 Bidirectional Yes Notes 1 For
60. rs Figure 4 Basic eZ80 Development Platform Block Diagram eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Tiig Physical Dimensions The dimensions of the eZ80 Development Platform PCB is 177 8mm x182 9mm The overall height is 38 1 mm See Figure 5 lt 175 3 mm gt Le 43 2 mm lt 114 3 mm gt lt 96 5 mm gt lt 55 9 mm gt al VOLT SELECT ro Lo e ct i o o o o cg al lo me col BFE BFE IEXANT SOCKETMODEM SF56D SP Eio20999099000990099009000099009 ET 2 Uni 5 WOON mmm se e e Deag amm imm Z loO000000000000000000000000 pooo000000000000000000000 9 z COPYRIGHT ZiLOG INC 2002 e280 WEBSERVER MODULE it vec c38 opd E EF sa o o o C 20 J S EX TRIG2 TRIG FLDS ID manni 5i Z lan RIS pm oy
61. t output control and LED anode register functions The register at address 800001h controls the register functions for the LED cathode modem reset and user triggers Address 800002h controls general pur pose port data Table 6 LED and Port Emulation Addresses Address Register Function Access 800000h LED Anode General Purpose Port WR Output Control 800001h LED Cathode Modem Trig WR 800002h General Purpose Port Data RD WR General Purpose Port The general purpose port is emulated with the use of the GPIO Output Control Register and the GPIO Data Register If bit 7 in the GPIO Output Control Register is 1 all of the lines on the general purpose port are con figured as inputs If this bit is O all of the lines on the general purpose port are configured as outputs Table 7 lists the multiple functions of the register Table 7 LED Anode General Purpose Port Output Control Register Bit 4 Function 7 6 5 4 3 2 1 0 Anode Col 1 Anode Col 2 X Anode Col 3 X Anode Col 4 X eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Am Tiig Table 7 LED Anode General Purpose Port Output Control Register Continued Bit Function 7 6 5 4 3 2 1 0 Anode Col 5 X Anode Col 6 X Anode Col 6 X GPIO Output X The GPIO Data Register receives inputs or provides outputs for each of the seven general purpose port lines depending on the configurat
62. teristics of the eZ80 Development Platform with Different Module Loads Continued Current Platform Modules Configurations Requirement mA Status eZ80 Development Platform eZ80190 350 When the LED demo is Module and Thermostat Application running Module eZ80 Development Platform eZ80190 360 When the LED demo is Module Modem Module and running Thermostat Application Module UM014103 0803 PRELIMINARY DC Characteristics eZ80190 Development Kit User Manual Diog eZ80190 Module This section describes the eZ80190 Module hardware its interfaces and key components including the CPU Ethernet Media Access Controller EMAC and memory Functional Description The eZ80190 Module is a compact high performance Ethernet module specially designed for the rapid development and deployment of embed ded systems requiring control and Internet Intranet connectivity via Ethernet and or fast Multiply Accumulate operations Additional devices such as serial ports LED matrices GPIO ports and DC devices are sup ported when connected to the eZ80 Development Platform A block dia gram representing both of these boards is shown in Figure 1 on page 4 The eZ80190 Module is developed to be a plug in module to the eZ80 Development Platform The small footprint eZ80190 Module provides a CPU SRAM Flash memory a real time clock and an EMAC This low cost expandable module is powered by the eZ80190 microprocessor a member of Z
63. the eZ80190 Module ZiLOG FAB 98C0877 001 A O bie r O O O O cB 0000 c5i Goce c 00 III 9000 FUDD c ID OR14 ERG iai C1B DH 8 DHC23 RIII eB amp SB SB Ec gE Pren paub R3200 DOC R22 ET ege 31 o Ct O GOR33 e geht pp 2002 O H o Dia Figure 13 eZ80190 Module Bottom Layer OO OO O o o O o o O O O O O O O O O O O O o o O O O O O o O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Operational Description The purpose of the eZ80190 Module as a feature of the eZ80190 Devel opment Kit is to provide the application developer with a plug in tool to evaluate memory and the other features of the eZ80190 device UMO014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 48 Diog Ethernet Media Access Controller The eZ80190 Module contains a CS8900A Ethernet Media Access Con troller EMAC combines MAC and PHY functions which is attached to the data address bus A0 A3 D0 D7 RD and WR of the processor This chip is connected to the processor s CS3 Chip Select and to the PD4 pins for interrupt purposes Connection of pins PD6 and PD7 for LANACT wake up from sleep and SLEEP is optional and resistor selectable onboard see below Details about the internal registers of the CS8900A EMAC can be found on the Cirrus Logic website at www cir rus com Ethernet LEDs There are two
64. the figure Note Key to blocks A D A eZ80190 Module interfaces B eZ80190 CPU C 10 100BaseT Ethernet Interface D IrDA transceiver Figure 3 The eZ80190 Module The structures of the eZ809 Development Platform and the eZ80190 Module are illustrated in the Schematic Diagrams starting on page 61 Introduction PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual Zi Tiig eZ80 Development Platform This section describes the eZ80 Development Platform hardware its key components and its interfaces including detailed programmer interface information such as memory maps register definitions and interrupt usage Functional Description The eZ80 Development Platform consists of seven major hardware blocks These blocks listed below are diagrammed in Figure 4 e780190 Module interface 2 male headers Power supply for the eZ80 Development Platform the eZ80190 Module and application modules Application Module interface 2 female headers General Purpose Port and LED matrix e RS232 serial communications ports Embedded modem interface e C devices UM014103 0803 PRELIMINARY Functional Description eZ80190 Development Kit User Manual Z 8 Diog l l I Peripheral Device Signals l l eZ80 Module Interface RS232 0 SRAM Console 512 KB up to 2 MB WEE RS232 1 Modem LED 7x5 matrix GPIO and Pc Address EEPROM Decoder T Application Module Heade
65. w the DIS FL input signal disables the Flash chip on the eZ80190 Module Flash Write Enable When active Low the FlashWE input signal enables Write operations on the Flash boot block of the eZ80190 Module Disable IrDA This signal does not perform a function on the eZ80190 Module UARTO is always used with the RS232 interface on the eZ80 Development Plat form Application Module Interface An Application Module Interface is provided to allow the user to add an application specific module to the eZ80 Development Platform ZiLOG s Thermostat Application Module not provided in the Kit is an example application specific module that demonstrates an HVAC control system eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual AR ZInp To design an application module the user should be familiar with the architecture and features of the eZ80190 Module currently installed Implementing an application module via the Application Module Interface requires that the eZ80190 Module also be mounted on the eZ80 Develop ment Platform because it the eZ80190 Module contains the eZ80190 microprocessor To mount an application module use the two male con nectors J6 and J8 Connector J6 carries the GPIO signals and connector J8 carries memory and control signals Tables 4 and 5 list the signals and functions related to each of these jumpers by pin Power and ground signals are omitted for the s
66. ws lower current because only the receiver is operating A zero Ohm resistor at position R14 on the eZ80190 Development Kit is required for this function If LAN activity is detected the LANACT signal is pulled Low The LANACT is connected to GPIO input PD6 and can be used in interrupt edge detection mode to wake up and reinitialize the Ethernet chip A zero Ohm resistor at position R15 on the module is required for this func tion In this case the PD6 pin is not available for GPIO on the I O con nector EMAC Access CS3 is used for selecting the Ethernet MAC For 50MHz operation set the CS3 CTL register I O address B3h to F8h 7 wait states for I O The EMAC requires IOR to be active for 135ns and IOW to be active for 110ns To satisfy proper setup times at 50 MHz IOR is delayed by one clock cycle and IOW is delayed by two clock cycles when CS3 goes active To satisfy proper hold times at 50 MHz the EMAC address and data are latched when CS3 goes inactive UM014103 0803 PRELIMINARY Operational Description eZ80190 Development Kit User Manual 50 Diog eZ80190 Module Memory The eZ80190 Module contains 512KB SRAM and 1 MB Flash memory This addressing structure provides 1 5 MB of contiguous RAM for imme diate use SRAM Memory The eZ80190 Module features 512KB of fast SRAM Access speed is typically 12ns or faster allowing zero wait state operation at 50 MHZ With the CPU at 50MHz onboard SRAM can be accessed with
67. y U3 Upon power up of the eZ809 Development Platform and the eZ80 Webserver i E NET Module the eZ80190 device on the module starts running code from this Flash memory area This code enables the Console port with settings of 577 6kbps 8 N 1 The Console checks the Receive buffer If a space character is received on the Console port the Flash Loader utility is enabled and a boot message should be displayed on your connected device If no message is dis played check the following Jumper J2 must be ON IrDA is disabled On Connector J6 the jumper must be removed from pins 6 and 9 pin names con dis and GND UM014103 0803 PRELIMINARY Overview eZ80190 Development Kit User Manual 58 Diog IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80 Webserver i E NET Module make sure the hardware is set up as follows Jumper J2 must be OFF to enable the control gate that drives the IrDA device Set port pin PD2 Low When this port pin and Jumper J2 are turned OFF the IrDA device is enabled Install a jumper on connector J6 across pin names con dis and GND to disable the console serial port driver Difference Between EMAC and IP Address Media Access Control MAC Each and every Ethernet device interface to the network media e g net work adapter port on a hub contains a unique MAC address which is hard coded into the hardware when it is manufactured An Ethernet device addresses a
68. y the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register eZ80 Development Platform PRELIMINARY UM014103 0803 eZ80190 Development Kit User Manual ZInp 15 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued eZ801900100ZCO Pin Symbol Signal Direction Active Level Signal 46 RD Bidirectional Low Yes 47 WR Bidirectional Low Yes 48 INSTRD Input Low Yes 49 BUSACK Input Pull Up 10KQ Low Yes 50 BUSREQ Output Pull Up 10KQ Low Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80190 Module Schematic Diagrams on pages 66 through 73 2 The Power and Ground nets are connected directly to the e2801900100ZCO device Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Pe

eZ80190 Development Kit User Manual - Digi-Key

Contents

Download Pdf Manuals

Related Search

Related Contents