MI/O Extension Spec - Mouser Electronics
Contents
1. Pin Name Pin 1 GND 2 3 PCIE_RXO PCIE_TXO 4 5 PCIE_RXO PCIE_TXO 6 7 GND GND 8 9 PCIE_RX1 PCIE_TX1 10 11 PCIE_RX1 PCIE_TX1 12 13 GND GND 14 15 PCIE_RX2 PCIE_TX2 16 17 PCIE_RX2 Pin PCIE_TX2 18 19 GND 83 84 85 86 GND 20 21 PCIE_RX3 GND PCIE_TX3 22 23 PCIE_RX3 PCIE_TX3 24 25 GND GND 26 27 PCIE_CLK 28 29 PCIE_CLK 30 31 GND 32 33 SMB_STB_CLK 34 35 SMB_STB_DAT 36 37 PCIE_WAKE 38 39 RESET 40 41 PowerOn 42 43 NC 44 47 GND LPC_AD2 48 51 DDP_AUX LPC_DRQ O 52 53 GND LPC_SERIRQ 54 55 DDP_DO LPC_FRAME 56 57 DDP_DO GND 58 59 GND USBO_D 60 61 DDP_D1 USBO_D 62 65 GND USB1_D USB_SSTX 66 69 DDP_D2 GND 70 71 GND USB2_D USB_SSRX 72 73 DDP_D3 USB2_D USB_SSRX 74 75 DDP_D3 GND 76 77 GND USB_OC 78 11 2 1 Audio The CODEC of AC 97 Audio or HD Audio is established on the CPU board The audio signal LOUTL LOUTR and AGND are the interface for audio application 2 1 1 Signal Descriptions The following table shows audio interface signals including pin number signals 1 0 and descriptions Pin No Audio Pin Type Power Rail Description 0 1 2Vrms 28 LOUTL Analog output Left channel Note2 1 1 0 1 2Vrms 30 LOUTR Analog output Right channel Note2 1 1 32 AGND AGND 0 Analog GND Table 2 1 1 Audio Signal Descri2. 9 90 V5SB Power 5VSB I5Vmio 3000 mA 2000 mA Table 3 1 2 MlOe Board Power Rating 28 The following figure is a system power flowchart 12Vmio and 5Vmio are the current rating for I O board 5Vsys is the current rating for system I O devices and I5Vall is the current rating of 12VSB to 5VSB power module The following equation is a necessary result I5Vall 15Vmio I5Vsys The power rail 5VSB and 5V are isolated by MOSFET but they have the same power source To evaluate 5V power budget must be concerned both 5VSB and 5V system I O devices for example SATA HDD CF card PS2 keyboard and mouse The following equation indicates the truth of power flow I5Vsys la Ib Ic Id le where la SATA HDD power consumption current from power rail V5 Ib CF or CFast power consumption current from power rail V5 Ic LCD Panel power consumption current from power rail V5 Id PS2 KB MS power consumption current from power rail V5SB le USB device power consumption current from power rail V5SB MlOe board can use more power from CPU board if the customer can reduce the power consumption from system I O devices But the equation I5Vall I5Vsys I5Vmio must be obeyed In other words CPU board can use all the power from power module if without MIOe board MIO 5xxx MIO 2xxx Current Rating Current Rating Current Description It is current rating for 5V and 5VSB I5Vsys system I O devices connected
3. Pin Power Pin No Signal Description Type Rail SMB_STB_ Boe te is 33 CLK VOD 3 3VSB System Management Bus bidirectional clock line SMB_STB_ ae 35 DAT VOD 3 3VSB System Management Bus bidirectional data line Table 2 5 1 SMBus Signal Description The following table is SMBus DC parameters for reference Considering minimum VIL and maximum VIH need to regard DC parameters of the SMBus controller on the CPU board For general case the minimum VIL of 0 5V and maximum VIH of 3 8V are reasonable value for reference when SMBus controller is supplied power with 3 3V Other details need to refer to System Management Bus SMBus Specification Version 2 0 Symbol Min Max Units VIL 0 8 V VIH 2 1 V Table 2 5 2 SMBus DC parameters 2 5 2 Schematic Guidelines The pull up resistor size for the SMBus data and clock signals is dependent on the bus load this includes all device leakage currents Generally the SMBus device that can sink the least amount of current is the limiting agent on how small the resistor can be The pull up resistor cannot be made so large that the bus time constant Resistance X Capacitance does not meet the SMBus rise and time specification The maximum bus capacitance that a physical segment can reach is 400 pF and the evaluation of capacitance is 3 3 pF per inch of trace length e The following figure is example circuit for SMBus The SMBus controlle
4. CPU board are generally set as 2Eh and 29Ch The recommendatory I O address is 4Eh if there is LPC device on I O board The following figure shows the application CPU Board T O Board LPC Super I O amp Other Devices LPC Device 1 VO Address 2Eh VO Address 4Eh 2 0 Address 29Ch Figure 2 3 1 LPC Example 16 2 4 PCI Express MlOe provides a PCI Express Bus interface that is compliant with the PCI Express Base Specification Revision 1 0 It supports four general purpose PCI Express port x1 and other configurations for example PCI Express port x2 or PCI Express port x4 PCI Express port x1 is the default setting and other available configurations need to refer to product specification and request vendor s technical support 2 4 1 Signal Descriptions PCI Express Lanes Pin No Pin Type Description General Purpose PCIE_TX0 6 PCIE_TX0 10 PCIE_TXI a POE IXI 5 PCI Express Differential Transmit Pairs 0 through 3 16 PCIE_TX2 PCIE 18 PCIE_TX2 22 PCIE_TX3 24 PCIE_TX3 3 PCIE_RX0 a PCIE_RX0 9 PCIE_RX1 A inne l PCI Express Differential Receive Pairs 0 through 3 15 PCIE_RX2 PCIE 17 PCIE_RX2 21 PCIE_RX3 23 PCIE_RX3 27 PCIE_CLK 0 R Reference clock output for all PCI Express 29 PCIE_CLK PCIE I Power Management Event Active low 37 PCIE_WAKE CMOS Used to reactivate the PCI Express devices main power rails and r
5. Holes Concentrated Thermal Design MIOe Unified Connector Compact Mechanical Design oe Less Cabling BW eas Design MA gt i gt Expansion Module Options By connecting with MIOe I O extension modules through high speed sockets customers get the most flexible I O choices to fulfill vertical applications The MlOe connector is ready for supporting additional extended interfaces and trend of future technologies which including DisplayPort 4 PCle x1 LPC SMBus USB2 0 USB3 0 Audio line out and Power The design of MI O Extension took into account of soft hard firmware applications These features are all parts of Advantech s thoughtful effort to J help integrators create their module designs most cost effectively in that integrators can flexibly develop market sensitive solutions and therefore get more promising business opportunities 1 2 Features MlOe Unified Connector gt A wiy Z TERN ty ae 2 Th Z Ore Ga MI O extension has one unified MIOe connector which supports additional extended interfaces that gives more flexible support to bundled I O modules either from MI O Extension solution provider or modules designed by the customer Through the interface the functions can be DisplayPort HDMI LVDS DVI CRT or eDP display type PCle x 1 GbE USB 3 0 SATA RAID FPGA or PCI expansion USB 2 0 3 0 Super speed storage capture card HD Webcam amp display interface LPC Lega
6. cass ie ea 24 2 1 3 Referenee Planes essen 24 2 7 4 Crossing Plane Splits 24 2 7 5 Referencing Different Plane Layers 25 2 7 6 Differential pair routing 26 Chapter 3 Power Management amp Power Delivery 28 3 1 Signal Descriptions and MIOe Power Rating 28 3 3 2 CPU Board Power rating without MIOe Board 31 3 3 DERSPEEIH CANON een 33 3 4 CPU board Supply Power to MIOe Board 33 3 5 External Power Source for CPU and MIOe Board 35 3 6 Other Design Concern ne 36 Chapter 4 Mechanical Characteristics 38 4 1 Mechanical Design 38 4 1 1 Mechanical Drawing e 39 4 1 2 MVO Compact Drawing e 40 4 1 3 MVO Ultra Drawing 44 4 1 4 Thermal Design u u 0 u0sss00u8an 0a 48 4 1 5 MIOe Connector aan gene 49 Chapter 1 General Information 1 1 Overview The innovative MI O multiple I O Extension Single Board Computer equipped flexible Multiple I O efficiency on schedule development resources amp assist integrators to provide optimized solutions in cost effective way while still securing the domain knowhow in key vertical industrial technologies uL gt 4 RE oA RT B Unified System ty Screw
7. needed to match lengths the following guidelines should be maintained The trace spacing should not become greater than 2 times the original spacing The length of the increased spacing should not be greater than 3 times the trace width A lt 3WH wi lt 2s Figure 2 7 6 serpentine rule 27 Chapter 3 Power Management amp Power Delivery This chapter provides the power supply design recommendations for customer s reference 3 1 Signal Descriptions and MlOe Power Rating The following table shows the power management signal including pin number signal naming pin type power rail and description The following section will introduce the real application for reference Pin Power NONE Pin No Signal Description Type Rail CPU board asserts RESET to reset devices on 39 RESET 0 3 3V the I O board e g LPC devices PCle devices LAN etc PowerOn can be used with application that needs 41 PowerOn 0 3 3V to turn on the power for MlOe board Table 3 1 1 Power Management Signal The following table shows independently the power rating for MI O Compact and MI O Ultra CPU board Figure 3 1 1 can explain the overall power flowchart in the system and define the symbol I5Vmio I5Vsys and 15Vall L Pin Power Current MIO 5xxx MIO 2xxx PinNo Signal Type Rail Symbol Current Rating Current Rating 79 80 V12SB Power 12VSB 112Vmio 2000 mA 2000 mA 87 88 8
8. with CPU 2000 mA 1000 mA board It is the current rating of 12VSB to 15Vall 5000 mA 3000 mA 5VSB power module on CPU board Table 3 1 3 CPU Board Power Rating 29 CPU Board VO Board V12SB I12Vmio mA gt V5SB 12VSB to i I5V mA 5VSB mio me Power Module Dyal ga 5V 5VSB System I O Devices 15Vall 15Vsys I5Vmio en Consumption 15Vsys la Ib Ic Id le 5 Ia mA u CF or CFast Power Consumption Ib mA LCD Panel Power Consumption Ic mA PS2 KB MS Power Consumption Id mA USB Device Power Consumption Te mA Figure 3 1 1 System Power Flowchart with MlOe board 30 3 2 CPU Board Power rating without MlOe Board The CPU board can be used alone without MIOe board It is easy to evaluate power budget of 5V power rail All the current rating of 12VSB to 5VSB power module can be used with 5V and 5VSB system I O devices connected with CPU board for example SATA HDD CF LCD panel PS2 and USB The following figure shows overall system power flowchart and the following table shows the current rating for MI O Compact and MI O Ultra CPU board without MlOe board On the figure 5Vsys is the current rating for system I O devices and 5Vall is the current rating of 12VSB to 5VSB power module The following equation is a necessary result I5Vall 15Vsys 31
9. 12_MlOe V5_MlOe lt 3 3V Figure 3 5 2 I O board power on sequence Min ms Max ms Description V12SB _ Ext active to V12SB_MlOe Tal 0 40 V5SB_MIOe V3 3SB_MIOe ready Ta2 0 20 PowerOn active to V12_MlOe V5_MlOe ready Ta3 0 20 PowerOn active to other power rail ready Table 3 5 1 Timing parameters 3 6 Other Design Concern PowerOn is the control signal to turn on main power rail and its maximum high level and low level output current is limited to under 1mA for I O board For high driving current application 74AHCT1G125 is the recommendatory solution for buffer The following figure shows this application and the following table is operating condition of IC 36 CPU Board VO Board V5SB V5SB PowerOn PowerOn 74AHCT1G125 Figure 3 6 1 PowerOn buffer UNIT Vcc Supply voltage VIH Hev in High level input voltage 2 Low level input voltage li o o IL I H L p s Input voltage ojojoj jnjo 2 elzlals 5181 Table 3 6 1 74AHCT1G125 operating condition RESET is reset signal and its maximum high level and low level output current is limited to under 1mA for I O board For high driving current application 74AHCT1G125 is the recommendatory solution for buffer 37 Chapter 4 Mechanical Characteristics 4 1 Mechanical Design MI O Extension Form Factor The Flexible Signal Board Compu
10. 6 Part No Printed in China Nov 2011 Chapter 1 General Information 5 en ee le ee ten 5 A DTIC ALTE 6 1 3 Name and Logo Usage nn ken 9 1 4 Definition Siisti aene erasi 10 Chap 2 Pin 455 5 1 PAET 12 2 1 1 Signal Descriptions v 26 Ass 12 2 1 2 Schematic Guidelines 13 2 2 Display Ports manager 14 2 2 1 Signal Descriptions nase 14 2 2 2 Schematic Guidelines nenn 15 7 LPC IE eS ac Sadan uaalaes 16 2 3 1 Signal Descriptions 16 2 3 2 Schematic Guidelines nen Hanne 16 DAC LI RDUGSS aa enge 17 2 4 1 Signal Descriptions 17 2 4 2 Schematic Guidelines 18 2 SS MBUS 2 une see 19 2 5 1 Signal Descriptions 19 2 5 2 Schematic Goidelinies aussen screen 19 ZB USB 1 22 2 6 1 Signal Descriptions 22 2 6 2 Schematic Guidelines 22 2 7 General Layout Guidelines 2 2 32 24 2 1 1 Impedanee ennnen nn 24 2 TOSS Ua Lies
11. AD ANTECH Enabling an Intelligent Planet Mio Extension MI O Extension Single Board Computer Specification November 2011 V1 0 Copyright This document is copyrighted 2011 All rights are reserved The copyright on this user manual remains with Advantech Co Ltd No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of the original manufacturer All brand and product names mentioned herein are trademarks or registered trademarks of their respective holders If you have any questions please contact your merchant or our service center for clarification We are not responsible for any losses resulting from using this product no matter what the reason Acknowledgements MI O Extension and MlOe are trademarks of Advantech Co Ltd Award is a trademark of Award Software International Inc IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation Intel is trademark of Intel Corporation Microsoft Windows is a registered trademark of Microsoft Corp RTL is a trademark of Realtek Semi Conductor Co Ltd ESS is a trademark of ESS Technology Inc Creative is a trademark of Creative Technology LTD CHRONTEL is a trademark of Chrontel Inc All other product names or trademarks are properties of their respective owners Revision History Version Date Description V1 0 2011 11 1
12. CPU Board V12SB V5SB 12VSB to 1 5VSB Power Module 15Vall mA 5V 5VSB System I O Devices SATA HDD Power Consumption Ta mA I5Vall I5Vsys CF or CFast Power Consumption Ib mA _ lt 2 u 3 LCD Panel Power Consumption Ic mA PS2 KB MS Power Consumption Id mA USB Device Power Consumption Te mA Figure 3 2 1 System Power Flowchart without MIOe board 32 MI O Extension MI O Extension Compact Series Ultra Series Current Description Current Rating Current Rating It is current rating for 5V and 5VSB I5Vsys system I O devices connected with CPU 5000 mA 3000 mA board It is the current rating of 12VSB to 15Vall 5000 mA 3000 mA 5VSB power module on CPU board Table 3 2 3 CPU Board Power Rating without MIOe Board 3 3 DC Specifications Pin Power Voltage Voltage Voltage Pin No Signal Type Rail Typical Min Max 79 80 V12SB Power 12VSB 12V 10 8V 13 2V 87 88 8 9 90 V5SB Power 5VSB 5V 4 75V 5 25V Table 3 3 1 MIOe DC specification 3 4 CPU board Supply Power to MlOe Board The following figure is the application that CPU board can fully supply power to I O board In lower power consumption case CPU board can provide enough power to meet I O board requirement and PowerOn is the must control sign
13. EF 0525 1 334 REF SECTION A A 50
14. O Extension SBC H 19mm Post e c Thermal Solution MI O Extension SBC The component maximum height in top side of MIOe module is 7mm 46 With MlOe module installation Thermal Solution MIO Extension SBC H 19mm POST MIOe Module Thermal Solution MI O Extension SBC MlOe Module 4 1 4 Thermal Design MI O Compact Thermal generation parts in the gray zone 102 146 Hy W MI O Ultra SBC Thermal generation parts in the gray zone 8 at En A Memory Zone CPU SB Zone 72 0 75 25 I 0347 100 00 48 4 1 5 MlOe Connector The connector vendor is Samtec Connector location Samtec P N Description Connector on CPU Board QSE 040 01 L D B B Conn 40x2P 0 8mm 180D F SMD zs Connector location Samtec P N Description Connector on MlOe module REF 165028 01 B B Conn 40x2P 0 8mm 180D M SMD 19mm mating height 1 5750 40 005 7878 20 009 REF 19 EQ SPACES E 03125 800 naana FEW f 1550 3 937 a 2350 5 969 2650 6 731 REF REF REF i d4 0080 0 203 REF 035 0 88 REF 6450 16 383 REF Samtec Website http www samtec com 49 3962 10 063 REF amp 7450 18 923 REF 1 515 38 48 REF 0350 0 889 REF 0 08 71972031 18 263 9 08 2810 7 137 REF 0515 1 308 R
15. Power Source for CPU and MlOe Board For some application CPU board can t supply enough power to I O board It is a recommendable solution to plug in external power supply for CPU and I O board The following figure shows the simple circuits and power on sequence for this application Some check points are very important as the below and designer must follow up these suggestions 1 The single power supply must provide power for CPU and I O board simultaneously 2 On the I O board the power pin V5SB amp V12SB of MIOe connector must be left open 3 On the I O board the GND pin of MlOe connector must be connected 4 Use PowerOn as control signal to turn on main power V12_MIOe and V5_MIOe and meet the power on sequence and timing parameters as the figure and table below Power Supply V12SB_Ext V12SB Ext GND al CPU Board MIOe T O Board Current Voltage Y 2SB_MiOe V12_MlOe Protect R V12SB V12SB_MIOe vV ST 514435DDY T1 GE3 100K Current Voltage Protect NO V5SB_MIOe Connect V5 B 12V to 5V Power Module V5SB_MlOe V5_MlOe a PowerOn PowerOn V12SB_MlOe FDMC7696 2 Figure 3 5 1 External power source for CPU and I O board 35 I O Board Power On Sequence V12SB_Ext Tal V12SB_MlOe V5SB_MlOe PowerOn 4 Ta3 V
16. al to turn on the main power V12 V5 and V3 3 In this case the power V12 V5 and V3 3 are obtained from MOSFET Q1 Q3 and Q4 whose gate is controlled by signal PowerOn The rising timing can be fine tuned by the soft start circuit R2 R4 and C1 for Q1 R7 C2 and C3 for Q3 Q4 connected with the individual MOSFET MOSFET with soft start circuit can reduce inrush current 33 when it is turned on But rising timing requirement must be concerned the following power on sequence and timing parameters are necessary conditions MIOe VO Board ST4435DDY T1 GES 100K V5SB V5SB to V3 3SB 258 Power Module PowerOn PowerO V12SB V5SB is 9 EJ T i o P V12SB ke o e Av 130 3 V12SB EN V5_ V3 3 Figure 3 4 1 CPU board supply power to I O board The following figure is power sequence requirement for I O board CPU board can t work normally if I O board doesn t follow up this specification I O Board Power On Sequence V12SB V5SB V3 3SB Tai i PowerOn Ta2 V12 V5 j Tas lt 3 3V Figure 3 4 2 I O board power on sequence Min ms Max ms Description V12SB V5SB V3 3SB active to Tal 0 40 V12SB V5SB V3 3SB ready Ta2 0 20 PowerOn active to V12 V5 ready Ta3 0 20 PowerOn active to other power rail ready Table 3 4 1 Timing parameters 34 3 5 External
17. connector V5_USB f O 074 F 0 1uF R165 NL 0 5 M0402 USB z D USB z D 90_100MHZ 4V5_USBo R166 NL O 5 0402 Bs 420099 EMI Solution by GND_F close to connector ESD Protection close to connector Figure 2 6 2 Demonstration for EMI and ESD design 23 2 7 General Layout Guidelines This section provides general layout guideline for high speed signals PCI Express USB and Display port 2 7 1 Impedance In a high speed signaling environment signal trace impedances must be controlled in order to maintain good signal quality across the motherboard Signal trace impedance is a function of the following three factors e Motherboard stack up e Dielectric constant of the PCB substrate e Signal trace width and thickness 2 7 2 Crosstalk The following list of recommendations should be followed to help reduce the crosstalk on the motherboard Do not allow high speed signals to cross plane splits e Reference critical signals to ground planes Do not cut ground planes unless it is absolutely necessary e Reduce the length of signals that are routed parallel e Provide analog signals with guard shields or guard rings Keep analog signals away from digital signals 2 7 3 Reference Planes The high frequency return path for any signal lies directly beneath the signal on the adjacent layer Provid
18. cy bus amp Multi UART PS2 GPIO FDD IR Parallel port from super I O HD Audio Line out keep flexibility with selected amplifier SMBus GPIO control Smart battery Charger W R EEPROM Power Supported by MI O Extension SBC Expansion Module Options CAA Standard modules that ready for future interfaces and flexibility for varies vertical application demands Display module or Communication module or Multiple I O module from MI O Extension solution vendors 9 Customer s own MlOe module to secure domain knowhow Unified System Screw Holes MlOe Extension provide unified screw mounting holes for thermal solution assembly and system integration 9 Easy for system maintain 9 Easy for platform upgrade Concentrated Thermal Design dd N Traditional the heat flow was designed on the topic and bottom sides of embedded boards MI O Extension SBC is designed with concentrated thermal design that all heat generation parts in top side disperse the heat via the heat sink or the heat spreader with better result Covers CPU the Southbridge Memory Power and active IC Maximum thermal space Heat spreader Heatsink Integration Simplify the system design Put thermal sensitive parts in bottom side to prevent thermal problems Reduced Cabling MI O Extension single board computers with unified I O connector coastlines and uniformly expanded compatibility of its CF card and mini PCle locations An ar
19. ea under the board is also designated for 2 5 hard disk The structural uniformity helps eradicating possible problems with structural interference during future upgrades Less cabling and Lockable connectors in bottom side Reduce assembly schedule complex procedures and labor cost Compact Mechanical Design Compact and simple integration are the major concern of embedded system integrator Reduce system assembly parts Saves up to 20 system space Optional heat spreader could have lowest total height 1 3 Name and Logo Usage Manufacturers or distributors can use the MI O Extension logo in promoting products if meet the Specification definition on the document The name and logo of MI O Extension and MlOe are trademarks of Advantech Technology in process of registration These trademarks must be followed by the TM symbol 1 4 Definitions Signal Naming Convention REO TH TX A 0 31 Bused signals are indicated by brackets with LS bit first MS bit last CBE 0 3 Bus brackets may appear anywhere in the signal name Pin and Signal Buffer Types Pin Types Input to the module Output from the module Bi directional input output signal Open drain output Buffer Types Logic input or output Input thresholds and output levels shall be 80 of supply rail for high side CMOS and 20 of the relevant supply rail for low side PCI Express compatible differential signal Please refer to
20. eference clocks Table 2 4 1 PCI Express signals 17 2 4 2 Schematic Guidelines Each PCI Express lane is AC coupled between its corresponding transmitter TX and receiver RX A 75 nF to 200 nF AC coupling capacitor is recommendable design The following figure shows the interconnection between CPU and I O boards The AC coupling capacitors of TX is present on CPU board The AC coupling capacitors of RX should be placed on the I O board and closely to the transmitter pins of the PCI Express devices If some of the PCI Express port s is not implemented on MlOe PCIE_TX n PCIE_RX n PCIE_CLK and PCIE_WAKE signals may be left unconnected where n is the port number CPU Board MIOe VO Board AC Coupling Cap 75 nF 200 nF C PCIE_TX0 PCIE_RX0 PCIE_RXO C AC Coupling Cap 75 nF 200 nF PCIE _CLK Figure 2 4 1 PCI Express Interconnection MlOe only supports one differential clock for I O board I O board needs added clock buffer if devices are more than one piece The following figure shows this application CPU Board MIOe VO Board PCIE_CLKO Device 0 PCIE_CLK1 A PCIE_CLK Clock PCE Device 1 PCIE_CLK Buffer PCIE _CLK2 PCIE_CLK3 PCIE CLK3 Device 3 Figure 2 4 2 PCI Express clock buffer 18 2 5 SMBus MlOe supports System Management Bus SMBus Specification Version 2 0 2 5 1 Signal Descriptions
21. ing a solid plane underneath a signal greatly reduces problems with signal integrity timing and EMI because the plane provides a direct return path for that signal There are two cases where a signal can change its reference plane crossing a plane split or changing signal layers If either of these are unavoidable techniques must be used to minimize the negative impact caused by changing reference planes 2 7 4 Crossing Plane Splits When crossing a plane split a 0 1 uF or 0 01 uF stitching capacitor with a 0402 or smaller body size should be used Place the stitching capacitors as close as possible to the traces crossing the split as shown in Figure 2 7 1 24 Trace Crossing Plane Splits Stitching Cap Trace Trace Reference Plane 1 Reference Plane 2 Side View Trace 2 Trace Dil TOP View Reference Plane 1 Reference Plane 2 Figure 2 7 1 Trace Crossing Plane Splits 2 7 5 Referencing Different Plane Layers When signal traces change layers ground stitching via should be placed amongst the signal via in order to provide a return path Place the stitching via as close as possible to the signal via as shown in Figure 2 7 2 Ground Stitching Via TOP Microstrip Stitching Via GND Plane Signal Via Side View Signal Via GND Plane BOT Microstrip Stitching Via TOP View TOP Microstrip Sig
22. n shall use 6 4mm diameter pads and shall have 3 2mm plated holes for use with M3 hardware The pads shall be tied to the PCB ground plane Stand off M3x D5 5x L1imm 41 MI O Compact Installation mm Without MIOe module installation Thermal Solution MI O Extension SBC H 11mm Stand Off Thermal Solution MI O Extension SBC 42 H 19mm POST MIOe Module With MlOe module installation Thermal Solution MI O Extension sac Q MIOe Module The component maximum height in top side of MIOe module is 7mm 43 19 4 1 3 MI O Ultra Drawing MI O Ultra Top side mm SS gr 26 40 LOCO YES Y ORTE f VigssoMemory Zone gg LEI 000004 2 CPG Caged COR OIROS ROS ROS MELO EIEIO or IS 1 O Connect Z MI O Ultra Bottom side mm GN ie T LIS 7 7777 77 7 6 40 1 0 Connector 44 The component maximum height in bottom side is 15mm on MI O Ultra SBC Tolerances shall be 0 25mm 0 010 unless noted otherwise The tolerances on MlOe connector locating peg holes dimensions 8 27 23 80 shall be 0 10mm 0 004 The 4 mounting holes shown shall use 6 4mm diameter pads and shall have3 2mm plated holes for use with M3 hardware The pads shall be tied to the PCB ground plane Stand off M3x D5 5x L1imm 45 MI O Ultra SBC Installation mm Without MIOe module installation Thermal Solution MI
23. nal Via BOT Microstrip Figure 2 7 2 Ground Stitching Via 25 2 7 6 Differential pair routing It is important to maintain routing symmetry between the two signals of a differential pair Failure to maintain symmetry between the signals of the differential pair will introduce an AC common mode voltage Preferred Symmetrical Routing Mo ooo Avoid Non symmetrical Routing En eNO e Figure 2 7 3 Symmetrical Routing for differential pair There is only one lane and each link will be routed to different devices at varied locations of the board it is most practical to route the TX signal and the RX signal of that lane next to each other on the same layer Differential Pair length matching should be maintained segment to segment Examples of segments might include breakout areas route to connect vias route to connect a connector and so forth Break out gt Break in TX Via Via LA OJ LB s LC O LD TX 5 RX LA HOJ LB Lc LO LD TX 3 Figure 2 7 4 length matching example When trace length matching compensation occurs it should be made as close as possible to the point where the variation occurs as shown in Figure 2 7 5 26 O Match near mismatch gt x Avoid gt Figure 2 7 5 length matching compensation near mismatch When serpentining is
24. ption Note 2 1 1 This value is just for reference and the real one must refer to the corresponding codec spec 12 2 1 2 Schematic Guidelines The following schematics show audio amplifier application For the CPU board the codec with AC couple capacitor and EMI solution is present On the I O board LDO is the better power solution for this application and can supply clean power to audio amplifier All the components should refer to analog ground AGND and should reserve the resistor for current return path between AGND and GND CPU Board Audio Amplifier 4V5_AUD tele HOUR eav tev tev u7 QN_MC78MOSCDTRKG AGND AGND AGND EMI Solution AC97 c Bead R146 yy 20K 5 INA AMP HD cse yaz r 16v BYPASS ANP CODEC Bead a R148 20K 5 INB AMP 15 J c c RIS iok 1 lt Characteristic gt RE AGND AGND AGND 4 088 yp 100uF LINEOUT A 16 R ss ik 5 AGND R153 yy 20K 5 INB AMP SPKL u LINEOUT_L oes ap io o msa ach 1k 3 EMI Solution AGND Figure 2 1 1 Audio Amplifier Application 13 2 2 Display Port MlOe can support one display port for DP eDP HDMI or LVDS application Some embedded applications for example eDP or LVDS should be working with video BIOS for setting panel information 2 2 1 Signal Descriptions The following table shows DisplayPor
25. r on CPU board is powered by V3 3SB power rail SMB_STB_CLK and SMB_STB_DAT signals 19 are pulled high on CPU board and don t need any pull high resistor for SMBus on I O board CPU Board VO Board EEPROM V3 3SB SMB_STB_DAT SMB_STB_CLK Figure 2 5 1 SMBus Example Devices that are powered by the V3 3SB well must not drive into other devices that are powered off To avoid leakage current from V3 3SB to V3 3 this is accomplished with the bus switch The figure below is the example for reference CPU Board TO Board EEPROM V3 3SB Bus Switch SMB_DAT 442K 543 3 Q22 2N7002E SMB_STB_DAT z SMB_STB_CLK SMB_CLK amp 543 3 Q21 2N7002E Figure 2 5 2 Bus Switch for SMBus For multiple devices on SMBus this is accomplished with the bus repeater to enhance driving capacity PCA9515 is a recommendatory solution for this application 20 CPU Board V3 3SB SMB_STB_CLK VO Board V3 3SB V3 3SB Bus Repeater NC VCC Eve STB DAT SCLO 501 RESET SDAO SDA1 T oug Ei E SMB_Dev_CLK SMB_Dev_DAT Figure 2 5 3 Bus Repeater for SMBus 21 SMB_Dev_CLK SMB_Dev_DAT 3 3VSB SMBus Devices SMB_Dev_CLK SMB_Dev_DAT 3 3VSB SMBus Devices 3 3VSB SMBus Devices 2 6 USB MlOe can provide up to th
26. ree USB 2 0 ports or one USB 2 0 port and one USB 3 0 port For detailed configuration please refer to product spec 2 6 1 Signal Descriptions Pin No Signal Pin Type Description 60 USBO_D USB 2 0 USB 2 0 differential pairs channel 0 62 USBO_D USB 2 0 ee USB1_D USB 2 0 USB_SSTX USB 3 0 USB 2 0 differential pairs channel 1 or USB1_D USB 2 0 USB 3 0 differential pairs channel TX 68 a USB_SSTX USB 3 0 3 USB2_D USB 2 0 USB_SSRX USB 3 0 USB 2 0 differential pairs channel 2 or USB2 D USB 2 0 USB 3 0 differential pairs channel RX 74 a USB_SSRX USB 3 0 78 USB_OC 1 3 3VSB USB over current sense Table 2 6 1 USB Signal Description 2 6 2 Schematic Guidelines USB_OCH which is an input pin with pull up resistor on CPU board is used as over current sense for USB port For two or more USB over current detection this pin can connect with two or more open drain buffers 22 CPU Board MIOe T O Board V3 3SB_MIO USB_OC from USB Port V3 3SB SB or PCH TI_SN74AHC1G125DBVR USB_OC USB_OC V3 3SB_MIO 1 USB_OC from USB Port TI_SN74AHC1G125DBVR Figure 2 6 1 Demonstration for USB over current sensing Considering EMI and ESD issue the common mode choke and TVS Transient Voltage Suppression diode with low capacitance which should be less than 1 0pF are the recommendatory solution For placement concern EMI and ESD solution should be close to
27. t interface signals including pin number signals 1 0 and descriptions Pin No Signal Pin Type Description VO 49 DDP_AUX DDP Display Port AUX VO 51 DDP_AUX DDP 0 55 DDP_D0 DDP 5 Display Port Lane 0 57 DDP_D0 DDP 0 61 DDP_D1 DDP 3 Display Port Lane 1 63 DDP_D1 DDP 0 67 DDP_D2 DDP 5 Display Port Lane 2 69 DDP_D2 DDP 0 78 DDP_D3 DDP 5 Display Port Lane 3 75 DDP_D3 DDP 45 DDP_HPD Display Port hot plug detect CMOS Table 2 2 1 Display Port 14 2 2 2 Schematic Guidelines For the application of all display port devices please refer to the schematic and layout guidelines from the display port device vendor and request vendor s technical support 15 2 3 LPC MlOe provides a LPC interface to some devices as Super I O TPM and others For general application Super I O can accomplish some legacy functions as Serial port Parallel port Floppy IR KBC and GPIO 2 3 1 Signal Descriptions Pin No LPC Interface Pin Type Description 42 LPC_CLK 0 LPC clock output 33MHz 44 LPC_ADO 46 LPC_AD1 LPC multiplexed address command and 48 LPC_AD2 data bus 50 LPC_AD3 52 LPC_DRQ 0 I LPC serial DMA request 54 LPC_SERIRQ VO LPC serial interrupt 56 LPC_FRAME o LPC frame indicates the start of an LPC cycle Table 2 3 1 LPC signal description 2 3 2 Schematic Guidelines The I O addresses for LPC devices on the
28. ter with MIOe Extension Modules Compact Series 146 mm gt Real I O connector coastline i 8 CF CFast O MiniPCle Expansion Dip Type 1 0 Zone 1 SMT Type I O Zone le Front Side Back Side Ultra Series A _ 100 mm a Ml0e Pin Assignments s DisplayPort LPC 4PClex1 HD Audio line out s USB 3 0 SMBus USB2 0x2 V12SB V5SB Power 2 5 Hard Disk zot zZ C CFast M oly Pin out functions depends on platform chipset Back Side 38 4 1 1 Mechanical Drawing MI O Extension SBC with 2 series one is MI O Compact and another one is MI O Ultra SBC The PCB size of the MI O Compact is 203mm x 146mm and 100 x 72mm for MIO Ultra The PCB thickness is designed at 1 6mm 10 The mounting holes shown in below are intended for mounting the MI O Extension SBC MlOe module and thermal solution combination The unit shown on below drawing is in millimeters 39 4 1 2 MI O Compact Drawing MI O Compact Top side mm SE A A A A A A 9 MI O Compact Bottom side mm NN Ve connector N The component maximum height in bottom side is 11mm on MI O Compact SBC Tolerances shall be 0 25mm 0 010 unless noted otherwise The tolerances on MlOe connector locating peg holes dimensions 8 40 13 36 shall be 0 10mm 0 0047 The 6 mounting holes show
29. the PCI Express Specification for details PCIE transmit pins module outputs shall be AC coupled on the module PCIE receive pins module inputs shall be DC coupled on the COM ExpressTM module and shall be assumed to be AC coupled PCIE off module close to the signal source If the target PCI Express device resides on the Carrier Board the module PCIE receive lanes target PCIE device transmit lanes shall be AC coupled near the device on the Carrier Board If the Carrier Board implements a PCIE slot then these signals shall be AC coupled on the add in card not on the Carrier Board PCI PCI 2 3 compatible signal Please refer to the PCI Rev 2 3 Specification for details SATA SATA compatible differential signal Please refer to the SATA Specification for details All COM ExpressTM SATA signals shall be AC coupled on the module LVDS Low Voltage Differential Signal 330mV nominal 450mV maximum differential signal USB USB 2 0 compatible differential signal Please refer to the USB 2 0 Specification for details REF Reference voltage output May be sourced from a module power plane Analog Inputs and Outputs used for Audio are analog signals Power Inputs used for power delivery to the module electronics 10 Chap 2 Pin Assignments MI O Extension has a number of connectors that allow you to configure your system to suit your application s3 s4 ss 36 37 88 89 bad
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