SH69P25
Contents
1. Features SH6610C Based Single Chip 4 Bit Micro Controller OTPROM 4K X 16 bits RAM 160 X 4 bits data memory Operation Voltage 2 4V 5 5V Typical 5 0V 22 CMOS Bi directional I O Pins Built in Pull high and Pull low Resistor for PortA PortF 4 Level Subroutine Nesting including interrupts One 8 Bit Auto Re load Timer Counter Warm Up timer Powerful Interrupt Sources TimerO Interrupt External Interrupts PORTB amp PORTC rising falling edge General Description SINO WEALTH SH69P25 OTP 4K 4 Bit Micro controller Oscillator OTP option Crystal Oscillator 32 768k 4MHz Ceramic Resonator 400k 4MHz RC Oscillator 400k 4MHz External Clock 30k 4MHz Instruction cycle time 4 32 768kHz 1221 for 32 768kHz OSC clock 4 4MHz 1us for AMHz OSC clock Two Low Power Operation Modes HALT and STOP Reset Built in Watch Dog Timer WDT OTP option Built in Power On Reset POR Built in Low Voltage Reset LVR Two LVR Level OTP option Level 1 2 5V Level 2 4 0V OTP type amp Code protection The SH69P25 is a 4 bit micro controller This chip integrates the SH6610C 4 bit CPU core with SRAM 4K OTPROM Timer and I O Ports Pin Configuration XI PORTE2 10 28 PORTE12. 2005 Add bonding diagram Change LVR low level voltage range from 2 5 0 1V to 2 540 2V 30
3. PORTD 0 3 Bit programmable I O PORTB 0 3 Bit programmable I O PORTC 0 3 Vector Interrupt Active rising or falling edge by system register setup VDD Power supplv pin OSCO OSC output pin No output in RC mode OSCI OSC input pin connected to a crystal ceramic or external resistor OTP Programming Pin Description OTP Program Mode Vpp P Ve Programming Power supply 5 5V P RESET Programming high voltage Power supply 11V ee EN OSCI Programming Clock input pin Programming Data pin Function Description 1 CPU The CPU contains the following function blocks Program Counter Arithmetic Logic Unit ALU Carry Flag Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and the Stack 1 1 PC Program Counter The Program Counter is used to address the 4K program ROM It consists of 12 bits the Page Register PC11 and the Ripple Carry Counters PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 and PCO The program counter normally increases by one 1 for every execution of an instruction except for the following cases 1 When executing a jump instruction such as JMP BAO 2 When executing a subroutine call instruction CALL 3 When an interrupt occurs 4 When the chip is in the INITIAL RESET mode The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP
4. 1 Oscillator Type 1 Crystal oscillator 32 768kHz 4MHz C1 Crystal 32 768k 4MHz C2 2 Ceramic resonator 400kHz 4MHz C1 Ceramic C2 3 RC oscillator 400kHz 4MHz VDD R OSCI C1 1000p OSCO JL 4 External input clock 30kHz AMHz OSCI External clock source OSCO 5 SH69P25 SH69P25 has one 8 bit timer The time counter has the following features 8 bit up counting timer counter Automatic re loads counter 8 level prescaler Interrupt on overflow from FF to 00 The simplified timer block diagram is shown below TOE TOS 5 1 Configuration and Operation TimerO consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH Both counter and load register have low order digits and high order digits Writing data into the timer load register TLOL TLOH can initialize the timer counter Load register programming Write the low order digit first and then the high order digit The timer counter is loaded with the contents of the load register automatically when the high order digit is written or the counter counts overflow from FF to 00 Timer Load Register Since the register H controls the physical READ and WRITE operation please follow these rules Write Operation First write Low nibble Then write High nibble to update the counter PRE SCALER E Te 8 BIT COUNTER
5. WDT under software controlled bv writing to the TMO register Pre scaler divide ratio Prescaler Divide Ratio Timer out Period 1 7ms 1 14ms 1 28ms 1 8 56ms 0 32 224ms 0 128 896ms 0 512 3 584ms 0 2048 Power on initial 14 336ms WDT Time WDT 0 875 mi Period PRESCALER TMO 0220 Internal 7ms mn RESSE SCALER 1 18 n 2 4 18 132 128 1512 12048 L I Final WDT Time out period 15 SH69P25 10 HALT and STOP Mode After the execution of HALT instruction the device will enter halt mode In the halt mode CPU will stop operating But peripheral circuit TimerO will keep operating After the execution of STOP instruction the device will enter stop mode In the stop mode the whole chip including oscillator will stop operating without watchdog timer if it is enabled In HALT mode SH69P25 can be waked up if any interrupt occurs In STOP mode SH69P25 can be waked up if port interrupt occurs or watchdog timer overflow WDT is enabled 11 OTP Option 11 1 Oscillator External Clock System Clock is provided by External Clock through OSCI RC Osc System Clock is provided by External RC through OSCI Crystal Ceremic Resonator 400k 4M System Clock is provided by Crystal Ceremic Resonator through OSCI and OSCO X tal 32768 System Clock is provided by Crystal 32 768k through OSCI and OSCO 11 2 Watchdog
6. to reset WDT 1F Reserved System Register 0E 12 refer to SH6610C User manual 1C TOS TOE 3 2 Svstem Register State Address Power On Reset Pin Reset Low Voltage Reset SH69P25 WDT Reset 00 0 0 0 0 01 0 0 0 0 02 000 000 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 PULLEN PH PL PBCFR 16 PA2OUT PA1OUT PAOOUT 17 PB3OUT PB2OUT PB1OUT PBOOUT 18 PC3OUT 200 PC1OUT PCOOUT 19 PD3OUT PD2OUT PD1OUT PDOOUT 1A PESOUT PE2OUT PE1OUT PEOOUT 1B PF1OUT PFOOUT 1C TOS TOE 1D 1E 1F Legend x unknown u unchanged unimplemented read as O SH69P25 3 3 Others Initial State Others After anv Reset Program Counter PC 000 CY Undefined Accumulator AC Undefined Data Memory Undefined 4 System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock to the CPU and any peripherals Instruction cycle time 1 4 32 768kHz 122us for 32 768kHz Oscillator 2 4 4MHz 1us for 4MHz Oscillator 4
7. 0 00 10 00 60 00 110 00 160 00 210 00 260 00 310 00 360 00 R kO Typical RC Oscillator Resistor vs Frequency Vpp 3V for reference only 3V RC Frequancy 10000 00 N I Ax 1000 00 o 17 LL 100 00 10 00 60 00 110 00 160 00 210 00 260 00 310 00 360 00 R 22 SH69P25 In Svstem Programming Notice for OTP The In System Programming technology is valid for SinoWealth OTP chip The Programming Interface of the OTP chip must be set on the user s application PCB and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip Of course it s accessible bonding OTP chip only first and then programming code and finally assembling other components Since the programming timing of Programming Interface is verv sensitive therefore four jumpers are needed VDD VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram Application PCB OTP Chip VPP VDD SCK OTP Writer SDA lt To Application Circuit lt 66 lt Jumper The recommended step is as follow for these jumpers 1 The jumper is Open to separate the programming pins from the application circuit before programmi
8. 9 can be displayed in this configuration ON OFF Vi1 Instrumentation Amplifier R6 1000 Vo 1 2R2 R1 R4 R3 Vi 10 47KQ 20 30 abcdefg abcdefg Jabcdefg 25 SH69P25 Bonding Diagram Amoma OPHDOU 42070 01 142 070 42020 2020 OmMHDOU 42027 20700 GNDI SH69P25 1879 6um OSCO GND2 P P P P P P P P P P P P V O O O O O O O O O O O O D R R R R R FR O R R R R R D T EC p CD B B B B D D D D C C C C 0 1 2 3 0 1 2 3 0 1 2 3 1920 24um Note 1 GND1 bonding to ground 2 GND2 bonding to Substratum 3 Substratum connects to ground Pad Location unit um Pad No Y 7498 7495 7495 7495 7495 7495 5195 227 Pad No Y 7495 7495 7495 7495 7495 7495 7 7495 585 7495 1 6 7495 7495 7495 7495 14 7495 7495 p p 16 17 18 19 20 21 22 23 24 25 26 27 28 26 Ordering Information Part No Packages SH69P25H CHIP FORM SH69P25K 28L SKINNY SH69P25M 28L SOP 27 SH69P25 SH69P25 Package Information SKINNY 28L Outline Dimensions unit inches mm Base Plane Mountin
9. AC 0 CY AC shift right one bit SHR 11110 0000 000 0000 Immediate Tvpe Lemon mom comm xi oromo cuca _ om wei wow xi ewm Decimal Adjustment 11001 0110 xxx xxxx AC Mx Decimal adjustment for add DAS X 11001 1010 xxx xxxx AC Mx Decimal adjustment for sub CY 17 SH69P25 Transfer Instructions _ Control Instructions lt 1 lt ifAC 3 1 lt CY 1 Flag Change gt Flag Change 11000 xxxx XXX xxxx lt X Not including p PC 4 ST TBR lt hhhh AC 1 oF Where emsa j RTNW H L 11010 000h hhh CY z 00 O X Immediate data RAM bank RAM bank Every 7F as one RAM bank Table Branch Register T ROM page s 18 SH69P25 Absolute Maximum Rating Comments DC Supply Voltage 0 3V to 7 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input Output Voltage GND 0 3V to Vpp 0 3V These are stress ratings only Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is Operating Amblent Temperature spas G not implied or intended Exp
10. PORTE3 2 27 PORTEO PORTF1 26 PORTFO PORTA2 4 25 PORTA 5 o 24 PORTAO TOL T 23 OSCI RESET 7 22 osco GND 8 U 21 PORTBO g gt 20 PORTC3 PORTB1 10 19 PORTC2 PORTB2 41 18 PORTC1 PORTB3 12 17 PORTCO PORTDO 43 16 PORTD3 PORTDI 44 15 PORTD2 1 V1 0 Block Diagram TO RESET OSCO OSCI LI LI T osc CPU WDTEN RC Y I RESET PRESCLALER PORTA 4 BITS WATCHDOG TIMER PORTB 4 BITS PORTC 4 BITS CTL REG PORTD 4 BITS 8 BITS TIMER PIERONI 4 p Up counter 4096 X 16 BITS PORTE 4 BITS DATA RAM TIMER 160 X 4 BITS INTERRUPT PORTF 2 BITS SH69P25 PORTA 0 3 PORTB 0 3 PORTC 0 3 PORTD 0 3 PORTE 0 3 PORTF 0 1 SH69P25 Pin Description Normal Mode Pin No Designation Descriptions 27 28 1 2 PORTE 0 3 Bit programmable I O 26 3 PORTF 0 1 Bit programmable I O 24 25 4 5 PORTA 0 3 Bit programmable I O TO Timer Clock Counter input pin Schmitt trigger input RESET Reset input active low Schmitt trigger input GND Ground pin Bit programmable Vector Interrupt Active rising or falling edge by system register setup
11. Read Operation High nibble first Followed by Low nibble Load Reg L Load Reg H 8 bit timer counter j 3 Latch Reg L SH69P25 5 2 Timer0 Interrupt The timer overflow will generate an internal interrupt request when the counter counts overflow from FF to 00 If the interrupt enable flag is enabled then a timer interrupt service routine will proceed This can also be used to waken the CPU from the HALT mode 5 3 Timer0 Mode Register The timer can be programmed in several different prescaler ratios by setting the Timer Mode register TMO The 8 bit counter counts prescaler overflow output pulses The timer mode registers TMO are 3 bit registers used for timer control as shown in table1 These mode registers select the input pulse sources into the timer Timer 0 Mode Register 02 Prescaler Divide Ratio Ratio N 12 2048 initial 129 512 p 128 32 8 4 2 5 4 External Clock Event as Timer0 Source When an external clock event input is used for the TMO it is synchronized with the CPU system clock Therefore the external source must follow certain constraints The output from the TOM multiplex is TOC It is sampled by the system clock in instruction frame cycle Therefore it is necessary for the TOC to be high at least 2 tosc and low at least 2 tosc When the prescaler ratio is set to 2 the TOC is the same as the system clock inpu
12. Timer Enable Enable the watchdog timer Disable Disable the watchdog timer 11 3 LVR Off Disable the LVR function On Enable the LVR function 11 4 LVR Voltage 4V Generate an internal reset signal when Vpp lt 4V if LVR enable 2 5V Generate an internal reset signal when Vpp lt 2 5V if LVR enable 11 5 Osc 32k 2M The Oscillator frequency is between 32768Hz and 2MHz 2M 4M The Oscillator frequency is between 2MHz and 4MHz 16 SH69P25 Instruction Set All instructions are one cycle and one word instructions The characteristic is memorv oriented operation Arithmetic and Logical Instruction Accumulator Tvpe Mnemonic Instruction Code Function Flag Change ADC X B 00000 Obbb xxx xxxx AC lt CY ADCM X B 00000 1bbb xxx xxxx AC Mx Mx AC CY CY ADD X B 00001 0bbb xxx xxxx AC lt CY ADDM X 00001 1bbb xxx xxxx AC Mx Mx AC CY SBC X B 00010 Obbb xxx xxxx AC lt AC CY CY SBCM X B 00010 1bbb xxx xxxx AC Mx Mx AC CY CY SUB X B 00011 Obbb xxx xxxx AC lt Mx 1 CY SUBM X B 00011 1bbb xxx xxxx AC Mx Mx AC 1 CY EOR X B 00100 Obbb xxx xxxx AC lt Mx AC EORM X B 00100 1bbb xxx xxxx AC Mx Mx AC OR X B 00101 Obbb xxx xxxx AC lt Mx ORM X B 00101 1bbb xxx xxxx AC Mx Mx AC AND X B 00110 Obbb xxx xxxx AC lt Mx amp AC ANDM X B 00110 1bbb xxx xxxx AC Mx Mx amp AC 0 gt AC 3
13. ammable I O so only the input port can generate an external interrupt When PBCFR is set to 0 any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an interrupt request And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD When PBCFR is set to 1 any one of the PORTB and PORTC input pin transitions from GND to VDD will generate an interrupt request And further rising edge transition would not be able to make interrupt request until all of the pins return to GND The port interrupt function block diagram is shown below PBOUT 3 PB 3 PBOUT 2 PB 2 PBOUT 1 PB 1 PBOUT 0 PB 0 PCOUT 3 PC 3 PCOUT 2 PC 2 PCOUT 1 PC 1 PCOUT 0 PC 0 PBOUT 3 PB 3 PBOUT 2 PB 2 PBOUT 1 PB 1 PBOUT 0 PB 0 PBCFR gt D PORT INTERRUPT PORTINT gt DETECT Iu gt PCOUT 3 PC 3 PCOUT 2 PC 2 PCOUT 1 PC 1 PCOUT 0 PC 0 13 SH69P25 7 Interrupt Two interrupt sources are available on SH69P25 interrupt Port B C interrupts Falling Rising edge 7 1 Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 and 01 of the system register They can be accessed or tested by the program Those flags are cleared to 0 at initialization by the chip reset Address Remarks 00 Interrupt enable
14. can be set at 1 bit page register for higher than 2K 1 2 ALU and CY ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustment for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decision BAO BA1 BA2 BA3 BAZ BNZ BC BNC Logic Shift SHR The Carry Flag CY holds the ALU overflow which the arithmetic operation generates During an interrupt servicing or call instruction the carry flag is pushed into the stack and retrieved back from the stack by the RTNI instruction It is unaffected by the RTNW instruction 2 OTP ROM SH69P25 1 3 Accumulator AC The Accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data transfer between the accumulator and system register or data memory can be performed 1 4 Table Branch Register TBR Table Data can be stored in program memory and can be referenced by using Table Branch TJMP and Return Constant RTNW instructions The Table Branch Register TBR and Accumulator AC is placed by an offset address in program ROM TJMP instruction branch into address PC11 PC8 X 28 TBR AC The address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bitO into AC 1 5 Data Pointer The Data Pointer can indirectly addres
15. eristics Vpp 3 0V GND 0V TA 25 unless otherwise specified Parameter Symbol Condition Oscillator Start Time Tosc1 Crystal Osc 32 768kHz Vpp 3 0V RESET pulse width low TRESET Vpp 3 0V WDT Period TWDT Vpp 3 0V Frequency Stability RC A F F Low Voltage Reset Electrical Characteristics Vpp Parameter RC oscillator 1MHz F 3 0V F 2 7V F 3 0V 2 4 5 5V GND OV TA 25 Fosc 4MHz unless otherwise specified Condition LVR Voltage 1 LVR enable LVR Voltage 2 LVR enable 20 SH69P25 AC Characteristics N Prescaler divide ratio ns High Pulse Width 1 2 Tiw Low Pulse Width 1 2 Tiw Timing Waveform TO Input width Tey 40yN TO Input Waveform 0 4 TIWH gt lt TIWL gt Built in RC Oscillator Only use for Watch Dog RESET osc WDT Built in RC it 1 gt TwoT 21 SH69P25 Typical RC Oscillator Resistor vs Frequency Vpp 5V for reference only 5V RC Frequencv 10000 00 N m 1000 00 o LL 10
16. flags 01 Interrupt request flags When IEx is set to 1 and the interrupt request is generated IRQx is 1 the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources When an interrupt occurs the PC and CY flag will be saved into stack memory and jump to interrupt service vector address After the interrupt occurs all interrupt enable flags 1 are reset to 0 automatically so when IRQx is 1 and IEx is set to 1 again the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources 1 2 3 4 5 Instruction Instruction Instruction Execution Execution Execution 12 N Vector Generated Fetch Vector address Interrupt Generated Interrupt Accepted Stacking Reset IE X Start at vector address During the SH6610C CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences If the interrupt request is ready and the instruction of execution N is IE enable then the interrupt will start immediately after the next two instruction executions However if instruction 11 or instruction 12 disables the interrupt request or enable flag then the interrupt service will be terminated Interrupt Servicing Sequence Diagram Inter
17. g Plane a 181 2 pu _ 0 018 0 004 0 46 0 10 s e eem 0 060 0 004 1 52 0 10 EBEN 0 010 0 004 0 25 0 10 EBENEN IEEE 138 m 400 Wax 3525 55858 01000010 25 05 5 58 05 Notes 1 The maximum value of dimension D includes the end flash 2 Dimension E1 does not include the resin fins 3 Dimension S includes the end flash 28 SH69P25 SOP N B 28L Outline Dimensions unit inches mm 28 15 w z 1 b 14 gt H D lt lt yke al Q P Seating Plane y See Detail F a 0 016 0 004 0 41 40 10 0 010 0 004 0 25 40 10 Lom ae 8 840 nom 0 004 0 10 Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 3 Dimension e is for the reference of PC Board surface mount pad pitch design only 4 Dimension S includes end flash 29 SH69P25 Data Sheet Version Historv Change Current limit Add In System Programming Notice for OTP Reduce operating current 9 4 Add RC Frequency Resistance diagram
18. gisters Direct addressing in one instruction can access both data memorv and svstem register The memorv allocation map is shown below 000 01F System register and I O 020 0BF Data memory 160 X 4 bits divided into 2 banks 020 07F banko 080 0BF bank1 3 1 The Configuration of the System Register Address Remarks 00 Interrupt enable flags 01 Interrupt request flags 02 Timer0 Mode register Prescaler 03 Reserved 04 Timer0 load counter register low digit 05 TimerO load counter register high digit 06 07 Reserved 08 PORTA 09 PORTB 0A PORTC 0B PORTD 0C PORTE 0D PORTF 0E Table Branch Register OF Pseudo index register 10 Data pointer for INX low nibble 11 Data pointer for INX middle nibble 12 Data pointer for INX high nibble 13 14 Reserved Bit1 PBC interrupt rising failing edge set 15 PULLEN PH PL PBCFR Bit2 PORT Pull high low set Bit3 PORT Pull high low enable control 16 PA2OUT PA1OUT PAOOUT PORTA input output control 17 PB3OUT PB2OUT PB1OUT PBOOUT PORTB input output control 18 PC3OUT PC2OUT PC1OUT PCOOUT PORTC input output control 19 PD3OUT PD2OUT PD1OUT PDOOUT PORTD input output control 1A PEZOUT PE1OUT PEOOUT PORTE input output control 1B PF1OUT PFOOUT PORTF input output control BitO TO signal edge Bit1 TO signal source 1D Reserved 1E Bit3 WDT timer reset write 1
19. illator F 5 0V F 4 5V F 5 0 19 SH69P25 DC Electrical Characteristics 3 0V GND OV TA 25C 4MHz unless otherwise specified Parameter Condition Operating Voltage Operating Current All output pins unloaded Execute NOP instruction Stand by Current HALT All output pins unloaded Stand by Current STOP All output pins unloaded LVR off If LVR on IsB2x IsB2 2uA WDT off If WDT on IsB2x IsB2 20 Input Low Voltage GND 0 2 X I O ports pins tri state Input Low Voltage GND 0 15 X VDD RESET TO Input Low Voltage GND 0 15 X OSCI Driven by external clock Input High Voltage 0 8 X VDD VDD I O ports pins tri state Input High Voltage 0 85 X VDD VDD RESET TO Input High Voltage 0 85 X Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage VDD OSCI Driven by external Clock wa a WO pons GND lt vio lt voo ul s ua ve Tu 1 s I O ports loH 7mA Vpp 3V Output Low Voltage User Notice Max Current into Vpp 100mA Max Current out of GND 150mA Max Output current sunk by any I O port 50mA Max Output current sourced by any I O port 40mA I O ports loL 8mA Vpp 3V AC Electrical Charact
20. ng the code 2 Connect the programming interface with OTP Writer and Begin Programming code 3 Disconnect OTP writer and short these jumpers when programming is finished For more detail information please refer to the OTP writer user manual 23 SH69P25 Application Circuit for reference only AP1 1 Operating voltage 5 0V 2 Oscillator Ceramic resonator 400kHz 3 TO input timer clock counter 4 PORTA F I O SH69P25 E oer OSCO RESET q PORTA PORTF AP2 1 Operating voltage 5 0V 2 Oscillator RC 400kHz 3 PORTA F I O 210KQ OSCI Tos SH69P25 OSCO 1000pF PORTA 4 7 yo PORTF AP3 1 PORTA C as scan KEY BOARD 32 keys 2 PORTD F I O 3 All input pins internal Pull high On 1 2 PBO PB1 PB2 PB3 PAO PA1 PA2 PA3 PORTF SH69P25 24 SH69P25 Weight Scale 1 Operating voltage 5 0V 2 Oscillator Ceramic resonator 4MHz 3 Port AO External interrupt input for ON OFF switch 4 Port E2 F1 A2 S1 S4 analog switch control signals that control Vi are charged or discharged by both reference voltage Vref and amplified voltage Vo The charging and discharging times are determined by the values of C1 R4 and the threshold voltage of the To input pin and the ADC resolution can be up to 8 bits 5 Other Ports Sink seven segment LED current directly O 19
21. osure to the absolute maximum rating conditions for extended affect device Storage Temperature 55 C to 125 C reliability DC Electrical Characteristics Vpp 5 0V GND 0V TA 25 Fosc 4MHz unless otherwise specified Parameter in i Condition Operating Voltage V All output pins unloaded Execute NOP instruction Stand by Current HALT MA All output pins unloaded All output pins unloaded LVR off If LVR on IsB2x IsB2 2uA WDT off If WDT on IsB2X IsB2 20uA Operating Current mA Stand by Current STOP Input Low Voltage GND 0 2 X Vpp Input Low Voltage GND 0 15 X Vpp Input Low Voltage GND 0 15 X Vpp Input High Voltage 0 8 X VDD VDD Input High Voltage 0 85 X VDD VDD Input High Voltage 0 85 X VDD I O ports pins tri state RESET TO OSCI Driven by external clock ports pins tri state RESET TO OSCI Driven by external Clock I O ports GND lt Viro lt Voo GND 0 25V A A For OSCI kQ PULL HIGH PULL LOW resistor Output High Voltage ports 10mA Output Low Voltage ports loL 20mA HA V V V V V V HA kal Parameter Symbol in Condition Oscillator Start Time 1 X tal 32 768kHz RESET pulse width low TRESET VDD 5 0V WDT Period TWDT Vpp 5 0V Frequency Stability RC A F F RC Osc
22. rupt Nesting SH69P25 8 Low Voltage Reset LVR The LVR function is to monitor the supply voltage and generate an internal reset in the device It is typically used in AC line applications or large batterv where large loads mav be switched in and cause the device voltage to temporarilv fall below the specified operating minimum The LVR function is selected bv OTP option The LVR circuit has the following functions It generates an internal reset signal when VDD lt VLVR It cancels the internal reset signal when VDD gt VLVR Here VDD power supply voltage VLvR LVR detect voltage There are two levels selected by OTP option Level 1 2 3 2 7V typical 2 5V Level 2 3 8 4 2V typical 4 0V LVR can be enabled or disabled permanently by OTP option 9 Watch Dog Timer WDT System Register 1E WDT Watchdog timer reset write 1 to reset WDT The input clock of the watchdog timer is generated by a built in RC oscillator so that the WDT will always run even in the STOP mode SH69P25 generates a RESET condition when the watchdog times out The watchdog can be enabled or disabled permanentiv bv using the OTP option To prevent its timing out and generating a device RESET condition vou should write this bit as 1 before timing out The WDT has a time out period of more than 7ms typical 18ms If longer time out periods are desired a prescaler with a division ratio of up to 1 2048 can be assigned to the
23. s data memory Pointer address is located in register DPH 3 bits DPM 3 bits and DPL 4 bits The addressing range can have 3FFH locations Pseudo index address INX is used to read or write Data memory then RAM address bit9 bito comes from DPH DPM and DPL 1 6 Stack A group of registers are used to save the contents of CY amp PC 11 0 sequentially for each subroutine call or interrupt It is organized into 13 bits X 4 levels The MSB is saved for CY 4 levels are the maximum allowed for subroutine calls and interrupts Note The contents of the Stack are returned sequentially to the PC with the return instructions RTNI RTNW The stack is operated on the first in last out basis This 4 level nesting includes both subroutine calls and interrupt requests Note that a program execution may enter an abnormal state if the number of calls and interrupt requests exceeds 4 and the bottom of the stack will be shifted out The SH69P25 can address up to 4K X 16bits words of the program area from 000 to FFF Service routine serves as the starting vector address Address Instruction Remarks 000H JMP Instruction Jump to RESET service routine 001H NOP Reserved 002H JMP Instruction Jump to TIMERO service routine 003H NOP Reserved 004H JMP Instruction Jump to PBC service routine SH69P25 3 RAM The built in RAM consists of general purpose data memories and svstem re
24. t Therefore the requirements are as follows TOH TOCH TO high time 2 2 tosc AT TOL TOCL TO low time gt 2 tosc AT Note AT 20ns When another prescaler ratio is selected the TMO is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical Then N TO TOC high time TOC low time 2 Where TO TimerO input period N prescaler value The requirement is therefore N TO gt 2tosc AT or TO gt The limitation is applied for the TO period time oniv The pulse width is not limited bv this equation It is summarized as follows 4 tosc 2AT TO TimerO period gt N SH69P25 System Register 1C 1C TOS TOE RIW TO signal edge Bit1 TO signal source TOE TO signal edge 0 Increment on low to high transition TO pin Power on initial 1 Increment on high to low transition TO pin TOS TO signal source 0 OSC 4 Power on initial 1 Transition on TO pin OSC 4 U gt TIMERO 8bits TO 1 x Built in RC Oscillator TMO 2 0 v WDT Enable OTP option WDT amp Warm Up Counter 3 WDT reset PI P Y WDT Timeout 10 6 I O Ports SH69P25 The SH69P25 provides 22 I O pins The port control register controls ON OFF of the output buffer The following sections show the circuit configuration of I O ports Every I O pin has an internal pull high p
25. ull low resistor which is controlled by PULLEN and PH PL of 15 Each of these ports contains 4 or 2 PF bits I O pins ON OFF of the output buffer for the port can be controlled by the port control register Port I O mapping address is shown as follows Equivalent Circuit for a Single I O Pin PULL EN PH PL DATA WRITE RESET DATA IN AND VDD O PIN READ CONTROL WRITE ck Q PXXOUT RESET QB RESET 2011 PULL EN PH PL OR AND 4 Do AND 11 he IL V GND gt EN SH69P25 System Register 15 1B Buz Om mw Remane PULLEN PH PL PBCFR Bit1 PBC interrupt rising failing edge set 15 R W Bit2 PORT Pull high low set Bit3 PORT Pull high low enable control s PFTOUT PFOOUT RAW PORTE inputioutputcontrol 00 PAXOUT PBXOUT PCXOUT PDXOUT PEXOUT X 0 1 2 3 PFXOUT X 0 1 1 Used as an output buffer 0 Used as an input buffer Power on initial PBCFR 1 Rising Edge interrupt 0 Falling Edge interrupt PH PL 1 Port Pull high resistor ON 0 Port Pull low resistor ON PULLEN 1 Port Pull high Pull low enable 0 Port Pull high Pull low disable 12 SH69P25 PORTB 8 PORTC Interrupt The PORTB and PORTC are used as port interrupt sources Since PORT I O is a bit progr
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