FIPSOC User Manual
Contents
1. New slave selected or CPHA 0 Pull Up slave SSN d Slave De select Slave De select Pull Up slave SSN 14 SIDSA 6 SPI Communication Process This section will be described with flow graphs how the SPI block of the Serial Communication Block would be programmed for each step initialize data transmission and flags interpretation 6 1 Initialize SCEN 1 enable SCSL 0 SPI SPI select 3 ODS 1 opendrain or ODS 0 CMOS Outputs configure SPMT 1 master or SPMT 0 slave Master Slave select WR SBCR Clear CCF RD CMREG CKO amp CK1 Configuration CPOL amp CPHA Configuration SCK SDA relationship Clear dummy flags WR CMREG gt 6 2 Flags Interpretation Write collision during transmission Transmission successfully ends Write collision before buffer were read Transmission in progress Chapter 8 Serial Communication Interface Semiconductor Design Solutions 7 2 Data Transmission Start command Send start command SCL line is pulled down sync procedure yes no Receiver bit0 1 Transmitter bit0 0 N Device address bit7 through bit1 Write dummy T Pa pej ee check status Mode select no yes Release SCL line RD CMBUF gt word X2. Data transferred n bytes Ack read A master reads a slave inmediately after the first byte e Clock Synchronization Direction and Ack Master devices generate the serial clock signal in Data transferred lt depends on RW bits O Data transferred f 2 nbytes Ack a bytes Ack the SCL line Since the 2 wire lines are pull up lines any devices in the bus can alter the SCL S Slave address RW A Data A A Sr Slave address RW A Data A A P signal by obliging a low level in the line Slow slave devices may use this characteristic to hold the low period of the serial clock leaving the master From master to slave A Acknowledge SDA low device in a high wait state When all the devices release the SCL line the low to high transition will Combined format From slave to master A Not acknowledge SDA high occur and the master device will continue its 5 Start Condition function see figure 2 7 P Stop Condition Different slow operations can be handled thank to this bus specification pull up resistor such as interrupt requesting on microcontrollers data and acknowledgement preparations long time needed to store information and so on Sr Repeated Start Condition Fig 2 5 Possible Data Transfer Formats 2 3 Arbitration wait state start condition Special situations will appear when more than one Ze sage Maste
3. transmission if the bus is free is accomplished Chapter 8 Serial Communication Interface Semiconductor Design Solutions with WCOL set followed by a write access to the SPI register to clear the bit CPOL Clock Polarity When the clock polarity bit is cleared and data is not being transferred a steady state low value is produced at the SCK pin of the master device Conversely if this bit is set the SCK pin will idle high This bit is also used in conjunction with the clock phase control bit to produce the desired clock data relationship between master and slave see figure 3 2 CPHA Clock Phase The clock phase bit in conjunction with the CPOL bit controls the clock data relationship between master and slave The CPHA bit selects one of the two fundamentally different clocking protocols When CPHA 0 the shift clock is the OR of SCK with SSN When CPHA 1 the SSN pin may be though of as a simple output enable control refer to figure 3 2 5 3 SCMBUF Serial Communication Buffer Register The Serial Communication Buffer Register SFR 9F CMBUF is used to transmit and receive data on the serial bus Only a write to this register will initiate transmission or reception of another byte and this will only occur in the master device A completion of transmitting a byte of data is signaled by the CCF flag bit in both master and slave modes Depending on bit SCIS of the SBCR register SFR 9D the internal circu
4. BMST bit in SBCR is only used during the boot sequence CK1 CKO SPI Clock Rate Selects These two rate bits select one of the four baud rates to be used as SCK if the SPI interface block is a master however they have no effect in the slave mode See Table 5 6 pcre te 10 fosc 32 500 KHz fosc 64 250 KHz Table 5 6 SPI serial clock frequencies MODF Mode Fault flag error The mode fault flag indicates that there may have been a multi master conflict for SPI bus control The MODFflag is normally cleared and is set only when the master device has its SSN line pulled low Any write to the buffer register is ignored while this flag is set Clearing the MODF bit is accomplished by reading the SPI register with MODF set followed by a clearing write to this bit in the SPI register WCOL write collision flag error The WCOL bit is set when an attempt is made to write to the CMbuffer register while data transfer is taking place A transfer is said to begin and end when v CPHA is zero A transfer is said to begin when SSN goes low and the transfer ends when SSN goes high after eight clock cycles on SCK v CPHA is one A transfer is said to begin the first time SCK becomes active while SSN is low and the transfer ends when the SPIF flag gets set after eight cycles of SCK Clearing the WCOL flag is accomplished by reading the SPI register Chapter 8 Serial Communication Interface S ID S A Semiconductor Des
5. as shown in Figure 5 5 SCK MOSI MISO and SSN lines are located in bits 7 through 4 of the general purpose port respectively Note that SSN is always an input SCK is always bi directional MOSI and MISO lines directions depends on the operating mode selected in the SPI interface block Serial Comm Block 2 wire block E SCL OOT buffer 2 LINT add reg A 38 2 w reg S U y P1 5 Fig 5 4 General Purpose Port if 2 wire block enabled The driving configuration of the general purpose port can be selected from either open drain or CMOS levels driven by setting or clearing bit 2 of the Serial Boot Control Register see below Only the two most significant bits of the general purpose port is open drain driven no selection is allowed when the 2 wire interface block is selected and the Serial Communication block is enabled too Chapter 8 Serial Communication Interface Semiconductor Design Solutions The CCF flag is set by the internal state machine after nine cycles of the serial clock line Clearing the CCF bit is accomplished by reading the 2 wire register with the CCF set When the 2 wire bus is free the CCF flag is set 2MST 2 wire Master The master flag indicates if the device controls or is suitable to control the 2 wire bus By default that is when the b
6. block amp gt _2 wire register 8 P S Pa bo a F SFR 9C 50158 gt plie butter 2 gt 5 SCIS WNT device address Teg 5 5 SFR 9F CMBUF lt 1 5 SPI register gt lt L sPl buffer M SPI block lt 4 SFR 9D SCISR Boot Control reg lt gt On reset lt SFR 9E CMBUF DDGP conf block as Control block lt _ mP 8051 lt Fig 5 2 Serial Registers Organization 5 1 SBCR Serial Communication Boot Control Register This register is accessed through position 9D of the SFR memory area SCEN SCSL BMST SCIE GOE ODS IREN bit configured on reset SCEN Serial Communication Enable bit If SCEN is set the serial communication block is enabled If so the corresponding bits of the general purpose port change their function These bit are different depending on the interface protocol selected If SCEN 0 the serial communication interface block is disabled and the general purpose port will be full controlled by the SFR 9E DDGPR and 90 P1 of the 8051 core See figure 5 3 SCIS Serial Communication Interface Selection When SCEN 1 if this bit is set the 2 wire interface is selected otherwise the SPI block will be enabled When the 2 wire interface block is chosen the two most significant bits of the general purpose port bits GPP 7 and GGP 6 will change its function to provide the two lines of the 2 wire
7. gt am gt lt a da DAMERNA i i i z5 it ola er F l 1 I et 0 0 0 as 7 diti start condition data valid change of data stop condition allowed Fig 2 1 Bit transfer on the 2 wire interface e Bus free Both SDA and SCL are bi directional lines connected to a positive supply via a pull up resistor see figure 2 2 When the bus is free no transfer between any devices is in progress and both lines stay high All SDA and SCL outputs of any devices connected to the bus must be open drain or open collector driven 1 Overview The Field Programmable System On Chip FIPSOC constitutes a new concept in system integration It provides the user with the possibility of integrating a microprocessor core along with programmable digital and analog cells within the same integrated circuit This chip can be considered as a large granularity FPGA with a FPAA Field Programmable Analog Array and a built in microprocessor core that does not only act as a general purpose processing element but also configures the programmable cells and their interconnections Therefore there is a strong interaction between hardware and software as long as signal values and configuration data within the programmable cells are accessible from microprocessor programs This chapter describes the Serial Communication Block integrated on the FIPSOC system It supports two serial communication interfaces a 2 wire protocol and an SPI interfac
8. in a slave device It is one of the two lines that transfer data in one direction e Serial Clock SCK The serial clock is used to synchronize data movement both in and out of the device through its MISO and MOSI lines The master device generates this signal so it is configured as an output in a master device and as an input in a slave device e Slave Select SS The slave select input line is used to select a slave device It is active with low level and it must stay low during the transmission The SS line on the master must be tied high The most significant bit is first sent in both MISO and MOSI lines MASTER SLAVE Buffer Register 1 Buffer Register ISB 1 8 bit Shift Register e a O ISB 8 bit Shift Register a v Y Internal Internal Control Control p o Fig 3 1 SPI Block Diagram 3 2 Bit Transfer Data transmission is controlled by the SCK signal For each cycle sent through the SCK line bits from the master device using the MOSI line and bits from the slave through the MISO line are simultaneously SPI Clock Generator Chapter 8 Serial Communication Interface Internal Data Bus Semiconductor Design Solutions SIDSA Boot Control Register On reset configuration Description Boot Control Serial Communication Enable If 1 serial communicatio
9. to the master This implies full duplex communication with both data out and data in synchronized with the same serial clock A read operation is realized by sending a word through the MOSI line that is generating the clock signal in the SCK line 3 3 Data Transfer The whole SPI system master device bus and slave device works like a system consisting of two shift registers interconnected The byte transmitted from the master shift register is replaced by the byte received from the slave On the other side the byte received from the master in the slave shift register replaces the previous word which is sent to the master device via the MISO line see figure 3 1 The SPI devices are double buffered on read but not on write Thus if a write is performed during data transfer stored data will be erased and both transmitted and received data would be corrupted In order to save the data received every eight cycles of the SCK the shift register is copied to the buffer register 3 4 Serial Clock Control Byte exchange takes place during eight cycles of SCK After any exchange operation the stored data is transferred to the buffer register A byte transmission is begun when the master device writes on the shift register This operation starts an internal counter which generates eight cycles in the SCK line Four possible timing relationships may be chosen for the transmission depending on the synchronization edge and level o
10. I device Master Slave configuration can be on reset set Chapter 8 Serial Communication Interface lt a S ID S A Semiconductor Design Solutions emn eror o apua Busy crna o apna Table 8 3 SCMREG Register AD BUFREG ADDRESS 6 0 AD 14 8 Table 8 4 BUFREG and 2 wire ADDRESS Register Chapter 8 Serial Communication Interface 18
11. Status Register Depending on bit SCIS of the SBCR register SFR 9D the internal circuitry will select the 2 wire register or the SPI register If SCIS is set operations realized in location 9C of the SFR map will affect to the 2 wire register otherwise the SPI register will be accessed 2 wire Register This register is accessed through position 9C of the SFR memory area if SCIS of the SBCR is set CCF 2MST SDRC CKO ID ERR CMD BUSY 1 1 1 7 1 1 0 0 bit configured on reset CCF Communication Complete flag This bit is set by hardware when a word transmission is completed If CCF flag is 0 the block is transmitting or receiving or is ready to transmit or receive Chapter 8 Serial Communication Interface Semiconductor Design Solutions sof NN SDA CK0 1 X ie K SDA CK0 0 X X 14 SDA line hold time SDA line hold time CKO 0 CKO 1 Fig 5 8 SDA hold time in a slave device ID Device address identification When the ID flag bit is set and of course the serial communication block is enabled and the 2 wire block is selected the block responds to the bus stimuli Otherwise if the ID 0 the 2 wire interface block enter to its idle mode waiting to a new start command as depicted from figure 5 6 When the block is in the waiting mode bus free both SDA and SCL line are released and no action will be produced or received The ID flag be
12. X y No device Master Master Slave Slave Slave not addressed Transmitter Receiver Transmitter Receiver addressed 15 SIDSA 7 2 wire Communication Process Note 2 wire serial interface is not available in device 8x12 of the FIPSOC family In this section will be described how the 2 wire block of the Serial Communication Block would be programmed for each step initialize data transmission flag interpretation A flow graph of the 2 wire communication process is also provided 7 1 Initialize SCEN 1 enable SCSL 1 2 wire yes Clear CCF hange address no Write Address WR SBCR RD CMREG lt _ WR CKO yes Configuration SCK rate select WR CMREG Chapter 8 Serial Communication Interface lt i D S A Semiconductor Design Solutions Send Receive Word 7 3 Flow Graph for the Communication Process Word Release SCL line Suppose to be master Start Condition detected Send Start Command Slave yes Selected Change TX RX mode Ts the slave identified RX TX another no Leave bus unlocked Command detected Start condition detected SCL line pull down sync procedure Dummy word in transmitter device no Read Word RD CMBUF Send Stop Command Stop command 7 4 Flags Interpretat
13. ZG SIDSA Chapter 8 Serial Communication Interface FIPSOC User s Manual Semiconductor Design Solutions SIDSA Serial Communication Interface This bus interface supports serial data transmission using two lines between the devices connected to it The two wires are used to one for data serial data SDA and one for the clock signal serial clock SCL Multiple devices can be connected to the bus and can operate as either a transmitter or receiver The transfer on the bus is initiated and controlled by a master device that generates the clock signal the other devices which send or receive data are known as slaves Each device hanging in the bus is recognized by an address Any master device must first identify the desired slave by sending its address through the 2 wire bus and configure it as either a transmitter or receiver read or write operations respectively The 2 wire interface is multi master That is more than one device are capable of controlling the serial clock of the bus 2 1 The transmission is controlled by the serial clock SCL The SCL line is used to control each data bit transferred The data on the SDA line must be stable during the high level of the SCL line Level of the SDA line can only change while the clock pulse on SCL is low Data changed during SCL high periods will indicate a start or stop command see figure 2 1 Bit Transfer bus free bus busy _ bus free 2
14. allowed without releasing the bus Various combinations of read write format are possible in the same transmission session These formats are described below and shown in figure 2 5 e Master transmitter The master device transmits data to the slave receiver The transfer direction is not changed and the acknowledge bit is always set by the slave This format is used in write operations e Master receiver The master device reads data from the slave after the first byte transmitted The transfer direction changes after the first byte that is the address word transmission has master slave direction while any other word is slave master transmitted The acknowledge bit is always set by the receiver Due to this fact only the first 2 2 Data Transfer After a start condition the master device must send a slave address This first word has two purposes firstly it is used to identify the slave device in the bus secondly it is used to establish the transfer direction of the communication that is configure the slave device as receiver or transmitter The first word is seven bits long address field followed by an eight bit operation field which is the R W command select bit A read operation is initiated if this bit is high otherwise a write operation is initiated see figure 2 4 The slave addressed must pull down the ninth bit as mentioned before see figure 2 3 If the master device do not detect a zero in the ninth clo
15. and has been executed the BUSY flag will keep set and the 2 wire block will pull down the SCL and the SDA lines v If a stop command is already executed the BUSY flag will be cleared and both lines will be released high Note that a command is executed by writing in the 2 wire register CKO bit will be overwritten during this access BUSY Bus busy status flag This bit accessed with the CMD bit is used in write to send the start and stop commands to the 2 wire bus and is used in read access to control the bus status If BUSY 1 the bus is not free otherwise bus is free When BUSY 0 if the bus is occupied the buffer register is accessed the device address register is accessed otherwise 2 wire Register flags Step msr src m Bus free waiting mode Master device during 1 byte Slave device during 1 byte Non addressed slave standby mode Addressed Transmitter slave Addressed receiver slave Table 5 4 2 wire block mode configuration ERR 2 wire transfer error The flag error indicates if a non successful transmission is produced If ERR 1 an error has occurred Otherwise there is not any problem in the transmission up to the current step The ERR flag represents different error situations depending on when they are produced 2 wire Register flags Error ccr 1 een Device has not been 1 addressed SPI Register This register is accessed through positi
16. aster send address and op mode 0 slave receiver slave transmitter slave mode Fig 5 6 Start up 2 wire interface process master receiver 0 1 master transmitter CKO Serial Clock frequency Configuration The frequency of the serial clock signal may be configured as shows in table 5 3 The serial clock frequency is compatible to other 2 wire interfaces when CKO 1 This bit configure the 2 wire interface block clock as depicted from Figure 5 7 Frequency for fosc 160 100 KHz Table 5 3 2 wire serial clock frequencies Therefor the CKO bit affects not only to the period of the serial clock SCL but also modified the time responses and SDA transitions times see figure 5 8 Due to this fact bit CKO affects to both master and slave modes frequency and transition times respectively fosc 16 2 wire interface block fosc 160 CKO Fig 5 7 Start up 2 wire interface process Chapter 8 Serial Communication Interface master mode xtal Semiconductor Design Solutions by writing in the 2 wire register with both CMD and BUSY bits set v Producing a stop condition in the bus to stop a transmission and leave the bus free is accomplished by writing in the 2 wire register with CMD 1 and BUSY 0 The CMD flag bit will keep its value set to one during the execution of the command After this it will be cleared by hardware v If a start comm
17. at it has received each word During this cycle the transmitter has to release the SDA line to receive the confirmation from the receiver bus free fr 5 bus busy i 0 i 1 i LS aa X 7 not acknowledge SCL out by transmitter TEE SDA out by transmitter Ss Se SDA out by i receiver acknowledge i start condition Fig 2 3 Acknowledge of receiver on the 2 wire bus SCL in 5515811 _ _ _ _ 1 i i 1 l i L SCL out SDA in SCL ou SDA in a 1 1 0 I 1 0 0 Li 0 1 anny SDA out S 1 aan SDA oui 4 1 Fig 2 2 Connection of devices to the 2 wire bus e Start Condition A high to low transition in SDA line with SCL high is a start condition see figure 2 1 Only the master device may generate this situation The bus is considered to be busy after a start condition A start command always precedes any command in the bus e Stop Condition A low to high transition in SDA while SCL is high is interpreted as a stop condition Bus busy last data word stop conditioi N acknowledge cycles Ist data word start condition address word address field operation field Fig 2 4 Data transfer on the 2 wire interface The number of bytes that can be transmitted between the start and the stop condition is unrestricted Data transfer is always finished by an stop command see figure 2 4 In other words several start commands are
18. ated in the usage have different SFR map These registers depending on the boot register configuration described further in this section Their values after reset depends on the levels set in a of the FIPSOC chip on reset in out pads few configuration The registers used to control the Serial Communication block are described below Serial Comm Register On Reset configuration Address Name Bit Description 9C SCMREG Serial Communication Register 2 wire SPI SCMREG 7 CCF Communication complete flag If 1 data is transferred if 0 transfer is in progress 2 wire Register SPI register SCMREG 6 MASTER 2MST SPMT SCMREG 5 SDRC CKI1 SDRC l send CK1 TX frec 0 receive select bit 1 SCMREG 4 CKO 1 100KHz CKO TX frec 0 1MHz select bit 0 SCMREG 3 ID MODEF _ ID this bit is set MODF if the device is multimaster addressed fault SCMREG 2 ERR WCOL ERR set if error WCOL write during TX collision SCMREG 1 CMD CPOL CMD 1 if cmd CPOL clock in progress polarity SCMREG 0 BUSY CPHA BBUSY set if CPHA clock bus busy phase blocks are 2 wire interface block which generate all the signals needed to the full implementation of the protocol The block is controlled by three registers mapped through locations of the SFR map of the 8051 It also includes a flag in a status SFR C4 ISR which would interrupt the mP8051 if enabled SPI interface block which generate the sig
19. cause an interrupt through the PLHW1 interrupt source of channel 0 of the External Interrupt Controller Block see EIC Block Document for further information If SCIE 0 no interrupt signal will be generated and a low level will be set in the wire The interrupt is produced either if a word is successfully transmitted or if any error is produced in any step of the transmission Table 5 1 shows the interrupt sources SCIE SCIS Interrupt sources ce 0 SPI CCF MODF WCOL 1 2 wire CCF ERR Table 5 1 SFR Locations of the breakpoints GOE Global Output Enable If GOE is cleared all the outputs of the cells and all the pad cells of the Programmable Logic core will be disabled That is none of any of the cells will drive its outputs This signal is routed to the whole FPGA to disable every single DMC output before chip configuration The flag can be set either from software of from hardware By default this bit is 0 General Purpose ZA SIDSA Serial Comm Block disabled IN OUT SELECT Open Drain CMOS t General Purpose Port DDGP 8051 lt Decod SBCR I Fig 5 3 General Purpose Port if Serial Comm Block disabled Otherwise if SCIS 0 the SPI block is selected and the most significant nibble of the general purpose port will change its function to communication purpose
20. ck cycle no device has been addressed The master must then re try to start a communication or release the 2 wire bus The first action would be done by sending a different address after a new start condition The second one will be done by producing a stop condition Chapter 8 Serial Communication Interface S ID S A Semiconductor Design Solutions acknowledge bit is set by the slave receiver start condition Data out 1 slave receiver behavior behavior v e Combined format It is used to change the Daou device TNU K i losing arbitration direction of a transfer or change the slave selected without releasing the 2 wire bus During a change See of direction the Start Condition and the Slave address are both repeated but with the operation bit reversed Fig 2 6 Arbitration procedure on the 2 wire interface Data transferred n bytes Ack 5 In other words re starting is not needed after the z ena O DE 5 mwe Wale multi master conflict is arbitrated If a master that loses the arbitration can also behave as a slave it is Master transmitter addresses a slave receiver Transfer direction is not changed possible that the master device would like to establish a communication with it In this case the i losing master must change to its slave receiver s Slave address rw A Data R Data Alp mode in order to acknowledge the addressing call from the winning master
21. e The 2 wire interface supports multi devices serial data communication using two lines The 2 wire subblock can be configured as either a master device or a slave device The block is identify by an address which can be set via software The SPI interface is a synchronous interface which allows several devices to be interconnected Two wires are required for data to obtain full duplex transfer communication A third line is used for clocking purposes The SPI subsystem supports different communication rates and can be configured to be both master or slave The Serial Communication Block would be programmed by the software However it also supports on reset configuration hardware configuration in order to provide more flexibility to the FIPSOC boot procedure 2 2 Wire Serial Interface Note 2 wire serial interface is not available in device 8x12 of the FIPSOC family Chapter 8 Serial Communication Interface th clock pulse for acknowledge Semiconductor Design Solutions see figure 2 1 After the stop condition the bus is considered to be free and a high level must be set in both SDA and SCL lines e Acknowledgement All address and data words are serially transmitted through the SDA line in 8 bit words most significant bit first Each byte transmitted is followed by an acknowledge bit set by the receiver The receiver must pull down the SDA line during the 9 clock cycle to acknowledge th
22. e bus it will automatically changes its waiting state mode master transmitter to the slave receiver mode to allows the master device to SIDSA ODS Open Drain Selection This bit affects the driving configuration of the general purpose port If this bit is cleared the general purpose port electrical characteristics will be normal CMOS inputs outputs If this bit is set the general purpose block will be open drain driven If the 2 wire interface block is selected no selection is possible in the two most significant bits of the port since the 2 wire bus requires an open drain driving pads IREN Internal ROM Enable If IREN is set locations 0000 through 001F will be mapped in the internal read only memory Otherwise the mP8051 will fetch the instructions from an external memory This bit is set on reset by hardware and it can be modified via software during the program execution BAUD SCI Baud Rate This flag is used by the on chip boot program to configure the serial interface routine if the FIPSOC is set to the serial interface boot mode so this flag has no effect in any other block Its value is set when the reset signal is active If BAUD 1 and the SCI boot mode is set the boot program is called to configure the serial port of the 8051 to work at 3205 1 baud if a typical 16 MHz crystal is used fosc 4992 otherwise if BAUD 0 fosc 1536 will be used 10416 6 bauds 5 2 SCMRKEG Serial Communication
23. f the clock Both master and slave devices must operate with the same synchronization for a right transmission A bit transfer is made by placing data on the MOSI and MISO lines a half cycle before the active clock edge internal strobe in figure 3 2 ss CPOL 0 CPHA 0 soka LILA LJ CPOL 1 CPHA 1 SCK4 MISO MOSI MSB data capture Fig 3 2 Synchronization Clock Timing Diagram Internal strobe for Internal Data Bus a ea is used to recognize any device connected to the bus slave select signal The transmission between the master device and the slave device selected is realized using two unidirectional lines A read operation is always accompanied with a write operation talk about receiver and transmitter devices has no sense in this interface 3 1 Signal Description The four basic SPI signals are MISO MOSI SCK and SS They can be described as follows as shown in figure 3 1 e Master in Slave out MISO this signal is configured as an input in a master device and as an output in a slave device It is one of the two lines that transfers serial data in one direction When multiple slave devices are connected to the SPI bus this output must be placed in the high impedance state if the slave is not selected e Master out Slave in MOSI The MOSI line is configured as an output in a master device and as an input
24. figuration Tables 8 2 8 3 and 8 4 list the correspondence between the pads of the chip and the bits on the Serial Communication Block registers Cse o REN Table 8 2 SBCR register 17 3 Command word status 2 wire Register Interpretation 000x 1101 Arbitration lost eee 000x 0101 Slave device not addressed O 11xx 1101 Acknowledge error No device addressed 11xx 1001 Command successfully transmitted and a device is addressed 4 Transmission status 0x01 1101 TX error false zero sent 5 Stop Command 2 wire Register Interpretation Stop condition executing Stop command executed 8 On Reset Configuration The FIPSOC chip has been designed to auto boot after reset In order to bring more flexibility to the boot process different boot modes and configurations are supported The information needed in the boot sequence is obtained from the external system through the input output cells The values set in some of the pads are captured in the reset condition and stored in the Serial Communication Block Registers The program boot later uses these values and configures the rest of the chip The boot modes supported are e 2 wire boot sequence the Serial Communication Block is configured as a 2 wire device Both address device and master slave configuration can be on reset set e SPI boot sequence the Serial Comm Block is configured as an SP
25. haves as follows Bus free by default any device hanging in the 2 wire bus can be addressed Due to this fact the 2 wire block must be listening during the first word if it is enabled In other words the 2 wire block is addressed at least during the first word transmission 7 After the first byte After the exchange of the command word the block will keeps the ID flag bit set if it is configured as master or the master device has addressed it If the block configured as a slave is not addressed the ID flag will be cleared by hardware Both lines will be left in high impedance and entered in the standby mode Start and stop conditions Either the start or the stop commands restart the communication between the 2 wire master and the sleeping device Any of this command will take out the 2 wire block from its standby mode and will change the ID flag to 1 Table 5 4 describes the flag configuration for any of the steps depicted from figure 5 6 10 SIDSA address it This process is shown in the flow graph of figure 5 6 After the first byte transmission called the command word the 2 wire interface block will change to one of the two receiver or transmitter mode to operate during the rest of the communication see table 5 4 Start condition yes Wait for bus free slave receive add and op mode Ose itration yes m
26. ign Solutions Note that the device address configuration is only available if bus is free that is if a transmission is in progress between any device hanging on the bus the 2 wire address of the block cannot be configured SPI buffer Register This register is accessed through position 9F of the SFR memory area if SCIS of the SBCR is cleared Transmission is initiated when master writes in this register Received data can be read from the buffer register after the CCF flag is set 5 4 DDGPR Data Direction Register This registers sets the data direction of the general purpose port In conjunction with SFR 90 P1 data is sent or received to from the external system The most significant nibble is used for communication purpose as mentioned If the Serial Communication block 15 enabled the corresponding bits of the DDPGR register will be ignored and those pins will be internally configured see figures 5 3 to 5 5 If a bit of the DDGPR is set the direction of the corresponding bit of the general purpose port will be configured as input Otherwise the output data direction will be selected Chapter 8 Serial Communication Interface 13 Semiconductor Design Solutions 6 3 Data Transmission Slave Select Pull Down slave SSN use GPP 3 0 WR DDGPR WR P1 3 0 Send Word WR CMBUF Execute only if e first word CPHA 0 Check Status RD CMREG Se Read Word Error Routine
27. ion Depending on the step of the communication the flags bit would be interpreted as follows see flow graph diagram 1 Initiate 2 wire Register Interpretation yes End of transmission 2 Start Command Relaese both SDA and SCL lines Set default values 2MST 1 BUSY 0 ID 0 SDRC 1 xxxx x 100 If BUSY is cleared after start command is executed a device in the bus has sent a stop command Chapter 8 Serial Communication Interface 16 Semiconductor Design Solutions Za SIDSA e SCI boot sequence the Serial Communication is disabled and the 8051 serial interface is used Two clock rates can be selected on reset e External Parallel Memory The internal memory is deselected The program instructions are fetched from an external memory using ports 0 and 2 of the 8051 The pads used to load the defaults values of the registers and the boot mode are e BT1 BTO These two inputs are used to select the boot mode as depicted from Table 8 1 0 9 2 wire boot mode SCI boot mode External Memory mode SPI boot mode Table 8 1 Boot modes supported e AD 15 8 The addresses port is sampled in a high to low transition of the reset signal to configure the default values of the Serial Communication Block Registers The direction of this port is set as input only if the reset signal is active otherwise the port has output direction Registers Con
28. itry will select the 2 wire block or the SPI one If SCIS is set operations realized in location 9F of the SFR map will affect to the 2 wire buffer or the device address register otherwise the SPI buffer register will be accessed 2 wire buffer Register This register is accessed through position 9F of the SFR memory area if SCIS of the SBCR is set and the 2 wire bus is occupied Transmission is initiated when master writes in this register Received data can be read from the buffer register after the CCF flag is set 2 wire Device Address Register This register is accessed through position 9F of the SFR memory area if SCIS of the SBCR is set and the 2 wire bus is free This register is configured on reset and is used to identify the block in the 2 wire bus Device address may be configured by software by writing the desired address in it SIDSA from the external line so the SCK bit of the general purpose port is configured as an input If the SPMT 0 the slave SPI block is selected by pulling down the SSN input This input bit 4 of the general purpose port can be permanently tied down if the block is going to behave always as an slave device or selected by the SPI master device If the SPMT is set and any device selects the block a mode fault will occur Note that this flag has different meaning than the boot master BMST bit of the SBCR register The SPMT bit configures the master or slave mode while the
29. n system I2C and SPI protocols is enabled Serial Communication Select If 1 serial communication system is configured as I2C if 0 serial communication system is configured as SPI Boot master Serial Communication Interrupt Enable If 1 enables the communication interrupt Global Output Enable If 0 it disables every output of every DMC and places all the IO pads in input state Open Drain If OD 0 the general purpose port outputs are normal CMOS outputs if 1 the general purpose port outputs act as open drain outputs Internal ROM Enable If 1 the internal ROM is mapped at locations 0000 001F of the program memory If 0 external memory is used for those locations SCI boot baud rate This bit selects the initial baud rate of the SCI port when booting from it Bit SCEN SCSL MASTER SCIE GOE OD IREN Baud Name SBCR SBCR 7 SBCR 6 SBCR 5 SBCR 4 SBCR 3 SBCR 2 SBCR 1 SBCR O Address 9D 5 Global Configuration 2 wire serial interface is not available in device 8x12 of the FIPSOC family Note The serial Communication Interface Block consist of four main blocks which control the protocol between the external serial device and the FIPSOC chip These 4 Serial Comm Interface Block SFR Note 2 wire serial interface is not available in device 8x12 of the FIPSOC family The Serial Communication Interface Block of the FIPSOC is controlled using registers loc
30. nals needed in a SPI bus protocol The block is configured and controlled by two registers mapped in the SFR memory area Control block The block sets the communication interface and is used by the boot program to obtain the configuration after reset on reset configuration On reset configuration circuitry which decodes external information set on the pads to configure the communication interface that would be used on boot Data Direction Port Register On Reset configuration Description Data Direction General Purpose Port Register For each bit of this register if 1 the corresponding pin is an input if 0 the corresponding pin is an output Bit Name DDGPR Address 9E Serial Comm Buffer Register hXX after Reset Description Communication buffer The register is used for both transmit and receive data through both I2C or SPI bus Transmit data is written to this location and receive data is read from this location Bit Name SCMBUF Address 9F Chapter 8 Serial Communication Interface External Inputs BAUD Semiconductor Design Solutions All the register are configured on reset That means that some external pads have a special function when the reset input is active The on reset configuration is later described in section 8 Figure 5 2 shows the registers organization SFR 90 P1 4 3 8 1 2 wire
31. on 9C of the SFR memory area if SCIS of the SBCR is cleared CCF SPMT CK1 CKO MODF WCOL CPOL CPHA Non acknowledge bit has been sent 1 1 An error has been produced 1 1 1 Table 5 5 Error situations bit configured on reset CCF Communication Complete flag This bit is set by hardware upon completion of data transfer between the block and the external device If CCF flag is 0 the block is transmitting or receiving or is ready to transmit or receive CMD 2 wire command bit This bit is set while start and stop commands required by the mP8051 are in progress The CMD flag is used to The CCF flag is set by the internal state machine after eight cycles of the serial clock line Clearing the CCF bit is accomplished by reading the SPI register with the CCF set SPMT SPI Master The master flag indicates if the device controls or is suitable to control the SPI bus On reset the flag is configured If this flag is set the SCK line is controlled by the SPI block and the corresponding bit of the general purpose port is configured as an output If not the serial clock must be obtained v Action send both start and stop commands to the bus Vv Status show if a sent command is finished Actually the command execution steps are as follows see BUSY flag description too v By default the CMD flag is cleared v Producing a start condition in the bus to start a
32. protocol SCL and SDA respectively as shown in figure 5 4 external system On reset the shows Figure 5 1 schematically Serial Communication Interface Block gt 2 wire G SPI Block Fig 5 1 Serial Communication Interface Block bit function selection Driving selection Internal bus Control Block Config Four Special Function Registers locations are used to access to any of the seven internal registers of the block These registers can be grouped according to their accessing address on the SFR map as described below a Serial Comm Status Register SCMREG 9C v 2 wire register It is used by the 8051 to control the protocol communication The bits of this register are for both configuring and status purposes The register is mapped to the SFR area if the 2 wire interface is selected v SPI registers It is used by the 8051 to control and receive information from the SPI block The register can be accessed only if the SPI interface is chosen b Serial Comm Buffer Register SCMBUF 9F v 2 wire buffer It is used for the data exchange and it can be accessed only if the 2 wire is enabled and the communication is in progress that is the bus is not free y 2 wire address register It is used to identify the 2 wire block device in the bus It can be accessed only when the block is enabled and the bus is free v SPI buffer register It is used for data e
33. r device clock device try to initiate a data transfer at the same time or __ devices with different speed responses are connected to Slave device clock T _ JR the bus The first situation called multi master conflict _ SCL requires an arbitration procedure the second one requires a clock signal synchronization method s EE Se e Multi master arbitration starting high starting low period period If two or more masters try to put information onto the bus the first device to produce a one when the other produces a zero will lose the arbitration Fig 2 7 Clock synchronization procedure on the 2 wire interface Note that bits transferred by the devices until that moment are equal in both transmissions so no 3 SPI Serial Interface corrupted information is sent This bus interface is a synchronous interface which allows several devices to be interconnected Separate wires are needed for data and clock Two wires are required for data to obtain full duplex transfer communication A third line is used for clocking purposes The transfer on the bus is controlled by the master device that generates the clock signal A fourth signal Chapter 8 Serial Communication Interface 4 Semiconductor Design Solutions generated When the master device transmit data the slave device responds by sending data
34. us is free this bit is set and the block would send a start command in order to get the bus control The 2 wire master bit is cleared if one of the following situations happens v A start condition is detected in the bus and no command operation has been executed v The device loses arbitration during the arbitration procedure The 2MST flag will change to high again if a stop condition is detected on the bus so the bus is left free Note that this flag has different meaning than the boot master BMST bit of the SBCR register The 2MST represents the status of the 2 wire interface block while the BMST bit in SBCR does not show any state of any subblock of the serial communication block SDRC Send Receive mode operation This bit indicates if the master or the slave device works in the transmit or the receive mode If this bit is set the device is set to be a transmitter otherwise the device will be a receiver device SDRC Operating mode reese Po sear Table 5 2 Operating modes of the 2 wire interface block The 2 wire interface block is configured as master transmitter device when the bus is free In this waiting state any device in the bus including itself can send a start command and therefor behaves as a master After the device gets the bus arbitration it must address an slave device by transmitting the word command If the 2 wire interface detects a non owner start condition in th
35. xchange between the serial communication block and the 8051 It is visible when SPI interface is selected Serial Comm boot control Register SBCR 9D wm c It has two functions firstly it selects and enable the desired communication interface protocol secondly it contains on reset information used by the boot program to configure the boot mode of the FIPSOC chip d Data Direction General Port Reg DDGPR 9E This register configures the general purpose port as an input or an output If either the 2 wire or the SPI interface is enabled the direction bits of the serial communication pads used will be ignored Chapter 8 Serial Communication Interface General Purpose Port Semiconductor Design Solutions Serial Comm Block SPI block Open Drain CMOS IN OUT SEL Fig 5 5 General Purpose Port if SPI block enabled BMST Boot Master Selection This flag is used by the on chip boot program to configure the FIPSOC chip on reset and it has no effect in any of the blocks of the Serial Comm Block Its value is set when the reset signal is active If BMST 1 master device configuration program is required during the boot process if this flag is cleared the boot program is called to execute the slave device routine SCIE Serial Communication Interrupt Enable When this bit is set the serial block would
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