Home

Epson S1D13704F00A200 Datasheet

1. QFP14 80 pin g Unit mm 0 4 n 14 0 R 12 0401 4 gt 60 41 A A 61 40 Y o o o o a Ea ef Index js 80 21 Vv 38 d l 01 2 es 5 0 5 0 18 0 05 Sy gt y ES 0 10 S 0 57 Bl e 1 0 Figure 14 1 Mechanical Drawing QFP14 S1D13704 X26A A 001 04 Hardware Functional Specification Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller Programming Notes and Examples Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document
2. z E E a gt leo a le ES a zi u z 5 ol a a 8 S ra w 3 p al w q E E a dE 2 6 A as es i 8 E 2 z 8 E 2 3 3 s a a w a o gt a 5 3 E a 2 Sl E oF Fl E SS oS 8 E sailed v HO El sal 2 E A E E a gt e re 3 3 x a 3 oe i a a as bs E bs x x lt 5 oS wx zS ZN Za i a nomad ZI raw INOA T ba le y ai ad gt 3 13 Q lo 9 a ka la 8 2 gt o 6 6 E a Capi o Fine E E a m a a z g I A O t a a zi a 3 S z S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 12 Figure 8 4 S1D13704B00C Schematic Diagram 4 of 4 1D13704 X26A G 005 03 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number X26A G 004 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representat
3. CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 bus interface 0 0 1 X SH 3 bus interface 0 1 0 X reserved 0 1 1 X MC68K bus interface 1 16 bit 1 0 0 X reserved 1 0 1 X MC68K bus interface 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 1 Generic 2 16 bit configuration for MFC5307 support 1D13704 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 03 Issue Date 01 02 12 Epson Research and Development Page 15 Vancouver Design Center 4 3 MCF5307 Chip Select Configuration Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the S1D13704 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the S1D13704 The S1D13704 only uses a 64K byte block with its 40K byte display buffer residing at the start of this 64K byte block and its internal registers occupying the last 32 bytes of this block This 64K byte block of memory will be shadowed over the entire 2M byte space The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus m
4. 1D13704 3 3V TX3912 TO Vpp CORE Vpp HA 12 0 gt AB 12 0 ENDIAN gt AB 15 13 HD 31 24 4 DB 7 0 HD 23 16 4 gt DB 15 8 System RESET gt RESETH Voo pull up CARDxWAIT le WAIT DCLKOUT See text r gt CLKI LHA 23 MFIO 10 gt WE1 LHA 22 MFIO 9 gt WEO LHA 21 MFIO 8 RD1 LHA 20 MFIO 7 gt RDO LHA 19 MFIO 6 gt CS LHA 15 13 MFIO 2 0 T RSi Figure 3 1 SID13704 to TX3912 Connection Using an IT8368E 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON Research and Development Page 11 Vancouver Design Center The Generic 1 host interface control signals of the S1D13704 are asynchronous with respect to the 1D13704 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on pixel and frame rates power budget part count and maximum S1D13704 respective clock frequencies Also internal S1D13704 clock dividers provide additional flexibility 3 2 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the 1D13704 host bus interface and a 16M byte por
5. A7 See Section 10 4 bit display data output 1D13704 Figure 11 1 2 Level Gray Shade Mode Look Up Table Architecture X26A A 001 04 Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Page 73 Vancouver Design Center 4 Level Gray Shade Mode 4 Gray Data Format 7 16 5 4 3 2 1 0 A0 BO A1 B1 A2 B2 A3 B3 Green Look Up Table See Section 10 Bank 0 2 bit pixel data 0 1 2 3 Bank 1 0 if a Bank a 3 Select 4 bit display data output Bank 2 Logic 0 gt 1 2 3 Bank 3 0 gt gt 3 Green Bank Select REG 16h bits 3 2 Figure 11 2 4 Level Gray Shade Mode Look Up Table Architecture 16 Level Gray Shade Mode 16 Gray Data Format 7166 5 4 3 2 1 0 AO BO CO DO A1 B1 C1 D1 Green Look Up Table 16x4 See Section 10 WN 0 4 bit pixel data 4 bit display data output moO Figure 11 3 16 Level Gray Shade Mode Look Up Table Architecture Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 74 Look Up Table Bypass Mode Epson Research and Development Vancouver Design Center 1 bit pixel data Ap 2 bit pixel data A Bn 4 bit pixel data An Bn Cn Dn
6. e 31 Generic Timing a ca mse a KORE A de AG ae ES a 32 Generic 2 Timing 3 cn A Ge a ae oe ge Mate She a a Aa 33 Clock Input Requirements 0 00000 eee eee eee 34 LCD Panel Power On Reset Timing 000000000005 35 Power Down Up Timing oaa aaa 36 Single Monochrome 4 Bit Panel TiMid8 a 37 Single Monochrome 4 Bit Panel A C Timing oaoa 38 Single Monochrome 8 Bit Panel TiMid8 a 39 Single Monochrome 8 Bit Panel A C Timing oaoa o 40 Single Color 4 Bit Panel Timing aoaaa ee eee 41 Single Color 4 Bit Panel A C Timing e e 42 Single Color 8 Bit Panel Timing Format l o 43 Single Color 8 Bit Panel A C Timing Format o o 44 Single Color 8 Bit Panel Timing Format 2 o o e 45 Single Color 8 Bit Panel A C Timing Format2 o oo 46 Dual Monochrome 8 Bit Panel Timing o e e 47 Dual Monochrome 8 Bit Panel A C TiMid8 o 48 Dual Color 8 Bit Panel TiMid8 e 49 Dual Color 8 Bit Panel A C TiMing e 50 12 Bit TFT D TFD Panel Timing e 51 TFT D TED A C Timing o ee ee 52 Screen Register Relationship Split Screen oo oo 64 1 2 4 8 Bit Per Pixel Display Data Memory Organization 71 2 Level Gray
7. Look Up Tables 1 bit display data output A 4 bit display data output An Bn An Bn 4 bit display data output An Bn Cn Dn gt 1D13704 X26A A 001 04 Figure 11 4 Look Up Table Bypass Mode Architecture Note In 1 bit per pixel display mode Look Up Table Bypass mode will turn off the FRM circuitry and place the S1D13704 in Black and White mode In 2 bit per pixel mode the Display Data Output values are 0 5 A and F in hex Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 11 2 Color Display Modes 2 Level Color Mode Page 75 2 Color Data Format Red Look Up Table 716 5 4 3 2 1 0 1 bit pixel data 0 AO A1 A2 A3 A4 A5 A6 A7 i See Section 10 gt 2 Bank 3 4 bit Red display data output Select 4 Logic gt 6 Red Bank Select REG 16h bits 5 4 f Green Look Up Table 0 e gt 4 2 La gt 3 Bank 4 bit Green display data output Select gt 4 4 Logic e gt 6 Green Bank Select REG 16h bits 3 2 Blue Look Up Table 0 0 e 2 Bank 3 4 bit Blue display data output Select gt 4 Logic 6 7 Blue Bank Select REG 16h bits
8. Normally unused entries Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 23 Vancouver Design Center Gray Shade Modes 1 Bpp Gray Shade Black and White In 1 bpp gray shade mode only the first two entries of the green LUT are used All other LUT entries are unused Table 4 9 Recommended LUT Values for 1 Bpp Gray Shade Address Red Green Blue SS Normally unused entries 2 Bpp Gray Shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel The remaining indices are unused Table 4 10 Suggested Values for 2 Bpp Gray Shade Index Red Green Blue Normally unused entries Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 24 1D13704 X26A G 002 03 4 Bpp Gray Shade The 4 bpp gray shade mode uses all 16 LUT elements Epson Research and Development Vancouver Design Center Table 4 11 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue 00 01 02 03 04 05 06 07 08 09 0A 0B 0c 0D OE OF Normally unused entries Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 25 Vancouver Design Center 5 Advanced Techniques This section contains information on the following e virtual display e
9. SOU ae el fe e Meals ea iT TS TA A O 31 xX X TSIZ 0 1 AT O 3 x Dlo 31 00000 valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A30 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 Do not increment address bits A28 and A29 between successive transfers the addressed device must increment th
10. 7 1 Bus Interface Timing 7 1 1 SH 4 Interface Timing Teko t2 13 l l CKIO t4 t5 E gt A 16 0 RD WR t6 t7 BS gt t8 CSn t9 t10 gt gt WEn 4 RD pt 112 t13 RDY t14 R L t15 D 15 0 write t16 t17 gt gt D 15 0 read X VALID Figure 7 1 SH 4 Timing Note The SH 4 Wait State Control Register for the area in which the S1D13704 resides must be set to a non zero value The SH 4 read to write cycle transition must be set to a non zero value with reference to BUSCLK 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table 7 1 SH 4 Timing Symbol Parameter Min Max Units fckio Bus Clock frequency 0 50 MHz Tokio Bus Clock period 1 fckio t2 Clock pulse width high 17 ns t3 Clock pulse width low 16 ns t4 A 15 0 RD WR setup to CKIO 0 ns t5 A 15 0 RD WR hold from CS 0 ns t6 BS setup 5 ns t7 BS hold 5 ns t8 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 Rising edge CSn to RDY high impedance t1 ns t11 Falling edge CSn to RDY driven 20 ns t12 CKIO to RDY low 20 ns t13 Rising edge CSn to RDY high 20 ns t14 DB 15 0 setup to 2 CKIO after BS write cycle 0 ns t15 DB 15 0 hold write cycle 0 ns
11. RD AO o BHE WE1 10 Vpp RD WR BS BUSCLK BUSCLK System RESET _____ RESET When connecting the S1D13704 RESET pin the system designer should be aware of all conditions that may reset the S1D13704 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of an 8 bit Processor to the S1ID13704 Generic 2 Interface Interfacing to an 8 bit Processor 1D13704 Issue Date 01 02 12 X26A G 013 02 Page 12 4 2 S1D13704 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13704 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the D13704 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the 8 bit processor interface The endian must be selected based on the 8 bit processor used Table 4 1 Configuration Settings Signal Low High CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian Big Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for 8 bit processor host bus interface Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus
12. Most color passive LCD panels and most single monochrome 640x480 passive LCD panels require a positive power supply to provide between 23V and 40V 1 45mA For ease of implementation such a power supply has been provided as an integral part of this design The Vpp power supply can be adjusted by R15 to provide an output voltage from 23V to 40V and is enabled disabled by the S1D 13704 control signal LCDPWR LCDPWR is an S1D13704 output signal which is configurable as active high or active low by the CNF4 signal status on the rising edge of the RESET signal For the proper operation of the VDDH power supply LCDPWR must be configured as active low Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 18 Epson Research and Development Vancouver Design Center 6 13 CPU Bus Interface Header Strips 1D13704 X26A G 005 03 All of the CPU Bus interface pins of the S1D13704 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than ISA Refer to Table 4 1 CPU BUS Connector H1 Pinout on page 11 and Table 4 2 CPU BUS Connector H2 Pinout on page 12 for specific settings Note These headers only provide the CPU Bus interface signals from the 1D13704 When another host bus interface is selected by CNF 3 0 an
13. yg Bank 1 Logic 0 1 2 3 4 5 6 7 Green Bank Select REG 16h bit 2 i Blue Look Up Table Bank 0 2 bit pixel data 0 gt 2 3 Bank 1 0 e ian Bank 3 Select Bank 2 Logic 0 e 1 2 3 Bank 3 0 ar 3 Blue Bank Select REG 16h bits 1 0 Figure 11 8 256 Level Color Mode Look Up Table Architecture 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 79 Vancouver Design Center 12 SwivelView Many of todays applications use the LCD panel in a portrait orientation In this case it becomes necessary to rotate the displayed image This rotation can be done by software at the expense of performance or as with the S1D13704 it can be done by hardware with no CPU penalty There are two SwivelView modes Default SwivelView and Alternate SwivelView 12 1 Default SwivelView Mode Default Swivel View Mode requires the portrait image width be a power of two e g a 240 line panel requires a minimum virtual image width of 256 This mode should be used whenever the required virtual image can be contained within the integrated display buffer i e virtual image size lt 40k bytes as it consumes less power than the Alternate SwivelView mode For example the panel size is 320x240 and the display mode is 4 bit per pixel The virtual image size is 320x256 which can be contained within the 40k Byte display buffer Default
14. 13704SPLT 13704SPLT demonstrates S1D13704 split screen capability by showing two different areas of display memory on the screen simultaneously Screen 1 memory is located at the start of the display buffer and is filled with horizontal bars Screen 2 memory is located immediately after Screen 1 in the display buffer and is filled with vertical bars On either user input or elapsed time the line compare register value is changed to adjust the amount of display area taken up by each screen 13704SPLT must be configured to work with each different hardware platform Consult documentation for the program 13704CFG EXE which can be used to configure 13704SPLT This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations 1D13704 Supported Evaluation Platforms 13704SPLT has been tested with the following S1D13704 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Devel
15. 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the NEC VR4102 Microprocessor Issue Date 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the PC Card Bus Document Number X26A G 009 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners
16. 800 441 2447 e Motorola Website http www mot com e Epson Research and Development Website http www erd epson com 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68328 Processor e Motorola Design Line 800 521 6274 e Local Motorola sales office or authorized distributor Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 02 12 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192
17. CNx Input Output Bi Directional Input Output Power pin CMOS level input CMOS level input with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively CMOS level Schmitt input CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA Tri state CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA Tri state CMOS output driver with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA CMOS low noise output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA 5 2 1 Host Interface RESET re Pin Names Type Pin Cell State Description This pin has multiple functions For SH 3 SH 4 mode this pin inputs system address bit O AO For MC68K 1 this pin inputs the lower data strobe LDS ABO l 70 CS Input e For MC68K 2 this pin inputs system address bit O AO For Generic 1 this pin inputs system address bit O AO For Generic 2 this pin inputs system address bit O AO See Host Bus Interface Pin Mapping for summary 53 54 55 56 57 58 ee z AB 15 1 59 62 63 c Input A input the system address bits 15 through 1 64 65 66 ea 67 68 69 These pins have multiple functions e For SH 3 SH 4 mode these pins are connected to D15 0 a a P For MC68K 1 these pins are connected to D 15 0 see gi aea High
18. Fe KI A I I RRA RAS AN ERR_OK 0 No error call was successful ERR_FAILED General purpose failure ERR_UNKNOWN_DEVICE PERES ERR_INVALID_PARAMETER Function was called with invalid parameter most significant reversed by the given compiler define MIN_NON_DISP_X 32 define MAX_NON_DISP_X 256 define MIN_NON_DISP_Y 2 define MAX_NON_DISP_Y 64 BOK KKK KK KR RK KR KK KO KK k kkk k Definitions for seSetFont Fe AK I I I I I KK Y enum HAL STDOUT HAL_STDIN HAL _DEVICE_ERR 7 define FONT_NORMAL 0x00 S1D13704 X26A G 002 03 Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center define FONT_DOUBLE_WIDTH 0x01 define FONT_DOUBLE_HEIGHT 0x02 enum T RED GREEN BLUE y Page 75 KOR KKK ARA RAR RARA RAR I RAR RARA RARA RR RRA RARA RRA I ARA RARA ARAS typedef struct tagHalStruct char szIdString 16 WORD wDetectEndian WORD wSize BYTE Reg MAX_REG 1 E DWORD dwClkI DWORD dwDispMem Input Clock Frequency in kHz PE ES WORD wFrameRate HAL STRUCT typedef HAL_STRUCT PHAL STRUCT ifdef INTEL f BARE typedef HAL STRUCT far LPHAL STRUCT else typedef HAL STRUCT LPHAL STRUCT endif Le X FUNCTION PR
19. Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 38 Epson Research and Development Vancouver Design Center Note Sync Timing Frame Pulse Line Pulse t5 DRDY MOD Data Timing Line Pulse lt t1 Shift Pulse Vv lt FPDAT 7 4 t9 t11 t10 A 18 4 gt 112 113 gt 1 2 x For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 11 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 4 Ts t10 Shift Pulse pulse width low 2 Ts t11 Shift Pulse pulse width high 2 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 2 Ts t13 FPDAT 7 4 hold to Shift Pulse falling edge 2 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1
20. 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 IO 6400 0000h 64M byte Card 1 Memory 6400 0000h 64M byte Card 2 Memory When the PR31500 PR31700 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2IOEN are ignored and the attribute IO space of the PR3 1500 PR31700 is divided into Attribute I O and S1D13704 access Table 3 2 PR31500 PR31700 to PC Card Slots Address Remapping Using the IT8368E provides all details of the Attribute IO address reallocation by the IT8368E Table 3 2 PR31500 PR31700 to PC Card Slots Address Remapping Using the ITS368E IT8368E Uses PC Card Slot Philips Address Size Function 0800 0000h 16M byte Card 1 IO 4 0900 0000h 16M byte S1D13704 aliased 256 times at 64K byte intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO o 0D00 0000h 16M byte S1D13704 aliased 256 times at 64K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory S1D13704 X26A G 012 02 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 EPSON Research and Development Page 13 Vancouver Design Center 3 4 S1D13704 Configuration The S1D13704 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details o
21. 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 42 Epson Research and Development Vancouver Design Center tl t2 Sync Timing Tr Frame Pulse p t4 ja 18 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 j t10 lt 4 gt gt Shift Pulse t12 t13 FPDAT 7 4 X Figure 7 15 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 0 5 Ts t9 Shift Pulse period 1 Ts t10 Shift Pulse pulse width low 0 5 Ts t11 Shift Pulse pulse width high 0 5 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 0 5 Ts t13 FPDAT 7 4 hold to Shift Pulse falling edge 0 5 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin 18min 9Ts 3 t3min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 0 5 Ts 5 t7min REG 08h bits 4 0 x 8 9 5 Ts S1D13704 Hardware Functional S
22. 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the PC Card Bus 1D13704 Issue Date 01 02 12 X26A G 009 03 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents PC Card PCMCIA Standard March 1997 e Epson Research and Development Inc D13704 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X26A A 001 xx e Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc S1D13704 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e PC Card web page http www pc card com e EPSON Research and Development web page http www erd epson com 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and
23. Connect to IO RD WR RD WR RD WR R W R W RD1 V DD RD RD RD nomeo O SIZ1 RDO RD DD WEO WEO WEO ra iD SIZO WEO WE DD WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 14 Epson Research and Development Vancouver Design Center 6 Technical Description 6 1 ISA Bus Support This board has been designed to support the 16 bit ISA bus environment and can be used in conjunction with either a VGA or a monochrome display adapter card There are 5 configuration inputs associated with the Host Interface CNF 3 0 and BS Refer to Table 2 3 Jumper Settings and Table 5 1 Host Bus Interface Pin Mapping for complete details 6 1 1 Display Adapter Card Support When using the S5U13704B00B in conjunction with another primary Display Adapter VGA or Monochrome the following applies ISA or VL Bus VGA Display Adapter When the S5U13704B00B board is used with an ISA or VL Bus VGA display adapter the VGA card must have a 16 bit BIOS to prevent conflicts during 16 bit accesses MEMCS 16 If an 8 bit VGA adapter card is installed in the system being used it must be removed and the screen display routed through a COM port to a terminal display device PCI Bus VGA Display Adapter All PCI based VGA display adapters can be used in conjunction with the S5U13704B00C
24. Currently seDrawLine only draws horizontal and vertical lines Parameters Device registered device ID xl yl first endpoint of the line in pixels x2 y2 second endpoint of the line in pixels see note below Color color to draw with Color is an index into the LUT Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 59 int seDrawRect int DeviD long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters This routine draws and optionally fills a rectangular area of display buffer The upper right corner is defined by x1 y1 and the lower right corner is defined by x2 y2 The color defined by Color applies both to the border and to the optional fill DevID registered device ID xl yl top left corner of the rectangle in pixels x2 y2 bottom right corner of the rectangle in pixels Color The color to draw the rectangle outline and fill with Color is an index into the Look Up Table SolidFill Flag whether to fill the rectangle or simply draw the border Set to 0 for no fill set to non 0 to fill the inside of the rectangle Return Value ERR_OK operation completed with no problems 9 2 7 LUT Manipulation These functions deal with altering the color values in the Look Up Table int seSetLut int DevID BYTE pLut int Count Descriptio
25. Figure 11 ERROR Unable to read HAL Help Clicking on the Help button will start the help file for S1D13704CFG Exit Clicking on the Exit button exits 13704CFG immediately The user is not prompted to save any changes they may have made 13704CFG EXE Configuration Program 1D13704 Issue Date 01 02 08 X26A B 001 02 Page 16 Comments S1D13704 X26A B 001 02 Epson Research and Development Vancouver Design Center It is assumed that the 13704CFG user is familiar with S1D13704 hardware and software Refer to the S1D13704 Functional Hardware Specification drawing office number X22A A 001 xx and the S1D13704 Programming Notes and Examples manual drawing office number X22A G 002 xx for information 13704CFG EXE Configuration Program Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704SHOW Demonstration Program Document No X26A B 002 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a re
26. Generic 2 interface the host interface pins are mapped as in the table below Table 2 2 SID13704 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR Connect to lO Vpp RD RD WEO WE Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 02 12 1D13704 X26A G 004 02 Page 10 EPSON Research and Development Vancouver Design Center 3 System Design Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the S1D13704 can be interfaced so that it shares a PC Card slot The S1D13704 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the S1D13704 virtually transparent to PC Card devices that use the same slot 3 1 Hardware Description The ITE8368E has been specially designed to support EPSON LCD controllers The ITE IT8368E provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the S1D13704 CPU interface The TX3912 processor only provides addresses A 12 0 therefore devices requiring more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address
27. Issue Date 01 02 12 Epson Research and Development Page 41 Vancouver Design Center 7 5 Limitations The only limitation to using SwivelView mode on the 1D13704 is that split screen operation is not supported A comparison of the two SwivelView modes is as follows Table 7 1 Default and Alternate Swivel View Mode Comparison Item Default Swivel View Mode Alternate SwivelView Mode The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 160x240x8bpp image would normally require only 38 400 bytes possible within the 40K byte address space but the virtual image is 256x240x8bpp which needs 61 440 bytes not possible Memory Requirements Does not require a virtual image MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz CLK need only be as fast as the required POLK then CLK must be 6MHz Note that Clock Requirements POEK 25MHz is the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Typically 20 higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Performance Nominal performance Slightly higher performance than Default Mode Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Pa
28. Issue Date 01 02 12 Page 5 1D13704 X26A G 002 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This guide describes how to program various features of the S1D13704 Embedded Memory Color LCD controller The demonstrations include descriptions of how to calculate register values and explanations of how or why you might want to do certain procedures This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13704 Most S1D1350x S1D1370x and 1380x products support the HAL allowing OEMs to switch chips with relative ease Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 8 Epson Research and Development Vancouver Design Center 2 Initialization This section describes the register settings and steps needed to initialize the S1D13704 The first step toward initializing the S1D13704 is to set the control registers The S1D13704 then generates the proper control signals for the display After setting the control registers the Look up Table must be programmed with meaningful values This section does not cover setting Look Up Table values See Section 4 on page 14 of this manual for Look up Table programming details The following initia
29. Jumper JP9 selects between these two types of panels A positive power supply for panels requiring a positive bias voltage is supplied to header J4 by the LCD module through the 50 pin LCD module connector J3 No negative power supply is available on the LCD module therefore only panels which have their own bias voltage supply or those that use a positive supply can be connected to J4 The LCD module can only support these panels as well Header J4 and its associated buffers and components have been left unpopulated on the CPU module These parts can be added by the user if desired 4 3 LCD Controller 4 3 1 S1D13704 vs S1D13705 The LCD controller used in conjunction with the TMPR3912 22U microprocessor can either be a S1D13704 or a S1D13705 If a S1D13704 is used jumper JP7 must be set to position 1 2 This setting allows CNF4 to be configured for the S1D13704 CNF4 controls the polarity of the LCDPWR signal and can be set either high or low with jumper JP11 If a S1D13705 is used jumper JP7 must be set to position 2 3 This setting allows pin 45 of the LCDC to be used as address bit AB16 which is needed on the S1D13705 to accom modate the larger display memory 4 3 2 LCDPWR Polarity The power supply on the LCD module used LCDON an active low signal to turn on the supply This signal is connected to LCDPWR Since LCDPWR is configurable on the S1D13704 and is set active high on the S1D13705 a facility must be provided to in
30. Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13704 X26A G 012 02 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 02 Issue Date 01 02 12 EPSON S1D13704 5 Embedded Memory Color LCD Controller S5U13704 5 TMPR3912 22U CPU Module Document Number X00A G 004 02 Copyright O 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Vancouver Design Center
31. Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T INEOGUCH OUD akas DARA Be AAA By wae 7 2 Interfacing tothe PC CardBus 2 2 02 ee eee ee ee es 8 2 1 The PC Card SystemBUS 2 20 ke ea a ZLE PCCard Overview ta dne food dew ick ea shy eed eee he wid he deh BS ad whos 8 2 1 2 Memory Access Cycles omo ee ee bee eb ke ee hee 8 3 91013704 Bus Interface ee Gi A E ee oe a ew 10 3 1 Bus Interface Modes 020 2 0 0 2 2 10 3 2 Generic 1 Interface Mode 2 2 2 222022022222 1 4 PC Card to S1D13704 Interface 12 4 1 Hardware Connections a westa a eee ee 1 4 2 S1D13704 Hardware Configuration 2222 2 13 4 3 PAL Equations 2 ey E a E e oe a ee eee 14 4 4 Register Memory Mapping 14 Softwaren se ce tee tig Se DS aes Se ee A eae ow hie aie 15 6 References o cia se Soe eee A a ee ee ae 16 6 1 Documents s 4 4 4 4 amp dct A a ee ek we 16 6 2 Document Sources e 16 7 Technical Support a 5 2 0 0 2 84 42 23 E A A A 17 7 1 EPSON LCD Controllers S1D13704 2 2 2 2 2 17 Ta PC Card Standard o 4 4 8 oir a tae dl as ar do ee tt a A aa DY Interfacing to the PC Card Bus S1D13704 Issue Date
32. RWE gt RDWR FPFRAME DD FPFRAME LCD SIZ1 gt RDF FPLINE gt FPLINE Display Sizo gt WEo DRDY MOD DSACK1 dt WAIT LCDPWR CLK gt BCLK RESET Pi RESET Figure 3 4 Typical System Diagram M68K 2 Bus Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 14 Epson Research and Development Vancouver Design Center Oscillator CLK _ GENERIC 1 psi BUS CSn Pp cSt A 15 0 AB 15 0 D 15 0 le DB 15 0 FPDAT 11 0 _ 11 0 FPSHIFT A FPSHIFT WEO p WEO S1 D13704 12 bit Wet gt wet FPFRAME FPFRAME TFT ae gt RD FPLINE FPLINE Display RDI gt RD WR ae PRADY WAIT WAIT LCDPWR BCLK BCLK RESET Vv RESET Figure 3 5 Typical System Diagram Generic 1 Bus Oscillator CLK d BS ISA REFRESH p BUS sap9 16 p Decoder P gt CS SA 15 0 gt AB 15 0 SD 15 0 gt DB 15 0 FPDATIS 0 gt 8 0 SMEMW P WEO FPSHIFT gt FPSHIFT SMEMR gt RD S1D13704 9 bit FPFRAME FPFRAME TFT ssie l were FPLINE FPLINE Display DRDY DRDY IOCHRDY WAIT LCDPWR BCLK gt BCLK RESET Do gt RESET Figure 3 6 Typical System Diagram Generic 2 Bus e g ISA Bus S1D1370
33. Table of Contents 1 INTFOGUCTION xi Sede RN a a BO ik ee 1 1 General Description 2 1D13704 5 Bus Interface 0 000 cee 2 1 Bus Interface Modes 2 2 Generic 2 Interface Mode 3 TMPR3912 22U and S1D13704 5 Interface lt 3 1 Hardware Connections 3 2 Memory Mapping and Aliasing a 3 3 1D13704 5 Configuration and Pin Mapping 4 CPU Module Description lt lt lt ee es 4 1 Clock Signals AI BUSCER Vos we le wee Bayete AA ak AND CEK eps ces dl o a bate gee Win E BA o Be ct Tah bas E 4 2 LCD Connectors 4 2 1 50 pin LCD Module Connector J3 00 0 4 2 2 Standard Epson LCD Connector J4 0 4 3 LCD Controller 43 1 1D13704 vs S1D13705 o 02 22 0008 4 32 LCEDPWR Polarity osos oc A ee EM 43 3 S1D13704V75 Chip Select o e S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 Page 3 X00A G 004 02 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 1D13704 5 Configuration for Generic 2 Bus Interface o o 11 Table 3 2 1D13704 5 Generic 2 Interface Pin Mapping e 11 List of Figures Figure 3 1 1D13704 to TMPR3912 22U
34. The S1D13704 is interfaced to the PC Card interface with a minimal amount of glue logic A PAL is used to decode the write and read signals of the PC Card bus to generate RD RD WR WE0 WE1 and CS for the S1D13704 The PAL also inverts the reset signal of the PC card since it is active high and the 1D13704 uses an active low reset For PAL equations for this implementation refer to Section 4 3 PAL Equations on page 14 In this implementation the address inputs AB 15 0 and data bus DB 15 0 connect directly to the CPU address A 15 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the S1D13704 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI BS bus start is not used by Generic 1 mode but is used to configure the S1D13704 for Generic 1 and should be tied low connected to GND The following diagram shows a typical implementation of the PC Card to 1D13704 interface PC Card socket PAL16L8 15 1D13704 gt RDA OE gt N RD WR WE IRA CE1 gt gt WEO CE2 gt gt WE1 REG gt gt CS RESET gt gt RESET A 15 0 gt AB 15 0 D 15 0 gt DB 15 0 15K pull up WAITH WAIT Lied BUSCLK Oscillator CLKI S1D13704 X26A G 009 03 Figure 4 1 Typical Imple
35. This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MC68328 Dragonball Microprocessor By implementing a dedicated display refresh memory the S1D13704 can reduce system power consumption improve image quality and increase system perfor mance as compared to the Dragonball s on chip LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68328 2 1 The MC68328 System Bus The MC68328 is an integrated controller for handheld products based upon the MC68EC000 microprocessor core It implements a 16 bit data bus and a 32 bit address bus The bus interface consists of all the standard MC68000 bus interface signals plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The MC68000 bus control signals
36. Ts pixel clock period 2 tlmin 138min 9Ts 3 83min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 2 Ts 5 t7min REG O8h bits 4 0 x 8 11 Ts S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 39 Vancouver Design Center 7 3 4 Single Monochrome 8 Bit Panel Timing VDP VNDP FPFRAME y FPLINE l j I fl j fl fl I I DRDY MOD X hate X FPDAT 7 0 XLINE1 XLINE2 X LINES X LINE4 X XLINE479XLINEA480 LINE1 X LINE2 ee FPLINE DRDY MOD y PA l HDP HNDP gt FPSHIFT es en e lt 2 7 FPDAT7 o 14 19 XX X KX 1 633 X FPDAT6 x 12 X 1 10 XX SS XX X 634 KA FPDAT5 ED ED GD ee a y AO 4 635 KX FPDAT4 o K 14 X 112X YX gt XX X YX Y X 1 636 AK FPDAT3 o 15 Y 113 X Y Y Y 1 637 X FPDAT2 a2 Lis XiX X Y X 1 638 Y A FPDAT1 ae 17 1 15 X y X Y 639 kK Xx FPDATO o A 18 X 1 16 X X X Y X Y 1 640 kX Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 12 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Pe
37. VDP Vertical Display Period VNDP Vertical Non Display Period HDP Horizontal Display Period HNDP Horizontal Non Display Period Hardware Functional Specification Issue Date 01 02 08 REG 06h bits 1 0 REG O5h bits 7 0 1 Lines REG OAh bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts REG 08h 4 x 8Ts 1D13704 X26A A 001 04 Page 46 Epson Research and Development Vancouver Design Center rates tl Sync Timing t2 a Frame Pulse gt 8 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 Shift Pulse FPDAT 7 0 Figure 7 19 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge
38. WORD pWord int seReadDisplayDword int nDevID DWORD offset DWORD pDword int seWriteDisplayBytes int nDevID DWORD addr BYTE val DWORD count int seWriteDisplayWords int nDevID DWORD addr WORD val DWORD count int seWriteDisplayDwords int nDevID DWORD addr DWORD val DWORD count Power Sav Af int seHWSuspend int nDevID BOOL val int seSetPowerSaveMode int nDevID int PowerSaveMode E Drawing int seSetPixel int nDevID int x int y DWORD color int seGetPixel int nDevID int x int y DWORD pVal int seDrawLine int nDevID int xl int yl int x2 int y2 int seDrawRect int nDevID int xl int yl int x2 int y2 till Ys DWORD color DWORD color BOOL Solid int seDrawCircle int nDevID int xCenter int yCenter int radius DWORD color BYTE SolidFill Text e int seDrawText int nDevID char fmt int seSetCursor int row int col int seSetColor DWORD foreground DWORD background int seSetFont BYTE FontSize BYTE FontAttr Color avd int seSetLut int nDevID BYTE pLut int seGetLut int nDevID BYTE pLut int seSetLutEntry int nDevID int index BYTE pEntry int seGetLutEntry int nDevID int index BYTE pEntry ndif _HAL H_ is k k APPCFG H Application configuration information Created 1998 Vancouver Design
39. board Monochrome Display Adapter All monochrome display adapters can be used in conjunction with the S5U13704B00C board 6 1 2 Expanded Memory Manager If a memory manager is being used for system memory the address range DOOOOh to DFFFFh must be excluded from use as this range is used by the S5U13704B00C 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Page 15 Vancouver Design Center 6 2 Non ISA Bus Support The S5U13704B00C board is specifically designed to support the standard 16 bit ISA bus however the 1D13704 directly supports many other host bus interfaces Header strips H1 and H2 are provided and contain all the necessary IO pins to interface to these host buses See CPU Bus Interface Connector Pinouts on page 11 Table 2 1 Configuration DIP Switch Settings on page 8 and Table 2 3 Jumper Settings on page 9 for details When using the header strips to provide the bus interface observe the following All IO signals on the ISA bus card edge must be isolated from the ISA bus do not plug the card into a computer Voltage lines are provided on the header strips U7 a TIBPAL16L8 15 PAL is currently used to provide the 1D13704 CS pin 74 RESET pin 73 and other decode logic signals for ISA bus use This functionality must now be provided externally remove the PAL from its socket to eliminate conflicts resulting fr
40. 01 02 12 X26A G 013 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to an 8 bit Processor 2 1 The Generic 8 bit Processor System Bus 1D13704 X26A G 013 02 Although the S1D13704 does not directly support an 8 bit CPU with minimal external logic an 8 bit interface can be achieved Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the S1D13704 only the write read and wait control signals as well as the data and address lines need to be interfaced Since the S1D13704 is a 16 bit device some external logic is required Interfacing to an 8 bit Processor Issue Date 01 02 12 Epson Research and Development Page 9 Vancouver Design Center 3 S1D13704 Bus Interface This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic 2 Host Bus Interface used to implement the interface to an 8 bit processor The S1D13704 provides a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The bus interface mode used in this example is e Generic 2 this bus interface is ISA like and can easily be modified to support an 8 bit CPU 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal
41. 1 0805 resistor 23 2 R17 R18 1K 5 0805 resistor 24 2 R19 R20 100K 5 0805 resistor 25 1 R21 100K 100K Trim POT Spectrol 63S104T607 or equivalent 26 1 S1 SW DIP 6 6 position DIP switch 27 1 U1 S1D13704F00A QFP14 80 80 pin SMT 28 1 U2 25 0 MHz oscillator FOX 25MHz oscillator or equiv 14 pin DIP socketed 29 3 U3 U5 74AHC244 SO 22 TI74AHC244 30 1 U6 LT1117CM 3 3 Linear Technology 5V to 3 3V regulator 800MA 31 1 U7 TIBPAL16L8 15 TI PAL 20 Pin DIP socketed 32 1 U8 74ALS125 SO 20 TI74ALS125 33 1 U9 RD 0412 Xentek RD 0412 positive PS 34 1 U10 EPNOO1 Xentek EPNOO01 negative PS S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 12 S1D13704 X26A G 005 03 Page 20 Epson Research and Development Vancouver Design Center 8 Schematic Diagrams z El o a E 3 t l 3 ol y fs E E El a a l y S n E D ol amp E El aa 3 N 3 Be E a 2 wo a g 13 o lu 4 v sje s a 4 3 s 5 3 5 a 8 m 2 ae es Ol o 2 x El aa 3 a E a ad gt g E y Ri a E a es ml 2 a a 5 a qwa x Za Law o o TI H 3 O E a a E 3 3 8 E ae S oy f 5 5 E og a a8 3 a 3395
42. 1 0 Figure 11 5 2 Level Color Look Up Table Architecture Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 76 4 Level Color Mode Epson Research and Development Vancouver Design Center 4 Color Data Format Red Bank Select REG 16h bits 5 4 Green Look Up Table REG 16h bits 3 2 AO Blue Look Up Table Bank 0 0 0 0 gt 5 3 Bank 1 0 e d 3 Bank 4 bit Green display data output 3 Select Bank 2 Logic 0 __ 4 gt 1 2 3 Bank 3 o oe Green Bank Select 3 Blue Bank Select REG 16h bits 1 0 Bank 0 0 o gt 2 3 Bank 1 0 E Bank 4 bit Blue display data output 3 Select Bank 2 Logic 0 gt 1 2 3 Bank 3 0 ar 3 Ea Red Look Up Table 7 6 5 4 3 2 1 0 Banko A0 BO A1 B1 A2 B2 A3 B3 2 bit pixel data g gt gt See Section 10 3 Bank 1 9 ro Bank 4 bit Red display data output 3 Select Bank 2 Logic 0 L 1 2 3 Bank 3 9 E 3 Figure 11 6 4 Level Color Mode Look Up Table Architecture 1D13704 X26A A 001 04 Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Pa
43. 12 Epson Research and Development Vancouver Design Center Table of Contents INTRODUCTION S1D13704 Embedded Memory Color LCD Controller Product Brief SPECIFICATION S1D13704 Hardware Functional Specification PROGRAMMER S REFERENCE S1D13704 Programming Notes and Examples S1D13704 Register Summary UTILITIES 13704CFG EXE File Configuration Program 13704SHOW Demonstration Program 13704SPLT Display Utility 13704VIRT Display Utility 13704PLAY Diagnostic Utility 13704BMP Demonstration Program 13704PWR Power Save Utility DRIVERS S1D13704 Windows CE Display Drivers EVALUATION S53U13704B00C Rev 1 ISA Bus Evaluation Board User Manual APPLICATION NOTES Interfacing to the Toshiba MIPS TX3912 Processor Power Consumption Interfacing to the Motorola MC68328 Microprocessor Interfacing to the NEC VR4102 Microprocessor Interfacing the S1D13704 to the PC Card Bus Interfacing to the Motorola MPC821 Microprocessor Interfacing to the Motorola MCF5307 Microprocessor Interfacing to the Philips MIPS PR31500 PR31700 Processor S5U13704 5 TMPR3912 22U CPU Module Interfacing to an 8 Bit Processor TECHNICAL MANUAL Issue Date 01 02 12 Page 5 S1D13704 X26A Q 001 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 TECHNICAL MANUAL X26A Q 001 04 Issue Date 01 02 12 EPSON f GRAPHICS February 2001 S1D13704 EMBEDDED MEMORY COLOR LCD CONTROLLER E DESCRIPTION The S1
44. 14 Table 4 2 Host Bus Selection my 4 2 68 a ek ao bie Re A eee he 14 List of Figures Figure 2 1 NEC VR4102 Read Write Cycles 2 2 2 2 e ee ee 9 Figure 4 1 Typical Implementation of VR4102 to S1D13704 Interface 13 Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the NEC VR4102 Microprocessor X26A G 008 05 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the NEC Vr4102 Microprocessor uPD30102 The NEC Vr4102 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfaci
45. 14 SA11 Connected to AB11 of the S1D13704 15 SA12 Connected to AB12 of the S1D13704 16 SA13 Connected to AB13 of the S1D13704 17 GND Ground 18 GND Ground 19 SA14 Connected to AB14 of the S1D13704 20 SA15 Connected to AB14 of the S1D13704 21 SA16 Connected to AB16 of the S1D13704 22 SA17 Connected to AB17 of the S1D13704 23 SA18 Connected to AB18 of the S1D13704 24 SA19 Connected to AB19 of the S1D13704 25 GND Ground 26 GND Ground 27 VCC 5 volt supply 28 VCC 5 volt supply 29 RD WR Connected to the R W signal of the S1D13704 30 BS Connected to the BS signal of the S1D13704 31 BUSCLK Connected to the BCLK signal of the S1D13704 32 RD Connected to the RD signal of the S1D13704 33 NC Not connected 34 NC Not connected S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5 1 Host Bus Interface Pin Mapping Page 13 Si D13707 SH 3 SH 4 MC68K 1 MC68K 2 Generic Bus 1 Generic Bus 2 Pin Names AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO BCLK BCLK BCLK BCLK BS BS BS AS AS Connect to Vss von ct to IO DD
46. 1D13704 X26A A 001 04 The following formulae are used to calculate the display frame rate TFT D TFD and Passive Single Panel modes Where fpcLK FrameRate lt lt HDP HNDP x VDP VNDP fpcLk PClIk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Horizontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG OSh bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Passive Dual Panel mode Where f FrameRate PCER 2 x HDP HNDP x 5 VNDP frerk PClk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Horizontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Page 71 Vancouver Design Center 10 Display Data Formats 1 bpp bit 7 bit 0 PoP P2 P3P4P5P6P7 Panel Display Host Address Display Memory 2 bpp bit 7 bit 0 PoP P2 P3P4Ps P6 P7 Panel Display Host Address Display Memory Po P4 P2 P3P4P5 Pe P7 Ph a An Br Cr Dn Panel Display Host Address Display Memory 8 bpp 3 3 2 RGB bit7
47. 25MHz A 25 0MHz oscillator U2 socketed is provided as the default clock source 6 6 LCD Panel Voltage Setting The S5U13704B00C board supports both 3 3V and 5 0V LCD panels through the single LCD connector J5 The voltage level is selected by setting jumper J4 to the appropriate position Refer to Table 2 3 Jumper Settings on page 9 for setting this jumper 6 7 Monochrome LCD Panel Support The S1D13704 directly supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 8 Color Passive LCD Panel Support The S1D13704 directly supports 4 and 8 dual and single color passive LCD panels All the necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 9 Color TFT D TFD LCD Panel Support S1D13704 The S1D13704 directly supports 9 and 12 bit active matrix color TFT D TFD panels All the necessary signals can also be found on the 40 pin LCD connector J5 The interface signals on the cable are alternated with grounds to reduce crosst
48. 3 HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Prana inactive LCDPWR Override 0 t4 LCDPWR low to FPLINE FPFRAME FPSHIFT FPDAT DRDY inactive 127 Erare LCDPWR Override 0 5 HW Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY 0 Frame LCDPWR active LCDPWR Override 0 t6 LCDPWR Override active 1 to LCDPWR inactive 1 Frame t7 LCDPWR Override inactive 1 to LCDPWR active 1 Frame S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 37 Vancouver Design Center 7 3 3 Single Monochrome 4 Bit Panel Timing VDP VNDP FPFRAME A FPLINE ll f L l fl l f l J DRDY MOD BA FPDAT 7 4 ALINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240 LINE1 X LINE2 FPLINE I DRDY MOD X HDP HNDP lt gt lt gt PERR A AAA A FPDAT7 1X15 X k XX X 4317 X FPDAT6 12 X 16 y X y X 1 318 X FPDAT5 13X17 Y a EN 1319 AR FPDAT4 14 X 18 X t Y 1 320 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 10 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP
49. 4 1 Typical Implementation of MCF5307 to S1D13704 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13704 Issue Date 01 02 12 X26A G 011 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 03 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13704 Issue Date 01 02 12 X26A G 011 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The M
50. 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 bit7 REG 01 REG 01 REG 01 REG 01 bit 5 bite bit bit 0 REG 01h Moe REGISTER 0 IO address FFE1h RW REG 14h SCREEN 1 VERTICAL SIZE REGISTER MSB IO address FFF4h RW 0 Mono Single 4 bit LCD 7 El 0 i 3 FPLine FPFrame Mask Data Width Screen 1 Vertical Size 1 Mono Single 8 bit LCD TFT STN Dual Single Color Mono Polarity Polarity FPSHIFT Bit 1 Bit 0 n a n a n a n a n a n a Bit 9 Bits 0 1 0 reserved REG 02h Move REGISTER 1 IO address FFE2h RW REG 15h Look Up TABLE ADDRESS REGISTER IO address FFF5h RW o 1 reserved 0 reserved High 5 Input Clock Display Hw Ngo Software ala wa RGB Index Look Up Table Address 0 f Performance Div CLKI 2 Blank Enable _ Video Invert Bit 1 Bit 0 Bit 3 Bit2 Bit 1 Bit 0 i 1 Mono Dual 8 bit LCD 0 reserved REG 03h MODE REGISTER 2 1O address FFESh RW REG 16h Look Up TABLE BANK SELECT REGISTER IO address FFF6h RW l 1 jesarved o Look Up s7 ai n a LGDPWR Hardware Sw Power Save n a n a ia eae besa ES Bank pou e ait pea 5 0 Color Single 4 bit LCD Table Bi id PS Enabl il ji i i il i i i A BYPASS Override PSEnable mig Bit O 1 Color Single 8 bit LCD Format 1 o 0 reserved REG 04h HORIZONTAL PANEL SIZE REGISTER IO address FFE4h RW REG 17h Look Up TABLE DATA REGISTER lO address FFF7h RW 1 Horizontal Panel Size 8 REG 1 Look Up Table Data i 1 Color Single 8 bitL OD Format 2 n a ji ji Bit 6 Bit 5 Bit 4 Bit 3
51. 8 bit Processor X26A G 013 02 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 20 00 0002 eee eee 9 Table 4 1 Configuration Settings ee 12 Tabl 4 2 Host Bus S lection 2 3 4 304 fg es ek ao ew Be A ee a a a 12 List of Figures Figure 4 1 Typical Implementation of an 8 bit Processor to the S1D13704 Generic 2 Interface 11 Interfacing to an 8 bit Processor 1D13704 Issue Date 01 02 12 X26A G 013 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to an 8 bit Processor X26A G 013 02 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and a generic 8 bit micropro cessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to an 8 bit Processor S1D13704 Issue Date
52. All rights reserved kk ifndef HAL _REGS_H define HAL _REGS_H Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 78 E 1374 register names E defin EG_REVISION_CODE fin EG _MODE_REGISTER_0 fin EG_MODE_REGISTER_1 EG_MODE_REGISTER_2 EG HORZ_PANEL_SIZE R a R d R d R d RI define REG_VERT_PANEL_SIZE_LSB define REG_VERT_PANEL_SIZE_MSB define REG_FPLINE_START_POS define REG_HORZ NONDISP_PERIOD define REG_FPFRAME_START_POS define REG_VERT_NONDISP_PERIOD define REG_MOD_RATE define REG_SCRN1_START_ADDR_LSB define REG_SCRN1_START_ADDR_MSB define REG_RESERVED_1 define REG_SCRN2_START_ADDR_LSB define REG_SCRN2_START_ADDR_MSB define REG_RESERVED_2 define REG_PITCH_ADJUST define REG_SCRN1_VERT_SIZE_LSB define REG_SCRN1_VERT_SIZE_MSB define REG_LUT_ADDR define REG_LUT_BANK_SELECT define REG_LUT_DATA define REG_GPIO_CONFIG define REG_GPIO_STATUS define REG_SCRATCHPAD define REG_PORTRAIT_MODE define REG_LINE_BYTE_COUNT d
53. Centre S1D13704 X26A G 002 03 Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 77 Vancouver Design Center Copyright c 1998 Epson Research and Development Inc All Rights Reserved The data in this file was generated using 1374CFG EXE The configureation parameters chosen were KK 320x240 Single Color 8 bit STN format 2 aoe 4 bpp 70 Hz Frame Rate 25 MHz CLKi KK High Performance enabled x k E KOK KKK ARK RAR RAR RARA RR RRA RRA RAR KARA RR RR ARA RA RRA RRA Y 1374 HAL HDR do not remove HAL STRUCT Information generated by 1374CFG EXE Af Copyright c 1998 Seiko Epson Corp All rights reserved JE E Include this file ONCE in your primary source file ad KOK KR KR KK KK KR I I I I I I KK OK HAL STRUCT HalInfo 1374 HAL EXE ID string ES 0x1234 Detect Endian sizeof HAL_STRUCT Size 0x00 0x23 OxBO 0x03 Ox27 OxEF 0x00 0x00 0x1E 0x00 0x3B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 25000 C1kI kHz 0xD0000 Display Address 70 Panel Frame Rate Hz y k k FK HAL_REGS H k Created 1998 Epson Research Development we Vancouver Design Center Copyright c Seiko Epson Corp 1998
54. Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com Interfacing to the PC Card Bus Issue Date 01 02 12 Page 17 Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13704 X26A G 009 03 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02
55. Fax 604 275 2167 J Email wince erd epson com http www erd epson com Microsoft PL EA Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 VDC EPSON 1D13704 Embedded Memory LCD Controller Hardware Functional Specification Document Number X26A A 001 04 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A Introdu
56. Interface e 10 S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the interface between the S1D13704 5 LCD Controller LCDC and the TMPR3912 22U microprocessor as implemented on the Toshiba 3912 22 and S1D13704 5 CPU Module This module is uS1D in conjunction with the Toshiba TX RISC Reference Platform For more information regarding the S1D13704 or S1D13705 refer to their respective Hardware Functional Specification document number X26A A 001 xx and X27A A 001 xx respectively For more information regarding the TMPR3912 22U refer to the TMPR3912 22U 32 Bit MIPS RISC Processor User s Manual See the Toshiba website under semiconductors at http toshiba com taec nonflash indexproducts html 1 1 General Description The Toshiba TX RISC Reference Kit consists of 6 boards which include a main board a CPU board a EPROM board a FMEM board a debug board and an analog board The main board acts as the motherboard for all the other add on boards In addition to these boards there is an LCD module that connects to the CPU board In order to support the add on LCD panel that connects to the LCD module the CPU board microprocessor must
57. Interface Ss required configuration for this application 4 3 Register Memory Mapping 1D13704 X26A G 013 02 The S1D13704 needs a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte register set The starting memory address is located at 0000h of the 64K byte memory block while the internal registers are located in the upper 32 bytes of this memory block i e REG O FFEOh An external decoder can be used to decode the address lines and generate a chip select for the S1D13704 whenever the selected 64K byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the S1D13704 whenever the S1D13704 memory block is accessed Interfacing to an 8 bit Processor Issue Date 01 02 12 Epson Research and Development Page 13 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or
58. Issue Date 01 02 12 Retrieves the HAL library version information The return values are ASCII strings A typical return would be 1 01 B 5 HAL version 1 01 B is the beta designator this example would be Beta 5 If pStatus is NULL then pStatusRevision should be NULL too pVersion Pointer to string to return the version in must point to an allocated string of size VER_SIZE pStatus Pointer to a string to return the release status in must point to an allocated string of size STATUS_SIZE pStatusRevision Pointer to return the current revision of status must point to an allocated string of size STAT_REV_SIZE None S1D13704 X26A G 002 03 Page 50 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center int seSetBitsPerPixel int DevID int BitsPerPixel Description Parameter Return Value This routine sets the color depth the S1D13704 displays in After performing validity checks to ensure the requested video mode can be set the appropriate registers are changed and the Look Up table is set its default values appropriate to the color depth This call is similar to a mode set call on a standard VGA DevID registered device ID BitsPerPixel desired color depth in bits per pixel Valid arguments are 1 2 4 and 8 ERR_OK operation completed with no problems ERR_FAILED possible causes for this error include 1 the desired frame rate may not be attainable with
59. LUT entry Unlike seSetLut the LUT entry indicated by Tndex can be any value from 0 to 15 A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID Index index to LUT entry 0 to 15 pLUT pointer to an array of three bytes Return Value ERR_OK operation completed with no problems int seGetLutEntry int DeviD int index BYTE pEntry Description Parameters This routine reads one LUT entry from any index A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID Index index to LUT entry 0 to 15 pEntry pointer to an array of three bytes Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 10 Sample Code 10 1 Introduction Page 61 Included in the sample code section are two examples of programing the S1D13704 The first sample uses the HAL to draw a red square wait for user input then rotates to SwivelView mode and draws a blue square The second sample code performs the same procedures but directly accesses the registers of the S1D13704 These code samples are for example purposes only 10 1 1 Sample code using the S1
60. Mapping LCD Interface Pin Mapping Absolute Maximum Ratings Recommended Operating Conditions Input Specifications o o Output Specifications o SH 4 Timing 2 o SH 3 Bus TiMidgB M68K 1 Bus Timing MC68000 M68K 2 Timing MC68030 Generic 1 Timing ocs ec ra Generic 2 TiMid8 Clock Input Requirements Power Down Up Timing Panel Data Format Gray Shade Color Mode Selection High Performance Selection Inverse Video Mode Select Options Hardware Power Save GPIOO Operation Software Power Save Mode Selection Look Up Table Access o o Selection of SwivelView Mode Selection of PCLK and MCLK in SwivelView Mode Look Up Table Configurations Default and Alternate SwivelView Mode Comparison Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 Power Save Mode Selection Software Power Save Mode Summary Hardware Power Save Mode Summary Power Save Mode Function Summary S1D13704 Internal Clock Requirements Hardware Functional Specification Issue Date 01 02 08 Page 5 S1D13704 X26A A 001 04 Page 6 Epson Research and Development Vancouver Design Center THIS P
61. REG 02h bit 6 0 0 2 Gray shade 1 bit per pixel 4 Gray shade 2 bit per pixel 16 Gray shade 4 bit per pixel reserved 2 Colors 1 bit per pixel 4 Colors 2 bit per pixel 16 Colors 256 Colors 4 bit per pixel o o o 8 bit per pixel bit 5 High Performance Landscape Modes Only When this bit 0 the internal Memory clock MCLK is a divided down version of the Pixel clock PCLK The denominator is dependent on the bit per pixel mode see the table below Table 8 3 High Performance Selection BPP Bit 1 BPP Bit 0 Display Modes MCIk PCIk 8 MCIk PCIk 4 MCIk PCIk 2 MCIk PClk 8 bit per pixel MClk PCIK High Performance 1 bit per pixel 0 2 bit per pixel 4 4 bit per pixel X fo j aj o 1 X When this bit 1 MCLK is fixed to the same frequency as PCLK for all bit per pixel modes This provides a faster screen update performance in 1 2 4 bit per pixel modes but also increases power consumption This bit can be set to 1 just before a major screen update then set back to 0 to save power after the update This bit has no effect in Swivel View mode Refer to REG 1Bh Swivel View Mode Register on page 68 for Swivel View mode clock selection Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Epson Research and Development Page 57 Vancouver Des
62. REG OAh needs to be set to 03h The 16 000 000 2 in the formula above represents the input clock being divided by two when this alternate SwivelView mode is selected With the values given for this example we must ensure the Input Clock Divide bit REG 02h b4 is reset with the given values it was likely set as a result of the frame rate calculations for landscape display mode No other registers need to be altered The display is now configured for SwivelView mode use Offset zero of display memory corresponds to the upper left corner of the display Display memory is accessed exactly as it was for landscape mode As this is the alternate Swivel View mode the power of two stride issue encountered with the default SwivelView mode is no longer an issue The stride is the same as the SwivelView mode width In this case 120 bytes Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 45 Vancouver Design Center Example 8 Pan the above SwivelView mode image to the right by 4 pixels then scroll it up by 6 pixels To pan by four pixels the start address needs to be advanced 1 Calculate the amount to change start address by Bytes Pixels x BitsPerPixel 8 4 x 4 8 2 bytes 2 Increment the start address registers by the just calculated value In this case the value writen to the start address register will be 81h 7Fh 2 81h To scroll by 4 lines we have to change the start address by the
63. Register 19h GPIO Status set to 0 aia This step has no reason other than it programs the GPIO Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 69 Vancouver Design Center EE values low should the pins get configured as outputs SET_REG 0x19 0x00 5 Register 1Ah Scratch Pad set to 0 tf SET_REG 0x1A 0x00 Register 1Bh SwivelView Mod set to 0 disable SwivelView mod SET_REG 0x1B 0x00 Register 1Ch Line Byte Count set to 0 Not used by landscape mode aad SET_REG 0x0C 0x00 Register 1Fh TestMod set to 0 SET_REG 0x1F 0x00 Draw a 100x100 red rectangle in the upper left corner 0 0 of the display Auf for y 0 y lt 100 y Set the memory pointer at the start of each line Ae Pointer MEM OFFSET Y Line Width BPP 8 X BPP 8 E pMem LPBYTE MEM_OFFSET y 320 BitsPerPixel 8 0 for x 0 x lt 100 x 2 pMem 0x44 Draws 2 pixels with LUT color 4 pMem Pause here getch Clear the display and all of video memory by writing 40960 bytes of 0 Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 70 Epson Research and Development Vancouver Design Center This is done because an imag
64. Shade Mode Look Up Table Architecture o 72 4 Level Gray Shade Mode Look Up Table Architecture 73 Specification 1D13704 X26A A 001 04 Page 8 Epson Research and Development Vancouver Design Center Figure 11 3 16 Level Gray Shade Mode Look Up Table Architecture 73 Figure 11 4 Look Up Table Bypass Mode Architecture o o e 74 Figure 11 5 2 Level Color Look Up Table Architecture o o ooo 75 Figure 11 6 4 Level Color Mode Look Up Table Architecture o o 76 Figure 11 7 16 Level Color Mode Look Up Table Architecture o o o 77 Figure 11 8 256 Level Color Mode Look Up Table Architecture o 78 Figure 12 1 Relationship Between The Screen Image and the Image Refreshed by S1D13704 79 Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by S1D13704 81 Figure 13 1 Panel On Off Sequence 2 2 a 86 Figure 14 1 Mechanical Drawing QFP14 0 00 00 000000000004 88 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 9 Vancouver Design Center 1 Introduction 1 1 Scope This is the Functional Specification for the S1D13704 Embedded Memory LCD Controller Chip Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descri
65. TFD Panel Timing Registers 8 1 Register Mapping 8 2 Register Descriptions Frame Rate Calculation Display Data Formats Look Up Table Architecture lt lt 11 1 Gray Shade Display Modes 11 2 Color Display Modes SwivelView 12 1 Default SwivelView Mode 12 1 1 How to Set Up Default SwivelView Mode 12 2 Alternate Swivel View Mode B A lah A 12 2 1 How to Set Up Alternate SwivelView Mode 12 3 Comparison Between Default and Alternate SwivelView Modes 12 4 SwivelView Mode Limitations Power Save Modes eee nee 13 1 Software Power Save Mode 13 2 Hardware Power Save Mode 13 3 Power Save Mode Function Summary 13 4 Panel Power Up Down Sequence 13 5 Turning Off BCLK Between Accesses 13 6 Clock Requirements Mechanical Data S1D13704 X26A A 001 04 Generic 1 Interface TiMiNg Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table 5 1 Table 5 2 Table 5 3 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 7 8 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 11 1 Table 12 1 List of Tables Summary of Power On Reset Options Host Bus Interface Pin
66. Table 3 1 Host Bus Interface Pin Mapping Sir athe Generic 2 Description AB 15 1 A 15 1 Address 15 1 ABO AO Address AO DB 15 0 D 15 0 Data WE1 BHE Byte High Enable CS External Decode Chip Select BCLK BCLK Bus Clock BS n c Must be tied to lO Vpp RD WR n c Must be tied to lO Vpp RD RD Read WEO WE Write WAIT WAIT RESET RESET For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx Interfacing to an 8 bit Processor Issue Date 01 02 12 1D13704 X26A G 013 02 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic 2 Interface Mode 1D13704 X26A G 013 02 Generic 2 Host Bus Interface is a general non processor specific interface mode on the S1D13704 that is ideally suited to interface to an 8 bit processor bus The interface requires the following signals e BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13704 It is separate from the input clock CLKD and is typically driven by the host CPU system clock If the host CPU bus does not provide this clock an asynchronous clock can be provided e The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order d
67. The physical display does not need to be a power of two wide The difference can be treated as a virtual width In addition scrolling in default SwivelView mode is restricted to two lines Alternate Swivel View mode requires more power as the internal clocks are run faster In return for a higher power consumption the power of two width restriction is removed Also the display can be scrolled one line at a time One benefit to removing the power of two width restriction is that panels which might not have been able to be used in SwivelView mode due to a lack of memory may now be used Clocking for the 1D13704 works as follows An external clock source supplies CLKI the input clock CLKT is routed through the Input Clock Divide from Mode Register 1 REG 02h bit 4 and is either divided by two or passed on This signal is now the Operating Clock CLK from which PCLK and MCLK are derived In SwivelView mode the CLK signal may be divided down by 0 2 4 or 8 before PCLK and MCLK are derived SwivelView mode offers additional clocking control over landscape mode One reason for the additional support is to maintain a register set that was backward compatible with previous Epson LCD controllers When setting SwivelView mode it is possible that the horizontal and vertical non display time must be recalculated as a result of PCLK changing in response to the SwivelView mode selected or the clock selection method Programming Notes and Examples
68. These bits specify the number of lines between the last line of display data FPDAT and the leading edge of FPFRAME This register is effective in TFT D TFD mode only REG O1h bit 7 1 FPFRAMEposition lines REG 09h The contents of this register must be greater than zero and less than or equal to the Vertical Non Display Period Register i e 1 lt REG 09h lt REG OAh 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 61 REG OAh Vertical Non Display Period Address FFEAh Read Write Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Display n a Display Display Display Display Display Display Status Period Bit5 Period Bit4 Period Bit3 Period Bit 2 Period Bit 1 Period Bit 0 bit 7 Vertical Non Display Status This bit 1 during the Vertical Non Display period bits 5 0 Vertical Non Display Period These bits specify the vertical non display period VerticalNonDisplayPeriod lines REG OAh Note This register should be set only once on power up during initialization REG OBh MOD Rate Register Address FFEBh Read Write wa nla MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 MOD Rate Bits 5 0 When the value of this register is 0 the MOD output signal toggle
69. Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the S1D13704 with other CPUs For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Interface Mode Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13704 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13704 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and W
70. a a g 8888 a Lt i ii i HEL a 3 S A loo 4 d 2 ARI E a oo DS E 8 g 5 p Z a Es 2 A A 3 E a 9 AH HHI lo f t ta Ll 8 E g al A man E oc vs y 3 5 E ll lo Hl H I a a AN g g a H ogo a 3 E 9 o E a a ES pii E var E am m fi 5 E ono z a E a J Figure 8 1 S1D13704B00C Schematic Diagram 1 of 4 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Page 21 Epson Research and Development Vancouver Design Center 1D13704 3 z z y i E z 1397 SOU 8661 780 1990390 APDTAS 13329 o t a nox 1 ozrg STOPESHIIM TOPRAMUADTIENTeAT 01 asu sng tass our eam _uosdal gt AQT ANT zo F AE E L PLATOS a 2000 T agi WOpNOD amaata op de nvazdza HAGA AGEGE loc SE 4 SNe TAs ACEES ve EE TITS IRE zoa E 5 OTAGO AT oe 6z ez LZ 92 sz vz EZ zz TZ oz 6 81 er 6 9 S M t Y E E oe HOIDINNOD GOI ONOW OTOS G A ATAVIDITES X26A G 005 03 Figure 8 2 S1
71. a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents WA INTFOGUCTION z ras fa ta erased ein as AA IEE ee ae eS e a ee 7 2 Interfacing to the MC68328 2 ee 8 2 1 The MC68328 System Bus o 8 2 2 Chip Select Modules a o a ala od te As a a at dS 3 S1D13704 Host Bus Interface es 9 3 1 Bus Interface Modes 2 0 2 0 0 000000 9 3 2 Generic l Interface Mode 2 2 2 2 LO 3 3 MC68K 1 Interface Mode 2 2 2 F 4 MC68328 To S1D13704 Interface o ee es 12 4 1 Hardware Description a a a ee ee ee 12 4 1 1 Using The MC68K 1 Host Bus Interface o o 12 4 1 2 Using The Generic 1 Host Bus Interface o e 13 4 2 S1D13704 Hardware Configuration 2 14 4 3 MC68328 Chip Select Configuration 2 2 2 2 2 2 14 SoftWare ai pe A ae ee A ae Bn a ie a a aw eae ae 15 References ee Gao ag ee a aed Se a eth ae DAS aes Av Sse a ee 16 6 1 Documents 0 0000000200 2 2 16 6 2 D
72. allows two different images to be simultaneously displayed Virtual display support displays images larger than the panel size through the use of panning Maximum operating clock CLK frequency of 25MHz Operating clock CLK is derived from CLKI input CLK CLKI or CLK CLKI 2 Pixel Clock PCLK and Memory Clock MCLK are derived from CLK 2 6 Miscellaneous 2 7 Package Hardware Software Video Invert Software Power Save mode Hardware Power Save mode LCD power down sequencing 5 General Purpose Input Output pins are available e GPIOO is available if Hardware Power Save is not required e GPIO 4 1 are available if upper LCD data pins FPDAT 11 8 are not required for TFT D TFD support or Hardware Video Invert IO Operates from 3 0 volts to 5 5 volts Core operates from 3 0 volts to 3 6 volts 80 pin QFP14 package Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 12 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator x SH 4 3 BUS CSnit p CS A 15 0 gt AB 15 0 D 15 0 gt DB 15 0 FPDAT 7 0 gt 70 LD FPSHIFT vost qi S1D13704 _ BS gt BS 8 bit hoes S Rowa FPFRAME FPFRAME LCD FPLINE gt FPLINE RD gt RD
73. and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13704 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to an 8 bit Processor Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design Center 4 8 Bit Processor to S1D13704 Interface 4 1 Hardware Description The interface between the S1D13704 and an 8 bit processor requires minimal glue logic A decoder is used to generate the chip select for the S1D13704 based on where the 1D13704 is mapped into memory Alternatively if the processor supports a chip select module it can be programmed to generate a chip select for the S1D13704 without the need of an address decoder An inverter inverts AO to generate the Byte High Enable signal for the S1D13704 If the 8 bit host interface has an active high WAIT signal it must be inverted as well In order to support an 8 bit microprocessor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical implementation of an 8 bit processor to S1D13704 interface Note Generic 8 bit Bus 1D13704 A 15 0 gt AB 15 0 D 7 0 1 DB 7 0 DB 15 8 Decoder gt cs WAITH lt 4 WAIT WE gt WEO RD
74. and other factors the higher the BUSCLK the higher the CPU performance and power consumption Vpp voltage levels Core and IO the voltage level of the Core and IO sections in the S1D13704 affects power consumption the higher the voltage the higher the consumption Display mode the resolution panel type and color depth affect power consumption The higher the resolution color depth and number of LCD panel signals the higher the power consumption Note If the High Performance option is turned on the power consumption increases to that of 8 bit per pixel mode for all color depths There are two power save modes in the S1D13704 Software and Hardware Power Save The power consumption of these modes is affected by various system design variables e CPU bus state during Power Save the state of the CPU bus signals during Power Save has a substantial effect on power consumption An inactive bus e g BUSCLK low Addr low etc reduces overall system power consumption e CLKI state during Power Save disabling the CLKI during Power Save has substantial power savings 1D13704 X26A G 006 02 Page 4 Epson Research and Development Vancouver Design Center 1 1 Conditions Table 1 1 S1D13704 Total Power Consumption below gives an example of a specific environment and its effects on power consumption Table 1 1 S1D13704 Total Power Consumption Test Condit
75. are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction ara Sere eee ata Hak a a fee EE A e 7 2 InMaliZatlON lt lt c i A Bs Ssh ae ia Seca ek A AA 8 2 1 Frame Rate Calculation o LD 3 Memory Models 13 hs 6 ak Se a we ee ee ee oe ee OA 11 3 1 Display Buffer Location g Ap eh athe re 4 er a a ey Se eee ML 3 1 1 1 Bit Per Pixel 2 Colors Gray Shades O O AN 11 3 1 2 2 Bit Per Pixel 4 Colors Gray Shades o o e 12 3 1 3 4 Bit Per Pixel 16 Colors Gray Shades o e 12 3 1 4 Eight Bit Per Pixel 256 Colors o o e e 13 4 Look Up Table LUT 000 a ee ee 14 4 1 Look Up Table Registers Das as ata Bons J ae ge Se ee ae A 4 2 Look Up Table LUT AN ANA A ts whe O 5 Advanced Techniques 2 22 ee eee 25 Sil Virtual Display ada a ra Pa a ar a A d Ge 2S DAL gt REPISIOIS 4 a A OR on BR Oo e do A ee Le 26 D1 2 EXAMpleS ar
76. are well documented in Motorola s user manuals and will not be described here A brief summary of the new signals appears below e Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The S1D13704 implements the MC68000 bus interface using its MC68K 1 mode so this mode may be used to connect the MC68328 directly to the S1D13704 with no glue logic However several of the MC68000 bus control signals are multiplexed with IO and interrupt signals on the MC68328 and in many applications it may be desirable to make these pins available for these alternate functions This requirement may be accommodated through use of the Generic 1 interface mode on the 1D13704 2 2 Chip Select Module The MC68328 can generate up to 16 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s a
77. dia o ed rl e AL 2 3 1 General Purpose Chip Select Module le GPCM bigs sy sissy o fete tea RY 11 2 3 2 User Programmable Machine UPM 0 0200004 12 3 1D13704 Host Bus Interface 13 3 1 Host Bus Interface Modes sua i takon a Aun ee 13 3 2 Generic 1 Host Bus Interface Mode 2 2 2 2 2 2 22 2 2 2 2 2 14 4 MPC821 to S1D13704 Interface naana 15 4 1 Hardware Description ee eee LS 4 2 Hardware Connections notin Hite fade a Bate a ee IN is O 4 3 1D13704 Hardware CEON i Pag aa ioi Aia Spe ise Ber ro aa Dado ak e y lG 4 4 MPC821 Chip Select Configuration a a a a a a 19 a Test OL Ware soa a We a wa et r a ae oe ok AP ee e as ZO 5 DONWANE 0 Ss E A a ee ca Se eS ee a A 22 ReTerentes cios y ds ee ae o Sh acne atic e id eae we Rt Gy Wy es an 23 6 1 Documents e ay an chee al we ay ie er a a A oe a ae a ad 23 602 Document Sources 23 T Technical SUpport stiri ra e s a a eaaa o a et a A Se AA a at e 24 7 1 EPSON LCD CRT Controllers S1D13704 2 24 7 2 Motorola MPC821 Processor gt s oca sa sors ee 2 A Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Dat
78. edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 timm 18min 9Ts 3 83min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 4 Ts 5 t7min REG O8h bits 4 0 x 8 13 Ts 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 41 Vancouver Design Center 7 3 5 Single Color 4 Bit Panel Timing VDP VNDP FPFRAME FPLINE l fl l l l L l l l fl l fl DRDY MOD X ES X FPDAT 7 4 A LINE1 X LINE2 X LINES X LINE4 XLINE479X LINE480 A LINE1 X LINE2 X FPLINE DRDY MOD 7 a HDP x HNDP j al at LI LILI LI LI MAA rios FPDAT7 o 1 R1X 1 62 X 1 B3 X x X aS X X1 B319 FPDAT6 Pez 1 G1X 1 B2 X_1 R4 x 4 Y MI R320 FPDAT5 OS 1 81 X 1 R3 X 1 G4X KX XA FPDAT4 a 1 R2X_1 G3X_1 B4 x X X X1 B320 o Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 14 Single Color 4 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification
79. ee 47 9 2 2 Miscellaneous HAL Support 0 000000000004 49 9 2 3 Advanced HAL Functions 0 020002 ee ee eee 52 9 2 4 Register Memory Access 2 2 0 00 2 ee ee 55 O 2 5 gt POWEr Saves erre te ety eye Gage Pee hg diate eo Oke Woe alate Ge ds 58 ODO MDraWwi 8 ti Gosek chelsea bee a Beth ee Ghee deve tik Seopa Se athe 58 9 2 7 LUT Manipulation ceo 8a BA a ee ee ee Bes 59 10 Sample Code e tentar bk tes os ek a A A I i 61 10 1 Introduction 02 e 44 4 amp cas ar aa a 6 10 1 1 Sample code using the S1D13704 HAL API o o 61 10 1 2 Sample code without using the S1D13704 HALAPT 64 10 1 3 Header Files ia a Hae ee Sa BO Ace Es eG AAA 72 S1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Table 2 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 5 1 Table 7 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 7 1 Figure 7 2 List of Tables S1D13704 Initialization Sequence e 2 Bpp Banking Scheme e 4 Bpp Banking SchemMe p gernes dd ae a oa a we 8 Bpp Banking Scheme e Look Up Table Configurations o e Recommended LUT Va
80. hardware REG 1Bh SwivelView Mode Register Address FFFBh Read Write SwivelView SwivelView SwivelView SwivelView ris nia na reseed Mode Pixel Mode Pixel Mode Enable Mode Select Clock Select Clock Select Bit 1 Bit O bit 7 SwivelView Mode Enable When this bit 1 Swivel View Mode is enabled When this bit 0 Landscape Mode is enabled bit 6 SwivelView Mode Select When this bit 0 Default Swivel View Mode is selected When this bit 1 Alternate SwivelView Mode is selected See Section 12 Swivel View on page 79 for further information on SwivelView Mode The following table shows the selection of Swivel View Mode Table 8 8 Selection of SwivelView Mode SwivelView SwivelView Mode Enable Mode Select Mode REG 1Bh bit 7 REG 1Bh bit 6 0 X Landscape 1 0 Default SwivelView 1 1 Alternate SwivelView bit 2 reserved reserved bits must be set to 0 bits 1 0 SwivelView Mode Pixel Clock Select Bits 1 0 These two bits select the Pixel Clock PCLK source in Swivel View Mode these bits have no effect in Landscape Mode The following table shows the selection of PCLK and MCLK in SwivelView Mode see Section 12 SwivelView on page 79 for details 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table 8 9 Selection of PCLK and MCLK in Swivel View Mode P
81. image in a 256x64 viewport Refer to Section 2 Initialization on page 8 and Section 5 1 Virtual Display on page 25 for assistance with these settings The examples are shown in a C like syntax Example 3 Panning Right and Left To pan to the right increase the start address value by one To pan to the left decrease the start address value Keep in mind that with the exception of 8 bit per pixel SwivelView mode the display will jump by more than one pixel as a result of changing the start address registers Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 29 Vancouver Design Center Panning to the right StartWord GetStartAddress StartWord SetStartAddress StartWord Panning to the left StartWord GetStartAddress StartWord if StartWord lt 0 StartWord 0 SetStartAddress StartWord Example 4 Scrolling Up and Down To scroll down increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line To scroll up decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line Step 1 Determine the number of words in one virtual scanline bytes_per_line pixels_per_line pixels_per_byte 320 2 160 words_per_line bytes_per_line 2 160 2 80 Step 2 Scroll up or down To scroll up StartWord GetStartAddress StartWord words
82. is easily interfaced to the PR31500 PR31700 with minimal additional logic The address bus of the PR31500 PR31700 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS latch e g 74 ACT373 The direct connection approach makes use of the S1D13704 in its Generic Interface 2 configuration The following diagram demonstrates a typical implementation of the interface S1D13704 3 3V PR31500 PR31700 t____ 1O Vpp CORE Vpp RD gt RD WE gt WE CARD1ICSL CARD1CSH gt BHE IO Vppt__ BS IO Voot RD wR ENDIAN System RESET gt RESET sae Latch D gt CS A12 gt AB 15 13 i pa gt a D 31 24 4 gt DB 7 0 D 23 16 gt DB 15 8 Voo pull up CARD1WAIT pa WAIT DCLKOUT See text CLKI gt Glock divider gt OF Oscillator BOLK 1D13704 X26A G 012 02 Figure 2 1 SID13704 to PR31500 PR31700 Direct Connection The Generic 2 host interface control signals of the S1D13704 are asynchronous with respect to the S1D13704 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maxim
83. is selected REG 01h bit 5 1 2 This bit REG O1h bit 2 1 bits 1 0 Data Width Bits 1 0 These bits select the display data format See Table 8 1 Panel Data Format below Table 8 1 Panel Data Format Data Width Data Width Mabel nesoni romero OC O Function REG 01h bit 1 REG 01h bit 0 o 0 Mono Single 4 bit passive LCD 1 Mono Single 8 bit passive LCD i 0 reserved 1 reserved y 0 reserved i i 1 Mono Dual 8 bit passive LCD 0 reserved 1 reserved d 0 0 Color Single 4 bit passive LCD 5 1 Color Single 8 bit passive LCD format 1 0 reserved i 1 Color Single 8 bit passive LCD format 2 0 reserved y 1 Color Dual 8 bit passive LCD 0 reserved 1 reserved 0 9 bit TFT D TFD panel 1 X don t care 7 1 12 bit TFT D TFD panel Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Epson Research and Development Page 56 Vancouver Design Center REG 02h Mode Register 1 Address FFE2h Read Write Hardware Video Invert Enable Input Clock divide CLKI 2 Software Video Invert Frame Repeat Bit Per Pixel Bit O Bit Per Pixel Bit 1 High Performance Display Blank bits 7 6 Bit Per Pixel Bits 1 0 These bits select the color or gray shade depth Display Mode Table 8 2 Gray Shade Color Mode Selection Color Mono REG 01h bit 6 Bit Per Pixel Bit 1 REG 02h bit 7 Bit Per Pixel Bit 0 Display Mode
84. long integer to the last byte of usable display memory This function is a holdover from 1350X products which support different amounts of memory DevID registered device ID plLastByte pointer to a long integer to receive the offset to the last byte of display memory 1D13704 X26A G 002 03 Page 52 Return Value Epson Research and Development Vancouver Design Center ERR_OK operation completed with no problems int seSetHightPerformance int DevID BOOL OnOff Description Parameters Return Value This function call enables or disable the high performance bit of the S1D13704 When high performance is enabled then MCIk equals PCIK for all video display resolutions In the high performance state CPU to video memory performance is improved at the cost of higher power consumption When high performance is disabled then MClk ranges from PClk 1 at 8 bit per pixel to PCIK 8 at 1 bit per pixel Without high performance CPU to video memory accessed speeds are slower but the S1D13704 uses less power DevID registered device ID OnOff a boolean value defined in HAL H to indicate whether to enable of disable high performance ERR_OK operation completed with no problems 9 2 3 Advanced HAL Functions Advanced HAL functions include the functions to support split virtual and rotated displays While the concept for using these features is advanced the HAL makes actually using them easy int seSetHWRotate int De
85. mode the lower 8 positions of the Red Look Up Table is arranged into four banks each with two positions These two bits select which bank is used for display data In 2 bpp color mode the 16 position Red Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Red Look Up Table is arranged into two banks each with eight positions Red Bank Select bit 0 selects which bank is used for display data Green Bank Select Bits 1 0 In 1 bit per pixel bpp color gray mode the lower 8 positions of the Green Look Up Table is arranged into four banks each with two positions These two bits select which bank is used for display data In 2 bpp color gray mode the 16 position Green Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Green Look Up Table is arranged into two banks each with eight positions Green Bank Select bit 0 selects which bank is used for display data Blue Bank Select Bits 1 0 In 1 bit per pixel bpp color mode the lower 8 positions of the Blue Look Up Table is arranged into four banks each with two positions These two bits select which bank is used for display data In 2 bpp color mode the 16
86. offset in bytes to the start of screen 2 ERR_OK operation completed with no problems It is assumed that the system has been properly initialized prior to calling seSplitInitO int seSplitScreen int DevID int Screen int VisibleScanlines Description Parameters Return Value Note Changes the relevant registers to adjust the split screen according to the number of visible lines requested WhichScreen determines which screen 1 or 2 to base the changes on The smallest surface screen can display is one line This is due to the way the S1D13704 operates Setting Screen 1 Vertical Size to zero results in one line of screen being displayed The remainder of the display will be screen 2 image DevID registered device ID Screen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 VisibleScanlines number of lines to display for the selected screen ERR_OK operation completed with no problems ERR_HAL_BAD_ARG argument VisibleScanlines is negative or is greater than vertical panel size or WhichScreen is not SCREEN1 or SCREEN 2 seSplitInit must be called before calling seSplitScreen Programming Notes and Examples Issue Date 01 02 12 1D13704 X26A G 002 03 Page 54 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center int seVirtInit int DevID DWORD VirtX DWORD VirtY Description This function prepares the system for virtual screen operation The programmer
87. passes the desired virtual width in pixels as VirtX When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width Parameter DevID registered device ID VirtX horizontal size of virtual display in pixels Must be greater or equal to physical size of display VirtY pointer to an integer to receive the maximum number of displayable lines of VirtX width Return Value ERR_OK operation completed with no problems ERR _HAL_BAD_ARG returned in three situations 1 the virtual width VirtX is greater than the largest possible width VirtX varies with color depth and ranges from 4096 pixels wider than the panel at 1 bit per pixel down to 512 pixels wider than the panel at 8 bit per pixel 2 the virtual width is less than the physical width or 3 the maximum number of lines becomes less than the physical number of lines Note The system must have been properly initialized prior to calling seVirtInit int seVirtMove int DevID int Screen int x int y Description This routine pans and scrolls the display after a virtual display has bee setup In the case where split screen operation is being used the WhichScreen argument specifies which screen to move The x and y parameters specify in pixels the starting location in the virtual image for the top left corner of the applicable display Parameter DevID registered device ID Screen must be set to 1 or 2 or use th
88. position Blue Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Blue Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Page 67 Vancouver Design Center REG 17h Look Up Table Data Register Address FFF7h Read Write Look Up Look Up Look Up Look Up n a n a n a n a Table Data Table Data Table Data Table Data Bit 3 Bit 2 Bit 1 Bit 0 bits 3 0 Look Up Table Data Bits 3 0 This register is used to read write the RGB Look Up Tables This register is an aperture into the three 16 position Look Up Tables The Look Up Table Address Register REG 16h selects which Look Up Table position is accessible See REG 16h Look Up Table Bank Select Register on page 66 REG 18h GPIO Configuration Control Register Address FFF8h Read Write ava A m a GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin lO GPIO1 Pin IO GPIOO Pin IO Configuration Configuration Configuration Configuration Configuration bits 4 0 GPIO 4 0 Pin IO Configuration These bits determine the direction of the GPIO 4 0 pins When GPIOn Pin IO Configuration bit 0 the corresponding
89. property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to an 8 bit Processor X26A G 013 02 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T troduction z rals a et aa ae Rite TR an ae EES BR ae aS fe ee 7 2 Interfacing to an 8 bit Processor eee ee 8 2 1 The Generic 8 bit Processor System Bus 2 2 8 3 S1D13704 Bus Interface 4 4 9 3 1 Host Bus Pin Connection o 9 3 2 Generic 2 Interface Mode 2 2 2 2 LO 4 8 Bit Processor to S1D13704 Interface lt lt ce eee ees 11 4 1 Hardware Description 0 200 022 2222 11 4 2 S1D13704 Hardware Configuration 2 2 ee 12 4 3 Register Memory Mapping 2 2 1 SoftWare iaa hire aetna et abe gS as ated ie Cee oy oe te wR tea 13 6 References seu Spoke id A Sy hee a We te a 14 Ol Documents 25 woe reene A A A ee Se 4 A 62 Document Sources o 14 7 Technical Support 1 00 22 220 eee ele eee ee el Sw Pee en 15 7 1 Epson LCD CRT Controllers S1D13704 2 0 0 2 020222 22 2 2 2 15 Interfacing to an 8 bit Processor 1D13704 Issue Date 01 02 12 X26A G 013 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to an
90. registers 5 Type x 5 to read register 5 6 Type x 3 10 to write 10 hex to register 3 7 Type f 0400 aa to fill the first 400 hex bytes of display memory with AA hex 8 Type f 0 a000 aa to fill 40k bytes of display memory 9 Type r 0 ff to read the first 100 hex bytes of display memory 10 Type q to exit the program 13704PLAY Diagnostic Utility 1D13704 Issue Date 01 02 08 X26A B 005 03 Page 6 Scripting Comments 1D13704 X26A B 005 03 Epson Research and Development Vancouver Design Center 13704PLAY can be driven by a script file This is useful when e there is no standard display output to monitor command entry and results e various registers must be quickly changed faster than can achieved by typing e The same series of keystrokes is being entered time and again A script file is an ASCU text file with one 13704PLA Y command per line All seripts must end with a q quit command in order to return control to the operating system The semi colon is used as a comment delimitor Everything on a line after the semi colon will be ignored On a PC platform a typical script command line is 13704PLAY lt dumpregs scr gt results This causes the script file dumpregs scr to be interpreted and the results to be sent to the file results Example 1 The script file dumpregs scr can be created with and text editor and will look like the following This file initia
91. sees a 240x320 image and how the image is displayed The application image is written to the S1D13704 in the following sense A B C D The display is refreshed by the S1D13704 in the following sense B D A C physical memory start address ss gt A JA B E Ww 4 o SwivelView cs a co 9 window z A display 56 Q start a 3 Si address 3 3 lt n o g C D y 4 320 5 240 image seen by programmer image refreshed by S1D13704 256 image in display buffer Figure 7 1 Relationship Between The Screen Image and the Image Refreshed by SID13704 7 3 Alternate SwivelView Mode Programming Notes and Examples Issue Date 01 02 12 Alternate Swivel View Mode may be used when the virtual image size of Default Swivel View Mode cannot be contained in the 40k Byte integrated frame buffer For example when the panel size is 240x160 and the display mode is 8 bit per pixel the minimum virtual image size for Default SwivelView Mode would be 240x256 which requires 60K bytes Alternate Swivel View Mode requires a panel size of only 240x160 which needs only 38 400 bytes Alternate Swivel View Mode requires the memory clock MCLK to be at least twice the frequency of the pixel clock PCLK i e MCLK gt 2 x PCLK Because of this the power consumption in Alternate Swivel View Mode is higher than in Default SwivelView Mode The following figure shows how the programmer sees a 240x160 image and
92. the Toshiba MIPS TX3912 Processor Issue Date 01 02 12 EPSON Research and Development Vancouver Design Center 2 2 Memory Mapping and Aliasing Page 9 The S1D13704 requires an addressing space of 64K bytes The on chip display memory occupies the range 0 through 9FFFh The registers occupy the range FFEOh through FFFFh The TX3912 demultiplexed address lines A16 and above are ignored thus the S1D 13704 is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space In this example implementation the TX3912 control signal CARDREG is ignored the S1D13704 also takes up the entire PC Card slot configuration space Note If aliasing is undesirable additional decoding circuitry must be added 2 3 S1D13704 Configuration and Pin Mapping The S1D13704 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the D13704 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to the direct connection approach Table 2 1 S1D13704 Configuration for Direct Connection S1D13704 Value hard wired on this pin is used to configure Configuration Pin 1 IO Vpp 0 Vss Generic 1 Big Endian CNF 2 0 EA configuration for Toshiba TX3912 host bus interface When the S1D13704 is configured for
93. the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Performance Nominal performance Higher performance than Default Mode 12 4 SwivelView Mode Limitations The only limitation to using SwivelView mode on the 1D13705 is that split screen operation is not supported Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 84 Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13704 to accommodate the need for power reduction in the hand held devices market These modes are enabled as follows Table 13 1 Power Save Mode Selection Hardware Power Software Power Software Power Save Save Bit 1 Save Bit 0 Not Configured or 0 Mode Software Power Save Mode Not Configured or 0 reserved 0 0 0 1 Not Configured or 0 1 0 reserved 1 1 X X Not Configured or 0 Normal Operation Configured and 1 Hardware Power Save Mode 13 1 Software Power Save Mode Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer Table 13 2 Software Power Save Mode Summary e Registers read write accessible e
94. the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13704 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D 13704 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13704 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the S1D13704 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design C
95. the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Page 23 Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM AD available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc S1D 3704 Embedded Memory LCD Controller Hardware Functional Specification Document Number X126A A 002 xx Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Research and Development Website http www erd epson com Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 24 7 Technical Support 7 1 EPSON LCD CRT Cont
96. to appear to slide down Both panning and scrolling are performed by modifying the start address register Start address refers to the word offset in the display buffer where the image will start being displayed from The start address registers in the S1D13704 are an offset to the first word to be displayed in the top left corner of every frame Keep in mind that the start address is a word offset Changing the start address by one means a change of one words worth of pixels The number of pixels in word varies according to the color depth At 1 bit per pixel a word contains sixteen pixels At 2 bit per pixel there are eight pixels at 4 bit per pixel there are four pixels and at 8 bit per pixel there are two pixels The number of pixels in each word represent the finest panning step the S1D13704 is capable of i e at 4 bit per pixel the display will move sideways by four pixels for each change to the start address registers When SwivelView mode see Swivel View on page 36 is enabled the start address registers become offsets to bytes In this mode the step rate for the start address registers if halved making for smoother panning Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 28 5 2 1 Registers Epson Research and Development Vancouver Design Center REG 0Ch Screen 1 Display Start Address 0 LSB Start Addr Start Addr Start Addr Start Addr Start Addr Start Add
97. to provide an interface between the S1D13704 Embedded Memory Color Graphics LCD Controller and the Toshiba MIPS TX3912 Processor For further information on the S1D13704 refer to the 7D13704 Hardware Functional Specifi cation document number X26A A 001 xx For further information on the TX3912 contact Toshiba or refer to the Toshiba website under semiconductors at http www toshiba com taec nonflash indexproducts html For further information on the ITE IT8368E refer to the JT8368E PC Card GPIO Buffer Chip Specification 1 1 General Description The Toshiba MIPS TX3912 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the S1D13704 connects to the TX3912 processor The S1D13704 can be successfully interfaced using one of two configurations e Direct connection to TX3912 see Section 2 Direct Connection to the Toshiba TX3912 on page 8 e System design using one ITE IT8368E PC Card GPIO buffer chip see Section 3 System Design Using the ITE IT8368E PC Card Buffer on page 10 Interfacing to the Toshiba MIPS TX3912 Processor 1D13704 Issue Date 01 02 12 X26A G 004 02 Page 8 EPSON Research and Development Vancouver Design Center 2 Direct Connection to the Toshiba TX3912 2 1 General Description In this example implementation the S1D13704 occupies the TX3912 PC Card slot 1 The S1D13704 is easily interfaced to the TX3912 with minimal additional logic Th
98. v5 0 3 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 4 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK Alternately use the current DEMO project included with the ETK Follow the steps below to create a X86 DEMO shortcut on the Windows NT v4 0 desktop which uses the current DEMO project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon X86 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO by right click ing on the icon and choosing rename Windows6 CE Display Drivers S1D13704 Issue Date 01 02 08 X26A E 001 02 Page 4 1D13704 X26A E 001 02 Epson Research and Development Vancouver Design Center h Right click on the icon X86 DEMO7 and click on Properties to bring up the X86 DEMO7 Properties window i Replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish Create a sub directory named 4BPP13704 under wince platform cepc drivers dis play Copy the source code to the 4BP
99. 0 There is no installation program for 13704CFG Installation to a local drive is done by copying 13704CFG EXE and 13704CFG HL P to your hard drive and optionally creating a link on the Windows desktop for easy access to the program Open the drive and folder where you copied 13704CFG EXE and double click the icon to start the program Optionally if you created a link to the program on your desktop double click the link icon 13704CFG EXE Configuration Program Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 13704CFG Page 7 The 13704CFG window has four main sections Panel information includes Dimensions LookUp Table Miscellaneous Options and System settings TAN Lordi C Mora Calor Single Dual D Mak FPSHIFT Fo Foma 2 Fiame Aepial Mod Couri Misc Options D Heat Video imen Enable D Hi Pow Save Erbin High Petioemance FT Parigi Moda i STH C aB i TFT FT pbi FPLine Sts FPFrame Sbai Polarty Hi Lo Flie e Frae C System Memory Location Fiama Fale fp leput Clock kHz Dimensions Ca Look lla Table C 1BPF IBP Cabre aa6PR Bypess LUT Open Save Esi Help Figure 1 13704CFG Window The following sections describe each of the main sections of the configuration dialog box 13704CFG EXE Configuration Program Issue Date 01 02 08 1D13704 X26A B 001 02 Page 8 Panel Information S1D13704 X26
100. 0 endif endif 7 SIZE_VERSION is the size of the version string eg 1 00 SIZE _STATUS is the size of the status string eg b for beta SIZE_REVISION is the size of the status revision string eg 00 E define SIZE_VERSION5 define SIZE_STATUS 2 define SIZE_REVISION3 ifdef ENABLE_DPF Debug_printf define DPF exp printf fexp n define DPF1 exp printf ftexp d n exp define DPF2 expl exp2 printf texpl d xp2 Sd n expl exp2 define DPFL exp printf fexp x n exp else define DPF exp void 0 define DPF1 exp void 0 define DPFL exp void 0 endif Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 74 Epson Research and Development Vancouver Design Center enum ERR_HAL_BAD_ARG ERR_TOOMANY_DEVS BORK KKK KK RK KK KR RK kkk k kkk k kkk k Definitions for seGetId A define PRODUCT_ID 0x18 enum ID_UNKNOWN ID_S1D13704 ID_S1D13704F00A defin AX_MEM_ADDR 40960 1 define FORTY_K 40960 defin AX_DEVICE 10 defin SE_RSVD 0 DetectEndian is used to determine whether th and least significant bytes ar El define ENDIAN 0x1234 define REV_ENDIAN 0x3412 BOK kkkkkkkkkk kkk kkk kk RR kkk kk kkk kkk k kkk k kkk k Definitions for Internal calculations
101. 00 0x00 BLACK S1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 65 Vancouver Design Center 0x00 0x00 Ox0F BLUE Ff 0x00 Ox0F 0x00 GREEN 0x00 0Ox0F 0x0F LT CYAN OxOF 0x00 0x00 LT RED OxOF 0x00 0x0F LT PURPLE OxOF Ox0F 0x00 LT YELLOW OxOF OxOF Ox0F LT WHITE y Register data for the configuratin described above These values were generated using 1374CFG EXE The sample code uses these values but does not refer to this array ES unsigned char Reg 0x20 0x00 0x23 OxBO 0x03 0x27 OxEF 0x00 0x00 0x1E 0x00 Ox3B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 y Useful definitions constants and macros to make the sample code easier to follow Af define MEM_OFFSET 0x01374B0B Location is platform dependent define REG_OFFSET MEM_OFFSET OxFFEO Memory offset 64K 0x20 RA define MEM_SIZE 0xA000 40 kb display buffer typedef unsigned char BYTE Some usefule typedefs typedef BYTE far LPBYTE typedef unsigned short WORD define LOBYTE w BYTE w define HIBYTE w BYTE WORD w gt gt 8 amp OxF
102. 01 02 12 X26A G 009 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 Summary of Power On Reset Options e o 13 Table 4 2 Host Bus Interface Selection 2 2 0 ee 13 List of Figures Figure 2 1e PC Card ReadiGycle strass eue Petey Shee ht ea eT oe es Fo ee a 9 Figure 2 2 PC Card WriteCycle 2 ee 9 Figure 4 1 Typical Implementation of PC Card to S1D13704 Interface 12 Interfacing to the PC Card Bus 1D13704 Issue Date 01 02 12 X26A G 009 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com f
103. 02 SystemBus 8 DIJE COVELVIEW veian da ds se AA 8 2 1 2 LCD Memory Access Cycles o o e 9 3 1D13704 Host Bus Interface lt lt lt lt 10 3 1 Bus Interface Modes o O 3 2 Generic 2 Interface Mode o o oe ats ioe aca a A aa E e a e a 11 4 VR4102 to S1D13704 Interface naonao 13 4 1 Hardware Description a a aaa 18 4 2 S1D13704 Hardware Configuration a a a a a a a aaa 14 4 3 NEC VR4102 Configuration 2 a a a ee ee 5 5 DOUWAIE A ee E ae oe es a aie E 16 Reterenc s 2 iu ied o eae do at nan we BC ey yee ee da 17 6 1 Documents Taarer a A ee te AL ie er a Gn ee Ae eA a ie Pe a A 6 2 Document Sources 1 2 ee 17 7 Technical Support 2 32 46 eo kee eee A Ra ete ee Pew eee Bae eee 18 7 1 Epson LCD Controllers S1D13704 2 2 2 20 2 2 2 18 72 NEC Electronics Inc 2 1 ee ee ee ee ew 18 Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the NEC VR4102 Microprocessor X26A G 008 05 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 020002 002 eee 10 Table 4 1 Summary of Power On Reset Options 0 20000 022 eae
104. 04 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the D13704 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the MPC821 interface The settings are very similar to the ISA bus with the following exceptions e the WAIT signal is active high rather than active low e the Power PC is big endian rather than little endian Table 4 2 Configuration Settings Signal Low High CNFO CNF1 CNF2 See Host Bus Selection table below CNF3 Little Endian CNF4 Active low LCDPWR signal See Host Bus Selection table below Active high LCDPWR signal se configuration for MPC821 host bus interface Table 4 3 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved 0 1 1 X MC68K 1 16 bit 1 0 0 X reserved 1 0 1 Xx MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 Generic 2 16 bit configuration for MPC821 host bus interface 1D13704 X26A G 010 03 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 Epson Research and Development Page 19 Vancouver Design Center 4 4 MPC821 Chip Select Configuration The DRAM on the MPC821 ADS board ex
105. 04PLAY 13704PLAY is a utility which allows the user to easily read write the S1D13704 registers Look up Table and display memory The user interface for 13704PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel and terminal for embedded platforms This utility requires the target platform to support standard I O 13704PLAY commands can be entered interactively using a keyboard monitor or they can be executed from a script file Scripting is a powerful feature which allows command sequences played back from a file thus avoiding having to retype lengthy sequences 13704PLAY must be configured to work with each different hardware platform Consult documentation for the program 13704CFG EXE which can be used to configure 13704PLAY This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations 1D13704 Supported Evaluation Platforms 13704PLAY Diagnostic Utility Issue Date 01 02 08 13704PLAY has b
106. 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X26A G 010 03 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction gt a 20 Gear ea ays AAA AA A e AA Aa 7 2 Interfacing to the MPC821 lt lt ee 8 2 1 The MPC8xx System BUS 8 2 2 MPC821 Bus Overview ao sia i as a sa AS 2 2 1 Normal Non Burst Bus Transactions e 9 222 Burst CV CleS io aa de tr CA AA eke A eg e ar E ieh 10 2 3 Memory Controller Module de
107. 2 12 4 MCF5307 To S1D13704 Interface 13 4 1 Hardware Description 2 e a a e e e 13 4 2 S1D13704 Hardware Configuration 2 a a a ee ee ee ee 14 4 3 MCF5307 Chip Select Configuration 2 2 0 ee ee 15 Software s lt a as Sh bee an A A Bee ak ee 16 Referentes aca woe eas ie aah O ar ee ae AO DI ae Ar aes e O 17 Oe DOCUMENIS La io ke oh te Sh di he ae a we ae be rin A ett AE 6 2 Document Sources 4 4 2 ea ee oe a a A aaa 17 7 Technical Support tud cis a e a ee As ee ee 18 7 1 EPSON LCD Controllers S1D13704 2 2 2 202 2 2 2 2 2 2 2 18 7 2 Motorola MCF5307 Processor 2 2 1 ee ee ee eee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13704 Issue Date 01 02 12 X26A G 01 1 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 03 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 0 00 00000000 11 Table 4 1 Summary of Power On Reset Options 0 000000 004 14 Table 4 2 Host Bus Interface Selection 0 000000 0000000045 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle aoaaa ee 9 Figure 2 2 MCF5307 Memory Write Cycle o 2000000022 eee eee 9 Figure
108. 23 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3 83min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 1 Ts 5 t7min REG O8h bits 4 0 x 8 10 Ts 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 47 Vancouver Design Center 7 3 8 Dual Monochrome 8 Bit Panel Timing VDP VNDP i t FPFRAME EPLINE l f l DRDY MOD X X FPDAT 7 0 LINE 1 241 X LINE 2 242 LINE 3 243 LINE 4 244 LINE 239 479XLINE 240 480 J LINE 1 241 LINE 2 242 Je FPLINE DRDY MOD X le HDP yi4 HNDP gt eer M M MU viia FPDAT7 11 X15 x Y X 1 637 X FPDAT6 Kk 12 YX ts X Y X 1 638 X FPDATS my X i O ae E 2 x FPDAT4 v4 ra X X X es KX FPDAT3 2411 Y 241 5 X x Y X 241 63 i Y FPDAT2 241 2 X 241 6 X x X X 241 638 X FPDAT1 241 3 X 241 7 x Y Y X 241 639 X FPDATO 241 4 241 8 X k Y X 241 640 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 20 Dual Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines H
109. 4 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 15 Vancouver Design Center 4 Functional Block Diagram 20k x 16 bit SRAM i Memory Power Save Register Controller Clocks LCD Generic MPU MC68K gt SH 3 SH 4 Look Up Table Sequence Controller Bus Clock Memory Clock Pixel Clock Figure 4 1 System Block Diagram Showing Data Paths 4 1 Functional Block Descriptions 4 1 1 Host Interface The Host Interface provides the means for the CPU MPU to communicate with the display memory and internal registers 4 1 2 Memory Controller The Memory Controller arbitrates between CPU accesses and display refresh accesses It also generates the necessary signals to control the SRAM frame buffer 4 1 3 Sequence Controller The Sequence Controller controls data flow from the Memory Controller through the Look Up Table and to the LCD Interface It also generates memory addresses for display refresh accesses Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 16 Epson Research and Development Vancouver Design Center 4 1 4 Look Up Table The Look Up Table contains three 16x4 Look Up Tables or palettes one for each primary color In monochrome mode only one of these Look Up Tables is used 4 1 5 LCD Interface The LCD Inte
110. 6 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgs connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to IO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO0 WE0 WE0 connect to IO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 5 5 LCD Interface Pin Mapping Table 5 3 LCD Interface Pin Mapping Page 23 Monochrome Passive Panel Color Passive Panel Color TFT D TFD S1 D13704 4 bit 8 bit 4 bit 8 bit 8 bit Pin Name Single Single 8 bit Dual Single Single Single 8 bit Dual 9 bit 12 bit Format 1 Format 2 FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD MOD MOD MOD FPSHIFT2 MOD MOD DRDY FPDATO driven 0 DO LDO driven 0 DO DO LDO R2 R3 FPDAT1 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2 FPDAT2 driven 0 D2 LD2 driven 0 D2 D2 LD2 RO R1 FPDAT3 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3 FPDAT4 DO D4 UDO DO D4 D4 UDO G1 G2 FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 GO G1 FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 B2 B3 FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 B1 B2 FPDAT8 GPIO1 GPIO1 GPIO1
111. 7 Vancouver Design Center 9 Hardware Abstraction Layer HAL 9 1 Introduction The HAL is a processor independent programming library provided by Epson with support for several different computing platforms The HAL was developed to aid implementation of internal test programs and provides an easy consistent method of programming S1D1350x S1D1370x and S1D1380x products on different processor platforms The HAL keeps sample code simpler although end programmers may find the HAL functions to be limited in their scope and may wish to ignore the HAL 9 2 API for 13704HAL The following is a description of the HAL library Updates and revisions to the HAL may include new functions not included in the following documentation The original design philosophy of the HAL was that function return values would be status of the call Most functions simple return ERR_OK If a value had to be returned then a pointer of the appropriate type was passed to the function 9 2 1 Initialization The following section describes the HAL functions dealing with S1D13704 initialization Typically a programmer has only to concern themselves with calls to seRegisterDevice and seSetInit int seRegisterDevice const LPHAL_STRUC IpHallnfo int pDevID Description Registers the S1D13704 device parameters with the HAL library The device param eters have been configured with address range register values desired frame rate etc and have been saved in t
112. 704 17 GND Ground 18 GND Ground 19 SD12 Connected to DB12 of the S1D13704 20 SD13 Connected to DB13 of the S1D13704 21 SD14 Connected to DB14 of the S1D13704 22 SD15 Connected to DB15 of the S1D13704 23 RESET Connected to the RESET signal of the S1D13704 24 GND Ground 25 GND Ground 26 GND Ground 27 12V 12 volt supply 28 12V 12 volt supply 29 WEO Connected to the WEO signal of the S1D13704 30 WAIT Connected to the WAIT signal of the S1D13704 31 CS Connected to the CS signal of the S1D13704 32 NC Not connected 33 WE1 Connected to the WE1 signal of the S1D13704 34 NC Not connected S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 12 1D13704 X26A G 005 03 Epson Research and Development Table 4 2 CPU BUS Connector H2 Pinout Vancouver Design Center Connector CPU BUS Comenta Pin No Pin Name 1 SAO Connected to ABO of the S1D13704 2 SA1 Connected to AB1 of the S1D13704 3 SA2 Connected to AB2 of the S1D13704 4 SA3 Connected to AB3 of the S1D13704 5 SA4 Connected to AB4 of the S1D13704 6 SA5 Connected to AB5 of the S1D13704 7 SA6 Connected to AB6 of the S1D13704 8 SA7 Connected to AB7 of the S1D13704 9 GND Ground 10 GND Ground 11 SA8 Connected to AB8 of the S1D13704 12 SA9 Connected to AB9 of the S1D13704 13 SA10 Connected to AB10 of the S1D13704
113. A B 001 02 Epson Research and Development Vancouver Design Center Durero E More Single f STW C abt a sl x Color Dus TFT C BBE F Mask FPSHIFT FPLive Stan FP Fomat 2 m I Fume Repeat FP Fearne Sbm Polity Hi Lo FAs C ares FO r Figure 2 Panel Information This section of the 13704CFG dialog describes the panel connected to the S1D13704 Each of the settings are described briefly below Mono Color select mono for monochrome panels or color for color panels This option is STN specific and is disabled if TFT is selected Single Dual select single when connected to a single panel or dual for connection to a dual panel This option is STN specific and is disabled if TFT is selected STN TFT select STN for passive panels or TFT for active panels Switching between these two panel types causes visible changes to take place to the configuration dialog box 4 Bit 8 Bit here the panel data width is selected When STN panel types are selected the options are 4 bit and 8 bit When TFT panels are selected the options will be 9 bit and 12 bit Dimensions in the left selection box horizontal pixels can be chosen from the list or typed in in the right selection box vertical lines in pixels can be selected from the list or typed in Mask FPSHIFT when selected the panel clocking signal FPSHIFT is masked off This option is required for most newer monochrome panels When color panel type is se
114. A14 A18 P6 D23 SA13 A19 P6 D22 SA12 A20 P6 D19 SA11 A21 P6 A19 SA10 A22 P6 D28 SA9 A23 P6 A28 SA8 A24 P6 C27 SA7 A25 P6 A26 SA6 A26 P6 C26 SA5 A27 P6 A25 SA4 A28 P6 D26 SA3 A29 P6 B25 SA2 A30 P6 B19 SA1 A31 P6 D17 SAO DO P12 A9 SD15 D1 P12 C9 SD14 D2 P12 D9 SD13 D3 P12 A8 SD12 D4 P12 B8 SD11 D5 P12 D8 SD10 D6 P12 B7 SD9 D7 P12 C7 SD8 D8 P12 A15 SD7 D9 P12 C15 SD6 D10 P12 D15 SD5 D11 P12 A14 SD4 D12 P12 B14 SD3 D13 P12 D14 SD2 D14 P12 B13 SD1 D15 P12 C13 SDO SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 17 Table 4 1 List of Connections from MPC821ADS to SID13704 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13704 Signal Name TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD WR RD P12 A1 P12 B1 P12 A2 P12 B2 GND P12 A3 P12 B3 P12 A4 P12 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note The bit numbering of the Power PC bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 1D13704 X26A G 010 03 Page 18 4 3 S1D13704 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D137
115. AGE LEFT BLANK 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 4 1 Figure 5 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 8 1 Figure 10 1 Figure 11 1 Figure 11 2 Hardware Functional Issue Date 01 02 08 Page 7 List of Figures Typical System Diagram SH 4 Bus o o 0000000000 12 Typical System Diagram SH 3 Bus o o e e 12 Typical System Diagram M68K 1 BUS oo o 13 Typical System Diagram M68K 2 BUS o o e e 13 Typical System Diagram Generic 1 Bus o o ooo o 14 Typical System Diagram Generic 2 Bus e g ISA Bus o 14 System Block Diagram Showing Data Paths o e 15 Pinout Diagram 2508 2 4 Be Gee ee a Bh es oe 17 SHF Timings se essa a ath eet oh Bree So ere a etal Lo eee pias 26 SH 3 Bus Timing inc 4 ah iid ed avo Ok A Cie I tas dB Bers 28 MO68K 1 Bus Timing MC68000 aaau aaa ee 30 M68K 2 Timing MC68030
116. Bit 2 Bit2 Bit 1 0 0 reserved 1 Color Dual 8 bit LCD REG 05h VERTICAL PANEL SIZE REGISTER LSB IO address FFESh RW REG 18h GPIO CONFIGURATION CONTROL REGISTER IO address FFF8h RW 1 0 esovad a sz GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIOO Pin 1 Vertical Panel Size REG O5h REG O6h 1 n a n a n a 10 Config 10 Config 10 Config 10 Config 10 Config 1 reserved Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 o DICTA Panel REG 19h GPIO Status CONTROL REGISTER IO address FFF9h RW 1 donit care 1 12 bit TFT Panel REG 06h VERTICAL PANEL SIZE REGISTER MSB IO address FFE6h RW GPiod Pin Gpiosen GPIO2 Pin GPIO Pin GPIOO Pia Vertical Panel Size IO Status IO Status IO Status IO Status lO Status z 7 n a n a n a n a n a n a 5 High Performance Selection Bit9 Bit 8 REG 1Ah SCRATCH PAD REGISTER IO address FFFAh RW E Bit Per Pixel Bit Per Pixel High Performance Bit 1 Bit 0 Display Modes REG 07h FPLINE START Position IO address FFE7h RW Scratch Pad Register REG 02 bit 7 REG 02 bit 6 FPLine Start Position 8 REG 07h 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 0 MCIk PCIW8 1 bit per pixel Bit 4 Bit3 Bit 2 0 F z REG 1Bh SwiveLView Mobe REGISTER IO address FFFBh RW 0 MGI PCWs 2 biiper pixel REG 08h HORIZONTAL NON DISPLAY PERIOD IO address FFESh RW eee ray SwivelView Mode PCLK i 9 MCKk PCIKk 2 4bit per pixel orizontal Non Swivel sa Mode Sel n a n a n a reserved i Select f 1 MCIk PCIk 8 bit per pixel Bit 3
117. Biti Bito 1 x x MC PCIk REG 09h FPFRAME START PosiTION 1O address FFE9h RW FEGI CNICNE Byte COUNT REGISTER O address HERO HW 6 Power Save Mode Selection FPFrame Start Position Eine Byte Count Power Save Bit 1 Power Save Bit 0 Mode n a n a Bis Bit 4 Bi Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 it it it 3 it 0 Software Power Save Mode Notes i i a 0 reserved REG 0Ah VERTICAL NON DISPLAY PERIOD REGISTER lO address FFEAh RW 1 These bits are used to identify the S1D13704 at power on reset Vert Non Vertical Non Display Period 2 10 addresses are relative to the beginning of display memory 1 reserved Disp Status n a Bit 5 Bit 4 Bit 3 Bit 2 3 Gray Shade Color Mode Selection 1 Normal Operation Color Mono Bit Per Pixel Bit 1 Bit Per Pixel Bit 0 Display Mode REG OBh MOD Rate REGISTER lO address FFEBh RW REG 01 bit 5 REG 02 bit 7 REG 02 bit 6 P 7 Look Up Table Access j MOD Rate 0 2 Colors 1 Bit Per Pixel Color Mono REG 15h n a n a l il Bit5 Bit 4 Bit 3 Bit 2 1 4 Colors 2 Bit Per Pixel REGION bit 5 pita ree oP Tabl Selacted Eolnter Sequence 1 0 16 Colors 4 Bit Per Pixel 5 REG OCh SCREEN 1 START WORD ADDRESS REGISTER LSB IO address FFECh RW 1 l BER Gia ane 2 X x Green Gray Look Up Table _ G n G n 1 Gin 2 Screen 1 Start Word Address REG OCh REG ODh 1 0 0 Auto Increment Rin Gln Bin Rin 1 G n 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0 0 p 2 Gray Shade RENCE Seno 1 0 1 Red Look Up
118. CF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions 1D13704 X26A G 011 03 A data transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size which indicate whether the bus cycle is 8 16 or 32 bits in width e R W which is high for read cycles and low for write cycles e A set of transfer type signals TT 1 0 which provide more detail o
119. D13704 HAL API JE x k SAMPLI El C Sample code demonstating a program using the S1D13704 HAL Created 1998 Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All Rights Reserved The HAL API code is configured for the following 320x240 Single Color 8 bit SIN format 2 4 bpp 70 Hz Frame Rate 25 MHz CLKi High Performance enabled xk ES inclu inclu inclu inclu inclu inclu de de de de de de lt conio h gt lt stdio h gt lt stdlib h gt lt string h gt hal ha Structures constants and prototypes appcfg h HAL configuration information void m ain void int Chipld int Device Initialize the HAL The call to seRegisterDevice actually prepares the HAL library for use The S1D13704 is not accessed z7 if ERR_OK seRegisterDevice amp HalInfo amp Device Programming Notes and Examples Issue Date 01 02 12 ay 1D13704 X26A G 002 03 Page 62 S1D13704 Epson Research and Development Vancouver Design Center printf AnERROR Could not register S1D13704 device exit 1 Get the product code to verify this is an S1D13704 NOTE If the s1D13704 design is modified then the ae product identification change Additional IDs ex will have to be checked for Bef seGetId Device
120. D13704 is a color monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer The high integration of the S1D13704 provides a low cost low power single chip solution to meet the require ments of embedded markets such as Office Automation equipment Mobile Communications devices and Palm size PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Hardware Portrait Mode feature of the S1D13704 Virtual and Split Screen are just some of the display modes supported The above features combined with the Operating System independence of the S1D13704 make it the ideal solution for a wide variety of applications E FEATURES Memory Interface e Embedded 40K byte SRAM display buffer CPU Interface e Direct support of the following interfaces Hitachi SH 3 Hitachi SH 4 Motorola M68K MPU bus interface with programmable READY e Direct memory mapping of internal registers e CPU write buffer Display Support e 4 8 bit monochrome LCD interface e 4 8 bit color LCD interface e Single panel single drive passive displays e Dual panel dual drive passive displays e Active Matrix TFT TFD interface e Register level suport for EL panels e Example resolutions 640x480 at acolor depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp Power Down Modes e Hardware and software
121. D13704B00C Schematic Diagram 2 of 4 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 12 Vancouver Design Center Epson Research and Development Page 22 g L 9 S y y A 1 TO E PASOS BO ASAOTDO REPSAMAL SITET o t a aay a quny queunseg ezts afoped Twa pue SNE YSI PARQRAMODIR SI Q00abOLETASS tour 43 yorvesey wsdal Has lt SZISTWDL ven rasau usauaae 9 TSOWGW AOT etu MOT 40 Tol s ztu Tta LUYT ant o ODA 919 ile a aqadr agar oda O NOD I G t 0 an TYT 61 T 0ZW1 1ZWI uot ZZWT o EZWT ATAOI 49 TSONAN SHES ors TT gt TaM SS Mo AA fst ols CT OTS a NOD I Y NOD atosan lt pusan 0 z v aa lt _ T tom MOT MOT a 7 eu Le sou Live aor She vto F aanor aanor MOT ou asa MOHOOI T TT aanor OTIS lt sT Olas ano 8 9 E y F T Figure 8 3 S1D13704B00C Schematic Diagram 3 of 4 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Epson Research and Development Vancouver Design Center Page 23
122. DP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 48 Epson Research and Development Vancouver Design Center Sync Timing t gt 2 a Frame Pulse t4 13 R Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 e gt Shift Pulse 2 x FPDAT 7 0 Figure 7 21 Dual Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pulse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 timm 18min 9Ts 3 Bmin REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 x 2 Ts 5 t6mi
123. Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The S1D13704 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping a SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgg connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RDA RDA RDA connect to lO Vpp SIZ1 RDO RD WEO WEO WEO connect to IO Vpp SIZO WEO WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 10 Epson Research and Developmen
124. Date 01 02 12 Page 3 1D13704 X26A G 005 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Configuration DIP Switch Settings o e 000 020 0020 00008 8 Table 2 2 Host Bus Selection ee 8 Table 2 3 Jumper Settings 2 4 a a A A A e a E 9 Table 3 1 LCD Signal Connector J5 Pinout 2 2 o e 10 Table 4 1 CPU BUS Connector H1 Pinout 2 e 11 Table 4 2 CPU BUS Connector H2 Pinout s ecr sania do ader e 12 Table 5 1 Host Bus Interface Pin Mapping 2 0 00 000000005 13 List of Figures Figure 8 1 S1D13704B00C Schematic Diagram 1 of 4 o o o ooo oo 20 Figure 8 2 S1D13704B00C Schematic Diagram 2 of 4 o o o o o ooo o 21 Figure 8 3 S1D13704B00C Schematic Diagram 3 of 4 o ooo oo 22 Figure 8 4 S1D13704B00C Schematic Diagram 4 of 4 o o o o ooo o 23 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13704 Issue Date 01 02 12 X26A G 005 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Pag
125. E1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13704 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13704 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13704 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the S1D13704 for Generic 1 mode and should be tied low connected to GND Interfacing to the PC Card Bus 1D13704 Issue Date 01 02 12 X26A G 009 03 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to S1D13704 Interface 4 1 Hardware Connections
126. EPSON 1D13704 Embedded Memory Color LCD Controller S1D13704 TECHNICAL MANUAL Issue Date 01 02 12 Document Number X26A Q 001 04 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 TECHNICAL MANUAL X26A Q 001 04 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and sche matics e To borrow an evaluation board please contact your local Seiko Epson Corp sales repre s
127. Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center xk S Page 71 et the memory pointer at the start of each line Pointer MEM_OFFS ET Y Line Width BPP 8 X BPP 8 NOTICE that in SwivelView mode we will use a value of 256 KK f af x pMem for or the line width value 110 7 LPBYTE MEM_OFFS x 110 x lt 210 pMem 0x11 pMem Programming Notes and Examples Issue Date 01 02 12 E x4 2 not 240 y 256 BitsPerPixel 8 x BitsPerPixel 8 Draws 2 pixels in LUT color 1 1D13704 X26A G 002 03 Page 72 10 1 3 Header Files Epson Research and Development Vancouver Design Center The header files included here are the required for the HAL sample to compile correctly HAL H Typical HAL header file for use with programs written to use the S1D13704 HAL Created 1998 Copyright c 1998 Epson Research and Development Vancouver Design Centre Inc All Rights Reserved kk lA ifndef _HAL H_ define _HAL H_ pragma warning disable 4001 Disable the single line comment warning include hal_regs h aes e typede
128. F define SET_REG idx val LPBYTE REG_OFFSET idx val 3 ES void main void LPBYTE pRegs LPBYTE REG_OFFSET LPBYTE pMem LPBYTE MEM_OFFSET LPBYTE pLUT int LUTcount RGBcount int X y tmp int BitsPerPixel 4 int Width 320 int Height 240 int OffsetBytes Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 66 Check the revision code if 0x18 pRegs return k k Initialize the chip Epson Research and Development Vancouver Design Center Exit if we don t find an S1D13704 Each register is individually programmed to make comments clearer isi Register 01h Mode Register 0 Color 8 bit format 2 af SET_REG 0x01 0x23 Register 02h Mode Register 1 4BPP High Performance CLKi 2 y SET_REG 0x02 0xB0 Register 03h Mode Register 2 Normal power mode a SET_REG 0x03 0x03 Register 04h Horizontal Panel Size 320 pixels 320 8 1 39 27h SET_REG 0x04 0x27 Register 05h Vertical Panel Size LSB 240 pixels Register 06h Vertical Panel Size MSB 240 1 239 EFh SET_REG 0x05 OXEF SET_REG 0x06 0x00 Register 07h FPLINE SET_REG 0x07 0x00 Start Position not used by STN Register 08h Horizontal Non Display P
129. FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME 2 26 GND Even GND GND GND GND GND GND GND GND GND Pins N C 28 VLCD 30 LCD panel negative bias voltage 18V to 23V LCDVCC 32 3 3V or 5V selectable with JP4 12V 34 12V 12V 12V 12V 12V 12V 12V 12V 12V VDDH 36 LCD panel positive bias voltage 24V to 38V BDRDY 38 MOD MOD MOD MOD MOD MOD DRDY DRDY BLCDPWR 40 LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design Center 4 CPU Bus Interface Connector Pinouts Table 4 1 CPU BUS Connector H1 Pinout Connector CPU BUS Comments Pin No Pin Name 1 SDO Connected to DBO of the S1D13704 2 SD1 Connected to DB1 of the S1D13704 3 SD2 Connected to DB2 of the S1D13704 4 SD3 Connected to DB3 of the S1D13704 5 GND Ground 6 GND Ground 7 SD4 Connected to DB4 of the S1D13704 8 SD5 Connected to DB5 of the S1D13704 9 SD6 Connected to DB6 of the S1D13704 10 SD7 Connected to DB7 of the S1D13704 11 GND Ground 12 GND Ground 13 SD8 Connected to DB8 of the S1D13704 14 SD9 Connected to DB9 of the S1D13704 15 SD10 Connected to DB10 of the S1D13704 16 SD11 Connected to DB11 of the S1D13
130. For MC68K 2 these pins are connected to D 31 16 for DB 15 0 UO 13 14 15 C TS2 itpedance a 32 bit device e g MC68030 or D 15 0 for a 16 bit 16 H 18 device e g MC68340 For Generic 1 these pins are connected to D 15 0 For Generic 2 these pins are connected to D 15 0 See Host Bus Interface Pin Mapping for summary 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 19 Pin Names Type Pin Cell RESET State Description WE0 l 77 CS Input This e See pin has multiple functions For SH 3 SH 4 mode this pin inputs the write enable signal for the lower data byte WEO For MC68K 1 this pin must be tied to IO Vpp For MC68K 2 this pin inputs the bus size bit O SIZO For Generic 1 this pin inputs the write enable signal for the lower data byte WEO For Generic 2 this pin inputs the write enable signal WE Host Bus Interface Pin Mapping for summary WE1 l 78 CS Input This See pin has multiple functions For SH 3 SH 4 mode this pin inputs the write enable signal for the upper data byte WE1 For MC68K 1 this pin inputs the upper data strobe UDS For MC68K 2 this pin inputs the data strobe DS For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 For Generic 2 this pin i
131. GPIO1 GPIO1 GPIO1 GPIO1 BO B1 FPDAT9 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 RO FPDAT10 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GO GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 FPDAT11 HW Video HW Video HW Video HW Video HW Video HW Video HW Video GPIO4 BO Invert Invert Invert Invert Invert Invert Invert Note 1 Unused GPIO pins must be connected to IO Vpp 2 Hardware Video Invert is enabled on FPDAT11 by REG 02h bit 1 Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 24 6 D C Characteristics Epson Research and Development Vancouver Design Center Table 6 1 Absolute Maximum Ratings Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 4 6 V IO Vop Supply Voltage Vss 0 3 to 6 0 V VIN Input Voltage Vss 0 3 to IO Vpp 0 5 V Vout Output Voltage Vss 0 3 to lO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C Tso Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core Vpp Supply Voltage Vss OV 3 0 3 3 3 6 V IO Vpp Supply Voltage Vss 0V 3 0 3 3 5 0 5 5 V Vin Input Voltage Vss IO Vop V Topr Operating Temperature 40 25 85 2G Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units Vic Low Level Input Volt
132. GPIOn pin is configured as an input The input can be read at the GPIOn Status Control Register bit See REG 19h below When GPIOn Pin IO Configuration bit 1 the corresponding GPIOn pin is configured as an output The output can be controlled by writing the GPIOn Status Control Register bit Note These bits have no effect when the GPIOn pin is configured for a specific function i e as FPDAT 11 8 for TFT D TFD operation All unused GPIO pins must be tied to IO Vpp REG 19h GPIO Status Control Register Address FFF9h Read Write wa TA nla GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Status Status Status Status Status bits 4 0 GPIO 4 0 Status When the GPIOn pin is configured as an input the corresponding GPIO Status bit is used to read the pin input See REG 18h above When the GPIOn pin is configured as an output the corresponding GPIO Status bit is used to control the pin output Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 68 Epson Research and Development Vancouver Design Center REG 1Ah Scratch Pad Register Address FFFAh Read Write Scratch bit 7 Scratch bit 6 Scratch bit 5 Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bit 1 Scratch bit 0 bits 7 0 Scratch Pad Register This register contains general use read write bits These bits have no effect on
133. IO 3 1 These pins should be connected to IO Vpp when unused See LCD Interface Pin Mapping for summary FPDAT11 1 0 23 CN3 Input This pin has multiple functions Panel Data bit 11 for TFT D TFD panels General Purpose Input Output pin GPIO4 e Inverse Video select pin This pin should be connected to IO Vpp when unused See LCD Interface Pin Mapping for summary FPFRAME 39 CN3 Frame Pulse 1D13704 X26A A 001 04 Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 21 RESET so Pin Name Type Pin Cell State Description FPLINE O 38 CN3 0 Line Pulse FPSHIFT O 28 CN3 0 Shift Clock 0 if CNF4 1 LCDPWR O 43 CO1 1 if CNF4 0 LCD Power Control This pin has multiple functions e TFT D TFD Display Enable DRDY DRDY O 42 CN3 0 LCD Backplane Bias MOD Second Shift Clock FPSHIFT2 See LCD Interface Pin Mapping for summary 5 2 3 Clock Input Pin Name Type Pin Driver Description CLKI l 51 C Input Clock 5 2 4 Miscellaneous RESET ii Pin Name Type Pin Cell State Description AENA Sol These inputs are used to configure the S1D13704 see f AO Fh s set by Summary of Configuration Options CNF 4 0 l 48 49 C hardware X 3 ig Must be connected directly to IO Vpp or
134. LINE Start FPLINE Start FPLINE Start Position Bit 4 Position Bit3 Position Bit 2 Position Bit 1 Position Bit O bits 4 0 FPLINE Start Position These bits are used in TFT D TFD mode to specify the position of the FPLINE pulse These bits specify the delay in 8 pixel resolution from the end of a line of display data FPDAT to the leading edge of FPLINE This register is effective in TFT D TFD mode only REG 01h bit 7 1 This register is programmed as follows FPLINEposition pixels REG 07h 2 x 8 The following constraint must be satisfied REG 07h lt REG 08h REG 08h Horizontal Non Display Period Address FFE8h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal n a n a n a Non Display Non Display Non Display Non Display Non Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 4 0 Horizontal Non Display Period These bits specify the horizontal non display period in 8 pixel resolution HorizontalNonDisplayPeriod pixels REG 08h 4 x 8 REG 09h FPFRAME Start Position Address FFE9h Read Write FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME n a n a Start Position Start Position Start Position Start Position Start Position Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 FPFRAME Start Position These bits are used in TFT D TFD mode to specify the position of the FPFRAME pulse
135. M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx PC platform copy the file 13704SHOW EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13704SHOW to the system 13704SHOW Demonstration Program S1D13704 Issue Date 01 02 08 X26A B 002 02 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at the prompt type 13704show a b n 1 p vertical noinit Embedded platform execute 13704show and at the prompt type the command line argument s Where a automatically cycle through all video modes b starts 13704SHOW at a user specified bit per pixel bpp level where can be 1 2 4 8 1 set landscape mode p set portrait mode vertical displays vertical line pattern noinit bypass register initialization and use values which are currently in the registers es displays the help screen Program Messages S1D13704 X26A B 002 02 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was
136. M68K MPU bus interface using WAIT signal e Direct memory mapping of internal registers e Single level CPU write buffer e Registers are mapped into upper 32 bytes of 64K byte address space e The complete 40K byte frame buffer is directly and contiguously available through the 16 bit address bus 2 3 Display Support e 4 8 bit monochrome LCD interface e 4 8 bit color LCD interface e Single panel single drive passive displays e Dual panel dual drive passive displays e Active Matrix TFT D TFD interface Register level support for EL panels e Example resolutions 640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 11 Vancouver Design Center 2 4 Display Modes 2 5 Clock Source SwivelView direct 90 hardware rotation of display image for portrait mode display 1 2 4 bit per pixel bpp 2 4 16 level grayshade display 1 2 4 8 bit per pixel 2 4 16 256 level color display Up to 16 shades of gray by FRM on monochrome passive LCD panels a 16x4 Look Up Table is used to map 1 2 4 bpp modes into these shades 256 simultaneous of 4096 colors on color passive and active matrix LCD panels three 16x4 Look Up Tables are used to map 1 2 4 8 bpp modes into these colors Split screen display for all landscape panel modes
137. MPR3912 22U s PC Card slot 1 Therefore this slot cannot be used for other devices on the main board The Generic 2 bus mode of the S1D13704 5 is used to interface to this PC Card slot 1 The S1D13704 5 is interfaced to the TMPR3912 22U with minimal glue logic Since the address bus of the TMPR3912 22U is multiplexed it is demultiplexed using an advanced CMOS latch 74ACT373 to obtain the higher address bits needed for the 1D13704 5 The following diagram demonstrates the implementation of the interface 1D13704 3 3V TMPR3912 22U T RD gt WE gt CARD1CSL CARD1CSH gt 3 3V 3 3V ENDIAN System RESET Latch AN ALE gt BY A 12 0 am gt D 31 24 lt D 23 16 gt 3 3V 40K pull up CARD1WAIT DCLKOUT Clock divider l gt or Oscillator Lp Clock divider gt IO Vpp CORE Vpp RD WE10 WE1 BS RD WR RESET CS AB 15 13 AB 12 0 DBI7 0 DB 15 8 WAIT CLKI BUSCLK X00A G 004 02 Figure 3 1 SID13704 to TMPR3912 22U Interface 5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 EPSON Research and Development Page 11 Vancouver Design Center 3 2 Memory Mapping and Aliasing The S1D13704 requires an addressing space of 64K bytes while the S1D13705 requires 128K The on chip display memory occupies the rang
138. Memory read write accessible LCD outputs are forced low 13 2 Hardware Power Save Mode Hardware Power Save Mode saves power by powering down the panel stopping accesses to the display buffer and registers and disabling the Host Bus Interface Table 13 3 Hardware Power Save Mode Summary Host Interface not accessible e Memory read write not accessible LCD outputs are forced low 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 85 Vancouver Design Center 13 3 Power Save Mode Function Summary Table 13 4 Power Save Mode Function Summary Hardware Software Normal Power Save Power Save IO Access Possible No Yes Yes Memory Access Possible No Yes Yes Sequence Controller Running No No Yes Display Active No No Yes LCDPWR Inactive Inactive Active FPDAT 11 0 FPSHIFT see note Forced Low Forced Low Active FPLINE FPFRAME DRDY Forced Low Forced Low Active Note When FPDAT 11 8 are designated as GPIO outputs the output state prior to enabling the Power Save Mode is maintained When FPDAT 11 8 are designated as GPIO in puts unused inputs must be tied to either IO Vpp or GND see Table 5 3 LCD Inter face Pin Mapping on page 23 13 4 Panel Power Up Down Sequence After chip reset or when entering exiting a power save mode the Panel Interface signals follow
139. O RD1 high read cycle to A 15 0 t2 i a 0 ns CS invalid t3 WEO WE1 low to D 15 0 valid write cycle TBcLK t4 RDO RD1 low to D 15 0 driven read cycle 17 ns t5 WEO WE1 high to D 15 0 invalid write cycle 0 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RDO RD1 high to D 15 0 high impedance read cycle 10 ns 8 WEO WE1 low write cycle or RDO RD1 low read cycle to WAIT 16 fie driven low t9 BCLK to WAIT high 16 ns WEO WE1 high write cycle or RDO RD1 high read cycle to WAIT t10 se Al ns high impedance Note BCLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 33 Vancouver Design Center 7 1 6 Generic 2 Interface Timing TBcLk A 15 0 BHE VALID CS tl t2 gt o WE RD B y t4 Hi Z D 15 0 bic write t5 t6 t7 1 gt Hi Z VALID Hi Z D 15 0 read 18 t9 t10 WAIT Hi Z Hi Z Figure 7 6 Generic 2 Timing Table 7 6 Generic 2 Timing Symbol Parameter Min Max Units fecLk Bus Clock frequency 0 50 MHz Tecik Bus Clock period 1 fBcLK t1 A 15 0 BHE CS valid to WE RD low 0 ns t2 WE RD high to A 15 0 BHE CS invalid 0 ns 13 WE low to D 15 0 valid w
140. OTO TYPES ie x Initialization int seRegisterDevice const LPHAL _STRUCT lpHalInfo int Device int seSetInit int device int seInitHal void Miscellaneous 7 int seGetId int nDevID int pld void seGetHalVersion const char pVersion const char pStatus const char pSta tusRevision int seSetBitsPerPixel int nDevID int nBitsPerPixel int seGetBitsPerPixel int nDevID int pBitsPerPixel int seGetBytesPerScanline int nDevID int pBytes int seGetScreenSize int nDevID int width int height void seDelay int nMilliSeconds int seGetLastUsableByte int nDevID long LastByte int seSetHighPerformance int nDevID BOOL OnOff Advanced int seSetHWRotate int nDevID int nMode Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 76 int seSplitInit int nDevID WORD ScrnlAddr WORD Scrn2Addr Epson Research and Development Vancouver Design Center i int seSplitScreen int nDevID int WhichScreen int VisibleScanlines int seVirtInit int nDevID int xVirt long yVirt int seVirtMove int nDevID int nWhichScreen int x int y T hee Register Memory Access int seGetReg int nDevID int index BYTE pValue int seSetReg int nDevID int index BYTE value int seReadDisplayByte int nDevID DWORD offset BYTE pByte int seReadDisplayWord int nDevID DWORD offset
141. P Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 44 Epson Research and Development Vancouver Design Center Sync Timing u 2 Frame Pulse t4 5 t3 Line Pulse Data Timin g Line Pulse t6a ten gt t8 t9 ta t14 t11 lt gt t _ Shift Pulse 2 t7b Shift Pulse A J a ees SS ea t12 t13 t12 t13 aa FPDAT 7 0 f f f X X Figure 7 17 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t6a Shift Pulse falling edge to Line Pulse rising edge note 4 t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5 t a Shift Pulse 2 falling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7 t8 Line Pulse falling edge to Shift Pulse rising Shift Pulse 2 falling edge t14 2 Ts t9 Shift Pulse 2 Shift Pulse period 4 Ts t10 Shift Pulse 2 Shift Pulse pulse width low 2 Ts t11 Shift Pulse 2 Shift Pulse pulse width high 2 Ts t12 FPDAT 7 0 setup to Shift Pulse 2 Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse 2 Shift Puls
142. P13704 subdirectory Add an entry for the 4BPP13704 in the file wince platform cepc drivers display dirs Modify the file CONFIG BIB using any text editor such as NOTEPAD to set the system RAM size the S1D13704 IO port and display buffer address mapping Note that CONFIG BIB is located in X wince platform cepc files where X is the drive letter Since the S5U13704BO00C maps the 64K byte region from DO000h to DFFFFh make sure no other devices occupy this area The following lines should be in CON FIG BIB NK 80200000 00500000 RAMIMGE RAM 80700000 00500000 RAM Note DISPDRVR C should include the following define PhysicalPortAddr OxOOODFOOOL define PhysicalVmemAddr Ox000DO000L Edit the file PLATFORM BIB located in X wince platform cepc files to set the de fault display driver to the file 4BPP13704 DLL 4BPP13704 DLL will be created dur ing the build in step 13 You may replace the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dl1 _FLATRELEASEDIR ddi_vga2 dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi dl1 _FLATRELEASEDIR ddi_vga8 d1ll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF with this line ddi dll _FLATRELEASEDIR 4BPP13704 d1l NK SH Windows CE Display Drivers Issue Date 01 02 08 Epson Research and Developme
143. R31500 PR31700 Processor S1D13704 Issue Date 01 02 12 X26A G 012 02 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 02 Issue Date 01 02 12 EPSON Research and Development Table 2 1 Table 2 2 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Figure 2 1 Figure 3 1 Interfacing to the Phi Issue Date 01 02 12 Page 5 Vancouver Design Center List of Tables S1D13704 Configuration for Direct Connection 2 o e 9 S1D13704 Generic 2 Interface Pin Mapping e 9 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping 12 PR31500 PR31700 to PC Card Slots Address Remapping Using the IT8368E 12 S1D13704 Configuration Using the IT8368 o o 13 S1D13704 Generic 1 Interface Pin Mapping e 13 List of Figures S1D13704 to PR31500 PR31700 Direct Comnecti0od 8 S1D13704 to PR31500 PR31700 Connection Using an IT8368 10 lips MIPS PR31500 PR31700 Processor S1D13704 X26A G 012 02 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 02 Issue Date 01 02 12 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the h
144. RD2IOEN are ignored and the attribute IO space of the TX3912 is divided into Attribute T O and S1D13704 access Table 3 2 TX3912 to PC Card Slots Address Remapping Using the IT8368E provides all details of the Attribute IO address reallocation by the IT8368E Table 3 2 TX3912 to PC Card Slots Address Remapping Using the IT8368E IT8368E Uses PC Card Slot TX3912 Address Size Function 0800 0000h 16M byte Card 1 IO 4 0900 0000h 16M byte S1D13704 aliased 256 times at 64K byte intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO 2 0D00 0000h 16M byte S1D13704 aliased 256 times at 64K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON Research and Development Page 13 Vancouver Design Center 3 4 S1D13704 Configuration The S1D13704 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 3 3 S1ID13704 Configuration Using the IT8368E CNF 2 0 S1D13704 Value hard wired on this
145. RGB Index setting one to three accesses of the Look Up Table Data register cause the LUT Address to automatically increment to the next index REG 16h Look Up Table Bank Select Register Read Write n m Red Bank Red Bank Green Bank Green Bank Blue Bank Blue Bank Select bit 1 Select bit 0 Select bit 1 Select bit 0 Select bit 1 Select bitO Look Up Table Bank Select The Look Up Table Bank Select register affects displayed colors Depending on the color mode not all of the sixteen Look Up Table LUT entries are required This register determines which entries will be displayed At 1 bpp only the lower eight Look Up Table addresses are used These are further divided into four banks of two colors The bank selects determine which of the four red green and blue banks the displayed colors will come from For instance Assume the Look Up Table Bank Select register was set to 18h 0001 1000 b Red pixels would come from the 2nd red lookup bank red LUT Addresses 2 and 3 Green would be taken from the 3rd green lookup bank green LUT addresses 4 and 5 Blue pixels would be taken from the Ist blue lookup bank blue LUT addresses 0 and 1 Programming Notes and Examples Issue Date 01 02 12 1D13704 X26A G 002 03 Page 16 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center At 2 bpp sixteen Look Up Table addresses are used The Look Up Table is a now arranged into four
146. Sack aca Display WEO P WEO RDY WAIT il LCDPWR CKIO P BCLK RESET P RESET Figure 3 1 Typical System Diagram SH 4 Bus Oscillator x SH 3 9 BUS CSnit gt CS A 15 0 gt AB 15 0 D 15 0 gt DB 15 0 FPDAT 3 0 gt 3 0 LD FPSHIFT ess bla S1D13704 D BS gt BS 4 bit eee paa FPFRAME FPFRAME LCD FPLINE gt FPLINE RD gt RDA Did buon Display WEO gt WEO WAIT WAIT i LCDPWR CKIO gt BCLK RESET Pi RESET 1D13704 X26A A 001 04 Figure 3 2 Typical System Diagram SH 3 Bus Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Page 13 Vancouver Design Center Oscillator MC68000 BUS 23 16 a FCO aah a D Decoder C _ gt CS A 15 1 AB 15 1 D 15 0 ke DB 15 0 OOO ses FPSHIFT FPSHIFT Lose gt aos S1D13704 4 bit UDS p weis FPFRAME FPFRAME LCD ASH gt Est FPLINE gt FPLINE Display RW gt RD WR PAD pes e MOD DTACK iq WAITH LCDPWR CLK gt BCLK RESET P RESET Figure 3 3 Typical System Diagram M68K 1 Bus Oscillator MC68030 BUS FCO tre gt Decoder CS a A 15 0 AB 15 0 PREISI e DB 15 0 FPDAT 7 0 _ _ D 7 0 bee pl Wee FPSHIFT gt FPSHIFT a ASH gt BS S1D13704 olt
147. Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Motorola Inc MC68328 DragonBall Integrated Microprocessor User s Manual Motorola Publication no MC68328UM AD available on the Internet at http www mot com SPS WIRELESS products MC68328 html Epson Research and Development Inc 1D13704 Hardware Functional Specification Document Number X26A A 001 xx e Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc S1D13704 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center
148. Suspend modes e LCD power down sequencing Display Modes e Hardware Portrait Mode direct hardware rotation of display image for portrait mode display e 1 2 4 bit per pixel bpp 2 4 16 level grayscale display e 1 2 4 8 bit per pixel 2 4 16 256 level color display e Up to 16 shades of gray by FRM on monochrome passive LCD panels e 256 simultaneous of 4096 colors on color passive and active matrix LCD panels e Split screen display for all panel modes allows two different images to be simultaneously displayed e Virtual display support displays images larger than the panel size through the use of panning Clock Source e Single clock input for both pixel and memory clocks e The S1D13704 clock source can be internally divided down for a higher frequency clock input e Dynamic switching of memory clocks in portrait mode General Purpose IO Pins e Five General Purpose Input Output pins available Operating Voltage e 2 7 volts to 5 5 volts Package 80 pin QFP14 surface mount package X26A C 001 07 07 a 1D13704 E SYSTEM BLOCK DIAGRAM EPSON Data and Digital Out CPU lt 4 Control Signals S1D13704 Flat Panel Actual Size CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e S1D13704 Technical Manual e S5U13704 Evaluation Boards e Windows CE Display Driver e CPU Independent Software Utilities Japan Seiko Epson Corporation E
149. Swivel View Mode also requires memory clock MCLK gt pixel clock PCLK The following figure shows how the programmer sees a 240x320 image and how the image is displayed The application image is written to the S1D13704 in the following sense A B C D The display is refreshed by the S1D13704 in the following sense B D A C physical 320 memory start ey lt address A 256 SwivelView we a a l z O window display gt 3 3 start o g A address 5 lt n O C D il 320 240 i image seen by programmer image refreshed by S1D13704 image in display buffer Figure 12 1 Relationship Between The Screen Image and the Image Refreshed by SID13704 Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 80 Epson Research and Development Vancouver Design Center 12 1 1 How to Set Up Default SwivelView Mode The following describes the register settings needed to set up Default Swivel View Mode for a 240x320x4 bpp image e Select Default Swivel View Mode REG 1Bh bit 7 1 and bit 6 0 e The display refresh circuitry starts at pixel B therefore the Screen 1 Start Address register must be programmed with the address of pixel B i e REG 0Dh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset AddressOfPixelA Pueiielossbeo 1 8bpb AddressOfPixelA 77h Where bpp is bits per pixel and bpb is bits per by
150. Table Rin R n 1 R n 2 o 1 4 Gray Shade 2 Bit Per Pixel 1 1 0 Green Gray Look Up Table G n G n 1 G n 2 REG 0Dh SCREEN 1 START WORD ADDRESS REGISTER MSB IO address FFEDh RW i 0 16 Gray Shade 4 Bit Per Pixel 1 1 1 Blue Look Up Table Bin B n 1 B n 2 Screen 1 Start Word Address 1 reserved reserved j p d si A P Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit9 Bit 8 REG OFh SCREEN 2 START WORD ADDRESS REGISTER LSB IO address FFEFh RW REG 10h SCREEN 2 START WORD ADDI Bit5 Bit 4 RESS REGISTE Bit3 Screen 2 Start Word Address REG OF REG 10h Bit 2 R MSB 1O address FFF Bit 15 Bit 14 REG 12h Memory ADDR Bit 13 Bit 12 ESS OFFSET REGISTER Screen 2 Start Bit 11 Word Address Bit 10 1O address FFF2h RW Bit7 Bit 6 Page 1 Bit5 Bit 4 Memory Address Offset Bit 3 Bit 2 4 Panel Data Format X26A R 001 03 01 02 12 S1D13704 Register Summary X26A R 001 03 Page 2 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller 13704CFG EXE Configuration Program Document No X26A B 001 02 Copyright 2001 Epson Research and Dev
151. Tel 337 7911 Fax 334 2716 1D13704 X26A G 007 03 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 EPSON S1D13704 Embedded Memory Color LCD Controller Interfacing to the NEC VR4102 Microprocessor Document Number X26A G 008 05 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the NEC VR4102 Microprocessor X26A G 008 05 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T INOGUCHOU s a a a aa DARA AAA By we ae 7 2 Interfacing to the NEC VR4102 o 8 2 1 The NEC VR41
152. UTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 loadcepc B 9600 C 1 c wince release nk bin 4 Confirm that NK BIN is located in c wince release 5 Reboot the system from the hard drive Windows CE Display Drivers 1D13704 Issue Date 01 02 08 X26A E 001 02 Page 6 Epson Research and Development Vancouver Design Center 1 4 Comments e At the time of this printing the drivers have been tested on the x86 CPUs and have only been run with version 2 0 of the ETK We are constantly updating the drivers so please check our website at www erd epson com or contact your Seiko Epson or Epson Electronics America sales representative S1D13704 Windows CE Display Drivers X26A E 001 02 Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 03 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a re
153. Vss V0 es This pin has multiple functions see REG O3h bit 2 GPIOO i 22 181 Input General Purpose Input Output pin Hardware Power Save TESTEN l 44 CD High Test Enable input This input must be connected to Vss Impedance 5 2 5 Power Supply Pin Name Type Pin Driver Description COREVDD P 1 a H P Core Vpp IOVDD P 10 29 52 P IO Vpp 20 27 40 VSS P 50 60 72 P Common Vss 80 Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 22 5 3 Summary of Configuration Options Epson Research and Development Vancouver Design Center Table 5 1 Summary of Power On Reset Options Configuration Power On Reset State Pin 1 0 CNF4 Active high On LCDPWR polarity Active low On LCDPWR polarity CNF3 Big Endian Little Endian Select host bus interface as follows CNF2 CNF1 CNFO BS Host Bus 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 x reserved CNF 2 0 0 1 1 x MC68K 1 16 bit 1 0 0 x reserved 1 0 1 Xx MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 Generic 1 16 bit 1 1 1 1 Generic 2 16 bit 5 4 Host Bus Interface Pin Mapping Table 5 2 Host Bus Interface Pin Mapping See SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 1
154. Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13704 X26A G 011 03 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the Philips MIPS PR31500 PR31700 Processor Document Number X26A G 012 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents
155. Width Data Width TPT STN Bielsa SGolor Mono Polarity Polarity FPSHIFT Bit 1 Bit 0 bit 7 TFT STN When this bit 0 STN passive panel mode is selected When this bit 1 TFT D TFD panel mode is selected If TFT D TFD panel mode is selected Dual Single REG 01h bit 6 and Color Mono REG 01h bit5 are ignored See Table 8 1 Panel Data Format below bit 6 Dual Single When this bit 0 Single LCD panel drive is selected When this bit 1 Dual LCD panel drive is selected See Table 8 1 Panel Data Format below bit 5 Color Mono When this bit 0 Monochrome LCD panel drive is selected When this bit 1 Color LCD panel drive is selected See Table 8 1 Panel Data Format below 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 55 bit 4 FPLINE Polarity This bit controls the polarity of FPLINE in TFT D TFD mode no effect in passive panel mode When this bit 0 FPLINE is active low When this bit 1 FPLINE is active high bit 3 FPFRAME Polarity This bit controls the polarity of FPFRAME in TFT D TFD mode no effect in passive panel mode When this bit 0 FPFRAME is active low When this bit 1 FPFRAME is active high bit 2 Mask FPSHIFT FPSHIFT is masked during non display periods if either of the following two criteria is met 1 Color passive panel
156. _per_line if StartWord lt 0 StartWord 0 SetStartAddress StartWord To scroll down StartWord GetStartAddress StartWord words_per_line SetStartAddress StartWord long GetStartAddress void return REG OD 256 REG OC void SetStartAddress long StartWord REG OC StartWord OxXFF REG OD StartWord 256 Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 30 5 3 Split Screen 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center Occasionally the need arises to display two different but related images For example a game where the main play area requires rapid updates and game status displayed at the bottom of the screen The status area updates far less often than the main play area The Split Screen feature of the S1D13704 allows a programmer to setup a display for such an application The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to scan line 239 Although this example picks specific values the split between image 1 and image 2 can occur anywhere on the display Scan Line 0 Image 1 Scan Line 199 Scan Line 200 Image 2 Scan Line 239 Figure 5 4 320x240 Single Panel For Split Screen In split screen operation Image 1 is taken from the display memory location pointed to by the Scr
157. a power on off sequence shown below This sequence is essential to prevent damage to the LCD panel Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 86 Epson Research and Development Vancouver Design Center RESET Software Power Save REG 03h bits 1 0 or Hardware Power Save LCDPWR CNF4 Low LCDPWR CNF4 Hi Panel Interface Output Signals except LCDPWR x 00 Power Save Mode gt tk 0 frame power up A 127 frames power down gt d 0 frame power up 13 5 Turning Off BCLK Between Accesses S1D13704 X26A A 001 04 Figure 13 1 Panel On Off Sequence After chip reset LCDPWR is inactive and the rest of the panel interface output signals are held low Software initializes the chip i e programs the registers and then as a last step set programs REG 03h bits 1 0 to 11 This starts the power up sequence as shown The power up power down sequence delay is 127 frames The power up power down sequence also occurs when exiting entering Software Power Save Mode BCLK may be turned off held low between accesses if the following rules are observed 1 BCLK must be turned off on in a glitch free manner 2 BCLK must continue for a period equal to 8Tgc xk 12Tuyc1 k after the end of the access RDY asserted or WAIT deasserted 3 BCLK
158. able O value being displayed A bit set to 1 results in the Look Up Table index 1 value displayed The following table shows the recommended values for 1 bpp on a color panel Table 4 5 Recommended LUT Values for 1 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 OF OF OF 02 OF Normally unused entries 2 Bpp Color When the S1D13704 is configured for 2 bit per pixel color mode only the first four colors from the active bank are displayed The four entries can be set to any color Each byte in the display buffer contains 4 adjacent pixels Each pair of bits in the byte are used as an index into the LUT The following table shows example values for 2 bpp color mode Table 4 6 LUT Values for 2 Bpp Color Mode Index Red Green Blue 00 00 00 OF 01 OF 00 00 02 00 OF 00 03 OF OF OF 04 OF Normally unused entries Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 4 Bpp Color Page 21 When the 1D13704 is configured for 4 bit per pixel operation all sixteen Look Up Table entries are used Each byte in the display buffer contains two adjacent pixels The upper and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 4 7 Suggested LUT Values t
159. age 69 SwivelView SwivelView _ Pixel Clock PCLK Select Mode Enable Mode Select REG 1Bh bits 1 0 PCLK MCLK REG 1Bh bit 7 REG 1Bh bit 6 Bit 1 Bit 0 0 X X Xx CLK See Reg 02h bit 5 1 0 0 0 CLK CLK 1 0 0 1 CLK 2 CLK 2 1 0 1 0 CLK 4 CLK 4 1 0 1 1 CLK 8 CLK 8 1 1 0 0 CLK 2 CLK 1 1 0 1 CLK 2 CLK 1 1 1 0 CLK 4 CLK 2 1 1 1 CLK 8 CLK 4 Where CLK is CLKI a REG 02h bit 4 0 or CLKI 2 REG 02h bit 4 1 REG 1Ch Line Byte Count Register for SwivelView Mode Address FFFCh Read Write Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Count bit 7 Count bit 6 Count bit 5 Count bit 4 Count bit 3 Count bit 2 Count bit 1 Count bit 0 bits 7 0 Line Byte Count Bits 7 0 This register is the byte count from the beginning of one line to the beginning of the next consecutive line commonly called stride by programmers This register may be used to create a virtual image in Swivel View mode REG 1Eh and REG 1Fh REG 1Eh and REG 1Fh are reserved for factory S1D13704 testing and should not be written Any value written to these registers may result in damage to the S1D13704 and or any panel connected to the S1D13704 Hardware Functional Specification Issue Date 01 02 08 S1D13704 X26A A 001 04 Page 70 Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation
160. age lOVpp 3 3 0 8 V CMOS inputs 5 0 1 0 V Vin High de ed lIOVpp 3 3 2 0 V inputs 5 0 3 5 V Vr Positive going Threshold IOVop 3 3 1 1 2 4 V CMOS Schmitt inputs 5 0 2 0 4 0 V Vr Negative going Threshold lOVpp 3 3 0 6 1 8 V CMOS Schmitt inputs 5 0 0 8 3 1 V Vpp Max liz Input Leakage Current Vin Vpp 1 1 uA Vi Vss Cin Input Pin Capacitance 10 pF HRpp Pull Down Resistance Vi Vpp 50 100 300 kQ S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table 6 4 Output Specifications Page 25 Symbol Parameter Condition Min Typ Max Units Low Level Output Voltage Type 1 TS1 CO1 lo 3mA VoL Type 2 TS2 CO2 lo 6mA Es y Type 3 TS3 CO3 lo 12mA High Level Output Voltage Type 1 TS1 CO1 lo 1 5 mA i VoH Type 2 TS2 CO2 lo 3 mA lO Vpop 0 4 y Type 3 TS3 CO3 loL 6 mA Vop MAX loz Output Leakage Current Vou Vpp 1 1 uA VoL Vss Court Output Pin Capacitance 10 pF Cpip Bidirectional Pin Capacitance 10 pF Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 26 Epson Research and Development Vancouver Design Center 7 A C Characteristics Conditions IO Vpp 3 3V 10 or IO Vpp 5V 10 Ta 40 C to 85 C Tise and Tfa1 for all inputs must be lt 5 nsec 10 90 C 60pF Bus MPU Interface C 60pF LCD Panel Interface
161. alk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for connection infor mation S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Page 17 Vancouver Design Center 6 10 Power Save Modes The S1D13704 supports one hardware and one software power save mode These modes are controlled by the utility 13704PWR The hardware power save mode needs to be enabled by 13704PWR and then activated by DIP switch SW1 6 See Table 2 1 Config uration DIP Switch Settings on page 8 for details on setting this switch 6 11 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V 1 45mA For ease of implementation such a power supply has been provided as an integral part of this design The VLCD power supply can be adjusted by R21 to give an output voltage from 14V to 23V and is enabled disabled by the S1D13704 control signal LCDPWR LCDPWR is an S1D13704 output signal which is configurable as active high or active low by the CNF4 signal status on the rising edge of the RESET signal For the proper operation of the VLCD power supply LCDPWR must be configured as active low Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 12 Adjustable LCD Panel Positive Power Supply
162. amp ChipId if 1D_S1D13704F00A Chipld printf nERROR Did not detect an S1D13704 exit 1 Initialize the S1D13704 This step programs the registers with values taken from the HalInfo struct in appcfg h aA if ERR_OK seSetInit Device printf nERROR Could not initialize device exit 1 The default initialization cleared the display Draw a 100x100 red rectangle in the upper left corner 0 0 of the display E seDrawRect Device 0 0 100 100 1 TRU El a Pause here Ky getch Clear the display Do this by writing 40960 bytes E seWriteDisplayBytes Device 0 0 FORTY_K Setup SwivelView mode af Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 63 Vancouver Design Center seSetHWRotate Device PORTRAIT Draw a solid blue 100x100 rectangle in center of the display This starting co ordinates assuming a 320x240 display is 320 100 2 240 100 2 110 70 sy seDrawRect Device 110 70 210 170 2 TRUI e Done exit 0 Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 64 Epson Research and Development Vancouver Design Center 10 1 2 Sample code without using the S1D13704 HAL API This second sample demonstrates exactly the same sequence as the first howerve
163. and should not be written to 2 1 Frame Rate Calculation The system the S1D13704 is being configured for dictates certain physical constraints such as the width and height of the panel and the video system input clock The following are the formulae for determining the frame rate of a panel The frame rate for a single passive or TFT panel is calculated as follows PCLK F Rat Ss A A A Famerate HDP HNDP x VDP VNDP for a dual passive panel the formula is PCLK VDP FrameRate 2 _______ _ 2 x HDP HNDP x ea VNDP where PCLK Pixel clock in Hz HDP Horizontal Display Period in pixels HNDP Horizontal Non Display Period in pixels VDP Vertical Display Period in lines VNDP Vertical Non Display Period in lines To achieve the desired frame rate the HNDP and VNDP values can be manipulated The example below is a generic routine to calculate HNDP and VNDP from a desired frame rate Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Epson Research and Development Page 10 Vancouver Design Center This routine first performs a formula rearrangement so that HNDP or VNDP can be solved for Start with VNDP set to a small value Loop increasing VNDP and solving the equation for HNDP until satisfactory HNDP and VNDP values are found If no satisfactory values are found then divide CLKI and repeat the process If a satisfactory frame rate still can
164. ardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 52 Epson Research and Development Vancouver Design Center t9 4 gt Frame Pulse y t12 me WU UU UY on o i FUT E E FPDAT 11 0 4 gt Note DRDY is used to indicate the first pixel Figure 7 25 TFT D TFD A C Timing 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 53 Vancouver Design Center Symbol Parameter Min Typ Max Units t1 Shift Pulse period 1 note 1 t2 Shift Pulse pulse width high 0 5 Ts t3 Shift Pulse pulse width low 0 5 Ts t4 Data setup to Shift Pulse falling edge 0 5 Ts t5 Data hold from Shift Pulse falling edge 0 5 Ts t6 Line Pulse cycle time note 2 t7 Line Pulse pulse width low 9 Ts t8 Frame Pulse cycle time note 3 t9 Frame Pulse pulse width low 2t6 t10 Horizontal display period note 4 t11 Line Pulse setup to Shift Pulse falling edge 0 5 Ts t12 elie Rese rt to Line Pulse falling 16 18Ts t13 DRDY to Shift Pulse falling edge setup time 0 5 Ts t14 DRDY pulse width note 5 t15 DRDY falling edge to Line Pulse falling edge note 6 t16 DRDY hold from Shift Pulse falling edge 0 5 Ts t17 Line Pulse Falling edge to DRDY active note 7 250 1 Ts pixel clock period 2
165. ardware and software environment required to provide an interface between the S1D13704 Embedded Memory Color Graphics LCD Controller and the Philips MIPS PR31500 PR31700 Processor For further information on the S1D13704 refer to the 7D13704 Hardware Functional Specifi cation document number X26A A 001 xx For further information on the PR31500 PR31700 contact Philips or refer to the Philips website at http www philips com For further information on the ITE IT8368E refer to the T8368E PC Card GPIO Buffer Chip Specification 1 1 General Description The Philips MIPS PR31500 PR31700 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the S1D13704 connects to the PR31500 PR31700 processor The S1D13704 can be successfully interfaced using one of two configurations e Direct connection to PR31500 PR31700 see Section 2 Direct Connection to the Philips PR31500 PR31700 on page 8 e System design using one ITE IT8368E PC Card GPIO buffer chip see Section 3 System Design Using the ITE IT8368E PC Card Buffer on page 10 Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13704 Issue Date 01 02 12 X26A G 012 02 Page 8 EPSON Research and Development Vancouver Design Center 2 Direct Connection to the Philips PR31500 PR31700 2 1 General Description In this example implementation the 1D13704 occupies the PR31500 PR31700 PC Card slot 1 The S1D13704
166. aster access to the S1D13704 e C I 1 disable CPU space access to the 1D13704 e SC 1 disable Supervisor Code space access to the S1D13704 e SD 0 enable Supervisor Data space access to the 1D13704 e UC 1 disable User Code space access to the S1D13704 e UD 0 enable User Data space access to the S1D13704 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13704 Issue Date 01 02 12 X26A G 01 1 03 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CKG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales supp
167. ata lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Note In an 8 bit environment D 7 0 must also be connected to D 15 8 respectively see Figure 4 1 Typical Implementation of an 8 bit Processor to the S1D13704 Gener ic 2 Interface e Chip Select CS is driven by decoding the high order address lines to select the proper memory address space BHE WE1 is the high byte enable for both read and write cycles Note In an 8 bit environment this signal is driven by inverting address line AO thus indicating that odd addresses are to be R W on the high byte of the data bus WEO is the enable signal for a write access to be driven low when the host CPU is writing the 13704 memory or registers RD is the read enable for the S1D13704 to be driven low when the host CPU is reading data from the S1D13704 WAIT is a signal which is output from the S1D13704 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low
168. ation data on the rising edge of RESET Refer to the D13704 Hardware Functional Specification document number X26A A 001 xx for details The tables below show those configuration settings important to the Generic 2 host bus interface Table 4 1 Summary of Power On Reset Options Signal value on this pin at the rising edge of RESET is used to configure 0 1 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Big Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal Nas configuration for NEC VR4102 support Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 Xx SH 4 interface 0 0 1 X SH 3 interface 0 1 0 Xx reserved 0 1 1 Xx MC68K 1 16 bit 1 0 0 X reserved 1 0 1 Xx MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 Generic 1 16 bit configuration for NEC VR4102 support S1D13704 X26A G 008 05 Interfacing to the NEC VR4102 Microprocessor Issue Date 01 02 12 Epson Research and Development Page 15 Vancouver Design Center 4 3 NEC VR4102 Configuration The NEC Vr4102 provides the internal address decoding necessary to map to an external LCD controller Physical address 0A000000h to OAFFFFFFh 16M bytes is reserved for an external LCD controller The S1D13704 supports up to 40K bytes of display buffer memory and 32 by
169. ay will occupy the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 3 1 Display Buffer Location The S1D13704 contains 40 kilobytes of internal display memory External support logic must be employed to determine the starting address for this display memory in CPU address space On the S5U13704B00C PC platform evaluation boards the address is usually fixed at DOOOOh 3 1 1 1 Bit Per Pixel 2 Colors Gray Shades 1 bit pixels support two color gray shades In this memory format each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out appropriate bits and if necessary setting bits to 1 With color panels the two colors are derived by indexing into positions O and 1 of the Look Up Table For monochrome panels the two gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT If the first two LUT elements are set to black RGB 0 0 0 and white RGB F F E then each 0 bit of display memory will display as a black pixel and each 1 bit will display as a white pixel The two LUT entries can be set to any desired colors for instance red green or cyan yellow Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Figure 3 1 Pixel Storage for I Bp
170. banks of four colors each As with 1 bpp the bank select bits determine the initial offset into the Look Up Table Incrementing a bank select by one bumps the Look Up Table offset by four Table 4 1 2 Bpp Banking Scheme Bank Red LUT Green LUT Blue LUT Addresses Addresses Addresses 0 0 0 1 1 1 0 2 2 2 3 3 3 4 4 4 5 5 5 4 6 6 6 7 7 7 8 8 8 9 9 9 2 A A A B B B C C C D D D 3 E E E F F F Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 17 Vancouver Design Center Issue Date 01 02 12 At 4 bpp the pixel data is a direct index to the color to be displayed At this color depth the Look Up Table Bank Select bits have no effect on the display colors For instance If the data was 7Bh then the first pixel color would be from the RGB values of the 8th Look Up Table address The second pixel would be the colored by the RGB value at the 12th OBh Look Up Table address Table 4 2 4 Bpp Banking Scheme Red LUT Green LUT Blue LUT Addresses Addresses Addresses 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 A A A B B B C C C D D D E E E F F F Programming Notes and Examples S1D13704 X26A G 002 03 Page 18 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center At 8 bpp the lookup scheme g
171. bit 0 Po P4 P2 P3P4P5Pe P7 Ph R 7 Gn 20 Ba 0 Panel Display Host Address Display Memory Figure 10 1 1 2 4 8 Bit Per Pixel Display Data Memory Organization Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 72 11 Look Up Table Architecture 11 1 Gray Shade Display Modes 2 Level Gray Shade Mode Epson Research and Development Vancouver Design Center Table 11 1 Look Up Table Configurations Display Mode 4 bit wide Look Up Table RED GREEN BLUE 2 level gray 4 banks of 2 4 level gray 4 banks of 4 16 level gray 1 bank of 16 2 color 4 bank of 2 4 bank of 2 4 bank of 2 4 color 4 banks of 4 4 banks of 4 4 banks of 4 16 color 1 bank of 16 1 bank of 16 1 bank of 16 256 color 2 banks of 8 2 banks of 8 4 banks of 4 Indicates the Look Up Table is not used for that display mode The following figures are intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations 1 bit pixel data Green Look Up Table Green Bank Select REG 16h bits 3 2 gt o gt 2 gt gt 3 Bank Select Logic gt E gt gt 2 gt 2 Gray Data Format 716 5 4 3 2 1 AO Al A2 A3 A4 A5 A6
172. box will inform the user when they try to save the configuration 1AM i Hi ERROR Fear rate must bs greater then zero Figure 6 ERROR Zero Frame Rate e Input Clock this field specifies the clock rate being applied to the 1D13704 in kHz LUT Control The items in this section control the color depth for the S1D13704 after initialization Lookin Tabie cc i BPF r ZBPP C ABP C BBPR T Bypass LUT Figure 7 LUT Control The color depth selections in this section will become enabled or disabled in response to the panel dimensions entered i e there is only enough memory to operate a 640x480 panel at 1 bit per pixel so the selections for 2 BPP 4 BPP and 8 BPP would be disabled if this size pane was selected e 1 BPP sets the color depth to 1 bit per pixel e 2 BPP sets the color depth to 2 bit per pixel 4 BPP sets the color depth to 4 bit per pixel 8 BPP sets the color depth to 8 bit per pixel 1D13704 13704CFG EXE Configuration Program X26A B 001 02 Issue Date 01 02 08 Epson Research and Development Page 13 Vancouver Design Center Bypass LUT when selected this option causes the lookup table to be bypassed Selecting to bypass the lookup table results in a power saving as the lookup table section of the S1D13704 is powered down when this option is selected This option is only applicable for monochrome displays If a color panel is selected this option is disabled When the lookup table is not enable
173. ch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address 1D13704 3 3V PR31500 PR31700 t IO Vpp CORE Vpop HA 12 0 gt AB 12 0 Py a ail gt AB 15 13 HD 31 24 le gt DB 7 0 HD 23 16 le gt DB 15 8 System RESET gt RESET Voo pull up CARDXWAIT le WAIT DCLKOUT See text r gt CLKI LHA 23 MFIO 10 gt WE1 LHA 22 MFIO 9 gt WEO LHA 21 MFIO 8 RD1 LHA 20 MFIO 7 gt RDO LHA 19 MFIO 6 gt CS LHA 15 13 MFIO 2 0 j BS Figure 3 1 S1D13704 to PR31500 PR31700 Connection Using an IT8368E 1D13704 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 02 Issue Date 01 02 12 EPSON Research and Development Page 11 Vancouver Design Center The Generic 1 host interface control signals of the S1D13704 are asynchronous with respect to the S1D13704 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13704 clock frequencies The S1D13704 also has internal clock dividers providing additional flexibility 3 2 IT8368E Configuration The IT8368E provides ele
174. ct the frame rate Write 80h to the Swivel View Mode Register REG 1Bh The display is now configured for Swivel View mode use Offset zero into display memory will corresponds to the upper left corner of the display The only thing to keep in mind is that the count from the first pixel of one line to the first pixel of the next line refered to as the stride is 128 bytes Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 43 Vancouver Design Center Example 7 Enable alternate SwivelView mode for a 320x240 panel at 4 bpp Note As we have to perform a frame rate calculation for this mode we need to know the fol lowing panel characteristics 320x240 8 bit color to be run at 80 Hz with a 16 MHz in put clock As in the previous example before switching to Swivel View mode display memory should be cleared Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared 1 Calculate and set the Screen 1 Start Word Address register OffsetBytes Width x BitsPerPixel 8 1 240 x 4 8 1 119 0077h Set Screen Display Start Word Address LSB REG 0Ch to 77h and Screen1 Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Line Byte Count LineByteCount Width x BitsPerPixel 8 240 x 4 8 120 78h Set the Line Byte Count REG 1C to 78h 3 Enable SwivelView
175. ction 32 2 3 4 a A ee a A 9 Pel lt SCOPS 0 Ses e a He ko eS Soe Benes A we Mod hee Aha we eee ue ele oom da aI 1 2 Overview Description 2 ee Dd 2 Features ado AA A A he ES AAA a 10 2 1 Integrated Frame Buffer andes eee LO 22 CRU Interfaces reia as che SL a A a ce ar AO 2 3 Display Support e s e 3o e cee ee LO 2 4 Display Modes 2 2 0 002 2 eee 11 2 5 Clock Sources 2 a hn hw ap ee eo Ba ea oe Dake ea a a AL 216 Miscellaneous upea sra soo on Ge ay gh BO hese o de oo aay ee ah aes rs Td Delt PACK ase foe a aby tate ana A Mak oh ob ee ae ee E Typical System Implementation Diagrams 0 000 ee eee 12 4 Functional Block Diagram 1 2 ee 15 4 1 Functional Block Descriptions 2 eee ee ee 15 AL Host Interface soss wt anc Ae haha es Be bo a ae aoe Bae a 15 4 1 2 Memory Controller 0 000 0000000000 20004 15 4 1 3 Sequence Controllers ita ah te ete EO a bee OE eg 15 4 14 Look Up Fable atar aww Anos ata bel a ode aie oe bi asses Bd ee oe 16 415 LED Interface oi A aye i en hes 16 4 1 6 Power Save 0 beer ee a a ee a ed elas ela Bea Ee 16 O PINS AAA AAA EA AAA A O a a 17 S L Pinout Diagrami a Sin ern ar A o a AN 5 2 Pin Description e e k a a e t a a a a e a a a er 18 S21 CHOSEN CE T cti e td E O AA R TATS 18 5 2 2 LED Iere ica a Gerd a a Wao a ae Sar he 20 D223 Clock Input ei kia
176. d BS appropriate external decode logic MUST be used to access the S1D13704 Refer to Table 5 1 Host Bus Interface Pin Mapping on page 13 for connection details S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 7 Parts List Page 19 Item Qty board Designation Part Value Description 1 13 C1 C11 C15 C16 0 1uF 5 50V 0805 ceramic capacitor 2 1 C12 1uF 10 16V Tantalum capacitor size A 3 2 C13 C14 10uF 10 25V Tantalum capacitor size D 4 2 C17 C21 47uF 10 16V Tantalum capacitor size D 5 3 C18 C20 4 7uF 10 50V Tantalum capacitor size D 6 1 C22 56uF 20 63V Electrolytic radial low ESR 7 2 H1 H2 CON34A Header 0 1 17x2 header PTH 8 4 JP1 JP4 HEADER 3 0 1 1x3 header PTH 9 1 J1 AT CON A ISA Bus gold fingers 10 1 J2 AT CON B ISA Bus gold fingers 11 1 J3 AT CON C ISA Bus gold fingers 12 1 J4 AT CON D ISA Bus gold fingers 13 1 J5 CON40A Shrouded header 2x20 PTH center key 14 1 L1 1uH MCI 1812 inductor 15 3 L2 L4 Ferrite bead Philips BDS3 3 8 9 4S2 16 1 Q1 2N3906 PNP signal transistor SOT23 17 1 Q2 2N3903 NPN signal transistor SOT23 18 6 R1 R6 15K 5 0805 resistor 19 7 R7 R13 10K 5 0805 resistor 20 1 R14 470K 5 0805 resistor 21 1 R15 200K 200K Trim POT Spectrol 63S204T607 or equivalent 22 1 R16 14K
177. d Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704VIRT Display Utility X26A B 004 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 13704VIRT 13704VIRT demonstrates the virtual display capability of the S1D13704 A virtual display is where the image to be displayed is larger than the physical display device The display surface is used a viewing window The entire image can be seen only by panning and scrolling 13704VIRT must be configured to work with each different hardware platform Consult documentation for the program 13704CFG EXE which can be used to configure 13704VIRT This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond
178. d Write Enable for high byte individual The S1D13704 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the host bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping a SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgg connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RDA RDA RDA connect to lO Vpp SIZ1 RDO RD WEO WEO WEO connect to IO Vpp SIZO WEO WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 14 Epson Research and Development Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host b
179. d then display intensities are dependent on the values in the lookup table A smaller numerical value in display memory may be displayed with a greater intensity than a larger value When the lookup table is bypassed the colors displayed on the panel are directly propor tional to their memory value i e at 4 bit per pixel 00h will display as black and OFh will display as full intensity Open Click on the Open button to read the settings saved in an executable program based on the S1D13704 hardware abstraction layer Clicking the Open button brings up the standard Windows file open dialog Lonk jr late som D ex le au bor 137 14C4g ene Figure 8 13704CFG File Open Dialog From here the user selects the file to be opened 13704CFG is capable of opening executable files based on the S1D13704 HAL Typically the file extension for these file are EXE for intel platform executables and S9 for 68k and SH3 platform executables 13704CFG EXE Configuration Program S1D13704 Issue Date 01 02 08 X26A B 001 02 Page 14 Epson Research and Development Vancouver Design Center Opening a file reads that files HAL configuration information Use the data read as a starting point in configuring this or other files or to check on the current configuration If 13704CFG is unable locate the HAL information in the selected file the following dialog box is displayed la CFS i 1 ERROR Unable lo locales HAL intonation L F hi f
180. ddress block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal Groups A and B can have a minimum block size of 64K bytes so these are typically used to control memory devices Chip select AO is active immediately after reset so it is typically used to control a boot EPROM device Groups C and D have a minimum block size of 4K bytes so they are well suited to controlling peripheral devices Chip select D3 is associated with the MC68328 on chip PCMCIA control logic 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 3 S1D13704 Host Bus Interface Page 9 This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic 1 and MC68K 1 host bus interfaces that may be used to implement the interface to the MC68328 3 1 Bus Interface Modes The 1D13704 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper
181. deo Invert Enable the S1D13704 supports inverted color output The color inversion can be toggled by software or in response to a signal applied to pin FPDAT11 In order for the hardware color inversion to succeed this option must be selected The color inversion is performed on the output from the LUT HW Video Invert is not availlable for TFT operation HW Power Save Enable the S1D13704 supports two power save modes One is initi ated by software the second in response to input on the GPIOO pin In order for the hardware power save mode to function this option must be selected High Performance improves chip throughput at the expense of power consumption When not selected the internal MCLK signal is divided down version of the internal PCLK signal Table 1 depicts the ratios when high performance is not selected The slower MCLKs result in lower power use Table 1 MCLK to PCLK ratios Color Depth bpp Ratio 1 MCLK PCLK 8 2 MCLK PCLK 4 4 MCLK PCLK 2 8 MCLK PCLK When this option is selected MCLK PCLCK at all pixel depths Running MCLK at higher frequencies results in greater power use 1D13704 13704CFG EXE Configuration Program X26A B 001 02 Issue Date 01 02 08 Epson Research and Development Page 11 Vancouver Design Center e Portrait Mode selecting Portrait Mode causes register settings and timings to be saved for portrait mode operation The HAL is capable of pe
182. der an example where REG 14h REG 13h OCEh for a 320x240 display system The upper 207 lines CEh 1 of the panel show an image from the Screen 1 Start Word Address The remaining 33 lines show an image from the Screen 2 Start Word Address 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 65 Vancouver Design Center Address FFF5h REG 15h Look Up Table Address Register Read Write n a n a Look Up Look Up Look Up Look Up RGB Index RGB Index Table Table Table Table Bit 1 Bit O Address Address Address Address Bit 3 Bit 2 Bit 1 Bit O bits 5 4 bits 3 0 The S1D13704 has three 16 position 4 bit wide Look Up Tables one each for red green and blue Refer to Look Up Table Architecture for details This register selects which Look Up Table position is read write accessible through the Look Up Table Data Register REG 17h RGB Index Bits 1 0 These bits select between the Red Green and Blue Look Up Tables and Auto Increment mode The Green Look Up Table is used in monochrome mode with these bits set to 10b See Note below Look Up Table Address Bits 3 0 These 4 bits select one of the 16 positions in the selected Look Up Table These bits are automatically changed as the Look Up Table Data Register is accessed See Note below Note Accesses to the Look Up Table Data Register automatically increment a
183. dge 0 ns t2 A 15 1 CS hold from AS rising edge 0 ns 13 ASH low to DTACK driven high 16 ns t4 CLK to DTACK low 15 ns t5 AS high to DTACK high 20 ns t6 AS high to DTACK high impedance Telk t7 UDS LDS falling edge to D 15 0 valid write cycle ToLk t8 D 15 0 hold from AS rising edge write cycle 0 ns t9 UDS LDS falling edge to D 15 0 driven read cycle 15 ns t10 D 15 0 valid to DTACK falling edge read cycle 0 ns t11 UDS LDS rising edge to D 15 0 high impedance 10 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 31 Vancouver Design Center 7 1 4 Motorola M68K 2 Interface Timing Terk A JONS A 15 0 CS VALID SIZO SIZ1 R W t gt gt ASH DS Sf t3 3 t4 t6 t Ft gt ie DSACK1 Hiz sles t7 t8 lt gt gt D 31 16 Hi Z Hi Z write VALID t9 t10 1 D 31 16 Hi Z A Hi Z read VALID Figure 7 4 M68K 2 Timing MC68030 Table 7 4 M68K 2 Timing MC68030 Symbol Parameter Min Max Units foLk Bus Clock frequency 0 33 MHz Telk Bus Clock period 1 fcLk ti A 15 0 CS SIZO SIZ1 valid before AS falling ed
184. e 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 202 000 0000 00 13 Table 4 1 List of Connections from MPC821ADS to S1D13704 16 Table 4 2 Configuration Settings ee 18 Table 4 3 Host Bus Selection s ee 18 List of Figures Figure 2 1 PowerPC Memory Read Cycle 0 00 00 002000000 9 Figure 2 2 PowerPC Memory Write Cycle o o e eee eee 10 Figure 4 1 Typical Implementation of MPC821 to S1D13704 Interface 15 Interfacing to the Motorola MPC821 Microprocessor S1D13704 Issue Date 01 02 12 X26A G 010 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13704 Embedded Memory LCD Controller and the Motorola MPC821 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before b
185. e 35 RESET REG 03h bits 1 0 LCDPWR CNF4 1 LCDPWR CNF4 0 FPLINE FPSHIFT FPDAT FPFRAME DRDY 00 11 ACTIVE Figure 7 8 LCD Panel Power On Reset Timing Symbol Parameter Min Typ Max Units H active REG 03h to FPLINE FPFRAME FPSHIFT FPDAT DRDY TFPFRAME ns t2 FPLINE FPFRAME FPSHIFT FPDAT DRDY active to LCDPWR Frames Note Where Tepper amg is the period of FPFRAME and Tre x is the period of the pixel clock Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 36 Epson Research and Development Vancouver Design Center 7 3 2 Power Down Up Timing LCDPWR Override REG 03h bit 3 HW Power Save or Software Power Save REG 03h bits 1 0 1 00 11 00 bl gt i t1 t2 gt FP Signals Active Inactive Active Inactive Active 13 t4 15 gt t6 gt gt t7 _ LCDPWR Active Inactive Active a Inactive Active polarity set by CNF4 Figure 7 9 Power Down Up Timing Table 7 8 Power Down Up Timing Symbol Parameter Min Typ Max Units a HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Frame inactive LCDPWR Override 1 2 HW Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 rama active LCDPWR Override 1
186. e 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S5U13704B00C Rev 1 0 Evaluation Board Implemented using the S1D13704 Embedded Memory Color LCD Controller the S5U13704B00C board is designed for the 16 bit ISA bus environment To accommodate other bus architectures the S5U13704B00C board also provides CPU Bus interface connectors For more information regarding the S1D13704 refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 1 1 Features 80 pin QFP14 package SMT technology for all appropriate devices 4 8 bit monochrome and color passive LCD panel support 9 12 bit LCD TFT D TFD panel support Selectable 3 3V or 5 0V LCD panel support Oscillator support for CLKI up to 50MHz with internal clock divide or 25MHz with no internal clock divide Embedded 40K byte SRAM display buffer for 1 2 4 bit per pixel bpp 2 4 16 level gray shade display and 1 2 4 8 bpp 2 4 16 256 level color display Support for software and hardware power save modes On board adjustable LCD bias positive power supply 23V to 40V On board adjustable LCD bias negative power supply 14V to 24V 16 bit ISA bus support CPU Bus interface header strips for non ISA bus support S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 8 Epson Research and Development Vancouver Design Center 2 Installat
187. e O through 9FFFh The registers occupy the range FFEOh through FFFFh The TMPR3912 22U demultiplexed address lines A16 and above are ignored if the S1D13704 is used thus it is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space If the S1D13705 is used address lines A17 and above are ignored therefore the S1D13705 is aliased 512 times at 128K byte intervals The TMPR3912 22U control signal CARDREG is ignored therefore the S1D13704 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 3 3 S1D13704 5 Configuration and Pin Mapping The 1D13704 5 host bus interface is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration One additional configuration pin for the S1D13704 CNF4 is also used to set the polarity of the LCDPWR signal The table below shows the configuration pin connections to configure the S1D13704 5 for use with the TMPR3912 22U microprocessor Table 3 1 SID13704 5 Configuration for Generic 2 Bus Interface S1D13704 Value hard wired on this pin is used to configure Configuration Pin 1 IO Vpp 0 Vss Generic 1 Big Endian CNF 2 0 E configuration for Toshiba TMPR3912 22U host bus interface When the 1D13704 5 is configured for Generic 2 bus interface mode the host interface pins are ma
188. e address bus of the TX3912 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS latch e g 74 ACT373 The direct connection approach makes use of the S1D13704 in its Generic Interface 2 configuration The following diagram demonstrates a typical implementation of the interface TX3912 RD WE CARD1CSL CARD1CSH 3 3V S1D13704 y gt IO Vpp CORE Vpp RD WE BHE IO Vopr RD WR System RESET RESET Latch PA ALE gt CSH A 2 0 gt AB 15 13 AB 12 0 D 31 24 pees Beet gt DB 15 8 VoD pull up CARD1WAIT WAT DCLKOUT Seset E I Clock divider Fe OF Oscillator BCLK 1D13704 X26A G 004 02 Figure 2 1 SID13704 to TX3912 Direct Connection The Generic 2 host interface control signals of the S1D13704 are asynchronous with respect to the S1D13704 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13704 clock frequencies The S1D13704 also has internal clock dividers providing additional flexibility Interfacing to
189. e constants SCREEN or SCREEN2 to identify which screen to base calculations on xX new starting X position in pixels y new starting Y position in pixels Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG there are several reasons for this return value 1 WhichScreen is not SCREEN1 or SCREEN2 2 the y argument is greater than the last available line less the screen height Note seVirtInit must be been called before calling se VirtMove Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 55 Vancouver Design Center 9 2 4 Register Memory Access The Register Memory Access functions provide access to the S1D13704 registers and display buffer through the HAL int seGetReg int DeviID int Index BYTE pValue Description Reads the value in the register specified by index Parameters DevID registered device ID Index register index to read pValue pointer to a BYTE to receive the register value Return Value ERR_OK operation completed with no problems int seSetReg int DeviD int Index BYTE Value Description Writes value specified in Value to the register specified by Index Parameters DevID registered device ID Index register index to set Value value to write to the register Return Value ERR_OK operation completed with no problems int seReadDisplayByte int DevID DWORD Offset BYTE pByte Description Reads a byte from the dis
190. e falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin 18min 9Ts 3 83min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6amin REG 08h bits 4 0 x 8 t13 t10 Ts 5 t6bmin REG O8h bits 4 0 x 8 t13 Ts 6 t7amin REG O8h bits 4 0 x 8 11 Ts 7 t7bmin REG O8h bits 4 0 x 8 11 t10 Ts S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 7 3 7 Single Color 8 Bit Panel Timing Format 2 Page 45 le VDP Sig VNDP gt FPFRAME yd ae E A o n M DRDY MOD X X FPDAT 7 0 LINE1 X LINE2 X LINES X LINE4 XLINE479XLINE480 LINE1 X LINE2 X P FPLINE l DRDY MOD P HDP pq HNDP gt dl O al rg at AA te AY SL FPDAT7 o 1 R1 X 1 B3 X 1 66 X X X X1 FPDAT6 AAA EO Y a PM LES X FPDAT5 1 81 X 1 G4 X 1 7 X X X1 R639 FPDAT4 1R2 X 1 B4X 1 G7X X X X O X FPDAT3 i 1 X 1 R5 X 1 B7 X X 1 B639 ee FPDAT2 Ba 1G YX X Y ES XRO O X FPDAT1 ARAS YX 1 68 Va N X84 FPDATO A RS Be XX ES ties KBA X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 18 Single Color 8 Bit Panel Timing Format 2
191. e in display memory is not rotated with the switch to SwivelView mode we are about to make Ay pMem LPBYTE MEM_OFFSET do pMem 0 pMem while pMem lt LPBYTE MEM_OFFSET MEM_SIZE SwivelView mode We will use the default SwivelView mode scheme so we have to adjust the ROTATED width to be a power of 2 NOTE current height will become the rotated width tmp 1 while Height gt 1 lt lt tmp tmp Height 1 lt lt tmp OffsetBytes Height BitsPerPixel 8 ae SECs 1 Line Byte Count to size of the ROTATED width i e current height 2 Start Address to the offset of the width of the ROTATED display ex in SwivelView mode the start address registers point to bytes SET_REG 0x1C BYTE OffsetBytes ff setBytes 5 ET_REG 0x0C LOBYTI ET_REG 0x0D HIBYTI OffsetBytes OffsetBytes Bi a nao Set SwivelView mode Use the non X2 default scheme so we don t have to re calc the frame rate MCLK will be lt 25 MHz so we can leave auto switch enabled E SET_REG 0x1B 0x80 Draw a solid blue 100x100 rectangle centered on the display Starting co ordinates assuming a 320x240 display are EX 320 100 2 240 100 2 110 70 for y 70 y lt 180 y 1D13704 Programming Notes and
192. e is not configurable Figure 9 ERROR Unable to read HAL Save Click on the Close button to save the current configuration settings When clicked the standard Windows file Save As dialog box is displayed Swen ma Go les VITAE ME e C TITDAYIAT exe 3T EM cre OTP LAT exe TIRE G cone 137145 HO e 137085 PLT ewe we Fo Ci Sawe atipa Esecitable Fobra ere E Cancel Figure 10 13704CFG Save As Dialog From the save as dialog box first select the type of file to save to in the Save as type edit field 13704CFG currently saves in three file formats e EXE files are binary images containing a HAL structure for execution on Intel plat forms e S9 files are ASCII binary format files used by several embedded systems The S9 file is a variation of S19 files e H files are ASCII C header files which can be included in other programs S1D13704 13704CFG EXE Configuration Program X26A B 001 02 Issue Date 01 02 08 Epson Research and Development Page 15 Vancouver Design Center If an executable file EXE or S9 is selected as the type of file to save to the file being saved to must already exist and be an S1D13704 HAL based program 13704CFG is cannot save to a non existent program If 13704CFG is unable to locate the HAL information in the file being saved to the following dialog box is displayed ERROR Unable lo locals HAL informalon hi Me 5 not configurable
193. ead and write cycles and WEO is the enable signal for a write access These must be generated by external decode hardware based upon the control outputs from the host CPU RD is the read enable for the S1D13704 5 to be driven low when the host CPU is reading data from the 1D13704 5 RD must be generated by external decode hard ware based upon the control outputs from the host CPU WAIT is a signal which is output from the S1D13704 5 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 5 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13704 5 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the 1D13704 5 for Generic 2 mode and must be tied high connected to IOVDD 3 3V RD WR must also be tied high S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 10 EPSON Research and Development 3 TMPR3912 22U and S1D13704 5 Interface 3 1 Hardware Connections Vancouver Design Center The 1D13704 5 occupies the T
194. ed that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 23 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by plac
195. een 1 Start Address registers and always is located at the top of the screen Image 2 is taken from the display memory location pointed to by the Screen 2 Start Address registers and begins after Screen 1 Vertical Size lines Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 5 3 1 Registers Page 31 The other registers required for split screen operations REG OCh through REG ODh Screen 1 Start Word Address and REG OFh through REG 10h Screen 2 Start Word Address are described in Section 5 2 1 on page 28 REG 13 Screen 1 Vertical Size LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14 Screen 1 Vertical Size MSB n a n a n a n a n a n a Bit 9 Bit 8 Figure 5 5 Screen 1 Vertical Size These two registers form a ten bit value which determines the size of screen 1 When the vertical size is equal to or greater than the physical number of lines being displayed there is no visible effect on the display When the vertical size value is less than the number of physically displayed lines display operation works like this 1 From the end of vertical non display beginning of a frame to the number of lines in dicated by vertical size the display data will come from the memory pointed to by the Screen 1 Display Start Address 2 After vertical size lines have been displayed the system will begin displaying data fro
196. een tested with the following S1D13704 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx S1D13704 X26A B 005 03 Page 4 Installation Usage 1D13704 X26A B 005 03 Epson Research and Development Vancouver Design Center PC platform copy the file 13704PLAY EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13704PLAY to the system PC platform at the prompt type 13704play Embedded platform execute 13704play and at the prompt type the command line argument Where displays program revision information The following commands are valid within the 13704PLAY program X index data XA L index datal data2 data3 LA F W addrl addr2 data R W addr count W W addr data Reads writes the registers Writes data to the register specified by the index when data is specified otherwise the register is read Reads all registers Reads writes Look Up Table LUT values Writes data
197. efine REG_NOT_PRESENT_1 define REG_FRAMING define REG_TEST_MODE WARNING xy define MAX_REG ndif HAL _REGS_H S1D13704 X26A G 002 03 E 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Ox0A Ox0B Ox0C Ox0D Ox0E Ox0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Ox1A 0x1B OxLC 0x1D Ox1lE 0x1F MAX_REG must be the last available register 0x1F Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 79 Vancouver Design Center Appendix A Supported Panel Values A 1 Introduction Future versions of this document will supply example tables for programming the S1D13704 for different panels Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 80 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 S1D13704 Register Summary REG 00h Revision CODE REGISTER 10 address FFEOh 2 RO REG 13h SCREEN 1 VERTICAL SIZE REGISTER LSB 1O address FFF3h RW Data Data ai eaS TFT STN Color Dual Width Width Product Code 000110 Revision Code 00 Screen 1 Vertical Size REG 13h REG 14h Mono Single da 7 A R y i y y lt N e sa i y i REG 01 Bit1 BitO Function Bit
198. eginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC821 Bus Overview S1D13704 The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be not
199. el Size Bits 6 0 This register determines the horizontal resolution of the panel This register must be pro grammed with a value calculated as follows HorizontalPanelSizeRegister This register must not be set to a value less than 03h Horizontalh ane Resolution pixels 1 8 REG 05h Vertical Panel Size Register LSB Address FFE5h Read Write Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Size Size Size Size Size Size Size Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 06h Vertical Panel Size Register MSB Address FFE6h Read Write Vertical Panel Vertical Panel n a n a n a n a n a n a Size Size Bit 9 Bit 8 REG 05h bits 7 0 REG 06h bits 1 0 Hardware Functional Specification Vertical Panel Size Bits 9 0 programmed with a value calculated as follows VerticalPanelSizeRegister VerticalPanelResolution lines 1 This 10 bit register determines the vertical resolution of the panel This register must be 3FFh is the maximum value of this register for a vertical resolution of 1024 lines Issue Date 01 02 08 1D13704 X26A A 001 04 Page 60 Epson Research and Development Vancouver Design Center REG 07h FPLINE Start Position Address FFE7h Read Write fila ae ra FPLINE Start FPLINE Start FP
200. elects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WE1F is the high byte enable for both read and write cycles and WEO is the enable signal for a write access These must be generated by external decode hardware based upon the control outputs from the host CPU RD is the read enable for the S1D13704 to be driven low when the host CPU is reading data from the S1D13704 RD must be generated by external decode hardware based upon the control outputs from the host CPU WAIT is a signal which is output from the S1D13704 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13704 internal registers and or Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 12 1D13704 X26A G 008 05 Epson Research and Development Vancouver Design Center refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS i
201. elopment Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704CFG EXE Configuration Program X26A B 001 02 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table of Contents INTOAUCHION i a ee ee a eee ce A ee ee Program Requirements 2 6 ee mm Installation Usage 13704CFG Panel Information Miscellaneous Options System LUT Control Open Save Help Exit Comments is Dcdo a Sela e a ade a aA List of Figures Figure 1 13704CFG WindoW e Figure 2 Panel Information e Figure 3 Miscellaneous Options o Figure 4 System Options e Figure 5 ERROR Frame Rate o e e Figure 6 ERROR Zero Frame Rate o e Fig
202. entative Chip Documentation e Technical manual includes Data Sheet Application Notes and Programmer s Refer ence Software e User Utilities OEM Utilities e Evaluation Software e To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 TECHNICAL MANUAL Issue Date 01 02 12 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13704 X26A Q 001 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 TECHNICAL MANUAL X26A Q 001 04 Issue Date 01 02
203. enter 3 3 MC68K 1 Interface Mode The MC68K 1 Interface Mode can be used to interface to the MC68328 microprocessor if the previously mentioned multiplexed bus signals will not be used for other purposes The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13704 It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB1 through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space AO and WElf are the enables for the low order and high order bytes respectively to be driven low when the host CPU is reading or writing data to the S1D13704 These must be generated by external decode hardware based upon the control outputs from the host CPU RD WRFA is the read write signal that is driven low when the CPU writes to the S1D13704 and is driven high when the CPU is doing a read from the S1D13704 This signal must be generated by external dec
204. ept that they occur as a series of four back to back 32 bit memory reads or writes with the TIP Transfer In Progress output asserted continuously through the burst Burst memory cycles are mainly intended to facil itate cache line fill from program or data memory they are typically not used for transfers to or from IO peripheral devices such as the S1D13704 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 1D13704 X26A G 01 1 03 Page 10 Epson Research and Development Vancouver Design Center 2 2 Chip Select Module 1D13704 X26A G 011 03 In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common pro
205. er Data Strobe Lower Data Strobe e Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The S1D13704 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping See SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vsg connect to lO Vpp RD WR RD WR RD WR R W R W RD1 connect to IO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO0 WE0 WE0 connect to IO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET 1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design Center
206. eriod S1D13704 X26A G 002 03 HNDP and VNDP are calculated to achieve the desired frame rate according to PCLK Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 67 Vancouver Design Center xx Frame Rat EK HDP HNDP VDP VNDP SET_REG 0x08 0x1 El Register 09h FPFRAME Start Position not used by SIN e SET_REG 0x09 0x00 T Register OAh Vertical Non Display Register ER CAlculated in conjunction with register 08h HNDP to EK achieve the desired frame rate Ry SET_REG 0x0A 0x3B Register OBh MOD Rate not used by this panel E SET_REG 0x0B 0x00 Register 0Ch Screen 1 Start Word Address LSB Register ODh Screen 1 Start Word Address MSB KR Start address should be set to 0 a SET_REG 0x0C 0x00 5 SET_REG 0x0D 0x00 Register OFh Screen 2 Start Word Address LSB Register 10h Screen 2 Start Word Address MSB ER Set this start address to 0 too z7 SET_REG 0x0F 0x00 SET_REG 0x10 0x00 Register 12h Memory Address Offset EX Used for setting memory to a width greater than the RA display size Usually set to 0 during initialization ER and programmed to desired value later ky SET_REG 0x12 0x00 Register 13h Screen 1 Vertical Size LSB Registe
207. ese address bits internally 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor will revert to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the S1D13504 therefore the interfaces described in this document do not attempt to support burst cycles However the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13504 address space 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the r
208. espective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Y2 clock cycle The CSNT bit causes chip select and WE to be negated clock cycle earlier than normal The TRLX relaxed timing bit will insert an additional one clock delay between asser tion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit will insert an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 12 Epson Research and Development Vancouver Design Center 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pat
209. ets a little more complicated Each byte of display data contains 3 bits of red lookup 3 bits of green lookup and 2 bits of blue lookup The 16 addresses of the Look Up Table are divided into 2 eight element banks for the red and green components and 4 four element banks for the blue component Table 4 3 8 Bpp Banking Scheme Red Green Red LUT Green LUT Blue Blue LUT Bank Addresses Addresses Bank Addresses 0 0 0 1 1 1 0 2 2 2 3 3 3 0 4 4 4 5 5 5 1 6 6 6 7 7 7 8 8 8 9 9 9 2 A A A B B B 4 C C C D D D 3 E E E F F F Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 19 REG 17h Look Up Table Data Register Read Write is ma Ald Wa LUT Data LUT Data LUT Data LUT Data Bit 3 Bit 2 Bit 1 Bit 0 LUT Data This register is where the 4 bit red green blue data value is written read With each successive read or write the internal RGB selector is incremented Depending on the RGB Index setting one to three access of this register will result in the Look Up Table Address incrementing 4 2 Look Up Table LUT Organization Color and monochrome operation is slightly different Both Look Up Table schemes are described here e The Look Up Table treats the value of a pixel as an index into an ar
210. f unsigned char BYTE typedef unsigned short WORD typedef unsigned long DWORD typedef unsigned int UINT typedef int BOOL ifdef INTEL typedef BYTE far LPBYTE typedef WORD far LPWORD typedef UINT far LPUINT typedef DWORD far LPDWORD Lis typedef BYTE LPBYTE typedef WORD LPWORD typedef UINT LPUINT typedef DWORD LPDWORD ndif ifndef LOBYTE defin OBYTE w BYTE w ndif ifndef HIBYTE defin HIBYTE w BYTE UINT w gt gt 8 OXxFF ndif ifndef LOWORD define LOWORD 1 WORD DWORD 1 ndif ifndef HIWORD define HIWORD 1 WORD DWORD 1 gt gt 16 amp OXxFFFF ndif 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 73 Vancouver Design Center ifndef MAKEWORD define MAKEWORD lo hi WORD WORD 10 WORD hi lt lt 8 endif ifndef MAKELONG define MAKELONG lo hi long WORD 10 DWORD WORD hi lt lt 16 endif ifndef TRUE define TRUE 1 endif ifndef FALSE define FALSE 0 endif define OFF 0 define ON 1 define SCREEN1 1 define SCREEN22 Constants for HW rotate support xe define DEFAULTO define LANDSCAPE 1 define PORTRAIT2 ifndef NULL ifdef __cplusplus define NULL 0 else define NULL void
211. g a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 and Figure 2 2 illustrate typical memory access cycles on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle A 25 0 REG CE1 CE2 OE WE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus S1D13704 Issue Date 01 02 12 X26A G 009 03 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13704 Bus Interface This section is a summary of the host bus interface modes available on the 1D13704 and offers some detail on the Generic 1 host bus interface used to implement the interface to the PC Card bus 3 1 Bus Interface Modes The S1D13704 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported e Hitachi SH 4 e Hitachi SH 3 e Motorola MC68000 using Upp
212. g of the display buffer All there is to do here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero Programming Notes and Examples 1D13704 X26A G 002 03 Issue Date 01 02 12 Page 34 Epson Research and Development Vancouver Design Center 6 LCD Power Sequencing and Power Save Modes 6 1 LCD Power Sequencing 6 2 Registers LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD logic signals Power sequencing is required to prevent long term damage to the panel and to avoid unsightly lines on power down and power up The S1D13704 performs automatic power sequencing when the LCD is enabled or disabled through the Power Save bits in REG 03h or in response to a hardware power save request For most applications the internal power sequencing is the appropriate choice Proper LCD power sequencing dictates there must be a time delay between the LCD power being disabled and the LCD signals being shut down During power up the LCD signals must be active prior to or when power is applied to the LCD The time intervals vary depending on the power supply design One frame after a power save mode has been enabled the 1D 13704 disables LCD power One hundred and twenty seven frames later the LCD logic signals are disabled There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are
213. ge 0 ns t2 A 15 0 CS SIZO SIZ1 hold from AS DS rising edge 0 ns 13 AS low to DSACK1 driven high 22 ns t4 CLK to DSACK1 low 18 ns t5 AS high to DSACK1 high 26 ns t6 AS high to DSACK1 high impedance ToLk t7 DS falling edge to D 31 16 valid write cycle Tetk 2 18 ASH DS rising edge to D 31 16 invalid write cycle 0 ns t9 D 31 16 valid to DSACK1 low read cycle 0 ns t10 AS DS rising edge to D 31 16 high impedance 20 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 32 Epson Research and Development Vancouver Design Center 7 1 5 Generic 1 Interface Timing Tack _ _ __ gt BCLK O A IE a A 15 0 VALID CSH tl t2 lt _ gt 1 _ gt WE0 WE1 RDO RD1 13 5 gt D 15 0 Hi Z write VALID t4 t6 t7 gt gt D 15 0 Hi Z VALID Hi Z read t8 t9 t10 WAITH Hi Z Hi Z Figure 7 5 Generic 1 Timing Table 7 5 Generic 1 Timing Symbol Parameter Min Max Units fBCLK Bus Clock frequency 0 50 MHz Tecik Bus Clock period 1 fBcLK MHz u A 15 0 CS valid to WE0 WE1 low write cycle or RDO RD1 low read 0 ns cycle WEO0 f WE1 high write cycle or RD
214. ge 42 7 6 Examples 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center Example 6 Enable default SwivelView mode for a 320x240 panel at 4 bpp Before switching to SwivelView mode from landscape mode display memory should be cleared to make the user perceived transition smoother Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared In this example we will bypass having to recalculate the horizontal and vertical non display times frame rate by selecting the default Swivel View mode scheme 1 Calculate and set the Screen 1 Start Word Address register OffsetBytes Width x BitsPerPixel 8 1 256 x 4 8 1 127 007Fh Width is the width of the Swivel View mode display in this case the next power of two greater than 240 pixels or 256 Set Screenl Display Start Word Address LSB REG 0Ch to 7Fh and Screen Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Line Byte Count The Line Byte Count also must be based on the power of two width LineByteCount Width x BitsPerPixel 8 256 x 4 8 128 80h Set the Line Byte Count REG 1C to 80h 3 Enable SwivelView mode This example uses the default Swivel View mode scheme If we do not change the SwivelView Mode Pixel Clock Select bits then we will not have to recalculate the non display timings to corre
215. ge 77 Vancouver Design Center 16 Level Color Mode 16 Color Data Format 7 6 5 4 3 2 1 0 Red Look Up Table 16x4 AO BO CO DO A1 B1 C1 Di 0 See Section 10 a 4 bit pixel data 3 gt 4 bit Red display data output e gt be gt C D E F Green Look Up Table 16x4 4 bit Green display data output gt moO Blue Look Up Table 16x4 WN 0 A 4 bit Blue display data output gt mMOQO Figure 11 7 16 Level Color Mode Look Up Table Architecture Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 78 Epson Research and Development Vancouver Design Center 256 Level Color Mode 256 Color Data Format Red Look Up Table 716 55 4 3 2 1 0 Bank 0 R2 R1 RO G2 G1 Go B1 BO 9 2 See Section 10 3 bit pixel data gt 3 4 5 6 Bank Select gt Bank 1 Logic 0 1 2 3 qlo Se a 5 6 7 Red Bank Select REG 16h bit 4 Green Look Up Table Bank 0 0 1 3 bit pixel data 5 gt 4 5 Ala Bank Select
216. gistered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704SHOW Demonstration Program X26A B 002 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 13704SHOW 13704SHOW demonstrates S1D13704 display capabilities by drawing a pattern image at different pixel depths 1 2 4 and 8 bits per pixel on the display 13704SHOW must be configured to work with each different hardware platform Consult documentation for the program 13704CFG EXE which can be used to configure 13704SHOW This software is designed to work in a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations 1D13704 Supported Evaluation Platforms Installation 13704SHOW has been tested with the following S1D13704 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e
217. gistered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center oOo a BON 7 8 Table of Contents Introduction 1 we 1 1 Features Installation and Configuration lt lt eee LCD Interface Pin Mapping CPU Bus Interface Connector Pinouts Host Bus Interface Pin Mapping 026200 ee eee Technical Description soc a a we ee 6 1 ISA Bus Support 6 1 1 Display Adapter Card Support o ooo 6 1 2 Expanded Memory Manager o 6 2 Non ISA Bus Support 6 3 Embedded Memory Support 6 4 Decode Logic 6 5 Clock Input Support 6 6 LCD Panel Voltage Setting 6 7 Monochrome LCD Panel Support 6 8 Color Passive LCD Panel Support 6 9 Color TFT D TFD LCD Panel Support 6 10 Power Save Modes he ote ao gees 6 11 Adjustable LCD Panel Negative Power Supply 6 12 Adjustable LCD Panel Positive Power Supply 6 13 CPU Bus Interface Header Strips Patts List o ee Grae ae ae Sh ae ee ea a ee A Schematic Diagrams 2 2 eee ee es S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue
218. grammable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for port size 8 16 32 bits 0 15 wait states or external acknowledge address space type burst or non burst cycle support and write protect Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 3 S1D13704 Bus Interface Page 11 This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic 1 host bus interface used to implement the interface to the MCF5307 3 1 Bus Interface Modes The 1D13704 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The S1D13704 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuratio
219. h on screen and off screen size the maximum virtual display width for each display mode is 1 bpp 4096 pixels 2 bpp 2048 pixels 4 bpp 1024 pixels 8 bpp 512 pixels The following keyboard commands are for navigation within the program Manual mode Automatic mode any key Both modes 2 y ES En HOME END b ESC scrolls up scrolls down pans to the left pans to the right moves the display screen so that the upper right of the virtual screen shows in the upper right of the display moves the display screen so that the lower left of the virtual screen shows in the lower left of the display changes the direction of screen changes the color depth bits per pixel exits 13704VIRT 13704VIRT Display Utility Issue Date 01 02 08 Epson Research and Development Page 5 Vancouver Design Center 13704VIRT Example 1 Type 13704virt a to automatically pan and scroll 2 Press b to change the bits per pixel from 1 bit per pixel to 2 bits per pixel 3 Repeat steps 1 and 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program Program Messages ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was not found at the configured addresses Check the configuration address using the 13704CFG configuratio
220. have an internal LCD controller or the CPU board must have an LCD controller on it that interfaces to the microprocessor For the TMPR3912 22U microprocessor the S1D13704 or S1D13705 LCDC is used to provide support for LCD panels The LCDC is socketed so that it can be interchanged between the S1D13704 and the S1D13705 These controllers are very similar with the main differences being the amount of embedded display memory and the lookup table architecture LUT The S1D13704 has 40K bytes of display memory and the 1D13705 has 80K bytes The Toshiba TMPR3912 22U processor supports two PC Card PCMCIA slots on the TX RISC Reference Platform The S1D13704 or S1D13705 LCD controller uses the PC Card slot 1 to interface to the TMPR3912 22U therefore this slot is unavailable for use on the TX RISC Reference Platform S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 8 EPSON Research and Development Vancouver Design Center 2 S1D13704 5 Bus Interface This section is summary of the bus interface modes available on the S1D13704 and S1D13705 LCDCs and offers some detail on the Generic 2 bus mode used to implement the interface to the TMPR3912 22U 2 1 Bus Interface Modes The S 1D13704 5 implements a general purpose 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Bus interface mode selections are made du
221. he HAL_STRUCT structure pointed to by IpHalInfo Parameters IpHallnfo pointer to HAL_STRUCT information structure pDevice pointer to the integer to receive the device ID Return Value ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to find an 1D13704 Note No S1D13704 registers are changed by calling seRegisterDevice Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 48 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center seSetlnit int DevID Description Parameters Configures the S1D13704 for operation This function sets all the S1D13704 control registers to their default values Initialization of the S1D13704 was made a stand alone step to accommodate those programs e g 13704PLAY EXE which needed the ability to start and examine the system before changing register contents DevID registered device ID Return Value ERR_OK operation completed with no problems Note After this call the Look Up Table will be set to a default state appropriate to the display type int selnitHal void Description Parameters This function initializes variables used by the HAL library Call this function once when the application starts Normally programmers will never need to call seInitHal On PC platforms seReg isterDevice automatically calls seInitHal Consecutive calls to seRegister Device wil
222. he blue elements at the Look Up Table index specified by the LUT Address After three accesses of REG 17h the LUT Address is incremented The next access of REG 17h will be the red element from the new Look Up Table address By altering the RGB Index the sequence can be changed such that three accesses of REG 17h will affect just the reds or just the greens or just the blues at three different LUT addresses When configured for monochrome panels the mechanism in which writes are handled is slightly different One to three reads are still required to update the LUT Address depending on the setting of the RGB Index bits If the RGB Index bits are set to auto increment then three writes to REG 17h are required to bump the LUT Address Only the last write will affect the display appearance it is copied across all three RGB elements If the RGB Index is set to access just red just green or just blue then a single write to REG 17h is copied to the red green and blue elements of the lookup address and the LUT Address is incre mented Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Look Up Table Address Page 15 The Look Up Table LUT consists of 16 indexed entries each consisting three 4 bit elements red green blue The LUT Address bits select which of the 16 entries is accessed Upon setting the LUT Address an internal pointer is set to the red element Dependent on the
223. his document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704PWR Power Save Utility X26A B 007 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 13704PWR The 13704PWR Power Save Utility is a tool to assist in the testing of the software and hardware power save modes Refer to the section titled Power Save Modes in the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx and the S1D13704 Functional Hardware Specification document number X26A A 001 xx for further information The 13704PWR utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13704CFG EXE which can be used to configure 13704PWR This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software f
224. how the image is being displayed The application image is written to the S1D13704 in the following sense A B C D The display is refreshed by the S1D13704 in the following sense B D A C S1D13704 X26A G 002 03 Epson Research and Development Page 38 Vancouver Design Center physical memory start ee address A TA B Q SwivelView a z a N j gt window display 3 4 start ENE address nS lt x O C D v P 240 5 160 image seen by programmer image refreshed by S1D13704 image in display buffer Figure 7 2 Relationship Between The Screen Image and the Image Refreshed by SID13704 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 7 4 Registers This section describes the registers used to set Swivel View mode operation Page 39 REG OCh Screen 1 Start Word Address LSB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O REG ODh Screen 1 Start Word Address MSB reserved bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 The start address registers must be set for Swivel View mode In SwivelView mode the offset contained in the start address points to a byte REG 1Ch Line Byte Count Register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O The line byte count register informs the S1D13704 of the
225. i eo ee a es ans le a ay eh oR ea a Re 21 52 4 Miscellaneouss ee A dd ak Bee A Se DE Ge a en es 21 55229 r POWER SUPPLY ese bh was as on ected at Geta Se ahi fod A bei tee piers 21 5 3 Summary of Configuration Options 2 2 ee ee 22 5 4 Host Bus Interface Pin Mapping 2 o 22 5 5 LCD Interface Pin Mapping 2 ee 23 D C Ch tracteristics cece eae dc A a AA eae fe 24 A C Characteristics col a a rs haw E 26 7 1 Bus Interface Timing a ap e y a aa Wara 26 7 1 1 SH 4 Interface Timing 26 1 2 4 3 Int rlace Timing ii als A A Be A A A a a 28 7 1 3 Motorola M68K 1 Interface Timing e 30 Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 4 10 11 12 13 14 7 1 4 Motorola M68K 2 Interface Timing 7 1 5 7 1 6 Generic 2 Interface TiMiNg 7 2 Clock Input Requirements 7 3 Display Interface 7 3 1 Power On Reset Timing o 7 3 2 Power Down Up Timing 7 3 3 Single Monochrome 4 Bit Panel Timing 7 3 4 Single Monochrome 8 Bit Panel Timing 7 3 5 Single Color 4 Bit Panel Timing 7 3 6 Single Color 8 Bit Panel Timing Format 1 7 3 7 Single Color 8 Bit Panel Timing Format 2 7 3 8 Dual Monochrome 8 Bit Panel Timing 7 3 9 Dual Color 8 Bit Panel Timing 7 3 10 9 12 Bit TFT D
226. iew Mode is higher than in Default Swivel View Mode The following figure shows how the programmer sees a 240x160 image and how the image is being displayed The application image is written to the S1D13704 in the following sense A B C D The display is refreshed by the 1D13704 in the following sense B D A C physical memory start Le dd address 4 A B A faa a SwivelView z window display S z start oy 2 address 5 3 lt E O C D M y 240 5 160 image seen by programmer image refreshed by S1D13704 image in display buffer Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by S1D13704 Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 82 Epson Research and Development Vancouver Design Center 12 2 1 How to Set Up Alternate SwivelView Mode 1D13704 X26A A 001 04 The following describes the register settings needed to set up Alternate Swivel View Mode for a 160x240x8 bpp image Select Alternate Swivel View Mode REG 1Bh bit 7 1 and bit 6 1 The display refresh circuitry starts at pixel B therefore the Screen 1 Start Address register must be programmed with the address of pixel B or REG ODh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset 160pixels x Sper 1 8bpb AddressOfPixelA AddressOfPixelA 9Fh Where bpp is bits per pixel and bpb is bits per byte The Line Byte Cou
227. ign Center Page 9 Table 2 3 Jumper Settings Description 1 2 2 3 JP1 IOVDD Selection 3 3V IOVDD JP2 RD WR Signal Selection No Connection JP3 BS Signal Selection No Connection JP4 LCD Panel Voltage Selection 3 3V LCD Panel L recommended settings configured for ISA bus support S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 10 Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping Table 3 1 LCD Signal Connector J5 Pinout Connector Single Passive Panel Dual Passive Panel Color TET D TFD Color Mono Color Mono Pin Name Pin f y 3 hE f 4 bit 8 bit Alternate 4 bit 8 bit 8 bit 8 bit 9 bit 12 bit Format BFPDATO 1 DO DO DO LDO LDO R2 R3 BFPDAT1 3 D1 D1 D1 LD1 LD1 R1 R2 BFPDAT2 5 D2 D2 D2 LD2 LD2 RO R1 BFPDAT3 7 D3 D3 D3 LD3 LD3 G2 G3 BFPDAT4 9 DO D4 D4 DO D4 UDO UDO G1 G2 BFPDAT5 11 D1 D5 D5 D1 D5 UD1 UD1 GO G1 BFPDAT6 13 D2 D6 D6 D2 D6 UD2 UD2 B2 B3 BFPDAT7 15 D3 D7 D7 D3 D7 UD3 UD3 B1 B2 BFPDAT8 17 BO B1 BFPDAT9 19 RO BFPDAT10 21 GO BFPDAT11 23 BO BFPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT BFPSHIFT2 35 FPSHIFT2 BFPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE BFPFRAME 39 FPFRAME FPFRAME FPFRAME FPFRAME
228. ign Center bit 4 Input Clock Divide When this bit 0 the operating clock CLK is same as the input clock CLKI When this bit 1 CLK CLKI 2 In landscape mode PCLK CLK and MCLK is selected as per Table 8 3 High Perfor mance Selection In Swivel View mode MCLK and PCLK are derived from CLK as shown in Table 8 9 Selection of PCLK and MCLK in SwivelView Mode on page 69 bit 3 Display Blank This bit blanks the display image When this bit 1 the display is blanked FPDAT lines to the panel are driven low When this bit 0 the display is enabled bit 2 Frame Repeat EL support This feature is used to improve Frame Rate Modulation of EL panels When this bit 1 an internal frame counter runs from 0 to 3FFFFh When the frame counter rolls over the modulated image pattern is repeated every 1 hour when the frame rate is 72Hz When this bit 0 the modulated image pattern is never repeated bit 1 Hardware Video Invert Enable In passive panel modes REG O1h bit 7 0 FPDAT11 is available as either GPIO4 or hardware video invert When this bit 1 Hardware Video Invert is enabled via the FPDAT11 pin When this bit 0 FPDAT11 operates as GPIO4 See Table 8 4 Inverse Video Mode Select Options below Note Video data is inverted after the Look Up Table bit 0 Software Video Invert When this bit 1 Inverse video mode is selected When this bit 0 standard video mode is selected See Table 8 4 Inver
229. ing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus sw AA eel TS TA A 0 31 l XK RDWR XX AS TSIZ 0 1 AT O 3 x Dro 31 XXMAXKAXMAXMAMAXMAXMAKMAX XXX Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor S1D13704 Issue Date 01 02 12 X26A G 010 03 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on the Power PC system bus
230. ing to the NEC VR4102 Microprocessor X26A G 008 05 Issue Date 01 02 12 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents e NEC VR4102 64 32 bit Microprocessor Preliminary User s Manual Epson Research and Development Inc D13704 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X26A A 001 xx e Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx e Epson Research and Development Inc 1D13704 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources NEC web page http www nec com e Epson Research and Development web page http www erd epson com Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 18 7 Technical Support 7 1 Epson LCD Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Santa Clara California Tel 800 366 9782 Fax 800 729 9288 http www nec com S1D13704 X26A G 008 05 North America Epson Electronics America Inc
231. ingle resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle The following diagram shows a typical implementation of the MCF5307 to S1D13704 interface MCF5307 S1D13704 A 16 31 AB 15 0 D O 15 DB 15 0 CS4 CS Vcc 470 TA WAIT WE3 WE1 WE2 WEO OE RD WR RD BCLKO BUSCLK RESET RESET Figure 4 1 Typical Implementation of MCF5307 to S1D13704 Interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 1D13704 X26A G 01 1 03 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13704 Hardware Configuration The S1D13704 uses CNFO through CNF4 and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Table 4 1 Summary of Power On Reset Options and Table 4 2 Host Bus Interface Selection shows the settings used for the S1D13704 in this interface Table 4 1 Summary of Power On Reset Options S1D1370 value on this pin at the rising edge of RESET is used to configure 0 1 4 Pin 0 4 Name CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for MFC5307 support Table 4 2 Host Bus Interface Selection
232. ion and Configuration The S1D13704 has five configuration inputs CNF 4 0 which are read on the rising edge of RESET and are fully configurable on this evaluation board One six position DIP switch is provided on the board to configure these five configuration inputs and to enable disable hardware power save mode The following settings are recommended when using the S5U13704B00C with the ISA bus Table 2 1 Configuration DIP Switch Settings Switch Signal Closed 0 or low Open 1 or high SW1 1 CNFO Sw1 2 CNF1 See Host Bus Selection table below See Host Bus Selection table below SW1 3 CNF2 SW1 4 CNF3 Big Endian SW1 5 CNF4 Active high LCDPWR signal SW1 6 GPIOO Hardware Suspend Enable L l recommended settings configured for ISA bus support Table 2 2 Host Bus Selection Host Bus Interface SH 4 bus interface dp 2 op a jus 02 1 2 S SH 3 bus interface reserved MC68K bus interface 1 16 bit reserved MC68K bus interface 2 16 bit reserved reserved Generic 1 16 bit L l recommended settings configured for ISA bus support olol olo oj o X X X X X Xx 0 0 1 1 0 0 1 1 1 O jJOoO O O O S1D13704 S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 03 Issue Date 01 02 12 Epson Research and Development Vancouver Des
233. ion for MC68328 support Table 4 2 Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved a 1 MC68K 1 0 0 X reserved 1 0 1 X MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 1 Generic 2 16 bit configuration for MC68328 using Generic 1 host bus interface configuration for MC68328 using MC68K 1 host bus interface 4 3 MC68328 Chip Select Configuration S1D13704 X26A G 007 03 The S1D13704 requires a 64K byte address space for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Virtually any chip select other than CSAO or CSD3 would be suitable for the S1D13704 interface In the example interface chip select CSB3 is used to control the S1D13704 A 64K byte address space is used with the S1D13704 control registers mapped into the top 32 bytes of the 64K byte block and the 40K bytes of display buffer mapped to the starting address of the block The chip select should have its RO Read Only bit set to 0 and the WAIT field Wait states should be set to 111b to allow the S1D13704 to terminate bus cycles exter nally Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 02 12 Epson Research and Development Page 15 Vancouver Design Center 5
234. ion rE eae Power Consumption Core Vpp 3 3V IO Vpp 3 3V dane Active Power Save Mode Byes SMA Core 10 Total Software Hardware Input Clock 6MHz Black and White 5 29mW 0 3mwW 5 59mW 1 LCD Panel 320x240 4 bit Single 4 Gray Shades 6 86mW 0 43mW 7 29mW 1 58mW 1 19mW Monochrome 16 Gray Shades 8 15mW 0 55mW 8 70mW Input Clock 6MHz 2 Colors 6 82mW 1 13mW 7 95mW 2 LCD Panel 320x240 4 bit Single Color 4 Colors 7 58mW 2 29mW 9 86mW 1 58mw 1 19mw 16 Colors 8 98mW 2 25mW 11 23mW Input Clock 25MHz 3 LCD Panel 640x480 8 bit Single Black and White 21 38mW 0 92mW 22 30mW 3 09mw 2 71mW Monochrome Input Clock 25MHz 1 2 4 LCD Panel 640x480 8 bit Single Color 2 Colors 23 66mW 2 40mW 26 07mW 3 09mW 2 71mW Input Clock 25MHz 5 LCD Panel 640x480 8 bit Dual Black and White 20 93mW 0 88mW 21 81mW 3 09mw 2 71mW Monochrome Input Clock 25MHz 6 LCD Panel 640x480 8 bit Dual Color 2 Colors 23 78mW 1 93mW 25 72mW 3 09mW 2 71mW Input Clock 25MHz 7 LCD Panel 640x480 9 bit TFT 2 Colors 16 48mW 8 07mW 24 55mW 3 09mw 2 71mW Note 1 Conditions for Software Power Save e CPU interface active signals toggling e CLKI active 2 Conditions for Hardware Power Save e CPU interface inactive high impedance e CLKI active 1D13704 Power Consumption X26A G 006 02 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center 2 Summary Power Co
235. ion that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction 2 N A E a AR A a O aT a a ar alaa a a E 7 1 1 General Description ede gee RA A o bree be ate eh 2 Direct Connection to the Toshiba TX3912 ooo o 8 2 1 General Description E E wee es be hk we ee 9S 2 2 Memory Mapping and pane 2 3 1D13704 Configuration and Pin Mapping 3 System Design Using the ITE IT8368E PC Card Buffer 0 10 3 1 Hardware Description 2 LO 3 2 IT8368E Configuration oa a a ee F 3 3 Memory Mapping and Aliasing oo a a LA 3 4 S1D13704 Configuration a a a a a 13 SOMWAare a a re a Se AN ele A ee A EA 14 Technical Support s aerd a Gis a a een 15 5 1 EPSON LCD Controllers S1D13704 2 2 aa aaa di oe Ay os a 5 2 Toshiba MIPS TX3912 Processor ao a a a aaa LS 9 30 ITETTS308E o morri sic ee E A A A ew A koe at a a a Interfacing t
236. ires more than 127 frames to discharge on power down or if the panel requires starting the LCD logic well in advance of enabling LCD power Power On Enable Sequence The following is the recommended sequence for manually powering up an LCD panel These steps would be used if LCD power had to be applied later than LCD logic 1 Set REG 03h bit 3 LCDPWR Override to 1 ensures that LCD power is disabled 2 Enable LCD logic This is done by either setting GPIOO to 0 for hardware power save mode and or by setting REG 03h bits 1 0 software power save to 11 3 Count x Vertical Non Display Periods x corresponds the length of time LCD logic must be enabled before LCD power up converted to the equivalent vertical non display periods For example at 72 HZ count ing 36 non display periods results in a one half second delay 4 Set REG 03h bit 3 to 0 enable LCD Power Power Off Disable Sequence The following is the recommended sequence for manually powering down an LCD panel These steps would be used if power supply timing requirements were larger than the timings built into the S1D13704 power disable sequence 1 Set REG 03h bit 3 LCDPWR Override to 1 disables LCD Power 2 Count x Vertical Non Display Periods x corresponds to the power supply discharge time converted to the equivalent verti cal non display periods 3 Disable the LCD logic by setting the software power save in REG 03h or setting hard
237. is less than the Vertical Panel Size REG 06h REG O5h then lines 0 to n of the panel contain Screen 1 and lines n 1 to REG 06h REG O5h of the panel contain Screen 2 See Figure 8 1 Screen Register Relationship Split Screen on page 64 If Split Screen is not desired this register must be programmed greater than or equal to the Vertical Panel Size REG 06h and REG O5h In SwivelView modes this register must be programmed greater than or equal to the Verti cal Panel Size REG 06h and REG O5Sh See Swivel View on page 79 Issue Date 01 02 08 1D13704 X26A A 001 04 Page 64 Epson Research and Development Vancouver Design Center REG ODh REG OCh Words Line O Last Pixel Address REG ODh REG OCh Line O Last Pixel Address REG 12h Words 8 REG 04h 1 X BPP 16 Words x Line 0 y K Line 1 Image 1 REG O6h REG 05 1 Lines Line REG 14h REG 13h x Image 2 REG 1 0h REG OFh Words 8 REG 04h 1 Pixels REG 12h Words Where REG ODh REG OCh is the Screen 1 Start Word Address BPP is Bits per Pixel as set by REG 02h bits 7 6 REG 12h is the Address Pitch Adjustment in Words REG 10h REG OFh is the Screen 2 Start Word Address REG 14h REG 13h is the Screen 1 Vertical Size REG 06h REG O5h is the Vertical Panel Size Virtual Image Figure 8 1 Screen Register Relationship Split Screen Consi
238. isplay Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 50 Epson Research and Development Vancouver Design Center Sync Timing Frame Pulse Line Pulse DRDY MOD Data Timing Line Pulse Shift Pulse FPDAT 7 0 Figure 7 23 Dual Color 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge 114 1 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDATT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 Umin 13min 9Ts 3 tBmin REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 x 2 Ts 5 mi
239. isters Epson Research and Development Vancouver Design Center REG 12h Memory Address Offset Register Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 5 1 2 Examples 1D13704 X26A G 002 03 Figure 5 2 Memory Address Offset Register REG 12h forms an 8 bit value called the Memory Address Offset This offset is the number of additional bytes on each line of the display If the offset is set to zero there is no virtual width Note This value does not represent the number of words to be shown on the display The dis play width is set in the Horizontal Display Width register Example 1 In this example we go through the calculations to display a 640x480 im age on a 320x240 panel at 2 bpp Step 1 Calculate the number of pixels per word for this color depth At 2 bpp each byte is comprised of 4 pixels therefore each word contains 8 pixels pixels_per_word 16 bpp 16 2 8 Step 2 Calculate the Memory Address Offset register value We require a total of 640 pixels The horizontal display register will account for 320 pixels this leaves 320 pixels for the Memory Address Offset register to account for offset pixels pixels_per_word 320 8 40 28h The Memory Address Offset register REG 12h will have to be set
240. it per pixel 3 Repeat step 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program S1D13704 13704SPLT Display Utility X26A B 003 02 Issue Date 01 02 08 Epson Research and Development Page 5 Vancouver Design Center Program Messages 13704SPLT Display Utility Issue Date 01 02 08 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was not found at the configured addresses Check the configuration address using the 13704CFG configuration program ERROR Did not detect 13704 The HAL was unable to read the revision code register on the S1D 13704 Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly 1D13704 X26A B 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704SPLT Display Utility X26A B 003 02 Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704VIRT Display Utility Document No X26A B 004 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research an
241. l hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13704 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the S1D13704 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 4 MCF5307 To S1D13704 Interface 4 1 Hardware Description Page 13 The S1D13704 is interfaced to the MCF5307 with a minimal amount of glue logic One inverter is required to change the polarity of the WAIT signal which is an active low signal to insert wait states in the bus cycle while the MCF5307 s Transfer Acknowledge signal TA is an active low signal to end the current bus cycle The inverter is enabled by CS so that TA is not driven by the 1D13704 during non S1D13704 bus cycles A s
242. l not call selnitHal again On non PC platforms the start up code supplied by Seiko will call seInitHal If support code for a new CPU platform is written the programmer must ensure that seInitHAL is called prior to calling other HAL functions None Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 49 9 2 2 Miscellaneous HAL Support Functions in this group do not fit into any specific category of support They provide a miscellaneous range of support for working with the S1D13704 int seGetld int DevID int pld Description Parameters Return Value Reads the S1D13704 revision code register to determine the chip product and revisions The interpreted value is returned in pID DevID registered device ID pld pointer to an integer which will receive the controller ID S1D13704 values returned in pID are ID_S1D13704 ID_S1D13704F00A ID_ UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to identify the display controller Returned when pID returns ID_UNKNOWN void seGetHalVersion const char pVersion const char pStatus const char pStatusRevision Description Parameters Return Value Programming Notes and Examples
243. last address of one line and the first address of the following line If this register is not equal to zero then a virtual image is formed The displayed image is a window into the larger vir tual image See Figure 8 1 Screen Register Relationship Split Screen on page 64 This register has no effect in Swivel View modes See REG 1Ch Line Byte Count Regis ter for Swivel View Mode on page69 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 63 REG 13h Screen 1 Vertical Size Register LSB Address FFF3h Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 14h Screen 1 Vertical Size Register MSB Address FFF4h Read Write Screen 1 Screen 1 n a n a n a n a n a n a Vertical Size Vertical Size Bit 9 Bit 8 REG 14h bits 1 0 REG 13h bits 7 0 Hardware Functional Specification Screen 1 Vertical Size Bits 9 0 This register is used to implement the Split Screen feature of the S1D13704 These bits determine the height in lines of Screen 1 On reset this register is set to Oh In landscape modes if this register is programmed with a value n where n
244. lected this option is disabled This option is STN specific and is disabled if TFT is selected 13704CFG EXE Configuration Program Issue Date 01 02 08 Epson Research and Development Page 9 Vancouver Design Center Format 2 There are two data clocking formats in use by 8 bit color panels The orig inal clocking scheme was designated to be format 1 and the newer scheme was desig nated format 2 Select this option for most 8 bit color panels To date all color panels smaller than 640x480 have been found to be format 2 Setting this attribute incorrectly will result in a garbled display but will not damage the panel The display may appear cut in half or possibly horizontally skewed This option is STN specific and is disabled if TFT is selected It is also disabled if the panel type is selected to be 4 bit or monochrome Frame Repeat is a feature for EL panel support EL panels use a frame of repeated data as the cue to change their polarization Without this change in polarization panel quality deteriorates When Frame Repeat is selected an internal counter causes the periodic repeat of one frame of modulated panel At a frame rate of 72 Hz the repeat period is roughly one hour When not selected the modulated image is never consecutively repeated This option is STN specific and is disabled if TFT is selected MOD Count the mod count value specifies the number of FPLINEs between toggles of the MOD output signal Whe
245. lectronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 5 2 Toshiba MIPS TX3912 Processor http www toshiba com taec nonflash indexproducts html 5 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 02 12 Page 15 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13704 X26A G 004 02 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON 1D13704 Embedded Mem
246. lectronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Copyright 1998 2001 Epson Research and Development Inc All rights reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Ep son EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation MEN X26A C 001 07 07 FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS CE CONTACT Epson Research amp Development Inc Suite 320 11120 Horseshoe Way Richmond B C Canada V7A 5H7 Tel 604 275 5151 Ene
247. lization presented in table form provides the sequences and values to set the registers The notes column comments the reason for the particular value being written This example writes to all the control registers In practice it may be possible to write to only a subset of the registers When the S1D13704 is first powered up all registers unless noted otherwise in the specification are set to zero This example programs these registers to zero to establish a known state The initialization enables the 1D13704 to control a panel with the following specifica tions e 320x240 color dual passive panel at 75Hz e Color Format 2 8 bit data interface e 4 bit per pixel bpp 16 colors e 25 MHz input clock CLKD Table 2 1 SID13704 Initialization Sequence Register Value hex Notes See Also 01 0010 0000 20 Select an passive Single Color panel with a data width of 4 bits 02 1010 0000 BO Select 4 bpp color depth and high performance 03 0000 0011 03 Select normal power operation 04 0010 0111 27 Horizontal display size Reg 04 1 8 39 1 8 320 pixels 05 11101111 EF Vertical display size Reg 06 05 1 06 0000 0000 00 0000 0000 1110 1111 1 239 1 240 lines 07 0000 0000 00 FPLINE start position not used by STN 08 0001 1110 1E ss es illegal Reg 08 4 8 Frame Rate Calculation 09 0000 0000 00 FPFRAME start p
248. lizes the S1D13704 and reads the registers i Initialize the registers Xa Dump all the registers la And the LUT q Exit e All numeric values are considered to be hexadecimal unless identified otherwise For example 10 10h 16 decimal 10t 10 decimal 010b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as though they were typed 13704PLAY Diagnostic Utility Issue Date 01 02 08 Epson Research and Development Page 7 Vancouver Design Center Program Messages 13704PLAY Diagnostic Utility Issue Date 01 02 08 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was not found at the configured addresses Check the configuration address using the 13704CFG configuration program WARNING Did not detect 13704 The HAL did not detect an S1D13704 however 13704PLAY will continue to function 1D13704 X26A B 005 03 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704PLAY Diagnostic Utility X26A B 005 03 Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704BMP Demonstration Program Document No X26A B 006 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to cha
249. lues for 1 Bpp Color Mode LUT Values for 2 Bpp Color Mode o o e e Suggested LUT Values to Simulate VGA Default 16 Color Palette Suggested LUT Values to Simulate VGA Default 256 Color Palette Recommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade o oo o Suggested LUT Values for 4 Bpp Gray Shade o o Number of Pixels Panned Using Start Address o o Default and Alternate SwivelView Mode Comparison List of Figures Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 8 Bpp 256 Colors in One Byte of Display Buffer Viewport Inside a Virtual Display o oo e Memory Address Offset Register oo o e Screen 1 Start Address Registers o o e 320x240 Single Panel For Split Screen o oo o Screen l VerticaliSIZS Si ua A ee to Screen 2 Start Address Registers 2 2 2 2 0 0 00000 e Relationship Between The Screen Image and the Image Refreshed by S1D13704 Relationship Between The Screen Image and the Image Refreshed by S1D13704 Programming Notes and Examples
250. m Screen 2 Display Start Address memory Screen 1 memory is always displayed at the top of the screen followed by screen 2 memory The start address for the screen 2 image may be lower in memory than that of screen 1 i e screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into the display buffer While not particu larly useful it is even possible to set screen 1 and screen 2 to the same address Programming Notes and Examples Issue Date 01 02 12 S1D13704 X26A G 002 03 Page 32 Epson Research and Development Vancouver Design Center REG 0Fh Screen 2 Display Start Address 0 LSB Start Addr Bit 7 Start Addr Bit 6 Start Addr Bit 5 Start Addr Bit 4 Start Addr Bit 3 Start Addr Bit 2 Start Addr Bit 1 Start Addr Bit 0 REG 10h Screen 2 Display S tart Address 0 LSB reserved Start Addr Bit 14 Start Addr Bit 13 Start Addr Bit 12 Start Addr Bit 11 Start Addr Bit 10 Start Addr Bit 9 Start Addr Bit 8 Figure 5 6 Screen 2 Start Address Registers In landscape mode these two registers form the offset to the word in display memory to be displayed immediately after the screen 1 area of display memory Changing these registers by one will shift the display 2 to 16 pixels depending on the current color depth Split screen operation is not supported in SwivelVie
251. mbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 15 Taiwan R O C Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13704 X26A G 013 02 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to an 8 bit Processor X26A G 013 02 Issue Date 01 02 12
252. mentation of PC Card to SID13704 Interface Interfacing to the PC Card Bus Issue Date 01 02 12 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the PC Card host bus interface Table 4 1 Summary of Power On Reset Options Signal Low High CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF4 Active low LCDPWR signal Active high LCDPWR signal fa configuration for PC Card host bus interface Table 4 2 Host Bus Interface Selection CNF2 CNF1 CNFO wo Q Host Bus Interface SH 4 bus interface SH 3 bus interface reserved MC68K bus interface 1 16 bit reserved MC68K bus interface 2 16 bit reserved lololo G l lM MM O X X X X X Xx reserved 1 1 1 1 Generic 2 16 bit ae configuration for PC Card host bus interface Interfacing to the PC Card Bus 1D13704 Issue Date 01 02 12 X26A G 009 03 Page 14 Epson Research and Development Vancouver Design Center 4 3 PAL Equations The PAL equa
253. milies Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The S1D13704 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping See SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vsg connect to lO Vpp RD WR RD WR RD WR R W R W RD1 connect to IO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO0 WE0 WE0 connect to IO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET 1D13704 Interfacing to the NEC VR4102 Micr
254. mmediately upon entering power save mode See Section 7 3 2 Power Down Up Timing on page 36 for further information Hardware Power Save Enable When this bit 1 GPIOO is used as the Hardware Power Save input pin When this bit 0 GPIOO operates normally Table 8 5 Hardware Power Save GPIOO Operation Hardware Power A GPIOO RESET Save Enable SPIS Contig Status Control GPIOO Operation State E REG 18h bit 0 REG 03h bit 2 REG 19h bit 0 0 X Xx Xx GPIOO Input 1 0 0 reads pin status high impedance 1 0 1 0 GPIOO Output 0 1 0 1 1 GPIOO Output 1 Hardware Power Save i 1 ZN Input active high Software Power Save Bits 1 0 These bits select the Power Save Mode as shown in the following table Table 8 6 Software Power Save Mode Selection Bit 1 Bit 0 Mode 0 0 Software Power Save 0 1 reserved 1 0 reserved 1 1 Normal Operation Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Refer to Power Save Modes on page 84 for a complete description Page 59 REG 04h Horizontal Panel Size Register Address FFE4h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n a Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit 6 5 4 3 2 1 0 bits 6 0 Horizontal Pan
255. mode This example uses the alternate Swivel View mode scheme We will not change the Pixel Clock Select settings Write COh to the Swivel View Mode register REG 1Bh 4 Recalculate the frame rate dependents This example assumes the alternate Swivel View mode scheme In this scheme without touching the Pixel Clock Select bits the PCLK value will be equal to CLK 2 Note These examples don t use the Pixel Clock Select bits The ability to divide the PCLK value down further than the default values was added to the S1D13704 to support SwivelView mode on very small panels The Pixel Clock value has changed so we must calculate horizontal and vertical non display times to reach the desired frame rate Rather than perform the frame rate calculations here I will refer the reader to the frame rate calculations in Frame Rate Calculation on page 9 and simply arrive at the following Horizontal Non Display Period 88h Vertical Non Display Period 03h Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 44 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center Plugging the values into the frame rate calculations yields PCLK FrameRate _W _____ HDP HNDP x VDP VNDP 16 000 000 FrameRate a oe 80 69 320 88 x 240 3 For this example the Horizontal Non Display register REG 08h needs to be set to 07h and the Vertical Non Display register
256. must be present for at least one Tc k before the start of an access Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 13 6 Clock Requirements Page 87 The following table shows what clock is required for which function in the 1D13704 Table 13 5 S1D13704 Internal Clock Requirements Function BCLK CLKI Register Read Write Is required during register accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8TgcLk 12TmcLk after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Not Required Memory Read Write Is required during memory accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8TecLk 12TwcLk after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Required Software Power Save Required Can be stopped after 128 frames from entering Software Power Save i e after REG 03h bits 1 0 11 Hardware Power Save Not Required Can be stopped after 128 frames from entering Hardware Power Save Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 88 14 Mechanical Data Epson Research and Development Vancouver Design Center
257. n REG 08h bits 4 0 x 2 x 8 17 Ts 6 t min REG O8h bits 4 0 x 2 x 8 26 Ts S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 51 Vancouver Design Center 7 3 10 9 12 Bit TFT D TFD Panel Timing VNDP2 VDP VNDP gt 4 b4 FPFRAME y FPLINE U U L L L Tol L L L FPDAT 11 0 LINE480 LINE1 X X LINE480 ao FPLINE ooo HNDP HDP HNDP e p lt gt PRSAIET LA Pe A el We 2 3 HN DRY S y oo A A O FPDAT 9 EPDAT 2 0 ooo PO RN ias FPDAT 10 Xr i S A UE a E are FPDATH1 88 NENE T NE Re FPDAT 8 6 Note DRDY is used to indicate the first pixel Example Timing for 640x480 panel Figure 7 24 12 Bit TFT D TFD Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period VNDP1 VNDP2 REG OAH bits 5 0 Lines VNDP1 Vertical Non Display Period 1 REG 09h bits 5 0 Lines VNDP2 Vertical Non Display Period 2 REG OAh bits 5 0 REG O9Ah bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 REG 08h 4 x 8Ts HNDP1 Horizontal Non Display Period 1 REG 07h bits4 0 x 8 16Ts HNDP2 Horizontal Non Display Period 2 REG O8h bits4 0 REG O7h bits 4 0 x 8 16Ts H
258. n REG O08h bits 4 0 x 2 x 8 20 Ts 6 tmin REG 08h bits 4 0 x 2 x 8 29 Ts S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 49 Vancouver Design Center 7 3 9 Dual Color 8 Bit Panel Timing VDP VNDP ta rl gt FPFRAME e ARA FPLINE l I l LJ l I l l I DRDY MOD y ae X FPDAT 7 0 LINE 1 241 X LINE 2 242 X E LINE 239 479XLINE 240 480 LINE 1 241 X FPLINE DRDY MOD X la HDP rie HNDP FESHI mn Sat AA A eo J FPDAT7 en Tar 1 42 X 1 83 X 1 R5 X 1 66 X 1 87 a Y 1 B639 FPDAT6 1 41 X 1 82 X 1 R4 X 1 45 X 1 B6 X 1 R8 X1 R640 OO FPDAT5 PON 1 B1 X 1 R3 X 1 G4 X 1 B5 X 1 R7 X 1 68 X 1 G640 FPDAT4 ae 1 R2 X 1 43 X 1 84 X 1 R6 X 1 67 X 1 B8 x Y 1 8640 FPDAT3 e 241 1X241 62241 B3 241 R5X241 G0 241 B7E X D A FPDAT2 _ Jem G1X241 B2 241 R4X241 G5X241 B6X241 R8 YX EF X FPDAT1 er 241 B1X241 R3N241 G4 241 85X241 R7 241 G8L X X Geno oe FPDATO 0 241 R2X241 G3 241 B4 241 R6X241 G7 241 BBX X n oe x Y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 22 Dual Color 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non D
259. n Parameters This routine writes one or more LUT entries The writes always start with Look Up Table index 0 and continue for Count entries A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component lut x 2 BLUE component Count the number of LUT entries to write Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 01 02 12 1D13704 X26A G 002 03 Page 60 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center int seGetLut int DevID BYTE pLUT int Count Description Parameters This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID pLUT pointer to an array of BYTE lut 16 3 pLUT must point to enough memory to hold Count x 3 bytes of data Count the number of LUT elements to read Return Value ERR_OK operation completed with no problems int seSetLutEntry int DeviD int Index BYTE pEntry Description Parameters This routine writes one
260. n The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping a SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgg connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RDA RDA RDA connect to lO Vpp SIZ1 RDO RD WEO WEO WEO connect to IO Vpp SIZO WEO WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13704 Issue Date 01 02 12 X26A G 01 1 03 Page 12 Epson Research and Development Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the S1D13704 with other CPUs For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Interface M
261. n be reduced by using the internal CLKI 2 and the various PCLK and MCLK dividers for portrait mode A socket for an external oscillator is also provided if a different frequency is required This option is selected by positioning jumper JP8 in the 2 3 position and adding a standard 14 DIP type oscillator in the socket U10 4 2 LCD Connectors 4 2 1 50 pin LCD Module Connector J3 X00A G 004 02 The standard connector used on Toshiba s CPU Modules to connect to the LCD module is included in this CPU module All twelve LCD data lines FPDAT 11 0 from the 1D13704 5 as well as the five video control signals FRPFRAME FPSHIFT FPLINE DRDY LCDPWR are passed through this connector Through this connector the 1D13704 5 supports monochrome and color STN panels up to a resolution of 640x480 as well as color TFT D TFT up to a resolution of 640x480 All touch panel signals from the main board have also been routed through this connector S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 EPSON Research and Development Page 13 Vancouver Design Center 4 2 2 Standard Epson LCD Connector J4 A shrouded 40 pin header J4 is also added to the CPU module to connect to LCD panels This header is the standard LCD connector used on Epson Research and Development evaluation boards and can be used to directly connect LCD panels to the 1D13704 5 controller All LCD signals are buffered to allow 3 3V or 5 0V logic LCD panels to be connected
262. n configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 3 3 S1ID13704 Configuration Using the IT8368E CNF 2 0 S1D13704 Value hard wired on this pin is used to configure Configuration Pin 1 IO Vpp 0 Vss BS Generic 2 CNF3 Big Endian E configuration for connection using ITE IT8368E When the S1D13704 is configured for Generic 1 interface the host interface pins are mapped as in the table below Table 3 4 SID13704 Generic 1 Interface Pin Mapping Pin Name Pin Function WE1 WE1 BS connect to Vss RD WR RD1 RD RDO WEO WEO0 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 S1D13704 X26A G 012 02 Page 14 4 Software 1D13704 X26A G 012 02 EPSON Research and Development Vancouver Design Center Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utili
263. n in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 03 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction gt as 20 0 8 a AA AR A hw aie ee By Gee 7 2 Interfacing to the MCF5307 es 8 2 1 The MCF5307 System Bus 2 a a e a e ee ee 8 Dil OVN EW iad ky ete odo hk ohn dee Ra ve a o E RES 8 2 1 2 Normal Non Burst Bus Transactions e 8 213 Burst Cycles oss arg wae ede TA hee MAR Gd Roe bi wa E ai 9 2 2 Chip Select Modul s c s a kos ee a a Ro ace ot Ge 10 3 1D13704 Bus Interface osos ee bee ee ee ee eee ee ee Lee 11 3 1 Bus Interface Modes 0 2 0 0 0 2 2 F 3 2 Generic 1 Interface Mode 2 2 2 2 02220222 2022 02
264. n program ERROR Did not detect 13704 The HAL was unable to read the revision code register on the S1D 13704 Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly 13704VIRT Display Utility 1D13704 Issue Date 01 02 08 X26A B 004 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704VIRT Display Utility X26A B 004 02 Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704PLAY Diagnostic Utility Document No X26A B 005 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704PLAY Diagnostic Utility X26A B 005 03 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 137
265. n set to 0 default the MOD output signal toggles every FPFRAME This field is for passive panels only and is generally only required for older mono chrome panels FPLINE Start this field specifies the delay in an 8 pixel resolution from the end of a line of display data FPDAT to the leading edge of FPLINE This field is a TFT specific setting and is disabled if an STN panel is chosen FPFRAME Start this field specifies the number of lines between the last line of display data FPDAT and the leading edge of FPFRAME This field is a TFT specific setting and is disabled if an STN panel is chosen FPLINE FPFRAME Polarity these settings control the sync pulse direction of the FPLINE and FPFRAME pulses in TFT modes Select the appropriate pulse direction for the panel being connected Selecting Lo results in an active low sync pulse while Hi results in an active high pulse These settings are TFT specific and are disabled when STN panel is selected When STN panel type is selected the pulse directions are preset to ve ve 13704CFG EXE Configuration Program 1D13704 Issue Date 01 02 08 X26A B 001 02 Page 10 Epson Research and Development Vancouver Design Center Miscellaneous Options Misc Options TH Video Invest Ervsbile FP Hw Power Sirve Enable High Pedlomancs T Poia Moda Figure 3 Miscellaneous Options Miscellaneous options are several items which do not fit into any other category e HW Vi
266. n the type of transfer being attempted e TIP Transfer In Progress which is asserted whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle completing the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 illustrates a typical memory read cycle on the MCF5307 system bus and Figure 2 2 illustrates a memory write cycle Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 9 BCLKO TS TA TIP Ast XX X RW XX XXXXKX SIZ 1 0 TT 1 0 X A D131 01 2000000000000 00000 JU Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 MCF5307 Memory Read Cycle sexo J LJ LI UW LU UL TS TA TIP A310 xX l X Rw IA LKR SIZ 1 0 TT 1 0 X E Drst 0 XXXXXXX valid XXX Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle Burst Cycles Burst cycles are very similar to normal cycles exc
267. ng to the NEC VR4102 Microprocessor S1D13704 Issue Date 01 02 12 X26A G 008 05 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2 1 The NEC VR4102 System Bus 2 1 1 Overview 1D13704 X26A G 008 05 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4102 is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU with its internal SysAD bus The BCU in turn communicates with external devices with its ADD and DAT buses that can be dynamically sized to 16 or 32 bit operation The NEC VR4102 has direct support for an external LCD controller Specific control signals are assigned for an external LCD controller that provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 Microprocessor Iss
268. nge without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704BMP Demonstration Program X26A B 006 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 13704BMP Installation Usage Comments 13704BMP demonstrates S1D 13704 display capabilities by rendering bitmap images on the display The 13704BMP display utility is designed to operate in a personal computer DOS environment and must be configured to work with your display hardware Consult documentation for the program 13704CFG EXE which can be used to configure 13704BMP 13704BMP is not supported on non PC platforms Copy the file 13704BMP EXE to a directory that is in the DOS path on your hard drive At the prompt type 13704bmp bmp_file a time 1 p Where bmp_file the name of the file to display a time automatic mode returns to the operating system afte
269. not found at the configured addresses Check the configuration address using the 13704CFG configuration program ERROR Did not find a 13704 device The HAL was unable to read the revision code register on the S1D13704 Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly ERROR Could not initialize device The HAL failed to initialize the registers 13704SHOW Demonstration Program Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704SPLT Display Utility Document No X26A B 003 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704SPLT Display Utility X26A B 003 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center
270. nputs the byte enable signal for the high data byte BHE Host Bus Interface Pin Mapping for summary CS l 74 O Input This pin inputs the chip select signal BCLK l 71 Input This pin inputs the system bus clock BS l 75 CS Input This e e e e e See pin has multiple functions For SH 3 SH 4 mode this pin inputs the bus start signal BS For MC68K 1 this pin inputs the address strobe AS For MC68K 2 this pin inputs the address strobe AS For Generic 1 this pin must be tied to Vgs For Generic 2 this pin must be tied to IO Vpp Host Bus Interface Pin Mapping for summary RD WR l 79 CS Input This e See Host Bus Interface Pin Mapping for summary pin has multiple functions For SH 3 SH 4 mode this pin inputs the RD WR signal The S1D13704 needs this signal for early decode of the bus cycle For MC68K 1 this pin inputs the R W signal For MC68K 2 this pin inputs the R W signal For Generic 1 this pin inputs the read command for the upper data byte RD1 For Generic 2 this pin must be tied to IO Vpp Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 20 Epson Research and Development Vancouver Design Center Pin Names Type Pin Cell RESET State Description RD 76 CS Input This pin has m
271. ns t6 BS setup 5 ns t7 BS hold 5 ns t8 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 Rising edge CSn to WAIT high impedance 10 ns t11 Falling edge CSn to WAIT driven 15 ns t12 CKIO to WAIT delay 20 ns t13 DB 15 0 setup to 2 CKIO after BS write cycle 0 ns t14 DB 15 0 hold from rising edge of WEn write cycle 0 ns t15 DB 15 0 valid to RDY falling edge setup time read cycle 0 ns t16 Rising edge RD to DB 15 0 high impedance read cycle 10 ns 2 One Software WAIT State Required Note Page 29 CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 30 Epson Research and Development Vancouver Design Center 7 1 3 Motorola M68K 1 Interface Timing Telk o A aoa fF US e A 15 1 CS VALID R WH tl t2 AS UDS LDS INVALID B a t6 DTACK Hiz gt Hi Z 18 t7 gt D 15 0 es lt Y write Hi Z VALID ue 19 t10 p t11 a D 15 0 i 7 read Hie 7 VALID Hiz Figure 7 3 M68K 1 Bus Timing MC68000 Table 7 3 M68K 1 Bus Timing MC68000 Symbol Parameter Min Max Units fork Bus Clock Frequency 0 33 MHz ToLk Bus Clock period 1 fcLK ti A 15 1 CS valid before AS falling e
272. nsumption Issue Date 01 02 12 The system design variables in Section 1 S1D13704 Power Consumption and in Table 1 1 S1D13704 Total Power Consumption show that S1D13704 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13704 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility S1D13704 X26A G 006 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Power Consumption X26A G 006 02 Issue Date 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the Motorola MC68328 Dragonball Microprocessor Document Number X26A G 007 03 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is
273. nt Page 5 Vancouver Design Center 6 Edit the file DISPDRVR C located in X wince platform odo drivers display 4BPP13704 to set the desired screen resolution color depth bpp and panel type The sample code defaults to a 320x240 color single passive 4 bit LCD panel To sup port one of the other listed panels change the define statement 7 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 8 Type BLDDEMO lt ENTER gt at the DOS prompt of the X86 DEMO7 window to gen erate a Windows CE image file NK BIN 1 3 Example Installation Installation for CEPC Environment Windows CE v2 0 can be loaded on a PC using a floppy drive or a hard drive The two methods are described below To load CEPC from a floppy drive 1 Create a DOS bootable floppy disk 2 Edit CONFIG SYS on the floppy disk to contain the following line only device a himem sys 3 Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c wince release nk bin 4 Copy LOADCEPC EXE from c wince public common oak bin to the bootable floppy disk 5 Confirm that NK BIN is located in c wince release 6 Reboot the system from the bootable floppy disk To load CEPC from a hard drive 1 Copy LOADCEPC EXE to the root directory of the hard drive 2 Edit CONFIG SYS on the hard drive to contain the following line only device c himem sys 3 Edit A
274. nt Register for Swivel View Mode must be set to the image width in bytes i e 160 160 L 160 AO ECON Epa bpp Where bpb is bits per byte and bpp is bits per pixel Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g one pixel in 8 bpp mode e Increment the register by the value in the Line Byte Count register to pan vertically by one line e g add AOh to pan by one line in the example above Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Page 83 12 3 Comparison Between Default and Alternate SwivelView Modes Table 12 1 Default and Alternate Swivel View Mode Comparison Item Default SwivelView Mode Alternate SwivelView Mode Memory Requirements The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 160x240x8bpp image would normally require only 38 400 bytes possible within the 40K byte address space but the virtual image is 256x240x8bpp which needs 61 440 bytes not possible Does not require a virtual image Clock Requirements CLK need only be as fast as the required PCLK MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz PCLK then CLK must be 6MHz Note that 25MHz is
275. o insert wait states in the bus cycle The MPC821 Transfer Acknowledge signal TA is an active low signal which ends the current bus cycle The inverter is enabled using CS so that TA is not driven by the 1D13704 during non S1D13704 bus cycles A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and should be tied low connected to GND The following diagram shows a typical implementation of the MPC821 to S1D13704 interface MPC821 S1D13704 A 16 31 AB15 ABO D O 15 DB 15 D0 734 CS Vcc 470 n WAIT WEO WE1 WE1 WEO OE RD WR RD SYSCLK BUSCLK RESET RESET Figure 4 1 Typical Implementation of MPC821 to S1D13704 Interface Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 1D13704 X26A G 010 03 Page 16 4 2 Hardware Connections 1D13704 X26A G 010 03 Epson Research and Development Vancouver Design Center The following table details the connections between the pins and signals of the MPC821 and the S1D13704 Table 4 1 List of Connections from MPC821ADS to S1D13704 MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13704 Signal Name Vcc P6 A1 P6 B1 Vcc A16 P6 B24 SA15 A17 P6 C24 S
276. o Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 0A 02 00 0A 00 03 00 0A 0A 04 OA 00 00 05 0A 00 0A 06 OA 0A 00 07 OA 0A 0A 08 00 00 00 09 00 00 OF OA 00 OF 00 0B 00 OF OF 0C OF 00 00 0D OF 00 OF 0E OF OF 00 OF OF OF OF Programming Notes and Examples Issue Date 01 02 12 1D13704 X26A G 002 03 Page 22 1D13704 X26A G 002 03 8 Bpp Color Epson Research and Development Vancouver Design Center When the S1D13704 is configured for 8 bit per pixel color mode 8 colors from red and green and 4 colors from the blue active banks are displayed The eight red eight green and four blue entries can be set to any color The S1D13704 LUT has four bits 16 levels of intensity control per primary color while a standard VGA RAMDAC has six bits 64 levels This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the S1D13704 LUT i e VGA levels 0 3 map to LUT level 0 VGA levels 4 7 map to LUT level 1 etc The following table shows LUT values that approximate the default 256 color VGA palette Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palett e Index Red Green Blue 00 00 00 00 01 02 02 05 02 04 04 0A 03 06 06 OF 04 09 09 05 0B 0B 06 0D 0D 07 OF OF
277. o the Toshiba MIPS TX3912 Processor 1D13704 Issue Date 01 02 12 X26A G 004 02 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON Research and Development Table 2 1 Table 2 2 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Figure 2 1 Figure 3 1 Issue Date 01 02 12 Page 5 Vancouver Design Center List of Tables S1D13704 Configuration for Direct Connection 2 0 2 2 2 e 9 S1D13704 Generic 2 Interface Pin Mapping e 9 TX3912 to Unbuffered PC Card Slots System Address Mapping 12 TX3912 to PC Card Slots Address Remapping Using the IT8368E 12 S1D13704 Configuration Using the IT8368E o o 13 S1D13704 Generic 1 Interface Pin Mapping e 13 List of Figures S1D13704 to TX3912 Direct Connection e 8 S1D13704 to TX3912 Connection Using an IT8368 o o 10 Interfacing to the Toshiba MIPS TX3912 Processor S1D13704 X26A G 004 02 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 02 Issue Date 01 02 12 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required
278. ocument Sources 2 0 0 0 0 000 0 ee eee ee ee ee 6 7 Technical Support tudo ol ao st a oe ek la ee 17 7 1 EPSON LCD Controllers S1D13704 2 2 2 02 02 2 2 17 7 2 Motorola MC68328 Processor 1 1 ee ee 17 Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 20 00 0000 eee eee 9 Table 4 1 Summary of Power On Reset Options o o 0 000000 00 14 Table 4 2 Host Bus Interface Selection 0 0 00000 00022000 G 14 List of Figures Figure 4 1 Typical Implementation of MC68328 to S1D13704 Interface MC68K 1 12 Figure 4 2 Typical Implementation of MC68328 to S1D13704 Interface Generic 1 13 Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 03 Issue Date 01 02 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction
279. ode 1D13704 X26A G 011 03 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13704 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13704 host interface It is sepa rate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13704 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D 13704 These signals must be generated by externa
280. ode hardware based upon the control output from the host CPU WAIT is a signal which is output from the S1D13704 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal indicates that the address on the address bus is valid This signal must be generated by external decode hardware based upon the control outputs from the host CPU The WEO signal is not used in the bus interface for MC68K 1 and must be tied high tied to IO Vpp Interfacing to the Motorola MC68328 Dragonball Microprocessor 1D13704 Issue Date 01 02 12 X26A G 007 03 Page 12 4 MC68328 To S1D13704 Interface 4 1 Hardware Description Epson Research and Development Vancouver Design Center The interface between the MC68328 and the S1D13704 can be implemented using either the MC68K 1 or Generic 1 host bus interface of the S1D13704 4 1 1 Using The MC68K 1 Host Bus Interface The MC68328 multiplexes dual functions on some of its bus control pins specifically UDS LDS and DTACK In implementations where all of these pins are available for use as bus control pins then
281. of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 02 Issue Date 01 02 12 EPSON Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction a oe te ee a a ae a a a We We We a 7 1 1 General Description Bae ae dame A Hew ard beet at oh 2 Direct Connection to the Philips PR31500 PR31700 lt lt 8 2 1 General Description pl A AAA a 2 2 Memory Mapping and pane 2 3 1D13704 Configuration and Pin Mapping 3 System Design Using the ITE IT8368E PC Card Buffer 0 10 3 1 Hardware Description 2 LO 3 2 IT8368E Configuration oa a a ee F 3 3 Memory Mapping and Aliasing ooa a eee LA 3 4 S1D13704 Configuration 1B SOMHMWAare 00 it Al ee a See ee ee A ne ee A 14 Technical Support lt a a a 15 5 1 EPSON LCD Controllers S1D13704 2 2 a a e o e 1S 5 2 Philips MIPS PR31500 PR31700 Processor 2 eo 15 23 ITEIESS6SE o ic ta Re Meee e A RA a a dD Interfacing to the Philips MIPS P
282. offset of four lines of display 1 Calculate the amount to change start address by BytesPerLine LineByteCount 128 Bytes Lines x BytesPerLine 4 x 128 512 200h 2 Increment the start address registers by the just calculated value In this case 281h 81h 200h will be written to the Screen 1 Start Word Address reg ister pair Set Screenl Display Start Word Address LSB REG OCh to 81h and Screen1 Display Start Word Address MSB REG ODh to 02h Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 46 Epson Research and Development Vancouver Design Center 8 Identifying the 1D13704 As there are several similar products in the 1350X and 1370X LCD controller families which can for the most part share the same code base It may be important for a program to identify between products at run time Identification of the S1D13704 can be performed any time after the system has been powered up by reading REG 00h the Revision Code register The six most significant bits form the product identification code and the two least significant bits form the product revision From reset power on the steps to identifying the S1D13704 are as follows 1 Read REG 00h Mask off the lower two bits the revision code to obtain the product code 2 The product code for the S1D13704 is 018h 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 4
283. ok Up Table For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 1 Pixel 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Figure 3 3 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 13 Vancouver Design Center 3 1 4 Eight Bit Per Pixel 256 Colors In eight bit per pixel mode one byte of display buffer represents one pixel on the display At this color depth the read modify write cycles required by the lessor pixel depths are eliminated Each byte of display memory consists of three pointers into the Look Up Table The three most significant bits form an index into the first eight red values The next three bits are an index into the first eight green values The last two bits form an index into the first four blue Look Up Table entries Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Red bit 2 Red bit 1 Red bit 0 Green bit 2 Green bit 1 Green bit 0 Blue bit 1 Blue bit 0 Figure 3 4 Pixel Storage for 8 Bpp 256 Colors in One Byte of Display Buffer Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 14 Ep
284. om two different outputs driving the same input Refer to Table 5 1 Host Bus Interface Pin Mapping for connection details Note When using a 3 3V host bus interface IOVDD must be set to 3 3V by setting jumper JP1 to the 2 3 position Refer to Table 2 3 Jumper Settings on page 9 6 3 Embedded Memory Support The S1D13704 contains 40K bytes of 16 bit SRAM used for the display buffer The SRAM starting address is set at DOOOOh Starting at this address the board design decodes a 64K byte segment accommodating both the 40K byte display buffer and the 1D 13704 internal register set The S1D13704 registers are mapped into the upper 32 bytes of the 64K byte segment DFFEO0h to DFFFFh 6 4 Decode Logic All the required decode logic is provided through a TIBPAL16L8 15 PAL U7 socketed This PAL contains the following equations ICS Address gt hD0000 amp Address lt hDFFFF REFRESH RESET MEMCS16 Addressl gt h0C0000 amp Addressl lt hODFFFF RESET_ RESET S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13704 Issue Date 01 02 12 X26A G 005 03 Page 16 Epson Research and Development Vancouver Design Center 6 5 Clock Input Support The input clock CLKI frequency can be up to 50 0MHz for the S1D13704 if the internal clock divide by 2 is set If the clock divide is not used the maximum CLKI frequency is
285. on the internet at http www eea epson com Interfacing to an 8 bit Processor 1D13704 Issue Date 01 02 12 X26A G 013 02 Page 14 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Epson Research and Development Inc S D13704 Embedded Memory LCD Controller Hardware Functional Specification Document Number X26A A 002 xx e Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx e Epson Research and Development Inc Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Epson Electronics America Website http www eea epson com S1D13704 Interfacing to an 8 bit Processor X26A G 013 02 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD CRT Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Interfacing to an 8 bit Processor Issue Date 01 02 12 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics G
286. opment Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx Installation PC platform Copy the file 13704SPLT EXE to a directory that is in the DOS path on your hard drive Embedded platform Download the program 13704SPLT to the system 13704SPLT Display Utility S1D13704 Issue Date 01 02 08 X26A B 003 02 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform at the prompt type 13704SPLT a 1 p Embedded platform execute 13704spl1t and at the prompt type the command line argument Where no argument enables manual split screen operation a enables automatic split screen operation a timer is used to move screen 2 n display the help screen After starting 13704SPLT the following keyboard commands are available Manual mode u move Screen 2 up Jl d move Screen 2 down HOME covers Screen 1 with Screen 2 END displays only Screen 1 Automatic mode any key change the direction of split screen movement for PC only Both modes b changes the color depth bits per pixel ESC exits 13704SPLT 13704SPLT Example 1 Type 13704splt a to automatically move the split screen 2 Press b to change the color depth from 1 bit per pixel to 2 b
287. oprocessor X26A G 008 05 Issue Date 01 02 12 Epson Research and Development Page 11 Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the S1D13704 with other CPUs For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13704 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the VR4102 control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13704 It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 s
288. or the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the PC Card Bus S1D13704 Issue Date 01 02 12 X26A G 009 03 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most micro processors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the addre
289. orola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 20 4 5 Test Software BR4 OR4 MemStart address RevCodeReg ter Start registers enable bits clock mem space Loop end 1D13704 X26A G 010 03 Epson Research and Development Vancouver Design Center The test software to exercise this interface is very simple It configures chip select 4 on the MPC821 to map the 1D13704 to an unused 64k byte block of address space and loads the appropriate values into the option register for CS4 At that point the software runs in a tight loop reading the 13704 Revision Code Register REG 00h which allows monitoring of the bus timing on a logic analyzer The source code for this test routine is as follows equ equ equ equ mfspr andis andis oris ori stw andis oris ori stw andis oris lbz 120 124 40 FFEO r1 IMMR PUES E BEE E2 r00 r2 r2 MemStart r2 r2 0801 r2 BR4 r1 200 E2 12 SECO r2 r2 0708 r2 OR4 r1 El y 20 0 r1 r1 MemStart r0 RevCodeReg r1 Loop CS4 base register CS4 option register upper word of S1D13704 start address of Revision Code Regis get base address of internal clear lower 16 bits to 0 clear r2 write base address port size 16 bits select GPCM write value to base register clear r2 address mask use upper 10 normal CS negation delay CS inhibit burst write to op
290. ort contact or on the internet at http www erd epson com 1D13704 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 03 Issue Date 01 02 12 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM AD available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc S1D13704 Hardware Functional Specification Document Number X26A A 002 xx Epson Research and Development Inc S5U13704B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc D13704 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Research and Development Website http www erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13704 Issue Date 01 02 12 X26A G 01 1 03 Page 18 7 Technical Support 7 1 EPSON LCD Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road
291. ory Color LCD Controller 1D13704 Power Consumption Document Number X26A G 006 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Power Consumption X26A G 006 02 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center 1 S1D13704 Power Consumption Power Consumption Issue Date 01 02 12 S1D13704 power consumption is affected by many system design variables Input clock frequency CLKTI the CLKI frequency and the internal clock divide register deter mine the operating clock CLK frequency of the S1D13704 The higher CLK is the higher the frame fate performance and power consumption CPU interface the S1D13704 current consumption depends on the BUSCLK frequency data width number of toggling pins
292. osition not used by STN 0A 0010 0110 26 Vertical non display period REG OA 38 lines Frame Rate Calculation 0B 0000 0000 00 MOD rate not required for this panel 0C 0000 0000 00 KEN Screen 1 Start Address set to 0 for initialization Split Screen on page 30 OD 0000 0000 00 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 9 Vancouver Design Center Table 2 1 S1D13704 Initialization Sequence Continued Register Value hex Notes See Also 0F 0000 0000 00 Screen 2 Start Address set to 0 for initialization 10 0000 0000 00 12 0000 0000 00 Memory Address offset not virtual setup so set to 0 13 1111 1111 FF 14 0000 0011 03 Set the vertical size to the maximum value Split Screen on page 30 15 0000 0000 00 16 0000 0000 00 Look Up Table LUT on SetLUT control registers to O for this example page 14 17 0000 0000 00 18 0000 0000 00 19 0000 0000 00 GPIO control and status registers set to 0 1A 0000 0000 00 Set the scratch pad bits to O 18 0000 0000 00 We are not setting up SwivelView mode so set this register to 0 1C 0000 0000 00 Line Byte Count is only required for SwivelView mode 1E 1F 0000 0000 00 ul E PR Ru Ru RP A RIA Ru ee ee These registers are reserved
293. p 2 Colors Gray Shades in One Byte of Display Buffer Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 12 Epson Research and Development Vancouver Design Center 3 1 2 2 Bit Per Pixel 4 Colors Gray Shades 2 bit pixels support four color gray shades In this memory format each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the appropriate bits and if necessary setting bits to 1 For color panels the four colors are derived by indexing into positions 0 through 3 of the Look Up Table For monochrome panels the four gray shades are generated by indexing into the first four elements of the green component of the Look Up Table Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 2 Pixel 2 Pixel 3 Pixel 3 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit O Bit 1 Bit 0 Figure 3 2 Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer 3 1 3 4 Bit Per Pixel 16 Colors Gray Shades Four bit pixels support 16 color gray shades In this memory format each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 For color panels the 16 colors are derived by indexing into the first 16 positions of the Lo
294. panning and scrolling e split screen display 5 1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display The difference can be in the horizontal vertical or both dimensions To view the image the display is used as a window into the display buffer At any given time only a portion of the image is visible Panning and scrolling are used to view the full image The Memory Address Offset register determines the number of horizontal pixels in the virtual image The offset register can be used to specify from 0 to 255 additional words for each scan line At 1 bpp 255 words span an additional 4 080 pixels At 8 bpp 255 words span an additional 510 pixels The maximum vertical size of the virtual image is the result of dividing 40960 bytes of display memory by the number of bytes on each line i e at 1 bpp with a 320x240 panel set for a virtual width of 640x480 there is enough memory for 512 lines Figure 5 1 Viewport Inside a Virtual Display depicts a typical use of a virtual display The display panel is 320x240 pixels an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling 320x240 gt Viewport 640x480 Virtual Display Figure 5 1 Viewport Inside a Virtual Display Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 26 5 1 1 Reg
295. pecification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 43 Vancouver Design Center 7 3 6 Single Color 8 Bit Panel Timing Format 1 VDP VNDP 7 FPFRAME po FPLINE l l l es acl l l l l FPDAT 7 0 LINE1 X LINE2 X LINES X LINE4 X XLINE479XLINE480 LINE1 X LINE2 X FPLINE l FPSHIFT E AAA e ee e a en HDP HNDP pa gt FPSHIFT 2 z FPDAT7 TRI YX 1 G1 X 1 66 X 1 B6 ABONA Y 1636 FPDAT6 o 180 a a X1 G12X 1812 X ree X FPDAT5 N A 62 X 1 B2 X 1 87 X R8 X1 RIBX 1 413 X TGEA X FPDAT4 n 1 R3 X 163 X_ 1 68 X_1 B8 X 1 B13X 1RIE X 1 R638 FPDAT3 os 183 X 1 R4 X 1 R9 X 1 69 X1 G14X 1B14 X 1 B6389 FPDAT2 as 64 X 1 84 Y 1 89 X 1 RIO1 R15X 1 15 X 1 663 A X FPDAT1 o TRS X 1 65 Y 1 G10X 1 B10X 11 815 X1 RI6 X RA O X FPDATO 1 85 X 1 R6 X 1 R11X 1 11 1 G16 X 1 B16L X 1 B640 7 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 16 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HND
296. peed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68328 to S1D13704 using the Generic 1 host bus interface MC68328 1D13704 A 15 0 AB 15 0 D 15 0 DB 15 0 CSB3 CS Vcc 470 DTACK i WAIT UWE WE1 LWE WEO OE RD WR RD CLKO BUSCLK RESET RESET Figure 4 2 Typical Implementation of MC68328 to SID13704 Interface Generic 1 Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 02 12 1D13704 X26A G 007 03 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the D13704 Hardware Functional Specification document number X26A A 001 xx for details The tables below show those configuration settings important to the MC68K 1 and Generic 1 host bus interfaces Table 4 1 Summary of Power On Reset Options S1D13704 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configurat
297. pin is used to configure Configuration Pin 1 IO Vpp 0 Vss BS Generic 2 CNF3 Big Endian E configuration for connection using ITE IT8368E When the S1D13704 is configured for Generic 1 interface the host interface pins are mapped as in the table below Table 3 4 SID13704 Generic 1 Interface Pin Mapping Pin Name Pin Function WE1 WE1 BS connect to Vss RD WR RD1 RD RDO WEO WEO0 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 02 12 S1D13704 X26A G 004 02 Page 14 4 Software 1D13704 X26A G 004 02 EPSON Research and Development Vancouver Design Center Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or www erd epson com Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 01 02 12 EPSON Research and Development Vancouver Design Center 5 Technical Support 5 1 EPSON LCD Controllers S1D13704 Japan Seiko Epson Corporation E
298. play buffer at the specified offset and returns the value in pByte Parameters DevID registered device ID Offset offset in bytes from start of the display buffer to read from pByte pointer to a BYTE to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater 40 kb Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 56 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center int seReadDisplayWord int DevID DWORD Offset WORD pWord Description Reads a word from the display buffer at the specified offset and returns the value in pWord Parameters DevID registered device ID Offset offset in bytes from start of the display buffer to read from pWord pointer to a WORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 40 kb int seReadDisplayDword int DevID DWORD Offset DWORD pDword Description Reads a dword from the display buffer at the specified offset and returns the value in pDword Parameters DevID registered device ID Offset offset from start of the display buffer to read from pDword pointer to a DWORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 40 kb int seWriteDisplayBytes in
299. pointer into the RGB Look Up Tables The pointer sequence varies as shown in the table below Table 8 7 Look Up Table Access REG 01h REG 15h Look Up Table bit 5 bit 5 bit 4 Selected Pointer Sequence Green Gray Look Up Table 1 0 0 Auto Increment R n G n Bin R n 1 G n 1 1 0 1 Red Look Up Table R n R n 1 R n 2 Green Gray Look Up Table 1 1 1 Blue Look Up Table B n B n 1 B n 2 0 1 0 Gn G n 1 G n 2 1 1 0 Gn G n 1 G n 2 In Auto Increment mode writing the Look Up Table Address Register automatically sets the pointer to the Red Look Up Table For example writing a value 03 into the Look Up Table Address Register selects Auto Increment mode and sets the pointer to R 3 Subsequent accesses to the Look Up Table Data Register move the pointer onto G 3 B 3 R 4 etc Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 66 Epson Research and Development Vancouver Design Center Address FFF6h REG 16h Look Up Table Bank Select Register Read Write n a n a Red Bank Select Bit 1 Red Bank Select Bit 0 Green Bank Select Bit 1 Green Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 bits 7 6 bits 5 4 bits 3 2 bit 1 0 1D13704 X26A A 001 04 n a Red Bank Select Bits 1 0 In 1 bit per pixel bpp color
300. pped as in the table below Table 3 2 SID13704 5 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR Connect to lO Vpp RD RD WEO WE S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 12 EPSON Research and Development Vancouver Design Center 4 CPU Module Description 4 1 Clock Signals 4 1 1 BUSCLK 4 1 2 CLKI This section will describe the various parts of the CPU module that pertain to the 1D13704 5 LCD Controller Because the bus clock for the S1D13704 5 does not need to be synchronous with the bus interface control signals a lot of flexibility is available in the choice for BUSCLK In this CPU module BUSCLK is a divided by two version of the SDRAM clock signal DCLKOUT Since DCLKOUT equals 73 728MHz BUSCLK 36 864MHz The pixel clock for the S1D13704 5 CLKI is also asynchronous with respect to the interface control signals This clock is selected based upon panel frame rates power vs performance budget and maximum input frequencies The maximum CLKI input is 25MHz if the internal CLKI 2 isn t used and if it is used the maximum input is 5OMHz On the CPU module CLKI s default input is a divided by four version of DCLKOUT which gives a CLKI 18 432MHZ This frequency gives good performance for 320x240 resolution panels for both portrait and landscape modes If power saving is desired the CLKI ca
301. ptions This document is intended for two audiences Video Subsystem Designers and Software Developers Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com 1 2 Overview Description The S1D13704 is a color monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer The high integration of the S1D13704 provides a low cost low power single chip solution to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Swivelview 90 Hardware Rotate feature of the S1D13704 Virtual and Split Screen are just some of the display modes supported The above features combined with the Operating System independence of the S1D13704 make it the ideal solution for a wide variety of applica tions Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 10 Epson Research and Development Vancouver Design Center 2 Features 2 1 Integrated Frame Buffer e Embedded 40K byte SRAM display buffer 2 2 CPU Interface e Direct support of the following interfaces Hitachi SH 3 Hitachi SH 4 Motorola
302. r time seconds Tf time is not specified the default is 5 seconds This option is intended for use with batch files to automate displaying a series of images EL override default configuration settings and set landscape display mode p override default configuration settings and set portrait display mode displays the Help screen e 13704BMP currently views only Windows BMP format images 13704BMP Demonstration Program 1D13704 Issue Date 01 02 08 X26A B 006 02 Page 4 Epson Research and Development Vancouver Design Center Program Messages 1D13704 X26A B 006 02 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was not found at the configured addresses Check the configuration address using the 13704CFG configuration program ERROR Did not detect 13704 The HAL was unable to read the revision code register on the S1D13704 Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly 13704BMP Demonstration Program Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller 13704PWR Power Save Utility Document Number X26A B 007 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use t
303. r 14h Screen 1 Vertical Size MSB Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 68 S1D13704 Epson Research and Development Vancouver Design Center ER Set to maximum i e Ox3FF This register is used Ae for split screen operation and should be set to 0 ate during initialization ia SET_REG 0x13 OxFF SET_REG 0x14 0x03 Look Up Table In this example the LUT will be programmed in the register sequenc In practice the LUT would probably be done after the other registers AA Register 15h Look Up Table Address ax Set to 0 to start RGB sequencing at the first LUT entry SET_REG 0x15 0x00 Register 16h Look Up Table Bank Select EE Set all the banks to 0 ae At 4BPP this makes no difference however it will affect pl appearance at other color depths T SET_REG 0x16 0x00 Register 17h Look Up Table Data a Write 16 RGB triplets to setup the LUT for 4BPP operation ds The LUT is 16 elements deep 4BPP uses all the idices EF pLUT Color_4BPP for LUTcount 0 LUTcount lt 16 LUTcount for RGBcount 0 RGBcount lt 3 RGBcount SET_REG 0x17 pLUT pLUT Register 18h GPIO Configuration set to 0 ER 0 configures the GPIO pins for input power on default i SET_REG 0x18 0x00
304. r Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 0Dh Screen 1 Display Start Address 1 MSB r s iwed Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Figure 5 3 Screen I Start Address Registers In landscape mode these two registers form the offset to the word in display memory to be displayed in the upper left corner of the screen Screen 1 is always the top of a display frame starting in the upper left corner and descending downward Changing these registers by one will shift the display 2 to 16 pixels depending on the current color depth In SwivelView mode these registers form the offset to the byte in display memory from where screen 1 will start displaying Changing these registers in Swivel View mode will result in a shift of 1 to 8 pixels depending on the color depth Refer to Table 5 1 Number of Pixels Panned Using Start Address to see the minimum number of pixels affected by a change of one to these registers Table 5 1 Number of Pixels Panned Using Start Address Color Depth bpp SwivelView Mode Number of Pixels Panned Landscape Mode Pixels per Word Number of Pixels Panned 1 16 16 8 2 8 8 4 4 4 4 2 8 2 2 1 5 2 2 Examples 1D13704 X26A G 002 03 For the following examples assume the display system has been set up to view a 320x240 4 bpp
305. r the HAL 1s not used all manipulation is done by manually adjusting the registers SAMPLE2 C Sample code demonstating a direct access of the S1D13704 Created 1998 Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All Rights Reserved The sample code using direct S1D13704 access will configure for the following 320x240 Single Color 8 bit SIN format 2 4 bpp 70 Hz Frame Rate 25 MHz CLKi High Performance enabled Notes 1 This code is pseudo C code intended to show technique mem It is assumed that pointers can access the relevant memory addresses 2 Register setup is done with discreet writes rather than being table EK driven This allows for clearer commenting It is more efficient to KR loop through the array writing each element to a control register 3 The array of register values as produced by 1374CFG EXE is included ER here I used the values directly rather than refer to the register da array in the sample code kk kk include lt conio h gt Look up table for 4 bpp color i unsigned char Color_4BPP 16 3 0x00 0x00 0x00 BLACK 0x00 0x00 Ox0A BLUE e 0x00 Ox0A 0x00 GREEN 0x00 Ox0A Ox0A CYAN Ox0A 0x00 0x00 RED Ox0A 0x00 Ox0A PURPLE Ox0A Ox0A 0x00 YELLOW Ox0A Ox0A Ox0A WHITE 0x00 0x
306. rated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D 13704 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the S1D13704 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13704 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the S1D13704 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 4 MPC821 to S1D13704 Interface 4 1 Hardware Description Page 15 The interface between the S1D13704 and the MPC821 requires minimal glue logic One inverter is required to change the polarity of the WAIT signal an active low signal t
307. ray of colors or gray shades For example a pixel value of zero would point to the first LUT entry a pixel value of 7 would point to the eighth LUT entry e The value inside each LUT entry represents the intensity of the given color or gray shade This intensity can range in value between 00 and OFh The following table shows how many elements from each Look Up Table index are used at the different color depths Table 4 4 Look Up Table Configurations 4 Bit Wide Look Up Table Display Mode Red Green Blue 1 Bpp Gray 4 banks of 2 2 Bpp Gray 4 banks of 4 4 Bpp Gray 1 bank of 16 1 Bpp Color 4 banks of 2 4 banks of 2 4 banks of 2 2 Bpp Color 4 banks of 4 4 banks of 4 4 banks of 4 4 Bpp Color 1 bank of 16 1 bank of 16 1 bank of 16 8 Bpp Color 2 banks of 8 2 banks of 8 4 banks of 4 E 1 Indicates the Look Up Table is not used for that display mode Programming Notes and Examples Issue Date 01 02 12 S1D13704 X26A G 002 03 Page 20 Color Modes 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center 1 Bpp Color When the 1D13704 is configured for 1 bit per pixel color mode only the first two colors from the active bank are displayed The two entries can be set to any color but are typically set to black and white Each byte in the display buffer contains 8 bits each bit represents an individual pixel A bit value of 0 results in the Look Up T
308. reen 2 Start Address Register LSB Address FFEFh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 10h Screen 2 Start Address Register MSB Address FFFOh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 10h bit 6 0 REG OFh bit 7 0 REG 10h bit 7 Screen 2 Start Address Bits 14 0 These bits determine the word address of the start of Screen 2 in landscape modes or the byte address of the start of Screen 2 in Swivel View modes Screen 2 Start Address Bit 15 This bit is for Swivel View mode only and has no effect in Landscape mode REG 12h Memory Address Offset Register Address FFF2h Read Write Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 bits 7 0 Memory Address Offset Bits 7 0 Landscape Modes Only This register is used to create a virtual image by setting a word offset between the
309. representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows is a registered trademark of Microsoft Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 Windows CE Display Drivers X26A E 001 02 Issue Date 01 02 08 Epson Research and Development Page 3 Vancouver Design Center 1 WINDOWS CE DISPLAY DRIVERS The Windows CE display drivers are designed to support the S1D13704 Embedded Memory LCD Controller running under the Microsoft Windows CE operating system Available drivers include 4 bit per pixel landscape mode and 4 bit per pixel portrait mode For updated source code visit Epson Research and Development on the World Wide Web at www erd epson com or contact your Seiko Epson sales representative 1 1 Program Requirements Video Controller S1D13704 Display Type LCD Windows Version CE Version 2 0 2 1 1 2 Example Driver Build Build For CEPC X86 Version 2 0 2 1 To build a Windows CE v2 0 2 1 display driver for the CEPC X86 platform using a S5U13704B00C evaluation board follow the instructions below 1 Install Microsoft Windows NT v4 0 2 Install Microsoft Visual C C
310. rface performs frame rate modulation for passive LCD panels It also generates the correct data format and timing control signals for various LCD and TFT D TFD panels 4 1 6 Power Save Power Save contains the power save mode circuitry 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 5 Pins 5 1 Pinout Diagram Page 17 6d 59 58 57 59 59 54 53 52 51 50 49 49 a7 49 45 44 49 42 41 lt Z DDDOD gt DDOOS ro O lt S OOOD OO S LOGO QRamannngnergezzzzznoaza0 x 0 61 O 40 COREVDD vss Ea 2 ABs FPFRAME 683 7 FPLINE 28 e FPDATO 5 aps FPDAT1 has 86 apy FPDAT2 gt A AB3 FPDAT3 2 aB2 FPDAT4 69 32 Fo AB1 FPDAT5 ETE ABO FPDAT6 Fan 7 71 30 71 BOLK S1D13704 FPDAT 7a PVDD og 74 RESET FPSHIFT 5 cst vss HS ast FPDAT8 8 aoe FPDAT9 2 7 WEO FPDATIo A wet FPDATI1 23_ 2 epwre GPIoo 22 80 21 VSS og COREVDD Og mg e lt PROURRIRROUZDUUUUUUUOS 073222234 20YU17000000000 Oo 0OND4A0DDNDND 0000J3O0O0_RA0Vv 0O0 E E la E e 7 E E hofia 12 1 14 15 16 17 14 19 20 Figure 5 1 Pinout Diagram Note Package type 80 pin surface mount QFP14 Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 18 Epson Research and Development Vancouver Design Center 5 2 Pin Description Key CS COx TSx TSxD
311. rforming rotations on the fly Most programs written for the HAL will ignore this setting and set Portrait or Landscape display modes as desired This setting is useful when the configuration is saved into a C header file to be used by non HAL programs System The options in the System section describe the items which are required for frame rate calculations and where in CPU address space the 1D13704 will be located Salen Memory Location Frame Fise hc rapid Clock Hz Figure 4 System Options e Memory Location this describes where in CPU address space the S1D13704 will be located This setting is required by the HAL to locate the S1D13704 If the settings from 13704CFG will be saved to a C header file for use in a non HAL program this value does not have to be filled in e Frame Rate indicate the desired frame rate here 13704CFG will attempt to write register settings which result in the requested frame rate If the frame rate cannot be reached then the following dialog inform the user of the problem ET N ERROR Unable to sel the dened hamna rate ong chock wha 7 Figure 5 ERROR Frame Rate 13704CFG EXE Configuration Program 1D13704 Issue Date 01 02 08 X26A B 001 02 Page 12 Epson Research and Development Vancouver Design Center A Frame rate must be entered in order for 13704CFG to complete the frame rate calcula tions If no frame rate is entered or the frame rate is set to 0 then the following dialog
312. ring reset by sampling the state of the configu ration pins CNF 2 0 and the BS line Table 5 1 in the S1D13704 or S1D13705 Hardware Functional Specification details the values needed for the configuration pins and BS to select the desired mode 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 9 Vancouver Design Center 2 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13704 5 The Generic 2 interface mode was chosen for this interface due to its compatibility with the PC Card interface The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13704 5 BUSCLK is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper memory address space WE1F is the high byte enable for both r
313. riod REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 40 Epson Research and Development Vancouver Design Center Sync Timing e Frame Pulse gt t4 13 Line Pulse t5 MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 gt 1 1 Shift Pulse t12 t13 FPDAT 7 0 x Note For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 13 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pulse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDATT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDAT 7 0 hold to Shift Pulse falling
314. rite cycle TBCLK t4 WE high to D 15 0 invalid write cycle 0 ns t5 RD low to D 15 0 driven read cycle 16 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RD high to D 15 0 high impedance read cycle 10 ns t8 WE RD low to WAIT driven low 14 ns t9 BCLK to WAIT high 16 ns t10 WE RD high to WAIT high impedance 11 ns Note BCLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 34 Epson Research and Development Vancouver Design Center 7 2 Clock Input Requirements Clock Input Waveform PWH anh we gt 90 Vin VIL 10 tp A gt o ty F TeLKI gt Figure 7 7 Clock Input Requirements Table 7 7 Clock Input Requirements Symbol Parameter Min Max Units foLKi Input Clock Frequency CLKI 0 50 MHz Tork Input Clock period CLKI Toki town Input Clock Pulse Width High CLKI 8 ns tow Input Clock Pulse Width Low CLKI 8 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns Note When CLKI is gt 25MHz it must be divided by 2 REG 02h bit 4 1 S1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Vancouver Design Center 7 3 Display Interface 7 3 1 Power On Reset Timing Pag
315. rollers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13704 X26A G 010 03 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 EPSON 1D13704 Embedded Memory Color LCD Controller Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X26A G 011 03 Copyright 1998 2001 Epson Research and Development Inc All Rights Reserved Informatio
316. rom the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13704 Supported Evaluation Platforms Installation 13704PWR Power Save Utility Issue Date 01 02 08 13704PWR has been designed to work with the following S1D13704 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx PC platform copy the file 13704PWR EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13704PWR to the system S1D13704 X26A B 007 02 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at the prompt type 13704pwr s0 s1 h0 h1 Embedded platform execute 13704pwr and at the prompt type
317. s Generic 1 Big Endian CNF 2 0 EA configuration for Philips PR31500 PR31700 host bus interface When the S1D13704 is configured for Generic 2 interface the host interface pins are mapped as in the table below Table 2 2 SID13704 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR Connect to lO Vpp RD RD WEO0 WE Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 1D13704 X26A G 012 02 Page 10 EPSON Research and Development Vancouver Design Center 3 System Design Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the S1D13704 can be interfaced so that it shares a PC Card slot The S1D13704 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the S1D13704 virtually transparent to PC Card devices that use the same slot 3 1 Hardware Description The ITE8368E has been specially designed to support EPSON LCD controllers The ITE IT8368E provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the S1D13704 CPU interface The PR31500 PR31700 processor only provides addresses A 12 0 therefore devices requiring more address space must use an external device to lat
318. s every FPFRAME For a non zero value the value in this register 1 specifies the number of FPLINEs between toggles of the MOD output signal These bits are for passive LCD panels only REG 0Ch Screen 1 Start Address Register LSB Address FFECh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0Dh Screen 1 Start Address Register MSB Address FFEDh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG ODh bit 6 0 REG OCh bit 7 0 REG ODh bit 7 Screen 1 Start Address Bits 14 0 These bits determine the word address of the start of Screen 1 in landscape modes or the byte address of the start of Screen 1 in SwivelView modes Hardware Functional Specification Issue Date 01 02 08 Screen 1 Start Address Bit 15 This bit is for Swivel View mode only and has no effect in Landscape mode S1D13704 X26A A 001 04 Page 62 Epson Research and Development Vancouver Design Center REG OFh Sc
319. s used to configure the S1D13704 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to the NEC VR4102 Microprocessor Issue Date 01 02 12 Epson Research and Development Page 13 Vancouver Design Center 4 VR4102 to S1D13704 Interface 4 1 Hardware Description The NEC Vr4102 Microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 interface only one inverter is required to change the polarity of the system reset signal to active low A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram shows a typical implementation of the VR4102 to 1D13704 interface NEC VR4102 S1D13704 WR WEO SHB WE1 RD gt RD LCDCS Pulbup CS t LCDRDY WAIT RSTOUT gt gt RESET ADD 15 0 AB 15 0 DATA 15 0 DB 15 0 BUSCLK gt BUSCLK Vcc T BS Vcc t RD WR Figure 4 1 Typical Implementation of VR4102 to S1D13704 Interface Interfacing to the NEC VR4102 Microprocessor S1D13704 Issue Date 01 02 12 X26A G 008 05 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13704 Hardware Configuration The S1D13704 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configur
320. se Video Mode Select Options below Note Video data is inverted after the Look Up Table Table 8 4 Inverse Video Mode Select Options Software Video FPDAT11 Hardware Video Invert A 3 Passive Panels Video Data Invert Enable Passive and Only Active Panels y 0 0 X Normal 0 1 X Inverse 1 x 0 Normal 1 x 1 Inverse Hardware Functional Specification 1D13704 Issue Date 01 02 08 X26A A 001 04 Page 58 Epson Research and Development Vancouver Design Center REG 03h Mode Register 2 Address FFE3h Read Write Hardware Software Software pida n a n a n a o Power Save Power Save Power Save yp Enable Bit 1 Bit 0 bit 7 bit 3 bit 2 bits 1 0 1D13704 X26A A 001 04 Look Up Table Bypass When the Look Up Table Bypass bit 0 the Green Look Up Table is used for display data output in gray shade modes When this bit 1 the Look Up Table is bypassed for dis play data output in gray shade modes for power save purposes See Look Up Table Architecture on pag e72 There is no effect on changing this bit in color modes In color display mode the Look Up Table cannot be bypassed LCDPWR Override This bit is used to override the panel on off sequencing logic When this bit 0 LCDPWR and the panel interface signals are controlled by the sequencing logic When this bit 1 LCDPWR is forced to off and the panel interface signals are forced low i
321. shut down This section details the sequences to manually power up and power down the LCD interface During the power up sequence the LCD power should not be applied before the LCD logic signals Usually the power and logic can begin at the same time There may be times when the LCD logic signals must begin before LCD power is applied REG 03h Mode Register 2 LCDPWR Hardware Software Software Override Power Save Power Save Power Save Enable bit 1 bit O 1D13704 The LCD Power LCDPWR Override bit forces LCD power to inactive one frame after being toggled The LCD logic signals to the panel are still active and are controlled by enabling or disabling a power save mode After enabling a power save mode there are still 128 frames before LCD logic signals are disabled The Hardware Power Save Enable bit must be set in order for a hardware power save request on GPIOO to have any affect Without enabling this bit toggling GPIOO will have no power save effect The Software Power Save bits are used to set the software power save mode The two valid states are 00 for power save and 11 for normal operation Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Page 35 Vancouver Design Center 6 3 LCD Enable Disable The descriptions below cover manually powering the LCD panel up and down Use them only if the power supply connected to the panel requ
322. son Research and Development Vancouver Design Center 4 Look Up Table LUT This section is supplemental to the description of the Look Up Table LUT architecture found in the S1D13704 Hardware Functional Specification Covered here is a review of the LUT registers recommendations for the color and monochrome LUT values and additional programming considerations for the LUT The S1D13704 Look Up Table consists of sixteen 4 bit wide entries for each of red green and blue The Look Up Table is controlled by three registers REG 15h forms the index into the table REG 16h determines which bank is active during display REG 17h is the register where the Look Up Table data is read and written The currently configured color depth affects how many indices will be used for image display In color modes pixel values are used as indices to an RGB value stored in the Look Up Table In monochrome modes only the green component of the LUT is used 4 1 Look Up Table Registers REG 15h Look Up Table Address Register Read Write n a n a RGB Index RGB Index LUT Address LUT Address LUT Address LUT Address bit 1 bit O Bit 3 Bit 2 Bit 1 Bit O 1D13704 X26A G 002 03 RGB Index The RGB Index bits determine how the 1D13704 will handle automatic LUT Address updates When the RGB Index is set to auto increment 00 then three consecutive accesses of REG 17h will read write the red green and then t
323. ss and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 16 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles 1D13704 X26A G 009 03 A data transfer is initiated when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 01 02 12 Epson Research and Development Page 9 Vancouver Design Center Durin
324. stride in bytes between two consecutive lines of display in Swivel View mode The Line Byte Count register only affects Swivel View mode operation The contents of this register are ignored when the S1D13704 is in landscape display mode SwivelView Mode Enable REG 1Bh SwivelView Mode Register SwivelView SwivelView SwivelView ala nja ia resend Mode Pixel Mode Pixel Mode Select Clock Select Clock Select Bit 1 Bit 0 Programming Notes and Examples Issue Date 01 02 12 The SwivelView mode register contains several items for Swivel View mode support The first is the Swivel View Mode Enable bit When this bit is 0 the S1D13704 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG 1Ch are ignored When this bit is a 1 Swivel View mode is enabled There are two SwivelView mode display schemes available The Swivel View mode select bit selects between the Default Mode and the Alternate Mode The default mode offers the lowest power consumption with some display mode limitations The alternate mode uses more power but offers greater display flexibility 1D13704 X26A G 002 03 Page 40 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center In return for using less power the default Swivel View imposes the restriction that the SwivelView display width must be a power of two e g 64 128 256 512
325. t Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the S1D13704 with other CPUs For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Interface Mode 1D13704 X26A G 007 03 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13704 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13704 host interface It is sepa rate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select
326. t DevID DWORD Offset BYTE Value DWORD Count Description This routine writes one or more bytes to display buffer at the offset specified by Addr If a count greater than one is specified all bytes will have the same value Parameters DevID registered device ID Offset offset from start of the display buffer to start writing at Value BYTE value to write Count number of bytes to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or the value of Addr plus Count is greater than 40 kb Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 57 int seWriteDisplayWords int DevID DWORD Offset WORD Value DWORD Count Description Parameters Return Value Writes one or more WORDS to the display buffer at the offset specified by Addr If a count greater than one is specified all WORDS will have the same value DevID registered device ID Offset offset from start of the display buffer Value WORD value to write Count number of words to write ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 40 kb int seWriteDisplayDwords int DevID DWORD Offset DWORD Value DWORD Count Description Parameters Return Value Programming Notes and Examples Issue Date 01 02 12 Writes one or more DWORDS to the display buffer at
327. t be reached return an error In C the code looks like the following snip for int loop 0 loop lt 2 loop VNDP 2 VNDP lt 0x3F VNDP 3 Solve for HNDP HNDP PCLK FrameRate VDP VNDP HDP if HNDP gt 32 amp amp HNDP lt 280 Solve for VNDP VNDP PCLK FrameRate HDP HNDP VDP If we have satisfied VNDP then we re don if VNDP gt 0 amp amp VNDP lt 0x3F goto DoneCalc Divide C1k1 and try again Reg 02 allows us to dived CLKI by 2 PCLK 2 If we still can t hit the frame rat throw an error if VNDP lt 0 VNDP gt 0x3F HNDP lt 32 HNDP gt 280 sprintf ERROR Unable to set the desired frame rate n exit 1 1D13704 Programming Notes and Examples X26A G 002 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 11 3 Memory Models The S1D13704 is capable of operating at four different color depths The data format for each color depth is packed pixel S1D13704 packed pixel modes can range from one byte containing eight adjacent pixels 1 bpp to one byte containing just one pixel 8 bpp Packed pixel data memory may be envisioned as a stream of data Pixels fill this stream with one pixel packed in adjacent to the next If a pixel requires four bits then it will be located in the four most significant bits of a byte The pixel to the immediate right on the displ
328. t16 DB 15 0 valid to RDY falling edge setup time read cycle 0 ns t17 Rising edge RD to DB 15 0 high impedance read cycle 10 ns Note Page 27 CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification Issue Date 01 02 08 1D13704 X26A A 001 04 Page 28 7 1 2 SH 3 Interface Timing Epson Research and Development Vancouver Design Center Teko t2 t3 4 pit CKIO t4 t5 e A 16 0 M R RD WR A t6 t7 BS l i t8 o CSn t9 t10 WEn al RD t11 t12 gt t gt gt WAIT Hi Z Hi Z t13 R 114 D 15 0 Hi Z Hi Z write 15 t16 D 15 0 Hi Z Hi Z read VALID Figure 7 2 SH 3 Bus Timing Note The SH 3 Wait State Control Register for the area in which the S1D13704 resides must be set to a non zero value 1D13704 X26A A 001 04 Hardware Functional Specification Issue Date 01 02 08 Epson Research and Development Vancouver Design Center Table 7 2 SH 3 Bus Timing Symbol Parameter Min Max Units fckio Bus Clock frequency 0 50 MHz Tekio Bus Clock period 1 fckio t2 Clock pulse width high 17 ns t3 Clock pulse width low 16 ns t4 A 15 0 RD WR setup to CKIO 0 ns t5 A 15 0 RD WR hold from CS 0
329. t6min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 3 t8min REG O6h bits 1 0 REG O5h bits 7 0 1 REG OAh bits 6 0 Lines 4 t10min REG 04h bits 6 0 1 x 8 Ts 5 ti4min REG 04h bits 6 0 1 x 8 Ts 6 ti5min REG O7h bits 4 0 x 8 16 Ts 7 17min REG O8h bits 4 0 REG 07 x 8 16 Ts Hardware Functional Specification S1D13704 Issue Date 01 02 08 X26A A 001 04 Page 54 Epson Research and Development Vancouver Design Center 8 Registers 8 1 Register Mapping The S1D13704 registers are located in the upper 32 bytes of the 64K byte S1D13704 address range The registers are accessible when CS 0 and AB 15 0 are in the range FFEOh through FFFFh 8 2 Register Descriptions Unless specified otherwise all register bits are reset to O during power up REG 00h Revision Code Register Address FFEOh Read Only Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Code Bit 1 Code Bit 0 bits 7 2 Product Code This is a read only register that indicates the product code of the chip The product code is 000110 bits 1 0 Revision Code This is a read only register that indicates the revision code of the chip The revision code is 00 REG 01h Mode Register 0 Address FFE1h Read Write f FPLine FPFrame Mask Data
330. ta DA a O AA A tt Oe A AE a 26 5 2 Panning and Scrolling 2 2 a 27 A A See ee GR ee Me Pe Se ee 28 5 2 2 Examples J if a o ee a es oe RA eh ee at ae Gal ata 28 5 3 SphtScreeny e arte lies eh ste oy Be Sw a A oy Se Oe ar 130 O Registers aan 25 es a A BR Oe A Be o SI ee 31 O32 Examples ta a at bet WOT a do eae weeds rs E A yt a 32 6 LCD Power Sequencing and Power Save ModeS 34 6 1 LCD Power Sequencing 2 2 34 6 2 Registers A a ia ca A ae E o rd 6 3 LCD Enable Disable 0 0 2 0 2 2 ee ee 39 de SMIVEIVIGWER os chen oe AAA AE AA A 36 7 1 Introduction To SwivelView d ee ee ee ee 36 7 2 Default SwivelView Mode 2 2 2 2 2 2 36 7 3 Alternate SwivelView Mod gt araos a sok ee ee 37 PA CRegisters qai moeck A ee we ORM a ee 89 R LAMItAUONS o gt ge eee hoe Siok toy Ss ee de ee ee ae Coe ee ie ee bh eee A T6 VB Kamples ae e oe EAS e Ps A ihe Eo AD Identifying the S1D13704 sasaaa et 46 9 Hardware Abstraction Layer HAL o ee es 47 Ol Introduction Js o o Zt es ee A de ek he BS Se a Re a oe Sa lt a Programming Notes and Examples 1D13704 Issue Date 01 02 12 X26A G 002 03 Page 4 Epson Research and Development Vancouver Design Center 9 2 API tor TI TOHA 0 amp 2 ach ap ee ee A a ee ee Ge ae a EE ce ee Ae A AT 9 21 Imitialization i2 e a parce Brae ged BOE Yee OS Eee Ee a
331. te e The Line Byte Count Register for Swivel View Mode must be set to the virtual image width in bytes i e 256 256 L 128 80h REG 1Ch 8bpb 4bpp 2 Where bpb is bits per byte and bpp is bits per pixel e Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g two pixels in 4 bpp mode e Increment the register by twice the value in the Line Byte Count register to pan verti cally by two lines e g add 100h to pan by two lines in the example above Note Vertical panning by a single line is not supported in Default Swivel View Mode 1D13704 Hardware Functional Specification X26A A 001 04 Issue Date 01 02 08 Epson Research and Development Page 81 Vancouver Design Center 12 2 Alternate SwivelView Mode Alternate Swivel View Mode may be used when the virtual image size of Default SwivelView Mode cannot be contained in the 40kByte integrated frame buffer For example the panel size is 240x160 and the display mode is 8 bit per pixel The minimum virtual image size for Default Swivel View Mode would be 240x256 which requires 60K bytes Alternate Swivel View Mode requires a panel size of only 240x160 which needs only 38 400 bytes Alternate Swivel View Mode requires the memory clock MCLK to be at least twice the frequency of the pixel clock PCLK i e MCLK gt 2 x PCLK Because of this the power consumption in Alternate Swivel V
332. tends from address 0 through 3F FFFFh so the S1D13704 is addressed starting at 40 0000h The S1D13704 uses a 64K byte segment of memory starting at this address with the first 40K bytes used for the display buffer and the upper 32 bytes of this memory block used for the S1D 13704 internal registers Chip select 4 is used to control the S1D13704 The following options are selected in the base address register BR4 BA 0 16 0000 0000 0100 0000 0 set starting address of S1D13704 to 40 0000h AT 0 2 0 ignore address type bits PS 0 1 1 0 memory port size is 16 bits PARE 0 disable parity checking WP 0 disable write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits 1D13704 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by clock cycle from address lines BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the S1D13704 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Mot
333. tern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the S1D13504 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM 1D13704 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 03 Issue Date 01 02 12 Epson Research and Development Vancouver Design Center 3 S1D13704 Host Bus Interface Page 13 This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic 1 host bus interface used to implement the interface to the MPC821 bus 3 1 Host Bus Interface Modes The S1D13704 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six host bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Read Write Enable for low byte Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Rea
334. tes for internal registers Therefore the S1D13704 will be shadowed over the entire 16M byte memory range at 64K byte segments The starting address of the display buffer is 0A000000h and register O of the S1D13704 REG 00h resides at OAOOFFEOh The NEC Vr4102 has a 16 bit internal register named BCUCNTREG2 located at address 0B000002h It must be set to the value of 0001h to indicate that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at address OB000000h must have bit D 13 USA LCD bit set to O to reserve the 16M bytes space 0AQ00000h to OAFFFFFFh for LCD use and not as ISA bus memory space Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CKG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13704 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com 1D13704 Interfac
335. the dimensions Virtual dimensions are not taken into account for this calculation When the display is in SwivelView mode the dimensions will be swapped i e a 640x480 display in Swivel View mode will return a width and height of 480 and height of 640 Parameters DevID registered device ID Width pointer to an integer to receive the display width Height pointer to an integer to receive the display height Return value ERR_OK the operation completed successfully int seDelay int MilliSeconds Description Parameters Return Value This function will delay for the length of time specified in MilliSeconds before returning to the caller This function was originally intended for non PC platforms Information about how to access the timers was not always available however we do know frame rate and can use that for timing calculations The S1D13704 registers must be initialized for this function to work correctly On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings DevID registered device ID MilliSeconds time to delay in seconds ERR_OK operation completed with no problems ERR_FAILED returned on non PC platforms when the S1D13704 registers have not bee initialized int seGetLastUsableByte int DevID long plLastByte Description Parameters Programming Notes and Examples Issue Date 01 02 12 This functions returns a pointer as a
336. the S1D13704 interface is a straightforward implementation of the MC68K 1 host bus interface For further information on this host bus interface refer to the 1D13704 Hardware Functional Specification document number X26A A 001 xx The following diagram shows a typical implementation of the MC68328 to S1D13704 using the MC68K 1 host bus interface MC68328 1D13704 A 15 0 AB 15 1 D 15 0 DB 15 0 CSB3 CS Vcc 470 DTACK WAIT AS BS UDS WE1 LDS ABO R W RD WR Vee RD CLKO BUSCLK RESET RESET cuales a hey Figure 4 1 Typical Implementation of MC68328 to SID13704 Interface MC68K 1 1D13704 X26A G 007 03 Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 01 02 12 Epson Research and Development Page 13 Vancouver Design Center 4 1 2 Using The Generic 1 Host Bus Interface If UDS and or LDS are required for their alternate IO functions then the MC68328 to S1D13704 interface may be implemented using the S1D13704 Generic 1 host bus interface Note that in either case the DTACK signal must be made available for the S1D13704 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode WAIT must be inverted using an inverter enabled by CS to make it an active high signal and thus compatible with the MC68328 architecture A single resistor is used to s
337. the command line argument Where s0 resets software power save mode sl sets software power save mode hO resets disables hardware power save mode REG 03h bit 2 h1 sets enables hardware power save mode REG 03h bit 2 displays this usage message Program Messages S1D13704 X26A B 007 02 ERROR Unknown command line argument An invalid command line argument was entered Enter a valid command line argument ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 13704 device A 13704 device was not found at the configured addresses Check the configuration address using the 13704CFG configuration program ERROR Did not detect 13704 The HAL was unable to read the revision code register on the S1D13704 Ensure that the S1D13704 hardware is installed and that the hardware platform has been set up correctly 13704PWR Power Save Utility Issue Date 01 02 08 EPSON 1D13704 Embedded Memory Color LCD Controller Windows CE Display Drivers Document Number X26A E 001 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any
338. the offset specified by Addr If a count greater than one is specified all DWORDSs will have the same value DevID registered device ID Offset offset from start of the display buffer Value DWORD value to write Count number of dwords to write ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 40 kb 1D13704 X26A G 002 03 Page 58 9 2 5 Power Save 9 2 6 Drawing 1D13704 X26A G 002 03 Epson Research and Development Vancouver Design Center This section covers the HAL functions dealing with the Power Save features of the 1D13704 int seSetPowerSaveMode int DevID int PwrSaveMode Description This function sets on the S1D13704 s software selectable power save modes Parameters DevID aregistered device ID PwrSaveMode integer value specifying the desired power save mode Acceptable values for PwrSaveMode are 0 software power save mode in this mode registers and memory are read writable LCD output is forced low 3 normal operation all outputs function normally Return Value ERR_OK _ operation completed with no problems The Drawing routines cover HAL functions that deal with displaying pixels lines and shapes int seDrawLine int DevID int x1 int y1 int x2 int y2 DWORD Color Description This routine draws a line on the display from the endpoints defined by x1 y1 to the endpoint x2 y2 in the requested Color
339. the scope of this document to provide support for target host configurations 1D13704 Supported Evaluation Platforms Installation 13704VIRT Display Utility Issue Date 01 02 08 13704VIRT has been tested with the following S1D13704 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13704 Programming Notes and Examples manual document number X26A G 002 xx PC platform copy the file 13704 VIRT EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 13704VIRT to the system S1D13704 X26A B 004 02 Page 4 Usage 1D13704 X26A B 004 02 Epson Research and Development Vancouver Design Center PC platform at the prompt type 13704virt a w Embedded platform execute 13704virt and at the prompt type the command line argument Where no argument a W panning and scrolling is performed manually defaults to virtual width physical width x 2 and maximum virtual height panning and scrolling is performed automatically specifies the virtual display width which includes bot
340. the specified input clock 2 the combination of width height and color depth may require more memory than is available on the S1D13704 int seGetBitsPerPixel int DeviD int pBitsPerPixel Description Parameters Return Value This function reads the S1D13704 registers to determine the current color depth and returns the result in pBitsPerPixel DevID registered device ID pBitsPerPixel pointer to an integer to receive current color depth return values will be 1 2 4 or 8 ERR_OK operation completed with no problems int seGetBytesPerScanline int DevID int pBytes Description Parameters Return Value Returns the number of bytes use by each scan line in the integer pointed to by pBytes The number of bytes per scanline will include the number of non displayed bytes if applicable Prior to calling seGetBytesPerScanline the S1D13704 control registers must have been correctly initialized DevID registered device ID pBytes pointer to an integer to receive the number of bytes per scan line ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 51 int seGetScreenSize int DevID int Width int Height Description Retrieves the width and height in pixels of the display surface The width and height are derived by reading the horizontal and vertical size registers and calculating
341. ties and Windows CE v2 0 display drivers are available from your sales support contact or www erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 EPSON Research and Development Vancouver Design Center 5 Technical Support 5 1 EPSON LCD Controllers S1D13704 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 5 2 Philips MIPS PR31500 PR31700 Processor Philips Semiconductors Handheld Computing Group 4811 E Arques Avenue M S 42 P O Box 3409 Sunnyvale CA 94088 3409 Tel 408 991 2313 http www philips com 5 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 Page 15 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287
342. tion of the system PC Card attribute and IO space is allocated to address the S1D13704 When accessing the S1D13704 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 3 1 S1D13704 to TX3912 Connection Using an IT8368E on page 10 For further information on the IT8368E refer to the T8368E PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode Interfacing to the Toshiba MIPS TX3912 Processor 1D13704 Issue Date 01 02 12 X26A G 004 02 Page 12 EPSON Research and Development Vancouver Design Center 3 3 Memory Mapping and Aliasing When the TX3912 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 3 1 TX3912 to Unbuffered PC Card Slots System Address Mapping Note Bits CARDIIOEN and CARD2IOEN need to be set in TX3912 Memory Configuration Register 3 Table 3 1 TX3912 to Unbuffered PC Card Slots System Address Mapping Function Function TX9912 Address aize CARDnIOEN 0 CARDnIOEN 1 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 10 6400 0000h 64M byte Card 1 Memory 6400 0000h 64M byte Card 2 Memory When the TX3912 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CA
343. tion register clear rl point rl to start of S 1D13704 read revision code into rl branch forever Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 12 Epson Research and Development Page 21 Vancouver Design Center This code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board It was executed on the ADS and a logic analyzer was used to verify operation of the interface hardware Note MPC8BUG does not support comments or symbolic equates these have been added for clarity It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the S1D13704 memory block is tagged as non cacheable to ensure that accesses to the S1D13704 will occur in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13704 or its display buffer Interfacing to the Motorola MPC821 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 010 03 Page 22 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13704 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13704CKG or by directly modifying
344. tions for the implementation presented in this document are as follows PAL device 1618 OE PI 1 WE PI 2 CE1 PIN 3 CE2 PIN 4 REG PIN 5 PCRESET PIN 6 RESET PIN 14 WEO PIN 15 WE1 PIN 16 RD PI 17 RDWR PI 18 ES PIN 19 equations IWEO WE amp CEl REG IWE1 WE amp CE2 REG ICS REG amp RD RDWR WEO WE1 IRD OE CEl REG IRDWR OE amp CE2 amp REG RESET PCRESET 4 4 Register Memory Mapping The S1D13704 is a memory mapped device The S1D13704 memory may be addressed starting at 0000h or on consecutive 64K byte blocks and its internal registers are located in the upper 32 bytes of the 64K byte block i e REG 0 FFEOh While the PC Card socket provides 64M bytes of address space the S1D13704 only needs a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte register set For this reason only address bits A 15 0 are used while A 25 16 are ignored Because the entire 64M bytes of memory is available the S1D13704 s memory and registers will be aliased every 64K bytes for a total of 1024 times Note Tf aliasing is not desirable the upper addresses must be fully decoded S1D13704 Interfacing to the PC Card Bus X26A G 009 03 Issue Date 01 02 12 Epson Research and Development Page 15 Vancouver Design Center
345. to 28h to satisfy the above condition Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 27 Vancouver Design Center Example 2 From the above what is the maximum number of lines our image can contain Step 1 Calculate the number of bytes on each line bytes_per_line pixels_per_line pixels_per_byte 640 4 160 Each line of the display requires 160 bytes Step 2 Calculate the number of lines the S1D13704 is capable of total_lines memory bytes_per_line 40960 160 256 The the maximum number of lines which can be accommodated by our image can contain is 256 This example will not fit in available display memory We must reduce either the color depth or the virtual image size 5 2 Panning and Scrolling Panning and scrolling describe the actions of appearing to move the image in a virtual display so that all the image can be viewed After correctly setting up a virtual display see above and loading an image into display memory panning and scrolling allow viewing the entire image a portion at a time Panning describes the horizontal side to side motion of the viewport When panning to the right the image in the viewport appears to slide to the left When panning to the left the image to appears to slide to the right Scrolling describes the vertical up and down motion of the viewport Scrolling down causes the image to appear to slide up and scrolling up causes the image
346. to the LUT index when data is specified otherwise the LUT index is read Data must consist of 3 bytes 1 red 1 green 1 blue and range in value from 0x00 to OxOF Reads all LUT values Fills bytes or words from address 1 to address 2 with data Data can be multiple values e g F 0 20 1 2 3 4 fills address O to 0x20 with a repeating pattern of 1 2 3 4 Reads count of bytes or words from the address specified by addr If count is not specified then 16 bytes words are read Writes bytes or words of data to address specified by addr Data can be multiple values eg W 0 1 2 3 4 writes the byte values 1 23 4 starting at address 0 Initializes the chip with user specified configuration 13704PLAY Diagnostic Utility Issue Date 01 02 08 Epson Research and Development Page 5 Vancouver Design Center M bpp Returns information about the current mode If bpp is specified then set the requested color depth P 0 1 12 Sets software power save mode 0 2 Power save mode 0 is normal operation H lines Halts after specified lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Set 0 to disable Q Quits this utility Displays Help information 13704PLAY Example 1 Type 13704PLAY to start the program 2 Type for help 3 Type i to initialize the registers 4 Type xa to display the contents of the
347. ue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 9 2 1 2 LCD Memory Access Cycles Figure 2 1 NEC VR4102 Read Write Cycles on page 9 shows the read and write cycles to the LCD Controller Interface Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read or write enable signals RD and WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable is driven low for 16 bit transfers and high for 8 bit transfers TCLK ADD 25 0 SHB LCDCS WR RD D 15 0 write D 15 0 read E A AA A MA Ly VALID VALID Hi Z i gt VALID E LCDRDY Figure 2 1 NEC VR4102 Read Write Cycles Interfacing to the NEC VR4102 Microprocessor 1D13704 Issue Date 01 02 12 X26A G 008 05 Page 10 3 S1D13704 Host Bus Interface Epson Research and Development Vancouver Design Center This section is a summary of the host bus interface modes available on the S1D13704 and offers some detail on the Generic 2 host bus interface used to implement the interface to the VR4102 3 1 Bus Interface Modes The S1D13704 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor fa
348. ultiple functions e For SH 3 SH 4 mode this pin inputs the read signal RD e For MC68K 1 this pin must be tied to IO Vpp e For MC68K 2 this pin inputs the bus size bit 1 SIZ1 For Generic 1 this pin inputs the read command for the lower data byte RDO For Generic 2 this pin inputs the read command RD See Host Bus Interface Pin Mapping for summary WAIT TS2 High Impedance This pin has multiple functions For SH 3 mode this pin outputs the wait request signal WAIT For SH 4 mode this pin outputs the device ready signal RDY For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK e For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 e For Generic 1 this pin outputs the wait signal WAIT For Generic 2 this pin outputs the wait signal WAIT See Host Bus Interface Pin Mapping for summary RESET 73 CS Active low input to set all internal registers to the default state and to force all signals to their inactive states 5 2 2 LCD Interface Pin Name Type Pin Cell RESET State Description FPDAT 7 0 O 30 31 32 33 34 35 36 37 CN3 Panel Data FPDAT 10 8 O 1 0 24 25 26 CN3 Input These pins have multiple functions Panel Data bits 10 8 for TFT D TFD panels e General Purpose Input Output pins GP
349. um S1D13704 clock frequencies The S1D13704 also has internal clock dividers providing additional flexibility Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 12 EPSON Research and Development Vancouver Design Center 2 2 Memory Mapping and Aliasing Page 9 The S1D13704 requires an addressing space of 64K bytes The on chip display memory occupies the range 0 through 9FFFh The registers occupy the range FFEOh through FFFFh The PR31500 PR31700 demultiplexed address lines A16 and above are ignored thus the 1D13704 is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space In this example implementation the PR31500 PR31700 control signal CARDREG is ignored the S1D13704 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 2 3 S1D13704 Configuration and Pin Mapping The S1D13704 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the D13704 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to the direct connection approach Table 2 1 S1D13704 Configuration for Direct Connection S1D13704 Value hard wired on this pin is used to configure Configuration Pin 1 IO Vpp 0 Vs
350. ure 7 LUT Conmtrol o e Figure 8 13704CFG File Open Dialog o oo Figure 9 ERROR Unable to read HAL o o Figure 10 13704CFG Save As Dialog e Figure 11 ERROR Unable to read HAL o o o 13704CFG EXE Configuration Program Issue Date 01 02 08 Page 3 1D13704 X26A B 001 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13704 13704CFG EXE Configuration Program X26A B 001 02 Issue Date 01 02 08 Epson Research and Development Page 5 Vancouver Design Center Introduction 13704CFG is a Win 32 program which gives developers an easy means to modify panel types clock rates color depths etc for S1D13704 demonstration programs 13704CFG can e Read programs based on the 13704 Hardware Abstraction Layer HAL modify the settings and write the changes back to the file The ability to read modify and write bypasses having to recompile after every change e Write C header files containing register settings which can be used to initialize the 13704 registers in programs which do not use the HAL 13704CFG EXE Configuration Program 1D13704 Issue Date 01 02 08 X26A B 001 02 Page 6 Epson Research and Development Vancouver Design Center Program Requirements Installation Usage S1D13704 X26A B 001 02 This program is designed to run under Windows 95 98 or Windows NT 4
351. us interface offers more flexibility in configuring the S1D13704 with other CPUs For details on configuration refer to the S1D13704 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Host Bus Interface Mode S1D13704 X26A G 010 03 Generic 1 host bus interface mode is the most general and least processor specific host bus interface mode on the S1D13704 The Generic 1 host bus interface mode was chosen for this interface due to the simplicity of its timing The host bus interface requires the following signals BUSCLK is a clock input which is required by the S1D13704 host interface It is sepa rate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13704 These signals must be gene
352. vID int Rotate Description Parameters Return Value 1D13704 X26A G 002 03 This function sets the rotation scheme according to the value of Rotate When Swivel View mode is selected as the display rotation the scheme selected is the non X2 scheme DevID registered device ID Rotate the direction to rotate the display Valid arguments for Rotate are LANDSCAPE and PORTRAIT ERR_OK operation completed with no problems ERR_FAILED the operation failed to complete The most likely reason for failing to set a Swivel View mode is an inability to set the desired frame rate when setting the mode Other factors which can cause a failure include having configured for a 0 Hz frame rate or specifying something other than LANDSCAPE or PORTRAIT for the rotation scheme Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 53 int seSplitInit int DevID WORD Scrn1Addr WORD Scrn2Addr Description Parameters Return Value Note This function prepares the system for split screen operation In order for split screen to function the starting address in display buffer for the upper portion screen 1 and the lower portion screen 2 must be specified Screen 1 is always displayed above screen 2 on the display regardless of the location of their start addresses DevID registered device ID SernlAddr offset in bytes to the start of screen 1 Sern2Addr
353. ven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the 1D13704 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13704 When accessing the S1D13704 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 3 1 S1D13704 to PR31500 PR31700 Connection Using an IT8368E on page 10 For further information on the IT8368E refer to the JTS36SE PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13704 Issue Date 01 02 12 X26A G 012 02 Page 12 3 3 Memory Mapping and Aliasing EPSON Research and Development Vancouver Design Center When the PR31500 PR31700 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 3 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping Note Bits CARDIIOEN and CARD2IOEN need to be set in PR31500 PR31700 Memory Configuration Register 3 Table 3 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping Phiips Address size CARDAOENEO ean sore
354. vert this signal if it is active high so that LCDON will be the right polarity to turn on the LCD power supply Jumper JP10 must be set to position 1 2 if LCDPWR is active low and to position 2 3 if LCDPWR is active high 4 3 3 S1D13704175 Chip Select Minimal glue logic is used on the CPU module to provide the chip select signal CS for the LCDC A simple AND gate activates the S1D13704 5 whenever the PC Card slot 1 is accessed whether it be memory space or attribute space S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 14 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON S1D13704 Embedded Memory Color LCD Controller Interfacing to an 8 bit Processor Document Number X26A G 013 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the
355. w mode leaving this register un used Refer to Table 5 1 Number of Pixels Panned Using Start Address on page 28 to see the minimum number of pixels affected by a change of one to these registers 5 3 2 Examples 1D13704 X26A G 002 03 Example 5 Display 200 scanlines of image 1 and 40 scanlines of image 2 Image 2 is located first offset 0 in the display buffer followed immediately by im age 1 Assume a 320x240 display and a color depth of 4 bpp Calculate the Screen 1 Vertical Size register values vertical_size 200 C8h Write the Vertical Size LSB REG 13h with C8h and Vertical Size MSB REG 14h with a 00h Calculate the Screen 1 Start Word Address register values Screen 2 is located first in display memory therefore we must calculate the number of bytes taken up by the screen 2 data bytes_per_line pixels_per_line pixels_per_byte 320 2 160 total bytes bytes_per_line x lines 160 x 40 6400 Screen 2 requires 6400 bytes 0 to 6399 therefore the start address offset for screen 1 must be 6400 bytes 6400 bytes 3200 words C80h words Set the Screen 1 Start Word Address MSB REG ODHh to OCh and the Screen 1 Start Word Address LSB REG OCh to 80h Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Page 33 Vancouver Design Center 3 Calculate the Screen 2 Start Word Address register values Screen 2 display data is coming from the very beginnin
356. ware power save via GPIOO Programming Notes and Examples S1D13704 Issue Date 01 02 12 X26A G 002 03 Page 36 Epson Research and Development Vancouver Design Center 7 SwivelView 7 1 Introduction To SwivelView Many of todays applications use the LCD panel in a portrait orientation In this case it becomes necessary to rotate the displayed image This rotation can be done by software at the expense of performance or as with the S1D13704 it can be done by hardware with no performance penalty There are two hardware rotated modes Default Swivel View Mode and Alternate SwivelView Mode 7 2 Default Swivel View Mode 1D13704 X26A G 002 03 Default Swivel View Mode requires the portrait image width be a power of two e g a 240 line panel requires a minimum virtual image width of 256 This mode should be used whenever the required virtual image can be contained within the integrated display buffer i e virtual image size lt 40k bytes as it consumes less power than the Alternate SwivelView mode For example the panel size is 320x240 and the display mode is 4 bit per pixel The virtual image size is 320x256 which can be contained within the 40k Byte display buffer Default Swivel View Mode also requires memory clock MCLK gt pixel clock PCLK Programming Notes and Examples Issue Date 01 02 12 Epson Research and Development Vancouver Design Center Page 37 The following figures show how the programmer

Epson S1D13704F00A200 Datasheet

Contents

Download Pdf Manuals

Related Search

Related Contents