Technical Information Manual
Contents
1. Fig 5 3 PDL_CONTROL bit fields PDL_WR 1 enables the updating of the PDL delay value in this way the delay value set either via dip switch or via PDL_DATA register is automatically loaded By setting this bit to 0 the delay value cannot be changed PDL_DIR allows to select the source of data for PDL programming 0 the selected PDL has as delay value on its parallel programming bus the dip switch value 1 the selected PDL has as delay value on its parallel programming bus the PDL_DATA register 8 LSB PDL_SEL allows to select one of the PDL s PDLO and PDL1 for read write operations PDL_DATA register is used to Write the delay value for the next delay update via VMEbus Read the on board switch status Examples updating of PDLO delay via switch the default value in the PDL_CONTROL allows to update the delay directly via dip switch just after the board turning ON each change in the dip switch status set immediately a new delay value The sequence to be followed is Step 1 write 0x1 in the PDL_CONTROL register Step2 update the dip switches value B updating of PDL1 delay via switch Step 1 write 0x5 in the PDL_CONTROL register Step 2 update the dip switches value C updating of PDLO delay via VMEbus Step 1 write 0x3 in the PDL_CONTROL register Step2 write the delay value in the PDL_DATA register D updating of PDL1 delay via VMEbus Step 1 write 0x7 in the2. Quartus 11 C 1495 USER DEMO v1495usr_derno y File Edit View Project Assignments Processing Tools Window n Gb hd S fe R vtagsusr derr Project Navigator ax SY Files E a Device Design Files io gba SRC v1485usr demo v1495usr pkg vhd s SRC Av14985usr demo coin reference vhd abe SRC vi495usr demo spare if rtl svhd i es SACA 1495ust_demo tristate_if_rtl hd 5 bd SRC VI 495usr_demo w1495us1_demo vhd di 495hal w1495usr_hal vqm Hierarchy B Files d Design Units Fig 5 12 Quartus II netlist The first time the project is launched the hierarchy includes only the name of the head of the project v1495usr demo At the end of the project flow the whole hierarchical structure of the project is shown NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 39 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 Quartus I C V1495 USER DEMO v1495usr demo v1495usr demo File Edit View Project Assignments Processing Tools Window Help Ch ca E Bajo pones demo Project Navigator for Free Fig 5 13 Quartus II hierarchical structure In order to generate a new programmation file it is necessary to launch the compiler by clicking on the red play button on the tool bar Quartus Il C 41495 USER DEMO v1495usr demo v1495usr demo File Edit View Project Assignments Pr
3. Recent Files Recent Projects Exit At F4 System A Processing A Estra Info A Info A Wari Critical Waming Enor Suppressed Message 4 F ross Locats Opens an existing project forsee de NM Fig 5 10 Quartus II file menu browse the file project v1 495usr demo qpf File Edi Vew Project Assignments Processing Tools Window Help Bs m sls ERES 1 dixe we s rie ja Project Navigator diy Compilation Hierarchy Cerca in E V14886 USER DEMO eB sec TI irsion 6 Risorse del computer Risorse direte Nome file v1485u81 cemo qpf Tipo file Quartus lI Project File qpf quartus qar Annulla d essing A Extra Info it Eee ES 3 ae A Dwe For Help press F1 mem m ie NM Fig 5 11 Quartus II project browser NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495_REV5 DOC 43 38 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 Once the project is open the Project Navigator shows the following information There are 5 VHDL files filename vhd and a Verilog netlist listname vqm The reference design is included in the coin_reference vhd file The other files provide support to the project and shall not be midified by the developer HAL Hardware Abstraction Layer is implemented on the netlist Verilog v1495usr_hal vqm
4. Revision date Revision 30 04 2007 5 Title Mod V1495 General Purpose VME Board 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE These signals allows to handle the interface with the motherboard ports A B C G A_DIN and B_DIN signals show the logic level of A and B ports 32 bit input only The output logic level on port C can be set via C_DOUT signal The logic level on port G LEMO connectors can be set via G_LEV signal the direction via G_DIR the datum to be written via G_DOUT or to be read via G_DIN 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE These signals allows to handle the interface with the piggy back board ports D E F The following table explains the available signals Table 5 2 V1495 Mezzanine Expansion Ports signals Port Signal Function Applies to D D_DIR Selects direction Bidirectional port D_DIN Read the logic level Input Bidirectional D_DOUT Set the logic level Output Bidirectional D IDCODE Read IDCODE for piggy back identification All D_LEV Set the logic level Output Bidirectional E E DIR Selects direction Bidirectional port E DIN Read the logic level Input Bidirectional E DOUT Set the logic level Output Bidirectional E IDCODE Read IDCODE for piggy back identification All E LEV Set the logic level Output Bidirectional F F DIR Selects direction Bidirectional port F DIN Read the logic level Input Bidirect
5. Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 3 2 START 2 Lo T PULSE 2 E be COUNT 0 COUNT 1 COUNT 2 COUNT 2 START 3 PULSES COUNT 3 COUNTO COUNT 1 COUNT 2 GATE Fig 3 3 Timer2 and Timer3 used together for handling a Gate pulse FPGA Programming The programming of FPGA VME and FPGA USER are handled by two independent microcontrollers flash memory The updating of the firmware contained in the flash memories does not require the use of external tools and can be executed via VME The flash related to FPGA VME contains the firmware dedicated to the interface of the board with the FPGA USER and the VME bus such firmware is developed by CAEN The flash related to the FPGA USER contains the firmware developed by the User according to his own application requirements 3 2 1 FPGA VME NPO The microcontroller provides the firmware uploading at board s power on The flash memory contains two versions of the firmware which can be selected manually via jumper Standard or Backup FPGA VME Program Circuit VME BUS VME FPGA Fig 3 4 FPGA VME diagram Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 15 EPA Ema Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME
6. STARTx WIDTHMIN 320ns recommended 22ns absolute min STARTx PERIODMIN 640ns recommended 46ns absolute min Fig 3 1 Timers diagram The use of STARTx signals with timing shorter than those recommended is possible although the linearity on the set delay scale is no longer guaranteed 3 1 2 Timer2 Timer3 Each timer is made up of one digital circuit which produces a typical fixed time base with 10ns period and 50 duty cycle These timers are proposed for generating any Gate pulse gt 10ns with a 10ns step The following figure shows an example of a Gate generation made with Timer2 and n 3 PULSE width Fig 3 2 Gate pulse example START SN s 7 PULSE 2 ENS I L Tod yl COUNT 2 COUNTO X COUNT COUNT 2 GATE oL 2 A FPGA USER drives a STARTx pulse and after Tey time FPGA USER will receive a PULSEx clock signal A counter with clock PULSEx implemented in the FPGA USER allows to generate a pulse with programmable duration It is possible to reduce to one half bns the counter step by advancing the counter on both sides of PULSEx Since the circuit is completely digital no recovery time is necessary between one stop and the following start it is thus possible to generate multiple gate pulses with very high rate Timer2 and Timer3 can be used together for handling one single Gate pulse from multiple overlapped triggers Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 14
7. Revision 5 The CAEN Mod A967 Cable Adapter allows to adapt each Robinson Nugent Multipin Connector into two 1 17 17 pin Header type male connectors 3M 4634 7301 with locks through two 25 cm long flat cables N C CH31 CH17 CH16 DOOODUOOUOOOO00000 ODODODODOO O0OO0DOoo ana az mm me on n a Fig 2 3 Mod A967 Cable Adapter NPO Filename Number of pages Page 12 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 3 Operating modes 3 1 Timers Gate Trigger applications require the production of an output signal with programmable width Gate whenever an input signal Trigger occurs Gates can be produced in several ways according to the system set up which can be either synchronous or asynchronous Synchronous systems Input signals are referred to a system clock they can be sampled by the clock itself and the output is a gate signal obtained with a counter whose width and delay is a multiple of the clock period If the application requires a width and delay of the Gate signal synchronous but with step resolution higher than the system clock period this can be achieved by enabling the PLL in the USER FPGA and enter the reference clock on channel GO Asynchronous systems Input signals are not referred to a system clock As a consequence the gate signal will be generate
8. X 0004 represents a multiple of the selected delay line period see detailed description Number of pages 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT C_CONTROL_L 0x001A D16 WO Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 15 0 is controlled by this register C CONTROL H 0x001C D16 WO Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 31 16 is controlled by this register MODE 0x001E D16 WO It configures the behaviour of the X 0008 system Default I O MODE 1 0 DELAY SEL Register MODE 3 UNIT MODE Mode 0 Coincidcence Unit 1 VO Register MODE 4 OPERATOR 0 C A AND B 1 C A ORB MODE 5 PULSE_MODE See Description SCRATCH 0x0020 D16 RW This register is available to test X 5A5A read and write to a register G CONTROL 0x0022 D16 W Only Bit 0 G CONTROL 0 is X 0000 used in this reference design It can be used to select G output level 0 TTL omar ows pe few www mcomonr mwc os w fon NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 30 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose
9. gt TTL 1 gt NIM G_DIR OUT 1 Output Enable 0 gt Output 1 gt Input G_DOUT OUT 2 Out G LEMO 2 x NIM TTL G_DIN IN 2 In G LEMO 2 x NIM TTL V1495 Mezzanine Expansion Ports PORT D E F INTERFACE D_IDCODE IN 3 D slot mezzanine Identifier D_LEV OUT 1 D slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port D_DIR OUT 1 D slot Port Direction D_DIN IN 32 D slot Data In Bus D_DOUT OUT 32 D slot Data Out Bus NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 23 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 PORT NAME DIRECTION WIDTH DESCRIPTION E_IDCODE IN 3 E slot mezzanine Identifier E_LEV OUT 1 E slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port E_DIR OUT 1 E slot Port Direction E_DIN IN 32 E slot Data In Bus E_DOUT OUT 32 E slot Data Out Bus F_IDCODE IN 3 F slot mezzanine Identifier F_LEV OUT 1 F slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port F_DIR OUT 1 F slot Port Direction F_DIN IN 32 F slot Data In Bus F_DOUT OUT 32 F slot Data Out Bus PDL CONFIGURATION INTERFACE PDL_WR OUT
10. A24 A32 Base 0x8008 Geo Address Register A24 A32 Base 0x800A Module Reset A24 A32 Base 0x800C Firmware revision A24 A32 Base 0x800E Select VME FPGA Flash A24 A32 Base 0x8010 VME FPGA Flash memory A24 A32 Base 0x8012 Select USER FPGA Flash A24 A32 Base 0x8014 USER FPGA Flash memory A24 A32 Base 0x8016 USER FPGA Configuration A24 A32 Base 0x8018 Scratch16 A24 A32 Base 0x8020 Scratch32 A24 A32 Base 0x8100 0x801FE Configuration ROM A24 A32 Read Write capability depends on USER FPGA implementation See 5 7 4 1 1 Configuration ROM The following registers contain some module s information according to the Table 3 2 they are D16 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model V1495 checksum_length2 0x8104 Pe checksum_length1 0x8108 Pe checksum lengthO 0x810C SC NPO Filename Number of pages Page 00117 04 V1495 MUTx 05 V1495 REV5 DOC 43 17 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 9 mac oeo man oma mma CATE hee CTI hme wmm 0x8130 0 ms mma we mma ww mma rem oo emn COC Thes
11. Board 30 04 2007 5 3 2 2 FPGA USER The microcontroller provides the firmware uploading at board s power on The flash memory contains one firmware image only Standard FPGA USER Program Circuit ys o m FPGA VME lt gt g gt FPGA USER S A E J Fig 3 5 FPGA USER diagram FPGA VME aim is to handle the operation of FPGA USER which can be programmed on the fly i e without turning off the system thus allowing quick debug operations by the Developer Register implemented on FPGA VME allows the following operations e FPGA USER flash memory programming e FPGA USER updating NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 16 Document type User s Manual MUT Title Mod V1495 General Purpose VME Board Revision date Revision 30 04 2007 5 4 VME Interface 4 1 Register address map The Address map for the Model V1495 is listed in Table 4 1 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address Table 4 1 Address Map for the Model V1495 ADDRESS REGISTER CONTENT ADDR DATA Read Write Base 0x0000 0x7FFC USER FPGA Access A24 A32 R W Base 0x8000 Control Register A24 A32 Base 0x8002 Status Register A24 A32 Base 0x8004 Interrupt Level A24 A32 Base 0x8006 Interrupt Status ID
12. PDL_CONTROL register Step2 write the delay value in the PDL_DATA register GATE WIDTH USING Delay Line Oscillators Filename Number of pages Page 33 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 The GATEWIDTH register can be used to set the gate signal width on the G port see Delay Unit using DLOs see 5 5 6 5 5 5 Delay Unit using PDLs The following diagram shows the implementation of the DELAY UNIT using the one of the two programmable delay lines PDL available on the boards MONOSTABLE 360 ns pulse Fig 5 4 Delay Unit with PDLs Tmon COINC PDLXIN OL PDLxOUT ofS L PDL PULSEOUT STARTDELAY STOPDELAY Fig 5 5 PDLs Delay line timing The pulse width generated using PDLs Tp can be adjusted setting the PDL delay using either on board dip switches or through register When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY triggers a monostable in order to generate a pulse with a duration large enough to ensure maximum linearity performance of the This value should be more than 320 ns PDL see 3D3428 component datasheet The selected value in the reference design is 360 ns NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 34 Document type
13. REG PDLO PDL1 DLOO DLO1 Fig 5 2 Front Panel Ports Interface Diagram The following table illustrates the the register map of the USER FPGA reference design COIN REFERENCE NPO Filename Number of pages Page 00117 04 V1495 MUTx 05 V1495 REV5 DOC 43 28 Document type User s Manual MUT Title Mod V1495 General Purpose VME Board Revision 5 Revision date 30 04 2007 Table 5 7 COIN_REFERENCE register map NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT C_MASK_L 0x0014 C_MASK_H 0x0016 GATEWIDTH 0x0018 Filename NPO 00117 04 V 1495 MUTx 05 MER 16 D V1495 REV5 DOC Port A status This register reflects A 15 0 bit status Port A status This register reflects A 31 16 bit status Port B status This register reflects B 15 0 bit status Port B status This register reflects B 31 16 bit status Port C status This register reflects C 15 0 bit status Port C status This register reflects C 31 16 bit status Port A mask This register X FFFF A 15 0 Mask bit is active low Port A mask This register X FFFF A 31 16 Mask bit is active low Port B mask This register X FFFF B 15 0 Mask bit is active low Port B mask This register X FFFF B 31 16 Mask bit is active low Port C mask This register X FFFF C 15 0 Mask bit is active low Port C mask This masks C 31 16 register X FFFF Mask bit is active low Gate signal width This number
14. THE MODEL V 1495 ooo ceeceessscesececsseceseeecaeceeneecsaeceneecsaeceseeecsaeceeeeecsaeeeeneecaeeeses 17 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL V 1495 ooo ceeeeesseceseceesseceeeeecssecesneeesaeceseeeenaeceseecsaeeeeeeecsaeeeeees 17 TABLES 1COIN REFERENCE SIGNAES etre Eee ih et re e beet eedem e dese tate e eere dore een de 23 TABLE 5 2 V1495 MEZZANINE EXPANSION PORTS SIGNALS s cccsseceseeecsseceseeecsaeceeeecsaeceeeeecsaeceneecnaeceeneeenaeeees 26 TABLE 5 3 PDL CONFIGURATION INTERFACE SIGNALS cccssccesscecsseceseeecaeceeeeecsaeceseeecsaeceeeecnaeceneecaeeeeneessaeeeees 26 TABLE 5 4 DELAY LINES AND OSCILLATORS SIGNALS c ccssccesececssecesneecsecesneecsaececeecsaeceeeeecsaeceeneeenaeceeneesaeeeees 27 FABLE 2 5 SPARE INTERFACE SIGNALS dieere tee eet eret rl eee nde e e e e Patet eren 27 TABLE 5 6 LED INTERFACE SIGNALS 45er cte tete sico a 27 TABLE 5 7 COIN REFERENCE REGISTER MAP eese ener ettet erret testen entere enin tenter entere enne 29 TABLE 5 8 SELECTION OF THE DELAY LINE eeeeee eese enne nennen entente nent EEK EAE EEEO enne tentent entente nenne 32 NPO Filename Number of pages Page 00117 04 V1495 MUTx 05 V1495 REV5 DOC 43 5 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 1 General description 1 1 NPO Overview The Mod V1495 is a VME 6U board 1U wide suitable for various digital
15. Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 The PDL_PULSEOUT internal signal is generated as the logic OR of PDL_IN and PDL_OUT so generating a pulse whose width is proportional to the PDL actual delay The PDL_PULSEOUT signal falling edge is used to reset the flip flop state The pulse width Tp is Tp Tpd T pf Where Tpd is the delay of the selected PDL programmable via VME or by on board dip switches whichever mode is enabled Tpf is the delay introduced by the FPGA pad and internal logic The maximum pulse width is limited by the PDL maximum delay in this case 5 5 6 Delay Unit using DLOs The following diagram shows the implementation of the DELAY UNIT using two oscillators based on delay lines DLO present on the board DLOx DELAY COUNTER Fig 5 6 Delay Unit with DLOs COINC DLOx GATE l DLOx OUT L LS I l PULSE STARTDELAY DELAY_COUNTER 0 X 1i Y 2 XY s Yayo STOPDELAY rq PULSE_OUT Fig 5 7 DLOs Delay line timing NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 35 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 5 6 NPO When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY enables the oscillator o
16. ee A e EC e 18 423 INTERRUPILEVEL REGISTER ic 18 4 5 INTERRUPT STATUS ID REGISTER eee e en nennen nnn nnn nnn nnn nnn ESEESE pn pap h 19 4 6 GEO ADDRESS REGISTER cccoconoconononononononononononononononononononononononononononononononononononononononononononononononononononononos 19 T MODULE RESET REGISTER uec NR IAN RINT NIEVE NI TNNT 19 4 8 FIRMWARE REVISION REGISTER eeeeeeenene nen n nennen nnn nnn n n n nnn nnn nnns n npn n pn se erot 19 4 9 SCRATCH 6 REGISTER eee d e eee erede oy ec e reete eh dede des doi ed e e de 20 4 10 SCRATCH22 REGISTER en ed edo o E EE O amo Mod oe GEHE 20 4 11 SELECT VME FPGA FLASH REGISTER ccccococononononononononononononononononononononononononononononononononononononononononononos 20 4 12 SELECT USER FPGA FLASH REGISTER ccocococonononononononononononononononononononononononononononononononononononononononononos 20 4 13 VME FPGA FLASH MEMORY ccccccccsesesesesesesesesesssesesesesesesesecesesesesesesesesereseseseseseseseresesesesenenesenens 20 NPO Filename Number of pages Page 00117 04 V 1495 MUTXx 05 V1495 REV5 DOC 43 3 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 4 14 USER FPGA FLASH MEMORY ccccccccsceeseseseseeeseseseseseseseseseseseseseseseseseseseseseseseseseseseeeeeseeeseseseseeens 20 4 15 USER FPGA CONFIGURATION REGISTER ccccccceseeesesesesesesesesesesesesesesesese
17. 0 it is necessary to launch V1495Upgrade V1495 rbf 32100000 user standard If the upgrading is successful the number of transferred bytes is reported and the program is exited If the upgrading fails then an error message is reported In case of successful upgrading the new firmware can be loaded without turning the board and the crate off by performing a write access on the USER FPGA Configuration register Base Address 0x8016 it is necessary to write 1 in order to reload the FPGA configuration The Flash Memory programming algorithm flow chart is reported below see source code for details 5 7 2 VME FPGA Upgrade VME FPGA flash memory can be updated in a similar way to the USER FPGA the board can store two firmware versions called STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the SW9 jumper on the motherboard which can be placed either on the STD position or in the BKP position The program to be launched is V1495Upgrade FileName BaseAdd vme image With FileName the path to be followed of the RBF file generated with Quartus Il see 5 6 BaseAdd the base address Hex 32 bit of the V1495 board Image Standard or Backup default standard Filename Number of pages Page 42 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpos
18. 04 2007 5 Design Entry Power Synthesis Analysis Engineering Timing Change Analysis Management Includes block based design system level design amp software development Programming amp Configuration Fig 5 8 Quartus II project flow The following screenshot shows the main menu of Quartus ll File Edit View Project Assignments Processing Tools Window Help osujs ae o e dx eee o v je e Project Navigator By Compilation Hierarchy A N Implement n for ENS Low Cost Processor in Cyclone Il FPGAs Y Documentation Bl System Procesna X Emari V Ino A Waring A Onea Waring A Ena A Supera Beene El P kocsin Locate For Help press F1 Toran Idle yum Fig 5 9 Quartus II main menu NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495_REV5 DOC 43 37 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 Now select File gt Open Project Edit View Project Assignments Processing Tools Window Help ow Jeep Xx evejo AA Ima ou Project Wizard Convert MAX PLUS II Project Save Project f No s Implement a dur fia SS Low Cost Processor SS in Cydone Il FPGAs YN gt m A UA a Bl Vis feta leEe nA File Pr i I UARTUS II Create Update C 4 Export Version 6 0 Convert Programming Files
19. 1 Write Enable PDL_SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read DELAY LINES AND OSCILLATORS I O PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLOO OUT IN 1 Signal from DLOO Output DLO1_OUT IN 1 Signal from DLO1 Output PDLO_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to PDL1 Input DLOO GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal to DLOI Input SPARE INTERFACE SPARE OUT OUT 12 SPARE Data Out SPARE IN IN 12 SPARE Data In NPO Filename 00117 04 V 1495 MUTx 05 V1495 REV5 DOC Number of pages Page 43 24 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 PORT NAME DIRECTION WIDTH DESCRIPTION SPARE_DIR OUT 1 SPARE Direction LED INTERFACE RED_PULSE OUT 1 RED Led Pulse active high GREEN PULSE OUT 1 GREEN Led Pulse active high 5 3 Interface description NPO 5 3 1 Global Signals The nLBRES must be used as an asynchronous reset signal by the user An active low pulse will be generated when a write is done at the Module Reset register address see 4 1 The LBCLK is a 40 MHz clock It is the FPGA main clock 5 3 2 REGISTER INTERFACE The signals of the Register Interface allows to read write into the USER FPGA registers which can be accessed via VMEbus The COIN REFERENCE modu
20. 3 50 0 SE Flow Non Default Global Settir 83 Flow Elapsed Time oe spare_if12 0 0 0 amp B Flow Log geo tristate_ f13 0 n D SU Analysis amp Synthesis 80 Fitter Flow Status Successful Mon May 15 10 15 55 2008 iz eS a ze Quartus ll Version 6 0 Build 178 04 27 2006 SJ Web Edition gem Revision Name v1495ust_demo Top evel Entity Name vl485usr demo Family Cyclone Device EP1C4FADOCE Timing Models Final Met timing requirements Yes gt Total logic elements 873 4 000 22 i e Total pins 275 301 91 Hi Fil D Unit y Hisrchy E Fies E Derin Total virtual pins 0 Status ajx Total memory bits O 78 336 0 Module Progress Time Total PLLs 972 0 Full Compilation 00 01 26 Analysis amp Synthesis 00 00 35 Fitter 1 00 00 40 Assembler 00 00 06 Timing Analyzer 00 00 05 L lt gt a E 5 Info Quartus II Timing Analyzer was successful 0 errors 4 warnings A 3 Info Quartus II Full Compilation was successful 0 errors 13 warnings 3 ME i gt 5 V System Processing Extra Info A Info A Warming A Critical Waming A Error Suppressed T Message 0 of 698 4 x E For Help press Fi TN Idle NUM Fig 5 15 Quartus II compiling summary At this point an updated RBF file is generated in the project directory This file can be used for updating the firmware as described in S 5 7 Firmware upgrade It is possible to upgrade the board firmware via VME
21. 495 Motherboard I O sections Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E A 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34434 pins input range 4V to 5V Fail Safe input feature LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E B 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34434 pins input range 4V to 5V Fail Safe input feature LVDS Robinson Nugent P50E C 32 Output Direct 1000hm RI 250MHz 068 P1 SR1 TG type 34 34 pins TTL IN Direct NIM TTL 1 0 TTL OUT Direct selectable G 2 selectable NIM IN Invert Open 50ohm Rt UE LEMO 00 NIM OUT Direct selectable 2 6 Mezzanine Specifications The four I O Mezzanine boards developed so far are described in the following table Table 2 3 V1495 Mezzanine boards Board No ofCh Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E A395A 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34 34 pins input range 4V to 5V Fail Safe input feature LVDS Robinson Nugent P50E A395B 32 Output Direct 250MHz 068 P1 SR1 TG type 1000hm RI 84 34 pins Robinson Nugent P50E A395C 32 Output Direct ECL 300MHz 068
22. 7 5 4 15 USER FPGA Configuration Register Base Address 0x8016 read write D16 This register allows the update of the USER FPGA configuration A write access to this register generates a configuration reload The configuration image Standard will be uploaded into the USER FPGA as the IMAGE SELECT bit is set to 1 IMAGE SELECT 1 Standard image default ESL EE ESTEE ERI CEA Es a IMAGE_SELECT Fig 4 5 USER FPGA Configuration Register Filename Number of pages Page V1495_REV5 DOC 43 21 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 5 V1495 USER FPGA Reference Design Kit 5 1 Introduction The CAEN V1495 board provides a user customizable FPGA called USER FPGA The COIN_REFERENCE reference design illustrates how to use the USER FPGA to implement a Coincidence Unit amp I O Register Unit This design can be customised by the user in order to adapt its functionality to his own needs ON BOARD DELAY LINES HARDWARE ABSTRACTION LAYER MEZZANINE reus N CARD N ON SLOT D MEZZANINE carb Y ON SLOT E USER DEFINED LOGIC CAEN LOCAL BUS MEZZANINE CARD N ONSLOT F Port A 32 IN ECL LVDS Port B 32 IN ECL LVDS Port C 32 OUT LVDS Fig 5 1 U
23. Gate Trigger Translate Buffer Test applications which can be directly customised by the User and whose management is handled by two FPGA s FPGA Bridge which is used for the VME interface and for the connection between the VME interface and the 2nd FPGA FPGA User through a proprietary local bus FPGA Bridge manages also the programming via VME of the FPGA User FPGA User which manages the front panel I O channels FPGA User is provided with a basic firmware which allows to perform coincidence matrix I O register and asynchronous timers functions FPGA User can be also free reprogrammed by the user with own custom logic function see 5 1 It is connected as slave to the FPGA Bridge via CAEN Local Bus whose protocol shall be used in order to communicate with the FPGA Bridge and thus with the VME bus The I O channel digital interface is composed by four sections A B C G placed on the motherboard see 1 2 The channel interface can be expanded in the D E F sections by using up to 3 mezzanine boards see 2 6 and 2 7 which can be added choosing between the four types developed in order to cover the I O functions and the ECL PECL LVDS NIM TTL electrical standard see 1 2 The maximum number of channels can be expanded up to 194 The FPGA User can be programmed on the fly directly via VME without external hardware tools without disconnecting the boar
24. IG 4 1 INTERRUPT LEVEL REGISTER eee eene emen nnnm eS EEE ESENE ner ese ese e etes e sss ese ese esses ENEE EEEa 18 FIG 4 2 INTERRUPT VECTOR REGISTER eee ee e e ene emen a sese se esses e ese sese sse e esses sess etes esee esee 19 FIG 4 3 GEOGRAPHICAL ADDRESS REGISTER ccccccccccncncnnnnononononononononononononononononononononononononononononononononononononononeneness 19 NPO Filename Number of pages Page 00117 04 V 1495 MUTXx 05 V1495 REV5 DOC 43 4 Document type Title Revision date Revision Users Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 FIG 4 4 FIRMWARE REVISION REGISTER cssccssssseosecesssvencecessevensessssevonsecessevenseessseveoseessssvensesssevonsesasevensessaes 19 FIG 4 5 USER FPGA CONFIGURATION REGISTER cssccecsseceercecsseceseeecsaeceeceecsaeceeneecsaeceeeecsaeceeneeeaeeeeneesaeeses 21 FiG 5 1 USER FPGA BLOCK DIAGRAM tooodo tbenbeceaptvonnecanapdacvevstadebenbodgeeevasestaccendesoues 22 FIG 5 2 FRONT PANEL PORTS INTERFACE DIAGRAM ssccessscesseecseceseeecsaecesceecsaeceneecsaeceneecsaeceeeecaeeeeeeeeaeeeees 28 E16 5 3 PDL CONTROL BIT FIEEDS inrer e erp ree EUR ERREUR dE SERRE GE PR ORE E leidos 33 FiG 5 4 DELAY UNIT WITH PDLS ert ete aia 34 FIG 5 5 PDES DELAY LINE TIMING piore reti Feet ete e ee EAR Fee EY XE te da ies EX EVER EEEE ce EE EA teens totes 34 EG 5 60 DELAY UNIT WITH DL OS edidere tete iet hd epe dioe e ee Patel eee d
25. P1 SR1 TG type 34 34 pins TTL IN Direct NIM TTL 1 0 TTL OUT Direct selectable A395D 1118 selectable NIM IN Invert Open 50ohm Rt ir LEMO 00 NIM OUT Direct selectable NPO Filename Number of pages 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Page 10 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 2 Mezzanine boards installation In order to install one A395x series mezzanine board on the V1495 motherboard it is necessary to follow these steps Remove unscrew the metal cover one at will Plug the mezzanine board into the 100 pin connector on the motherboard Fixthe mezzanine board with the screws WARNING If you wish to install three A395C s on the module please contact us at support nuclear caen it 2 8 Front panel connector cabling Motherboard I O sections A B C and A395A A395B and A395C Mezzanine boards feature the Robinson Nugent P50E 068 P1 SR1 TG multipin connector whose pin set is shown in the following figure N C N C N C N C CH31 CH15 CH31 CH15 CH30 CH14 CH30 CH14 CH17 CH1 CH17 CH1 CH16 CH0 CH16 CHO Fig 2 2 Multipin connector pin assignment NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 11 Document type Title User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 Revision date
26. RIREQUIREMENTS nit e ir decere E Gv Ren er e RE eei ax eee ec b ix eR re eine eee Ee 8 2 3 FRONT PANEL DISPLAYS eeseeeetee Ie eene ener nsese ese e ese e ese ese ese ese ases sseseseseseseses eset etes esee eset eset ee 8 2 4 BRONTPANEL z enu eO EO RENOVARE GNE EE EO VETERA CIT ee cc 9 2 5 MOTHERBOARD SPECIFICATIONS ccccccccoscoccssescoccecescoscesescoveccescocessesseceecescescesescevescescesessessocescescoseesessovvs 10 2 6 MEZZANINE SPECIFICATIONS c cccccccsccececcoseccccccecececcescscecsocceseccesesescsescseescescsesesesceseccesosecesoscesessoseseessoves 10 2 7 MEZZANINE BOARDS INSTALLATION cccccccccecccececcsescceseseceseseseseseseseseseseseseseseseseseseseseeeseseseseseesseseseeseeees 11 2 8 FRONT PANEL CONNECTOR CABLING eee e ene e a a ea a ese ese assess ier esee esee es eset esee esee 11 3 OPERA TING MODES e E A 13 31 MIME A e nce 13 3 1 1 Tun rO ALUMNO L serai a A AE A e ALAE de E Noa 13 3 1 2 Tun r2 2IImer335 5 s teme mentehotesetevhiedeteetadeneta eus beet 14 3 2 3 FPGA PROGRAMMING 5 eee ete ai e dida cdt es 15 3 2 1 gut ar o 15 3 2 2 EPGA USER A adi 16 4 AVINEUD SU 17 44 REGISTER ADDRESS MAP 5s eset titer eer eee ect he eere eee eet e pete eee eee eder eh een 17 4 1 1 Configuration RO Mision ddr eee rie ee c t eee ie en 17 AD CONTROL REGISTER ueterem n tre RHEINE 18 4 3 STATUS REGISTER 5 55 ete e erdeace e
27. SER FPGA block diagram 5 2 Design Kit 5 2 1 V1495HAL The V1495 Hardware Abstraction Layer V1495HAL is a HDL module provided in Verilog format at netlist level in order to help the hardware interfacing NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 22 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 5 2 2 COIN_REFERENCE Design The COIN REFERENCE design VHDL entity is the interface to the V1495HAL If the User wishes to use V1495HAL to develop his own application on the V1495 platform the VHDL entity must not be modified this means that signals names and function of the COIN_REFERENCE entity must be used as shown in the following table Table 5 1 COIN_REFERENCE signals PORT NAME DIRECTION WIDTH DESCRIPTION GLOBAL SIGNALS NLBRES IN 1 Async Reset active low LCLK IN 1 Local Bus Clock 40 MHz REGISTER INTERFACE REG_WREN IN 1 Write pulse active high REG_RDEN IN 1 Read pulse active high REG_ADDR IN 16 Register address REG_DIN IN 16 Data from CAEN Local Bus REG_DOUT OUT 16 Data to CAEN Local Bus USR_ACCESS IN 1 Current register access is at user address space Active high V1495 Front Panel Ports PORT A B C G INTERFACE A_DIN IN 32 In A 32 x LVDS ECL B_DIN IN 32 In B 32 x LVDS ECL C_DOUT OUT 32 Out C 32 x LVDS G_LEV OUT 1 Output Level Select 0
28. TATUS ID Fig 4 2 Interrupt Vector Register 4 6 GEO Address Register Base Address 0x8008 read D16 The register content is the following GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 4 3 Geographical address register This register allows readback of the level of GEO pins for the selected board The register content is valid only for the VME64X board version The register content for the VME64 version is Ox1F 4 7 Module Reset Register Base Address 0x800A write only D16 A dummy access to this register allows to generate a single shot RESET of the module 4 8 Firmware Revision Register Base Address 0x800C read only D16 This register contains the firmware revision number coded on 8 bit For instance the REV 1 2 register content is EXER EIE ESTER GA CURES ERES CREDI o oro ojo ejoj1 o ojo ojo ojt o Ox1 0x2 Fig 4 4 Firmware Revision Register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 19 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 4 9 Scratch16 Register Base Address 0x8018 D16 read write This register allows to perform 16 bit test accesses for test purposes 4 10 Scratch32 Register Base Address 0x8020 D32 read write This register allows to perform 32 bit test accesses for test purposes 4 11 Select VME FPGA Flash Registe
29. Technical Information Manual Revision n 5 30 April 2007 MOD V1495 GENERAL PURPOSE VME BOARD NPO 00117 04 V1495 MUTx 05 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CE CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 TABLE OF CONTENTS T GENERAL DESCRIPTION gi sccsessssecisssesvcsesvesvossnsesvssevsssesssvcessecntestvesc s sucuess sceteeivesecsesvebestes ecedbesseccssuasesvesses 6 kli OVERVIEW a e e ce 6 12 BEOCK DIAGRAM A aa gi 2 TECHNICAL SPECIFICATIONS oso ooa oo eran oe epo o o Eee a ao eta Pa oer noe E arena e eS Ina stss E PER e e eR Ka e apa 8 Delt EM Lei elt RENNES 8 2 2 iJPOWE
30. VME Board 30 04 2007 5 hs mcomonr nms os fw im mcomons nwe os fw eow __ _ REVISION 0x003C Firmware revision For example X XXYY the register conent for release 1 0 is X 0100 PDL CONTROL 0x003E D16 It allows to either set the PDL X 0001 delay though either on board Default PDL switches or via VMEbus delay is set by on board dip switches D IDCODE 0x0042 D16 Read Slot D mezzazine ID Code ID Code is X 0007 if mezzanine is plugged E_IDCODE 0x0044 D16 Read Slot E mezzazine ID Code ID Code is X 0007 if mezzanine is plugged F_IDCODE 0x0046 D16 Read Slot F mezzazine ID Code ID Code is X 0007 if mezzanine is plugged 5 5 REGISTER DETAILED DESCRIPTION 5 5 1 V1495 Front Panel Ports Registers PORT A B C G The Front Panel ports A B C G can be configured and accessed using a set of registers The x MASK y x can be A B C y can be L or H registers can be used to selectively mask a bit of a port Each status register is split into two 16 bit register MASK_L corresponds to MASK 15 0 while MASK_H corresponds to MASK 31 16 There is not a MASK register associated with G port Each bit of the input ports A B mask registers are internally used in a logic AND operation with the corresponding bit of the port so it is an active low mask bit For instance when A_ MASK L 0 is set to 0 the A 0 bit is internally masked logic 0 NPO Filename Number of pages Pa
31. by writing the Flash for this purpose download the software package available at http www caen it nuclear software_download php The program is provided as executable source code and Microsoft Visual C 2005 project The executable file is the pre compiled program for Windows platform The program is based on the CAENVMEIib library available both for Windows and Linux The program must be launched as follows V1495Upgrade FileName BaseAdd TargetFPGA image These are the options available and defaults Filename the RBF filename V1495vme01 rbf for instance BaseAdd hex value of base address of the 1495 32100000 is the module is mapped has a base address equal tio 0x32100000 TargetFPGA vme or user user is default option if not specified image standard or backup standard is default option if not specified Filename Number of pages Page 00117 04 V1495 MUTx 05 V1495_REV5 DOC 43 41 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 NPO 5 7 1 USER FPGA Upgrade In order to update the flash memory of the USER FPGA the program must be launched as follows V1495Upgrade FileName BaseAdd user standard With FileName the path to be followed of the RBF file generated with Quartus Il see 5 6 BaseAdd the base address Hex 32 bit of the V1495 board For example in order to update the firmware of a V1495 with base address 3210000
32. d from the set up without resetting it or turning the crate off allowing quick debug operations by the developer with his own firmware A flash memory on the board can store the different programming file which can be loaded to the FPGA User at any moment Four independent digital programmable asynchronous timers are available for Gate Trigger applications It is possible to chain them for generating complex Gate Trigger pulse Filename Number of pages Page 6 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 1 2 Block Diagram BRIDGE lt gt FPGA 16 32 64 bit VME interface 8 bit USER PROGRAMMABLE FPGA FW LOADING optional r v FLASH USER FPGA CONFIG Asyn Timers A Fig 1 1 Mod V1495 Block Diagram NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 7 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 2 Technical specifications 2 1 Packaging The module is housed in a 6U high 1U wide VME unit The board is provided the VME P1 and P2 connectors and fits into both VME standard and V430 backplanes 2 2 Power requirements T
33. d without any time reference It is possible to use the implementation described above with the freedom of choosing the clock source between external or 40MHz internal The resulting Gate signal will have stable duration but with maximum position jitter equal to one clock period Such position jitter can be rejected by using the asynchronous timers present on the V1495 which allow to generate references synchronous with the occurred trigger 3 1 1 Timer0 Timer1 NPO Each timer is based on a programmable delay line FPGA USER drives a STARTx pulse and after the programmed delay it receives the return signal PULSEx The time difference between transmission and reception logic implementation inside the FPGA USER can be used to drive a gate signal The programming of the delay time can be done manually as binary value either via 8 bit dip switches SW4 and SW5 or via VME register with a 1ns step resolution max step delay 255ns The software setting has higher priority with respect to the dip switches The following figure shows a diagram of the timers usage Filename Number of pages Page 13 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 lt Tperiod gt q iih y START 0 mooo qr Tset gt NPO Toffset PULSE pu ee a GATE Tdly Toffset Tset Toffset 30 2ns Tset SETBINARY Ins
34. dition implemented in this reference design is true when a bit per bit logic operation on port A and B is true The logic operator applied to Port A and B is selectable by means of a register bit MODE Register Bit 4 If MODE bit 4 is set to 0 an AND logic operation is applied to corresponding bits in Port A and B i e A 0 AND B 0 A 1 AND B 1 etc In this case a trigger is generated if corresponding A and B port bits are 1 at the same time If MODE bit 4 is set to 1 an OR logic operation is applied to corresponding bits in Port A and B i e A 0 OR B 0 A 1 OR B 1 etc In this case a trigger is generated if there is a 1 on one bit of either port A or B Port A and B bits can be singularly masked through a register so that a 1 on that bit doesn t generate any trigger Expansion mezzanine cards can be directly controlled through registers already implemented in this design The expansion mezzanine is identified by a unique identification code that can be read through a register PORTA A MASK operator de M ADIN Jal A S AND K M S M K BDN a B OR S ee COINCIDENCE E PORTB LOGIC COINC G DOUT 0 o DELAY G_DOUT 1 E READ ONLY REG WRITE ONLY
35. e VME Board 30 04 2007 5 PAGE 768d for VME STANDARD START PAGE ADDRESS SETTING PAGE 1408d for VME BACKUP PAGE 48 for USER STANDARD OPEN RBF FILE IN READ BINARY MODE READ ONE PAGE FROM FILE PAGE_SIZE 264d WRITE FLASH PAGE Writing in the FLASH of the page via VME register access Reading from the FLASH of the READ_FLASH_PAGE page via VME register access INCREMENT PAGE POINTER YES oo NO Fig 5 16 Flash programming algorithm flow chart NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 43
36. e data are written into one Flash page at Power ON the Flash content is loaded into the Configuration ROM 4 2 Control Register Base Address 0x8000 read write D16 This register allows performing some general settings of the module Not used for VME FPGA Rev 0 0 Foreseen for future development 4 3 Status Register Base 0x8002 read only D16 This register contains information on the status of the module Not used for VME FPGA Rev 0 0 Foreseen for future development 4 4 Interrupt Level Register Base Address 0x8004 read write D16 The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is 0x0 In this case interrupt generation is disabled Not implemented in VME FPGA Rev 0 0 Available in next releases 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 arr Fig 4 1 Interrupt Level Register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 18 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 4 5 Interrupt Status ID Register Base Address 0x8006 read write D16 This register contains the STATUS ID that the V1495 places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is OxDD Not implemented in VME FPGA Rev 0 0 Available in next releases 15 14 13 12 120110 9 8 7 6 5 4 3 2 1 0 S
37. ecaeceaeeceaeeeeaeecsaeeesnes 31 A V1495 Mezzanine Expansion Ports Registers PORT D E F esee 32 5 5 3 Delay Sel ctiOns ee E t te e m SH REED ERE eR e ERE d 32 5 5 4 PDL DELAY VALUE SETTING AND READBACK sse eene nn nun 32 5 5 5 Delay Unit using PDES ices seu Eire tt e EE e REN de copies e EE EEEE RE RAS 34 5 5 6 Delay Unitusing DEOS dei me e e e e EE cure pane SERE MEE pe ORI 35 5 6 QUARTUS II WEB EDITION PROJECT r r re a aa a te aea eeen oa ena Seea a or ES heana EEE 36 Dike EIRMWARE UPGRADE 000 A dece eaten ence ee EE ere d 41 5 7 1 USER FPGA Upgrades iioc tegunt tete ld gre tt 42 34 2 VME FPGA Upgrade eee eniti tie edet P EET 42 LIST OF FIGURES FIG 1 1 MOD V 1495 BLOCK DIAGRAM here eter eret eere eee Ee d 7 FIG 2 1 MODEL V1495 FRONT PANEL WITH A395A B C PIGGY BACK BOARDS sees enne ener 9 FIG 2 2 MULTIPIN CONNECTOR PIN ASSIGNMENT ccccccccccccccesesecesescsesesecescscsesesesesesesescsescsceesesesesesesessesessseseseeees 11 FIG 2 3 MOD A967 CABLE ADAPTER eeeeeeI Ie eme eme ene ener enesesesesese sese e ese ess e ese se sese ses esee esee esas eset esee stesse 12 FIG 3 31 TIMERS DIAGRAMA oido de 14 FiG 3 2 GATE PULSE EXAMPLE reete ett eet ee ee de a reet ate eese exe erede event ee eter oe e erede eoe 14 FIG 3 3 TIMER2 AND TIMER3 USED TOGETHER FOR HANDLING A GATE PULSE eeee eene 15 Ke 34 FPGA VME DIAGRAM loo Deo 15 EIG 5 5 EPGACUS BRE DIAGRAM stu ueeuno a iia 16 F
38. ection 5 3 8 LED Interface These signals when active for one clock cycle allow to generate a blink of the relevant Led Table 5 6 LED Interface signals RED_PULSE OUT 1 RED Led Pulse active high GREEN PULSE OUT 1 GREEN Led Pulse active high 5 4 Reference design description The reference design preloaded into the USER FPGA is given as a design guide It is a full functional application of the usage of the board as a concidence and or I O register unit This reference design give access to A B C G ports So no mezzanine expansion cards are needed in order to use this design The MODE register can be used to set the preferred operating mode When the board is switched on the default operating mode is I O Register mode NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 27 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 In I O Register Mode C port is directly driven by the C CONTROL register The coincidence is anyway still active so that a pulse in generated on G port when a coincidence event is detected In Coincidence Mode the C port is used to report the coincidence operator on A and B port In this case the C port can be masked through a mask register C MASK A gate pulse is generated on G port when data patterns on input ports A and B satisfy a trigger condition The trigger con
39. enda 35 FIG 5 7 DEOS DEEAY LINE TIMING 4 6 eres teas erben EE E R ERE Gee eR re PEE E ERE Feb tbat sole o v e Re ERE 35 FIG 5 8 QUARTUS II PROJECT FLOW essit cod sehcadescasenesscdbceidecaeda ceduveceleasuasheus ete ade ee eere a eroe cado ea ng 37 FIG 5 9 QUARTUS II MAIN MEN erora E aree aer Er E E a EAs E RE S ESE EEE EESE E 37 FIG 5 10 QUARTUSTLELE MEN aida 38 FIG 5 11 QUARTUS II PROJECT BROWSER csssccceessececssssecessscsecsesececssnaececsceecsesseeecsenaececnnesecsesaesecseseesesseaseceens 38 FIG 5 12 QUARTUS M NETLIS Di a a iii 39 FIG 5 13 QUARTUS II HIERARCHICAL STRUCTURE s cccssssecesssececeesnececsesaececsnsceceesseeecsesaececeeeeeesesaeeessesaeeesnenaeeeees 40 FIG 5 14 QUARTUS II COMPILER LAUNCHING ccccsssscecessseeecssececeesaececsesaececsceeceeueeecsesaececeeaeecseaeeecseaeeessaseeeeees 40 FIG 5 15 QUARTUS II COMPILING SUMMARY s cccssssscecessseeecsnscecessaececsesaececsnececeesueeecsesaececeeaeeceeaeeecsesaesesseaaeeeees 41 FIG 5 16 FLASH PROGRAMMING ALGORITHM FLOW CHART csccccssscesrcecsseceeneecaeceeneecsaecesneecsaeceeeeeesaeceeneessaeeeeee 43 LIST OF TABLES TABLE 2 1 MODEL V1495 AND MEZZANINE BOARDS POWER REQUIREMENTS ccce ener eene tnn nennen 8 TABLE 2 2 V1495 MOTHERBOARD I O SECTIONS eese ener eneen tenent entente nennen enn ee tenen enne 10 TABLE2 3 V1495 MEZZANINE BOARDS icc tette n ORE e DER E PEE EO EAE p FEE anne 10 TABLE 4 1 ADDRESS MAP FOR
40. ge 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 31 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 NPO Each bit of the output port C mask register is internally used in a logic AND operation with the corresponding bit of the internal signal so it is an active low mask bit For instance when C MASK _L 0 is set to 0 the C O bit is masked output bit is stuck at 0 The x_STATUS_ y x can be A B C y can be L or H registers can be used to read back eack port bit Each status register is split into two 16 bit register STATUS_L corresponds to STATUS 15 0 while STATUS H corresponds to STATUS 31 0 There is not a STATUS register associated with G port The x STATUS vy register reflects the status of the unmasked input and output ports A control register C CONTROL is available to set the C port when the board is configured in I O register mode 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F The mezzanine expansion ports D E F can be configured and accessed using a set of registers In this reference design no mask register is implemented for the expansion ports The x DATA y x can be D E F y can be L or H registers can be used to read back each port bit Each status register is split into two 16 bit register D DATA L corresponds to D 15 0 while D DATA H corresponds to D 31 16 The expansion ports can be bidirectional In case the por
41. he power requirements of the modules are as follows Table 2 1 Model V1495 and mezzanine boards power requirements Power supply Mod V1495 Mod A395A Mod A395B Mod A395C Mod A395D 5 V 1A 0 1A 0 1A 14A 11A 2 3 Front panel displays The front panel refer to 2 4 hosts the following LEDs DTACK Colour green Function it lights up green whenever a VME read write access to the board is performed USER Colour green orange red Function programmable NPO Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 8 Document type User s Manual MUT Title Mod V1495 General Purpose VME Board 2 4 Front Panel NPO 00117 04 V 1495 MUTx 05 Mod V1495 USER DTACK e e e A rom 00 lt r z w rom oocrz Revision date Revision 30 04 2007 5 Fig 2 1 Model V1495 front panel with A395A B C piggy back boards Filename V1495 REVS DOC Number of pages 43 Page 9 Document type User s Manual MUT 2 5 Motherboard Specifications Title Mod V1495 General Purpose VME Board Revision date 30 04 2007 Revision 5 The Mod V1495 Motherboard is composed by four I O sections see 1 2 described in the following table Table 2 2 V1
42. igure shows the typical project flow for generating the firmware for an ALTERA FPGA through the following steps Design Entry is the functional descritption of the circuit it could be either a description of the hardware VHDL Verilog AHDL or a scheme made with the tool provide by Quartus The reference design provided is developed through VHDL a VHDL knowledge is required in order to modify this design A different description can be developed with a different language among those allowed by the Quartus tool Syntesis translates the descritpion into a format compatible with the subsequent place amp route step Place amp route starting from the netlist performs the placing place and the subsequent interconnection route of the FPGA capabilities Simulation and timing analysis allow to verify the functionality of the project The reference design includes a minimum set of contraints in order to allow the design to perform the foreseen function The last important step is the generation of the programmation file Quartus allows to generate different formats the RBF format is the one used to program the FPGA USER via VME The provided reference project produces automatically this format in the project directory under the filename v1495usr demo rbf Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 36 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30
43. ional F DOUT Set the logic level Output Bidirectional F IDCODE Read IDCODE for piggy back identification All F LEV Set the logic level Output Bidirectional 5 3 5 PDL Configuration Interface PDL Configuration Interface signals are as follows Table 5 3 PDL Configuration Interface signals PDL WR OUT 1 Write Enable PDL SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 26 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 5 3 6 Delay Lines and Oscillators I O Delay Lines and Oscillators signals are as follows see also 5 5 5 and 5 5 6 Table 5 4 Delay Lines and Oscillators signals PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLOO OUT IN 1 Signal from DLOO Output DLOI OUT IN 1 Signal from DLO1 Output PDLO_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to PDL1 Input DLOO_GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal to DLOI Input 5 3 7 SPARE Interface These signals allow to set and read the status of SPARE pin present on the board Table 5 5 SPARE Interface signals SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPARE_DIR OUT 1 SPARE Dir
44. le shows how to implement a set of registers The following table shows the registers map as it is provided Each register address is coded via constants in V1495pkg vhd file This file allows to modify the registers map all registers allow D16 accesses write only read only or read write Registers default value is the value after a reset for write only and read write registers read only registers return the status of the signals read by the FPGA and have no default value The Register Interface allows to abstract the VME registers access The User can access a simple register interface two signals REG_WREN e REG_RDEN are pulses with a one clock cycle duration which enables respectively a write or a read access to a register REG_ADDR signal represents the register address Writing into a register In case of a write operation into a register via VME the 16 bit datum is available through the REG_DIN signal The datum is guaranteed stable on the CLK leading edge where REG_WREN is active The register access is valid only when USR_ACCESS is at logic level 1 Reading from a register In case of a read operation from a register via VME the datum to be returned must drive the REG_DOUT and be stable on the CLK leading edge where REG_RDEN is active The register access is valid only when USR_ACCESS is at logic level 1 Filename Number of pages Page 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 25 Document type User s Manual MUT
45. n external delay line DLOx selected via MODE register At the same time the DELAY_COUNTER is enabled The PULSE signal leading edge increases the counter until the value set via GATEWIDTH register is reached The PULSE signal corresponds in this reference with the selected PDL output On the first PULSE leading edge after the coincidence PULSE_OUT is activated high and is kept high until a time GATEWIDTH times the period of the selected DLO The period in this case is constant The maximum pulse width is limited by the GATEWIDTH counter in the case of this reference design the GATEWIDTH register is 16 bit wide so a maximum width of 65536 Td Td is the intrinsic delay of the selected DLO Quartus II Web Edition Project The freely available Altera Quartus II it can be downloaded from the Altera Web site software must be used in order to generate a user firmware for the USER FPGA It includes the source of VHDL reference design which can be modified according to the decription provided with the manual in order to modify the card functionalities The tool provides a complete pinout of the FPGA it is also enabled to generate the file type of programming RBF format used fot the flash programming This software tool requires the Quartus Il Web Edition rel 5 1 and newer and can be freely downloaded at http www caen it nuclear software_download php Quartus II manual is available at www altera com literature hb ats The following f
46. ocessing Tools Window Help IT TERT e R2 vraosusr demo jx 9g m FX eu Project Navigator xi amp Files E a Device Design Files os ewe SAC V1495ust_demo v1495ust_pkg vhd Download Es SRC v143Busr demo coin reference vhd i SRC v1495ustdemo spare_it_ttlvhd Aus SRC V1495uist_demo tistate_itrtlvhd Imp one f ES uis TOL Free te do SRC VI4SBust demo v1495usr demo vhd S Low Cost Processor i d SRC v1495hal v1 495usr_halvam in Cyclone Il FPGAs Software Files L I Other Files Fig 5 14 Quartus II compiler launching Quartus at this point launches in sequence the steps of the flow chart synthesis fitting place amp route then shows the correct compiling and the following screen NPO Filename Number of pages Page 00117 04 V1495 MUTx 05 V1495_REV5 DOC 43 40 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 5 7 NPO Quartus C V1495 USER DEMO v1495usr demo v1495usr_demo Compilation Report Flow Summary QE File Edit View Project Assignments Processing Tools Window Help 2X Dui amp BE a R viassusr demo cx 44 ug Dr Fre h SO mu Project Navigator BE Compilation Report Flow Su Entity Logic Cells LC Registers Mer Compilation Report Flow Summary Cyclone EP1C4F400C6 SB Legal Notice SE Flow Summary T 3 Flow Settings v1495usr hall 178
47. r Base Address 0x800E read write D16 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 12 Select USER FPGA Flash Register Base Address 0x8012 read write D16 This register allows USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 13 VME FPGA Flash Memory Base Address 0x8010 read write D16 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 14 USER FPGA Flash Memory Base Address 0x8014 read write D16 This register allows the USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 NPO Filename 00117 04 V1495 MUTx 05 Number of pages Page V1495_REV5 DOC 43 20 NPO 00117 04 V 1495 MUTx 05 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 200
48. seseseseseseceseseseseseseseseeeeees 21 5 V1495 USER FPGA REFERENCE DESIGN KIT cccssssscssssssccssssccccssssccssssccccsssscccssscsecesssesessnses 22 31s J INTROD CGCTION 3 ad ueesseeseeescessueenel eed uei eed he ENEETS 22 3 2 DESIGN KITE tet ERE ET EET as CENE e ee ERE IS 22 3 21 A A E 22 3 2 2 COIN REEERENCGE Desiglhi ie tei td AR e IRI utet Ode e aa ee ipe een 23 5 3 INTERFACE DESCRIPTION ccccccccccscscscsesecescsesescsesesesesesesssesssesesesescsesesesesssssesesssessssscssssssssssssssesesesesevevees 25 5 3 1 Global Signal eaa elo ade ad A RE PATE ep Ee og eus 25 5 3 2 REGISTER INTERFACE esee ertt idas 25 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE sss ener 26 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE essere 26 3 3 3 PDE Configuration Interface ssec pete pente deii ret ep Enea sas tds 26 5 3 6 Delay Lines and Oscillators T O test gd edi reete kiaia 27 5 3 7 SPARE Interface a Ge dr E e ee etre a ees EEE p sass 27 5 3 8 LEDAnterfdcen ina IA aa E deeds ahs EDO ERN OE 27 5 4 REFERENCE DESIGN DESCRIPTION cccccceccoccsceccoccsceccoccscececcoscecceccscccsoccsceceeecscececsesceccecceseccesveseceeevesevevees 27 5 5 REGISTER DETAILED DESCRIPTION cocococcncnononononcnnnnnnnononononononononononononononnnnnnnnnnnnnnnnnonononnnanononinons 31 5 5 1 V1495 Front Panel Ports Registers PORT A B C G cccssccessseesseceeeeensecsenc
49. t is configured as an output the register value set the port value In case the port is configured as an input the register content reflects current port value A x CONTROL register x can be D E F is available to set the corresponding port direction and logic level selection 5 5 3 Delay Selection The selection of the asynchronous timer is made through the MODE register by means of the DELAY SEL bit MODE 1 0 The selection of the delay line is made according to the following table Table 5 8 Selection of the delay line MODE MODB 0 DELAY LINE 0 0 PDLO 0 1 PDLI 1 0 DLOO 1 1 DLOI 5 5 4 PDL DELAY VALUE SETTING AND READBACK The programmable delay lines chip available on board can be programmed with a specific delay using on board 8 bit dip switch SW6 for Delay 0 and SW5 for Delay1 on motherboard via VMEbus Filename Number of pages Page 32 00117 04 V 1495 MUTx 05 V1495 REV5 DOC 43 Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 30 04 2007 5 NPO Two registers are available to configure PDLs PDL_CONTROL PDL_DATA PDL_CONTROL is used to Select target PDL for read write operations Enable delay update Select programming mode via VME register or by on board switches The PDL_CONTROL bit fields are shown in the following figure 2 1 L gt X PDL WR PDL DIR PDL SEL isi is ou 10 9 8 7 6 5 4 3 0
Download Pdf Manuals
Related Search