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1. ettet erecta De dede ebd Bde edet 109 BGT XV Em 109 zelo P 110 BESX label Ee ER ERR RS RR ER RENDERE 110 BGCX ini di 111 C 11 BVCX label 2 eene nde irte hti n dti tiene 112 112 BNCX S 113 113 IMP G 5 RR 114 IMP 2 it eu 114 0000 70 0000 80 EEEE E E E 115 EE o kE 116 ISR a a E 116 EE TE 117 er 118 cs 119 M A 120 Chapter 3 Use Of Instructions Notes Regarding Use of MStrUCtiONS 122 Minimum Knowledge 123 Word Accesses To Odd Addresses 123 Increment Decrement Of Address RISES 124 24 Bit Pointer Operations 125 Programming Examples General Speed Optimization Size Optimization 126 Register Initialization ette tenete een tet cte 126 126 Storing Immediate Data In MEMON 127
2. 0 F5 EF d8 Notes 33 src gt dest 150 JMP label16 PC434d16 labelt6 PC FC d16 I d16 h JMP label24 PC 5 d24 label24 PC F4 E0 d24 1 d24 m d24 h JMP An 34 src2dest 35 lt 36 src lt dest 37 src gt dest 38 src2dest 39 src lt dest 40 src lt dest 41 VX 0 42 VX 1 43 NX 0 44 NX 1 Instruction set An gt PC 24 bits signed 24 bits signed 24 bits signed 24 bits signed 24 bits unsigned 24 bits unsigned 24 bits unsigned 24 bits unsigned F0 An 2 Instruction Mnemonic JSR label16 Operation A3 4 A3 PC 3 mem24 A3 3 916 6 Machine Code FD d16 I d16 h JSR label24 4 5 24 5 924 24 4 1 924 1 924 924 1 4 PC 2 mem24 A3 An gt PC F0 01 An lt lt 2 PC 1 gt PC mem24 A3 gt PC A3 4 gt A3 mem16 A3 2PSW 24 2 A346 A3 Reading the instruction set W Symbols used in tables Dn Dm Di An Am MDR PSW PC imm8 imm16 imm16 l imm16 h imm24 imm24 l imm24 m imm24 h d8 d16 d16 l d16 h d24 d24 l d24 m d24 h abs16 abs16 l abs16 h abs24 abs24 l abs24 m abs24 h mema An mem8 0516 mem8 abs24 mem16 An mem16 abs16 mem16 abs24 mem24 mem24 abs16 mem24 abs24
3. 116 JSR Chapter2 Instruction Specifications JSR Operation A3 4 A3 2 24 15 0 An gt PC High byte Low byte Calls the subroutine at the address pointed to QUEM IEEE lower address by register An The stack pointer value will NewA3 SP PC42 return address lower be subtracted by 4 and the address of the next 2 return instruction after the JSR instruction the re turn address will then be stored at the stack pointer After the JSR instruction executes peel the stack will be as shown at right Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 5 FO 01 An lt lt 2 JSR 117 Chapter 2 Instruction Specifications N OP Branch Instructions Operation 1 PC Proceeds to the next instruction without performing any operation Flag Changes Size Cycles Codes No changes 118 NOP Chapter2 Instruction Specifications R S Branch Instructions RTS Operation 24 A344 0 High byte Low byte PC return address lower PC return reserved Lec Size Cycles Codes lower address Returns from a subroutine to the original pro OIdAS SP gram The address of the next instruction to execute will be popped from stack into PC and 4 will be added to the stack pointer NewA3 SP After the RTS instruction executes t
4. 88 OR immo b eh be 89 OR RENE 89 D 90 XOR imo ciae tr 90 Mer PY 91 ASR 92 Ep P 93 MEPPI 94 Di E 95 Bit Manipulation Instructions DI 96 BIST 96 BSED Diy 97 BCLR AT 98 Branch Instructions T 99 BNE trei n c dn ine biens 99 IEEE E 100 55 5 100 labe E 101 BGT labe 101 cielo D 102 BES 102 BCC label p 103 zii 103 OGM ccc 104 BS 104 ea ee eere i cedens 105 BNS 105 106 107 EE 107 BETA o 108 BLEX Iaa ih tite ads 108
5. 81 Chapter2 Instruction Specifications Operation Dm An Subtracts the values of register An from the value of register Dm but the result is not stored in register Dm Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated to MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise f Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 lt lt 2 Subtracts values of register from the value of register Am but the result is not stored register Am Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated to MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0
6. NX 1 then PC 3 d8 label IF VX NX 0 then PC 3 If VX is 0 and NX is 1 or if VX is 1 and NX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both VX and NX are 0 or if both are 1 then execution will continue with the instruction following the BLTX instruction For example the BLTX instruction will branch when the previous CMP instruction encounters src dest as a signed 24 bit value Flag Changes Size Cycles Codes No changes Operation 108 BLEX label Flag Changes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E3 d8 Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E0 d8 IF NX I ZX 1 then PC 3 d8 label IF VX NX I ZX 0 then PC 3 If VX is 0 and NX is 1 or if VX is 1 and NX is 0 or if ZX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both VX NX and ZX are 0 or if both VX and NX are 1 and ZX is 0 then execution will continue with the instruction following the BLEX instruction For example the BLEX instruction will branch when the previous CMP instruction encounters src gt dest as a signed 24 bit value Size Cycles Codes Chapter2 Instruction Specif
7. Di ab524 terne decirte 40 JMP 115 27 Dri MDR nete tmn desc ie dead 29 s scis re i rene eT 28 JSR AIG 44 L LSR bl 93 PSW ID icr nier eiut 28 MOVB 86516 ser See 52 eco ND M 53 anaes 50 MOV abeo ATI uhren ente eee titi 36 98 AD DIT e cca eite rece etre ti 50 Di PE 40 Dm 53 An zie tere 41 Drm d8 An uo Saad eire edite 54 1 016 T 41 016 4 0 4 44 1 54 m AM a a 33 616 nre renti ee es 59 Ss 26 AD DU tane deu axes 30 AB AN AIM asc tas itta tr e tee stus 34 AB AT DITE us acit citare cient tre ees xs 30 916 34 916 tien 31 024 AT PAM Tea creber HERREN HAUTE 35 MOVX 924 An aet 31 Di An Drs o 48 Dro de AD iiic iin nen 48 GIG An uias cio tetti tette iR ore 49 924 49 MUL 78
8. MOVB 98 An Dm Operation Bytes 2 Cycles 2 30 lt lt 2 B8 Dm mem8 An d8 Sign extends the 8 bit displacement 128 to 127 adds it to register An to obtain a pointer to memory sign extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes No changes Size Cycles Codes Bytes 3 Cycles 2 F5 20 An lt lt 2 Dm 48 50 MOVB Chapter2 Instruction Specifications MOVB 416 An Dm mem8 An d16 Dm Operation Sign extends the 16 bit displacement 32768 to 32767 adds it to register An to obtain a pointer to memory sign extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes l MOVB 424 An Dm mem8 An d24 Dm F7 0 lt lt 2 416 1 d16 h Operation Adds the 24 bit displacement to register An to obtain a pointer to memory sign extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes Bytes 5 Cycles 3 F4 A0 An lt lt 2 Dm 424 1 d24 m d24 h MOVB 5l Chapter2 Instruction Specifications MOVB An Dm Operation mem8 An Di Dm Adds the register Di to register An to obtain a pointer to memory sign extends the contents of that mem
9. gt mem24 A3 PC 3 d16 label16 gt Calls the subroutine at the address indicated by la bel16 The subroutine call range is from 32768 Operation bytes before the first address of the next instruction to 32767 bytes after The stack pointer value will be subtracted by 4 and the address of the next instruc tion after the JSR instruction the return address will then be stored at the stack pointer After the JSR in struction executes the stack will be as shown at right Flag Changes No changes JSR Operation label24 A3 4 A3 5 gt mem24 A3 PC 5 d24 label24 gt Calls the subroutine at the address indicated by label24 The stack pointer value will be sub tracted by 4 and the address of the next in struction after the JSR instruction the return address will then be stored at the stack pointer After the JSR instruction executes the stack will be as shown at right Flag Changes No changes lower address 0 High byte Low byte 3 return address lower PC 3 return aaa SEE cu NewA3 SP OIdAS SP Size Cycles Codes Bytes 3 Cycles 4 FD d16 1 d16 h 15 0 High byte Low byte 5 return address lower Size Cycles Codes lower address NewA3 SP OIdA3 SP Bytes 5 Cycles 5 F4 El 424 1 d24 m d24 h 1 The assembler will determine whether 416 424 is optimazation processing
10. 4 2 3 Program Counter 4 2 4 Multiply Divide Register 4 1 nene 4 2 5 Processor Status Word 5 Instruction 7 3 1 Data Move 7 3 2 Arithmetic Calculation Instructions 4 22 8 3 3 Logical Calculation Instructions 44 44 eene eee 8 3 4 Manipulation 9 3 5 Branch 10 Memory Space ROM 11 Addressing 4 000 nene nenene nennen 12 5 1 Register Direct Addressing sse nnne 14 5 2 Immediate Addressing 14 5 3 Register Indirect Addressing 2 eene 15 5 4 Register Relative Indirect Addressing eee 16 5 5 Absolute Addressing eene enn nnne 17 5 6 Indexed Register Indirect Addressing eee 17 Instruction 18 6 1 Endian 18 6 2 Instruction 0 19 Operand Format 20 7 1 Single Operand Format 1 operand eee nee 20 7 2 Double Operand Format 2 operands eee
11. Symbol Definitions 25 Chapter2 Instruction Specifications M Data Move Instruction Flag Changes Size Cycles Codes Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 F2 0 lt lt 2 26 Dm gt An Moves the value of register Dm to register An Bytes 2 Cycles 2 F2 30 Dm lt lt 2 An An gt Dm Moves the value of register An to register Dm Chapter2 Instruction Specifications Dn gt Dm Moves the value of register Dn to register Dm Flag Changes Size Cycles Codes Cycle 1 1 The same register cannot be specified for Dn and Dm Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 F2 70 lt lt 2 80 Dn lt lt 2 Dm gt Am Moves the value of register An to register Am Mov 27 Chapter2 Instruction Specifications PSW Dn Zero extends the value of PSW to 24 bits and moves that value to register Dn Flag Changes Size Cycles Codes MOV Dn PSW VX Will be set to bit 7 of the moved data CX Will be set to bit 6 of the moved data NX Will be set to bit 5 of the moved data ZX Will be set to bit 4 of the moved data VF Will be set to bit 3 of the moved data CF Will be set to bit 2 of the moved data NF Will be set to bit 1 of the moved data Will be set to bit 0 of the moved data Bytes 2 Cycles 2 F
12. XOR Dn Dm 00 8 F3 20 Dn lt lt 2 Dm 15 XOR imm16 Dn Dn imm16 Dn F7 4C Dn imm16 l imm16 h 15 NOT Dn Dn x O0FFFF Dn F3 E4 Dn 15 ASR Dn Dn Isb CF Dn bp Dn bp 1 bp15 1 Dn bp15 Dn bp15 o o o o o o e oe e e e o o o e o o e o o o e e e e e e MO m I TO mo o N N TO ITO F3 38 Dn 15 Dn Isb gt CF Dn bp Dn bp 1 bp15 1 0 Dn bp15 F3 3C Dn Dn Isb temp Dn bp Dn bp 1 bp15 1 CF Dn bp15 temp CF F3 34 Dn Dn bp15 temp Dn bp Dn bp 1 bp14 0 CF Dn Isb F3 30 Dn BTST imm8 Dn Dn amp imme PSW F5 04 Dn imm8 BTST imm16 Dn Dn amp imm16 PSW F7 044Dn imm16 l imm16 h BSET Dm An mem8 An amp Dm PSW meme8 An Dm mem8 An F0 20 An lt lt 2 Dm BCLR Dm An mem8 An amp Dm PSW mema8 An amp Dm mem8 An F0 30 An lt lt 2 Dm BEQ label IF ZF 1 PC 24d8 label 2PC IF ZF 0 2 E8 d8 BNE label IF ZF 0 PC 2 d8 label PC IF ZF 1 2 Notes 15 16 bit computation 16 Performed under the conditions of bus lock and disabled interrupts IF VF NF 1 PC 2 d8 label PC IF VF NF 0 2 17
13. 11 Address registers 00 Al 01 A2 10 11 Other registers are fixed by the instruction Ex The one byte instruction MOV An Dn is represented by the in struction code 20 lt lt 2 Dn MOV 1 DO instruction code x 24 7 0 ERR Operation A1 DO Source Destination Instruction Format 19 Chapter 1 Instruction 56 Overview 20 Operand Format Operand Format M IEEE RE XXX The calculation and move instructions of this series are divided into two different operand formats single operand format 1 operand double operand format 2 operands Single Operand Format 1 Operand Sa a With single operand format the register that specifies the operand is read and then the calculation result is stored back in that register Operand Value Calculation gt Operand Value Thesingle operand instructions are EXT EXTX EXTXU EXTXB EXTXBU NOT ASR LSR ROR and ROL The only addressing mode of these instructions is register di rect addressing Chapter 1 Instruction Set Overview 7 2 Double Operand Format 2 Operands With double operand format a calculation is performed on the register RAM or immediate values specified by the source and destination operands and then the result is stored back in the register or RAM specified by the destination operand Destination Source Destination Ope
14. ADD imm16 An An imm16 4An F7 08 An imm16 l imm16 h ADD imm24 An An imm24 An F4 644An imm24 l imm24 m imm24 h ADDC Dn Dm F2 80 Dn lt lt 2 Dm ADDNF imm8 An An imm8 An F5 0C An imm8 11 SUB Dn Dm A0 Dn lt lt 2 Dm SUB Dm An An DmAn 2 10 lt lt 2 SUB Dm An2Dm 2 00 lt lt 2 SUB Am An Am 2 50 lt lt 2 SUB imm16 Dn Dn imm16 Dn F7 1C Dn imm16 l imm16 h SUB imm24 Dn Dn imm24 Dn F4 68 Dn imm24 l imm24 m imm24 h SUB imm16 An An imm16 An F7 0C An imm16 l imm16 h SUB imm24 An An imm24 An F4 6C An imm24 l imm24 m imm24 h SUBC Dn Dm Dm Dn CF2Dm m 2 90 lt lt 2 MUL Dn Dm Dn gt gt 16 MDR 06 oe 6 E F3 40 Dn lt lt 2 Dm 12 MULU Dn Dm Dm Dn 216 MDR 50 lt lt 2 13 Notes 6 DIVU Dn Dm MDR 16 Dm Dn2Dm MDR 32 bit sign extended word data 7 24 bit sign extended word
15. Data Move From Memory To 128 Repeated Access To The Same Memory 129 Byte Access And Word 129 Byte Move From Memory 130 Zero Check Of Metrory etii diee te ted ds 130 Block MOVE M HE 131 PUSH POP ee ode lem ve en 132 PUSEUPOP Of PS restes rese eot etc rete teres 133 Zero Clear Of Registers iaie 134 Calculations With Memory 134 zl P 135 Bit Cl Geis M 136 zl cc 137 Subtract 129 entire tetendit ie tena naci 137 SION NVEMSION tatu cedet catre ces Ree eatin deans 138 Logica Single Bit Shift 138 Logical Multiple Bit Shift essent 139 amp BIESWapu ede nte det esee nin al aed 140 Decimal Conversion Of 4 Bit 141 Interrupt Disable Enable 141 PSW FlagsSelt Cleer 141 Ovetrlappi ng ITIEBImipte acce iicet tee tit 142 3 Deleted ristr ctlon aset 143 MOV MOV AmYDi An 143 Appendix
16. No changes Bytes 3 Cycles 3 F5 50 An lt lt 2 Dm 48 a Accessing to odd addresses in memory is not allowed a 48 Chapter2 Instruction Specifications zx ve e Te 77 Es MOVX Dm di6 An Operation L3 ES Dm gt mem24 An d16 Adds the value of register An and a sign extended 16 bit displacement 32768 to 32767 to obtain a pointer to memory and moves the 3 byte value of register Dm to that memory Flag Changes Size Cycles Codes 1 Accessing to odd addresses in memory is not allowed LI Bytes 4 Cycles 3 F7 60 An lt lt 2 Dm d16 1 d16 h MOVX Dm d24 An Operation Dm gt mem24 An d24 Adds the value of register An and a 24 bit displacement to obtain a pointer to memory and moves the 3 byte value of register Dm to that memory Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 4 F4 30 An lt lt 2 Dm d24 1 d24 m d24 h 1 Accessing to odd addresses in memory is not allowed MOVX 49 Chapter 2 Instruction Specifications Data move instruction Operation mem8 An gt Dm Sign extends the one byte contents of memory pointed to by register An to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes This instruction is supported by assembler the assembler generates the two instruction codes for An Dm and H Dm
17. Word accesses give smaller faster code x10 A0 DO 2 bytes 1 cycle Programming Examples General Speed Optimization Size Optimization 129 Chapter 3 Use Of Instructions 2 7 Byte Move From Memory To Register Contents D When moving bytes from memory to registers zero extending results in better code size and speed Speed Size optimization optimization Example MOVB A3 DO 2 bytes 2 cycles Zero extending gives smaller faster code MOVBU 00 1 byte 1 cycle 2 8 Zero Check Of Memory Contents Flags do not change when moving data from memory to registers To check if a Speed Size memory value is zero another instruction that does change the flags needs to be optimization optimization used In such cases CMP instructions will be faster than AND instructions Fur thermore if it does not matter whether or not the moved data in the register is valid then ADD instructions will result in smaller code size CF and ZF will reflect the results Example D Register data must be valid MOV x f000 DO 3 bytes 1 cycle AND 00 00 2 bytes 2 cycles Total 5 bytes 3 cycles CMP instruction is faster MOV 0009 00 8 bytes 1 cycle CMP 0 DO 2 bytes 1 cycle Total 5 bytes 2 cycles 0 Register data may be invalid MOV x t000 DO 3 bytes 1 cycle CMP 0 00 2 bytes 1 cycle Total 5 bytes 2 cycles ADD instruction gives smaller
18. 146 M ap teda net iter d ae dte ie na ht editt i At e eius 152 Index NNO a 158 90 Instruction Set Overview Chapter 1 Instruction Set Overview Instruction Set SSS The instruction set of the MN102L Series was basically designed for use with C compilers Preferential assignment of instructions most frequentl y used by C com pilers to single byte single cyde codes has enabled much faster execution and smaller code size Splitting the register set into four 24 bit data registers and four 24 bit address registers has allowed frequently used basic instructions such as register register calculations and register memory moves to be implemented single bytes Ex Movethe contents of the DO register to the memory address pointed to by the AO register 1 byte 1cyde Add the contents of the DO register to the contents of the D1 register 1 byte 1 cycle 2 Instruction Set Chapter 1 Instruction Set Overview Register Set The register set is divided by function into data registers for calculations and ad dress registers tor pointers This greatly contributes to improvements in instruc tion code size compression and pipeline processing parallelism When Matsushit
19. 39 25524 40 40 0000 30 4 MOV AT snm eae fere cm ns ca Ea t d a d iD ce LEG 41 MOV AN 41 MOV AM 024 AAD ERR 42 MOV 516 tacui ten e et 43 MOV Ari 3924 ino tte brc i Pr aria Prec atas 43 44 MOV 44 eM MP 45 45 MOV ERE 46 WEE e Mb 47 MOV X di6 Ain DEI rrr ee tenure taret oret un rove sca a teure tenore 47 d24 DN deerat cre e cene rastro 48 MOVX Dm AT 48 Dir di6 An uidet Rie eaa dra 49 MOVX Dry 024 Ati i cete coh entienda atn 49 MOVB AN cerea ci ke radere 50 98 X 50 MOVB 906 AT DET iiio ptt cott eiae to poe ni pert ren 51 MOVB d24 An ta te n PES bee e ERR ie 51 MOVB NE OPI MP 52 MOVB 8056 Disagree eti
20. D 3 MOVBU 08 An D 5 MOVX d8 An 7 MOVX d8 An D 4 byte instructions Byte 1 F7 Second byte UpperLower 0 1 2 3 4 5 6 7 8 9 D E F 0 AND imm16 Dn BTST imm16 Dn ADD imm16 An SUB imm16 An OR immt6 1 ADD imm16 Dn SUB imm16 Dn MOV abs16 3 MOV abs16 An 4 OR imm16 Dn CMP imm16 imm16 Dn 5 MOVBU d16 An D 6 MOVX Dm d16 An 7 MOVX 416 An 8 MOV Dm d16 9 MOVB Dm d16 An A MOV Am d16 An B MOV d16 An A MOV 416 An D D MOVB 416 An D Ver 2 0 2001 02 01 Instruction 159 Appendix 156 Instruction map Index Index ADD ADDC ADDNF AND ASR BCC BCCX BCLR BCS BCSX BEQ BEQX BGE BGEX BGT BGTX BHI BHIX BLE BLEX BLS BLSX BLT BLTX BNC 158 I ndex BNCX BNE LYDg 67 BNEX ATHEN i erm 67 BNS BP qoM 66 BNSX Delirium 66 BRA ES 69 BSET TEES 68 BTST Jur oT 70 ee P PEE 68 BVC INRA A icit tese iade 70 BVCX denen MD e 69 BVS DOM DIM E TT 71 BVSX ci te aire ntum dd in sta d s 72 Dn DE sient tici e eie un 86 86 B irmmil6 totae tte t iet tien 87 CMP 6
21. DO 8 bytes 1 cycle OR 4 DO 8 bytes 2 cycles MOVB DoO x c20 8 bytes 1 cycle Total 9 bytes 4 cycles The example below gives smaller code size 20 8 bytes 1 cycle A0 DO 1 byte 1 cycle 4 DO 8 bytes 2 cycles DO A0 1 byte 1 cycle Total 8 bytes 5 cycles Using BSET Instruction For Byte Access MOV 20 0 8 bytes 1 cycle MOV 4 DO 2 bytes 1 cycle BSET DO A0 2 bytes 5 cycles Total 7 bytes 7 cycles Programming Examples General Speed Optimization Size Optimization 135 Chapter 3 Use Of Instructions 2 15 Bit Clear Contents Normally AND instructions are used to clear bits For byte accesses the BCLR Si instruction can be used in addition to an AND instruction If the bits to be cleared Ize MUS TE all fit within a byte then a byte access will give smaller code than a word access optimization a Use the BCLR instruction to prohibit reception of bus release requests and interrupts during read modify writes Example D Word Access MOV x fc20 DO 3 bytes 1 cycle AND x ftfb DO 4 bytes 2 cycles MOV DO x fc20 3 bytes 1 cycle Total 10 bytes 4 cycles The example below gives smaller code size MOV X c20 A0 8 bytes 1 cycle MOV A0 DO 3 1 byte 1 cycle AND x iffb DO 4 bytes 2 cycles MOV 00 0 1 byte 1 cycle Total 9 bytes 5 cycles Using AND Instru
22. MULU M M M 79 159 Index NOP NOT OR ROL ROR RTI RTS SUB SUBC XOR 160 CT 118 DI 91 M 88 E 88 1777716 Dn tentent tette treten nna 89 imle PSW oi c irre 89 95 BIER 94 eens 120 C M 119 MULU XOR MN102L Series Instruction Manual April 2001 3rd Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES E U S A SALES OFFICE Panasonic Industrial Company PIC New Jersey Office 2 Panasonic Way Secaucus New Jersey 07094 Tel 201 392 6173 Fax 201 392 4652 Milpitas Office 1600 McCandless Drive Milpitas California 95035 Tel 408 945 5630 Fax 408 946 9063 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 Tel 847 468 5829 Fax 847 468 5725 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee Georgia 30174 Tel 770 338 6940 Fax 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego
23. x 7f A0 4 bytes 2 cycles Total 8 bytes 4 cycles The example below gives smaller faster code 7 00 2 bytes 1 cycle X 7f AO 2 bytes 1 cycle Total 4 bytes 2 cycles Programming Examples General Speed Optimization Size Optimization 137 Chapter 3 Use Of Instructions 2 18 Sign Inversion Contents Sign inversion is performed by a sequence of instructions Example 2 below needs two registers but it results in faster smaller code Speed Size optimization optimization Example D Use one data register NOT DO 2 bytes 2 cycles ADD 1 DO 2 bytes 1 cycle Total 4 bytes 3 cycles Use two data registers SUB D1 D1 1 byte 1 cycle SUB 00 01 1 byte 1 cycle Total 2 bytes 2 cycles 2 19 Logical Single Bit Shift Left Contents To multiply a register value by 2 or 4 or in other words to perform a logical shift left of one or two bits use the ADD instruction Speed Size optimization optimization Example x fffb PSW 4 bytes 3 cycles DO 2 bytes 2 cycles Total 6 bytes 5 cycles 00 00 1 byte 1 cycle Total 1 byte 1 cycle x fffD PSW 4 bytes 3 cycles DO 2 bytes 2 cycles x fffb PSW 4 bytes 3 cycles DO 2 bytes 2 cycles Total 12 bytes 10 cycles i 00 00 1 byte 1 cycle 00 00 1 byte 1 cycle Total 2 bytes 2 cycles 138 Programming Examples General Speed Optimization Size Opt
24. 0 then PC 2 d8 label IF CF ZF 1 then PC 2 If both CF and ZF are 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CF is 1 or if ZF is 1 then execution will continue with the Operation instruction following the BHI instruction For example the BHI instruction will branch when the previous CMP in struction encounters src lt dest as a un signed 16 bit value Flag Changes Size Cycles Codes Cycles 2 branch Cycle 1 non branch E5 d8 Bcc 103 Chapter2 Instruction Specifications BVC Operation label IF VF 0 then PC 3 d8 label IF VF 1 then PC 3 If VF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VF is 1 then execution will continue with the instruction following the BVC instruction Flag Changes Size Cycles Codes No change Operation 104 Bcc BVS label Flag Changes Size Cycles Codes No change Bytes 3 Cycles 3 branch Cycles 2 non branch F5 FD d8 Bytes 3 Cycles 3 branch Cycles 2 non branch F5 FC d8 IF VF 1 then PC 3 d8 label IF VF 0 then PC 3 If VF is 1 then branches to the address indicated by label The branch range is from 128
25. 1 The 8 bit immediate value imm8 will be sign extended to 24 bits MOV imm16 Dn Flag Changes Size Cycles Codes 1 The 16 bit immediate value imm16 will be sign extended to 24 bits a imms Dn Sign extends the 8 bit immediate value imm8 to 24 bits and moves it to register Dn imm16 Dn Sign extends the 16 bit immediate value imm16 to 24 bits and moves it to register Dn Bytes 3 Cycle 1 F8 Dn imm16 1 imm16 h 44 MOV Chapter2 Instruction Specifications Operation imm24 Dn Moves the 24 bit immediate value imm24 to register Dn Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 70 Dn imm24 1 imm24 m imm24 h MOV imm16 An Flag Changes Size Cycles Codes 1 The 16 bit immediate value imm16 will be zero extended to 24 bits a imm16 gt Zero extends the 16 bit immediate value imm16 to 24 bits and moves it to register An Bytes 3 Cycle 1 DC An imm16 l imm16 h MOV 45 Chapter2 Instruction Specifications MOV imm24 Flag Changes Size Cycles Codes imm24 An Moves the 24 bit immediate value imm24 to register An Bytes 5 Cycles 3 F4 74 imm24 l imm24 m imm24 h 46 MOV Chapter2 Instruction Specifications M O X Data move instruction MOVX 48 An Dm Operation 24 An d8 Dm Sign extends the 8 bit displac
26. 424 An Dm mem8 An d24 gt Dm Bytes 4 Cycles 2 F7 50 An lt lt 2 Dm 416 1 d16 h Operation Adds the 24 bit displacement to register An to obtain a pointer to memory zero extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 90 An lt lt 2 Dm d24 1 d24 m d24 h 58 MOVBU Chapter 2 Instruction Specifications MOVBU Dm Operation 8 0 Dm Adds register Di to register An to obtain a pointer to memory zero extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 80 Di lt lt 4 An lt lt 2 Dm MOVBU abs16 Dn Operation mem8 abs16 Dn Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory zero extends the contents of that memory 1 byte to 24 bits and moves the result to register Dn Flag Changes Size Cycles Codes No changes Bytes 3 Cycle 1 CC Dn abs16 1 abs16 h MOVBU 59 Chapter2 Instruction Specifications MOVBU abs24 Dn Operation mem8 abs24 Zero extends the contents of 24 bits to obtain an absolute address pointing to memory 1 byte to 24 bits and moves the result to register Dn Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4
27. 7 111 Level 0 is the highest interrupt level IE Interrupt Enable The interrupt enable bit enables reception of interrupts when set to 1 Note that non maskable interrupts will always be received regardless of the state of IE S1 SO Software Bit The software bits are used by the operating system as software control bits a The value of PSW will be x 0000 when started after a reset m 6 Register Set Chapter 1 Instruction Set Overview Instruction Functions MEX X The instructions of this series can be divided by function into five categories data move instructions arithmetic calculation instructions logical calculation instructions bit manipulation instructions branch instructions Data Move Instructions The data move instructions are as follows MOV Move Data M ove Pointer Data MOVX Move Pointer Data MOVB Move Byte MOVBU Move Byte Unsigned EXT Extention EXTX Extension Word Data to Pointer Data EXTXU Extension Word Data Unsigned to Pointer Data EXTXB Extension Byte Data to Pointer Data EXTXBU Extension Byte Data Unsigned to Pointer Data MOV instructions move 16 bit data in data registers and 24 bit pointer data in address registers An MOV X instructions move 24 bit pointer data in data registers Dn MOVB and MOV BU instructions move byte data between memory and data regis ters The MOVB instruction sign extends 8 bit data in
28. C8 Dn 24 1 abs 24 m abs24 h 60 MOVBU Chapter2 Instruction Specifications E X T Data move instruction EXT Operation IF Dn bp15 0 then 0000 IF Dn bp15 1 then x FFFF Sign extends the lower 16 bits of register Dn 2 bytes to 32 bits and moves the 16 bit extension to register MDR The contents of Dn are not changed Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 3 1 0 lt lt 2 61 Chapter2 Instruction Specifications E X T X Data move instruction Operation IF Dn bp15 0 then Dn amp x O0FFFF Dn IF Dn bp15 1 then Dn I x FF0000 gt Dn Sign extends the lower 16 bits of register Dn 2 bytes to 24 bits and stores the result in register Dn Flag Changes Size Cycles Codes 62 EXTX Chapter2 Instruction Specifications E X T X U Data move instruction Flag Changes Size Cycles Codes amp Zero extends the lower 16 bits of register Dn 2 bytes to 24 bits and stores the result in register Dn 63 Chapter2 Instruction Specifications E X X Data move instruction Operation IF Dn bp7 0 then Dn amp x 0000FF Dn IF Dn bp7 1 then Dn I 00 Sign extends the lower 8 bits of register Dn 1 byte to 24 bits and stores the result in register Dn Flag Changes Size Cycles Codes 64 Chap
29. California 92123 Tel 619 503 2940 Fax 619 715 5545 CANADA SALES OFFICE Panasonic Canada Inc PCI 5700 Ambler Drive Mississauga Ontario LAW 2T3 Tel 905 624 5010 Fax 905 624 9880 GERMANY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Munich Office Hans Pinsel Strasse 2 85540 Haar Tel 89 46159 156 Fax 89 46159 195 B U K SALES OFFICE Panasonic Industrial Europe Ltd PIEL Electric component Group Willoughby Road Bracknell Berkshire RG12 8FP Tel 1344 85 3773 Fax 1344 85 3853 FRANCE SALES OFFICE Panasonic Industrial Europe G m b H PIEG Paris Office 270 Avenue de President Wilson 93218 La Plaine Saint Denis Cedex Tel 14946 4413 Fax 14946 0007 B ITALY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Milano Office Via Lucini N19 20125 Milano Tel 2678 8266 Fax 2668 8207 TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6th Floor Tai Ping amp First Building No 550 Sec 4 Chung Hsiao E Rd Taipei 10516 Tel 2 2757 1900 Fax 2 2757 1906 Kaohsiung Office 6th Floor Hsien 1st Road Kaohsiung Tel 7 223 5815 Fax 7 224 8362 Matsushita Electric Industrial Co Ltd 2001 HONG KONG SALES OFFICE Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11 F Great Eagle Centre 23 Harbour Road Wanchai Hong Kong Tel 2529 7322 Fax 2865 3697 SINGAPORE SALES OFFICE Panasonic Semiconductor of South As
30. ZF Set if the lower 16 bits of the result are 0 reset otherwise imm16 PSW Operation PSW amp imm16 PSW Performs a bitwise logical AND of the 16 bit immediate value imm16 and the PSW and stores the result in the PSW The lower 8 bits will be stored in the PSW flags VX bit 7 CX bit 6 NX bit 5 ZX bit 4 VF bit 3 CF bit 2 NF bit 1 and ZF bit 0 The PSW flags 51 SO IE and IM27IMO will also be changed Flag Changes Size Cycles Codes Will be set to bit 7 of the result Bytes 4 Will be set to bit 6 of the result Will be set to bit 5 of the result Cycles 3 Will be set to bit 4 of the result 7 10 1 16 1 1 16 Will be set to bit 3 of the result Will be set to bit 2 of the result Will be set to bit 1 of the result Will be set to bit O of the result AND 87 Chapter2 Instruction Specifications Logical Calculation Instructions OR Dn Dm Operation Dm Dn amp x OOFFFF gt Dm Performs a bitwise logical OR of the lower 16 bits or registers Dm and Dn and stores the result in the lower 16 bits of register Dm The upper 8 bits of register Dm will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 2 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F3 10 Dn lt lt 2 Dm ZF Set if the lower 16 bits of the result are 0 reset otherwise OR imm8 Dn Operation Dn I imm8 Dn Performs a
31. reset otherwise F2 60 lt lt 2 82 CMP Chapter2 Instruction Specifications Operation Dn imm8 Sign extends the 8 bit immediate value imm8 to 24 bits subtracts it from register Dn but does not store the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated to the MSB reset otherwise Cycle 1 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise D8 Dn imm8 1 8 bit immediate value imm8 will be sign extended to 24 bits 16 Operation Dn imm16 Sign extends the 16 bit immediate value imm16 to 24 bits subtracts it from register Dn but does not store the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 4 Set if a borrow is generated to the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated
32. 1 Accessing to odd addresses memory is not allowed a Po ox wx ve Te Tw T7 MOV abs16 Operation mem16 abs16 gt Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory then sign extends con tents of that memory two bytes to 24 bits and moves that value to register Dn Flag Changes Size Cycles Codes No changes Bytes 3 Cycle 1 C8 Dn abs16 1 abs16 h 1 Accessing to odd addresses in memory is not allowed 32 MOV Chapter2 Instruction Specifications MOV abs24 Dn Operation mem16 abs24 24 bits abs24 to obtain an absolute address pointing to memory then sign extends the contents of that memory two bytes to 24 bits and moves that value to register Dn Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 0 abs24 1 abs24 m abs24 h 1 Accessing to odd addresses in memory is not allowed Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 70 An lt lt 2 Am 00 mem24 An Moves the value in memory three bytes pointed to by register An to register Am Accessing to odd addresses in memory is not allowed This instruction is supported by the assembler The assembler generates the instruction code for MOV d8 An Am 48 0 Mov 33 Chapter2 Instruction Specifications MOV d8 An Am O
33. 10 Instruction Functions Chapter 1 Instruction Set Overview Memory Space ROM RAM SSe BH SET The memory space of this series can be up to 16 Mbytes Thereis no distinction between ROM space and RAM space so table data can be referenced in programs with data move instructions M OV instructions Therefore all addressing modes can be used to access table data enabling more efficient programming x 000000 i 008000 Can made i m x 080000 92 16M bytes en be made gi 160 496K bytes intemal ROM XFFFFFF M Space ROM RAM 11 Chapter 1 Instruction 56 Overview 12 Addressing Modes Addressing Modes ILS There are six addressing modes addressing modes that can be used with each instruction are fixed Register direct addressing Immediate addressi ng Register indirect addressing Register relative indirect addressing Absolute addressing Indexed register indirect addressing The addressing modes provided the six types most frequently used by C compilers Data move instructions in particular can use all addressing modes When moving data to or from memory four addressing modes can be used register indirect register relative indirect absolute and indexed register indirect The indexed register indirect addressing mode allows array dat
34. 21 Instruction Execution Time 2 22 Chapter2 Instruction Specifications Symbol Deri MN ONS 222 nr RT 24 Data Move Instructions MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV DIAN lm 26 Bop 26 27 AN 27 28 28 MOR 29 29 30 98 Am DE iita ctc ett a ed cec PE Ce ha e Da CARO Ead 30 CLG AT DM Ea nva 31 31 32 AMOS LG RE 32 coepi 33 A ATIS eret datis 33 dB ATI tere De trend rd dan 34 dI6 ATL ius iri eerie cerca dace Fer Tad Dni 34 RAAM ediscere ere jene or EN Dr rk 35 0516 36 S24 AN 36 DEDE TE 37 08 AM 37 COLGAN ERAN PEERS 38 Dri AAT a 38 OMADA M iit intet e a 39 Bac ocilo
35. 71 ADDNF ATL iieri heiter rere terrier ten einen di 72 SUB iere re REPRE 73 SUB i trei te eie erra deus 73 SUB AR DM PU 74 5 e aaae 74 SUB 16 0 iiec doter 75 SUB 24 Dni cesse eerte 75 SUB 76 SUB IMMA 76 SUBGC 77 MUL 78 MULU E 79 D 000 50 000 60 Di 81 ETE 81 DIT icc e RE Re 82 82 CMP SIEGE 83 DEL ai etiem 83 CMP Mt dentes tert incu fer nne tnra ta eee tee re nct 84 16 84 AD i 85 ABI 86 86 AND TMT sD 87 AND 16 iater eni niet ata atti 87 DN DM 88 IMME caeco rire ree
36. A0 Parameters MOV dist A3 A1 Norm_end SUB 00 00 Postprocessing MOV push 1 1 MOV push A2 A3 A2 MOVX push 02 02 MOVX push D3 A3 D3 ADD work size A3 RTS Minimum Knowledge Required 125 Chapter Use Of Instructions Programming Examples General Speed Optimization Size Optimization 2 1 Register Initialization Contents registers are undefined after a reset start Register initialization must be per Precaution formed first Especially do not forget to set the stack pointer A3 Example Clear all registers to 0 and set the stack pointer to label stack SUB 00 00 Clear DO MOV 00 01 00 02 MOV 00 03 00 DO A1 MOV DO A2 MOV a stack A3 Set to initial value of stack pointer 2 2 VO Access TELAM ICE CR E CC ccc IM RAV Contents MOV instructions MOVB instructions and MOVBU instructions can be used for input output operations Precaution 1 D Output from Port 1 MOVB DO piout Input from Port 2 MOVBU p2in DO 126 Programming Examples General Speed Optimization Size Optimization Chapter 3 Use Of Instructions 2 3 Storing Immediate Data In Memory Contents To store an immediate value in memory first store the immediate value in a reg Speed Size optimization optimization ister and then move it to memory with a MOV instruction
37. Am MOV Am Di An The instruction above has been removed from the instruction set currently and it is not available to use You are required to change the program in case of using the instruction E Instruction replacement example Note Flags are chnaged as a result of arithmetic operations mov Dn An Am gt add Dn An mov Am Dn An gt add Dn An mov Am mov Am An sub Dn An sub Dn An Programming Examples General Speed Optimization SizeOptimizaion 143 Chapter 3 Use Of Instructions 144 Programming Examples General Speed Optimization Size Optimization Appendix MN102L SERIES INSTRUCTION SET Instruction Mnemonic Operation MOV Dm An Dm An F2 30 Dm lt lt 2 An MOV An Dm An Dm 2 0 lt lt 2 MOV Dn Dm 80 Dn lt lt 2 Dm MOV An Am An Am 2 70 lt lt 2 MOV PSW Dn PSW Dn F3 F0 Dn MOV Dn PSW Dn PSW F3 D0 Dn lt lt 2 MOV MDR Dn MDR Dn F3 E0 Dn MOV Dn MDR Dn MDR F3 C0 Dn lt lt 2 MOV An Dm mem16 An 2Dm 20 lt lt 2 48 16 8 60 An lt lt 2 Dm d8 MOV d16 An Dm 16 916 F7 C0 An lt lt 2 Dm d16 I d16 h MOV d24 An Dm 16 924 F4 80 An lt lt 2 Dm d24 d24 m d24 h MOV Di An Dm mem16 An Di Dm F1 40 Di lt lt 4 An lt lt 2 Dm MOV abs16 Dn mem16 abs16 Dn C
38. An Dm mem8 An 5Dm 30 lt lt 2 MOVBU d8 An Dm mem8 An d8 5Dm F5 30 An lt lt 2 Dm d8 MOVBU d16 An Dm meme8 An d16 5Dm F7 50 An lt lt 2 Dm d16 l d16 h MOVBU d24 An Dm F4 90 An lt lt 2 Dm d24 d24 m d24 h mem8 An Di 7 Dm F0 80 Di lt lt 4 An lt lt 2 Dm MOVBU abs16 Dn 8 24 16 CC Dn abs16 l abs16 h MOVBU Di An D MOVBU abs24 Dn mem8 abs24 Dn F4 C8 Dn abs24 l abs24 m abs24 h EXT Dn IF Dn bp15 0 0000 IF Dn bp15 1 x FFFF MDR como ROJO 1 0 lt lt 2 6 IF Dn bp15 0 Dn amp x 00FFFF Dn Dn bp15 1 Dn x FF0000 Dn EXTXU Dn Dn amp x 00FFFF gt Dn EXTXB Dn IF Dn bp7 0 Dn amp x 0000FF Dn Dn bp7 1 Dn x FFFF00 5 Dn EXTXBU EXTXBU Dn Dn amp x 0000FF Dn BC Dn ADD ADD Dn Dm 90 Dn lt lt 2 Dm ADD Dm An F2 00 Dm lt lt 2 An ADD An Dm Dm An Dm F2 C0 An lt lt 2 Dm ADD An Am Am An7Am F2 40 An lt lt 2 Am ADD imm8 Dn Dn imm8 Dn D4 Dn imm8s ADD imm16 Dn Dn imm16 Dn F7 18 Dn imm16 l imm16 h ADD imm24 Dn Dn imm24 Dn F4 60 Dn imm24 l imm24 m imm24 h ADD imm8 An An imm8 An DO An imm8
39. Chapter 3 Use Of Instructions Minimum Knowledge Required Dee ee RPG A m O0 O0 Word Accesses To Odd Addresses Contents Word accesses and poi nter accesses to odd addresses cannot be performed The stack pointer also should not hold an odd address If the value of is odd then JSR RTS and similar instructions that use the stack area will not operate correctly By restricting word accesses and pointer accesses to odd addresses the MN102 designs possibly increase RAM size requirements but are able to make faster accesses Example Word Accesses MOV x f001 DO address not allowed Code as follows MOV x f000 DO Stack Pointer Operation ADD 1 A3 Odd address not allowed 4 Code as follows ADD 2 43 Stack Pointer Operation ADD LA3 Odd address not allowed 1 Code as follows ADD 2 Minimum K nowledge Required 123 Chapter Use Of Instructions 124 Precaution Minimum Knowledge Required 1 2 Increment Decrement Of Address Registers Contents Address registers are incremented and decremented by ADD and SUB instruc tions but the PSW flags will change according to the results To use PSW flags set according to the results of a subroutine after returning from the subroutine use the ADDNE instruction which does not change PSW flags to adjust the stack pointer when returning f
40. IMO will also be changed Flag Changes Size Cycles Codes Will be set to bit 7 of the result Bytes 4 Will be set to bit 6 of the result Will be set to bit 5 of the result Cycles 3 Will be set to bit 4 of the result Will be set to bit 3 of the result F7 14 imm16 1 imm16 h Will be set to bit 2 of the result Will be set to bit 1 of the result Will be set to bit O of the result 89 Chapter2 Instruction Specifications Logical Calculation Instructions Operation Dm x O0FFFF amp Dn Dm Performs a bitwise logical XOR of the lower 16 bits or registers Dm and Dn and stores the result in the lower 16 bits of register Dm The upper 8 bits of register Dm will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 2 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise 20 Dn lt lt 2 Dm ZF Set if the lower 16 bits of the result are 0 reset otherwise XOR imm 16 Dn Operation Dn imm16 Dn Performs a bitwise logical XOR of the lower 16 bits or registers Dn and the immediate value imm16 and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 4 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F7 4C Dn imm16 l imm16 h ZF Set if the lower 1
41. SUB Dm An 2 CMP Dm An 3 MOV Dm An 4 ADD An Am 5 SUB An Am 6 CMP An Am 7 MOV An Am 8 ADDC Dn Dm 9 SUBC Dn Dm ADD An Dm D SUB An Dm E CMP An Dm F MOV An Dm Instruction 153 Appendix 2 byte instructions Byte 1 F3 Second byte Upper Lower 0 1 2 3 5 6 9 A D E F 0 AND Dn Dm 1 OR Dn Dm 2 XOR Dn Dm 3 ROL Dn 4 MUL Dn Dm 5 MULU Dn Dm 6 DIVU Dn Dm 7 8 9 CMP Dn Dm A B C D E MOV MDR Dn F MOV PSW Dn 5 byte instructions Byte 1 F4 Second byte Upper Lower 0 1 2 3 0 MOV Dnm d24 An 1 MOV Am d24 An 2 MOVB Dnm d24 An 3 MOVX Dm d24 An 4 MOV Dn abs24 MOVB Dn abs24 5 MOV An abs24 6 ADD imm24 Dn ADD imm24 SUB imm24 Dn SUB imm24 7 MOV imm24 Dn MOV imm24 CMP imm24 CMP 24 An 8 MOV d24 An 9 MOVBU d24 An D A MOVB 024 An D B MOVX d24 An D MOV abs24 Dn MOVB abs24 Dn MOVBU abs24 Dn D MOV abs24 An JMP JSR E tabel24 label24 F MOV 924 154 Instruction map Appendix 3 byte instructions Byte 1 F5 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B D E F 0 AND imm8 Dn BTST imm8 Dn OR imma ADDNF imm8 1 MOVB 98 2 98 An
42. Set if a borrow is generated from the MSB reset otherwise Set if the MSB of the result is 1 reset otherwise Cycle 1 Set if the result is 0 reset otherwise A0 Dn lt lt 2 Dm Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise Operation An Dm An Subtracts the value of register Dm from the value of register An and stores the result in register An Size Cycles Codes 22 AgChangs Changes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise pem Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 10 Dn lt lt 2 An SUB 73 Chapter2 Instruction Specifications Dm An gt Dm Subtracts the value of register An from the value of register Dm and stores the result in register Dm Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow
43. When storing a 24 bit pointer immediate value in memory code size and speed is better if the move is through an address register than if it is through a data register Example D Store an immediate value in memory MOV x1234 DO 8 bytes 1 cycle MOV DO A1 1 byte 1 cycle Total 4 bytes 2 cycles Store a pointer immediate value in memory MOV x 123456 DO 5 bytes 3 cycles MOVX DO 0 A1 3 bytes 3 cycles Total 8 bytes 6 cycles Moving through an address register gives faster smaller code MOV x 123456 A0 5 bytes 3 cycles MOV AO A1 2 bytes 2 cycles Total 7 bytes 5 cycles Programming Examples General Speed Optimization Size Optimization 127 Chapter 3 Use Of Instructions 2 4 Data Move From Memory To Memory 5 5 OA lJ Contents D Data moves from memory to memory are performed through a register When 7 moving 24 bit pointer data code size and speed is better if the move is through an Speed Size for Re HORS address register than if it is through a data register optimization optimization Example D Data Moves MOV 000 00 8 bytes 1 cycle MOV DO x f002 3 bytes 1 cycle Total 6 bytes 2 cycles MOV 000 0 3 bytes 1 cycle A0 DO 1 byte 1 cycle MOV D0 2 A0 2 bytes 1 cycle Total 6 bytes 3 cycles Pointer Data Moves MOV 10007 0 4 bytes 3 cycles MOV AO x f004 4 bytes 3
44. bp Isb msb amp l lt lt VX CX NX ZX VF CF NF ZF temp E yis OP EX Operand Extensions 0 Zero extension S Sign extension Not applicable Cycle Minimum cycle count is shown Units machine cycles a b acycles if branch taken b cycles if branch not taken W Notes Flag Ver 2 0 2001 02 01 Data register Address register Multiply Divide Register Processor Status Word Program Counter Constant Displacement Absolute address 8 bit memory data which is determined by the address inside parentheses 16 bit memory data which is determined by the address inside parentheses 24 bit memory data which is determined by the address inside parentheses Bit specification Logical AND logical OR exclusive OR Bit inversion bit shift Extended overflow flag carry flag negative flag zero flag 24 bit data Overflow flag carry flag negative flag zero flag 16 bit data CPU internal temporary register Substitution reflects calculation results Code Size Unit bytes No change 0 Always 0 1 Always 1 Undefined W Machine Code indicates a delimiter between bytes lt lt 2 indicates a 2 bit shift Dn Dm Di An Am Register numbers DO 00 AO 00 D1 01 Al 01 D2 10 A2 10 D3 11 A3 11 16 bit or 24 bit access instruction must not access odd memory addresses 8 displacements 98 and 16 bit di
45. bytes after If ZF is 0 then execution will continue with the instruction following the BEQ instruction For example the BEQ instruction will branch when the previous CMP instruction encounters a 16 bit source equal to a 16 bit destination Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch E8 d8 BNE label IF ZF 0 then PC 2 d8 label gt IF ZF 1 then PC 2 PC Operation If ZF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If ZF is 1 then execution will continue with the instruction following the BNE instruction For example the BNE instruction will branch when the previous CMP instruction encounters a 16 bit source not equal to a 16 bit destination Flag Changes Size Cycles Codes Cycles 2 branch Cycle 1 non branch E9 d8 99 Chapter2 Instruction Specifications BLT Operation IF VF 1 then PC 2 d8 label IF VF NF 0 then 2 If VF is 0 and NF is 1 or if VF is 1 and NF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both VF and NF are 0 or if both VF and NF are 1 then execution will continue with the instruction following the BLT instruction For exam
46. code MOV x f000 DO 8 bytes 1 cycle ADD 00 00 1 byte 1 cycle Total 4 bytes 2 cycles 130 Programming Examples General Speed Optimization Size Optimization information Chapter 3 Use Of Instructions 2 9 Block Move QAO Block moves are performed by a sequence of several instructions There are many examples trading off speed size and numbers of registers used but use QD below as a typical example Example Move 16 bytes from x f000 x fOOf to x f100 x f10f D Use two data registers and two address registers DO D1 AO A1 MOV 00 0 8 bytes 1 cycle MOV 100 1 8 bytes 1 cycle MOV 8 01 2 bytes 1 cycle Sub total 8 bytes 3 cycles loop MOV 0 00 1 byte 1 cycle MOV DO A1 1 byte 1 cycle ADD2 A0 2 bytes 1 cycle ADD2 A1 2 bytes 1 cycle ADD 1 D1 2 bytes 1 cycle BNE loop 2 bytes 2 1 cycle Sub total 10 bytes 7 6 cycles Total 18 bytes 59 cycles Use three data registers and one address register DO D1 D2 0 MOV x f000 A0 8 bytes 1 cycle MOV x 100 D2 8 bytes 1 cycle MOV x 8 D1 2 bytes 1 cycle Sub total 8 bytes 3 cycles loop MOV A0 DO 1 byte 1 cycle MOV 00 02 0 2 bytes 2 cycles ADD2 A0 2 bytes 1 cycle ADD 1 D1 2 bytes 1 cycle BNE loop 2 bytes 2 1 cycle Sub total
47. d8 109 Chapter2 Instruction Specifications BCSX label Operation IF CX 1 then PC 3 d8 label IF CX 0 then PC 3 PC If CX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CX is 0 then execution will continue with the instruction following the BCSX instruction For example the BCSX instruction will branch when the previ ous CMP instruction encounters src gt dest as a un signed 24 bit value Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E4 98 BLSX label Operation IF CX I ZX 1 then PC 3 d8 label IF CX 1 ZX 0 then PC 3 PC If CX is 1 or ZX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both CX and ZX are 0 then execution will continue with the instruction following the BLSX instruction For example the BLSX instruction will branch when the previous CMP instruction encounters src dest as a un signed 24 bit value Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E7 d8 110 Operation Chapter2 Instruction Specifications label IF CX 0 then PC 3 d8 label IF CX 1 then
48. memory to 24 bits when moving from merrory to a register and moves the lower 8 bits of data in a register when moving fromthe register to memory The MOV BU instruction zero extends 8 bit data in merrory to 24 bits when moving EXT instructions sign extend 16 bit data in data registers Dn to 32 bits The upper 16 bits that are sign part are moved to where they will be used for 32 bit calculations EXTX instructions sign extend 16 bit data in data registers Dn to 24 bits EXTXU instructions zero extend 16 bit data in data registers Dn to 24 bits EXTXB instructions sign extend 8 bit data in data registers Dn to 24 bits EXTXBU instructions zero extend 8 bit data in data registers Dn to 24 bits Instruction Funcions 7 Chapter 1 Instruction Set Overview 3 2 Arithmetic Calculation Instructions The arithmetic calculation instructions are as follows ADD Addition ADDC Addition with Carry ADDNF Addition with Non Flag Change SUB Subtract SUBC Subtract with Borrow MUL Multiply MULU Multiply Unsigned DIVU Divide Unsigned CMP Compare Arithmetic calculations include addition subtraction multiplication division and comparison Multiplication can be signed or unsigned 3 3 Logical Calculation Instructions The logical calculation instructions are as follows AND And OR Or XOR Exclusive Or NOT Complement ASR Arithmetical Shift Right LSR Logical Shift Right ROR Rotate Right with Carry ROL Rotate Left wi
49. moves the lower 8 bits of register Dm one byte to that memory Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 2 F5 10 An lt lt 2 Dm 48 MOVB Dm 416 Operation Dm mem8 An d16 Sign extends the 16 bit displacement 32768 to 32767 adds it to register An to obtain a pointer to memory and moves the lower 8 bits of register Dm one byte to that memory Flag Changes Size Cycles Codes No changes Bytes 4 Cycles 2 F7 90 An lt lt 2 Dm 416 1 d16 h 54 MOVB Chapter2 Instruction Specifications MOVB Dm d24 An Operation Dm mem8 An d24 Adds the 24 bit displacement and register An to obtain a pointer to memory and moves the lower 8 bits of register Dm one byte to that memory Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 20 An lt lt 2 Dm 424 1 d24 m d24 h MOVB Di Operation Dm mem8 An Di Adds register An and register Di to obtain a pointer to memory and moves the lower 8 bits of register Dm one byte to that memory Flag Changes Size Cycles Codes Bytes 2 Cycles 2 No changes FO 0 lt lt 4 lt lt 2 55 Chapter2 Instruction Specifications MOVB abs16 Operation Dn gt 8 16 Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory and moves the lower 8 bits of registe
50. reset otherwise Bytes 4 Set if a borrow is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise TRE Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F7 1C Dn imm16 1 imm16 h 1 The 16 bit immediate value imm16 will sign extended to 24 bits SUB imm24 Dn Operation Dn imm24 Dn Subtracts the 24 bit immediate value from the value of register Dn and stores the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 5 Set if a borrow is generated from the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise F4 68 0 imm24 1 imm24 m Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise imm24 h Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise suB 75 Chapter2 Instruction Specifications SUB 16 Operation An imm16 An Sign extends the 16 bit immediate value imm16 to 24 bit
51. ritenere rin 52 MOVB 6524 ETE 53 MOVB Dry AT uiii aecenas ttt incen eel due Pee Ta kn 53 MOVB An e rci alata dst 54 MOVB 16 AM 54 MOVB 024 55 MOVB Mu Wale aie nia di ea 55 MOVB Dti 3916 56 MOVB S24 fore ite err Rin rp e eerie 56 MOVBU MD Em 57 MOVBU 08 An i 57 MOVBU 916 AD DET eicere i 58 MOVBU 924 An DIO 58 DI AT crest cad avis ccna 59 oculo MID jT 59 MOV BU t 60 EXT M M 61 PME 62 PA REN 63 pp 64 65 ADD DN 66 ADD eae 66 ADD M 67 ADD AD AUR inier 67 DIP 68 ADD NMG DM 68 ADD E 69 ADD aper dcn dni Bre dx 69 ADD pii 70 ADD IMEA ATi a a dg e 70 ADDG EE
52. signed src lt dest lower 16 bits signed src gt dest lower 16 bits unsigned src2dest lower 16 bits unsigned src lt dest lower 16 bits unsigned src dest lower 16 bits unsigned 0 1 0 1 src dest 24 bits srczdest 24 bits F5 E9 d8 Instruction set 149 Appendix Instruction Mnemonic BLTX label Operation IF VX NX 1 PC 3 d8 label 2 PC IF VX NX 0 F5 E0 d8 Machine Code BLEX label IF VX NX IZX 1 PC 3 d8 label 2 PC IF VXANX ZX 0 PC 3 PC F5 E3 d8 label IF VX NX 0 PC 3 d8 label PC IF VX NX 1 F5 E2 d8 BGTX label IF VXANX ZX 0 PC 3 d8 label PC IF VX NX IZX 1 F5 E1 d8 BCSX label IF 1 PC 3 d8 label PC IF CX 0 PC 3 gt PC 5 4 08 BLSX label IF 2 PC 3 d8 label 2 PC IF CX ZX 0 PC 3 PC F5 E7 d8 BCCX label IF 0 3 98 gt IF 1 F5 E6 d8 BHIX label IF 2 0 PC 3 d8 label PC IF PC 3 PC F5 E5 d8 label IF VX 0 PC 3 d8 label PC IF VX 1 PC 3 gt PC F5 EC d8 BVSX label IF VX 1 PC 3 d8 label gt PC IF VX 0 PC 3 gt PC F5 ED d8 BNCX label IF 0 PC 3 d8 label PC IF NX 1 F5 EE d8 BNSX label IF 1 3 98
53. src dest lower 16 bits 18 srczdest lower 16 bits 19 src gt dest lower 16 bits signed 148 Instruction set Operation BLE label VF NF ZF 1 2 46 VFANF ZF 0 2 Machine Code BGE label 0 PC 2 d8 label PC 1 2 label VF NF ZF 0 PC 2 d8 label PC VFANF ZF 1 2 BCS label F CF 1 PC 24d8 label 2PC F CF 0 2 BLS label CF ZF 1 PC 2 d8 label PC CFIZF 0 2 label F CF 0 PC 24d8 label 2PC F CF 1 2 BHI label CF ZF 0 PC 24d8 label 2PC F CFIZF 1 2 VF 0 PC 3 d8 label PC F VF 1 PC 3 PC F5 FC d8 BVS label VF 1 PC 3 d8 label PC F VF 0 F5 FD d8 BNC label F NF 0 PC 3 d8 label 2 PC NF 1 PC 3 PC F5 FE d8 BNS label 1 PC 3 d8 label 2 PC F NF 0 F5 FF d8 BRA label PC 2 d8 label PC EA d8 BEQX label IF ZX 1 PC 3 d8 label 2 PC IF ZX 0 5 8 08 Notes 20 21 22 23 24 25 26 27 28 29 30 31 32 BNEX label IF ZX 0 PC 3 d8 label PC IF ZX 1 src2dest lower 16 bits signed src lt dest lower 16 bits
54. to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F7 48 Dn imm16 1 imm16 h 1 The 16 bit immediate value imm16 will be sign extended to 24 bits LI 83 Chapter2 Instruction Specifications 24 Dn Operation Dn imm24 Subtracts the 24 bit immediate value imm24 from register Dn but does not store the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 5 Set if a borrow is generated to the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise FA 78 Dn imm24 1 imm24 m Set if result taken as a 16 bit signed value overflows reset otherwise imm24 h Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise imm16 An Operation An imm16 Zero extends the 16 bit immediate value imm16 to 24 bits subtracts it from register An but does not store the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 3 Set if a borrow is generated to the MSB reset otherwise Cycle 1 Set if the MSB of the result is 1 reset oth
55. 0 lt lt 2 48 1 Accessing to odd addresses memory is not allowed 20 Chapter2 Instruction Specifications v ox wx 2 ve per P MOV 916 Dm Operation mem16 An d16 Adds the value of register An and a sign extended 16 bit displacement 32768 to 32767 to obtain a pointer to memory then sign extends the contents of that memory two bytes to 24 bits and moves that value to register Dm Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Bytes 4 Cycles 2 F7 CO An lt lt 2 Dm 116 1 d16 h MOV d24 An Dm Operation mem16 An d24 gt Dm Adds the value of register An and a 24 bit displacement to obtain a pointer to memory then sign extends the contents of that memory two bytes to 24 bits and moves that value to register Dm Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Bytes 5 Cycles 3 F4 80 An lt lt 2 Dm 424 1 d24 m d24 h MOV 31 Chapter 2 Instruction Specifications Operation mem16 An Di gt Adds the values of registers An and Di to obtain a pointer to memory then sign extends the contents of that memory two bytes to 24 bits and moves that value to register Dm Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 F1 40 Di lt lt 4 An lt lt 2 Dm
56. 0 ZF Set if the lower 16 bits of the result are reset otherwise F5 04 imm8 1 The 8 bit immediate value imm8 will be zero extended to 24 bits a BTST imm16 Dn Operation Dn amp imm16 PSW Zero extends the 16 bit immediate value imm16 to 24 bits performs a logical AND with the value of register Dn and reflects the result in the PSW flags Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 4 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise ZF Set if the lower 16 bits of the result are 0 reset otherwise F7 044Dn imm16 l imm16 h 1 The16 bit immediate value imm16 will be zero extended to 24 bits a 96 BTST Chapter2 Instruction Specifications S E T Bit Manipulation Instructions BSET mem8 An amp Dm PSW mem8 An Dm gt mem8 An Operation Zero extends the 1 byte contents of memory pointed to by register An to 24 bits performs a logical AND with the value of register Dm and reflects the result in the PSW flags Also performs a logical OR of the zero extended value and the value of register Dm and stores the result in the lower 8 bits in the memory pointed to by register An This instruction does not change the value of register Dm Flag Changes Size Cycles Codes VX CX NX ZX No change Bytes 2 VF Always 0 CF Always 0 Cycles 5 2 20 An l
57. 0 Dn Dn PSW Moves the lower 16 bits of register Dn to the PSW The change affects not only the PSW flags VX CX NX ZX VF CF NF and ZF but also affects S1 SO IE and 271 0 Size Cycles Codes Bytes 2 Cycles 3 2 egCchnges Changes D0 Dn lt lt 2 28 MOV Chapter2 Instruction Specifications Dn Zero extends the value of to 24 bits and moves that value to register Dn Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 E0 Dn No changes Dn gt Moves the lower 16 bits of register Dn to the MDR Size Cycles Codes Bytes 2 Cycles 2 0 lt lt 2 Mov 29 Chapter2 Instruction Specifications Operation mem16 An Dm Sign extends the 2 byte value in memory pointed to by register An to 24 bits and moves that value to register Dm Flag Changes Size Cycles Codes No changes Byte 1 Cycle 1 20 An lt lt 2 Dm 1 Accessing to odd addresses memory is not allowed MOV d8 An Dm Operation mem16 An d8 Adds the value of register An and a sign extended 8 bit displacement 128 to 127 to obtain a pointer to memory then sign extends the contents of that memory two bytes to 24 bits and moves that value to register Dm Flag Changes Size Cycles Codes No changes Bytes 2 Cycle 1 6
58. 2 Dm 80 DIVU Chapter2 Instruction Specifications Operation Dm Dn Subtracts the values of register Dn from the value of register Dm but the result is not stored in register Dm Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated to the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F3 90 Dn lt lt 2 Dm CMP Dm An Operation An Dm Subtracts the values of register Dm from the value of register An but the result is not stored in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated to the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 20 Dm lt lt 2 An
59. 4 abs24 F4 50 An abs24 l abs24 m abs24 h MOV imm8 Dn imm8 Dn 80 Dn 24Dn imm8 MOV imm16 Dn imm16 Dn F8 Dn imm16 l imm16 h MOV imm24 Dn imm24 Dn F4 70 Dn imm24 l imm24 m imm24 h MOV imm16 An 16 DC An imm16 l imm16 h MOV imm24 An imm24 4An F4 74 An imm24 l imm24 m imm24 h MOVX d8 An Dm mem24 An4d8 5Dm F5 70 An lt lt 2 Dm d8 MOVX d16 An Dm mem24 An d16 5 Dm F7 70 An lt lt 2 Dm d16 l d16 h MOVX d24 An Dm mem24 An d24 Dm F4 B0 An lt lt 2 Dm d24 d24 m d24 h MOVX Dm d8 An Dm meme 24 An d8 F5 50 An lt lt 2 Dm d8 MOVX Dm d16 An Dm mem24 An d16 F7 60 An lt lt 2 Dm d16 l d16 h MOVX Dm d24 An Dm mem24 An d24 F4 30 An lt lt 2 Dm d24 d24 m d24 h Notes MOVB An Dm mem8 An Dm 30 An lt lt 2 Dm B8 Dm 4 MOVB d8 An Dm mem8 An d8 5Dm F5 20 An lt lt 2 Dm d8 MOVB d16 An Dm mem8 An d16 5Dm F7 D0 An lt lt 2 Dm d16 I d16 h F4 A0 An lt lt 2 Dm d24 d24 m d24 h MOVB Di An Dm mem8 An Di Dm F0 40 Di lt lt 4 An lt lt 2 Dm MOVB d24 An Dm mem8 An d24 5Dm MOVB abs16 Dn mem8 abs16 Dn CC Dn abs16 l abs16 h B8 Dn 5 MOVB abs24 Dn mem8 abs24 Dn F4 C4 Dn abs24 l abs24 m abs24 h Dm An Dm mem8 An 10 Dm lt lt 2 An MOVB Dm d8 An Dm mem8 An d8 F5 10 An lt lt 2 Dm d8 MOVB Dm d16 An Dm mem
60. 6 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 00 Dm lt lt 2 An 66 ADD Chapter2 Instruction Specifications ADD An Dm Operation gt Dm Adds the value of register Dm to register An and stores the result in register Dm Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Cvcles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 lt lt 2 Operation gt Am Adds the value of register Am to register and stores the result in register Am Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Set if the MSB of the result is 1 reset otherwise Cycles 2 Set if the result is 0 reset otherwise F2 40 lt lt 2 Set if result t
61. 6 bits of the result are 0 reset otherwise 90 XOR Chapter2 Instruction Specifications Operation Dn x O0FFFF Dn Inverts each of the lower 16 bits in register Dn and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Size Cycles Codes 2 FlagChaaes Changes Bytes 2 Cycles 2 VX CX NX ZX Nochange VF Always 0 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise E44 Dn ZF Set if the lower 16 bits of the result are 0 reset otherwise NOT 91 Chapter2 Instruction Specifications A S R Logical Calculation Instructions Operation Dn Isb gt CF Dn bp Dn bp 1 bp15 1 Dn bp15 Dn bp15 Performs a 1 bit arithmetic shift right towards the LSB on the lower 16 bit value in register Dn and stores the result in the lower 16 bits of register Dn The value of bit 15 will not change The LSB before the shift will be stored in the 16 bit data carry flag CF The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange VF Always 0 Cvcles 2 CF Set if the LSB of the beforeoperation is 1 reset otherwise gue NF Set if bit 15 of the result is 1 reset otherwise F3 384Dn ZF Set if the lower 16 bits of the result are 0 reset otherwise Bytes 2 1 Use ADD Dn Dm to perform shift left of one bit See Section 2 19 in Chapter 3 Use of Instructions 92 ASR Chapt
62. 8 An d16 F7 90 An lt lt 2 Dm d16 l d16 h F4 20 An lt lt 2 Dm d24 d24 m d24 h MOVB Dm d24 An Dm mem8 An d24 MOVB Di An Dm mem8 An Di 1 Itis not possible to specify that Dn Dm OINI AJA gt o RO NJ e O H TO Imo IO ITO JA Jo WO O WO IO TO F0 C0 Di lt lt 4 An lt lt 2 Dm 2 This instruction is supported by the assembler For MOV d8 An Am the assembler will generate a bit pattern for d8 0 3 This instruction is supported by the assembler For MOV Am d8 An the assembler will generate a bit pattern for d8 0 4 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU An Dm and Dm 5 This instruction is supported by the assembler The assembler generates bit patterns for the two instructions MOVBU abs16 Dn and EXTXB Dn 146 Instruction set Instruction Mnemonic MOVB Dn abs16 Operation Dn mem8 abs16 Machine Code C4 Dn abs16 l abs16 h MOVB Dn abs24 Dn mem8 abs24 F4 444 Dn abs24 l abs24 m abs24 h MOVBU
63. 8 Dn abs16 l abs16 h F4 C0 Dn abs24 l abs24 m abs24 h MOV An A 24 70 lt lt 2 00 2 48 X Am mem24 An4d8 5Am 70 An lt lt 2 Am d8 MOV d16 An Am mem24 An d16 5 Am F7 B0 An lt lt 2 Am d16 I d16 h MOV d24 An Am mem24 An d24 5Am F4 F0 An lt lt 2 Am d24 d24 m d24 h MOV mem16 abs24 Dn MOV abs16 An mem24 abs16 An F7 30 An abs16 l abs16 h MOV abs24 An mem24 abs24 An F4 D0 An abs24 l abs24 m abs24 h MOV Dm An Dm mem 16 An 00 lt lt 2 MOV Dm d8 An Dm mem16 An d8 40 An lt lt 2 Dm d8 F7 80 An lt lt 2 Dm d16 l d16 h MOV Dm d16 An 16 916 F4 00 An lt lt 2 Dm d24 d24 m d24 h A MOV Dm d24 An 16 424 MOV Dm Di An 16 0 F1 C0 Di lt lt 4 An lt lt 2 Dm MOV Dn abs16 Dn mem16 abs16 C0 Dn abs16 l abs16 h MOV Dn abs24 Dn mem16 abs24 F4 40 Dn abs24 l abs24 m abs24 h MOV Am An 24 50 lt lt 2 00 3 MOV Am d8 An Am mem24 An d8 50 An lt lt 2 Am d8 MOV Am d16 An Am mem24 An d16 F7 A0 An lt lt 2 Am d16 d16 h MOV Am d24 An Am mem24 An d24 F4 10 An lt lt 2 Am d24 1 d24 m d24 h MOV An abs16 24 0516 F7 20 An abs16 l abs16 h MOV An abs24 An mem2
64. 9 bytes 7 6 cycles Total 17 bytes 59 cycles Use two data registers and one address register DO D1 MOV x f000 A0 3 bytes 1 cycle MOV 8 01 2 bytes 1 cycle Sub total 5 bytes 2 cycles loop MOV 0 00 1 byte 1 cycle MOV D0 x100 A0 4 bytes cycles ADD2 A0 2 bytes 1 cycle ADD 1 D1 2 bytes 1 cycle BNE loop 2 bytes 2 1 cycle Sub total 11 bytes 8 7 cycles Total 16 bytes 65 cycles Use two data registers and two address registers DO D1 AO A1 MOV 000 0 3 bytes 1 cycle MOV x f100 A1 3 bytes 1 cycle MOV x e D1 2 bytes 1 cycle Sub total 8 bytes 3 cycles loop MOV D1 A0 DO 2 bytes 2 cycle MOV 00 01 1 2 bytes 2 cycles ADD 2 D1 2 bytes 1 cycle BGEloop 2 bytes 2 1 cycle Sub total 8 bytes 7 6 cycles Total 16 bytes 59 cycles Programming Examples General Speed Optimization Size Optimization 131 Chapter 3 Use Of Instructions 2 10 PUSH AE Contents Push and pop operations are performed by sequences of several instructions By S increasing the number of registers used to perform push and pop example Q optimization shows smaller code size Example 4 A3 2 bytes 1 cycle DO A3 spush DO 3 bytes 3 cycles 4 A3 2 bytes 1 cycle D1 A3 push D1 3 bytes 3 cycles 1Obytes 8 cycles A3 D1 pop D1 8 bytes 3 cycles 4 A3 2 bytes 1
65. Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Bytes 4 Cycles 3 F7 A0 An lt lt 2 Am 416 1 d16 h MOV 41 Chapter 2 Instruction Specifications Operation Am gt mem24 An d24 Adds the value of register An and 24 bit displacement to obtain a pointer to memory and moves the 3 byte of register Amto that memory Flag Changes Size Cycles Codes Bytes 5 Cydes 4 F4 10 lt 2 424 1 d24 m d24 h 1 Accessing to odd addresses memory is not allowed 42 non Chapter 2 Instruction Specifications MOV abs16 An gt mem24 abs16 Operation Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory and moves the 3 byte value of register An to that memory Flag Changes Size Cycles Codes l Cycles 3 Accessing to odd addresses in memory is not allowed F7 20 An abs16 1 abs16 h MOV abs24 Operation An gt mem24 abs24 Moves the 3 byte value of register An to memory pointed to by the 24 bit absolute address abs24 Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 4 F4 50x An abs24 1 abs24 m abs24 h Accessing to odd addresses in memory is not allowed Mov 43 Chapter2 Instruction Specifications MOV imm 8 Flag Changes Size Cycles Codes No changes Bytes 2 Cycle 1 80 Dn lt lt 2 Dn imm8
66. Flags BNEX Branch Not Equal by Extended Flags BGTX Branch Greater Than by Extended Flags BGEX Branch Greater or Equal by Extended Flags BLEX Branch Less or Equal by Extended Flags BLTX Branch Less Than by Extended Flags BHIX Branch Higher by Extended Flags BCCX Branch Extended Carry Flag Clear BLSX Branch Low or Same by Extended Flags BCSX Branch Extended Carry Flag Set BVCX Branch Extended Overflow Flag Clear BVSX Branch Extended Overflow Flag Set BNCX Branch Extended Negative Flag Clear BNSX Branch Extended Negative Flag Set JMP Jump JSR Jump to Subroutine NOP No Operation RTS Return from Subroutine RTI Return from Interrupt Branch instruction types include register indirect specifications and program counter PC relative address specifications A branch instruction with a program counter relative address specification can branch within a range around the address that stores the instruction after the branch instruction 128 to 127 addresses d8 32768 to 32767 addresses d16 or 8388608 to 8388607 d24 There are 29 types of relative branch instructions Subroutine call instruction types include register indirect specifications and pro gram counter PC relative address specifications and can branch within 16 Mbytes 000000 to x FFFFFF then the lower 24 bits of the result will become the 1 If the address calculation of a branch destination falls outside the range branch destination address wraparound
67. For example the BGE instruction will branch when the previous CMP instruction encounters srcSdest as a signed 16 bit value Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch 2 48 Operation IF VF NF ZF 0 then PC 2 d8 label PC IF VF NF I ZF 1 then 2 If both VF NF and ZF are 0 or if both VF NF and ZF are 1 and if ZF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VF is 0 and NF is 1 orif VF is 1 and NF is 0 or if ZF is 1 then execution will continue with the instruction following the BGT instruction For example the BGT instruction will branch when the previous CMP instruction encounters src dest as a signed 16 bit value Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch 1 48 101 Chapter2 Instruction Specifications BCS label Operation IF CF 1 then PC 2 d8 label IF CF 0 then PC 2 If CF is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CF is 0 then execution will continue with the instruction following the BCS instruction For example the BCS instruction will branch when the previous CMP instruction encounters s
68. MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F7 18 Dn imm16 imm16 h 1 Thel16 bit immediate value imm16 will be sign extended to 24 bits a 68 ADD Chapter2 Instruction Specifications ADD imm24 Operation Dn imm24 Adds the 24 bit immediate value imm24 to register Dn and stores the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 5 Set if a carry is generated from the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F4 60 Dn imm24 1 imm24 m imm h ADD 8 An Operation An imms An Sign extends the 8 bit immediate value imm8 128 to 127 to 24 bits adds it to register An and stores the result in register An Fla
69. PC 3 If CX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CX is 1 then execution will continue with the instruction following the BCCX instruction For example the BCCX instruction will branch when the previ ous CMP instruction encounters src S dest as a un signed 24 bit value Flag Changes Size Cycles Codes No changes Operation BHIX label Flag Changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E6 d8 IF CX I ZX 0 then PC 3 d8 label IF CX I ZX 1 then PC 3 gt PC If both CX and ZX are 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CX or ZX is 1 then execution will continue with the instruction following the BHIX instruction For example the BHIX instruction will branch when the previous CMP instruction encounters src dest as a un signed 24 bit value Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E5 d8 111 Chapter2 Instruction Specifications BVCX label Operation IF VX 0 then PC 3 d8 label IF 1 then PC 3 If VX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instructi
70. Pana Series The One toWatch for Constant Innovation Making the Future Come Alive MICROCOMPUTER MN102L MN102L Series Instruction Manual Pub No 12250 030E Panasonic PanaX Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained fromthe competent authorities of the J apanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of J apan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book or Mats
71. SB of the beforeoperation is 1 reset otherwise NF Set if bit 15 of the result is 1 reset otherwise F3 344 Dn ZF Set if the lower 16 bits of the result are 0 reset otherwise 94 ROR Chapter2 Instruction Specifications R OL Logical Calculation Instruction Operation Dn bp15 temp Dn bp Dn bp 1 bp14 0 CF gt Dn Isb Performs a 1 bit rotate left towards the MSB on the lower 16 bit value in register Dn temp CF and the carry flag CF and stores the result in the lower 16 bits of register Dn The value of the carry flag CF before the shift will be stored in bit 15 The LSB before the shift will be stored in the carry flag CF The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX_ No change Bytes 2 VF Always 0 Cycles 2 CF Set if the LSB of the beforeoperation is 1 reset otherwise NF Set if bit 15 of the result is 1 reset otherwise F3 304Dn 7 Set if the lower 16 bits of the result are 0 reset otherwise ROL 95 Chapter2 Instruction Specifications 4 Bit Manipulation Instructions BTST 8 Operation Dn amp imms PSW Zero extends the 8 bit immediate value imm8 to 24 bits performs a logical AND with the value of register Dn and reflects the result in the PSW flags Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 3 VF Always 0 Always 0 Cycles 2 NF Always
72. a s C compiler is used this configurations shrinks code size to the maxi mum extent possible Address registers are 24 bits enabling use of a contiguous memory space up to 16 Mbytes 23 0 Data Registers 15 0 MDR Multiply Divide Register 15 0 PSW Processor Status Word Register Set 3 Chapter 1 Instruction Set Overview 2 1 Data Registers a EEEesl 03 0 Data Register 4 x 24 bits Data registers can generally be used for any calculation Calculations are performed in 24 bits but a flag change can cause calculations with both 24 bits and the lower 16 bits The data size will be changed by memory data move instructions and specialized size extension instructions When 8 bit data is loaded it will be sign extended or zero extended to 24 bits and moved to a register When stored the lower 8 bits of the register will be moved to memory When 16 bit data is loaded it will be sign extended to 24 bits and moved to a register When stored the lower 16 bits of the register will be moved to memory Finally 24 bit data will be moved to and from memory as is 2 2 Address Registers Sl Address Register 4 x 24 bits Address registers are used as address pointers They are supported only by instruc tions for address calculations add subtract compare Calculations are per formed in 24 bits but a flag change can cause calculations with both 24 bits and the lower 16 bits A3 is assigned as the stack poi
73. a to be accessed efficiently Calculation instructions can use two addressing modes register direct and immediate This series instruction set is based 16 bit data access instructions and 24 bit pointer data access instructions The address specifications for these instruc tions must be even addresses word boundaries Word boundaries must be observed especially for these addressing modes register indirect register rela tiveindirect absolute and indexed register indirect The address specifications for 8 bit data access instructions may also be odd addresses Chapter 1 Instruction Set Overview lllAddressing Modes Addressing Mode Address Calculation Effective Address Dn An imm8 Immediate imm16 imm24 Register Direct Register Indirect 24 bit address d8 An 1148 is sign extended 916 2916 is sign extended d24 An 24 bit address Register Relative Indirect 98 is sign extended 24 bit address d16 PC 119416 is sign extended d24 PC 15 7 branch instructions 924d 16 d8 only abs16 15 Absolute abs16 is zero extended abs24 abs16 24 bit address abs24 Indexed Register Indirect 24 bit address Dm An Addressing Modes 13 Chapter 1 Instruction Set Overview 14 Addressing Modes 5 1 Register Direct Addressing The register direct addressing mode directly specifies a register The following regist
74. aken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise ADD 67 Chapter2 Instruction Specifications ADD 8 Operation Dn imm8 Sign extends 8 bit immediate value imm8 128 to 127 to 24 bits adds it to register Dn and stores the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Cvcle 1 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise D4 Dn imm8 1 8 bit immediate value imm8 will be sign extended to 24 bits ADD 16 Operation Dn imm16 Dn Sign extends the 16 bit immediate value imm16 32768 to 32767 to 24 bits adds it to register Dn and stores the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 4 Set if a carry is generated from the
75. bitwise logical OR of zero extends the 8 bit immediate value imm8 to 16 bits and the lower 16 bits of register Dn and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX No change Bytes 3 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F5 08 Dn imm8 ZF Set if the lower 16 bits of the result are 0 reset otherwise 1 The 8 bit immediate value imm8 will be zero extended to 16 bits 88 Chapter2 Instruction Specifications OR imm16 Operation Dn I imm16 gt Dn Performs a bitwise logical OR of the lower 16 bits or registers Dn and the 16 bit immediate value imm16 and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 4 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F7 404Dn imm16 l imm1 6 h ZF Set if the lower 16 bits of the result are 0 reset otherwise OR 16 PSW Operation PSW imm16 PSW Performs a bitwise logical OR of the 16 bit immediate value imm16 and the PSW and stores the result in the PSW The lower 8 bits will be stored in the PSW flags VX bit 7 CX bit 6 NX bit 5 ZX bit 4 VF bit 3 CF bit 2 NF bit 1 and ZF bit 0 The PSW flags S1 SO IE and IMZ
76. bytes before the first address of the next instruction to 127 bytes after If VF is 0 then execution will continue with the instruction following the BVS instruction Operation Chapter2 Instruction Specifications label IF NF 0 then PC 3 d8 label IF NF 1 then PC 3 If NF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If NF is 1 then execution will continue with the instruction following the BNC instruction Flag Changes Size Cycles Codes No change Operation BNS label Flag Changes Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 FE d8 IF 1 then PC 3 d8 label if NF 0 then gt If NF is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If NF is 0 then execution will continue with the instruction following the BNS instruction Bytes 3 Cycles 3 branch Cycles 2 non branch F5 FF d8 Bcc 105 Chapter2 Instruction Specifications BRA label Operation PC 2 d8 label Branches unconditionally to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after Flag Changes Siz
77. ction For Byte Access MOVBU x fc20 DO 8 bytes 1 cycle AND x fb DO 8 bytes 2 cycles MOVB DO x fc20 8 bytes 1 cycle Total 9 bytes 4 cycles The example below gives smaller code size x c20 A0 3 bytes 1 cycle A0 DO 1 bytes 1 cycle x fb DO 3 bytes 2 cycles DO A0 1 bytes 1 cycle Total 8 bytes 5 cycles 0 Using BCLR Instruction For Byte Access MOV X c20 A0 8 bytes 1 cycle MOV x 04 DO 2 bytes 1 cycle BCLR 00 0 2 bytes 5 cycles Total 7 bytes 7 cycles 136 Programming Examples General Speed Optimization Size Optimization Chapter Use Of Instructions 2 16 Bit Test LS Au Contents Use the BTST instruction to test bits If it does not matter whether or not the value in a register moved from memory is valid then an AND instruction can also be General used but code size and processing speed will not change information Example D Register data must be valid MOV x fc20 DO 3 bytes 1 cycle BTST x 5 DO 3 bytes 2 cycles Total 6 bytes 3 cycles 2 Register data may be invalid MOV x fc20 DO 3 bytes 1 cycle AND x 5 DO 8 bytes 2 cycles Total 6 bytes 3 cycles 2 17 Subtracting 1 128 Contents When subtracting values 1 128 an ADD instruction will result in faster smaller Speed Size code than a SUB instruction optimization optimization Example x 7f DO 4 bytes 2 cycles
78. cycle A3 DO pop DO 3 bytes 3 cycles 4 A3 2 bytes 1 cycle Total 10 bytes 8 cycles 8 A3 2 bytes 1 cycle DO 4 A3 push DO 3 bytes 3 cycles D1 A3 push D1 3 bytes 3 cycles Total 8 bytes 7 cycles A3 D1 01 3 bytes 3 cycles 4 A3 DO pop DO 3 bytes 3 cycles 8 A3 2 bytes 1 cycle Total 8 bytes 7 cycles 132 Programming Examples General Speed Optimization Size Optimization Chapter 3 Use Of Instructions 2 11 Of PSW Contents When pushing and popping the PSW the PSW flags will change if the stack Precaution pointer value is changed using an ADD instruction Example PUSH ADD 10 A3 PSW is changed MOVX D0 6 A3 MOV PSW DO Push the changed PSW MOV DO 4 A3 MOVX D1 A3 Code as follows ADDNF 10 PSW is not changed MOVX DO 6 A3 MOV PSW DO Move PSW to DO MOV DO 4 A3 Push PSW MOVX D1 A3 Q POP MOVX A3 D1 MOV 4 A3 DO MOV DO PSW Pop PSW MOVX 6 A3 D0 ADD 10 A3 Poping PSW is changed Code as follows MOVX A3 D1 MOV 4 A3 DO Move PSW to DO MOV DO PSW Pop PSW MOVX 6 0 ADDNF 10 Programming Examples General Speed Optimization Size Optimization 133 Chapter 3 Use Of Instructions 2 12 Zero Clear Of Registers 22 2 2222 2522 22 ic Ce vC NC S EEUU RM Contents To zero clear registers use the SUB instruction for
79. cycles Total 8 bytes 6 cycles MOV x f000 A1 8 bytes 1 cycle MOV A1 A0 2 bytes 2 cycles MOV 0 4 1 2 bytes 2 cycles Total 7 bytes 5 cycles MOV x 000 A1 3 bytes 1 cycle MOVX 0 1 00 8 bytes 3 cycles MOVX DO 4A1 3 bytes 3 cycles Total 9 bytes 7 cycles 128 Programming Examples General Speed Optimization Size Optimization Chapter 3 Use Of Instructions 2 5 Repeated Access To The Same Memory Se GPL MEC TOU M CUN 5 52 Contents When performing repeated accesses to the same memory register indirect address Size ing will result in smaller code size than absolute addressing optimization Example x f000 DO 8 bytes 1 cycle 1 DO 2 bytes 1 cycle x f000 8 bytes 1 cycle Total 8 bytes 3 cycles Register indirect addressing gives smaller code size 000 0 8 bytes 1 cycle A0 DO 1 byte 1 cycle 1 DO 2 bytes 1 cycle DO A0 1 byte 1 cycle Total 7 bytes 4 cycles 2 6 Byte Access And Word Access Contents Word accesses result in better code speed and size than byte accesses Speed Size optimization optimization Example MOVB A3 D0 2 bytes 2 cycles Word accesses give smaller faster code A3 DO 1 byte 1 cycle x 10 A0 DO 3 bytes 2 cycles Word accesses give smaller faster code x10 A0 DO 2 bytes 1 cycle x 10 A0 DO 8 bytes 2 cycles
80. d8 PC is specified 1 in assembly language with a label BEQ LABEL LABEL MOV DO D1 16 Addressing Modes Chapter 1 Instruction Set Overview 5 5 Absolute Addressing EEUU EDAD OW a 27 2 22 222 TT UNES CUN The absolute addressing mode directly specifies 24 bit address with 16 bit or 24 bit operand value added to the instruction code A 16 bit operand will be zero extended to 24 bits With this mode data move instructions can directly specify up to 16 Mbytes of memory space ROM RAM space Absolute syntax abs 16 abs24 15 o abs 16 Zero extension o Memory address specification abs24 0524 23 Memory address specification 5 6 Indexed Register Indirect Addressing The indexed register indirect addressing mode specifies the address pointed to by an address register An and a data register Dm The 24 bit value in the address register An is added to the 24 bit value in the data register Dm Indexed register indirect syntax Dm A n 23 Memory address specification numbers n and m of An and Dm may be the same Addressing Modes 17 Chapter 1 Instruction Set Overview Instruction Format There are seven instruction formats The format used by each instruction is fixed 8 bits Format1 Formar OP Formats OP 7 Formats oP OP mmer OP OP instruction ope
81. data 8 24 bit zero extended word data 9 24 bit sign extended byte data 10 24 bit zero extended byte data 11 Addition without changing flag 12 16x16 32 signed 13 16x16 32 unsigned 14 32 16 16 16 unsigned F3 60 Dn lt lt 2 Dm Instruction set 147 Appendix Instruction Mnemonic CMP Dn Dm Operation Dm Dn Machine Code F3 90 Dn lt lt 2 Dm CMP Dm An An Dm F2 20 Dm lt lt 2 An CMP An Dm Dm An F2 E0 An lt lt 2 Dm CMP An Am Am An F2 60 An lt lt 2 Am CMP imm8 Dn Dn imm8 D84 Dn imm8 CMP imm16 Dn Dn imm16 F7 48 Dn imm16 l imm16 h CMP imm24 Dn Dn imm24 F4 78 Dn imm24 l imm24 m imm24 h CMP imm16 An An imm16 EC An imm16 l imm16 h CMP imm24 An An imm24 F4 7C An imm24 l imm24 m imm24 h AND Dn Dm Dm amp x FF0000 Dn 2Dm F3 00 Dn lt lt 2 Dm 15 AND imm8 Dn Dn amp x FF0000 imm8 Dn F5 00 Dn imm8 15 AND imm16 Dn Dn amp x FF0000 iimm16 Dn F7 004 Dn imm16 l imm16 h 15 AND imm16 PSW PSW amp imm16 PSW F7 10 imm16 l imm16 h 15 OR Dn Dm Dm Dn amp x O0FFFF 2Dm 10 lt lt 2 15 OR imm8 Dn Dn imm8 Dn F5 08 Dn imm8 15 OR imm16 Dn Dn imm16 Dn F7 40 Dn imm16 l imm16 h 15 OR imm16 PSW PSW imm16 PSW F7 14 imm16 l imm16 h 15
82. derstanding of the text 2 instruction Set Instruction Set instruction set of the MN10200 Series High speed linear addressing version was basically designed for use with C compilers Preferential assignment of in structions most frequently used by C compilers to single byte single cycle codes has enabled much faster execution and smaller code size Splitting the register set into four 24 bit data registers and four 24 bit address registers has allowed fre quently used basic instructions such as register register calculations and register memory moves to be implemented in single bytes Section summary Ex E Move the contents of the DO register to the memory address pointed to by the 0 register Mov DO 0 W Add the contents of the DO re ADD 01 DO 1 byte 1 cycle gister to the contents of the D1 register 1 byte 1 cycle The insruction set of the 10200 Series High speed Linear Linear Addressing Version by Matsushita Additional instruc 1 Addressing Version is upper compatible of MN10200 Series tions flages for High speed Linear Addressing Version are as follows Additional instructions and flags for High speed Linear Addressing Version Additional instructions and flags outline Arthmetic Calculation Instructions Bit Manipulation Instructions Bit Test amp Branch Instructions Control Instructions Saturation Enable Flags Addi
83. diah 87 D 92 E o P 103 11 Dm An i nennen 98 Lo 102 cnet darin tan 110 ot 99 a EET 107 Loc 101 DIVU ccce eis mae rea 109 101 109 E 103 11 100 label 108 EXTXBU 25 102 EXTXU liE 0 110 pon 100 label 108 Lo 105 ADD EXTXU 113 label 99 107 105 Eo 113 label aon eee eth 106 DERE UTI 97 DR 96 104 e 112 TTE 104 conica d te a e FUR ER MP 112 AN DM p 82 AN PUM m 82 AT the ti ete enenatis ett id Rn 81 81 rt rrrr 83 84 Toa aq Usha 83 dace 85 WIAA Spr 84 80 61 rhet i a 62 64 pp 65 M 63 Index
84. e reset otherwise 76 SUB Chapter2 Instruction Specifications S UB C Arithmetic Calculation Instructions SUBC Dn Dm Dm Dn CF gt Dm Operation Subtracts the value of register Dn and the 16 bit data borrow CF from register Dm and stores the result in register Dm Flag Changes VX Set if result taken as a 24 bit signed value overflows reset otherwise CX Set if a borrow is generated from the MSB reset otherwise NX Set if the MSB of the result is 1 reset otherwise ZX Set if the result is 0 reset otherwise VF Set if result taken as a 16 bit signed value overflows reset otherwise CF Set if a borrow is generated from bit 15 reset otherwise NF Set if bit 15 of the result is 1 reset otherwise if ZF 1 and the lower 16 bits of the result are 0 reset otherwise Size Cycles Codes Bytes 2 Cycles 2 F2 90 Dn lt lt 2 Dm 32 bit subtraction can be performed by combining an SUB instruction and SUBC instruction A zero check on the 32 bit result can be done only with ZF after the SUBC instruction has been executed 4 sUBC 77 Chapter2 Instruction Specifications M L Arithmetic Calculation Instructions Operation Dm Dn Dm Dm 0 gt gt 16 gt Multiplies the lower 16 bits of register Dm and the lower 16 bits of register Dn as signed numbers and stores the upper 16 bits of the 32 bit result in register MDR and the lower 24 bits in reg
85. e Fixed number of process cycles DW x 0001 This code does not work properly DW x 0002 for an input value of 0 for D2 0004 8000 Programming Examples General Speed Optimization Size Optimization 139 Chapter 3 Use Of Instructions Speed Size optimization optimization 2 21 8 Bit Swap a a i Contents When performing an 8 bit swap exchange upper 8 bits and lower 8 bits sequence of instructions will result in smaller or faster code than a shift instruction Example 00 01 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle ADD 00 00 1 bit shift left 1 byte 1 cycle LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles LSR D1 1 bit shift right 2 bytes 2 cycles OR D1 DO 2 bytes 2 cycles Total 27 bytes 27 cycles Use of stack gives faster code ADD 2 A3 2 by
86. e Cycles Codes 2 EA d8 106 Bcc Chapter2 Instruction Specifications B CCX Branch Instructions BEQX label Operation IF ZX 1 then PC 3 d8 label PC IF ZX 0 then PC 3 gt PC If ZX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If ZX is 0 then execution will continue with the instruction following the BEQX instruction For example the BEQX instruction will branch when the previous CMP instruction encounters a 24 bit source equal to a 24 bit destination Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E8 d8 BNEX label IF ZX 0 then PC 3 d8 label PC IF ZX 1 then PC 3 PC Operation If ZX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If ZX is 1 then execution will continue with the instruction following the BNEX instruction For example the BNEX instruction will branch when the previ ous CMP instruction encounters a 24 bit source not equal to a 24 bit destination Flag Changes Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 F9 48 107 Chapter2 Instruction Specifications BLTX Operation label IF
87. e in the range 0000 to x FFFF MOV x Do ADD x 89AB DO x 7FFF x 89AB x 109AA Carry from VF Overflow Flag The overflow flag is set if a calculation resulting in a 16 bit signed value generates an overflow if not generated then the flag is cleared Ex The VF is set if the result of a calculation cannot be expressed by a 16 bit signed value in the range x 8000 the most negative value to 7 the most positive value MOV x TODA DO ADD x 49 ZL DO 1 x 7654 x 4321 x B975 positive positive negative Register Set 5 Chapter 1 Instruction Set Overview ZX Extended Zero Flag The extended zero flag is set if 24 bits of a calculation result are all 0 otherwise the flag is cleared NX Extended Negative Flag The extended negative flag is set if the most significant bit of a calculation result is 15 if 0 then the flag is cleared CX Extended Carry Flag The extended carry flag is set if a calculation generates a carry from or a borrow to the most significant bit if not generated then the flag is cleared Extended Overflow Flag The extended overflow flag is set if a calculation resulting in a 24 bit signed value generates an overflow if not generated then the flag is cleared IM2 IMO Interrupt Mask The interrupt mask bits indicate the CPU interrupt mask level These three bits can be set from level 0 000 to level
88. ement 128 to 127 adds it to register An to obtain a pointer to memory and moves the contents of that memory 3 bytes to register Dm Flag Changes Size Cycles Codes a Accessing to odd addresses in memory is not allowed Bytes 3 Cycles 3 F5 70 An lt lt 2 Dm 48 Dx BARAA MOVX d16 An Dm Operation w mem24 An d16 gt Dm Sign extends 16 bit displacement 32768 to 32767 adds it to register An to obtain a pointer to memory and moves the contents of that memory 3 bytes to register Dm Flag Changes Size Cycles Codes a Accessing to odd addresses in memory is not allowed Bytes 4 3 F7 70 An lt lt 2 Dm 416 1 d16 h MOVX 47 Chapter2 Instruction Specifications 924 An Operation mem24 An d24 Dm Adds the 24 bit displacement to register An to obtain a pointer to memory and moves the contents of that memory 3 bytes to register Dm Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 4 F4 0 lt lt 2 424 1 d24 m d24 h 1 Accessing to odd addresses memory is not allowed a MOVX Dm 98 An Operation Dm mem24 An d8 Adds the value of register An and a sign extended 8 bit displacement 128 to 127 to obtain a pointer to memory and moves the 3 byte value of register Dm to that memory Flag Changes Size Cycles Codes
89. er2 Instruction Specifications Logical Calculation Instructions LSR Operation Dn Isb CF Dn bp gt Dn bp 1 bp15 1 0 Dn bp15 Performs a 1 bit logic shift right towards the LSB on the lower 16 bit value in register Dn and stores in the register Dn The value of bit 15 stores 0 The LSB from before the shift will be stored in the 16 bit data carry flag CF The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 2 VF Always 0 Cycles 2 CF Set if the LSB of the beforeoperation is 1 reset otherwise XS F3 3C Dn NF Always 0 ZF Set if the lower 16 bits of the result are 0 reset otherwise a Use ADD Dn Dm to perform a shift left of one bit See Section 2 19 in Chapter 3 Use of Instructions LSR 93 Chapter2 Instruction Specifications R OR Logical Calculation Instructions Operation Dn Isb temp Dn bp gt Dn bp 1 bp15 1 CF Dn bp15 Performs a 1 bit rotate right towards the LSB on the lower 16 bit value temp CF register Dn and the carry flag CF and stores the result in the lower 16 bits of register Dn The value of the 16 bit data carry flag CF before the shift will be stored in bit 15 The LSB before the shift will be stored in the carry flag CF The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 2 VF Always 0 1 2 CF Set if the L
90. ers can be specified Dn data registers 24 bit An address registers 24 bit MDR multiply divide register 16 bit PSW processor status word 16 bit 5 2 Immediate Addressing EDGE 5 2 2224 35225224 2 225 552 IRI A Jm UR quU S The immediate addressing mode allows move values and mask values to be di rectly specified as an operand added to the instruction code Immediate sizes can be 8 bits 16 bits and 24 bits Chapter 1 Instruction Set Overview 5 3 Register Indirect Addressing The register indirect addressing mode uses the 24 bit address pointed to by the value in an address register An Register indirect syntax A n 23 0 L Memory address specification Addressing Modes 15 Chapter 1 Instruction Set Overview 5 4 Register Relative Indirect Addressing 2221222 M The register relative indirect addressing mode is an address specification pointed to by either an address register An or the program counter PC with a displace ment The size of the displacement can be 8 bits 16 bits or 24 bits An 8 bit or 16 bit displacement will be sign extended before being added to the address register An or program counter PC Register relative indirect syntax d 8 d16 An d24 An d8 416 PC 424 6 08 6 48 Memory address specification Of the various register relative indirect addressing modes
91. erwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise imm16 1 imm16 h 1 The 16 bit immediate value imm16 will be zero extended to 24 bits a 84 Chapter2 Instruction Specifications Operation 24 Subtracts the 24 bit immediate value imm24 from register An but does not store the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 5 Set if a borrow is generated to the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise F4 7C An imm24 1 imm24 m Set if result taken as a 16 bit signed value overflows reset otherwise imm24 h Set if a borrow is generated to bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise CMP 85 Chapter2 Instruction Specifications AN D Logical Calculation Instructions AND Operation Dm amp x FF0000 1 Dn gt Dm Performs a bitwise logical AND of the lower 16 bits registers Dn and Dm and stores the result in the lower 16 bits of register Dm The
92. g Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Cycle 1 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise 0 imm8 1 The 8 bit immediate value imm8 will be sign extended to 24 bits ADD 69 Chapter2 Instruction Specifications ADD imm16 An Operation An imm16 gt An Sign extends the 16 bit immediate value imm16 32768 to 32767 to 24 bits adds it to register An and stores the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 4 Set if a carry is generated from MSB reset otherwise Set if the MSB of the result is 1 reset otherwise Cycles 2 Set if the result is 0 reset otherwise F7 08 An imm16 1 imm16 h Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise 1 The 16 b
93. gister Dn and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes 7 No change Bytes 3 VF Always 0 Cycles 2 CF Always 0 SHE NF Set if bit 15 of the result is 1 reset otherwise F5 08 00 imm ZF Set if the lower 16 bits of the result are 0 reset otherwise The 8 bit immediate value imms will be zero extended to 16 bits Footer May change Will not change Undefined Always 0 0 Always 1 1 Code size cycles instruction code Indicates the code size number of cycles minimum and instruction code when the instruction format is used The bytes of the instruction code are delimited by colons A 2 will indicate a 2 bit shift and a register name will be converted to the corresponding register number in code Warning Indicates the instruction About This Manual 3 gt Read thoroughly to ensure correct operation of programs Chapter 1 Chapter 2 Chapter 3 Table Of Contents Instruction Set Overview Instruction Specifications Use Of Instructions Appendix Index Table of Contents Chapter 1 2 gt Instruction Set Overview e Instruction 6 2 Register Set 2 nennen enne 3 2 1 Data Registers 4 2 2 Address
94. he stack will be as shown at right Flag Changes Byte 1 Cycles 5 FE RTS 119 Chapter2 Instruction Specifications R T I Branch Instructions RTI Operation mem16 A3 gt PSW mem24 A3 2 PC A346 A3 1 Returns from an interrupt process to the pro 0 High byte Low byte lower address PC address lower PC return pe Du E gram that was executing before the interrupt OIdA3 SP was received The PSW before the interrupt will be popped from the stack into the PSW and the address of the next instruction to ex ecute will be popped from the stack into the PC and 6 will be added to the stack pointer After the RTI instruction executes the stack will be as shown at right Flag Changes Size Cycles Codes Restored to its pre interrupt status Byte 1 CX Restored to its pre interrupt status Cycles 6 NX Restored to its pre interrupt status yes ZX Restored to its pre interrupt status VF Restored to its pre interrupt status CF Restored to its pre interrupt status NF Restored to its pre interrupt status Restored to its pre interrupt status EB 120 RTI Use Of Instructions Chapter 3 UseOf Instrudions 122 Notes Regarding Use Of Instructions Chapter 3 Use Of Instructions collects notes precautions and know how for instruction se lection that the
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96. ications BGEX label Operation IF NX 0 then PC 3 d8 label PC IF VX NX 1 then PC 3 PC If both and NX are 0 or if both and NX are 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VX is 0 and NX is 1 or if VX is 1 and NX is 0 then execution will continue with the instruction following the instruction For example the instruction will branch when the previous CMP instruction encounters src lt dest as a signed 24 bit value Flag Changes Size Cycles Codes No changes Operation BGTX label Flag Changes Bytes 3 Cycles 3 branch Cycles 2 non branch 5 2 48 IF VX NX I ZX 0 then PC 3 d8 label IF VX NX I ZX 1 then PC 3 If both VX NX and ZXare 0 or if both and NX are 1 and ZX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VX is 0 and NX is 1 or if VX is 1 and NX is 0 or if ZX is 1 then execution will continue with the instruction following the BGTX instruction For example the BGTX instruction will branch when the previous CMP instruction encounters src dest as a signed 24 bit value Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 E1
97. ications D I Arithmetic Calculation Instructions DIVU Dn Dm MDR 164Dm Dn Dm Operation Divides the unsigned 32 bit concatenation of register MDR s upper 16 bits and register Dm s lower 16 bits by the unsigned 16 bit value from the lower 16 bits of register Dn The 16 bit quotient is zero extended to 24 bits and stored in register Dm The 16 bit remainder is stored in register If an overflow occurs VF 1 then the resulting contents of registers Dm and will be undefined VF will also be set to 1 when division by zero is performed divisor is 0 The DIVU instruction performs an unsigned division 32 bits 16 bits 16 bits 16bits 1 upper 015 lower 0 15 0 quvidend ee un signed un signed 23 15 0 15 0 p quotient remainder Flag Changes Size Cycles Codes If VF 0 Bytes 2 Indicates that no overflow occurs for 16 bit unsigned quotient Cycles 13 VX CX Undefined NX 0 indicates that the MSB of the quotient in register Dm is 0 ZX Set if quotient in register Dm is 0 reset otherwise VF 0 CF Undefined NF Set if MSB of 16 bit quotient is 1 reset otherwise ZF Set if 16 bit quotient is 0 reset otherwise elf VF 1 Indicates that the quotient overflowed or that division by zero was performed VX CX NX ZX Undefined VF 1 CF NF ZF Undefined 60 Dn lt lt
98. imization Speed optimization Chapter 3 Use Of Instructions 2 20 Logical Multiple Bit Shift 125225252 EE AA Contents A multiply instruction using a look up table for the multiplier levels processing times for multibit shifts left or right to a fixed number of cycles speeding up ex ecution for all sizes greater than 3 Example D Left shift of any number of bits D1 lt lt D2 Nisl BRA NIsl1 2 bytes 2 cycles NislO ADD D1 D1 1 byte 1 cycle Nisl1 ADD 1 D2 2 bytes 1 cycle BNC NislO 2 bytes 2 1 cycle Total 7 bytes 4 92 4 cycles Small ROM size 4 60 process cycles Nisl MOV Ntbl A1 5 bytes 3 cycles ADD D2 D2 1 byte 1 cycle MOV D2 A1 D2 2 bytes 2 cycles MULU D2 D1 2 bytes 12 cycles Total 10 32 bytes 18 cycles Large ROM size Fixed number of process cycles x 0001 DW 0002 0004 8000 2 Right shift of any number of bits 2 01 gt gt 02 Nisr BRA Nisr1 2 bytes 2 cycles Nlsr0 LSR D1 2 bytes 2 cycles ADD 1 D2 2 bytes 1 cycle BNC NisrO 2 bytes 2 1 cycle Total 8 bytes 4 d2 5 cycles Small ROM size 4 75 process cycles Nisr MOV Ntbl 32 A1 5 bytes 3 cycles ADD D2 D2 1 byte 1 cycle SUB D2 A1 2 bytes 2 cycles MOV A1 D2 1 byte 1 cycle MULU D2 D1 2 bytes 12 cycles MOV MDR D1 2 bytes 2 cycles Total 13 32 bytes 21 cycles Large ROM siz
99. ion Specifications MOV Dn abs24 Operation Dn gt mem16 abs24 Moves the lower 16 bits of register Dn two bytes to the memory pointed to by the 24 bit absolute address abs24 Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed MOV Am An Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Bytes 5 Cycles 3 F4 404 Dn abs24 1 abs24 m abs24 h Am gt 24 Moves the value of register Am three bytes to the memory pointed to by the register An Bytes 2 Cycles 2 50 An lt lt 2 Am 00 a This instruction is supported by the assembler The assembler generates the instruction code for MOV Am d8 An d8 0 40 Chapter2 Instruction Specifications Am d8 Operation Am mem24 An d8 Adds the value of register An and a sign extended 8 bit displacement 128 to 127 to obtain a pointer to memory and moves the 3 byte value of register Am to that memory Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Bytes 2 Cycles 2 50 An lt lt 2 Am 48 916 Operation Am mem24 An d16 Adds the value of register An and a sign extended 16 bit displacement 32768 to 32767 to obtain a pointer to memory and moves the 3 byte value of register Am to that memory
100. irect or register relative indirect d8 d16 d24 An address ing mode ex ecutes immediately after that same address register wes modified Too few instructions instructions do not exist in the instruction queue Memory waits inserted Data bus for external memory is 8 bits wide Cycle counts will also differ for single chip mode memory expansion mode and processor mode Specific cycle counts should be measured with an emulator 22 Instruction Execution Time Instruction Specifications Chapter2 Instruction Specifications Symbol Definitions ee Following is the list of symbols used in the instruction specifications Dn Dm Di An Am MDR PSW PC abs16 abs16 l abs16 h abs24 abs24 l abs24 m abs24 h imm8 imm16 imm16 l imm16 h imm24 imm24 imm24 m imm24 h d8 d16 916 1 d16 h d24 924 d24 m d24 h 156 msb amp gt gt VX CX NX ZX 24 Symbol Definitions Data register 24 bits Address register 24 bits Multiply divide register 16 bits Processor status word 16 bits Program counter 24 bits 16 bit absolute address 8 bits of 16 bit absolute address High 8 bits of 16 bit absolute address 24 bit absolute address Low 8 bits of 24 bit absolute address Middle 8 bits of 16 bit absolute address High 8 bits of 16 bit absolute address 1 Memory space specifying address by contents of the parenthese
101. is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F2 0 lt lt 2 Operation Am An gt Am Subtracts the value of register An from the value of register Am and stores the result in register Am Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a borrow is generated from the MSB reset otherwise Set if the MSB of the result is 1 reset otherwise Cycles 2 Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise 74 SUB Chapter2 Instruction Specifications SUB 16 Dn Operation Dn imm16 Dn Sign extends the 16 bit immediate value imm16 32768 to 32767 to 24 bits subtracts it from register Dn and stores the result in register Dn Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows
102. ister Dm The upper 8 bits of register Dm will be the same as the lower 8 bits of register MDR The MUL instruction performs a signed multiplication 16 bits x 16 bits 32 bits 23 15 0 23 15 0 L_ Multiplicand L Multiplier signed signed 2423 1615 Flag Changes Size Cycles Codes VX CX NX ZX Undefined Bytes 2 VF Always 0 Cycles 12 CF Undefined NF Set if MSB of result 32 bits is 1 reset otherwise 40 Dn lt lt 24 Dm ZF Set if result is 0 reset otherwise 78 MUL Chapter2 Instruction Specifications M UL U Arithmetic Calculation Instructions MULU Dn Dm Operation Dm Dn gt Dm Dm gt gt 16 gt Multiplies the lower 16 bits of register Dm and the lower 16 bits of register Dn as unsigned numbers and stores the upper 16 bits of the 32 bit result in register MDR and the lower 24 bits in register Dm The upper 8 bits of register Dm will be the same as the lower 8 bits of register MDR The MULU instruction performs an unsigned multiplication 16 bits x 16 bits 32 bits 23 15 0 23 15 0 L Multiplicand Multiplier un signed un signed 24 23 1615 Dn O Flag Changes Size Cycles Codes VX CX 5 ZX Undefined Bytes 2 VF AI 12 CF Undefined NF Set if MSB of result 32 bits is 1 reset otherwise F3 50 lt lt 2 ZF Set if result is 0 reset otherwise MULU 79 Chapter2 Instruction Specif
103. it immediate value imm16 will be sign extended to 24 bits ADD 24 Operation An imm24 Adds the value of register An to the 24 bit immediate value and stores the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 5 Set if a carry is generated from the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise F4 64 An imm24 l imm24 m Set if result taken as a 16 bit signed value overflows reset otherwise imm24 h Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise 70 ADD AD D C Arithmetic Calculation Instructions Chapter2 Instruction Specifications ADDC Dm Dn CF gt Dm Adds the value of register and 16 bit data carry to register Dm and stores the result in register Dm Flag Changes i Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise F2 80 Dn lt lt 2 Dm Set if result taken as a 16 bit signed value overflows reset
104. ize Cycles Codes No changes Bytes 4 Cycles 3 F7 30 An abs16 1 abs16 h 1 Accessing to odd addresses memory is not allowed a MOV abs24 An mem24 abs24 Operation 24 bits to obtain an absolute address pointing to memory and moves that value in memory three bytes to register An Flag Changes Size Cycles Codes 1 Accessing to odd addresses memory is not allowed a Bytes 5 Cycles 4 F4 D0 An 5524 1 abs24 m abs24 h 36 MOV Chapter2 Instruction Specifications MOV Flag Changes Size Cycles Codes Accessing to odd addresses in memory is not allowed Dm mem16 An Moves the lower 16 bits of register Dm two bytes to the memory pointed to by register An Byte 1 Cycle 1 00 An lt lt 2 Dm MOV Dm d8 An Operation Dm gt mem16 An d8 Adds the value of register An and a sign extended 8 bit displacement 128 to 127 to obtain a pointer to memory and moves the lower 16 bits of register Dm two bytes to that memory Flag Changes Size Cycles Codes No changes Bytes 2 Cycle 1 40 An lt lt 2 Dm d8 Accessing to odd addresses in memory is not allowed Mov 37 Chapter2 Instruction Specifications MOV d16 An Operation Dm gt mem16 An d16 Adds the value of register An and a sign extended 16 bit displacement 32768 to 32767 to obtain a pointer to memor
105. nter Moves to and from memory are always as 24 bits 2 3 Program Counter 2222222 2222 PC Program Counter 1 x 24 bits The program counter is a 24 bit counter that indicates the address of the instruction currently executing 2 4 Multiply Divide Register Fa MDR Multiply Divide Register 1 x 16 bits The multiply divide register is provided for multiply and divide instructions For multiply instructions it will store the upper 16 bits of the 32 bit product For di vide instructions it will store the upper 16 bits of the dividend before execution and the 16 bit remainder of the result after execution 4 Register Set Chapter 1 Instruction Set Overview 2 5 Processor Status Word PSW Processor Status Word 1 x 16 bits The processor status word is a register that indicates the CPU state It contains flags for calculation results and interrupt mask levels 15 0 nope wore ZF Zero Flag The zero flag is set if the lower 16 bits of a calculation result are all 0 otherwise the flag is cleared NF Negative Flag The negative flag is set if bit 15 of a calculation result is 1 if 0 then the flag is cleared CF Carry Flag The carry flag is set if a calculation generates a carry from or a borrow to bit 15 if not generated then the flag is cleared Ex The CF is set if the result of a calculation cannot be expressed by a 16 bit unsigned valu
106. on to 127 bytes after If VX is 1 then execution will continue with the instruction following the BVCX instruction Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 EC d8 BVSX label Operation IF VX 1 then PC 3 d8 label IF VX 0 then PC 3 PC If VX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VX is 0 then execution will continue with the instruction following the BVSX instruction Flag Changes 112 Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch F5 ED d8 Chapter2 Instruction Specifications BNCX label Operation IF NX 0 then PC 3 d8 label gt IF NX 1 then PC 3 If NX is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If NX is 1 then execution will continue with the instruction following the BNCX instruction Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 3 branch Cycles 2 non branch 5 48 BNSX label Operation IF NX 1 then PC 3 d8 label PC IF NX 0 then 3 If NX is 1 then branches to the address indicated by label The branch range is from 128 bytes before the fi
107. ory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes MOVB abs16 Dn mem8 abs16 40 Di lt lt 4 An lt lt 2 Dm Operation Zero extends abs16 to 24 bits to obtain an absolute address pointer to memory sign extends the contents of that memory 1 byte to 24 bits and moves the result to register Dn Flag Changes Size Cycles Codes No changes Bytes 4 Cycles 2 CC Dn abs16 1 abs16 h B8 Dn 1 This instruction is supported by the assembler the assembler generates the two instruction codes for MOVBU abs16 Dn and Dn 52 MOVB Chapter2 Instruction Specifications MOVB abs24 Dn Operation mem8 abs24 gt Dn Sign extends the one byte contents of memory pointed to by 24 bits abs24 to obtain an absolute address pointer to memory and moves the result to register Dn Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 C4 Dn abs24 1 abs24 m abs24 h MOVB Dm An Flag Changes Size Cycles Codes Dm mem8 An Moves the lower 8 bits of register Dm one byte to the memory pointed to by register An Byte 1 Cycle 1 10 Dm lt lt 2 An MOVB 53 Chapter2 Instruction Specifications MOVB 48 An Operation Dm mem8 An d8 Sign extends the 8 bit displacement 128 to 127 adds it to register An to obtain a pointer to memory and
108. otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if ZF 1 and the lower 16 bits of the result are 0 reset otherwise 32 bit addition can be performed by combining an ADD instruction and ADDC instruction zero check on the 32 bit result can be done only with ZF after the ADDC instruction has been executed ADDC 71 Chapter2 Instruction Specifications AD D N Arithmetic Calculation Instructions ADDNF 8 Operation An imms gt Sign extends 8 bit immediate value imm8 128 to 127 to 24 bits adds it to register An and stores the result in register Flag Changes Size Cycles Codes No changes Bytes 3 Cycles 2 F5 imm8 1 8 bit immediate value is sign extended to 24 bits Flags do not change The primary application for this instruction is incrementing the stack pointer A3 past the stack frame at the end of a subroutine without changing the PSW flags reporting results See Section 1 2 in Chapter 3 Use of Instructions for an example 72 ADDNF Chapter2 Instruction Specifications Arithmetic Calculation Instruction J Operation Dm Dn gt Dm Subtracts the value of register Dn from the value of register Dm and stores the result in register Dm Size Cycles Codes Flag Changes Set if result taken as 24 bit signed value overflows reset otherwise Byte 1
109. oulevard Laguna Technopark Sta Rosa Laguna 4026 Philippines Tel 02 520 3150 Fax 02 843 2778 130301 Printed in JAPAN
110. peration mem24 An d8 gt Adds the value of register An and a sign extended 8 bit displacement 128 to 127 to obtain a pointer to memory and moves that value in memory three bytes to register Am Flag Changes Size Cycles Codes Cycles 2 Y Accessing to odd addresses in memory is not allowed 70 An lt lt 2 Am 48 416 mem24 An d16 Operation Adds the value of register An and a sign extended 16 bit displacement 32768 to 32767 to obtain a pointer to memory and moves that value in memory three bytes to register Am Flag Changes Size Cycles Codes 3 Accessing to odd addresses memory is not allowed F7 0 lt lt 2 416 1 d16 h 34 MOV Chapter 2 Instruction Specifications Operation mem24 An d24 gt Adds the value of register and the 24 bit displacement to obtain a pointer to memory and moves that val ue in memory three bytes to register Am Flag Changes Size Cycles Codes Bytes 5 Cycles 4 lt lt 2 d24 l d24 m d24 h 1 Accessing to odd addresses memory is not all owed Chapter2 Instruction Specifications MOV abs16 An mem24 abs16 An Operation Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory and moves that value in memory three bytes to register An Flag Changes S
111. ple the BLT instruction will branch when the previous CMP instruction encounters src gt dest as a signed 16 bit value Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch 0 48 Operation IF VF NF I ZF 1 then PC 2 d8 label gt PC IF VF I ZF 0 then 2 PC If VF is 0 and NF is 1 or if VF is 1 and NF is 0 or if ZF is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both NF and ZF are both VF and ZF are 1 and NF is 0 or if ZF is 1 then execution will continue with the instruction following the BLE instruction For example the BLE instruction will branch when the previous CMP instruction encounters src Z dest as a signed 16 bit value Flag Changes Size Cycles Codes 100 Bcc Bytes 2 Cycles 2 branch Cycle 1 non branch E3 d8 Chapter2 Instruction Specifications BGE label Operation IF VF NF 0 then PC 2 d8 label IF VF NF 1 then 2 PC If VF and NF are 0 or if VF and NF are 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If VF is 0 and NF is 1 or if VF is 1 and NF is 0 then execution will continue with the instruction following the BGE instruction
112. r Dn one byte to that memory Flag Changes Size Cycles Codes abs24 Operation Bytes 3 Cycle 1 C44 Dn abs16 abs16 h Dn meme8 abs24 Moves the lower 8 bits of register Dn one byte to the memory pointed to by the 24 bit absolute address abs24 Flag Changes Size Cycles Codes 56 MOVB Bytes 5 Cycles 3 F4 44 Dn abs24 abs24 m abs24 h Chapter2 Instruction Specifications Operation mem8 An Dm Zero extends the 1 byte contents of memory pointed to by register to 24 bits and stores the result in register Dm Flag Changes Size Cycles Codes No changes Byte 1 Cycle 1 30 lt lt 2 MOVBU 48 An Dm mem8 An d8 gt Dm Operation Sign extends the 8 bit displacement 128 to 127 adds it to register An to obtain a pointer to memory zero extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes Bytes 3 Cycles 2 F5 30 An lt lt 2 Dm 48 MOVBU 57 2 Instruction Specifications MOVBU 416 An Dm mem8 An d16 gt Dm Operation Sign extends the 16 bit displacement 32768 to 32767 adds it to register An to obtain a pointer to memory zero extends the contents of that memory 1 byte to 24 bits and moves the result to register Dm Flag Changes Size Cycles Codes MOVBU
113. rand Value Operand Value tion ADD DO D2 l Add the value in register DO to the value in register D2 a Operation D 2 D 0 D 2 The double operand instructions are MOV MOVX MOVB MOVBU ADD ADDC ADDNF SUB SUBC MUL MULU DIVU CMP AND OR XOR BTST BSET and BCLR a The CMP and BTST instructions do not store their calculation results a MOV instructions have the following six addressing modes Register direct Immediate imm8 imm16 imm24 Register indirect A n Register relative indirect d8 An d16 An d24 An Absolute abs16 abs24 Indexed register indirect Dm An Operand Forma 2 Chapter 1 Instruction 56 Overview Instruction Execution Time ELIO LLZEJ The instruction execution cycle count for this series is gi ven by the shortest num ber of cycles for an instruction when instructi ons already exist in the instruction queue For details refer to chapter 2 Instruction Specifications For details refer to the appendix Instruction Set For faster execution instructions are processed from a 3 level pipeline Therefore the actual execution cycle count will change depending on the combination of pre viously executing instructions and memory waits 1 Factors causing executi on cycles to change Register dependence Register dependence occurs when an instruction with register in d
114. ration code 6 1 Endian In instruction formats 3 6 and 7 a 16 bit immediate value imm16 16 bit abso lute address abs16 16 bit displacement d16 24 bit immediate value imm24 24 bit absolute address abs24 or 24 bit displacement d24 may follow after the instruction operation code In such cases each 8 bit portion appears in order with lower significance placed in a lower address little endian Ex The 16 bit immediate value x 1234 is placed in memory as follows for little endian Address 50 x 34 Address 51 x 12 18 Instruction Format Chapter 1 Instruction Set Overview 6 2 Instruction Codes ee Instruction formats have either 8 bit instruction operation code formats 1 3 or a 16 bit instruction operation code formats 4 7 In general the lower four bits of the instruction operation code will be coded the register numbers of data regis ters or address registers Of those four bits two bits will represent the register number of the source and two bits will represent the register number of the desti nation The representation of the source and destination register numbers will dif fer between bits 0 1 and bits 2 3 depending on the instruction Instruction format has a 16 bit instruction operation codes enter coded the register number in the second operation 7 0 Operation Register Register Data registers DO 00 Dic 0 132 5 7207 D3
115. rc dest as a un signed 16 bit value Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch EA d8 BLS label IF CF I ZF 1 then PC 2 d8 label gt IF CF I ZF 0 then PC 2 gt PC If CF is 1 or ZF is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If both CF and ZF are 0 then execution will Operation continue with the instruction following the BLS instruction For example the BLS instruction will branch when the previous CMP instruction encounters 2 dest as a signed 16 bit value Flag Changes Size Cycles Codes Cycles 2 branch 102 Bec Cycle 1 non branch E7 18 Chapter2 Instruction Specifications BCC label Operation IF CF 0 then PC 2 d8 label IF CF 1 then 2 PC If CF is 0 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127 bytes after If CF is 1 then execution will continue with the instruction following the BCC instruction For example the BCC instruction will branch when the previous CMP instruction encounters src dest as a un signed 16 bit value Flag Changes Size Cycles Codes No change Bytes 2 Cycles 2 branch Cycle 1 non branch E6 d8 BHI label IF CF I ZF
116. ries C Compiler User s Manual Usage Guide Describes the installation the commands and options of the C Compiler MN102L Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler MN102L Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler MN102L Series C Source Code Debugger User s Manual Describes the use of the C source code debugger gt Note For C Source Code Debugger for Windows this manual is not necessary MN102H Series C Source Code Debugger for Windows User s Manual Describes the use of the C source code debugger for Windows MN102H Series Installation Manual Describes the installation of the C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator Matsushita Please send any comments or questions regarding the contents of this manual to your nearest Semiconductor Design Center refer to the list of addresses at the back of the manual About This Manual 1 gt Layout of the manual Chapter 1 broadly consists of section titles and summaries text examples and important notes Chapter 2 consists of instruction commands operation descriptions and important notes The following diagrams show the layout and meaning of each page Section title Chapter Instruction Set Overview Example Information to aid un
117. rom the subroutine Example D Increment Decrement Of Address Registers ADD 2 0 0 Stack Pointer Operation Without Changing PSW Flags MOV 3 1 MOV 4A3 A2 MOVX 8 A3 D2 MOVX 12 A3 D3 ADDNF 16 RTS Chapter 3 Use Of Instructions 1 3 24 Pointer Operations Contents Pointer data is handled as 24 bit data Register saves restores for subroutines are always processed as pointer data 24 bits The data register Dn makes use of MOVX instructions Example Preprocessing and postprocessing of subroutine kyo int column char sou char dist SECTION TEXT CODE ALIGN 2 BYTESIZ 1 Byte size INTSIZ equ 2 Integer size PTRSIZ 4 Pointer size inear version LONGSIZ 4 size push D2 assign 0 push D3 assignpush 02 PTRSIZ push A1 assign push 03 PTRSIZ push A2 assignpush A1 PTRSIZ Stack frame pushwk assign 0 Storage area for D2 03 and 2 Subroutine work area follows X ener eee Parameters colmun assign work size PTRSIZ 2 contcolumn sou assign colmun INTSIZ swromadr dist assign sou PTRSIZ wramadr export _kyo _kyo DEFINE work_size 16 ADD work size Preprocessing MOV A1 push_A1 A3 MOV A2 push_A2 A3 storage MOVX D2 push D2 A3 MOVX D3 push_D3 A3 MOV colmun A3 D2 get column MOV sou A3
118. rst address of the next instruction to 127 bytes after If NX is 0 then execution will continue with the instruction following the BNSX instruction Flag Changes Size Cycles Codes Bytes 3 Cycles 3 branch Cycles 2 non branch 5 48 113 Chapter2 Instruction Specifications M P Branch Instructions JMP Operation PC 3 d16 label16 PC Branches unconditionally to the address indicated by label The branch range is from 32768 bytes before the first address of the next instruction to 32767 bytes after Flag Changes Size Cycles Codes l JMP label24 Operation PC 5 d24 label24 gt Branches unconditionally to the address indicated by label The branch range is from 8388608 bytes before the first address of the next instruction to 8388607 bytes after Flag Changes Size Cycles Codes 1 The assembler will determine whether 416 424 is optimazation processing a FC 416 1 d16 h Bytes 5 Cycles 4 F4 d24 1 d24 m d24 h 114 Chapter 2 Instruction Specifications JMP An EN E Flag Changes Size Cycles Codes An PC Branches unconditionally to the address indicated by register An Bytes 2 Cycles 3 FO An lt lt 2 JMP 115 Chapter2 Instruction Specifications Branch Instructions label16 4
119. s 8 bit immediate value 16 bit immediate value Low 8 bits of 16 bit immediate value High 8 bits of 16 bit immediate value 24 bit immediate value Low 8 bits of 24 bit immediate value Middle 8 bits of 24 bit immediate value High 8 bits of 24 bit immediate value 8 bit displacement 128 to 127 bytes 16 bit displacement 32768 to 32767 bytes Low 8 bits of 16 bit displacement High 8 bits of 16 bit displacement 1 24 bit displacement 8388608 to 8388607 bytes Low 8 bits of 24 bit displacement Middle 8 bits of 24 bit displacement High 8 bits of 24 bit displacement bit position bit 0 to 23 bit position bit 0 bit position bit 23 Logical AND Logical OR Exclusive OR Bit inversion Left shift Right shift Extended overflow flag Extended carry flag Extended negative flag Extended zero flag 2 temp label mem8 xxx mem16 xxx mem24 xxx src dest flag Carry flay Negative flag Zero flag CPU internal temporary register Replacement Calculation result Address 8 bit data value in memory specified by xxx 16 bit data value in memory specified by xxx 24 bit data value in memory specified by xxx Flag may change Flag will not change Flag will always be 0 Flag will always be 1 Flag changes undefined Value of source operand Value of destination operand
120. s 32768 to 32767 subtracts it from register An and stores the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 4 Set if a borrow is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise MES Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise F7 imm16 1 imm16 h 1 The 16 bit immediate value imm16 will be sign extended to 24 bits a SUB Operation An imm24 An Subtracts the 24 bit immediate value from the value of register An and stores the result in register An Flag Changes Size Cycles Codes Set if result taken as 24 bit signed value overflows reset otherwise Bytes 5 Set if a borrow is generated from the MSB reset otherwise Cycles 3 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise F4 6C An 24 1 imm24 m Set if result taken as a 16 bit signed value overflows reset otherwise imm24 h Set if a borrow is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result ar
121. shown below Example D Basic format AND imm PSW 4 bytes 3 cycles OR imm PSW 4 bytes 3 cycles Q Size and speed optimization SUB ZF set NF VF CF clear Dn clear 1 byte 1 cycle ADD 0 Dn VF CF clear 2 bytes 1 cycle XOR Dn Dn ZF set NF VF CF clear Dn clear 2 bytes 2cycles BTST O Dn ZF set NF VF CF clear 2 bytes 1 cycle CMP 0 Dn_ VF CF clear 2 bytes 1 cycle AND 0O Dn ZF set NF VF CF clear Dn clear 2 bytes 1 cycle AND DnjDn VF CF clear 2 bytes 2 cycles OR 0 Dn VF CF clear 2 bytes 1 cycle OR Dnjn VF CF clear 2 bytes 2 cycles NOT Dn VF CF clear Dn changes 2 bytes 2 cycles Programming Examples General Speed Optimization Size Optimization 141 Chapter 3 Use Of Instructions 2 25 Overlapping Interrupts Contents y The following example shows overlapping interrupts Example General information 30 Save registers to be used A1 4 A3 A2 8 A3 DO 12 A3 D1 16 A3 D2 20 A3 D3 24 A3 MDR DO DO 28 A3 x 0800 PSW Enable overlapping interrupts Interrupt process x f7ff PSW Disable overlapping interrupts 28 A3 DO Restore registers DO MDR 24 A3 D3 20 A3 D2 16 A3 D1 12 A3 DO 8 A3 A2 4 A3 A1 A3 A0 30 A3 142 Programming Examples General Speed Optimization Size Optimization Chapter 3 Use Of Instructions Deleted Instructions M 3 1 MOV Di An
122. smaller code size Size optimization Example MOV 0 DO 2 bytes 1 cycle SUB instruction gives smaller code size SUB 00 00 1 byte 1 cycle 2 13 Calculations With Memory Values Contents To calculate with values in memory the memory values must be moved to regis General ters for the calculations information Example Add the values in memory at addresses x f000 x f003 to addresses x f010 x f013 32 bit addition MOV x1000 A0 MOV xt010 A1 MOV 0 0 MOV 1 01 ADD 01 00 MOV DO AO MOV x 2 A0 D 2 1 1 ADDC 01 00 MOV DO x2 A0 134 Programming Examples General Speed Optimization Size Optimization Chapter 3 Use Of Instructions 2 14 BitSet Contents Normally OR instructions are used to set bits For byte accesses the BSET instruc tion can be used in addition to an OR instruction Size optimization a Use the BSET instruction to prohibit reception of bus release requests and interrupts during read modify writes Example D Word Access MOV x fc20 DO 3 bytes 1 cycle OR 4 00 8 bytes 2 cycles MOV DO x fc20 8 bytes 1 cycle Total 9 bytes 4 cycles The example below gives smaller code size MOV x fc20 A0 3 bytes 1 cycle MOV A0 DO 1 byte 1 cycle OR 4 DO 3 bytes 2 cycles MOV DO A0 1 byte 1 cycle Total 8 bytes 5 cycles Using OR Instruction For Byte Access MOVBU x fc20
123. splacements 916 are all sign extended 151 Instruction set Appendix MN102L SERIES INSTRUCTION MAP First byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B D E F 0 MOV Dm An 1 MOVB 2 3 MOVBU An Dm 4 MOV Dm d8 An 5 MOV Am d8 An 6 MOV d8 An Dm 7 MOV d8 An Am 8 MOV Dn Dm when src dest MOV imm8 Dn 9 ADD Dn Dm A SUB Dn Dm B EXTX Dn EXTXU Dn EXTXB Dn EXTXBU Dn C MOV Dn abs16 MOVB Dn abs16 MOV abs16 Dn MOVBU abs16 Dn D ADD imm8 An ADD imma imma MOV imm16 An BLT BGT BGE BLE BCS BHI BCC BLS BNE BRA label label label label label label label label label label CMP IR TE AD Extended code Extended NOP Extended code MOV imm16 Dn JMP F Extended code 2 bytes bytes G bytes 4 bytes label16 2 byte instructions Byte 1 FO Second byte Upper Lower 0 1 2 3 4 5 6 7 8 B A B C D E F 0 JMP A2 JSR A2 2 BSET Dm An 3 BCLR Dm An MOVB Di An D MOVBU Di An D MOVB Dn Di An 152 Instruction map Appendix 2 byte instructions Byte 1 F1 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 A B D E F MOV Di An D MOV Dm Di An 2 byte instructions Byte 1 F2 Second byte Upper Lower 0 1 2 3 4 5 6 7 8 9 B D E E 0 ADD Dm An 1
124. t lt 2 Dm ZF Set if the lower 8 bits of the result are 0 reset otherwise 1 When BSET instruction is executed bus line release request and interrupt request won t be accepted a BSET 97 Chapter2 Instruction Specifications CLR Bit Manipulation Instructions BCLR Dm An mem8 An amp Dm PSW 8 gt Operation Zero extends the 1 byte contents of memory pointed to by register An to 24 bits performs a logical AND with the value of register Dm and reflects the result in the PSW flags Also performs a logical OR of the zero extended value and the inverted value of register Dm and stores the result in the lower 8 bits in the memory pointed to by register An This instruction does not change the value of register Dm Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 2 VF Always 0 CF Always 0 Cycles 5 um F0 30 An lt lt 2 Dm ZF Set if the lower 8 bits of the first result are 0 reset otherwise 1 When BCLR instruction is executed bus line release request and interrupt request won t be accepted 98 BCLR Chapter2 Instruction Specifications CC Branch Instructions BEQ label Operation IF ZF 1 then PC 2 d8 label gt IF ZF 0 then PC 2 PC If ZF is 1 then branches to the address indicated by label The branch range is from 128 bytes before the first address of the next instruction to 127
125. ter2 Instruction Specifications E X T XB U Data move instruction Flag Changes Size Cycles Codes Dn amp x 0000FF Dn Zero extends the lower 8 bits of register Dn 1 byte to 24 bits and stores the result in register Dn EXTXBU 65 Chapter2 Instruction Specifications Arithmetic Calculation Instructions ADD Operation Dm Dn gt Dm Adds the value of register Dm to register Dn and stores the result in register Dm Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Byte 1 Set if a carry is generated from the reset otherwise Cycle 1 Set if the MSB of the result is 1 reset otherwise Set if the result is 0 reset otherwise Set if result taken as a 16 bit signed value overflows reset otherwise Set if a carry is generated from bit 15 reset otherwise Set if bit 15 of the result is 1 reset otherwise Set if the lower 16 bits of the result are 0 reset otherwise 90 Dn lt lt 2 Dm Operation gt Adds the value of register An to register Dm and stores the result in register An Flag Changes Size Cycles Codes Set if result taken as a 24 bit signed value overflows reset otherwise Bytes 2 Set if a carry is generated from the MSB reset otherwise Cycles 2 Set if the MSB of the result is 1 reset otherwise 7 Set if the result is 0 reset otherwise Set if result taken as a 1
126. tes 1 cycle MOV DO A3 1 byte 1 cycle MOVBU 1 3 01 3 bytes 2 cycles MOVB D1 A3 1 byte 1 cycle MOVB _ D0 1 A3 3 bytes 2 cycles MOV A3 DO 1 byte 1 cycle ADD 2 A3 2 bytes 1 cycle Total 13 bytes 9 cycles Use of multiply instruction gives smaller code MOV x 0100 D1 3 bytes 1 cycle MULU D1 DO 2 bytes 12 cycles MOV MDR D1 2 bytes 2 cycles ADD D1 DO 1 byte 1 cycle 8 bytes 16 cycles 140 Programming Examples General Speed Optimization Size Optimization optimization General information General information Size optimization Chapter 3 Use Of Instructions 2 22 Decimal Conversion Of 4 Bit Data I EIN 7 2 UNE a Contents Below is an example of decimal conversion of 4 bit data Example Data before conversion is in 10 DO register DO label x e DO Data after conversion is in register DO 2 23 Interrupt Disable Enable ER i a a a TT Contents The method for disabling and enabling interrupts is as follows However non maskable interrupts cannot be disabled Example D Disable interrupts IE 0 AND x f7ff PSW Enable interrupts IE 1 OR x 0800 PSW 2 24 PSW Flags Set Clear I a O u a Contents Example 1 shows the basic format for setting and clearing flags in the PSW but other instructions can also be used as
127. th Carry All logical calculation instructions are performed on data registers The AND and OR instructions can also operate with immediate data on the processor status word PSW For a left shift use ADD Dn Dn where Dn is the same for both operands 8 Instruction Functions Chapter1 Instruction Set Overview 3 4 Bit Manipulation Instructions The bit manipulation instructions are as follows BTST Bit Test BSET Bit Test and Set BCLR Bit Test and Clear BTST instructions test data register contents with immediate data The result of a logical OR of the data register and immediate value will be reflected in the flags BSET and BCLR instructions test memory while the bus is locked and interrupts disabled reflect the result in the flags and then set clear the specified BSET and BCLR instructions access memory as 8 bytes Instruction Functions 9 Chapter 1 Instruction Set Overview 3 5 Branch Instructions FD qid utl The branch instructions are as follows BEQ Branch Equal BNE Branch Not Equal BGT Branch Greater Than BGE Branch Greater or Equal BLE Branch Less or Equal BLT Branch Less Than BHI Branch Higher BCC Branch Carry Flag Clear BLS Branch Low or Same BCS Branch Carry Flag Set BVC Branch Overflow Flag Clear BVS Branch Overflow Flag Set BNC Branch Negative Flag Clear BNS Branch Negative Flag Set BRA Branch Always BEQX Branch Equal by Extended
128. tional instructions specification WArthmetic Calculation Instruction 7 instructions singed maltiplication 12 instructions set clear 1 or multiple bits of memory 6 instructions bit test amp branch of memory 1 instruction inversion of Saturation control specification 1 bit control flag for Saturation control specification Stores the lower 24 bits of product in register Dm and the upper 16 bits in register MDR MULQ Dn Dm Introduction to the section lt About This Manual 2 gt Instruction function and type VX OX NX ZX NF CF NF ZF changes Chapter2 Instruction Spyifications Instruction for OR Logical Calculation Instructions OR Dn Dm Operation Dm I Dn amp x O0FFFF Dm Performs a bitwise logical OR of the lower 16 bits or registers Dm and Dn and stores the result in the lower 16 bits of register Dm The upper 8 bits of register Dm will not change Operation description Flag Changes Size Cycles Codes 7 No change Bytes 2 VF Always 0 Pap CF Always 0 Cycles 2 NF Set if bit 15 of the result is 1 reset otherwise F3 104Dnec 24Dm ZF Set if the lower 16 bits of the result are 0 reset otherwise OR imm8 Dn Operation Dnlimm8 gt Dn Performs a bitwise logical OR of zero extends the 8 bit immediate value immi to 16 bits and the lower 16 bits of re
129. upper 8 bits of register Dm will not change Flag Changes Size Cycles Codes Bytes 2 VX CX NX ZX Nochange VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F3 00 Dn lt lt 2 Dm ZF Set if the lower 16 bits of the result 0 reset otherwise AND imm Operation Dn amp x FF0000 imm8 Dn Performs a bitwise logical AND of zero extends the 8 bit immediate value imm8 to 16 bits and the lower 16 bits of register Dn and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 3 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F5 00 Dn imm8 ZF Set if the lower 16 bits of the result are 0 reset otherwise 1 8 bit immediate value imm8 will be zero extended to 16 bits 86 AND Chapter2 Instruction Specifications AND 16 Dn Operation Dn amp x FF0000 imm16 Performs a bitwise logical AND of the 16 bit immediate value imm16 and the lower 16 bits of register Dn and stores the result in the lower 16 bits of register Dn The upper 8 bits of register Dn will not change Flag Changes Size Cycles Codes VX CX NX ZX Nochange Bytes 4 VF Always 0 Cycles 2 CF Always 0 NF Set if bit 15 of the result is 1 reset otherwise F7 00 0 imm16 1 imm16 h
130. user must know when using instructions in the MN 102L series This information can be divided into two categories 1 Minimum knowledge Required 2 Programming examples general speed optimization size optimization Each itemof information consists of the following Contents This describes what the program does Also explains such conditions as memory model for use Category Categories are shown by the following icons Precaution Thisis a precaution that the user absolute y should know Speed optimization D This is a technique for increasing code speed Size optimization Thisis atechnique for decreasing code size General information Example These actual assembly language program examples The code size and cycle count are shown after each instruction as shown below instruction code size cycle count 1 The execution cycle counts shown in the code examples indicate the minimum cycles for each instruction so actual counts may increase depending on condi tions for use Note that these cycle counts may differ from those listed in the appendix Cycle counts will also differ for single chip mode memory expansion mode and processor mode Specific cycle counts should be measured with an emula tor Notes Regarding Use of Instructions Precaution
131. ushita Electronics Corporation s Sales Department About This Manual This manual describes in detail the instruction set for the MN102L Series Chapter 1 explains the functions basic format and instruction execution times of the instruction set Chapter 2 describes the operation of each instruction and the flags changed by each Chapter 3 provides cautions and warnings for the use of instructions The appendix contains a summary of the instruction set and an instruction map Searching for information This manual has four types of indexing to speed up searches for necessary information 1 To find a start of chapter refer to the index at the start of the manual 2 To find a title refer to the table of contents at the start of the manual 3 The chapter title for each page is shown at the top of the right hand page and the section title is shown at the bottom You can get a brief idea of the contents while flipping through the pages 4 find an instruction refer to the index at the end of the manual Also an instruction index can be found on the right hand pages so you can search for an instruction while flipping through the pages mRelated manuals Matsushita provides the following manuals related to the product covered in this manual e MN102L Series LSI User s Manual Describes the device hardware MN102L Series Cross assembler User s Manual lt Describes the assembler syntax and notation gt MN102L Se
132. y and moves the lower 16 bits of register Dm two bytes to that memory Flag Changes Size Cycles Codes No changes Bytes 4 Cycles 2 F7 80 An lt lt 2 Dm 416 1 d16 h 1 Accessing to odd addresses memory is not allowed MOV Dm d24 An Operation Dm mem16 An d24 Adds the value of register An and a 24 bit displacement to obtain a pointer to memory and moves the lower 16 bits of register Dm two bytes to that memory Flag Changes Size Cycles Codes No changes Bytes 5 Cycles 3 F4 00 An lt lt 2 Dm 124 1 d24 m d24 h 1 Accessing to odd addresses in memory is not allowed 28 Chapter 2 Instruction Specifications Dm Di An Operation Dm mem16 An Di Adds the value of register An and Di to obtain a pointer to memory and moves the lower 16 bits of register Dm two bytes to that memory Flag Changes Size Cycles Codes No changes Bytes 2 Cycles 2 F1 0 lt lt 4 lt lt 2 1 Accessing to odd addresses memory is not allowed MOV abs16 Operation Dn mem16 abs16 Zero extends abs16 to 24 bits to obtain an absolute address pointing to memory and moves the lower 16 bits of register Dn two bytes to that memory Flag Changes Size Cycles Codes No changes Bytes 3 Cycle 1 C0 Dn abs16 1 abs16 h 1 Accessing to odd addresses in memory is not allowed 39 Chapter2 Instruct

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