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CR8F612X

1. Memory and register map CR8F612X Table 12 General hardware register map continued Address Block Register label Register name Weg 0x00 525F TIMI CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 es TIM1 CCR2H TIMI capture compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1_CCR8L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCRAL TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 0x00 5270 to Reserved area 147 bytes 0x00 52FF 0x00 5300 TIM5 CR1 TIM5 control register 1 0x00 0x00 5301 TIM5 CR2 TIM5 control register 2 0x00 0x00 5302 TIM5 SMCR TIM5 slave mode control register 0x00 0x00 5303 TIM5 IER TIMB interrupt enable register 0x00 0x00 5304 TIM5 SR1 TIM5 s
2. 1 TS SOS Rleak 1 ESR is the equivalent series resistance and ESL is the equivalent inductance Doc ID 15590 Rev 1 45 88 Electrical characteristics CR8F612X 9 3 2 Supply current characteristics The current consumption is measured as described in Figure 6 on page 42 Total current consumption in run mode The MCU is placed under the following conditions e AN UO pins in input mode with a static value at Vpp or Vas no load e All peripherals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and T Table 19 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 fcpu waeren 16 MHz HSE user ext clock 16 MHz 2 2 35 HSI RC osc 16 MHz 1 7 2 Supply current in run fopy fMASTER 128 HSE user ext clock 16 MHz 0 86 more ecde 125 KZ HSI RC osc 16 MHz 0 7 0 87 executed from RAM fcpu fwasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu fMAsTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN HSE crystal osc 16 MHz 4 5 mA CPU MASTER 16 MHz HSE user ext clock 16 MHz 4 3 4 75 HSI RC osc 16 MHz 3 7 4 5 Supply eu IMASTER HSI RC osc 16 MHz 8 2 0 84 1 05 current in run 2 MHz mode code f Br 7128 executed from CPU MASTER 9 HS
3. d Table 8 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 defined as UBC memory write protected 0x02 Pages 0 to 1 defined as UBC memory write protected Page 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Pages 0 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 AFR 7 0 Refer to Table 9 and Table 10 for alternate function remapping decriptions of bits 7 2 and 1 0 respectively OPT3 HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG w
4. 16 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system e Full documentation and a wide choice of development tools e Advanced core and peripherals made in a state of the art technology Table 1 CR8F612X access line features 2 o 3 o o 2 2 D a e E 8 2 8 O E og Slo gt ele 88 EIS i z Z g EI 5 9 al gt GTA 2 2 Bai 3 3 5 ox ox sEQ 5 ES Device 8 Q Eo 882 E Peripheral set c a EIB 91 a 298 a oz at Es a5 8 di ls Els 2 2 5 8 o AQ S z E ois iL a E E LL CR8F6126T 27 7 20 8K a 4K Multipurpose timer TIM1 32 28 7 3 640 SPI I2C UART CR8F6125 28 24 24 7 3 7 20 8K 640 1K window WDG CR8F6124 24 20 20 7 0 7 18 8K 0 1K independent WDG 640 ADC 3 12 1 CR8F6123 20 16 16 7 0 8K gad 1K PWM timer TIMS CR8F6122 14 10 10 7 0 5 8 8K ead TK 8 bit timer TIM6 1 Including 21 high sink outputs 2 Noread while write RWW capability ky Doc ID 15590 Rev 1 9 88 Block diagram CR8F612X 3 Block diagram Figure 1 Block diagram Reset block Wm 116 MH2 K gt Clock controller Reset L Reset 4 RC int 16 MHz Detector POR BOR Al RC int 128 kHz c rrr r Clock to peripherals and core Window WDG CR8F core S Independent WDG 8 Kbytes lt gt m 5 gt
5. Symbol Ratings Conditions Class Geier Unit V Electrostatic discharge voltage TA 25 C conforming to A 4000 ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage Tal QFP32 package VESD CDM 25 C conforming to IV 1000 Charge device model SD22 C101 1 Data based on characterization results not tested in production Doc ID 15590 Rev 1 1577 CR8F612X Electrical characteristics d Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 49 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A Ta 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Doc ID 15590 Rev 1 77 88 Package characteristics CR8F612X 10 78 88 Package characteristics To meet environmental requirements ST offers these devices
6. Ay CR8F612X 16 MHz CR8F 8 bit MCU up to 8 Kbytes Flash 1 Kbyte RAM 640 bytes EEPROM 10 bit ADC 2 timers UART SPI 12C Features Core m 16 MHz advanced CR8Fcore with Harvard architecture and 3 stage pipeline m Extended instruction set Memories m Program memory 8 Kbytes Flash data retention 20 years at 55 C after 10 kcycles m Data memory 640 bytes true data EEPROM endurance 300 kcycles m RAM 1 Kbytes Clock reset and supply management m 2 95 to 5 5 V operating voltage m Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC W Clock security system with clock monitor m Power management Low power modes wait active halt halt Switch off peripheral clocks individually m Permanently active low consumption power on and power down reset Interrupt management m Nested interrupt controller with 32 interrupts m Up to 28 external interrupts on 7 vectors Timers m Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization April 2009 Preliminary data Y E E Er LQFP32 7x7 VFQFPN32 5x5 m 16 bit general purpose timer with 3 CAPCOM channels IC OC or PWM m 8 bit basic timer with 8 bit prescaler Auto wake up timer m 2 watchdog timers Window watchd
7. Electrical characteristics 9 9 1 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vas Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5 Figure 5 Pin loa
8. 4 CR8F6124 SOP DIP 24 UART1_RX AIN6 HS PD6 NRST OSCIN PA1 OSCOUT PA2 Vss VCAP VDD TIM5 CH3 HS PA3 TIM1_ETR AIN3 HS PB3 TIM1_CH3N AIN2 HS PB2 TIM1_CH2N AIN1 HS PB1 TIM1_CH1N AINO HS PBO PD5 PD4 HS AIN5 UART1_RX HS BEEP TIM5 CH PD3 HS AIN4 TIM5 CH2 ADC ETR PD2 HS PD1 HS SWIM PC7 HS SPI_MISO PC6 HS SPI MOSI o JI OV RW IN a PC5 HS SPI SCK PC4 HS TIM1 CH4 CLK CCO PC3 HS TIM1 CH3 o s o s PC2 HS TIM1_CH2 N PC1 HS TIM1 CH1 UART1 CK Doc ID 15590 Rev 1 25 88 d Option bytes CR8F612X Figure6 CR8F6122B M SOP DIP 14 UART1_RX AIN6 HS PD6 1 5 HS 1 OSCIN PA1 Us 2 HS TIM1 CH2 BO HS AINO CH1N TIM1 AIN1 CH2N TIM1 AIN2 CH3N TIM1 HS HS PD5 PD1 PC2 HS OSCOUT PA2 4 PC1 HS TIMi CH1 UART1 CK PBO HS PB1 PB2 1 HS 2 HS HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Figure 7 CR8F6123 SOP 20 UART1 RX AIN6 HS PD6 J 1e 20 3 PDS HSJ AIN5 UART1 TX NRST J 2 19E3 PD4 HS BEEP TIM5
9. 5202 SPI ICH SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 GC CR1 DC control register 1 0x00 0x00 5211 I2C CR2 DC control register 2 0x00 0x00 5212 I2C FREQR ec frequency register 0x00 0x00 5213 I2C_OARL DC Own address register low 0x00 0x00 5214 I2C OARH DC Own address register high 0x00 0x00 5215 Reserved 0x00 5216 I2C DR DC data register 0x00 0x00 5217 lc DC SR1 I2C status register 1 0x00 0x00 5218 I2C SR2 DC status register 2 0x00 0x00 5219 l2C SR3 IC status register 3 OXOX 0x00 521A I2C ITR ec interrupt control register 0x00 0x00 521B I2C CCRL I2C Clock control register low 0x00 0x00 521C I2C CCRH I2C Clock control register high 0x00 0x00 521D I2C TRISER I2C TRISE register 0x02 0x00 521E I2C PECH DC packet error checking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F 34 88 Doc ID 15590 Rev 1 D CR8F612X Memory and register map Table 12 General hardware register map continued Address Block Register label Register name ai 0x00 5230 UART1_SR UART1 status re
10. Based on characterization results not tested in production 60 88 Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics Figure 20 Typical Vj and Vj vs Vpp 4 temperatures 40 0 6 25 C 5 85 C 1250 _4 2 gt 3 zi gt 2 1 0 T T T 25 3 35 4 45 5 55 6 Voo V Figure 21 Typical pull up resistance vs Vpp 4 temperatures 40 C 60 25 C 85 C 55 125C gi s 8 a as K 4 45 8 a i 4 E a 35 30 T T T T T 25 3 3 5 4 45 5 5 5 6 Vee V Figure 22 Typical pull up current vs Vpp 4 temperatures 140 m gt 2 e z 3 5 80 E a 60 o i 25 C E 40 85 C E i bo Vet 12570 se oL i 0 1 2 3 4 5 6 d Doc ID 15590 Rev 1 61 88 Electrical characteristics CR8F612X Table 37 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 10 VoL Output low level with 8 pins sunk lio 10 mA Vpp 5V 2 Output high level with 4 pins sourced lig 4 mA Vpp 3 3 V 2 10 S Von Output high level with 8 pins sourced lig 10 mA Vpp 5 V 2 8 1 Da
11. VO X X X HS O3 X X Port C2 Timer 1 channel 2 channel 3 AFR1 0 AER 3 22 PES TIMI SKO TELI VO X X X HS O3 X X Port C3 Timer 1 channel 3 Timer 1 TIM1 CHIN a inverted channel 1 AFR7 Analog input 2 PC4 TIM1 CH4 Timer 1 channel 4 AFR2 23 CLK CCO AIN2 VO X X X HS O3 X X Port C4 configurable clock Timer 1 TIM1 CH2N output inverted channel 2 AFR7 Timer 5 24 ME cnr UO X X X HS O3 X X Port C5 SPI clock channel 1 E AFRO Timer 1 25 uc vo x X x IHs os X x Portce re channel 1 E AFRO lt imer 26 Ba a vo x x x Hs 03 X X PortC7 Mida w phannel 2 ES AFRO deg igurable 27 FEO TIMI BRIN vo x x x Hs os X x Port po fimer 1 break Lech CLK CCO input output AFR5 28 PD1 SWIM vo X x x Hs 04 x x pant pnl SWIM data interface Analog input 3 AFR2 29 PD2 AIN3 TIM5_CH3 l O X X X HS OS X X Port D2 Ti imer 5 channel 3 AFR1 Analog input 4 PD3 AIN4 TIM5_CH2 Timer 5 channel 30 ADC KTR VO X X X IHS O3 X X Port D3 2 ADC external trigger ky Doc ID 15590 Rev 1 23 88 Pinout and pin description CR8F612X Table 5 VFQFPN32 LQFP32 pin description continued Alternate function Default alternate after function remap option bit Pin name floating Main function after reset 2 3 o pe LLI High sink PD4 TIM5 CH1 BEEP Timer 5 channel UART Port D4 clock UART1_CK 1 BEEP
12. addition the CR8F is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition CR8F application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of CR8F microcontrollers via the CR8F single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of me
13. and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals or to synchronize with TIM5 or TIM6 Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM5 16 bit general purpose timer 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 3 individually configurable capture compare channels PWM mode Interrupt sources 3 x input capture output compare 1 x overflow update Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM6 Doc ID 15590 Rev 1 ky CR8F612X Product overview 4 12 TIM6 8 bit basic timer 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source CPU clock Interrupt source 1 x overflow update Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM5 Table 3 TIM timer features Timer Timer eounter Prescaler Counting CAPCOM Complem Ext synchronization size bits mode channels outputs trigger S chaining TIM1 16 Any integer OR Up down 4 3 Yes 1 to 65536 p Any power of 2 from 1 TIM5 16 to 32768 Up 3 0 No Yes Any power of 2 from 1 TIM6 8 to 128 Up 0 0 No 4 13 Ana
14. clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Doc ID 15590 Rev 1 15 88 Product overview CR8F612X 4 8 4 9 4 10 4 11 16 88 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Fourindependent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge
15. in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Doc ID 15590 Rev 1 1577 CR8F612X Package characteristics 10 1 Package mechanical data 10 1 1 LQFP package mechanical data d Figure 42 32 pin low profile quad flat package 7 x 7 32 D1 D3 24 Pin 1 identification 1 CN ccc C ES E1 E ag Sh ON j 5V ME Table 50 32 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Doc ID 15590 Rev 1 79 88 Package characteristics CR8F612X 10 1 2 80 88 VFQFPN package mechanical data Figure 4
16. interrupt controller registers 39 Voltage characteristics nn 42 Current characteristics unaua aeaee 43 Thermal characteristics x eR R R a R R R RRR RR R RRR RRR RRR n 43 General operating conditions 44 Operating conditions at power up power down ssssssssssssss 45 Total current consumption with code execution in run mode at Vpp 2 5 V 46 Total current consumption with code execution in run mode at Vpp2 3 8V 47 Total current consumption in wait mode at Vpp5V eee 48 Total current consumption in wait mode at Vpp 2 N elles 48 Total current consumption in active halt mode at Vpp 25V eee eee eee 49 Total current consumption in active halt mode at Vpp z 233N a 49 Total current consumption in halt mode at Von B VY nursan nenene 50 Total current consumption in halt mode at Vpp 32N eee eee 50 Wakeup times sisse am Santka kn kula eee da ek DES ee eee 50 Total current consumption and timing in forced reset state 51 Peripheral current consumption e e cece re 51 HSE user external clock characteristics liliis 55 HSE oscillator characteristics liliis 56 HSI oscillator characteristics 2l eh 57 LSI oscillator characteristics liil eh 58 RAM and hardware registers sss re 59 Flash program memory data EEPROM memory 59 I O static characteristics liliis en 60 Output driv
17. must be at least 8 MHz to achieve max fast DC speed 400kHz Data based on standard DC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL d Doc ID 15590 Rev 1 71 88 Electrical characteristics CR8F612X 9 3 10 72 88 10 bit ADC characteristics Subject to general operating conditions for Vpp faster and Ta unless otherwise specified Table 43 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 2 95 to 5 5 V 1 4 fanc ADC clock frequency MHz Vpp 45t05 5V 1 6 Vain Conversion voltage range Vas Vpo V Internal bandgap reference _ VBGREF voltage Vpp 2 95to5 5V 1 19 1 22 1 25 V Internal sample and hold Cape capacitor 3 pF fap 4 MHz 0 75 tg Minimum sampling time us fADC 6MHz 0 5 terap Wake up time from standby 7 us Minimum total conversion time hos Mhz tconv including sampling time 10 bit fanc 6 MHz 2 33 US resolution 14 TE 1 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the
18. program m Single wire debug interf Debug SWIM lt gt Flash 640 bytes data EEPROM Ke GE spi 400 Kbit s c 8 Mbit s G LIN master SPI emul mb VARTI KE 1 Kbytes RAM X Up to 4 CAPCOM 16 bit advanced control channels timer TIM1 Cae 3 complementary Address and data bus outputs lt 16 bit general purpose Ke Up to Timer TIM5 3 CAPCOM channels 8 bit basic timer Up to 7 lt gt channels gt I ADEI NS 1 2 4 kHz lt gt beep lt Beeper AWU timer D 10 88 Doc ID 15590 Rev 1 CR8F612X Product overview 4 4 1 Product overview The following section intends to give an overview of the basic features of the CR8F612X functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit CR8F The 8 bit CR8F core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed add
19. second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 8 in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 8 Kbytes minus UBC e User specific boot code UBC Configurable up to 8 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation Data Data memory area 640 bytes EEPROM memory Option bytes r Programmable area from 64 bytes UBC area 1 page up to 8 Kbytes Remains write protected during IAP in 1 page steps Low density Flash program memory 8 Kbytes Program memory area Write access possible for IAP Doc ID 15590 Rev 1 13 88 Product overview CR8F612X 4 5 14 88 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a globa
20. 0 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vit nrst NRST Input low level voltage 1 0 3 V 0 3 x Vpp y 1 0 7 x Vpp ViH NAST NRST Input high level voltage U Vb 0 3 V VOL NAST NRST Output low level voltage 1 lo 2 MA 0 5 Reuwrst NRST Pull up resistor 30 40 60 kQ trPNAST NRST Input filtered pulse 9 75 ns tinrp nrst NRST Input not filtered pulse 3 500 ns toP NRST NRST output pulse 3 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vj vs Vpp 4 temperatures 40 C 6 e 25 C 5 85 C 125 C 4 33 E 0 L 2 1 0 7 T 7 7 T 7 1 25 3 35 4 45 5 5 5 6 Wor V Figure 34 Typical NRST pull up resistance vs Vpp 4 temperatures 40C 60 25 C 85 C e 125 C tri as E 45 4 NS EE Z 40 35 30 T T T T T T 1 2 5 3 3 5 4 45 5 5 5 6 Voo V 66 88 Doc ID 15590 Rev 1 ky CR8F612X Electrical characteristics Figure 35 Typical NRST pull up current vs Vpp 4 temperatures NRESET Pull Up current 120 100 40 C 25 C 125 C 85 C 3 WO The reset network shown i
21. 0 Ra a tt 2 00 oj S 4009 a S 0 0095 N aa p A nu a s nz Ea 1 00 2 00 3 00 4 00 5 00 l 2 25 3 3 5 4 45 5 55 6 d 58 88 Doc ID 15590 Rev 1 CR8F612X Electrical characteristics 9 3 5 Memory characteristics RAM and hardware registers Table 34 RAM and hardware registers Symbol VRM Parameter Conditions Min Data retention mode Halt mode or reset 2 8 V Typ Max Unit 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 18 on page 45 for the value of Vit max Flash program memory data EEPROM memory Table 35 Flash program memory data EEPROM memory Symbol Parameter Operating voltage all modes execution write erase Conditions fcpu 16 MHz Min 2 95 Typ Max 5 5 Unit Standard programming time including erase for byte word block 1 byte 4 bytes 64 bytes Fast programming time for 1 block 64 bytes 6 6 3 33 Erase time for 1 block 64 bytes 3 33 ms Erase write cycles program memory Ta 85 C 10k Erase write cycles data memory Data retention program and data memory after 10k erase write cycles at Ta 55 C Ta 125 C Tper 55 C 300 k 20 1M RET Ipp Data retenti
22. 0 MHz O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T True open drain OD Open drain PP Push pull Reset state is shown in bold Table 5 VFQFPN32 LQFP32 pin description Input utput E up CE Alternate g 9 function Pi 9l o sit c9 Default alternate after Pin name el e El Zl 3 3r no Ei ale Sl 3 al a z5 function remap Zi 215 Si 8 DI aj 5 option si bit x Ol Analog input 6 1 Posaneuant AK _RX io x X HS O3 E E Port D6 UART1 data Timer 1 2 PD7 TLI TIM1 CH4 UO X HS X Port D7 Top level interrupt channel 4 AFR6 ee See JC CNN NS ED ITUNES ET reas ms s macscour wol x x e ellene de LLLI LI eneen 7 VCAP var s 1 8 V regulator capacitor we sp pa power supp AFR1 0 Hii l A N UART1 PF4 UART1 RX i AER1 0 SPI master slave select AFR1 UART1 data transmit Timer 5 channel 3 10 d Doc ID 15590 Rev 1 21 88 Pinout and pin description CR8F612X Table 5 VFQFPN32 LQFP32 pin description continued Input Output Ga Alternate 25 function Pin o S e 0 Default alternate after Pin name EIS EP fv 3t no C za sc v i9g a a 5 func
23. 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 crs CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register Xx 0x00 50CD CLK SWIMCCR SWIM clock control register XO 0x00 50CE to Reserved area 3 bytes 0x00 50DO 0x00 50D1 WEG WWDG CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to Reserved area 13 bytes 00 50DF 0x00 50E0 IWDG KR IWDG key register 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer Ox3F register 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to Reserved area 12 bytes 0x00 50FF Doc ID 15590 Rev 1 33 88 Memory and register map CR8F612X Table 12 General hardware register map continued Address Block Register label Register name i 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00
24. 0x00 5341 TIM6_CR2 TIM6 control register 2 0x00 0x00 5342 TIM6_SMCR TIM6 slave mode control register 0x00 0x00 5343 TIM6_IER TIM6 interrupt enable register 0x00 0x00 5344 TIM6 TIM6_SR TIM6 status register 0x00 0x00 5345 TIM6_EGR TIM6 event generation register 0x00 0x00 5346 TIM6 CNTR TIM6 counter 0x00 0x00 5347 TIM6 PSCR TIM6 prescaler register 0x00 0x00 5348 TIM6 ARR TIM6 auto reload register OxFF 0x00 5349 to Reserved area 153 bytes 0x00 53DF 0x00 53E0 to ADC1 ADC _DBxR ADC data buffer registers 0x00 0x00 53F3 0x00 53F4 to Reserved area 12 bytes 0x00 53FF Doc ID 15590 Rev 1 37 88 Memory and register map CR8F612X Table 12 General hardware register map continued Address Block Register label Register name duran status 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0x00 0x00 5405 ADC_DRL ADC data register low 0x00 0x00 5406 ADC_TDRH ADC Schmitt iron disable register 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register 0x00 ADC1 low 0x00 5408 contd ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low OxFF 0x00 540A ADC LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC lo
25. 2X Electrical characteristics Total current consumption in active halt mode Table 23 Total current consumption in active halt mode at Vpp 5 V Conditions i Maxat85 Max at Symbol Parameter Main voltage Flash Clock Typ soi 425 e Unit regulator model source MVR HSE crystal osc 1030 Operating 16 MHz mode LSI RC osc 128 kHz 200 260 300 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD H active halt mode LSI RC osc mode 128 kHz 150 200 230 Operating 66 85 110 ott mode LSI RC osc E 128 kHz Power down 10 20 40 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 24 Total current consumption in active halt mode at Vpp 3 3 V Conditions Maxat Maxat l Symbol Parameter Main voltage Flash Clock Typ 85 scil 125 cl Unit regulator model source MVR 2 HSE crystal osc 550 Operating 16 MHz mode LSI RC osc 128 kHz 200 260 290 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD H active halt mode LSI RC ose H mode 128 kHz 150 200 230 perang 66 80 105 Bi mode LSI RC osc Power down 128 kHz 10 18 35 mode 1 Data based on characterization results not tested in production 2 Configured
26. 3 32 lead very thin fine pitch quad flat no lead package 5 x 5 Seating plane C 4 E2 Bottom view 42 ME Table 51 32 lead very thin fine pitch quad flat no lead package mechanical data mm inches Dim Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 0315 0 0354 0 0394 Al 0 0 02 0 05 0 0008 0 0020 A3 0 20 0 0079 0 18 0 25 0 30 0 0071 0 0098 0 0118 D 4 85 5 00 5 15 0 1909 0 1969 0 2028 D2 3 20 3 45 3 70 0 1260 0 1457 E 4 85 5 00 5 15 0 1909 0 1969 0 2028 E2 3 20 3 45 3 70 0 1260 0 1358 0 1457 e 0 50 0 0197 L 0 30 0 40 0 50 0 0118 0 0157 0 0197 ddd 0 08 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Doc ID 15590 Rev 1 D CR8F612X Package characteristics Figure 44 Recommended footprint for on board emulation date 0 8mm 0 032 4mm 0 157 Pol 0 5mm i 1 65mm 0 065 m HL 0 9mm 0 035 0 3mm 0 012 M 4mm 0 157 ai15319 Bottom view 1 Drawing is not to scale Figure 45 Recommended footprint without on board emulation ET aen mu E 3 30 Ele HI 2 30 num E 0 55 E SR GEN I 3 30 4 1 Drawing is not to scale 2 Di
27. 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 9FFF 0x00 A000 0x02 7FFF RAM 1 Kbyte Reserved 640 bytes data EEPROM Reserved Option bytes Reserved GPIO and periph reg see Table 11 and Reserved CPU SWIM debug ITC registers see Table 13 l 32 interrupt vectors Flash program memory 8 Kbytes Reserved Doc ID 15590 Rev 1 D CR8F612X Memory and register map 8 2 d Register map Table 11 I O port hardware register map Address Block Register label Register name Weer 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 PortA PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C i
28. 5590 Rev 1 19 88 Pinout and pin description CR8F612X 5 Pinout and pin description Figure3 CR8F612X VFQFPN32 LQFP32 pinout AINA TIM5 CH2 ADC ETR SPI MOSI AINS UART1 TX SPI MISO BEEP TIM5 CH1 TIMI BKIN PD4 HS PD3 HS PD2 HS PD1 HS SWIM PDO HS PC7 HS PC6 HS E e o N N co N NI N Su NE RO PC5 HS SPI SCK PC4 HS TIM1_CH4 CLK_CCO PC3 HS TIM1_CH3 PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 UART1_CK PE5 SPI NSS PBO HS AINO CH1N TIMI e 21 PDS HS UART1 RX AIN6 HS PD6 TLI HS PD7 NRST OSCIN PA1 OSCOUT PA2 VSS VCAP VDD OW JO LI E VM I o 1 111213141516 PF4 PB7 PB6 T PB5 T PB4 HS PA3 Ho HS PB3 TIM5_CH3 l2C SDA l2C SCL HS PB2 TIM1 ETR AIN3 TIM1 CH3N AIN2 PB1 HS AIN1 CH2N_TIM1 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function D 20 88 Doc ID 15590 Rev 1 CR8F612X Pinout and pin description Table 4 Legend abbreviations Type I Input O Output S Power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 1
29. 8 Auto wakeup counter 16 4 9 Beeper per Pr TTT TTT TTT TTT TTT TITT TT 16 4 10 TIMI 16 bit advanced control timer 16 4 11 TIM5 16 bitgeneralpurposetimer 16 4 12 TIMO 8 bit basic timer nnua anaana 17 4 13 Analog to digital converter ADC1 17 4 14 Communication interfaces 17 4141 UARV csse Red SA Eae e x RR bee IRL RR RUN SR ud 18 BAA o AA 18 Er A o AA 19 5 Pinout and pin description ssssss 20 5 1 Alternate function remapping ssa aeaaaee 24 6 Interrupt vector mapping sssssssssrsee 25 7 Option DytesS ww TETUR 26 8 Memory and register map s sssssssss s 30 2 88 Doc ID 15590 Rev 1 ky CR8F612X Contents 8 1 MEON Map TP ne pus kus aks snu uamska o as 30 8 2 gig MM pan R EE duels baa a ee wees o a 31 9 Electrical characteristics sss 41 9 1 Parameter conditions s s ss s s sss 41 9 1 1 Minimum and maximum values 41 9 1 2 Typical values ersa 0 R a 9 RR 0 R R R Ra RR R LRR RR RE RRR E NR 41 9 1 3 Typical CUFVes sz sasa rea Pie eR OPERE EK ib ERR AU 41 9 1 4 Loading capacitor 60 E 6 ces ove idee a tanba ar kule knn ae dea 41 9 1 5 Pin input voltage K e RR R RR RRR RRR RRR RRR RRR RRR RRR 42 9 2 Absolute maximum ratings aana 42 9 3 Operating conditions ce
30. 95 4 te 45 C E B gege 1 75 Luj 1 65 4 Figure 12 Typ Ipp wri VS Vpp HSE user external clock fcpy 16 MHz 0 8 IDD WFI HSE mA 0 6 04 0 2 250 85 C mmm 125 C t 45 C 2 25 3 3 5 4 45 5 5 5 6 No Ui Figure 13 Typ Ipp wen VS fcpu HSE user external clock Vpp 5 V P mA IDD WFI HSE 0 8 4 0 6 0 4 0 2 4 25 C 85 C 125 C 45 C Feru MHz Doc ID 15590 Rev 1 53 88 Electrical characteristics CR8F612X 54 88 Figure 14 Typ Ipp wF vs Vpp HSI RC osc fepy 16 MHz ma IDD_WFI_HSI 25 C 85 C 125 C 45 C 2 2 5 3 3 5 4 Fceu MHz Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T Table 30 HSE user external clock characteristics Symbol Parameter Conditions Min Max Unit fen clock source 0 16 MHz Vase a input pin high level 0 7xVop Vue 0 3 V Vuen Di input pin low level Ves 0 3 x Vpp bi LEAK uer OSCIN input leakage current Vss lt Vin lt Vpp 1 1 HA 1 Data based on characterization results not tested in production Figure 15 HSE external clock source TT GN dk 4 d
31. C 1 5 125 C Fa Vo V 25 Doc ID 15590 Rev 1 63 88 d Electrical characteristics CR8F612X 64 88 Figure 27 Typ Vo Vpp 3 3 V high sink ports 40C 25 C 1 25 85 C 125 C lo mA Figure 28 Typ Vo E Vpp 5 V high sink ports 25 lo mA Figure 29 Typ Vpp Von Vpp 3 3 V standard ports 40 C a 25 C 85 C 125 C 274 Voo Mu V lou mA Doc ID 15590 Rev 1 1577 CR8F612X Electrical characteristics Figure 30 Typ Vpp Von 9 Vpp 5 V standard ports 4C m 25 C 85 C 15 125 C Voo WH V lo mA Figure 31 Typ Vpp Von Vpp 3 3 V high sink ports Voo Gu V lo mA Figure 32 Typ Vpp Von Vpp 5 V high sink ports 49C 25 C 85 C 15 125 C Voo Mu V 25 ky Doc ID 15590 Rev 1 65 88 Electrical characteristics CR8F612X 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 4
32. CH1 OSCIN PA1 C3 3 185 PD3 HS AIN4 TIM5 CH2 ADC ETR OSCOUT PA2 C 4 177 PD2 HS VSS 15 16E3 PD1 HS SWIM VCAPE 6 15 PC7 HS SPI_MISO VDD r3 7 14E3 PO6 HS SPI MOSI TIM5 CH3 HS PA3 LI 8 1395 PC5 HS SPI_SCK 12C_SDA T PB5 Ca 1255 PC4 HS TIM1_CH4 CLK_CCO 12C_SCL T PB4 CJ 10 115 PC3 HS TIM1_CH3 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 5 1 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 7 Option bytes When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 d Doc ID 15590 Rev 1 25 88 CR8F612X Interrupt vector mapping 6 Interrupt vector mapping Table 6 Interrupt mapping Description aem OTT Vector adres
33. I RC osc 16 MHz 0 72 0 9 125 kHz Flash fopu fuasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu fuasTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d 46 88 Doc ID 15590 Rev 1 CR8F612X Electrical characteristics Table 20 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 8 fcpu MASTER 16 MHz HSE user ext clock 16 MHz 2 2 3 HSI RC osc 16 MHz 1 5 2 Supply o fopy fuasTER 128 125 HSE user ext clock 16 MHz 0 81 kHz executed HSI RC osc 16 MHz 0 7 0 87 from RAM fcpu fMASTER 1 28 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN HSE crystal osc 16 MHz 4 mA fcpu IMASTER 16 MHz HSE user ext clock 16 MHz 3 9 4 7 HSI RC osc 16 MHz 3 7 4 5 Supply Cru IMASTER HSI RC osc 16 MHz 8 2 0 84 1 05 current in run 2 MHz mode code executed fopu ImasTER 128 125 ist RC osc 16 MHz 072 og kHz from Flash fopu luasren 128 HSI RC osc 16 MHz 8 0 46 0 58 15 625 kHz i fcpu MASTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in pr
34. RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level Interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes veel 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 EXTI5 Port F interrupt Yes Yes 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIMI p 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 13 TIM5 TIM5 update overflow trigger 0x00 803C 14 TIM5 TIM5 capture compare 0x00 8040 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 ae I2C interrupt Yes Yes 0x00 8054 20 Reserved 0x00 8058 21 Reserved 0x00 805C JE 3 AR 0100 soo 23 TIM6 TIM6 update overflow trigger 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Reserved 0x00 806C to 0x00 807C 1 Except PA1 Dr Doc ID 15590 Rev 1 25 88 Option bytes CR8F612X 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular f
35. SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority register 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F Doc ID 15590 Rev 1 39 88 Memory and register map CR8F612X 40 88 Table 13 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name ean 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BKIRL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F 1 Accessible by debug module only Doc ID 15590 Rev 1 D CR8F612X
36. ange of gang and automated programming solutions from third party tool developers already supplying programmers for the CR8F family Doc ID 15590 Rev 1 ky CR8F612X Revision history 13 Revision history Table 53 Document revision history Date 30 Apr 2009 Revision 1 Initial revision Changes Doc ID 15590 Rev 1 87 88 CR8F612X Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third
37. by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register 1577 Doc ID 15590 Rev 1 49 88 Electrical characteristics CR8F612X Total current consumption in halt mode Table 25 Total current consumption in halt mode at Vpp 5 V Symbol Parameter Conditions Typ ap cet PRO Unit Flash in operating mode HSI clock after wakeup 63 75 105 Supply current in A DD H halt mode Flash in power down mode HSI clock after 6 0 15 35 H wakeup i 1 Data based on characterization results not tested in production Table 26 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Ed Ka Ac Unit Supply current in Flash in operating mode HSI clock after wakeup 60 75 100 e DD H H halt mode Flash in power down mode HSI clock after wakeup 4 5 12 30 1 Data based on characterization results not tested in production Low power mode wakeup times Table 27 Wakeup times Symbol Parameter Conditions Typ Max Unit See t Wakeup time from wait note WU WF mode to run mode fopu fuAsrER 16 MHz 0 56 Flash in operating 4 6 mode MVR voltage 4 regulator on East in power 30 5 i Wakeup time active halt down mode HSI us WU AH mode to run model Flash in operating after wakeup 4866 5 MVR voltage mode 4 regulator off Flash in pow
38. by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU
39. cation running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Table 47 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz 0 1MHz to 30 MHz 2 3 Vppz 5V Peak level Ta 25 C 30 MHz to 130 MHz 10 10 dBuV EMI LQFP32 package 130 MHz to 1 GHz 5 7 Conforming to SAE J 1752 3 SAE EMI level SAE EMI level 2 5 2 5 1 Data based on characterization results not tested in production 76 88 Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin One model can be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 48 ESD absolute maximum ratings
40. ccuracy with Rain lt 10 ko Rain Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fADC 2 MHz 1 6 TBD E r Total unadjusted error fADC 4 MHz 1 9 TBD fApc 2 MHz 1 TBD lEg Offset error i fADC 4 MHz 1 5 TBD fapc 2 MHz 1 3 TBD IEgl Gain error LSB fADC 4 MHz 2 TBD fapc 2 MHz 0 7 TBD IEp Differential linearity error fapc 4 MHz 0 7 TBD fapc 2 MHz 0 6 TBD IE I Integral linearity error E fADC 4 MHz 0 8 TBD 1 Data characterization in progress Doc ID 15590 Rev 1 73 88 Electrical characteristics CR8F612X 74 88 Figure 40 ADC accuracy characteristics A Ee L Sosy y a Vopa V LE 1022 DDA SSA i 1LSB lt c x 1021 IDEAL 1024 z 2 1 7 s st 1 p oy 7 1 7 K P K p T4 d 7 1 L 2 1 6 i T 7 1 1 4 e mu 7 SH 44 9 SR i L 3 Tz 7 Kd En 2 Ee Z gt 1 o ou 1 LSBiDEAL 1 H LI ji J Dipig oj 0 1 2 3 4 5 6 7 1021102210231024 Vssa VDD 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity erro
41. close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 28 external interrupts on 7 vectors including TLI Trap and reset interrupts Doc ID 15590 Rev 1 1577 CR8F612X Product overview 4 4 Flash program and data EEPROM memory e 8 Kbytes of Flash program single voltage Flash memory e 640 bytes true data EEPROM e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A
42. conte OxFF register 2 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection OxFF register 0x00 505F FLASH IAPSR Flash in application programming 0x00 status register 0x00 5060 to Reserved area 2 bytes 0x00 5061 0x00 5062 Flash FLASH RUE ash program memory unprotection ep register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to Reserved area 59 bytes 0x00 509F 0x00 50A0 mi EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 to Reserved area 17 bytes 0x00 50B2 0x00 50B3 RST RST SR Reset status register XX 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50C0 So CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte Doc ID 15590 Rev 1 D CR8F612X Memory and register map d Table 12 General hardware register map continued Address Block Register label Register name aaa status 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register 0x00 50C6 CLK CKDIVR Clock divider register 0x18
43. ctronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 88 88 Doc ID 15590 Rev 1 ky
44. ding conditions CBSE PIN S0pF Doc ID 15590 Rev 1 41 88 Electrical characteristics CR8F612X 9 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6 Figure 6 Pin input voltage l CR8F PIN S NN 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 14 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage 0 3 6 5 Input voltage on true open drain pins Vss 0 3 6 5 V VIN Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 T IVssx Vss Variations between all the different ground pins 50 see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 76 1 All power Vpp and ground Vss pins must always be connected to the external power supply 2 liNu PIN must never be exceeded This is implicitly insured if Vjy maximum is respected If Vum maximum cannot be respected the injection current must be limited externally to the liy pix value A positive injection is induced b
45. e ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your CR8F microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for CR8F Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Haisonance C compiler for CR8F Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com e CR8F assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the CR8F Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your CR8F For production environments programmers will include a complete r
46. e the formula Ppmax Timax Ta ja see Section 10 2 Thermal characteristics with the value for T Jmax given in Table 17 and the value for Oj4 given in Table 52 Thermal characteristics 3 TJmax is given by the test limit Above this value the product behavior is not guaranteed Figure 7 fcpumax Versus V np fopu MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY 77 GUARANTEED Ta 40 to 125 r 8 ei l l 4 A ET Zi 0 l l SUPPLY VOLTAGE V Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics 9 3 1 d Table 18 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 co typp us V Vpp fall time rate 2 co Reset release T trEMP delay Vpp rising 1 7 ms Power on reset Vit threshold 2 6 2 7 2 85 g Brown out reset VIT threshold 2 5 2 65 2 8 Brown out reset VHYS BOR 70 mV hysteresis 1 Reset is always generated after a trgyp delay The application must ensure that Vpp is still above the minimum ooperating voltage Vpp min when the trepp delay has elapsed VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin Cgxz is specified in Table 17 Care should be taken to limit the series inductance to less than 15 nH Figure 8 External capacitor Cey7 ESR C ESL e
47. end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics d Table 44 ADC accuracy with Ran lt 10 KQ Vpp 5 V Symbol Parameter Conditions Typ Max Unit fanc 2 MHz 1 6 TBD IEr Total unadjusted error fapo 4 MHz 2 2 TBD fanc 6 MHz 2 4 TBD fanc 2 MHz 1 1 TBD IE Offset error fApc 4 MHz 1 5 TBD fapc 6 MHz 1 8 TBD fanc 2 MHz 1 5 TBD IEgl Gain error 9 fapo 4 MHz 2 1 TBD LSB fanc 6 MHz 2 2 TBD fanc 2 MHz 0 7 TBD Epl Differential linearity error fanc 4 MHz 0 7 TBD fapc 6 MHz 0 7 TBD fanc 2 MHz 0 6 TBD IE Integral linearity error fapc 4 MHz 0 8 TBD fanc 6 MHz 0 8 TBD Data characterization in progress 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for Ij j piy and Zlins Piny in Section 9 3 6 does not affect the ADC accuracy Table 45 ADC a
48. er 50 down modell i Wakeup time from halt Flash in operating mode 9 52 WU H 3 UH mode to run mode Flash in power down mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 6 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization 50 88 Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics d Total current consumption and timing in forced reset state Table 28 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state ppr SCH UA Vpp 3 8 V 300 tRESETBL Reset pin release to vector fetch 150 US 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vgs Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T HSI internal RC fcpy fMASTER 16 MHz Vpp 5 V Table 29 Peripheral current consumption Symbol Parameter Typ Unit Ippcrim1 TIM1 supply current 210 Ipo rims TIM5 supply current 130 Ipp TIM6 TIM6 timer supply current 50 Ipo uanri UARTI supply current 120 UA Ippse SPI supply current 45 Ipp i c CC supply current 65 IDD ADC1 ADC1 supply current when co
49. ev 1 ky CR8F612X Package characteristics 10 2 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 11 Ordering information on page 84 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tamax 75 C measured according to JESD51 2 lbDmax 8 MA Vpp 5 V e Maximum 20 I Os used at the same time in output at low level with lot 8 mA VoL 0 4 V Pintmax 8 MA x 5 V 400 mw Piomax 20 X 8 MA x 0 4 V 64 mW This gives PinTmax 400 mW and Pjomax 64 mW Ppmax 400 mw 64 mW Thus Ppmax 464 mW Using the values obtained in Table 52 Thermal characteristics on page 82 T jmay is calculated as follows for LQFP32 59 C W TJmax 75 C 59 C W x 464 mW 75 C 27 C 1029 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 Doc ID 15590 Rev 1 83 88 CR8F612X CR8F development tools 12 12 1 CR8F development tools Development tools for the CR8F microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In
50. gister Coh 0x00 5231 UART1_DR UART1 data register xxh 0x00 5232 UART1 BRR1 UART1 baud rate register 1 00h 0x00 5233 UART1 BRR2 UART1 baud rate register 2 00h 0x00 5234 UART1 CR1 UART1 control register 1 00h 0x00 5235 UART1 UART1 CR2 UART1 control register 2 00h 0x00 5236 UART1 CR3 UART1 control register 3 00h 0x00 5237 UART1_CR4 UART1 control register 4 00h 0x00 5238 UART1_CR5 UART1 control register 5 00h 0x00 5239 UART1_GTR UART1 guard time register 00h 0x00 523A UART1_PSCR UART1 prescaler register 00h 0x00 523B to Reserved area 21 bytes 0x00 523F 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1 SRI TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 FARAON In mode register 0x00 TIM1 0x00 5259 TIM1_CCMR2 TIM1 paini mode register 0x00 0x00 525A TIM1 CCMR3 TIM1 didi mode register 0x00 0x00 525B TIM1 CCMR4 TIM1 ddl as mode register 0x00 0x00 525C TIM1 CCER1 TIM1 HUANG enable register 0x00 0x00 525D TIMI CCER2 TIM1 ae AG enable register 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 ky Doc ID 15590 Rev 1 35 88
51. igure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 ky Block diagram asy uci sas bore nu askas d SEN d EE ET EE NEEN oa 10 Flash memory organisation 13 CR8F612X VFQFPNS2 LQFP32 pinout eee 20 Mere elo o do beetle a oe d eei ee eas oa dew th eae E 30 Pin loading conditions gas a 0 ee RI I R K 41 Pin input voltage erres nesr ieradies eera EE EAE EEEE EEEa 42 foPUmax VEFSUS VDD 44 External capacitor CEXT l l esles sss a 45 Typ Ipp Ruw VS Vpp HSE user external clock fepy 16MHZ 52 Typ Ipp Ruw VS fopu HSE user external clock Vpp 25 V ee eee eee eee 52 Typ IDD RUN VS Vpp HSI RC OSC fcpu 16 MHZ E AEn KALUGA 53 Typ Ipp wri VS Vpp HSE user external clock fepy 16 MHz 58 Typ Ipp wri VS fopu HSE user external clock Vpp lt B V 58 Typ IDD WFI VS Vpp HSI RC OSC fopu 16MHZ ss 54 HSE external clock source 55 HSE oscillator circuit diagram lilii 56 Typical HSI accuracy at Vpp 5Vvs5temperatures ss esos 57 Typical HSI frequency variation vs Vpp E 4 temperatures 58 Typical LSI frequency variation vs Vpp E 4temperatures 58 Typical Vj and Vj vs Vpp 4 temperatures eese 61 Typical pull up resistance
52. illator 25 C Ta B5 C 2 5 2 Yo factory calibrated 2 95 SVpp 25 5 V 2 3 40 C Ta 125 C 450 5 t HSI oscillator wakeup time 40 a su HSI including calibration H HSI oscillator power 2 opman consumption Lon Ba p 1 Referto application note 2 Data based on characterization results not tested in production 3 Subject to further characterization to give better results 4 Guaranteeed by design not tested in production Figure 17 Typical HSI accuracy at Vpp 5 V vs 5 temperatures 3 00 7 2 00 1 00 0 00 max 1 00 4 min 2 00 3 00 4 4 00 4 5 00 T T 40 0 25 85 125 Doc ID 15590 Rev 1 57 88 Electrical characteristics CR8F612X Figure 18 Typical HSI frequency variation vs Vpp 4 temperatures a 25 C 85 C 1 00 c m 125 0 45 C 0 50 0 00 A 0 50 Pap plo B n a a i 1 00 1 50 2 00 T r T r r T 1 25 3 3 5 4 45 5 55 6 Vo V Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 33 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 110 128 150 kHz Luten LSI oscillator wake up time 7 Hs Ibos LSI oscillator power consumption 5 HA Figure 19 Typical LSI frequency variation vs Vpp 4 temperatures 25 C 85 C 5 00 Y 125 C 4 00 45 C 3 0
53. imization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 46 EMS data Symbol Parameter Conditions Level class Vpp 3 3 V Ta 25 C fMASTER 16 MHz HSI clock 2 B conforming to IEC 1000 4 2 V Voltage limits to be applied on any I O pin FESD to induce a functional disturbance Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 C Verte applied through 100 pF on Vpp and Vss fuasrEn 16 MHz HSI clock 4 A pins to induce a functional disturbance conforming to IEC 1000 4 4 Doc ID 15590 Rev 1 75 88 Electrical characteristics CR8F612X Electromagnetic interference EMI Based on a simple appli
54. indow watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active Doc ID 15590 Rev 1 27 88 Option bytes CR8F612X 28 88 Table 8 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles Table 9 CR8F612X alternate function remapping bits 7 2 Option byte no OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions 1 Port C3 alternate function TIM1 CHIN port C4 alternate function TIM1_CH2N AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 1 Port D7 alternate function TIM1 CH4 AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 1 Port DO alterna
55. ing current standard ports 00 cee eee 62 Output driving current true open drain porte 62 Output driving current high sink porte 62 NRST pin characteristics 66 SPI characteristics 68 2C characteristics uuu usui EE 71 ADC characteristics 72 ADC accuracy with RAIN lt 10kQ Vpp SON enous decent d kr Ko wae RIDE EI ERES DU RR SUR 73 ADC accuracy with Rain lt 10 kQ RAIN Von e EEN 73 EMS Gata isc ano san swe hte kalao meta oro mo atin Des aa EA Kee aren ee 75 EMI data ss ss kerran ties d actes ra sede edge had kvak kulera Gwe hee is 76 ESD absolute maximum ratings sasaaa aeaea ren 76 Doc ID 15590 Rev 1 5 88 List of tables CR8F612X Table 49 Table 50 Table 51 Table 52 Table 53 6 88 Electrical sensitivities anaana 77 32 pin low profile quad flat package mechanical data 79 32 lead very thin fine pitch quad flat no lead package mechanical data 80 Thermal characteristics rr 82 Document revision history 87 Doc ID 15590 Rev 1 ky CR8F612X List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 F
56. kan Rc Aqu Edu ae Rd 86 12 2 2 Candassemblytoolchains 86 12 3 Programming tools osos don o RE ER REN EE RR 86 13 REVISION history 2223 s x x x x x 9 a do do re e s lk RN 87 4 88 Doc ID 15590 Rev 1 1577 CR8F612X List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 br CR8F612X access line features 9 Peripheral clock gating bit assignments in CLK PCKENRT 2 registers 14 TIMtimerfeatures ssssssssssssrsessrsessroooso 17 Legend abbreviations 0 000 RR rn 21 VFQFPN32 LQFP32 pin description a aaaea 21 Interrupt mapping essc tees 25 Option bytes sss sss sketas Pda uw R er dox bue Redon A CHO GLb ank bona dos 26 Option byte description sasaaa eaea 27 CR8F612X alternate function remapping bits 7 2 ee 28 CR8F612X alternate function remapping bits DO 29 I O port hardware register map RII III 31 General hardware register map 32 CPU SWIM debug module
57. l erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fyasTER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as s
58. log to digital converter ADC1 CR8F612X products contain a 10 bit successive approximation A D converter ADC1 with up to 7 external and 1 internal multiplexed input channels and the following main features e Input voltage range 0 to Vpp e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where x number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Internal reference voltage on channel AINT This internal reference is constant and can be used for example to monitor Vpp It is independent of variations in Vpp and ambient temperature Ta e Analog watchdog interrupt e External trigger input e Trigger from TIMI TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented e UART1 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 1 master capability e SPI Full and half duplex 8 Mbit s e BC Up to 400 Kbit s 1577 Doc ID 15590 Rev 1 17 88 Product overview CR8F612X 4 14 1 4 14 2 18 88 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchron
59. mensions are in millimeters ky Doc ID 15590 Rev 1 81 88 Package characteristics CR8F612X 10 2 10 2 1 82 88 Thermal characteristics The maximum chip junction temperature T imas must never exceed the values given in Table 17 General operating conditions on page 44 The maximum chip junction temperature T imas in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X ya Where Tamax is the maximum ambient temperature in C e dia is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pyomax PDmax Pintmax Promax e Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pi omax represents the maximum power dissipation on output pins Where Pyomax Nool Vpp Vow y lon taking into account the actual Vo lo and VoH loH of the I Os at low and high level in the application Table 52 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient d Qa LQFP 32 7 x 7 mm bid uiid Thermal resistance junction ambient P Dan VFOFPN 82 5 x5 mm Le CIW 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Doc ID 15590 R
60. mory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for CR8F Doc ID 15590 Rev 1 85 88 CR8F development tools CR8F612X 12 2 12 2 1 12 2 2 12 3 86 88 Software tools CR8F development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for CR8F which are available in a free version that outputs up to 16 Kbytes of code CR8F toolset CR8F toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST visual develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverag
61. n 81 CR8F612X ordering information scheme cee eee 84 Doc ID 15590 Rev 1 7 88 Introduction CR8F612X 8 88 Introduction This datasheet contains the description of the CR8F612X features pinout electrical characteristics mechanical data and ordering information e Forcomplete information on the CR8F microcontroller memory registers and peripherals please refer to the CR8F microcontroller family reference manual RM0016 e Forinformation on programming erasing and protection of the internal Flash memory please refer to the CR8F Flash programming manual PM0051 e Forinformation on the debug and SWIM single wire interface module refer to the CR8F SWIM communication protocol and debug module user manual UM0470 e Forinformation on the CR8F core please refer to the CR8F CPU programming manual PM0044 Doc ID 15590 Rev 1 1577 CR8F612X Description 2 Description The CR8F612X 8 bit microcontroller offers 8 Kbytes Flash program memory plus integrated true data EEPROM The CR8F microcontroller family reference manual RM0016 refers to devices in this family as low density They provide the following benefits e Reduced system cost Integrated true data EEPROM for up to 300 k write erase cycles A High system integration level with internal clock oscillators watchdog and brown out reset e Performance and robustness
62. n Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 36 Otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection External reset circuit optional Vpp Rpu Do Filter CR8F Internal reset Doc ID 15590 Rev 1 67 88 Electrical characteristics CR8F612X 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 41 are derived from tests performed under ambient temperature faster frequency and Vpp supply voltage conditions tyaster 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 41 SPI characteristics Symbol Parameter Conditions Min Max Unit fsck Master mode 0 8 sc SPI clock frequency S MHz Losch Slave mode 0 TBD ec SPI clock rise and fall time Capacitive load C 30 pF 25 hsc Lues NSS setup time Slave mode 4 X tMASTER Lues NSS hold time Slave mode 70 3 tusCkH SCK high and low time Master mode tsck 2 15 tsck 2 15 tw SCKL t 3 Master mode 5 su MI Data input setup time tsu S1 Slave mode 5 t 3 Master mode 7 ns TD Data input hold time this Slave mode 10 tas
63. n page 72 5 When several inputs are submitted to a current injection the maximum liy pi is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with lj py maximum current injection on four I O port pins of the device Table 16 Thermal characteristics Symbol Ratings Value Unit Terme Storage temperature range 65 to 4150 Ty Maximum junction temperature 150 d Doc ID 15590 Rev 1 43 88 Electrical characteristics CR8F612X 9 3 44 88 Operating conditions Table 17 General operating conditions Symbol Parameter Conditions Min Max Unit fcpu Internal CPU clock frequency 0 16 MHz Vpp Standard operating voltage 2 95 5 5 V lt lt Cext VCAP external capacitor m peca 470 3300 nF Power dissipation at LQFP32 330 Ta 85 C for suffix 6 VFQFPN32 550 Pp mW Power dissipation at LQFP32 83 TA 125 C for suffix 3 VFQFPN32 110 Ambient temperature loro Maximum power dissipation 40 85 suffix version Ta AMBIEN temperature SP Maximum power dissipation 40 125 C suffix version 6 suffix version 40 105 Tj Junction temperature range 3 suffix version 40 130 9 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 2 To calculate Pp TA us
64. n results not tested in production tsU HSE is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 16 HSE oscillator circuit diagram Resonator Cia OSCIN Resonator OSCOUT fuse to core Consumption control CR8F 56 88 HSE oscillator critical g formula Omorit 2x IIx HSE x R 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 1 C C Grounded external capacitance 9m gt gt 8mcrit Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics 9 3 4 d Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and T High speed internal RC oscillator HSI Table 32 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz User trimmed with Accuracy of HSI oscillator EN register 10 96 for given Vop and Ta conditions ACCus Vpp 5 V Ta 25 C 2 5 9 130 Von 5 V E 3 3 o Accuracy of HSI osc
65. nput pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0x00 0x00 5016 Port E PE_DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 Doc ID 15590 Rev 1 31 88 Memory and register map CR8F612X 32 88 Table 12 General hardware register map Address Block Register label Register name nesel status 0x00 501E to Reserved area 60 bytes 0x00 5059 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary
66. nverting 1000 1 Data based on a differential lnn measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production Data based on a differential lnn measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production conversions Not tested in production Doc ID 15590 Rev 1 Data based on a differential Ipp measurement between reset configuration and continuous A D 51 88 Electrical characteristics CR8F612X Current consumption curves Figure 9to Figure 14 show typical current consumption measured with code executing in RAM Figure 9 Typ Ipp Ruw VS Vpop HSE user external clock fcpy 16 MHz IDD run HSE mA 23 2 25 N XI N a N N o a N to a to E a eo 25 C 85 C 125 C Aer N 25 4 5 55 Voo V Figure 10 Typ Ipp nuw VS fcpu HSE user external clock Vpp 5 V mA IDD run HSE 25 25 C 85 C 125 C dr 45 C Fceu MHz 52 88 D Doc ID 15590 Rev 1 CR8F612X Electrical characteristics d Figure 11 Typ Ipp RUN vs Vpp HSI RC OSC fepy 16 MHz IDD run HSI mA 25 C 2 uM 85 C 125 C 1
67. o wsHour BIT6 OUT Bou OUT me Sl a pi SI INPUT man IN l Li l Lem O IN ai14135 SCK Input 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp d Doc ID 15590 Rev 1 69 88 Electrical characteristics CR8F612X Figure 39 SPI timing diagram master mode SCK Input SCK Input High NSS input e e scky a CPHA 0 CPOL 0 f ae CPHA 0 i 3 Y ix XM TA IM rit MISO _ f SCK b gt T rik mom Xo OUTUT BOUT BIT1 OUT LSB OUT ty mo h MO ex ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp 70 88 Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics 9 3 9 I2C interface characteristics Table 42 IC characteristics Standard mode I2C Fast mode CH Symbol Parameter Unit Min 2 Max Min Max twscii SCL clock low time 4 7 1 8 US tw SCLH SCL clock high time 4 0 0 6 tsu spaA SDA setup time 250 100 tsp SDA data hold time 06 09 900 tsoa SDA and SCL rise time 1000 300 ns tsc WSDA SDA and SCL fall time 300 300 hac thsra START condition hold time 4 0 0 6 US Luem Repeated START condition setup time 4 7 0 6 lsusro STOP condition setup time 4 0 0 6 US STOP to START condition time bus lw STO STA free 4 7 1 3 us Cp Capacitive load for each bus line 400 400 pF 1 fwaster
68. o VA Data output access time Slave mode 3 X MASTER tasso Data output disable time Slave mode 25 tuso Data output valid time Slave mode after enable edge TBD tuo Data output valid time Master mode after enable edge 30 tao Slave mode after enable edge 270 Data output hold time mo Master mode after enable edge 112 1 Parameters are given by selecting 10 MHz I O output frequency 2 Data characterization in progress 3 Values based on design simulation and or characterization results and not tested in production 4 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 68 88 Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics Figure 37 SPI timing diagram slave mode and CPHA 0 NSS input A tc T SCK Input OO i ST dt O 77 o A lt v He ISCH t ta SO I th SO pa Pa dis SO r T X BITO NSO MISO OUTPUT MSB OU our our OUT su Sl atin Ya X INPUT ths ai14134 Figure 38 SPI timing diagram slave mode and CPHA 1 NSS input fi CPHA 1 ES N N i CPOL 0 i CPHA 1 t ii l i CPOL 1 l e e i M axem tg p SCK at di th SO Za is SO e MISO OUTPUT ab
69. oduction 2 Default clock configuration measured with all peripherals off ky Doc ID 15590 Rev 1 47 88 Electrical characteristics CR8F612X Total current consumption in wait mode Table 21 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 n UE S HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fcpu f 128 Ipp wr current in HSI RC osc 16 MHz 0 7 0 88 mA wait mode fcpu fuasTER 128 2 45 COE Ms HSI RC osc 16 MHz 8 0 45 0 57 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 22 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 fcpu fMasTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fopu f 128 Ippiwri current in uui en HSI RC osc 16 MHz 0 7 0 88 mA wait mode fcpu fuasTER 128 2 46 625 kH HSI RC osc 16 MHz 8 0 45 0 57 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 48 88 Doc ID 15590 Rev 1 D CR8F61
70. og and independent watchdog Communications interfaces m UART with clock output for synchronous operation Smartcard IrDA LIN master mode m SPlinterface up to 8 Mbit s m DC interface up to 400 Kbit s Analog to digital converter ADC m 10 bit 1 LSB ADC with up to 7 multiplexed channels 1 internal channel scan mode and analog watchdog lOS m Upto28l Os on a 32 pin package including 21 high sink outputs m Highly robust I O design immune against current injection m Development support Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging Doc ID 15590 Rev 1 1 88 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice www st com Contents CR8F612X Contents 1 Introduction mE 8 2 Description ou sa ss kea NAA ERE DIKE WAL KEEP ped D RA eee 9 3 Block diagram sua eron ck s sa RUE ed cab ae eu RRR RR R RRR RRR bo 10 4 Product overview xe ausu j eg RC Re C OUS NEU o RR tn 11 4 1 Central processing unit CR8F 02 ce ee 11 4 2 Single wire interface module SWIM and debug module DM 12 4 3 Interrupt controller 535 css e e eed es XE Reha eee RR ced 12 4 4 Flash program and data EEPROM memory 13 45 Clock controller a nn REN EEN KH PBA UK teases EET EE hoe P ER 14 4 6 Power management auaa anaana 15 4 7 Watchdog timers aaua aa 15 4
71. on data memory after 300k erase write cycles at Ta 125 C Supply current Flash programming or erasing for 1 to 128 bytes Tret 85 C cycles years mA 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte d Doc ID 15590 Rev 1 59 88 Electrical characteristics CR8F612X 9 3 6 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 36 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 V 0 3 x Vpp V Input high level Vpo 5V Vin voltage 0 7 x Von Vpp 0 3 V V Vays Hysteresis 700 mV Rp Pull up resistor Vpp 5 V Vin Vss 30 45 60 kl Fast I Os 20 ns luj Rise and fall time Load 50 pF R F 10 90 Standard and high sink I Os 125 ns Load 50 pF Digital input leakage likg pic P 9 Vas S VIN lt Vpp 1 HA Analog input likg ana Beers sudaj Vss 5 Vin S Von Se Leakage current in likg inj VO Injection current x4 mA 1 1 Hysteresis voltage between Schmitt trigger switching levels
72. oon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM6 PCKEN10 Pe PCKEN24 Reserved PCKEN20 Reserved Doc ID 15590 Rev 1 br CR8F612X Product overview 4 6 4 7 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals
73. orm OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 7 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the CR8F Flash programming manual PM0051 and CR8F SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 7 Option bytes Option Option Option bits Factory Addr namie byte default no 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 00h ROP 0x4801 User boot OPT1 UBC 7 0 00h oxago2 code UBC NOPTI NUBC 7 0 FFh 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function ox4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 0x4805h OPT3 Reserved HSITRIM 00h Miscellaneous EN HW HW HALT option d NLSI 0x4806 NOPT3 Reserved NEISI S krm NANG FFh TRIM _EN W HW _HALT EXT CKAWU PRS PRS 0x4807 OPT4 Reserved 00h CLK SEL Ci CO Clock option NEXT NCKAWUS NPR NPR 0x4808 NOPT4 Reserved FFh CLK EL SC1 SCO 0x4809 HSE clock OPTS HSECNT 7 0 00h Ox480A Startup NOPT5 NHSECNT 7 0 FFh 26 88 Doc ID 15590 Rev 1 ky CR8F612X Option bytes
74. ous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes A Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpy 16 LIN master mode SPI Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame Maximum speed 8 Mbit s fyastER 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin Doc ID 15590 Rev 1 ky CR8F612X Product overview 4 14 3 PC e PC master features Clock generation Start and stop generation e DC slave features Programmable I2C address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz ky Doc ID 1
75. output AFR2 Analog input 5 PD5 AIN5 UART1_TX UART1 data transmit 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Table 15 Current characteristics 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented 24 88 Doc ID 15590 Rev 1 D CR8F612X Pinout and pin description Figure 4 CR8F6125 28SOP DIP TIM5 CH1 BEEP HS PD4 J UART1_TX AIN5 HS PD5 EI UART1_RX AIN6 HS PD6 7 TLI HS PD7 E HS AIN4 TIM5 CH2 ADC ETR HS TIM1 BKIN PC7 HS SPI MISO OSCIN PA1 L PC6 HS SPI_MOSI OSCOUT PA2 1 2 3 4 5 6 7 8 k AG o TIM5 CH3 HS PA3 KA H Hp w N KA TIM1_ETR AIN3 HS PB3 p CR8F6125 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Figure
76. party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroele
77. r maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 41 Typical application with ADC Von CR8F V I ZN osv AIN AINx yn 10 bit A D VAIN NNN 1 onversian C gk Zoly ei IL p TI Capo Doc ID 15590 Rev 1 D CR8F612X Electrical characteristics 9 3 11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and opt
78. ressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Doc ID 15590 Rev 1 11 88 Product overview CR8F612X 4 2 4 3 12 88 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance
79. sus ERE kelen veku deno tus Lees 44 9 3 1 VCAP external capacitor snanu uaaa 45 9 3 2 Supply current characteristics s 46 9 3 3 External clock sources and timing characteristics 55 9 3 4 Internal clock sources and timing characteristics 57 9 3 5 Memory characteristics aasa auaa anaana 59 9 3 6 I O port pin characteristics unaua uaea 60 9 3 7 Reset pin characteristics 66 9 3 8 SPI serial peripheral interface 68 9 3 9 DC interface characteristics sss ss 71 9 3 10 10 bit ADC characteristics 00 000 ccc eee 72 9 3 11 EMCcharacteristios else tees 75 10 Package characteristics s ss 78 10 4 Package mechanical data ea 79 10 1 1 LQFP package mechanical data 79 10 1 2 VFQFPN package mechanicaldata 80 10 2 Thermal characteristics ssa RR xr RE 82 10 2 1 Reference document ss ee x e anaana nnana 82 10 2 2 Selecting the producttemperaturerange 83 11 Ordering information leeren 84 12 CR8F development tools lesen 85 12 1 Emulation and in circuit debugging tools 85 ky Doc ID 15590 Rev 1 3 88 Contents CR8F612X 122 Software tools 0 cee hs 86 1224 GR8F toolset sss simia sis Rad eti
80. ta based on characterization results not tested in production Table 38 Output driving current true open drain ports Symbol Parameter Conditions Min Max Unit lio 10 MA Vpp 3 3 V 150 Vo Output low level with 2 pins sunk lo 10 MA Vpp 5 V 1 V lio 20 mA Vpp 5 V 2 1 Data based on characterization results not tested in production Table 39 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lo 10 mA Vpp 3 3 V 10 VoL Output low level with 8 pins sunk lio 10 mA Vpp DM 0 8 Output low level with 4 pins sunk lo 20 mA Vpp 5 V 1 5 y Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 2 40 Vou Output high level with 8 pins sourced lio 10 mA Vpp 5 V 4 0 Output high level with 4 pins sourced lo 20 mA Vpp 5V 3 30 1 Data based on characterization results not tested in production Figure 23 Typ Vo E Vpp 3 3 V standard ports 15 40 C 25 C 125 85 C 125 C 62 88 Doc ID 15590 Rev 1 ky CR8F612X Electrical characteristics Figure 24 Typ Vo Vpp 5 V standard ports 40 C 25 C 1 25 85 C 125 C Vol V lo mA Figure 25 Typ Vo E Vpp 3 3 V true open drain ports Va V lo mA Figure 26 Typ Vo 8 Vpp 5 V true open drain ports 40 C a 25 C 1 75 85
81. tatus register 1 0x00 0x00 5305 TIM5 SR2 TIMS status register 2 0x00 0x00 5306 TIM5 EGR TIM5 event generation register 0x00 0x00 5307 TIM5 TIM5 CCMR1 TIM5 iaa mode register 0x00 0x00 5308 TIM5 CCMR2 TIM5 pL d mode register 0x00 0x00 5309 TIM5 CCMR3 TIM5 ee mode register 0x00 0x00 530A TIM5 CCER1 TIM5 PU enable register 0x00 0x00 530B TIM5 CCER2 TIM5 SE enable register 0x00 36 88 Doc ID 15590 Rev 1 D CR8F612X Memory and register map d Table 12 General hardware register map continued Address Block Register label Register name Reset status 00 530COx TIM5 CNTRH TIM5 counter high 0x00 0x00 530D TIM5 CNTRL TIM5 counter low 0x00 0x00 530E TIM5_PSCR TIM5 prescaler register 0x00 0x00 530F TIM5 ARRH TIM5 auto reload register high OxFF 0x00 5310 TIM5 ARRL TIM5 auto reload register low OxFF 0x00 5311 M TIM5 CCR1H TIM5 capture compare register 1 high 0x00 0x00 5312 TIM5 CCR1L TIM5 capture compare register 1 low 0x00 0x00 5313 TIM5 CCR2H TIM5 capture compare register 2 high 0x00 0x00 5314 TIM5 CCR2L TIM5 capture compare register 2 low 0x00 0x00 5315 TIM5 CCR3H TIM5 capture compare register 3 high 0x00 0x00 5316 TIM5 CCR3L TIM5 capture compare register 3 low 0x00 0x00 5317 to Reserved area 43 bytes 0x00 533F 0x00 5340 TIM6 CR1 TIM6 control register 1 0x00
82. te function CLK CCO AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC ETR port P5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive Default alternate functions 1 Port C4 alternate function AIN2 port D2 alternate function AINS port D4 alternate function UART1 CK 1 Do not use more than one remapping option in the same port 2 Refer to pinout description D Doc ID 15590 Rev 1 CR8F612X Option bytes Table 10 CR8F612X alternate function remapping bits 1 0 AFR1 option bit value AFRO option bit value HO port AFR1 and AFRO remapping options inactive Alternate function mapping o D Default alternate functions PC5 TIM5 CH1 0 1 PC6 TIM1 CH1 PC7 TIM1_CH2 PA3 SPI NSS i g PD2 TIM5_CH3 PD2 TIM5 CH3 PC5 TIM5 CH1 PC6 TIM1 CH1 PC7 TIM1_CH2 1 1 PC2 TIM1_CH3N PC1 TIM1_CH2N PE5 TIM1_CH1N PA3 UART1_TX PF4 UART1_RX 1 Refer to pinout description Doc ID 15590 Rev 1 29 88 Memory and register map CR8F612X 8 8 1 30 88 Memory and register map Memory map Figure 4 Memory map 0x00 0000 0x00 O3FF 0x00 4000 0x00
83. tion remap o 3 5 O ak option 9 Z bit Li 11 PB7 JO X X X O1 X X Port B7 12 PB6 VO X X X O1 X X Port B6 Timer 1 PB5 I2C SDA 3 2 break 13 TIM1 BKIN VO X X X O1 T X Port B5 I C data input AFR4 ADC PB4 12C SCL 3 2 external 14 ADC ETA VO X X X O1 T X Port B4 I C clock trigger AFR4 Analog input 3 15 PB3 AIN3 TIM1_ETR VO X XX HS O3 X X Port B3 Timer 1 external trigger Analog input 2 16 PB2 AIN2 TIM1_CH3N VO X X X HS O3 X X Port B2 Timer 1 inverted channel 3 Analog input 1 17 PB1 AIN1 TIM1 CH2N VO X XX HS O3 X X Port Bi Timer 1 inverted channel 2 Analog input 0 18 PBO AINO TIM1 CHIN VO X X X HS O3 X X Port BO Timer 1 inverted channel 1 Timer 1 PE5 SPI NSS SPI master slave inverted 19 TIMI CH1N ARE o AS LES E LS kaka channel 1 AFR1 0 PG TATIMI CHA Timer 1 channel 1 eed 20 UART1 CK UO X X X HS O3 X X Port C1 TIM1 CH2N UART 1 clock channel 2 _ AFR1 0 22 88 Doc ID 15590 Rev 1 ky CR8F612X Pinout and pin description Table 5 VFQFPN32 LQFP32 pin description continued Input Output ES Alternate FF Ss function o o O Pin a 9o 91 x c9 Default alternate after Pin name le sl e uo SE no FIlzs 2 S a3 2 nO a z5 function remap o SI EI c O9 ak option e o bit I Timer 1 PC2 TIM1 CH2 inverted 21 TIM1 CH3N
84. uo VHSEL L LL External clock source fuse OSCIN CR8F HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Doc ID 15590 Rev 1 55 88 Electrical characteristics CR8F612X Table 31 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse A speed oscillator 4 16 MHz Rr Feedback resistor 220 kQ Cc Recommended load capacitance 2 20 pF C 20 pF 6 fosc 16 MHz stabilized 9 Ipp Hsg HSE oscillator power consumption ebu mA C 10pF 12 fosc 16 MHz stabilized 9 Om Oscillator transconductance 5 mA V tsU HSBO Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer for more details Data based on characterizatio
85. vs Vpp 4 temperahures sis 61 Typical pull up current vs Vpp 4 temperatures 61 Typ Vol Vpp 3 3 V standard ports eese 62 Typ VoL 9 Vpp 5 V standard ports 0 eee 63 Typ Vol Vpp 3 3 V true open drain porte 63 Typ VoL 9 Vpp 5 V true open drain porte 63 Typ VoL 9 Vpp 3 3 V high sink porte 64 Typ VoL 9 Vpp 5 V high sink portal a a BRI 64 Typ Vpop Vou Vpp 3 3 V standard porte 64 Typ Vpp Vou 9 Vpop 5 V standard porte 65 Typ Vpp Vou 9 Vpop 3 3 V high sink porte 65 Typ Vpp Vou 9 Vpop 5 V high sink ports eee 65 Typical NRST Vj and Vj vs Vpp E 4 temperatures nana aa aaaea 66 Typical NRST pull up resistance vs Vpp 4 temperatures 66 Typical NRST pull up current vs Vpp E 4 temperatures s 67 Recommended reset pin protection auaa aaaea 67 SPI timing diagram slave mode and CPHA 0 2 222 69 SPI timing diagram slave mode and CPHA lt T 000 cece eee 69 SPI timing diagram master mode MC 70 ADC accuracy characteristics 2 74 Typical application with ADC s s RI RII ne 74 32 pin low profile quad flat package 7X7 4 4 79 32 lead very thin fine pitch quad flat no lead package 5x5 80 Recommended footprint for on board emulation 81 Recommended footprintwithouton boardemulatio
86. w threshold register low 0x00 0x00 540C ADC AWSRH ADC analog e status register 0x00 0x00 540D ABE ANSAL ADC analog p status register 0x00 0x00 540E ABO ANCHE ADC analog uon control register 0x00 0x00 540F ADC ame ankad ADC analog watchdog control register 0x00 cont d low 0x99 ee om Reserved area 1008 bytes 38 88 Doc ID 15590 Rev 1 D CR8F612X Memory and register map d Table 13 CPU SWIM debug module interrupt controller registers Address Block Register label Register name 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7FOB to 0x00 Reserved area 85 bytes 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ue ITC_
87. y Viy Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected D 42 88 Doc ID 15590 Rev 1 CR8F612X Electrical characteristics Table 15 Current characteristics Symbol Ratings Max Unit Jupp Total current into Vpp power lines source 100 lyss Total current out of Vss ground lines sink 80 Output current sunk by any I O and control pin 20 lo Output current source by any I Os and control pin 20 Injected current on NRST pin 4 Ge lue 24 Injected current on OSCIN pin 4 Injected current on any other pin 4 Zluup E Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production All power Vpp and ground Vss pins must always be connected to the external supply liNu PIN must never be exceeded This is implicitly insured if Vu maximum is respected If Vim maximum cannot be respected the injection current must be limited externally to the lj j piyy value A positive injection is induced by Viz Vpp while a negative injection is induced by Viy Vss For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 4 Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics o

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