GFEC MAX V Starter Kit User`s Manual
Contents
1. aw i Device Checksum Usercode Program verify bh stat SE k s SM1270ZT144 DD627AEC FFFFFFFF alb Stop amp Hierarchy B Files ai Dds M Auto Detect Flow Compilation ze X Delete Task i Add File wv m Compile Design Y HB b Analysis amp Synthesis v BB Fitter Place 8 Route Y Y us Change File Bb Assembler Generate proi le Save File B M TimeQuest Timing Analys e M EDA Netlist Writer Add Device Vi Program Device Open Progr Fup 5M12702T 144 Down gt Type Message Y Info Quartus II Info Quartus II Full Compilation was successful 0 errors 6 warnings Lit B System 16 i Extra Info Info 72 X Warning 3 A Critical Warning 3 A Error A Suppressed 4 A Flag Message O of 136 Ek PF location Locate 100 00 00 06 Messages OC ESBOSIRA GALAXY FAR EAST CORP Part 6 Hardware settings and operation descriptions While DIP SWI is ON DO D4 LED lights up While DIP SW2 is ON D1 D5 LED lights up While DIP SW3 is ON D2 D6 LED lights up While DIP SW4 is ON D3 D7 LED lights up Only one DIP SW will be ON at the same time 1 e if DIP SWI is ON all other DIP SWs shall be OFF or all LED will not be lit When all DIP SWs are OFF LED shall be in Marquee mode press SWO with one LED lit up press SW1 to light up two LED CFCC IMID APR2. File Device Checksum Usercode Program Verify Blank Examine Security Erase ISP pli Start giie Check Bit CLAMP E MAXV pojA SM12 5M1270ZT144 00628298 FFFFFFFF Wb Stop CFM X Delete PO add File b Change File UFM E Save File S Add Device Fup Down SM12702T144 OC EISBOSIRAU GALAXY FAR EAST CORP Chapter 2 Quartus II Starter In this chapter an example of Marquee in VHDL design shall be revealed and how to create new projects program edit and download etc via Quartus II It is necessary to copy the data in the ledtest directory into the hard drive before starting the following procedure the example shows how to transfer data from the ledtest to D ledtest Part 1 Create new project Step 1 Open Project Wizard File New Project Wizard Quartas I File E dit view Project Assignments Processing Tools Window Help oa k RS 9o o y gt O AA Ctro x Ctrl F4 qu meme ere as R AN aD QUARTUS II QU Q AV DIM File Properties JA A r GA Create Update Export Convert Programming Files j e A R I U S U MO Page Setup bh a 4 Print Preview amp Print Recent Files Recent Projects Exit Alt F4 TimeQuest Timing Analysis E EDA Netlist Writer E Program Device Open Programmer zs a Fem gt SE dm trogqrar n MD Documentation
3. Step 5 Click Next uw Altera Software Installer 10 1 Build 153 Installation Summary Review the installation summary to verity your software installation options and then click Mextto begin the installation Destination Directory c altera 10 1 Program Folder Altera selected Components Quartus Subscription Edition Paid e Quartus Subscription Edition Paid e Ara Gx Family e Arria Il Gs Family Cyclone Family Cyclone Il Family Cyclone Illi LS Families Cyclone h E Family e Cyclone hx Family Legacy Families e hix I Family e hix Family e Stratix Family e Stratis G Family e Stratix Gx Family gt Summary e Stratix ll and HardCopy Il Families e Stratix fl HardCopsy lly and Arria ll G2 Families e Stratix W Family Modelsim Altera Starter Edition Free Step 6 Start installation cinta Bs APRO e GALAXY FAR EAST CORP Si Altera Software Installer 10 1 Build 153 Installation Please wat while the Altera software is installed Extracting Quartus Subscription Edition Paid archives Components Quartus Subscription Edition Paid c Quartus Il Subscription Edition Paid Arria GX Family Arria Il GX Family Cyclone Family Cyclone Family Cyclone NM LS Families Cyclone W E Family Cyclone M GS Family Legacy Families MAX II Family MA S Famil etratix Family start Quartus 10 1 Create Desktop Shortcut Quartus Subscription Ed
4. OOC BER DE Step 2 Select a directory From List or a specific directory for installation gt click Next q uq e e DVDICD ROM JERR 38 IDE ATA ATAPI tlas Gay IEEE 1394 ENTHE tell ae RU E EELER Altera USB Blaster nhanced Host Controller 3B34 nhanced Host Controller 3B3C O RARE CD RAH REBECH VP Ao PEA HELA Ke Step3 Select path C altera quartus drivers usb blaster Dini 43 ETE ez CAM em SECA ema E OM LEE ERO ATA RRA SEUS JEK w e w Ed pn ZER ie MRE HE CH common CH cusp E IDE ATA ATAPI 4 Sech EH eg EIE ide d eJ 1386 A 2 sentinel A CH usb blaster ape SYS re a dsp_builder amp E eda libraries O ENE ries TS RE E EFA PRA EA EU EMA E EEdE Litt B TE EE SEE EI TER TA di pis GRE CD ROM dub SS IJ ms SP elias ative O e s altera 10 l quartus drivers usb blaster lt OF SEES gt Rise ie iets Bose TB Ria RE Windows 7 Raw OAT sae Smeets T EET GD ss 0 30 me Dima Sa BRR ZS e GALAXY FAR EAST CORP Step4 Select Continue to install gt Finish gt Next 48 3 8 62 e Sy en amesra emp Cm EQ BTA BED RHD E EE J m GFEC 57E7DCC3FF AER See MM SEI SES 2 DVDICD ROM 368848 E IDE ATA ATAPI 22255185 uy IEEE 1394 DECHE PAE RISE Ur I
5. System 16 Processing 78 Extra Info A Info 72 AN Warning 3 Critical Warning 3 A Error A Suppressed 4 AN Flag Message 0 of 136 Ek 9 Location Locate Opens a Programmer window 10096 00 00 06 Messages CFEC Doref el GALAXY FAR EAST CORP Step 2 Make sure the Download Cable is set 1f not please refer to Download Cable under Windows XP Win7 If in Hardware Setup select USB Blaster USB 0 if not please refer to Hardware Setup Download the file by selecting ledtest pof check all boxes in Program Configure at this moment the MAX V Kit must be connected to the Download Cable and power cord finally click Start to complete downloading Quartus II EZMAXV poj MAX V MENU Iledtest ledtest ledtest File Edit View Project Assignments Processing Tools Window Help ED Og amp X BB o c edes xl uuo o 2 10 tX e e Project Navigator m x CH ledtest vhd m amp Compilation Report EJ Assignment Editor E Fl Ma ue EE KS gt Programmer EZMAXV poj MAX V MENU ledtest ledtest ledtest ledtest lx e Jul 19 18 28 55 2011 d MAX V 5M1270ZT144C5 AJ L P z 7 01 19 2011 SP 1 SJ Full abo ledtest File Edit View Processing Tools Window amp s Hardware Setup USB Blaster USB 0 Mode JTAG lt Progress Enable real time ISP to allow background programming for MAX II and MAX V devices
6. S OC RISIBIOSIRA GALAXY FAR EAST CORP EEE C O Ce e9 m E H s 8 PRE w ARE 4 3 Erich PC gt cg IDE ATA ATAPI 5588 od ALN EEE gt a Sees pM AER a j Shee fex S m fo 1 5 a Bh AZ x GS gt DIS er Sp BE Sen A er EST BAGE d e PRAIA SF Windows SEGAH SSRN RT IE AER gt O EM RURSUS b Dess D BRENES E PBEREMIBESE ox EX p Me SS gt mE Pc ME gt ENE gt RE gt zm EE gt E BET gt IES C BESTES d Sr BS R SENEN AE AN Step 3 Browse and select the driver from the list gt browse gt select C altera 10 1 quartus drivers USB blaster gt click Next TET B SSH LAN SEREN Sr SS tr Sah ILES SSES gt ERCE CNR BS ers ES PEL HEESETOESVARSSEONHHEANE LRRIEEEEXERSESSEE Ee Step4 Select Continue to install this driver 50 CFEC Doref el GALAXY FAR EAST CORP gt ak IER ENE eN CERRAR CCS EA E SHEARS gt Une It BR ILES GH E EECHER v a e ME BD Step 5 Installation complete gt Exit Windows BIER E Sm f Bg SEE TA ES Windows PhS HS Es MET ER FS Altera USB Blaster Step 6 Installation complete POC RISIBIOSIRA GALAXY FAR EAST CORP H F MIA KE ERBB H sz EJ B cs S Ot 8 G6 A Erich PC gt cg IDE ATA ATAPI 2588 gt Da Ais gt B ales pe E LED b S SB ANBAR D ema 4 g ESPERES x x i Altera USB Blaster Generic USB Hub x Generic USB Hub Intel R 5 Series 3400 Series
7. Auto device selected by the Fitter Show advanced devices 8 Specific device selected in Available devices list Other n a HardCopy compatible only Available devices UFM blocks Companion device jocumentation E Limit DSP amp RAM to HardCopy device resources Processing A Extra Info Info A Warning Jl Critical Warning Error A Suppressed A Flag gC cat 0 00 00 00 POC EiSBOSIRA GALAXY FAR EAST CORP Step 6 Click Next d Quartus II Project Assignments Processing Tools Window Help DS ug Project Navigator EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your project EDA tools Tool Name Format s Run Tool Automatically Run this tool automatically to synthesize the current desi Simulation lt None gt Slshioe v Run gate level simulation automatically after compilatio Timing Analysis Run this tool automatically after compilation Formal verification K E Board Level Timing ee ei Signal Integrity None ei Boundary Scan lt none gt el E i PZ Locate 0 00 00 00 CFEC Eege IR GALAXY FAR EAST CORP Step 7 Click Finish to complete creating the new project 8 Quartus II File Edit View Project Assignments Processing Tools Window Help T D oc EO e Tee z New Project Wizard Project Mavigator Summary page 5 of 5 When you click Fi
8. JP6 IO 1 andJP7 IO 4 with their output voltage ranges at 1 2V 1 5V 1 8V 2 5V and 3 3V JP4 IO 3 Is a fixed VCC I O at 3 3V the user can link to this connector and input a working voltage of 5V for the experiment board VIOI JP6 1 3 3V 2 2 9 3 1 8V 4 1 5V ALL OFF 1 2V VIO2 JP5 1 3 3V 2 2 5V 3 1 8V 4 1 5V ALL OFF 1 2V CFEC Eege IR sl GALAXY FAR EAST CORP VIOA JP7 1 3 3V DE DV 3 1 8V 4 1 5V ALL OFF 1 2V 6 Power Selection 2 experiment board working voltages are available for selection which come from the USB socket or VCC I O 3 JP4 and which can light up the PWR D 11 LED DC USB cord EXT JP4 CFEC ESSA GALAXY FAR EAST CORP 7 4 Extension I O Connectors JP4 JP5 JP6 JP7 Tg E M M ME B EHH ob 8 Gi Wen b p KS K g 5M1270ZT144C5N provides 114 common I O pins The expansion I O ports of this experimental board connect to JP6 IO 1 JP5 IO 2 JP4 IO 3 and JP7 IO 4 respectively so that the user can easily link this connector to other PC boards Furthermore JP6 JP5 and JP7 also provide the Power Pin and GND pin Power Pins offer 1 2V 1 5V 2 5V and 3 3V voltages but without current protection We suggest that you set up a power circuit in your own expansion circuit before connecting the two if a large current would be obtained from this experimental board Except for the Power Pin and GND Pin othe
9. voltage of expansion I O is limited to 3 3V so that if an IC 5M1270ZT144C5N has been burnt out due to carelessness you will need to purchase it from our service department and solder it by yourself 3 month warranty is provided for normal use Feature This experimental board is a simulation board specially made for the Altera MAX V Family of Devices Those interested in digitizing design could realize their ideas through this experimental board The built in CPLD 5M1270ZT144C5N provides 1270 LEs with 114 common I O 8K bits User Flash Memory Detailed information and specs are available on the DVD enclosed or on the Altera Web Site http www altera com Except IC 5M1270ZT144C5N some peripheral parts connected to it are available for users upon completion of a digital logic design GfOC BER eran gt Peripheral parts 4 Bits DIP Switch 2 Push Buttons 8 LEDs 1 Oscillator Socket 4 Extension I O Connectors Appearance of MAX V Experimental Board FELT CT sh 871 38 WL 2222222222223 3 55 bh A 3885 Le Sp 101 35 CFEC Eege IR sl GALAXY FAR EAST CORP gt Detailed specs are listed below 1 4 Bits DIP Switch DIP_SW The MAX V Experimental Board comes equipped with a 4 bit DIP Switch when it is switched to ON it will turn MAX V Device I O on in Low the signal pin position of the 4 Bits DIP Switch and the connection to the MAX V Device I O can be found
10. END IF END PROCESS CLK CNT LED REG CON PROCESS RESET CNT CLK LED SEL BEGIN IF RESET 0 THEN LED REG lt 00000001 ELSIF LED SEL 0 THEN LED REG lt 00000011 ELSIF CNT CLK EVENT AND CNT_CLK 1 THEN LED REG 0 lt LED REG 7 LED REG 7 DOWNTO 1 lt LED REG 6 DOWNTO 0 END IF END PROCESS LED REG CON LED OUT WITH DIP SW SELECT LED lt lt LED REG WHEN 1111 00010001 WHEN 1110 00100010 WHEN 1101 01000100 WHEN 1011 10001000 WHEN 0111 00000000 WHEN others END a Step 2 Thi VHDL file can be constructed as a symbol of an electric circuit for a circuit diagram Design with the following process Step2 1 Open VHDL file to create the symbol click File Create Update Create SymbolFiles for Current File GALAXY FAR EAST CORP OC RRRGARAA Quartes 11 EZMAXV poy MAX V MENU ediest ledtest ledtest d Gdit View Project Assignments Processing Tools Window Help crt ledtest niv LLO DD gt m amp 2 us sea x ledtest vhd o Crha M TANG CX AAAKRH ES Die LIBRARY ieee USE ieee std logic 1164 ALL USE ieee std logic unsigned all USE WORK my package ALL LIBRARY ALTERA USE ALTERA MAXPLUS2 ALL D I New Project Wizard QE Open Project Save Project Closg Project al Save As a Save All Elle Properties STD LOGIC STD LOGIC Convert Programming Files Create AHOL Include Files for Current File STD LOGIC RI Page S
11. Help Processing led test he name of the top level design entity for this project This name is case sensitive and must exactly match the entity ithe design file Messages lt gC Extra Info A Info A Warning N Critical Warning A Error X Suppressed A Flag Processing Locate 0 00 00 00 GALAXY FAR EAST CORP POC RARAS Step 4 Select ledtest VHD click ADD and add it into this project click Next A Quartus II Assignments Processing Tools Window Add Files page 2 of 5 Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Note you can always add design files to the project later File Name Type Library Design Entry Synthesis Tool HDL Version Add All ledte WH Remove Up lt iray E Flow Compilation lt IN ocumentation Specify the path names of any non default libraries 2 9 ES 0 00 00 00 CFEC RARAS GALAXY FAR EAST CORP Step 5 Select Chip model 5M1270ZT144C5N of MAX V series I A Quartus II File Edit View Project Assignments Processing Tools nua Window Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Show in Available devices list Package Any v Pin coumt Any v Target device Speed grade
12. Synthesis CH A Fitter Place 8 Route v Category All lt lt new gt gt new zk TimeQu jest Timing em This cell specifies the value of the assignment EDA Netlist Writer W Program Device Open Progr gt Type Message 4p Info Command quartus map read settings files on write settings files off ledtest c ledtest mu Info Quartus II Create Symbol File was successful 0 errors warnings lt System 16 Processing Info AQ dE Critical Warning ee Starts a new compilation 100 00 00 02 GALAXY FAR EAST CORP CFEC Doref el Step 2 Compilation complete F Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest File Edit View Project Assignments Processing Tools Window Help Oe B GS X mm c ene x ebe ore eh 69 Bs Project Navigator m x Lo ledtest vhd amp Compilation Report EJ Assignment Editor Table of Contents m Flow Summary zin Bro Summary Flow Status Successful Tue Jul 19 18 28 55 2011 MAX V 5M12702T144C5 ES Flow Settings Quartus II Version 10 1 Build 197 01 19 2011 SP 1 SJ Full inn ledtest ES Flow Non Default Global Settings Revision Name ledtest BB Flow Elapsed Time Top level Entity Name ledtest BB Flow OS Summary Family MAX V B Flow Log Device 5M1270ZT144C5 Analysis amp Synthesis Timing Models Preliminary amp C Fitter Tota
13. Timing Analyzer Quartus II version 10 1 Build 197 01 19 2011 SP 1 SJ Full sin ledtest EB Flov Revision Name ledtest ES Flov Advisors Top level Entity Name dreet ES Flov Family MAX V E Flov Chip Planner Floorplan and Chip Editor Device 5M12702T144C5 e C Ana d i Design Partition Planner Timing Models Preliminary E C Fitte Netlist Vi Total logic elements 43 1 270 3 d Ca Asse oe rs Total pins 15 114 13 96 amp C3 Tim ia SignalTap II Logic Analyzer Total virtual pins 0 a UFM blocks 0 1 0 m In System Memory Content Editor amp Hierarchy B Files P Dds gt ma Logic Analyzer Interface Editor ai In System Sources and Probes Editor SignalProbe Pins Flow complaton N O Programmer Bh ITAG Chain Debugger Task pol Transceiver Toolkit G b Compile Design Y External Memory Interface Toolkit amp M Analysis amp Synthesis T amp M Fitter Place amp Route a Megawizard Plug In Manager zk Assembler Generate pro DN SOPC Builder amp M TimeQuest Timing Analys S Dr EDA Netlist Writer om Osys Beta ZE Program Device Open Progra Tel Scripts i B Entity KB Launch Design Space Explorer Tasks Bx gt Custornize Options Type Message License Setup g d Info Quartus II TimeQuest Timing Analyzer was successful errors 3 warnings Info Quartus II Full Compilation was successful errors 6 warnings
14. 5 amp No matches gt est Yo Le ATA Tm All the pin name of the ledtest will be generated in the Node Finder window select all of the pins and click OK 32 Dima A BRR ZS e GALAXY FAR EAST CORP Node Finder Named 2 Fiter Par RECO Look in lectest v m Include subentities Nodes Found Selected Nodes Mare Assignments Type Mare Assignments Type fi EN CLE Unassigned Input i CLE Unassigned Input Eme DIP Gw Unassigned Input Group im DIP Gw Unassigned Input Group E DIP_SW 0 Unassigned Input ES DIP Sw D Unassigned Input gt DIF_SW 1 Unassigned Input gm DIP Sw 1 Unassigned Input EB DIP_SW 2 Unassigned Input F DIP Sw 2 Unassigned Input DIP SwV 3 Unassigned Input is DIP Sw 3 Unassigned Input LED Unassigned Output Group P LED Unassigned Output Group E LED O Unassigned Output E LED O Unassigned Output 2 LED 1 Unassigned Output a LED 1 Unassigned Output LED 2 Unassigned Output E LED 2 Unassigned Output P LED 3 Unassigned Output i LED 3 Unassigned Output i LED 4 Unassigned Output LED 4 Unassigned Output P LED 5 Unassigned Output E LED S Unassigned Output E LED 6 Unassigned Output es LED 6 Unassigned Output LED 7 Unassigned Output a LED 7 Unassigned Cutout iil ai amp il Step 4 Left click Assignment Name column and type in Location repeat until all Assignment name spaces are filled with Location E Qu
15. A a GALAXY FAR EAST CORP Part 7 Hardware Setup Step 1 Tools Programmer Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest File Edit View Project Assignments Processing De Eg amp A BI o c Fed ax HOA Project Navigator Entity dy MAX V 5M1270ZT144C5 ww ledtest Brus fos Tasks m x Flow Compilation v Task SG Kk Compile Design E be Analysis 8 Synthesis zk Fitter Place amp Route zk Assembler Generate proc zk TimeQuest Timing Analys amp EDA Netlist Writer a Program Device Open Progra lii gt ieee Window Help Run EDA Simulation Tool 4 Run EDA Timing Analysis Tool Z Launch EDA Simulation Library Compiler KE Launch Design Space Explorer 5 TimeQuest Timing Analyzer Advisors Chip Planner Floorplan and Chip Editor da Design Partition Planner Netlist viewers tm SignalTap II Logic amp nalyzer m In System Memory Content Editor m Logic Analyzer Interface Editor ai In System Sources and Probes Editor SignalProbe Pins W Pr ogrammer Bh ITAG Chain Debugger i Transceiver Toolkit Y External Memory Interface Toolkit lt MegaWizard Plug In Manager EN SOPC Builder A Osys Beta Tel Scripts Type Message lt ill System 16 Processing 78 Opens a Programmer window step 2 Customize Options License Setup Click Hardware Setup M
16. B Ho ta Sg SCH ECT EENE ELIT TOA Altera USB Blaster nhanced Host Controller 3B34 nhanced Host Controller 3B3C 2 TR RTA Step5 Installation complete BT HH RED HTA SOU BA b E GFEC 57E7DCC3FF 3 DVD CD ROM 3660648 Sy IDE ATA ATAPI PERA Gg IEEE 1394 Enh E MEME ae SCSI E RAID PERE a VET Sse a d FIRE O EM MAM rl ae i Altera USE Blaster eue E ub e Generic USB Hub Ge Intel R 5 Series 2400 Series Chipset Family USB Enhanced Host Controller 3B34 Eh Intel R 5 Series 2400 Series Chipset Family USE Enhanced Host Controller 3B3C G NEC Electronics USB 3 0 Host Controller K POC EiSBOSRA GALAXY FAR EAST CORP Create new hardware on Windows 7 Step 1 Start gt Setup gt Control panel gt System gt Hardware Hardware administrator gt New delete hardware wizard pops up gt click Next m SEG gt BRAS E d 3R V IAM RH E 7 SEMENG o FESE sees EE G EFES Stet 3H Evi PARES 4 3 Erich PC AME gt cdi IDE ATA ATAPI 25122 AES b ta ATEET BEBE E gt AE a us AMES ff USB Blaster o O EM ARABES b D D ERE ARRE b BEREMESSES b P Bx b Aa Bia gt ERS gt vs ERR b JAH Sieg gt a 2 a TERA Step 2 Insert Download Cable into USB PC select USB Blaster right click on it and select update new driver or software
17. Chipset Family USB Enhanced Host Controller 3B34 x Intel R 5 Series 3400 Series Chipset Family USB Enhanced Host Controller 3B3C M USB Composite Device i USB Root Hub p Y BERAHHESE gt ap EX p Me SS A ERs TL TH Lali z j
18. ERA CORPORATION SUBSIDIARY FROM WHICH YOU HAVE ACQUIRED THIS LICENSE COLLECTIVELY ALTERA HOWEVER THIS SOFTWARE MAY CONTAIN PARTICULAR COMPONENTS FILES OR PORTIONS WHICH ARE SUBJECT TO SEPARATE LICENSE AGREEMENTS WITH DIFFERENT TERMS AND CONDITIONS IN EACH SUCH CASE Step 3 Designate Quartus 10 1 installation path click Next SE Altera Software Installer 10 1 Build 153 Select Destination Specify the software destination directory Destination Directory Available Space 29 G Program Folder Specity the Program Folder Existing Folders ALL 100 Allegro SPB 15 5 1 Altera ASUS Autodesk Ara gt Destination Select Sapa Ma D HTC HTC Syne WT BlueSoleil Mentor Graphics SDD Microsoft Office MEC Electronics Mera Orcad Family Release 4 2 CFEC iem SA GALAXY FAR EAST CORP afec com tw Step 4 Check Quartus gt NIOS and Modelsim boxes then click Yes r2 Altera Software Installer 10 1 Build 153 select components Selectthe software components you want to install Components Install Size e kl MadalSim Altera Edition Faid ModelSim Altera Starter Edition Free AHERN x Nios Il Embedded Design Suite L OSP Builder Stand Alone Quartus Programmer Free l Description gt Components Select Altera Software Installer 10 1 space Required 136 Select Deselect All space Available 41 G Cancel cinta Bs APRO e GALAXY FAR EAST CORP
19. GFEC MAX V Starter Kit User s Manual LX m BS 123 B BR ZS 5 GALAXY FAR EAST CORP Address 14F 207 5 Sec 3 Peihsin Rd Hsintien Taiwan R O C TEL 886 2 8913 2200 FAX 886 2 8913 2277 CFEC Eege IR sl GALAXY FAR EAST CORP GALAXY FAR EAST CORP Taipei Head Office 14F No 207 5 Sec 2 Bei Hsin Rc Hsin Dien New Taipei TEL 886 2 8913 2200 FAX 886 2 8913 2277 Hsinchu Branch 3F No 526 Sec 1 Kuang Fu Rd Hsinchu City TEL 886 3 578 6766 FAX 886 3 577 4795 Kaohsiung Branch 10F 8 No 56 Sec 1 Min Sen 1 Rd Hsin Hsin District Kaouhsiung City TEL 886 7 223 1338 FAX 886 7 222 4051 For technical support please call TEL 0800819595 GALAXY website HTTP WWW GFEC COM TW IX Wa ES 17 A B lt AND GALAXY FAR EAST CORP fs www gfec com tw _ 7 GALAXY FAR EAST CORP OC ESBOSIRA Table of Contents Table of Content ESR fl Kk IE Xe E Chapter 1 Ji EGIL ette 4 Chapter 2 Quartus II Starter 200 Appendix A Quartus II 10 1 Installation 41 Appendix B Installing Download Cable on Windows XP Win7 46 cinta Bs APRO e GALAXY FAR EAST CORP Chapter 1 Instructions e Contents Altera MAX V Main Board USB Cable CD ROM Attention Please check the contents of the box are complete when you receive this Experimental Board The max
20. Step 1 Click Next i Altera Software Installer 10 1 Build 153 Introduction vvelcome to the Altera Sofware Installer The Altera Software Installer quides you through the process of installing Altera software To continue click Next For more information about Altera software go to the Design Software Support website gt Fartechnical support ga ta the www altera cam mwysupport website gt For online documentation an software installations click here gt For Altera Software Installer command line options click here Introduction Cue Comes Step 2 Click I agree to the terms of the license agreement then click Next Dima A BRR ZS O e GALAXY FAR EAST CORP S Altera Software Installer 10 1 Build 153 TORK End User License Agreement To continue installing the software you must agree to the terms of the software license agreement below QUARTUS IL VERSION 10 1 STANDARD LICENSE AGREEMENT ALTERA PROGRAM LICENSE SUBSCRIPTION AGREEMENT PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE INSTALLING OR USING THE SOFTWARE PROVIDED TO OU ON OWO YAA WEB SITE OR ON ANOTHER MEDIUM OR THROUGH ANOTHER DELMERY MECHANISM EY INSTALLING OR USING THIS SOFTWARE OR PAYING A SUBSCRIPTION FEE YOU INDICATE OUR ACCEPTANCE OF SUCH gt License TERMS AND CONDITIONS WHICH CONSTITUTE THE LICENSE AGREEMENT AGREEMENT BETWEEN OLI AND ALTERA CORPORATION OR THE ALT
21. Type Message Processing X Extra Info A Info A Warning Critical Warning Error X Suppressed Flag Message RA 9 Location Locate Starts the New Project Wizard 0 00 00 00 CFCC mA FS BRR ZS GALAXY FAR EAST CORP Step 2 td Quartus II File Edit View Click Next Project Assignments Processing Tools Window Help iD ug Project Navigator z New Project Wizard amp Hierarchy Introduction The New Project Wizard helps you create a new project and preliminary project settings including the following Project name and directory Name of the top level design entity Project files and libraries Target device family and device EDA tool settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use the various pages of the Settings dialog box to add functionality to the project Tasks Flow Compilation Compil P Ans P Fitt f Ass P Ti P EDA Progra ill Don t show me this introduction again Type Messe Finish Messages step 3 Quartus II Message t F Location Extra Info A Info A Warning N Critical Warning N Error N Suppressed A Flag Processing Locate 00 00 00 0 Type in project working directory and name then click Next Assignments Tools Window
22. U B2 P113 D D 1 B2 P109 itle Title Document Number Doc Date Monday July 18 2011 Sheet 2 of o HEADER 2002 M CFEC IMID FS BR ZS G GALAXY FAR EAST CORP Yi TYPEB 120ohm 3 0805 b FB4 DH p s C63 Ta 0603 y C25 Di u 0603 LED C24 100u 18 D R35 po Sch 2k 0603_L ALL OFF 1 2v nas putus itle Title E Document Number Doc Date Monday July 18 2011 Bheet RABAID A BIS ZS e GALAXY FAR EAST CORP gt Easy Download and Installation of Quartus II A Install Altera Quartus II 10 1 SP1 or later by opening the included CD and clicking Install Quartus II Web Edition rg Alteta Software Installer 10 1 Boild 153 Introduction Welcome to the Altera Software Installer The Altera Software Installer quides you through the process of installing Altera software To continue click Next gt For more information about Altera software go to the Design Software Support website gt Fortechnical support qo to the www altera com mysuppon website gt For online documentation on software installations click here Far Altera Software Installer command line options click here gt Introduction B Apply License 1 Open Quartus II 10 1 Start gt program files gt Altera gt Quartus II 10 1 2 From the main menu select Tools gt License Setup gt jot down the NIC ID 3 Then v
23. am Schematic File EDIF File Qsys System File State Machine File Systemer ilog HOL File Tel Sd File Verilog HDL File Memory Files c Hexadecimal dntel For mat File eis Edit View Project Assignments Processing CtrHF4 New Project Wizard 4 Memory Initialization File Open Project Chr verification Debugging Files be In System Sources and Probes File save Project Logic Analyzer Interface File 3 SignalTap II Logic Analyzer File Close Project Other Files AHDL Include File Block Symbol File E Save Cries Chain Description File TS ti E Step 1 Open ledtest vhd E Quartus II EMAXV poi MAX V MENU ledtest led test led test ale File Edit view Project Assignments Processing Tools Window Help POS ID EG ai DE Sa ed est Jy s GUe 2 eH e BA OD Project Navigator m x 9 bw D BMT EE 7 A IOS OE E LIBRARY ieee USE ieee std logic 1164 ALL USE ieee std logic unsigned all USE WORK my package ALL LIBRARY ALTERA USE ALTERA MAXPLUSZ2 ALL Entity MAX V 5M12702T144C5 gt led test EIENTITY MAX5 IS E PORT CLK STD LOGIC lt i gt RESET STD LOGIC LED SEL STD LOGIC VO 0 C Cn a GA DJ amp Hierarchy B Files d Design Units Tasks m x LED STD LOGIC VECTOR DOWNTO 0 DIP SW gt STD LOGIC VECTOR 3 DOWNTO 0 Flow Compilation v Task END MAX5 Compile Desi
24. ang Create Ver ilog Inetantistion Template Files for Current File Create WHO Component Declaration Files for Current File STD LOGIC VECTOR 7 DOWNTO 0 g STD LOGIC VECTOR 3 DOWNTO 0 BENTITY ledtest 15 E PORT o m QN n 2 Q Ne Alt F4 i Create Update PS File Y Program Device Open Programm Croate Board Level Boundary Scan File STD LOGIC VECTOR 7 DOWNTO 0 SER RANGE D TO 4704203 Type Message Y Info Command quartus map read settings files on write settings files off ledtest c ledtest amp p Info Quartus II Create Symbol File was successful O errors 0 warnings t Create symbol fies for current file Step 2 2 Complete the symbol to be built SS Quartus II i 1 Create Symbol File was successful Step 2 3 To create a new Block Diagram click File New to choose a new designing method click Block Diagram Schematic File under Design Files to open a new Electric circuit diagram designing file Dima A BIS ZS O e GALAXY FAR EAST CORP New Quartus II Project SOPC Builder System Design Files 0 AHOL File 3 Block Diagram Schematic File a Quartos II E M AXV poj M X V MENU ee i EDIF File dit View Project Assignments Processing Qsys System File Im a x State Machine File Ctr N Systemverilog HDL File is e Tel Script File Ga DO VHDL File ap Open Ge E Verilog HDL File Close Chr AE Memory Files He
25. artus II E MAXV poj MAX V MENU ledtest ledtest ledtest LOK File Edit view Project Assignments Processing Tools Window Help E D G e XH o amp etes x ebe G gt O dama e e Project Navigator mx LB o ledtestvhd E Compilation Report E Assignment Editor J lt lt new gt gt Filter on node names Category All Entity diy MAX V 5M1270ZT144C5 From To Assignment Name Value Enabled d ledtest MIA gt or sinto Location ES DIP Sw 1 Location E DIP Sw 2 Location EEUU i or suis Location x LED O Location X LED 1 Location SO x WW ct Location x LED 3 Location amp Hierarchy B Files d Dds p LED 4 Location 10 LED 5 Location ial 11 ee vn LED 6 Location oon ou WN HF 13 gt LED SEL Location Task 14 EN i RESET Location bk Compile Design 15 BEER gt CLK Location E e Analysis 8 Synthesis 16 d it AE Dk Fitter Place 8 Route lt bk Assembler Generate prod g gt TimeQuest Timing Analyst This cell specifies the value of the assignment H EDA Netlist Writer qi Program Device Open Progra Flow Compilation 12 DEM LED 7 Location 2 Type Message ip Info Command quartus map read settings files on write settings files off ledtest c ledtest e d Info Quartus II Create Symbol File was successful errors 0 war
26. e cr O E Ss Bis 2 pr D CNT CLK 1 THEN G T lt LED REG 6 DOWNTO T Ls gt 5 52 1210 HNT LUN PR E a 01711 others i Info Quartus II TimeQuest Timing Analyzer was successful errors 3 warnings Info Quartus II Full Compilation was successful 0 errors 6 warnings Extra Info A Info 72 A Warning 3 A Critical Warning 3 A Error A Suppressed 4 A Flag ess CS 10096 Locate 00 00 06 CFEC RRRGARAA GALAXY FAR EAST CORP Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest Eile Edit View Project Assignments Processing Tools Window Help Ose S kami a c it X YG G gt gt o E Project Navigator m x o E D Programmer EMAXV poj MAX V MENU ledtest ledtest ledtest ledtest EIN aea File Edit view Processing Tools Window MAX V 5M1270ZT144C5 T ww ledtest 2 ca Hardware Setup 3 USB Blaster USB 0 Mode DTAG v Progress J Enameres e ISP to allow background programming for MAX II and MAX Y devices Device Checksum Usercode Program Verify Ph Start Configure E 5M12702T144 00627470 FFFFFFFF Po Stop Hierarchy B Files d Dis M Auto Detect Tasks ax X Delete Flow Compiaton de db add Fie Task EP Copie Deem HB b Analysis 8 Synthesis Bib save File zk Fitter Place amp Route wb Assembler Generate pro amp b TimeQuest T
27. gn amp Analysis amp Synthesis zk Fitter Place amp Route zk Assembler Generate programmini H TimeQuest Timing Analysis P EDA Netlist Writer SIGNAL LED REG STD LOGIC VECTOR 7 DOWNTO 0 QD Program Device Open Programmer 24 SIGNAL CNT INTEGER RANGE 0 TO 4194303 oc lt HARCHITECTURE a OF MAX5 IS gt ECKE ARTI CST TR D mbang e EE d a TB cl a DI Type Message Processing X Extra Info Info A Warning A Critical Warning X Error X Suppressed A Flag Message t Location Locate 0 00 00 00 Dima A BIS ZS O e GALAXY FAR EAST CORP Marquee programming code and description Marquee programming code LIBRARY ieee USE iteee std logic 1164 ALL USE 1eee std logic unsigned all LIBRARY ALTERA USE ALTERA MAXPLUS2 ALL ENTITY ledtest IS PORT CLK IN STD LOGIC RESET IN STD LOGIC LED SEL IN STD LOGIC LED OUT STD LOGIC VECTOR 7 DOWNTO 0 DIP SW IN SID LOGIC VECTOR 3 DOWNTO 0 ENDledtest ARCHITECTURE a OF ledtest IS SIGNAL LED REG STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL CNT INTEGER RANGE 0 TO 4194303 SIGNAL CNT CLK STD LOGIC BEGIN CLK CNT PROCESS CLK RESET BEGIN IF RESET 0 THEN CNT CLK lt 0 CNT lt 0 ELSIF CLK EVENT AND CLK 1 THEN IF CNT 4194303 THEN CNT CLK lt NOT CNT CLK CNT lt 0 ELSE CNT lt CNT 1 27 cinta Bs APRO e GALAXY FAR EAST CORP END IF
28. iming Analys amp b EDA Netlist Writer Qi Program Device Open Progra 4 vp 5M1270ZT144 Down Z Add Device Type Message md Info Quartus II TimeQuest Timing Analyzer was successful 0 errors 3 warnings Info Quartus II Full Compilation was successful 0 errors 6 warnings lt gt Ju il System 16 Extra Info A Info 72 Jl Warning 3 Jl Critical Warning 3 A Error A Suppressed 4 N Flag mesmos P Locate 100 00 00 06 Step3 Select USB Blaster F Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest File Edit Vi DSE Project Navigator ew Project Assignments Processing Tools Window Help R AT GR GE 7 X DS pe dy MAX V 5M1270ZT144C5 wm ledtest H gt Hardware Setup Hardware Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware USB Blaster USB 0 Ki E Available hardware items Usp Blaster USB 0 Flow Hardware Usercode Program Verify USB Blaster Configure FFFFFFF is Change File Type Message let Save File m W Info Quartus I Y Info Quartus I T up i System 16 rm NEL d Message D of 136 00 00 06 CFEC BRA ARAS GALAXY FAR EAST CORP afec com tw Appendix A Quartus II 10 1 Installation
29. in the following table 6 s 91 9 MAX V pin position Comments ON is Low OFF is High 2 2 Push Buttons SW0 SWI R45L 2 Push buttons are available push button down to direct the Low signal to the MAX V leave it without pushing for a High signal For the pin positions of the Push Buttons vs I O of MAX V Device please refer to the following table Devices 2 Push Buttons Push Button code MAX V pin position 108 107 Comments pushed down low level normal high level POC EiSBOSIRA GALAXY FAR EAST CORP 3 8 LEDs D1 D8 2 DA 05 D6 Di A i F EXE Ea DO DI 02 E When High signals are sent by MAX V I O the LED will light up the pin positions of the 8 LEDs vs I O of MAX V Device are listed in the following table Devices 8 LEDs Lie Di D2 0 p4 ps pe p7 D MAX V pin postion 106 165 104 163 102 101 98 97 Comments high level lit LED low level LED off 4 Oscillator Socket A half long oscillator socket is provided which can transmit Clock to the MAX V Device The appropriate frequency of the oscillator should be selected by the user when applying the clock source The output of this clock source is connected to the 89 Pin CLK 2 of MAX V CFEC Eege IR sl GALAXY FAR EAST CORP 5 VCC I O Voltage Selection 4 I O extension connectors are provided the VCC I O in 3 of the connectors is adjustable They are JP5 IO 2
30. isit http www altera com support licensing lic index html click Quartus II Web Edition Software License so you can apply for a free 17 CFEC SERA GALAXY FAR EAST CORP account of Quartus II License 4 Altera will then return a License dat file through e mail Open Tools gt License Setup window via the License file and place the Lincense dat there 5 When you see the figure as shown on the below this means that the installation 1s complete e Genaral EDA Tool Cie Fonts internet Connectivity Libr ar ie L l use LM LICENSE FILE variable nodelech_5 6c LICENSE DAT C est kee dat CETE Preferred Text Editor kandhaa anaa Wat Licores Update Proceseng License Type Full Version Espr atri apes 2012 Begin 30 03 Grace Period Host ID Type ME m Most D Value DDI D Wait for floating licenses Lienei AMPTP Megatore functions ABa AFT Color Space Converters VOUS 9979 12 Aera APT EIS Compiler 0012 aoa 1 Aera AF7 HO Compiler D014 9993 12 Alora BET Utopia Level 2 Slave 0016 goa 12 Alora 54F7 Litopla Level Mastor 0017 599912 Aera SAF7 PCI 32 bit Master Target 0022 9999 12 Alora SET PCL 64 bit Master Target DO11 9900 13 Aera SAT PCI 32 bit Target niy OW 9500 12 Afera amp AFT PCI 64 bit Target Only 0025 Q999 12 EETAEET 0034 Qr 12 gt omaso 0013348391 abada na j Not found e come we jJ C After Com
31. ition Paid Modelsim Altera Starter Edition Free LUE Nios Il Embedded Design Suite A EEA EN IK Bate your installation experience lt Back Step 7 Click Finish to complete installation cg Altera Software Installer 10 1 Build 153 Installation Please wait while the Altera software is installed Installation successful Components Cyclone ME Family Cyclone Iv GX Family Legacy Families MAX II Famil The Altera Software Installer has finished installing Altera Complete Design Suite software version 10 1 on your computer Start Quartus II 10 1 Create Desktop Shortcut Quartus Il Subscription Edition Paid hModelSim ltera Starter Edition Free gt Installation Nios Il Embedded Design Suite Rate your installation experience lt Back Finish Cancel OOC KE it Appendix B Installing Download Cable on Windows XP Win7 The download cable is a standard USB hardware interface which requires an additional driver under XP or Win 7 O S so that the burning of the chip can go through the USB interface Create new hardware on Windows XP Step 1 Start gt Setup gt Control panel gt System gt Hardware Hardware administrator New hardware wizard pops up gt click Next Y i yA Ma ESTA ERR feb TL EL mu eus PEER d nn 2X RSET SE EE ABE E Windows TH Windows Update E Windows HI fora oe Update CIE BENET ma m ME Ta 3 a ados
32. l logic elements 43 1 270 3 96 amp CJ Assembler E Quartus II 15 114 13 CJ TimeQuest Timing Analyz e ao gt o m i Full Compilation was successful 6 warnings y Hierarchy B Files P Dds p Tasks Bx Flow Compilation Task SG gt Compile Design EP Analysis 8 Synthesis amp Fitter Place amp Route amp M Assembler Generate pro w TimeQuest Timing Analyst amp EDA Netlist Writer wW Program Device Open Progra Type Message D Info Quartus II TimeQuest Timing Analyzer was successful errors 3 warnings j Info Quartus II Full Compilation was successful 0 errors 6 warnings System 16 i Extra Info A Info 72 X Warning 3 N Critical Warning 3 N Error A Suppressed 4 X Flag Message 0 of 136 4 location Locate 100 00 00 06 Part 5 Downloading the program Step 1 Open program Tools Programmer z Quartus II EZMAXV poj MAX V_MENU ledtest ledtest ledtest File Edit View Project Assignments Processing Pills Window Help i Dodo amp x E o ME led Run EDA Simulation Tool QS Dor 5 O Ola A Run EDA Timing Analysis Tool a Z Z Launch EDA Simulation Library Compiler Assignment Editor Project Mavigator Fow Summary Flow Status Successful Tue Jul 19 18 28 55 2011 MAX V SM12702T144C5 ES Flov 5 TimeQuest
33. logic unsigned all ip Back Annotate Assignments y package ALL Import Assignments RA Export Assignments AXPLUSZ ALL Assignment Groups Ul st IS a LogicLock Regions Window Alt L a Design Partitions Window Alt D STD LOGIC A dh Hierarchy PR eee RESET STD LOGIC Tasks ax 12 LED SEL STD LOGIC e Flow 14 LED STD LOGIC VECTOR 7 DOWNTO 0 des DIP 5 STD LOGIC VECTOR 3 DOWNTO Task 16 n We Sk Compile Design 17 S Sk Analysis 8 Synthesis 2 Dk Fitter Place 8 Route ca ib Assembler Generate programmini 19 Dk TimeQuest Timing Analysis EARCHITECTURE a OF ledtest IS be EDA Netlist Writer zu Prozam Device Open Programer SIGNAL LED REG STD LOGIC VECTOR 7 DOWNTO D n gt TONAL CNT TNTEGER RANGA N TO 4194303 w Type Message 4p Info Command quartus map read settings files on write settings files off ledtest c ledtest i Info Quartus II Create Symbol File was successful errors warnings 3 lt lii System Processing 4 Extra Info JA Info 4 Warning A Critical Warning X Error A Suppressed A Flag Edits assignments 100 00 00 02 Messages Step 2 Double click left lt NEW gt under the lt To gt column to open up the Node Finder as follows GALAXY FAR EAST CORP POC RRRGARAA Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest File Edit View Project Assignments Processing Tools Window Hel
34. nings gt lt System Processing 4 Extra Info AN Info 4 X Warning Critical Warning X Error JA Suppressed A Flag Message 0 of 10 t Location Locate 10096 00 00 02 Messages Step5 Type in the pin positions in the Value column as follows 33 OC ESBOSRA GALAXY FAR EAST CORP Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest LOX File Edit Yiew Project Assignments Processing Tools Window Help D Hg 62k mR Oo few NY e Ge G r 2 6H amp x es Project Navigator Bx dr ledtest vhd E L compilation Report 3 AssignmentEditor E lt lt new gt gt Filter on node names EN Category All A AX V 5M12702T144C5 Assignment Name Value Enabled ww ledtest E DIP_SW 0 Location IN 96 E DIP wii Location PIN_95 E Dip Sw 2 Location PIN 94 E DIP Sw 3 Location PIN 93 gt LED O Location PIN_106 gt LED 1 Location PIN 105 gt LED 2 Location PIN 104 i LED 3 Location PIN 103 PP LEDI4 Location PIN 102 Bris Pomp x LED 5 Location PIN_101 mx ies LED 6 Location PIN_98 Flow Compilation v LED 7 Location PIN_97 E LED SEL Location PIN 107 Task E RESET Location PIN_108 Compile Design D CLK Location PIN 89 Ee Analysis amp Synthesis dit ON pu bk Fitter Place amp Route bk Assembler Generate proi amp TimeQuest Timing Analys X This cell specifies the value
35. nish the project will be created with the following settings Project directory E MAXV poj MAX VM MENU ledtest Project name led test Top level design entity led test Number of files added 1 Number of user libraries added Device assignments Family name MAX V Hierarchy Device SM1270ZT144C5 EDA tools Design entry synthesis lt None gt lt None gt Flow Compilation Simulation lt None gt lt None gt Task Timing analysis lt None gt lt None gt Tasks amp b Compil Operating conditions Dk Ana j g k Fitt VCCINT voltage 1 8V Ass Ti Junction temperature range ORS E mx Processing X Extra Info Info A Warning N Critical Warning A Error A Suppressed A Flag 0 00 00 00 Messages Part 2 Create program file The input methods of circuits in Quartus II come with AHDL Block Diagram Schematic Verilog HDL and VHDL File etc however an example of Marquee in VHDL shall be introduced in this chapter To create a new VHDL program click File New to start a designing method click VHDL File under Design Files to open a new VHDL programming file In this example programmed codes have been prepared that will only open old files by ledtest vhd De B lt EPR e GALAXY FAR EAST CORP Quartos II EZMAXV poj MAX V MENU led New Quartus II Project H SORT Builder System Design Files 0 AHDL File Block Diagr
36. of the assignment E M EDA Netlist Writer E gt Program Device Open Progra oon OO SG Nr gt a Type Message 4p Info Command quartus map read settings files on write settings files off ledtest c ledtest m d Info Quartus II Create Symbol File was successful errors warnings lt System 16 Processing Extra Info Info 4 AN Warning A Critical Warning N Error A Suppressed Flag 100 GfOC NS DE Part4 Program compilation Step 1 Compilation Processing Start Compilation amp Quartus II EZMAXV poj MAX V MENU ledtest ledtest ledtest File Edit View Project Assignments Tools Window Help Ge G e A amp Ctrl Shift c Project Navigator m x Start Compilation etr Assignment Editor EJ Ki Analyze Current File Entity Start Max V SM1270ZT144CS Update Memory Initialization File EE SS yaks EA me ledtest Compilation Report CtrHR cen FIN 96 Location PIN_95 49 PowerPlay Power Analyzer Tool Location PIN_94 Y SSN Analyzer Tool Location gt LED 0 Location PINO 106 Bon Location PIN 105 o LED 2 Location PIN_104 ep LED 3 Location PIN 103 B Files disp gt LED 4 Location PIN 102 4 LED 5 Location PIN_101 TES az LED 6 Location PIN_98 Flow Compilation v LED 7 Location PIN 97 gt LED SEL Location PIN_107 Task gt RESET Location PIN 108 Eb Compile Design o gt CLK Location PIN 89 amp p Analysis 8
37. p DG ibi e c gt lledtest x R20 G gt 2 eh 0045 Project Navigator m x ledtest vhd compilation Report E assignment Editor EJ m lt lt new gt gt Filter on node names ei Category All nti From y MAX V 5MI270ZT144C5 aoe ledtest lt lt new gt gt gt amp Hierarchy B Files ol Design Units Tasks Bx Flow Compilation v Task B Compile Design amp analysis 8 Synthesis Bb Fitter Place amp Route amp Assembler Generate programmin SP TimeQuest Timing Analysis X This cell specifies the destination name for point to point assignments For single point assignments this cell specifies Hj b EDA Netlist Writer 8 the destination of the assignment Altera recommends using the Node Finder to assign a destination name gt Program Device Open Programmer UE Type Message Y Info Command quartus map read settings files on write settings files off ledtest c ledtest i Info Quartus II Create Symbol File was successful errors D warnings ili Extra Info Info 4 AN Warning N Critical Warning Error Suppressed Message O of 10 4 location Locate 10096 00 00 02 Messages Step 3 Click the selector key on the right of Look in in the Node Finder window and select ledtest then click list Modes Found Marne Assignments Type 1970771440
38. piler is done select Tools open Programmer 1 Select Hardware Setup 2 Highlight USB Blaster and click close CH Programmer Chain2 cdf File Edit View Processing Tools Window Hardware Setup USB Blaster USB 0 Mode TAG _ Enable real time ISP to allow background programming for MAX II and MAX V devices File Device Checksum Usercode Program Verify Blank Examine Security Erase ISP Pl Start Configure Check Bit CLAMP wh Stop gt Hardware Setup Bb Auto Detect X Delete Hardware Settings JTAG Settings b Add File Select a programming hardware setup tp use when programming devices This programming Arie a hardware setup applies only to the current programmer window oi e 15 Change File Currently selected hardware g88 Blaster USB 0 ab Save File Available hardware items S Add Device arcane Server Port Add Hardware Local USB 0 4 Up Remove Hardware Down z POC Eege IR sl GALAXY FAR EAST CORP Mode gt JTAG Add File gt select pof file If UFM is not in use check the following window Insert the USB Download cable into JP3 Insert USB into the Power Cable JP16 Press Start to burn ally Programmer Chain2 cdf File Edit View Processing Tools Window YY IE doter sanp EEE TA w J Enable real time ISP to allow background programming for MAX II and MAX V devices
39. power from JP4 IO3 by switching JP8 to EXT Pin amp 2 39 amp 40 of JP4 are for input of EXT Power SOC BiSBIOSRAU GALAXY FAR EAST CORP 9 JTAG 5X2 Header Connector The Altera MAX V Device comes with ISP In System Programming as a function insert the USB Download Cable sold separately into the USB port on the PC with the other end inserted into JP3 Use Altera s proprietary software Quartus II and then download the data onto this experimental board OC ESBOSRA GALAXY FAR EAST CORP Circuit diagram of this experimental board _102 INT _102 Bi P1 1 UR 20 D si BIP 3 106 L R28 LR 4 i D 5 6K 060 P 5 104 LED BL Posi 103 LED sw VCC lOi BPP 7 102 LEDS VOC 103 HI P o L EDA SW DIP L UU s DIP3 pi P27 2 BIP 29 vec Im Bi Pan pet BL 5 Viet T JN A HE EI mm DB5 TMS 33 A AN E iye D k D 10 EX GH eral iam IO R12p d D DO 35 WR Loa du Da 55K P SW DIP 4 Stactiac ac EpESESSOST ST NA Siess be an EDER tc 55655659856000056 le I VEMIZTOZ LEES H INT Dao doko A Ur c9 cio cit ctz D o ele leda NLED G S lee eege y VEC IO RR RRREERRERR AREE 0 1u 0603 0 1u 0603 0 1u 0603 0 1u 0603 VEC INT di AR x aue 1 EC 104 VEL 102 VE 102 a cta C14 Ct Cp Diu 060s ou i3 hu i3 bu 0603 d M De ct ctg ctg c20 IL 3 ou SN sl 0603 82 F141 B2 P139 BZ PIS Pn BZ PI P129 82 P125 B2 P
40. r pins of the JP4 to JP7 connectors are directly connected to I O of MAX V Device signals exceeding 3 3V are prohibited to connect to this connector Furthermore besides the partial pins connected to the MAX V Device some of them are also connected to other parts on the board e g LED Push Button etc and the user is advised to pay attention to the possible affect that expansion of the I O pin would have on these parts The mapping of the expansion of the I O connector vs MAX V Device can be found in the following table For the JP4 some of the pins are defined as external Asynchronous FIFO which enable MAX V to exchange data with other systems Doi BSD APRO e GALAXY FAR EAST CORP MAX V pin Connector position property VCC IO2 JP5 Pinl VCC IO2 JP5 Pin2 MAX V pin Connector position property VCC 101 JP6 Pin VCC 101 JP6 Pin2 ms mms vee ro m mmm s umma lm mme Dem ASAT S BRR ZS O e GALAXY FAR EAST CORP MAX V pin Connector MAX V pin Connector position property position property me mm e mm em amma mms oe amma mme mss amma la mme CFEC Eege IR sl GALAXY FAR EAST CORP 8 DC Input Connector TB The voltage regulator has been built in to this experimental board power can be obtained by inserting a USB cable into JP16 The LED D11 will light up when the power comes on Users are able to input working
41. xadecimal Intel Forrnat File Memory Initialization File E Mew Project Wizard B v erification Debugging Files H In System Sources and Probes File u j Logic Analyzer Interface File Ex Open Project Cre SignalTap II Logic Analyzer File Other Files Save Project AHDL Include File Block Symbol File Close Project Chain Description File N Save Cris Step 2 4 Double click on any blank space to open the symbol selection window where the ledtest symbol as built under Project can be found Libraries ER E Project CLE LED UI RESET LED SEL DIR Sww 3 0 Mame m Repeat insert mode Insert symbol as block Launch MegatWizard Plug In Megatvizard Plug In Manager Part 3 Designated chip pin positions Step 1 Quartus II provides several methods to designate pin positions by selecting 30 POC ESO SIRAU GALAXY FAR EAST CORP one of the them Assignments Assignment Editor menu Quartus II E MAXV poj MAX V_MENU ledtest ledtest ledtest File Edit View Project MENU Processing Tools Window Help Dela e 9 Device g ob D r Ses Y Settings Ctrl Shift E D a Project Navigator Compilation Report TimeQuest Timing Analyzer Wizard AAAA DS E El e 268 Assignment Editor Ctri Shift 4 Entity MAX v 5M12702T1440 Me bd ledtest Pin Planner CrhShiftN logic 1164 ALL Remove Assignments
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