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C8051F58x/F59x

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1. Bit 7 6 5 4 3 2 1 0 ARSEL ECOV COVF CLSEL 1 0 Type R W R W R W R R R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD9 SFR Page OxOF Bit Name Function 7 ARSEL Auto Reload Register Select This bit selects whether to read and write the normal PCAO capture compare registers or the Auto Reload registers at the same SFR addresses This function is used to define the reload value for 9 10 and 11 bit PWM modes In all other modes the Auto Reload registers have no function 0 Read Write Capture Compare Registers at PCAOCPHn and PCAOCPLn 1 Read Write Auto Reload Registers at and PCAOCPLn 6 ECOV Cycle Overflow Interrupt Enable This bit sets the masking of the Cycle Overflow Flag COVF interrupt 0 COVF will not generate PCAO interrupts 1 A PCAO interrupt will be generated when COVF is set 5 COVF Cycle Overflow Flag This bit indicates an overflow of the 8th 9th 10th or 11th bit of the main PCAO counter PCAO The specific bit used for this flag depends on the setting of the Cycle Length Select bits The bit can be set by hardware or software but must be cleared by software 0 No overflow has occurred since the last time this bit was cleared 1 An overflow has occurred since the last time this bit was cleared 4 2 Unused Read 000b Write Don t care 1 0 CLSEL 1 0 Cycle Length Select When 16 bit PWM
2. Timer 1 UART TL1 2 4 1 Detected P lt Timer ow 2 p RX Clock Figure 25 2 UART1 Baud Rate Logic Timer 1 should be configured for Mode 2 8 bit auto reload see Section 27 1 3 Mode 2 8 bit Counter Timer with Auto Reload on page 288 The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of six sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 the external oscillator clock 8 or an external input T1 For any given Timer 1 clock source the UART1 baud rate is determined by Equation 25 1 A and Equation 25 1 B A UartBaudRate 15 T1 Overflow Rate TI CLK B OK T1 Overflow Rate 256 THI Equation 25 1 UART1 Baud Rate Where is the frequency of the clock supplied to Timer 1 and T1H is the high byte of Timer 1 reload value Timer 1 clock frequency is selected as described in Section 27 Timers on page 285 A quick ref erence for typical baud rates and system clock frequencies is given in Table 25 1 Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1 266 Rev 1 3 SILICON LABS 8051 58 59 25 2 Operational Modes UART1 provides standard asynchronous full duplex communication The UA
3. Bit 7 6 5 4 3 2 1 0 OVRO PERRO THREO RENO TBXO RBXO TIO RIO Type R W R W R R W R W R W R W R W Reset 0 0 1 0 0 0 0 0 SFR Address 0x98 Bit Addressable SFR Page 0x00 Bit Name Function 7 OVRO Receive FIFO Overrun Flag 0 Receive FIFO Overrun has not occurred 1 Receive FIFO Overrun has occurred A received character has been discarded due to a full FIFO 6 PERRO Parity Error Flag When parity is enabled this bit indicates that a parity error has occurred It is set to 1 when the parity of the oldest byte in the FIFO does not match the selected Parity Type 0 Parity error has not occurred 1 Parity error has occurred This bit must be cleared by software 5 THREO Transmit Holding Register Empty Flag Firmware should use or poll on TIO rather than THREO for asynchronous UART writes that may have a random delay in between transactions 0 Transmit Holding Register not Empty do not write to SBUFO 1 Transmit Holding Register Empty it is safe to write to SBUFO 4 RENO Receive Enable This bit enables disables the UART receiver When disabled bytes can still be read from the receive FIFO 0 UART1 reception disabled 1 UART1 reception enabled 3 TBXO Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when is set to 1 This bit is not used when Parity is enabled 2 RBXO Extra Receive Bit
4. HILIHIL 4lo 1 1 0 0 1 0 1 0 Pre scaled Clock 0 SYSCLK gt Interrupt TRI THO T gt 8 bits gt Interrupt TLO D gt 8 bits Crossbar GATEO m I I I I Figure 27 3 TO Mode Block Diagram e 290 Rev 1 3 gt SILICON LABS 8051 58 59 SFR Definition 27 2 TCON Timer Control SILICON LABS Bit 7 6 5 4 3 2 1 0 Name TF1 TR1 TFO TRO IE1 IT1 IEO ITO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x88 Bit Addressable SFR Page All Pages Bit Name Function 7 TF1 Timer 1 Overflow Flag Set to 1 by hardware when Timer 1 overflows This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine 6 TR1 Timer 1 Run Control Timer 1 is enabled by setting this bit to 1 5 TFO Timer 0 Overflow Flag Set to 1 by hardware when Timer 0 overflows This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine 4 TRO Timer 0 Run Control Timer 0 is enabled by setting this bit to 1 3 IE1 External Interrupt 1 This flag is set by hardware when an edge level
5. SILICON LABS Parameter Description Min Max Units Master Mode Timing See Figure 26 8 and Figure 26 9 SCK High Time 1x ns SCK Low Time 1 5 Tuis MISO Valid to SCK Shift Edge 1 X Tsyscik 20 ns SCK Shift Edge to MISO Change 0 ns Slave Mode Timing See Figure 26 10 and Figure 26 11 Tse NSS Falling to First SCK Edge 2 X ns Tsp Last SCK Edge to NSS Rising 2 X TsyscLK ns NSS Falling to MISO Valid 4 nS Tspz NSS Rising to MISO High Z 4 X ns Tekh SCK High Time 5 X TsyscLK ns Teki SCK Low Time 5x TsyscLK ns Tsis MOSI Valid to SCK Sample Edge 2 X ns Sample Edge to MOSI Change 2 X ns TsoH SCK Shift Edge to MISO Change 4 nS Last SCK Edge to MISO Change 6 X 8 ns CKPHA 1 ONLY Note is equal to one period of the device system clock SYSCLK Rev 1 3 284 8051 58 59 27 Timers Each MCU includes six counter timers two 16 bit counter timers compatible with those found in the standard 8051 and the other four are 16 bit auto reload timers for use with the ADC SMBus or for gen eral purpose use These timers can be used to measure time intervals count external events and generate periodic interrupt requests Timer 0
6. Snapshot Register SYSCLK 12 SYSCLK 4 Timer 0 Overflow 010 c oo PCAOL P Interrupt System 011 SYSCLK 100 External Clock 8 101 a To PCA0 Modules Timer 4 Overflow 110 Timer 5 Overflow 111 Figure 28 2 PCAO Counter Timer Block Diagram 315 Rev 1 3 SILICON LABS 8051 58 59 28 2 PCAO Interrupt Sources Figure 28 3 shows a diagram of the PCAO interrupt tree There are five independent event flags that can be used to generate PCAO interrupt They as follows the main PCAO counter overflow flag CF which is set upon a 16 bit overflow of the PCAO counter an intermediate overflow flag COVF which can be set on an overflow from the 8th 9th 10th or 11th bit of the PCAO counter and the individual flags for each PCAO channel CCFO CCF1 CCF2 CCF3 CCF4 and CCF5 which are set according to the opera tion mode of that module These event flags are always set when the trigger condition occurs Each of these flags can be individually selected to generate a PCAO interrupt using the corresponding interrupt enable flag ECF for CF ECOV for COVF and ECCFn for each CCFn PCAO interrupts must be globally enabled before any individual interrupt sources are recognized by the processor interrupts are glob ally enabled by setting the EA bit and the EPCAO bit to log
7. Interrupt Source Interrupt Priority Pending Flag S Enable Priority Vector Order 5 Control 4 B s S lt 9 m Reset 0x0000 Top None N A N A Always Always Enabled Highest External Interrupt 0 0x0003 0 IEO TCON 1 Y JY IE 0 PXO IP 0 INTO Timer 0 Overflow 0x000B 1 TCON 5 Y ETO IE 1 PTO IP 1 External Interrupt 1 0x0013 2 IE1 TCON 3 Y EX1 IE 2 PX1 IP 2 INT1 Timer 1 Overflow 0 001 3 TF1 TCON 7 Y ET1 IE 3 PT1 IP 3 UARTO 0x0023 4 RIO SCONO 0 Y N ESO IE 4 PSO IP 4 TIO SCONO 1 Timer 2 Overflow 0x002B 5 TF2H TMR2CN 7 Y N ET2 5 PT2 IP 5 TF2L TMR2CN 6 SPIO 0x0033 6 SPIF SPIOCN 7 Y N ESPIO PSPIO WCOL SPIOCN 6 IE 6 IP 6 SPIOCN 5 RXOVRN SPIOCN 4 SMBO 0x003B 7 SI SMBOCN 0 Y N ESMBO PSMBO EIE1 0 EIP1 0 ADCO Window Com 0x0043 8 ADOWINT Y N EWADCO PWADCO pare ADCOCN 3 EIE1 1 1 1 ADCO Conversion 0x004B 9 ADOINT ADCOCN 5 Y N EADCO PADCO Complete EIE1 2 EIP1 2 Programmable 0x0053 10 CF 7 Y N EPCAO PPCAO Counter Array 0 CCFn PCAOCN n EIE1 3 EIP1 3 COVF PCAOPWM 6 0 005 11 CPOFIF 4 N N CPORIF 5 EIE1 4 1 4 Comparator1 0x0063 12 CP1FIF CPT1CN 4 N ECP1 PCP1 CP1RIF CPT1CN 5 EIE1 5 1 5 Timer 3 Overflow 0x006B 13 TF3H 7
8. yPCAOCPMn Wri PCAOCPHn 1 M O P PIT GM C n x 00 x PCAO Interrupt PCAOCN PCAOCPLn PCAOCPHn FIFIF FIF F j j 5 413 21110 0 Enab 16 bit Comparator Match oo TOGn Toggle 4 1 0 CEXn 1 x Crossbar Port I O Timebase gt P PCAOL PCAOH Figure 28 6 PCAO High Speed Output Mode Diagram 28 3 4 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCAO clocks to count before the output is toggled The frequency of the square wave is then defined by Equation 28 1 Fo CEXn 5x PCAOCPHn Note A value of 0x00 in the PCAOCPHnh register is equal to 256 for this equation Equation 28 1 Square Wave Frequency Output Where is the frequency of the clock selected by the CPS2 0 bits in the PCAO mode register PCAOMD The lower byte of the capture compare module is compared to the PCAO counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCAOCPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCAOCPMn reg ister Note that the MATn bit should normally be set to 0 in this mode If the
9. Name Pin Pin Pin Type Description F580 1 4 5 F588 9 F582 3 6 7 F590 1 48 pin 40 pin 32 pin P0 6 44 36 28 D I O or A In Port 0 6 P0 7 43 35 27 D I O or A In Port 0 7 P1 0 42 34 26 D I O or A In Port 1 0 See SFR Definition 20 17 for a description P1 1 41 33 25 D or A In Port 1 1 P1 2 40 32 24 D or A In Port 1 2 P1 3 39 31 23 D I O or A In Port 1 3 P1 4 38 30 22 D I O or A In Port 1 4 P1 5 37 29 21 D I O or A In Port 1 5 P1 6 36 28 20 D I O or A In Port 1 6 P1 7 35 27 19 D I O or A In Port 1 7 P2 0 34 26 18 D I O or A In Port 2 0 See SFR Definition 20 21 for a description P2 1 33 25 17 D I O or A In Port 2 1 P2 2 32 24 16 D I O or A In Port 2 2 P2 3 31 23 15 D I O or A In Port 2 3 P2 4 30 22 14 D I O or A In Port 2 4 P2 5 29 21 13 D I O or A In Port 2 5 P2 6 28 20 12 D I O or A In Port 2 6 P2 7 27 19 11 D I O or A In Port 2 7 P3 0 26 18 D I O or A In Port 3 0 See SFR Definition 20 25 for a description P3 1 25 17 D I O or A In Port 3 1 P3 2 24 16 D I O or A In Port 3 2 P3 3 23 15 DI Oor A In Port 3 3 P3 4 22 14 DI Oor A In Port 3 4 P3 5 21 13 DI Oor A In Port 3 5 P3 6 20 12 D I O or A In Port 3 6 25 Rev 1 3 SILICON LABS 8051 58 59 Table 3 1 Pin Definitions for the C8051F58x F59x Continued SILICON LABS Name Pin Pin Pin
10. 4 n 4 1 4 E D 4 1 n D 4 4 1 4 4 4 4 4 Internal VDD Monitor Low Threshold 1 6 5 46 System Clock Frequency MHz Rev 1 3 Figure 5 1 Maximum System Clock Frequency vs VDD Voltage VDMLVL 1b in SFR VDMOCN to prevent undefined CPU operation The high threshold should only be used with an external regulator powering Vpp directly See Figure 10 2 on page 90 for the recommended power With system clock frequencies greater than 25 MHz the monitor level should be set to the high threshold supply connections Note SILICON LABS 8051 58 59 Table 5 3 Port I O DC Electrical Characteristics Vpp 1 8 to 2 75 V 40 to 125 C unless otherwise specified Parameters Output High Voltage 3 mA Port I O push pull 10 pA Port I O push pull 10 mA Port I O push pull Output Low Voltage Vio 1 8 V lot 70 8 5 mA Vio 2 7 V loL 70 pA lo 8 5 mA Vio 5 25 V lo 70 uA lo 8 5 mA 40 400 Input High Voltage 0 7 x VIO Input Low Voltage VnEaiN 2 7 V 0 3 x VIO
11. J Ee 32 4 1 QFP 48 Package Specifications 32 4 2 QFN 48 Package Specifications 34 4 3 QFN 40 Package 2220 4 0 0 10 36 4 4 QFP 32 Package 5 38 4 5 QFN 32 Package 2 40 5 Electrical Characteristics Locos n 42 5 1 Absolute Maximum Specifications 42 5 2 Electrical Gh aracteriStiCS 43 6 12 Bit ADC ADG0 u e ovoe 54 6 1 Modes of Operaltion r 55 6 1 1 Starting a Conversion Pa pagus 55 6 1 2 Tracking 55 6 19 NTC T 56 6 1 4 Burst Mode 57 6 2 Output Code Formatting 59 6 2 1 Settling Time Requirements 59 6 3 Selectable Gain r 60 6 3 1 Calculating the Gain Value 60 6 3 2 Setting the Gain Value admet cocer v
12. epu put E ER 40 Figure 4 10 QFN 32 Package Drawing 41 Figure 5 1 Maximum System Clock Frequency vs VDD Voltage 46 Figure 6 1 ADCO Functional Block Diagram 54 Figure 6 2 ADCO Tracking Modes 000 56 Figure 6 3 12 Bit ADC Tracking Mode Example 57 Figure 6 4 12 Bit ADC Burst Mode Example With Repeat Count Set to 4 58 Figure 6 5 ADCO Equivalent Input Circuit De DE 60 Figure 6 6 ADC Window Compare Example Right Justified Data 71 Figure 6 7 ADC Window Compare Example Left Justified Data 71 Figure 6 8 ADCO Multiplexer Block Diagram 2 72 Figure 7 1 Temperature Sensor Transfer Function 74 Figure 8 1 Voltage Reference Functional Block Diagram 75 Figure 9 1 Comparator Functional Block Diagram 77 Figure 9 2 Comparator Hysteresis Plot 2 78 Figure 9 3 Comparator Input Multiplexer Block Diagram 85 Figure 10 1 External Capacitors for Voltage Regulator Input Output Regulator En abled RO 89 Figure 10 2 External Capacitors for Vol
13. Reset 0 0 0 0 0 0 0 1 Indirect Address 0x08 Bit Name Function 7 1 Reserved Reserved Must Write 00000000 0 GAINADD ADCO Additional Gain Bit Setting this bit add 1 64 0 016 gain to the gain value in the ADCOGNH and ADCOGNL registers Note This register is accessed indirectly See Section 6 3 2 for details for writing this register SILICON LABS Rev 1 3 64 8051 58 59 SFR Definition 6 4 ADCOCF ADCO Configuration Bit 7 6 5 4 3 2 1 0 Name ADOSC 4 0 ADORPT 1 0 GAINEN Type R W R W R W R W Reset 1 1 1 1 1 0 0 0 SFR Address 0xBC SFR Page 0x00 Bit Name Function 7 3 ADOSC 4 0 ADCO SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation where ADOSC refers to the 5 bit value held in bits ADOSC4 0 SAR Conversion clock requirements are given in the ADC specification table BURSTEN 0 FCLK is the current system clock BURSTEN 1 FLCLK is a maximum of 30 Mhz independent of the current system clock FCLK AD 05 1 Note Round up the result of the calculation for ADOSC 2 1 AORPT 1 0 ADCO Repeat Count Controls the number of conversions taken and accumulated between ADCO End of Conversion ADCINT and ADCO Window Comparator ADCWINT interrupts A con vert start is required for each conversion unless Burst Mode is enabled
14. 4 4 nnn 307 28 Programmable Counter Array 0 312 28 1 E De ut una ep p RE Ed 313 28 2 Interrupt 314 28 3 Capture Compare Modules a 319 28 3 1 Edge triggered Capture Mode 315 28 3 2 Software Timer Compare 316 28 3 3 High Speed Output MOG nacti titt eei epa cete 317 28 3 4 318 28 3 5 8 bit 9 bit 10 bit and 11 bit Pulse Width Modulator Modes 319 28 3 5 1 8 bit Pulse Width Modulator 319 28 3 5 2 9 10 11 bit Pulse Width Modulator 320 28 3 6 16 Bit Pulse Width Modulator 321 Rev 1 3 7 SILICON LABS 8051 58 59 28 4 Watchdog Timer Mode 322 28 4 1 Watchdog Timer 322 28 4 2 Watchdog Timer Usage
15. SFR Address OxF1 SFR Page OxOF Bit Name Function 7 0 POMDIN 7 0 Analog Configuration Bits for 7 0 0 respectively Port pins configured for analog mode have their weak pull up and digital receiver disabled For analog mode the pin also needs to be configured for open drain mode in the POMDOUT register 0 Corresponding PO n pin is configured for analog mode 1 Corresponding PO n pin is not configured for analog mode SFR Definition 20 15 POMDOUT Port 0 Output Mode Bit 7 6 5 4 3 2 1 0 POMDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA4 SFR Page Ox0F Bit Name Function 7 0 POMDOUTT 7 0 Output Configuration Bits for 7 0 0 respectively These bits are ignored if the corresponding bit in register POMDIN is logic 0 0 Corresponding 0 Output is open drain 1 Corresponding PO n Output is push pull 205 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 16 POSKIP Port 0 Skip These bits select Port 0 pins to be skipped by the Crossbar Decoder Port pins used for analog special functions or GPIO should be skipped by the Crossbar 0 Corresponding pin is not skipped by the Crossbar 1 Corresponding pin is skipped by the Crossbar Bit 7 6 5 4 3 2
16. SILICON LABS Name Pin Pin Pin Type Description F580 1 4 5 F588 9 F582 3 6 7 F590 1 48 pin 40 pin 32 pin VDD 4 4 4 Digital Supply Voltage Must be connected GND 6 6 6 Digital Ground Must be connected VDDA 5 5 5 Analog Supply Voltage Must be connected GNDA 7 7 7 Analog Ground Must be connected VREGIN 3 3 3 Voltage Regulator Input VIO 2 2 2 Port I O Supply Voltage Must be connected RST 12 10 10 D I O Device Reset Open drain output of internal POR or Vpp Monitor An external source can initiate a system reset by driving this pin low C2CK DVO Clock signal for the C2 Debug Interface C2D 11 D IO Bi directional data signal for the C2 Debug Interface P4 0 9 D or A In Port 4 0 See SFR Definition 20 29 for a description C2D D Bi directional data signal for the C2 Debug Interface P3 0 9 D or A In Port 3 0 See SFR Definition 20 25 for a description C2D D IO Bi directional data signal for the C2 Debug Interface 0 0 8 8 8 D or Port 0 0 See SFR Definition 20 13 for a description PO 1 1 1 1 D or A In 0 1 2 48 40 32 D I O or A Port 0 2 47 39 31 D I O or A In Port 0 3 P0 4 46 38 30 or A Port 0 4 P0 5 45 37 29 D I O or A In Port 0 5 Rev 1 3 24 8051 58 59 Table 3 1 Pin Definitions for the C8051F58x F59x Continued
17. 203 Rev 1 3 SILICON LABS 8051 58 59 20 6 Special Function Registers for Accessing and Configuring Port I O All Port are accessed through corresponding special function registers SFRs that are both byte addressable and bit addressable except for P4 which is only byte addressable When writing to a Port the value written to the SFR is latched to maintain the output data value at each pin When reading the logic levels of the Port s input pins are returned regardless of the XBRn settings i e even when the pin is assigned to another signal by the Crossbar the Port register can always read its corresponding Port pin The exception to this is the execution of the read modify write instructions that target a Port Latch reg ister as the destination The read modify write instructions when operating on a Port SFR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SETB when the destination is an individ ual bit in a Port SFR For these instructions the value of the latch register not the pin is read modified and written back to the SFR Ports 0 3 have a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig ital functions or skipped by the Crossbar All Port pins used for analog functions GPIO or dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1 The Port input mode of the I O pins is defined using the Port Inp
18. Reload Crossbar INTO a Figure 27 2 T0 Mode 2 Block Diagram 27 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only In Mode 3 Timer 0 is configured as two separate 8 bit counter timers held in TL0 and THO The counter timer in TLO is controlled using the Timer 0 control status bits in TCON and TMOD TRO C TO GATEO and TLO can use either the system clock or an external input signal as its timebase The THO register is restricted to a timer function sourced by the system clock or prescaled clock THO is enabled using the Timer 1 run control bit TR1 THO sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set tings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it for Mode 3 Rev 1 3 289 SILICON LABS 8051 58 59 CKCON TMOD 6 6 Gjc T T G C T T alalel2lolcic 1 1
19. 166 CLKSEL Clock Select 175 OSCICN Internal Oscillator Control 177 OSCICRS Internal Oscillator Coarse Calibration 178 OSCIFIN Internal Oscillator Fine Calibration 178 CLKMUL Clock Multiplier 2 180 OSCXON External Oscillator Control 182 XBRO Port I O Crossbar Register 0 194 XBR1 Port I O Crossbar Register 1 195 XBR2 Port I O Crossbar Register 2 196 XBRS3 Port I O Crossbar Register 197 POMASK Port 0 Mask Register 198 Port 0 Match Register 198 P1MASK Port 1 Mask Register 199 1 Port 1 Match Register 199 P2MASK Port 2 Mask Register 200 P2MAT Port 2 Match Register 200 Port 3 Mask Register 201 Port 3 Match Register 201 Mall
20. 211 SFR Definition 21 1 LINOADR LINO Indirect Address Register 219 15 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 21 2 SFR Definition 21 3 SFR Definition 22 1 SFR Definition 23 1 SFR Definition 23 2 SFR Definition 23 3 SFR Definition 24 1 SFR Definition 24 2 SFR Definition 24 3 SFR Definition 24 4 SFR Definition 24 6 SFR Definition 24 5 SFR Definition 25 1 SFR Definition 25 2 SFR Definition 26 1 SFR Definition 26 2 SFR Definition 26 3 SFR Definition 26 4 SFR Definition 27 1 SFR Definition 27 2 SFR Definition 27 3 SFR Definition 27 4 SFR Definition 27 5 SFR Definition 27 6 SFR Definition 27 7 LINODAT LINO Indirect Data Register 219 LINOCF LINO Control Mode Register 220 CANOCFG CAN Clock Configuration 236 SMBOCF SMBus Clock Configuration 243 SMBOCN SMBus Control n hid anie ete e Rin MEE 245 SMBODAT SMBus Data 247 SCONO Serial Port 0 Control 259 SMODO Serial Port 0 260 SBUFO Serial UARTO Port Data Buffer 261 SBCONO UARTO Baud Rate Generator Control 261 SBRLLO UARTO Baud Rate Generator Reload Low Byte 26
21. 276 aha in u D TD ORIENT MOON 283 27 1 Timer 0 and Timer 1 mr 285 27 1 1 Mode 0 13 bit Counter Timer 285 27 1 2 Mode 1 16 bit Counter Timer 286 27 1 3 Mode 2 8 bit Counter Timer with Auto Reload 286 27 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 287 Ig A DD 293 27 2 1 16 bit Timer with Auto Reload 293 27 2 2 8 bit Timers with 293 27 2 3 External Oscillator Capture 294 PREE 299 27 3 1 16 bit Timer with Auto Reload 299 27 3 2 B bit Timers with Auto BReload emere teneris 299 27 3 3 External Oscillator Capture 300 27 4 Timer 4 and Timer B codes ceci d tempu o xi 305 27 4 1 Configuring Timer 4 and 5 to Count 305 27 4 2 Capture Mode 305 27 4 3 Auto Reload 22 306 27 4 4 Toggle Output
22. SFR Definition 14 4 EIP1 Extended Interrupt Priority 1 Bit 7 6 5 4 3 2 1 0 Name PLINO PT3 1 PCPO PADCO PWADCO PSMBO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 SFR Address OxF6 SFR Page All Pages Bit Name Function 7 PLINO PT3 LINO Interrupt Priority Control This bit sets the priority of the LINO interrupt 0 LINO interrupts set to low priority level 1 LINO interrupts set to high priority level Timer 3 Interrupt Priority Control This bit sets the priority of the Timer 3 interrupt 0 Timer 3 interrupts set to low priority level 1 Timer 3 interrupts set to high priority level PCP1 0 CP1 Interrupt Priority Control This bit sets the priority of the CP1 interrupt 0 CP1 interrupt set to low priority level 1 CP1 interrupt set to high priority level PCPO 0 Interrupt Priority Control This bit sets the priority of the CPO interrupt 0 CPO interrupt set to low priority level 1 CPO interrupt set to high priority level Programmable Counter Array PCAO Interrupt Priority Control This bit sets the priority of the PCAO interrupt 0 PCAO interrupt set to low priority level 1 PCAO interrupt set to high priority level PADCO ADCO Conversion Complete Interrupt Priority Con
23. The level of Flash security depends on the Flash access method The three Flash access methods that can be restricted are reads writes and erases from the C2 debug interface user firmware executing on unlocked pages and user firmware executing on locked pages Table 15 1 summarizes the Flash security features of the C8051F58x F59x devices Table 15 1 Flash Security Summary if any page is locked Action C2 Debug User Firmware executing from interface an unlocked page a locked page Read Write or Erase unlocked pages Permitted Permitted Permitted except page with Lock Byte Read Write or Erase locked pages Not Permitted Flash Error Reset Permitted except page with Lock Byte Read or Write page containing Lock Byte Permitted Permitted Permitted if no pages are locked Read or Write page containing Lock Byte Not Permitted Flash Error Reset Permitted if any page is locked Read contents of Lock Byte Permitted Permitted Permitted if no pages are locked Read contents of Lock Byte Not Permitted Flash Error Reset Permitted Erase page containing Lock Byte Permitted Flash Error Reset Flash Error Reset if no pages are locked Erase page containing Lock Byte Unlock all C2 Device Flash Error Reset Flash Error Reset pages if any page is locked Erase Only Lock additional pages change 1s to 0 in the Lock Byte Not Permitted Flash Error Reset Flash Error Reset Unlock i
24. Internal Oscillator Frequency Divider Control Bits 000 SYSCLK derived from Internal Oscillator divided by 128 001 SYSCLK derived from Internal Oscillator divided by 64 010 SYSCLK derived from Internal Oscillator divided by 32 011 SYSCLK derived from Internal Oscillator divided by 16 100 SYSCLK derived from Internal Oscillator divided by 8 101 SYSCLK derived from Internal Oscillator divided by 4 110 SYSCLK derived from Internal Oscillator divided by 2 111 SYSCLK derived from Internal Oscillator divided by 1 179 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 19 3 OSCICRS Internal Oscillator Coarse Calibration Bit 7 6 5 4 3 2 1 0 Name OSCICRS 6 0 Reset 0 Varies Varies Varies Varies Varies Varies Varies SFR Address 0xA2 SFR Page OxOF Bit Name Function 7 Unused Read 0 Write Don t Care 6 0 OSCICRS 6 0 Internal Oscillator Coarse Calibration Bits These bits determine the internal oscillator period When set to 0000000b the internal oscillator operates at its slowest setting When set to 1111111b the inter nal oscillator operates at its fastest setting The reset value is factory calibrated to generate an internal oscillator frequency of 24 MHz SFR Definition 19 4 OSCIFIN Internal Oscillator Fine Calibration Bit 7 6 5 4 3 2 1 0 OSCIFIN 5 0 Type R R R
25. bine eios 138 15 1 3 Flash Write ProCed re u u u ter expe ndi un tue 139 15 1 4 Flash Write 139 15 2 Non volatile Data 140 15 3 Security Options RE 140 15 4 Flash Write and Erase Guidelines 142 15 4 1 Maintenance and the Monitor 142 15 4 2 PSWE Maintenance 142 154 3 System COG 143 16 Power Management Modes J J J 147 uo 147 16 2 eem C 148 16 3 Suspend Mode 148 17 Reset SourceS du dx MAS ARE Gd RN x cui M EU 150 17 1 Power On FSS Ob 151 17 2 Power Fail Reset VDD 2 22 4 0404 nennen 152 17 3 zu duri E 153 17 4 Missing Clock Detector 153 154 17 6 Watchdog Timer 154 17 7 Flash Error Reset t m 154 17 8 Software 154 18 External Da
26. Figure 27 9 Timer 3 External Oscillator Capture Mode Block Diagram Rev 1 3 303 SILICON LABS 8051 58 59 SFR Definition 27 13 TMR3CN Timer 3 Control Bit 7 6 5 4 3 2 1 0 T3SPLIT TR3 T3XCLK Type R W R W R W R W R W R W R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x91 SFR Page 0x00 Bit Name Function 7 Timer 3 High Byte Overflow Flag Set by hardware when the Timer 3 high byte overflows from OxFF to 0 00 In 16 bit mode this will occur when Timer 3 overflows from OxFFFF to 0x0000 When the Timer 3 interrupt is enabled setting this bit causes the CPU to vector to the Timer 3 interrupt service routine This bit is not automatically cleared by hardware 6 Timer 3 Low Byte Overflow Flag Set by hardware when the Timer low byte overflows from OxFF to 0x00 will be set when the low byte overflows regardless of the Timer 3 mode This bit is not automatically cleared by hardware 5 TFSLEN Timer 3 Low Byte Interrupt Enable When set to 1 this bit enables Timer 3 Low Byte interrupts If Timer 3 interrupts are also enabled an interrupt will be generated when the low byte of Timer 3 overflows 4 TF3CEN Timer 3 Capture Mode Enable 0 Timer 3 Capture Mode is disabled 1 Timer 3 Capture Mode is enabled 3 T3SPLIT Timer 3 Split Mode Enable When th
27. Input Leakage Current Weak Pullup Off Weak Pullup On Vio 2 1 V Vin 0 V Vpp 1 8 V Weak Pullup On 2 6 V Vin 0 V Vpp 2 6 V Weak Pullup On 5 0 V Vin 0 V Vpp 2 6 V 2 47 Rev 1 3 SILICON LABS 8051 58 59 Table 5 4 Reset Electrical Characteristics 40 to 125 C unless otherwise specified Parameter Conditions RST Output Low Voltage VIO 5 0 V IOL 70 pA RST Input High Voltage RST Input Low Voltage RST Input Pullup Current Vpp POR Threshold Vrst Low RST 0 0 V Vpp POR Threshold VnsT HiGH Vpp Ramp Time for Power On Vpp Ramp 0 1 8 V Missing Clock Detector Timeout Time from last system clock rising edge to reset initiation Vpp 2 1 V Vpp 2 5 V Reset Time Delay Delay between release of any reset source and code execution at location 0 0000 Minimum RST Low Time to Generate a System Reset Vpp Monitor Turn on Time Vpp Monitor Supply Current Table 5 5 Flash Electrical Characteristics Vpp 1 8 to 2 75 V 40 to 125 C unless otherwise specified Parameter Conditions Typ Units Flash Size C8051 F580 1 2 3 8 9 131072 C8051F584 5 6 7 F590 1 98304 Bytes Endurance 150 Erase Write Flash Retention 85 C 10 years Erase Cycle Time 25 MHz System Clock 28 30 ms Write Cycle Time
28. in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC Solid State Outline MO 220 variation VJJD 5 except for features A D2 and E2 which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Rev 1 3 36 SILICON LABS 8051 58 59 UD LI T T Y Figure 4 6 QFN 40 Landing Diagram Table 4 6 QFN 40 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 5 80 5 90 X2 4 10 4 20 C2 5 80 5 90 Yi 0 75 0 85 e 0 50 BSC Y2 4 10 4 20 X1 0 15 0 25 Notes General 1 All dimensions shown in millimeters mm unless otherwise noted 2 Dimension and Tolerancing is per the ANSI Y14 5M 1994 specification 3 This Land Pattern Design is based on the IPC SM 7351 guidelines 4 All dimensions shown are at Maximum Material Condition Least Material Condition LMC is calculated based on a Fabrication Allowance of 0 05 mm Solder Mask Design 5 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 um minimum all the way around the pad Stencil Design 6 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good sold
29. 323 28 5 Register Descriptions for 325 29 Programmable Counter Array 1 PCA1 331 29 1 POAT 332 29 2 Interrupt SOURCES 333 29 3 Capture Compare 8 334 29 3 1 Edge triggered Capture 335 29 3 2 Software Timer Compare 336 29 3 3 High Speed Output Mode 337 29 3 4 Frequency Output Mode nnne 338 29 3 5 8 bit 9 bit 10 bit and 11 bit Pulse Width Modulator Modes 339 29 3 5 1 8 bit Pulse Width Modulator 339 29 3 5 2 9 10 11 bit Pulse Width Modulator 341 29 3 6 16 Bit Pulse Width Modulator 342 29 4 Register Descriptions for PCA1 343 30 C2 NTE fACE e H 349 30 1 C2 Interface Registers r 349 30 2 G2 Pin Sharing waqa aN 353 D
30. 1 2 ass f 2 x C8051F582 IM 2 mA i C8051F583 IM P i C8051F586 IM 21 FS Meme Rmo gap e YDER gt i 8051F587 IM 5 2 1 6 GND rear a VIO VREGIN 9 P0 0 VREF sa pen o9 6 P30 C2D 9 RST 2 10 27 711 26 12 7 P25 13 P24 P23 P22 Figure 3 5 QFN 32 Pinout Diagram Top View 31 Rev 1 3 SILICON LABS 8051 58 59 4 Package Specifications 4 1 QFP 48 Package Specifications rl i Y 2 a E lt K i A tpm i p i Sm ECTION Lae TI
31. Name CF1 CR1 CCF6 CCF7 CCF8 CCF9 CCF10 CCF11 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD8 Bit Addressable SFR Page 0x10 Bit Name Function 7 CF1 PCA1 Counter Timer Overflow Flag Set by hardware when the PCA1 Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF1 interrupt is enabled setting this bit causes the CPU to vector to the interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CR1 PCA1 Counter Timer Run Control This bit enables disables the PCA1 Counter Timer 0 PCA1 Counter Timer disabled 1 PCA1 Counter Timer enabled CCF11 PCA1 Module 11 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF11 interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF10 PCA1 Module 10 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF10 interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF9 PCA1 Module 9 Capture Compare Flag This bit is set by hardware when
32. Optional 6 7 8 bit Data N bits N 5 6 7 or 8 Figure 24 2 UARTO Timing Without Parity or Extra Bit MARK START SPACE BIT TIMES Optional 6 7 8 bit Data N bits N 5 6 7 or 8 Figure 24 3 UARTO Timing With Parity mace XX SPACE BIT TIMES Optional 6 7 8 bit Data N bits N 5 6 7 or 8 Figure 24 4 UARTO Timing With Extra Bit Rev 1 3 258 SILICON LABS 8051 58 59 24 3 Configuration and Operation UARTO provides standard asynchronous full duplex communication It can operate in a point to point serial communications application or as a node on a multi processor serial interface To operate in a point to point application where there are only two devices on the serial bus the MCEO bit in SMODO should be cleared to 0 For operation as part of a multi processor communications bus the MCEO and XBEO bits should both be set to 1 In both types of applications data is transmitted from the microcontroller on the TXO pin and received on the pin The and pins are configured using the crossbar and the Port I O registers as detailed in Section 20 Port Input Output on page 188 In typical UART communications The transmit TX output of one device is connected to the receive RX input of the other device either directly or through a bus transceiver as shown in Figure
33. mV V Notes Represents one standard deviation from the mean Offset and full scale error can be removed through calibration additional 2 FCLK cycles are required to start and complete a conversion Additional tracking time may be required depending on the output impedance connected to the ADC input See Section 6 2 1 Settling Time Requirements on page 59 An increase in tracking time will decrease the ADC throughput See Section 6 3 Selectable Gain on page 60 for more information about the setting the gain 51 Rev 1 3 SILICON LABS 8051 58 59 Table 5 11 Temperature Sensor Electrical Characteristics VDDA 1 8 to 2 75 V 40 to 125 C unless otherwise specified Parameter Conditions Power Supply Current Tracking Time Note Represents one standard deviation from the mean Table 5 12 Voltage Reference Electrical Characteristics VDDA 1 8 to 2 75 V 40 to 125 unless otherwise specified Parameter Conditions Internal Reference REFBE 1 Output Voltage 25 C ambient REFLV 0 25 ambient REFLV 1 Vpp 2 6 V VREF Short Circuit Current VREF Temperature Coefficient Power Consumption Internal Load Regulation Load 0 to 200 HA to AGND VREF Turn on Time 1 4 7 uF and 0 1 uF bypass VREF Turn on Time 2 0 1 uF bypass Power
34. 26 1 Signal Descriptions The four signals used by SPIO MOSI MISO SCK NSS are described below 26 1 1 Master Out Slave In MOSI The master out slave in MOSI signal is an output from a master device and an input to slave devices It is used to serially transfer data from the master to the slave This signal is an output when SPIO is operat ing as a master and an input when SPIO is operating as a slave Data is transferred most significant bit first When configured as a master MOSI is driven by the MSB of the shift register in both 3 and 4 wire mode 26 1 2 Master In Slave Out MISO The master in slave out MISO signal is an output from a slave device and an input to the master device It is used to serially transfer data from the slave to the master This signal is an input when SPIO is operat ing as a master and an output when SPIO is operating as a slave Data is transferred most significant bit first The MISO pin is placed in a high impedance state when the SPI module is disabled and when the SPI operates in 4 wire mode as a slave that is not selected When acting as a slave in 3 wire mode MISO is always driven by the MSB of the shift register 26 1 3 Serial Clock SCK The serial clock SCK signal is an output from the master device and an input to slave devices It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines SPIO gen erates this signal when operating as a m
35. 8051 58 59 SFR Definition 20 2 XBR1 Port I O Crossbar Register 1 Bit 7 6 5 4 3 2 1 0 Name T1E TOE ECIE PCAOME 2 0 SYSCKE Reserved Type R W R W R W R W R W R R W R W Reset 0 0 0 0 0 0 0 0 SFR Address OxE2 SFR Page Ox0F Bit Name Function 7 TIE T1 Enable 0 T1 unavailable at Port pin 1 T1 routed to Port pin 6 TOE TO Enable 0 TO unavailable at Port pin 1 TO routed to Port pin 5 ECIE External Counter Input Enable 0 ECI unavailable at Port pin 1 ECI routed to Port pin 4 2 PCAOME 2 0 PCAO Module I O Enable Bits 000 All PCAO I O unavailable at Port pins 001 routed to Port pin 010 CEX1 routed to Port pins 011 CEX1 CEX2 routed to Port pins 100 CEX1 CEX2 CEX3 routed to Port pins 101 CEX1 CEX2 CEX3 CEX4 routed to Port pins 110 CEX1 2 CEX5 routed to Port pins 111 RESERVED 1 SYSCKE SYSCLK Output Enable 0 SYSCLK unavailable at Port pin 1 SYSCLK output routed to Port pin 0 Reserved Always Write to 0 197 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 3 XBR2 Port Crossbar Register 2 Bit 7 6 5 4 3 2 1 0 Name WEAKPUD XBARE Reserved CP2AE CP2E URT1E LINOE Type R W R W R W R W R W R W R
36. Adder Enable Note that the 8 bit offset held in 5 is compared to the upper byte of the 16 bit PCAO counter This offset value is the number of PCAOL overflows before a reset Up to 256 PCAO clocks may pass before the first PCAOL overflow occurs depending on the value of the PCAOL when the update is per formed The total offset is then given in PCAO clocks by Equation 28 5 where PCAOL is the value of the PCAOL register at the time of the update Offset 256 X PCAOCPL5 256 PCAOL Equation 28 5 Watchdog Timer Offset PCAO Clocks The WDT reset is generated when PCAOL overflows while there is a match between PCAOCPH5 PCAOH Software may force a WDT reset by writing a 1 to the CCF5 flag PCAOCN 5 while the WDT is enabled 28 4 2 Watchdog Timer Usage To configure the WDT perform the following tasks Disable the WDT by writing a O to the WDTE bit Select the desired PCAO clock source with the CPS2 CPSO bits Load PCAOCPLS with the desired WDT update offset value Configure the PCAO Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode Enable the WDT by setting the WDTE bit to 1 m Reset the WDT timer by writing to 5 325 Rev 1 3 SILICON LABS 8051 58 59 The clock source and Idle mode select cannot be changed while the WDT is enabled The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCAOMD register Whe
37. Figure 9 3 Comparator Input Multiplexer Block Diagram Rev 1 3 85 SILICON LABS 8051 58 59 SFR Definition 9 7 Comparator0 MUX Selection Bit 7 6 5 4 3 2 1 0 Name CMXON 3 0 3 0 R W R W Reset 0 1 1 1 0 1 1 1 SFR Address 0x9C SFR Page 0x00 Bit Name Function 7 4 CMXON 3 0 Comparator0 Negative Input MUX Selection 0000 PO 1 0001 P0 3 0010 P0 5 0011 7 0100 P1 1 0101 P1 3 0110 P1 5 0111 P1 7 1000 P2 1 1001 P2 3 1010 P2 5 1011 P2 7 1100 1111 3 0 CMXOP 3 0 Comparator0 Positive Input MUX Selection 0000 P0 0 0001 P0 2 0010 P0 4 0011 P0 6 0100 P1 0 0101 P1 2 0110 P1 4 0111 P1 6 1000 P2 0 1001 P2 2 1010 P2 4 1011 P2 6 1100 1111 None 86 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 9 8 CPT1MX Comparator1 MUX Selection Bit 7 6 5 3 2 1 Name 1 3 0 CMX1 P 3 0 Type R W R W Reset 0 1 1 1 0 1 1 1 SFR Address Ox9F SFR Page 0x00 Bit Name Function 7 4 CMX1N 3 0 Comparator1 Negative Input MUX Selection 0000 PO 1 0001 P0 3 0010 P0 5 0011 7 0100 1 1 0101 P1 3 0110 P1 5 0111 P1 7 1000 P2 1 1001 P2 3 1010 P2 5 1011 P2 7 1100 1111 3 0 CMX1P 3 0 Comparator1 Positive Input MUX Selection 0
38. Overflow c h 1 PCA1L Dl PCA1 Interrupt System CF1 Figure 29 2 PCA1 Counter Timer Block Diagram 334 Rev 1 3 SILICON LABS 8051 58 59 29 2 1 Interrupt Sources Figure 29 3 shows a diagram of the PCA1 interrupt tree There are five independent event flags that can be used to generate a PCA1 interrupt They are as follows the main PCA1 counter overflow flag CF1 which is set upon a 16 bit overflow of the PCA1 counter an intermediate overflow flag COVF1 which can be set on an overflow from the 8th 9th 10th or 11th bit of the PCA1 counter and the individual flags for each PCA1 channel CCF6 CCF7 CCF8 CCF9 CCF10 and CCF11 which are set according to the operation mode of that module These event flags are always set when the trigger condition occurs Each of these flags can be individually selected to generate a PCA1 interrupt using the corresponding interrupt enable flag ECF1 for CF1 ECOV1 for COVF1 and ECCF1n for each CCFn PCA1 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor 1 interrupts are globally enabled by setting the EA bit and the 1 bit to logic 1 for n 2 0 to 2 PCA1CPMn PCA1PWM PIEICICIMITIPIE PCA1CN PCA1
39. SILICON LABS 8051 58 59 SFR Definition 18 1 EMIOCN External Memory Interface Control Bit 7 6 5 4 3 2 1 0 Name PGSEL 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address OxAA SFR Page 0x00 Bit Name Function 7 0 PGSEL 7 0 XRAM Page Select Bits The XRAM Page Select Bits provide the high byte of the 16 bit external data memory address when using an 8 bit MOVX command effectively selecting a 256 byte page of RAM 0x00 0x0000 to 0x00FF 0x01 0x0100 to OxO1FF OxFE OxFEO0 to OxFEFF OxFF OxFFOO to OxFFFF SILICON LABS Rev 1 3 162 8051 58 59 SFR Definition 18 2 EMIOCF External Memory Configuration Bit 7 6 5 4 3 2 1 0 Name EMD2 EMD 1 0 EALE 1 0 Type R W Reset 0 0 0 0 0 0 1 1 SFR Address 0xB2 SFR Page Ox0F Bit Name Function 7 5 Unused Read 000b Write Don t Care 4 EMD2 EMIF Multiplex Mode Select Bit 0 EMIF operates in multiplexed address data mode 1 EMIF operates in non multiplexed mode separate address and data pins 3 2 EMD 1 0 EMIF Operating Mode Select Bits 00 Internal Only MOVX accesses on chip XRAM only All effective addresses alias to on chip memory space 01 Split Mode without Bank Select Accesses below the 8 kB boundary are directed on chip Accesses above the 8 kB boundary are directed off
40. When set to 0 the digital comparator is off For high speed and frequency output modes the associated pin will not toggle In any of the PWM modes this generates a 0 duty cycle output 0 5 D Selects whether the Capture Compare register 0 or the Auto Reload register 1 for the associated channel is accessed via addresses PCA1CPHn and PCA1CPLn 6 E When set a match event will cause the CCFn flag for the associated channel to be set 7 All modules set to 8 9 10 or 11 bit PWM mode use the same cycle length setting 336 Rev 1 3 SILICON LABS 8051 58 59 29 3 1 Edge triggered Capture Mode In this mode a valid transition on the CEXn pin causes PCA1 to capture the value of the 1 counter timer and load it into the corresponding module s 16 bit capture compare register PCA1CPLn and PCA1CPHn The CAPP1n and CAPN1n bits in the PCA1CPMn register are used to select the type of transition that triggers the capture low to high transition positive edge high to low transition negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCA1CN is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPP1n and CAPN1n bits are set to logic 1 then the st
41. 0 Bit Addressable SFR Page 0x00 Bit Name Description Read Write 7 MASTER SMBus Master Slave 0 SMBus operating in N A Indicator This read only bit slave mode indicates when the SMBus is 1 SMBus operating in operating as a master master mode 6 TXMODE SMBus Transmit Mode 0 SMBus in Receiver N A Indicator This read only bit Mode indicates when the SMBus is 1 SMBus in Transmitter operating as a transmitter Mode 5 STA SMBus Start Flag 0 No Start or repeated 0 No Start generated Start detected 1 When Configured as a 1 Start or repeated Start Master initiates a START detected or repeated START 4 STO SMBus Stop Flag 0 No Stop condition 0 No STOP condition is detected transmitted 1 Stop condition detected 1 When configured as a if in Slave Mode or pend Master causes a STOP ing if in Master Mode condition to be transmit ted after the next ACK cycle Cleared by Hardware 3 ACKRQ SMBus Acknowledge 0 No Ack requested N A Request 1 ACK requested 2 ARBLOST SMBus Arbitration Lost 0 No arbitration error N A Indicator 1 Arbitration Lost 1 ACK 5 Acknowledge 0 NACK received 0 Send NACK 1 ACK received 1 Send ACK 0 Sl SMBus Interrupt Flag 0 No interrupt pending 0 Clear interrupt and initi This bit is set by hardware 1 Interrupt Pending ate next state machine under the conditions listed in event Table 15 3 SI must be cleared 1 Force interrupt by software While Sl
42. 010 Muxed 8 bit WRITE with Bank Select ADDR 15 8 AD 7 0 Muxed 8 bit READ with Bank Select ADDR 15 8 AD 7 0 Figure 18 9 Multiplexed 8 bit MOVX with Bank Select Timing Rev 1 3 174 SILICON LABS 8051 58 59 Table 18 3 AC Parameters for External Memory Interface Parameter Description Min Max Units Tacs Address Control Setup Time 0 X ns Tacw Address Control Pulse Width 1 x Tsvscik 16x ns Address Control Hold Time 0 X TsyscLK ns TALEH Address Latch Enable High Time 1 x 4 X Tsysc_k ns TALEL Address Latch Enable Low Time 1 XTsvscik 4 X ns Twps Write Data Setup Time 1 XTsvscik 19xTsvscik nS TwpH Write Data Hold Time 0 3 X ns Tros Read Data Setup Time 20 ns Read Data Hold Time 0 ns Note is equal to one period of the device system clock SYSCLK 175 Rev 1 3 SILICON LABS 8051 58 59 19 Oscillators and Clock Selection C8051F58x F59x devices include a programmable internal high frequency oscillator an external oscillator drive circuit and a clock multiplier The internal oscillator can be enabled disabled and calibrated using the OSCICN OSCICRS and OSCIFIN registers as shown in Figure 19 1 The system clock can be sourced by the external oscillator circuit or th
43. 1 PCAO operation is suspended while the system controller is in Idle Mode 6 WDTE Watchdog Timer Enable If this bit is set PCAO Module 5 is used as the watchdog timer 0 Watchdog Timer disabled 1 PCAO Module 5 enabled as Watchdog Timer 5 WDLCK Watchdog Timer Lock This bit locks unlocks the Watchdog Timer Enable When WDLCK is set the Watchdog Timer may not be disabled until the next system reset 0 Watchdog Timer Enable unlocked 1 Watchdog Timer Enable locked 4 Unused Read 0b Write Don t care 3 1 CPS 2 0 PCAO Counter Timer Pulse Select These bits select the timebase source for the PCAO counter 000 System clock divided by 12 001 System clock divided by 4 010 Timer 0 overflow 011 High to low transitions on ECI max rate system clock divided by 4 100 System clock 101 External clock divided by 8 synchronized with the system clock 110 Timer 4 overflow 111 Timer 5 overflow 0 ECF PCAO Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCAO Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCAO Counter Timer Overflow interrupt request when CF PCAOCN 7 is set Note When the WDTE bit is set to 1 the other bits in the PCAOMD register cannot be modified To change the contents of the PCAOMD register the Watchdog Timer must first be disabled Rev 1 3 328 8051 58 59 SFR Definition 28 3 PWM Configuration
44. 25 MHz System Clock 79 84 us Vpp Write Erase operations 2 VRST HIGH V Temperature during Programming Opera Devices tions A Devices 40 1 On the 128K Flash devices 1024 bytes at addresses OxFCOO to OxFFFF Bank 3 are reserved 2 See Table 5 4 for the specification SILICON LABS Rev 1 3 8051 58 59 Table 5 6 Internal High Frequency Oscillator Electrical Characteristics Vpp 1 8 to 2 75 V 40 to 125 unless otherwise specified Using factory calibrated settings Parameter Conditions Min Max Oscillator Frequency IFCN 111b VDD gt VREGMIN IFCN 111b VDD lt VREGMIN 24 0 5 24 0 5 24 1 0 Oscillator Supply Current from Vpp Internal Oscillator On OSCICN 7 6 11b 1300 Internal Oscillator Suspend OSCICN 7 6 00b ZTCEN 1 Temp 25 Temp 85 Temp 125 Wake up Time From Suspend Power Supply Sensitivity OSCICN 7 6 00b Constant Temperature 0 13 V Temperature Sensitivity3 Constant Supply TC 5 0 0 65 ppm C VREGMIN is the minimum output of the voltage regulator for its low setting REGOCN REGOMD Ob See Table 5 9 Voltage Regulator Electrical Characteristics on page 50 This is the average frequency across the operating temperature range Use temperature coefficients
45. 4 044 4 99 SFR Definition 11 5 B B Register 99 SFR Definition 11 6 PSW Program Status Word 100 SFR Definition 11 7 SNn Serial Number 101 SFR Definition 12 1 PSBANK Program Space Bank Select 104 SFR Definition 13 1 SFROCN SFR Page Control 113 SFR Definition 13 2 SFRPAGE SFR Page seen 114 SFR Definition 13 3 SFRNEXT SFR 115 SFR Definition 13 4 SFRLAST SFR Last 116 SFR Definition 14 1 IE Interrupt Enable 130 SFR Definition 14 2 IP Interrupt Priority 224 8881 131 SFR Definition 14 3 EIE1 Extended Interrupt Enable 1 132 SFR Definition 14 4 EIP1 Extended Interrupt Priority 1 133 SFR Definition 14 5 EIE2 Extended Interrupt Enable 2 134 SFR Definition 14 6 EIP2 Extended Interrupt Priority Enabled 2 135 SFR Definition 14 7 ITO1CF INTO INT1 Configuration 1 137 SFR Definition 15 1 PSCTL Program Store R W Control 143 SFR Definition 15
46. OxOF Bit Name Function 7 MULEN MULINIT Clock Multiplier Enable 0 Clock Multiplier disabled 1 Clock Multiplier enabled Clock Multiplier Initialize This bit is 0 when the Clock Multiplier is enabled Once enabled writing a 1 to this bit will initialize the Clock Multiplier The MULRDY bit reads 1 when the Clock Mul tiplier is stabilized MULRDY Clock Multiplier Ready 0 Clock Multiplier is not ready 1 Clock Multiplier is ready PLL is locked 4 2 MULDIV 2 0 Clock Multiplier Output Scaling Factor 000 Clock Multiplier Output scaled by a factor of 1 001 Clock Multiplier Output scaled by a factor of 1 010 Clock Multiplier Output scaled by a factor of 1 011 Clock Multiplier Output scaled by a factor of 2 3 100 Clock Multiplier Output scaled by a factor of 2 4 1 2 101 Clock Multiplier Output scaled by a factor of 2 5 110 Clock Multiplier Output scaled by a factor of 2 6 1 3 111 Clock Multiplier Output scaled by a factor of 2 7 Note The Clock Multiplier output duty cycle is not 5096 for these settings MULSEL 1 0 Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier Clock Multiplier Output MUESELTIgI for MULDIV 2 0 000b Selected Input Clock 00 Internal Oscillator Internal Oscillator x 2 01 External Oscillator External Oscillator x 2 10 Internal Oscillator Internal O
47. Philips Semiconductor 2 The 12 Specification Version 2 0 Philips Semiconductor 3 System Management Bus Specification Version 1 1 SBS Implementers Forum 23 2 SMBus Configuration Figure 23 2 shows a typical SMBus configuration The SMBus specification allows any recessive voltage between 3 0 V and 5 0 V different devices on the bus may operate at different voltage levels The bi direc tional SCL serial clock and SDA serial data lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high recessive state when the bus is free The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns respectively VIO 5V VIO 3 V VIO 5V VIO 3V SDA SCL Figure 23 2 Typical SMBus Configuration 23 3 SMBus Operation Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters atte
48. SFR Definition 6 9 ADCOGTH ADCO Greater Than Data High Byte Bit 7 6 5 4 3 1 0 Name ADCOGTH 7 0 Reset 1 1 1 1 1 1 SFR Address 0xC4 SFR Page 0x00 Bit Name Function 7 0 ADCOGTH 7 0 ADCO Greater Than Data Word High Order Bits SFR Definition 6 10 ADCOGTL ADCO Greater Than Data Low Byte Bit 7 6 5 4 3 1 0 ADCOGTL 7 0 Reset 1 1 1 1 1 1 1 SFR Address 0xC3 SFR Page 0x00 Bit Name Function 7 0 ADCOGTL 7 0 ADCO Greater Than Data Word Low Order Bits 69 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 6 11 ADCOLTH ADCO Less Than Data High Byte Bit 7 6 5 4 3 Name ADCOLTH 7 0 Reset 0 0 0 0 0 SFR Address 0xC6 SFR Page 0x00 Bit Name Function 7 0 ADCOLTH 7 0 ADCO Less Than Data Word High Order Bits SFR Definition 6 12 ADCOLTL ADCO Less Than Data Low Byte Bit 7 6 5 4 3 Name ADCOLTL 7 0 Reset 0 0 0 0 0 SFR Address 0xC5 SFR Page 0x00 Bit Name Function 7 0 ADCOLTL 7 0 ADCO Less Than Data Word Low Order Bits 6 4 1 Window Detector In Single Ended Mode Figure 6 6 shows two example window comparisons for right justified data with
49. SILICON LABS C8051F58x F59x Mixed Signal ISP Flash MCU Family Analog Peripherals 12 Bit ADC Up to 200 ksps Up to 32 external single ended inputs VREF from on chip VREF external pin or Vpp Internal or external start of conversion source Built in temperature sensor Three Comparators Programmable hysteresis and response time Configurable as interrupt or reset source Low current On Chip Debug On chip debug circuitry facilitates full speed non intrusive in system debug no emulator required Provides breakpoints single stepping inspect modify memory and registers Superior performance to emulation systems using ICE chips target pods and sockets Low cost complete development kit Supply Voltage 1 8 to 5 25 V Typical operating current 15 mA at 50 MHz Typical stop mode current 230 uA High Speed 8051 Core Pipelined instruction architecture executes 70 of instructions in 1 or 2 system clocks Up to 50 MIPS throughput with 50 MHz clock Expanded interrupt handler Automotive Qualified Temperature Range 40 to 125 C Memory 8448 bytes internal data RAM 256 8192 XRAM 1280r 96 kB Banked Flash In system programma ble in 512 byte Sectors External 64 kB data memory interface programma ble for multiplexed or non multiplexed mode Digital Peripherals 40 33 or 25 Port I O All 5 V push pull with high sink current CAN 2 0 Controller no crystal required LIN 2 1 Control
50. Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0 9 SFR Page 0x00 Bit Name Function 7 0 PCAO 7 0 PCA0 Counter Timer Low Byte The PCAOL register holds the low byte LSB of the 16 bit PCAO Counter Timer Note When the WDTE bit is set to 1 the PCAOL register cannot be modified by software To change the contents of the PCAOL register the Watchdog Timer must first be disabled SFR Definition 28 6 PCAO Counter Timer High Byte Bit 7 6 5 4 3 2 1 0 Name PCAO 15 8 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address SFR Page 0x00 Bit Name Function 7 0 PCAO 15 8 PCAO Counter Timer High Byte The PCAOH register holds the high byte MSB of the 16 bit PCAO Counter Timer Reads of this register will read the contents of a snapshot register whose contents are updated only when the contents of PCAOL are read see Section 28 1 Note When the WDTE bit is set to 1 the PCAOH register cannot be modified by software To change the contents of the PCAOH register the Watchdog Timer must first be disabled 331 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 28 7 PCAOCPLn PCAO Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 Name PCAOCPn 7 0 RW R W R W R W R W R W R W R W Reset 0 0 0 0 0
51. Updated 20 1 Port I O Modes of Operation to remove note regarding interfacing to voltages above VIO Updated 23 SMBus to remove all hardware ACK features including SMBOADM and SMBOADR SFRs Updated 24 3 2 Data Reception to clarify UART receive FIFO behavior Updated SFR Definition 24 1 SCONO to correct SFR Page to 0x00 from All Pages Various formatting changes and corrections throughout the document Note All items from the C8051F58x 59x Errata dated July 1 2009 are incorporated into this data sheet Revision 1 1 to Revision 1 2 Updated 1 System Overview with a voltage range specification for the internal oscillator Updated Table 5 6 Internal High Frequency Oscillator Electrical Characteristics on page 49 with new conditions for the internal oscillator accuracy The internal oscillator accuracy is dependent on the operating voltage range Updated 5 Electrical Characteristics to remove the internal oscillator curve across temperature diagram Updated Figure 6 4 with new timing diagram when using CNVSTR pin Updated SFR Definition 8 1 REFOCN with oscillator suspend requirement for ZTCEN Fixed incorrect cross references in 9 Comparators Updated SFR Definition 10 1 REGOCN with a new definition for Bit 6 The bit 6 reset value is 1b and must be written to 1b Updated SFR Definition 12 1 PSBANK with correct reset value Updated 16 3 Suspend Mode with note regarding ZTCEN Rev 1 3 356 S
52. den of switching SFR pages from the interrupt service routine Upon execution of the RETI instruction the SFR page is automatically restored to the SFR Page in use prior to the interrupt This is accomplished via a three byte SFR Page Stack The top byte of the stack is SFRPAGE the current SFR Page The second byte of the SFR Page Stack is SFRNEXT The third or bottom byte of the SFR Page Stack is SFRLAST Upon an interrupt the current SFRPAGE value is pushed to the SFRNEXT byte and the value of SFRNEXT is pushed to SFRLAST Hardware then loads SFRPAGE with the SFR Page containing the flag bit associated with the interrupt On a return from interrupt the SFR Page Stack is popped resulting in the value of SFRNEXT returning to the SFRPAGE register thereby restoring the SFR page context without software intervention The value in SFRLAST 0x00 if there is no SFR Page value in the bottom of the stack of the stack is placed in SFRNEXT register If desired the values stored in SFRNEXT and SFR LAST may be modified during an interrupt enabling the CPU to return to a different SFR Page upon exe cution of the RETI instruction on interrupt exit Modifying registers in the SFR Page Stack does not cause a push or pop of the stack Only interrupt calls and returns will cause push pop operations on the SFR Page Stack On the C8051F58x F59x devices vectoring to an interrupt will switch SFRPAGE to page 0x00 except for the CANO interrupt which will switch SF
53. ting the ET1 bit in the IE register Section 14 2 Interrupt Register Descriptions on page 129 Both counter timers operate in one of four primary modes selected by setting the Mode Select bits 1 1 0 0 in the Counter Timer Mode register TMOD Each timer can be configured independently Each operating mode is described below 27 1 1 Mode 0 13 bit Counter Timer Timer 0 and Timer 1 operate as 13 bit counter timers in Mode 0 The following describes the configuration and operation of Timer 0 However both timers operate identically and Timer 1 is configured in the same manner as described for Timer 0 The THO register holds the eight MSBs of the 13 bit counter timer TLO holds the five LSBs in bit positions TLO 4 TLO 0 The three upper bits of TLO TLO 7 TLO 5 are indeterminate and should be masked out or ignored when reading As the 13 bit timer register increments and overflows from Ox1FFF all ones to 0x0000 the timer overflow flag TCON 5 is set and an interrupt will occur if Timer 0 interrupts are enabled The C TO bit TMOD 2 selects the counter timer s clock source When is set to logic 1 high to low transitions at the selected 0 input pin increment the timer register Refer to Section 20 3 Priority Crossbar Decoder on page 192 for information on selecting and configuring external I O pins Clearing C T selects the clock defined by the TOM bit CKCON 3 When TOM is set Timer 0 is
54. 16 bit timer register increments and overflows from OxFFFF to 0 0000 the 16 bit value in the Timer 3 reload registers TMR3RLH and TMR8RLL is loaded into the Timer 3 register as shown in Figure 27 7 and the Timer 3 High Byte Overflow Flag TMR3CN 7 is set If Timer interrupts are enabled an interrupt will be generated on each Timer 3 overflow Additionally if Timer 3 interrupts are enabled and the TF3LEN bit is set 5 an interrupt will be generated each time the lower 8 bits TMR3L overflow from OxFF to 0x00 T3XCLK SYSCLK 12 T To SMBus SMBus Overflow TR3 TCLK External Clock 8 TMRSL TMR3H SYSCLK E TMRSRLL TMR3RLH Reload Interrupt z o e a E Figure 27 7 Timer 3 16 Bit Mode Block Diagram 27 3 2 8 bit Timers with Auto Reload When T3SPLIT is set Timer 3 operates as two 8 bit timers TMR3H and TMR3L Both 8 bit timers oper ate in auto reload mode as shown in Figure 27 8 TMR3RLL holds the reload value for TMR3L TMR3RLH holds the reload value for TMR3H The bit in handles the run control for TMR3H TMR3L is always running when configured for 8 bit Mode Each 8 bit timer may be configured to use SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 The Timer Clock Select bits and T3ML in CKCON select either SYSCLK or the clock defined by the Ti
55. 23 2 SMBus Configuration 238 23 3 SMBus Operation MD 238 23 3 1 Transmitter Vs 2 239 23 3 9 MAO RET 239 23 3 3 Glock LOW EXIORSIO sse rat wa nda n rd 239 23 3 4 SCL Low TNS OU e 239 23 3 5 SCL High SMBus Free Timeout 240 23 4 Using the SMBus r 240 23 4 1 SMBUS Configuration Register 240 23 4 2 SMB0CN Control Register 244 23 5 3 Data Register us uuu n ue 247 23 5 SMBus Transfer 247 23 5 1 Write Sequence Master 248 23 5 2 Read Sequence Master 249 23 5 3 Write Sequence 2 20 20 404 250 23 5 4 Head Sequence Slave ene kan ne toa 251 23 5 SMBus Status Decoding n ERE n nero edes 251 24 Q 254 24 1 Baud Rate Generator 254 24 2 Data ET S m TT 256 24 3 Configuration and Operation ue Sta 257 24
56. 59 Write to PCAOCPLn Reset Wri PCAOCPHn Interrupt W PCAOCPLn 6 n x 00 00 T 16 bit Comparator HIS PCAO eser PCAOL Figure 28 5 PCAO Software Timer Mode Diagram 28 3 3 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCAO Counter and the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Setting the TOGn MATn and ECOMnh bits the PCAOCPMn register enables the High Speed Output mode If ECOMn is cleared the associated pin will retain its state and not toggle on the next match event Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Cap ture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 319 Rev 1 3 SILICON LABS 8051 58 59 Write to PCAOCPLn Reset
57. 8051 58 59 SFR Definition 20 24 P2SKIP Port 2 Skip Bit 7 6 5 4 3 2 1 0 Name P2SKIP 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0 06 SFR Page OxOF Bit Name Function 7 0 P2SKIP 7 0 Port 2 Crossbar Skip Enable Bits These bits select Port 2 pins to be skipped by the Crossbar Decoder Port pins used for analog special functions or GPIO should be skipped by the Crossbar 0 Corresponding P2 n pin is not skipped by the Crossbar 1 Corresponding P2 n pin is skipped by the Crossbar SFR Definition 20 25 P3 Port 3 Bit 7 6 5 4 3 2 1 0 Name P3 7 0 Type R W Reset 1 1 1 1 1 1 1 1 SFR Address 0 0 SFR Page All Pages Bit Addressable Bit Name Description Write Read 7 0 PS 7 0 Port Data 0 Set output latch to logic 0 P3 n Port is logic Sets the Port latch logic LOW LOW value or reads the Port pin 1 Set output latch to logic 1 P3 n Port pin is logic logic state in Port cells con HIGH HIGH figured for digital I O Note Port P3 1 P3 6 are only available on the 48 pin and 40 pin packages Rev 1 3 210 SILICON LABS 8051 58 59 SFR Definition 20 26 P3MDIN Port 3 Input Mode Bit 7 6 5 4 3 2 1 0 P3MDIN 7 0 Reset 1 1 1 1 1 1 1 1
58. Note that false rising edges and falling edges can be detected when the comparator is first powered on if changes are made to the hysteresis or response time control bits Therefore it is recommended that the rising edge and falling edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed SFR Definition 9 1 CPTOCN Comparator0 Control Bit 6 5 4 3 2 1 0 Name CPOEN CPOOUT CPORIF CPOFIF CPOHYP 1 0 CPOHYN 1 0 Type R W R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x9A SFR Page 0x00 Bit Name Function CPOEN ComparatorO Enable Bit 0 ComparatorO Disabled 1 ComparatorO Enabled CPOOUT Comparator0 Output State Flag 0 Voltage on CP0 lt 1 Voltage on CP0 gt CPO CPORIF Comparator0 Rising Edge Flag Must be cleared by software 0 No ComparatorO Rising Edge has occurred since this flag was last cleared 1 Rising Edge has occurred 3 2 CPOFIF 1 0 Comparator0 Falling Edge Flag Must be cleared by software 0 No Falling Edge has occurred since this flag was last cleared 1 Falling Edge has occurred Comparator0 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hyste
59. OxFC PCA1CPH7 OxEA PCA1CPH8 OxEC PCA1CPH9 OxEE PCA1CPH10 OxFE PCA1CPH11 OXCF SFR Page all registers 0x10 Bit Name Function 7 0 PCA1CPn 15 8 PCA1 Capture Module High Byte The PCA1CPHn register holds the high byte MSB of the 16 bit capture module n This register address also allows access to the high byte of the corresponding PCA1 channel s auto reload value for 9 10 or 11 bit PWM mode The ARSEL1 bit in register PCA1PWM controls which register is accessed Note A write to this register will set the module s 1 bit to a 1 350 Rev 1 3 SILICON LABS 8051 58 59 30 C2 Interface C8051F58x F59x devices include an on chip Silicon Labs 2 Wire C2 debug interface to allow Flash pro gramming and in system debugging with the production part installed in the end application The C2 inter face uses a clock signal 2 and a bi directional C2 data signal C2D to transfer information between the device and a host system See the C2 Interface Specification for details on the C2 protocol 30 1 C2 Interface Registers The following describes the C2 registers necessary to perform Flash programming through the C2 inter face All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification C2 Register Definition 30 1 C2ADD C2 Address Bit 7 6 5
60. RBXO is assigned the value of the extra bit when XBE1 is set to 1 If XBE1 is cleared to 0 RBX1 will be assigned the logic level of the first stop bit This bit is not valid when Parity is enabled 1 TIO Transmit Interrupt Flag Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit When the UARTO interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by software 0 RIO Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UARTO set at the STOP bit sampling time When the UARTO interrupt is enabled setting this bit to 1 causes the CPU to vector to the UARTO ISR This bit must be cleared manually by soft ware Note that RIO will remain set to 1 as long as there is data still in the UART FIFO RIO can be cleared after the last byte has been shifted from the FIFO to SBUFO 261 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 24 2 SMODO Serial Port 0 Control Bit 7 6 5 4 3 2 1 0 Name SOPT 1 0 PEO SODL 1 0 XBEO SBLO Type R W R W R R W R W R W R W R W Reset 0 0 0 0 1 1 0 0 SFR Address 0 9 SFR Page 0x00 Bit Name Function 7 MCEO Multiprocessor Communication Enable 0 RIO will be activated if stop bit s are 1 1 RIO will be activated if stop bit s and extra bit are 1 Extra bit must be enabled using
61. Reset 0 0 0 0 0 0 1 0 SFR Address Ox9E SFR Page 0x00 Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 CP1RIE Comparator1 Rising Edge Interrupt Enable 0 Comparator1 Rising edge interrupt disabled 1 Comparator1 Rising edge interrupt enabled 4 CP1FIE Comparator1 Falling Edge Interrupt Enable 0 Comparator1 Falling edge interrupt disabled 1 Comparator1 Falling edge interrupt enabled 3 2 Unused Read 00b Write don t care 1 0 CP1MD 1 0 Comparator1 Mode Select These bits affect the response time and power consumption for Comparator1 00 Mode 0 Fastest Response Time Highest Power Consumption 01 Mode 1 10 Mode 2 11 Mode 3 Slowest Response Time Lowest Power Consumption 82 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 9 5 2 Comparator2 Control Bit 6 5 4 3 2 1 0 Name CP2EN CP2OUT CP2RIF CP2FIF CP2HYPT1 0 CP2HYN 1 0 Type R W R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x9A SFR Page 0x10 Bit Name Function 7 CP2EN 2 Comparator2 Enable Bit 0 Comparator2 Disabled 1 Comparator2 Enabled Comparator2 Output State Flag 0 Voltage on CP2 lt CP2 1 Voltage on CP2 gt CP2 CP2RIF Comparator2 Rising Edge Flag Must be cleared by software 0 No Comparato
62. TMRnCN 6 will be set to 1 and an interrupt will occur if the interrupt is enabled See Section 14 Interrupts on page 126 for further information concerning the configuration of interrupt sources As the 16 bit timer register increments and overflows TMRnH TMRnL the TFn Timer Overflow Underflow Flag TMRnCN 7 is set to 1 and an interrupt will occur if the interrupt is enabled The timer can be config ured to count down by setting the Decrement Enable Bit TMRnCF 0 to 1 This will cause the timer to dec rement with every timer clock count event and underflow when the timer transitions from 0x0000 to OxFFFF Just as in overflows the Overflow Underflow Flag TFn will be set to 1 and an interrupt will occur if enabled Rev 1 3 307 SILICON LABS 8051 58 59 Counter Timer with Capture mode is selected by setting the Capture Reload Select bit CPRLn 0 and the Timer 4 and 5 Run Control bit TRn TMRnCN 2 to logic 1 The Timer 4 and 5 respec tive External Enable EXENn TMRnCN 3 must also be set to logic 1 to enable captures If EXENn is cleared transitions on TnEX will be ignored TMRnCF nin O n C 110 T Toggle Logic 2 N AN 0 E p Tn OxFF OxFF i SYSCLK
63. clocked by the system clock When TOM is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON see SFR Definition 27 1 Setting the TRO bit TCON 4 enables the timer when either GATEO TMOD 3 is logic 0 or the input signal INTO is active as defined by bit INOPL in register ITO1CF see SFR Definition 14 7 Setting GATEO to 1 allows the timer to be controlled by the external input signal INTO see Section 14 2 Interrupt Register Descriptions on page 129 facilitating pulse width measurements TRO GATEO INTO Counter Timer 0 X X Disabled 1 0 x Enabled 1 1 0 Disabled 1 1 1 Enabled Note X Don t Care Setting TRO does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and 1 form the 13 bit register for Timer 1 in the same manner as described above for TLO and THO Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 the INT1 polarity is defined by bit INTPL in register ITO1CF see SFR Definition 14 7 Rev 1 3 287 SILICON LABS 8051 58 59 oron ogod m a gt Pre scaled Clock 0 SYSCLK 1 Interrupt TRO I m I I I zd Crossbar I I I I l I
64. f performing a master transmit operation load the data bytes to transmit into the data buffer LINODT 1 to LINODTS 5 Set the STREQ bit LINOCTRL O to start the message transfer The LIN controller will schedule the message frame and request an interrupt if the message transfer is successfully completed or if an error has occurred This code segment shows the procedure to schedule a message in a transmission operation LINOADR 0x08 Point to LINOCTRL LINODAT 0x20 Select to transmit data LINOADR OxOE Point to LINOID LINODAT 0 11 Load the ID in this example 0x11 LINOADR 0 Point to LINOSIZE LINODAT LINODAT amp OxFO 0x08 Load the size with 8 LINOADR 0x00 Point to Data buffer first byte for 0 1 lt 8 i LINODAT i 0 41 Load the buffer with A LINOADR Increment the address to the next buffer LINOADR 0x08 Point to LINOCTRL LINODAT 0 01 Start Request Rev 1 3 218 SILICON LABS 8051 58 59 The application should perform the following steps when an interrupt is requested 1 Check the DONE bit LINOST 0 and the ERROR bit LINOST 2 2 If performing a master receive operation and the transfer was successful read the received data from the data buffer 3 If the transfer was not successful check the error register to determine the kind of error Further error handling has to be done by the applic
65. gt gt 8 LINOADR 0x0C Point to the LINODIV register LINODAT unsigned char 0x138 Initialize LINODIV LINOADR 0x0B Point to the LINOSIZE register LINODAT 0x80 Initialize the checksum as Enhanced LINOADR 0x08 Point to LINOCTRL register LINODAT 0 0 Reset any error and the interrupt Table 21 2 includes the configuration values required for the typical system clocks and baud rates Rev 1 3 216 SILICON LABS 8051 58 59 Table 21 2 Manual Baud Rate Parameters Examples Baud bits sec 20K 19 2 9 6 4 8 1 SYSCLK g 2s 1 G 5 gt 5 gt 5 gt 5 gt 5 gt 2 amp 5 S l 25 0 1 312 0 1 325 1 1 325 3 1 325 19 1 312 24 5 0 1 306 0 1 319 1 1 319 3 1 319 19 1 306 24 0 1 300 0 1 312 1 1 312 3 1 312 19 1 300 22 1184 0 1 276 0 1 288 1 1 288 3 1 288 19 1 276 16 0 1 200 0 1 208 1 1 208 3 1 208 19 1 200 12 25 0 306 0 0 319 1 0 319 3 0 319 19 O 306 12 0 300 0 312 1 0 312 3 0 312 19 0 300 11 0592 0 0 276 0 0 288 1 0 288 3 0 288 19 0 276 8 0 0 200 0 0 208 1 0 208 3 0 208 19 O 200 21 2 4 Baud Rate Calculations Automatic Mode If the LIN controller is configured for slave mode only the prescaler and divid
66. regardless of whether the event also causes an interrupt The CPU resumes execution at the instruction following the write to SUSPEND Note When entering suspend mode firmware must be the ZTCEN bit in REFOCN SFR Definition 8 1 Rev 1 3 178 SILICON LABS 8051 58 59 SFR Definition 19 2 OSCICN Internal Oscillator Control Bit 7 6 5 4 3 2 1 0 Name IOSCEN 1 0 SUSPEND IFRDY Reserved IFCN 2 0 Type R W R W R W R R R W Reset 1 1 0 1 0 0 0 0 SFR Address 0xA1 SFR Page OxOF Bit Name Function 7 6 IOSCEN 1 0 Internal Oscillator Enable Bits 00 Oscillator Disabled 01 Reserved 10 Reserved 11 Oscillator enabled in normal mode and disabled in suspend mode SUSPEND Internal Oscillator Suspend Enable Bit Setting this bit to logic 1 places the internal oscillator SUSPEND mode The inter nal oscillator resumes operation when one of the SUSPEND mode awakening events occurs Before entering suspend mode firmware must set the ZTCEN bit in REFOCN IFRDY Internal Oscillator Frequency Ready Flag Note This flag may not accurately reflect the state of the oscillator Firmware should not use this flag to determine if the oscillator is running 0 Internal oscillator is not running at programmed frequency 1 Internal oscillator is running at programmed frequency Reserved Read 0b Must Write Ob 2 0 IFCN 2 0
67. 0 LINODIV DIVLSB 7 0 LINOMUL 1 0 LINMUL 4 0 DIV9 LINOID OxOE ID5 104 103 102 101 IDO Note These registers are used in both master and slave mode The register bits marked with m are accessible only in Master mode while the register bits marked with s are accessible only in slave mode All other registers are accessible in both modes 223 Rev 1 3 SILICON LABS 8051 58 59 LIN Register Definition 21 4 LINODTn LINO Data Byte Bit 7 6 5 4 3 2 1 0 Name DATAn 7 0 Reset 0 0 0 0 0 0 0 0 Indirect Address LINODT1 0x00 LINODT2 0x01 LINODT3 0x02 LINODT4 0x03 LINODT5 0x04 LINODT6 0x05 LINODT7 0x06 LINODT8 0x07 Bit Name Function 7 0 DATAn 7 0 LIN Data Byte n Serial Data Byte that is received or transmitted across the LIN interface SILICON LABS Rev 1 3 224 8051 58 59 LIN Register Definition 21 5 LINOCTRL LINO Control Register Bit 7 6 5 4 3 2 1 0 STOP SLEEP TXRX DTACK RSTINT RSTERR WUPREQ STREQ Type R W R W R W W W R W R W Reset 0 0 0 0 0 0 0 0 Indirect Address 0x08 Bit Name Function 7 STOP Stop Communication Processing Bit slave mode only This bit always reads as 0 0 No effe
68. 0 10 e 0 50 BSC ddd 0 05 E 7 00 BSC eee 0 08 Notes 1 All dimensions shown in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MO 220 variation VKKD 4 except for features D2 and L which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Rev 1 3 34 SILICON LABS 8051 58 59 lal no80000060601 Figure 4 4 QFN 48 Landing Diagram Table 4 4 QFN 48 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 6 80 6 90 X2 4 00 4 10 C2 6 80 6 90 Yi 0 75 0 85 e 0 50 BSC Y2 4 00 4 10 X1 0 20 0 30 Notes General 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimension and Tolerancing is per the ANSI Y14 5M 1994 specification 3 This Land Pattern Design is based on the IPC SM 7351 guidelines 4 All dimensions shown are at Maximum Material Condition MMC Least Material Condition LMC is calculated based on a Fabrication Allowance of 0 05 mm Solder Mask Design 5 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 um minimum all the way around the pad Stencil Design 6 Astainless steel laser cut and electro polished stencil with trapezoidal walls
69. 0xB1 SFR Page 0x00 Function 7 0 2 7 0 Port 2 Match Value Match comparison value used on Port 2 for bits in which are set to 1 0 P2 n pin logic value is compared with logic LOW 1 P2 n pin logic value is compared with logic HIGH SILICON LABS Rev 1 3 202 8051 58 59 SFR Definition 20 11 PSMASK Port 3 Mask Register Bit 7 6 5 4 3 2 1 0 PSMASK 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address OxAF SFR Page 0x00 Bit Name Function 7 0 PSMASK 7 0 Port 1 Mask Value Selects P3 pins to be compared to the corresponding bits in PSMAT 0 P3 n pin logic value is ignored and cannot cause a Port Mismatch event 1 pin logic value is compared to Note P3 1 P3 6 are only available on the 48 pin and 40 pin packages SFR Definition 20 12 P3MAT Port 3 Match Register Bit 7 6 5 4 3 2 1 0 Name P3MATT 7 0 Type R W Reset 1 1 1 1 1 1 1 1 SFR Address OxAE SFR Page 0x00 Bit Name Function 7 0 7 0 Port Match Value Match comparison value used on Port 3 for bits in PSMAT which are set to 1 0 pin logic value is compared with logic LOW 1 P3 n pin logic value is compared with logic HIGH Note P3 1 P3 6 are only available on the 48 pin and 40 pin packages
70. 1 P4 7 only available on the 48 pin available on the 48 and 40 pin packages pin packages 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 4 2 39 4 5 6 7 0 1 2 3 4 5 6 7 y pinned out in 4 wi 01100100 00000000 POSKIP 0 7 P1SKIP 0 7 00000000100000000 P3SKIP 0 7 P2SKIP 0 7 Figure 20 4 Crossbar Priority Decoder in Example Configuration SILICON LABS Rev 1 3 UARTO pin assignments are fixed for bootloading purposes UART TXO is always assigned to P0 4 UART is always assigned to P0 5 CANO pin assignments are fixed to P0 6 for CAN TX and 7 for CAN Standard Port I Os appear contiguously after the prioritized functions have been assigned Important Note The SPI can be operated in either 3 wire or 4 wire modes pending the state of the NSS MD1 NSSMDO bits in register SPIOCN According to the SPI mode the NSS signal may or may not be routed to a Port pin As an example configuration if CANO SPIO in 4 wire mode and PCAO Modules 0 1 and 2 6 and 7 are enabled on the crossbar with P0 1 P0 2 and P0 5 skipped the registers should be set as follows XBRO 0x06 CANO and SPIO enabled XBR1 0 0 PCAO modules 0 1 and 2 enabled XBR2 0x40 Cross bar enabled XBR3 0x02 PCA1 modules 6 and 7 and
71. 12 1 External Clock 8 0 XTAL1 E 1 TMRnL TMRnH Tn Crossbar gt n THn TRn LN f EXENn gt M M EXFn gt Interrupt v gt TMRnCAPL TMRnCAPH Crossbar I x Figure 27 10 Timer 4 and 5 Capture Mode Block Diagram 27 4 3 Auto Reload Mode In Auto Reload mode the counter timer can be configured to count up or down and cause an interrupt flag to occur upon an overflow underflow event When counting up the counter timer will set its overflow under flow flag TFn and cause an interrupt if enabled upon overflow underflow and the values in the Reload Capture Registers TMRnCAPH and TMRnCAPL are loaded into the timer and the timer is restarted When the Timer External Enable Bit EXENn bit is set to 1 and the Decrement Enable Bit DCENn is 0 a falling edge 1 0 transition on the TnEX pin will cause a timer reload Note that timer overflows will also cause auto reloads When DCENn is set to 1 the state of the TnEX pin controls whether the counter timer counts up increments or down decrements and will not cause an auto reload or interrupt event See Section 27 4 1 for information concerning configuration of a timer to count down When counting down the counter timer will set its overflow underflow flag TFn and cause an interrupt if enabled when the value in the TMRnH and TMRnL registers matches the 16 bit value i
72. 197 XBR2 0 7 Port Crossbar Control 2 198 XBR3 0xC6 Port Crossbar Control 3 199 Note The CAN registers are not explicitly defined in this datasheet See Table 22 2 on page 236 for the list of all available CAN registers 125 Rev 1 3 SILICON LABS 8051 58 59 14 Interrupts The C8051F58x F59x devices include an extended interrupt system supporting a total of 23 interrupt sources with two priority levels The allocation of interrupt sources between on chip peripherals and exter nal inputs pins varies according to the specific version of the device Each interrupt source has one or more associated interrupt pending flag s located in an SFR When a peripheral or external source meets a valid interrupt condition the associated interrupt pending flag is set to logic 1 If interrupts are enabled for the source an interrupt request is generated when the interrupt pending flag is set As soon as execution of the current instruction is complete the CPU generates an LCALL to a prede termined address to begin execution of an interrupt service routine ISR Each ISR must end with an instruction which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred If interrupts are not enabled the interrupt pending flag is ignored by the hardware and program execution continues as normal The interrupt pending flag is set to logic 1 regard
73. 2 0 XFCN 2 0 External Oscillator Frequency Control Bits Set according to the desired frequency for Crystal or RC mode Set according to the desired K Factor for C mode XFCN Crystal Mode RC Mode C Mode 000 f lt 32 kHz lt 25 kHz K Factor 0 87 001 32 kHz lt f lt 84 kHz 25 kHz f lt 50 kHz Factor 2 6 010 84 kHz lt 1 lt 225 kHz 50kHz lt f lt 100 kHz Factor 7 7 011 225 kHz f lt 590 kHz 100 kHz f 200 kHz Factor 22 100 590 kHz lt f lt 1 5 MHz 200 kHz f lt 400 kHz Factor 65 101 1 5 MHz f 4 MHz 400 kHz f 800 kHz Factor 180 110 4 MHz lt f lt 10 MHz 800 kHz f lt 1 6 MHz Factor 664 111 10 MHz lt lt 30 MHz 1 6 MHz lt f lt 3 2 MHz Factor 1590 184 Rev 1 3 SILICON LABS 8051 58 59 19 4 1 External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 19 1 Option 1 The External Oscillator Frequency Control value XFCN should be chosen from the Crystal column of the table in SFR Definition 19 6 OSCXCN register For example an 11 0592 MHz crystal requires an XFCN setting of 111b and a 32 768 kHz Watch Crystal requires an XFCN setting of 001b After an external 32 768 kHz oscillator is stabilized the XFCN setting can be switched to 000 to save power It is recommended to enable the missing clock detector before switching the system clock to
74. 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF1 PCAO Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF1 interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCFO PCAO Module 0 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCFO interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software 327 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 28 2 Mode SILICON LABS Bit 7 6 5 4 3 2 1 0 Name CIDL WDTE WDLCK CPS2 CPS1 CPSO ECF Type R W R W R W R R W R W R W R W Reset 0 1 0 0 0 0 0 0 SFR Address 0xD9 SFR Page 0x00 Bit Name Function 7 CIDL PCAO Counier Timer Idle Control Specifies PCAO behavior when CPU is in Idle Mode 0 PCAO continues to function normally while the system controller is in Idle Mode
75. 25 OxFF OxFO 0 4095 0 1 0 OxFF OxFO 1 4096 64 1 016 For any desired gain value the GAIN registers can be calculated by the following GAIN gain GAINADD x x 4096 Equation 6 3 Calculating the ADCOGNH and ADCOGNL Values from the Desired Gain Where GAIN is the 12 bit word of ADCOGNH 7 0 and ADCOGNL 7 4 GAINADD is the value of the GAINADD bit ADCOGNA 0 gain is the equivalent gain value from 0 to 1 016 When calculating the value of GAIN to load into the ADCOGNH and ADCOGNL registers the GAINADD bit can be turned on or off to reach a value closer to the desired gain value For example the initial example in this section requires a gain of 0 44 to convert 5 V full scale to 2 2 V full scale Using Equation 6 3 GAIN 0 44 _ GAINADD x x 4096 If GAINADD is set to 1 this makes the equation GAIN 044 1 x 4 x 4096 0 424 x 4096 1738 0x06CA The actual gain from setting GAINADD to 1 and ADCOGNH and ADCOGNL to Ox6CA is 0 4399 A similar gain can be achieved if GAINADD is set to 0 with a different value for ADCOGNH and ADCOGNL 61 Rev 1 3 SILICON LABS 8051 58 59 6 3 2 Setting the Gain Value The three programmable gain registers are accessed indirectly using the ADCOH and ADCOL registers when the GAINEN bit ADCOCF 0 bit is set ADCOH acts as the address register and ADCOL is the data register The programmable gain registers can only be written to and cann
76. 25 MHz Analog Supply Voltage VDDA System Clock lt 25 MHz Must be connected to Vpp System Clock gt 25 MHz Digital Supply RAM Data Retention Voltage Port Supply Voltage Vig Normal Operation SYSCLK System Clock SYSCLK High Time Tsys SYSCLK Low Time Specified Operating 125 Temperature Range Digital Supply Current CPU Active Normal Mode fetching instructions from Flash 4 Vpp 2 1 V F 200 kHz 150 Vpp 2 1 V 1 5 MHz 650 Vpp 2 1 V 25 MHz 8 5 Vpp 2 1 V F 50 MHz 15 Given in Table 5 4 on page 48 Vio should not be lower than the Vpp voltage SYSCLK must be at least 32 kHz to enable debugging Based on device characterization data Not production tested Does not include oscillator supply current IDD can be estimated for frequencies 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Ipp for gt 15 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V F 20 MHz Ipp 21 mA 50 MHz 20 MHz 0 46 mA MHz 7 2 mA Idle IDD can be estimated for frequencies lt 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Id
77. 28 4 Watchdog Timer Mode on page 324 the WDT is enabled and clocked by SYSCLK 12 following any reset If a system malfunction prevents user software from updating the WDT a reset is generated and the WDTRSF bit RSTSRC 5 is set to 1 The state of the RST pin is unaffected by this reset 17 7 Flash Error Reset If a Flash read write erase or program read targets an illegal address a system reset is generated This may occur due to any of the following m A Flash write or erase is attempted above user code space This occurs when PSWE is set to 1 and a MOVX write operation targets an address above address OxFBFF in Bank on C8051F580 1 2 3 8 9 or any address in Bank 3 on C8051F584 5 6 7 F590 1 devices m read is attempted above user code space This occurs when a MOVC operation targets an address above address OxFBFF in Bank 3 on C8051F580 1 2 3 8 9 or any address in Bank 3 on C8051F584 5 6 7 F590 1 devices m A Program read is attempted above user code space This occurs when user code attempts to branch to an address above OxFBFF in Bank 3 on C8051F580 1 2 3 8 9 or any address in Bank 3 on C8051F584 5 6 7 F590 1 devices m A Flash read write or erase attempt is restricted due to a Flash security setting see Section 15 3 Security Options on page 141 m A Flash read write or erase is attempted when the VDD Monitor is not enabled to the high threshold and set as a reset source The FERROR bit RSTSRC 96 is set
78. 2x6 Priority v T channel M Crossbar P1 0 X PCA WDT Decoder P1 1 P1 2 Voltage Regulator LIN2 1 Port 1 P13 LDO 2 0B gt Drivers 1 4 SPI 1 5 EUM P1 6 GND I P1 7 SFR Crossbar Control P2 0 Bus P2 1 System Clock Setup External Memory Interface p22 XTAL1 XTAL2 On F588 F590 devices Port 2 P2 3 Drivers P2 4 Internal Oscillator External Oscillator P2 5 Analog Peripherals P2 6 Y Y P2 7 Clock Multiplier Voltage P3 0 Reference VREF P3 1 P3 2 Port 3 P3 3 6 VDD Drivers P3 4 lt VREF P3 5 lt P3 6 Temp P3 7 Sensor GND Port4 gt P4 0 C2D CPO CPOA q Driver Comparator 0 CP1 1 4 VDDA X 1 2 2 q Comparator 2 Figure 1 2 C8051F588 9 F590 1 Block Diagram Rev 1 3 20 SILICON LABS 8051 58 59 E VIO ii On CIP 51 8051 Port Configuration ntroller Cor Controller Core Digital Peripherals 128 or 96 kB Flash UARTO CoCK AST x Debug Program Memory Port 0 Drivers Programming m gt Hardware 256 Byte RAM Timers 0 1 2 3 4 5 C2D 8 XRAM 2 6 Priority v I channel Crossbar PCA WDT Decoder VREGIN X Voltage Regulator LIN 2 1 P
79. 3 Special Function Registers SFRs are listed in alphabetical order All undefined SFR locations are reserved SILICON LABS Register Address Description Page ACC OxEO Accumulator 99 ADCOCF OxBC ADCO Configuration 65 ADCOCN OxE8 ADCO Control 67 ADCOGTH 0 4 ADCO Greater Than Compare High 69 ADCOGTL 0xC3 ADCO Greater Than Compare Low 69 ADCOH OxBE ADCO High 66 ADCOL OxBD ADCO Low 66 ADCOLTH 0xC6 ADCO Less Than Compare Word High 70 ADCOLTL 0xC5 ADCO Less Than Compare Word Low 70 ADCOMX OxBB ADCO Mux Configuration 73 ADCOTK OxBA ADCO Tracking Mode Select 68 B OxFO B Register 99 CCHOCN OxE3 Cache Control 148 CKCON Ox8E Clock Control 286 CLKMUL 0x97 Clock Multiplier 182 CLKSEL Ox8F Clock Select 177 CPTOCN Ox9A ComparatorO Control 79 CPTOMD 0x9B Comparator0 Mode Selection 80 CPTOMX 0x9C Comparator0 MUX Selection 86 CPT1CN 0 9 Comparator1 Control 79 CPT1MD Ox9E Comparator1 Mode Selection 80 CPT1MX Ox9F Comparator1 MUX Selection 86 CPT2CN Ox9A Comparator2 Control 83 CPT2MD 0x9B Comparator2 Mode Selection 84 CPT2MX 0x9C Comparator2 MUX Selection 88 DPH 0x83 Data Pointer High 98 DPL 0x82 Data Pointer Low 98 EIE1 OxE6 Extended Interrupt Enable 1 132 EIE2 OxE7 Extended Interrupt Enable 2 132 EIP1 OxF6 Extended Interrupt Priority 1 133 EIP2 OxF7 Extended Interrupt Priority 2 134 EMIOCF 0 2 External Memory Interface Configuration 163 EMIO
80. 3 1 Data Transmission MEET c 257 24 3 2 Receptori psu EE E aeu 257 24 3 3 Multiprocessor 258 ui 263 25 1 Enhanced Baud Rate 264 25 2 Operational Modes 265 6 Rev 1 3 SILICON LABS 8051 58 59 25 2 1 8 Bit UART 265 25 2 2 9 Bit VART E 265 25 3 Multiprocessor Communications eere She antera x xay Yu xen cte ioa 266 26 Enhanced Serial Peripheral Interface SPIO 270 26 1 e cu 271 26 1 1 Master Out Slave In 2 271 26 1 2 Master In Slave Out MISO 271 26 1 3 Serial Clock SCK E 271 26 1 4 Slave Select NSS 271 26 2 SPIO Master Mode Operation 272 26 3 SPIO Slave Mode 4 000000 274 26 4 SPIO Interrupt 4 4 rr 274 26 5 Serial Clock Phase and 275 26 6 SPI Special Function Registers
81. 4 3 2 1 0 Name C2AD D 7 0 Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 C2ADD 7 0 C2 Address The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands Address Description 0x00 Selects the Device ID register for Data Read instructions 0x01 Selects the Revision ID register for Data Read instructions 0x02 Selects the C2 Flash Programming Control register for Data Read Write instructions 0 4 Selects the C2 Flash Programming Data register for Data Read Write instructions Rev 1 3 351 SILICON LABS 8051 58 59 C2 Register Definition 30 2 DEVICEID C2 Device ID Bit 7 6 5 4 3 2 1 0 Name DEVICEID 7 0 Reset 0 0 1 0 0 0 0 0 C2 Address OxFD SFR Address OxFD SFR Page Ox0F Bit Name Function 7 0 DEVICEID 7 0 Device ID This read only register returns the 8 bit device ID 0x20 C8051 F58x F59x C2 Register Definition 30 3 REVID C2 Revision ID Bit 7 6 5 4 3 2 1 0 Name REVID 7 0 Type R W Reset Varies Varies Varies Varies Varies Varies Varies Varies C2 Address OxFE SFR Address OxFE SFR Page Ox0F Bit Name Function 7 0 REVID 7 0 Revision ID This read only register returns the 8 bit revision ID For example 0x00 R
82. 51 Instruction Set 50 MIPS Peak Throughput with 50 MHz Clock 0 to 50 MHz Clock Frequency Extended Interrupt Handler Reset Input Power Management Modes On chip Debug Logic Program and Data Memory Security 11 1 Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with no instructions taking more than eight system clock cycles Rev 1 3 91 SILICON LABS 8051 58 59 DATA BUS 2 8 a 8 ACCUMULATOR B REGISTER STACK POINTER m TMP1 TMP2 x lt 5 PSW ADDRESS gt SRAM ALU REGISTER i 5 8 05 SFR_ADDRESS BUFFER D SFR_CONTROL BUS DATA POINTER com ce DATA SFR_READ DATA PC INCREMENTER MEM_ADDRESS PROGRAM COUNTER PC av 1 LL MEM CONTROL _ MEMORY PRGM ADDRESS REG Hc MEM WRITE DATA a F MEM READ DATA PIPELINE RESET
83. 9 00 BSC A1 0 05 0 15 1 7 00 5 2 1 5 1 40 1 45 L 0 45 0 60 0 75 b 0 30 0 37 0 45 aaa 0 20 0 09 0 20 bbb 0 20 D 9 00 BSC ccc 0 10 D1 7 00 BSC ddd 0 20 e 0 80 BSC 0 3 5 79 Notes 1 All dimensions shown in millimeters mm unless otherwise noted 2 Dimensioning Tolerancing per ANSI 14 5 1994 3 This drawing conforms to the JEDEC outline MS 026 variation BBA 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Rev 1 3 38 8051 58 59 Figure 4 8 QFP 32 Package Drawing _ noni Table 4 8 QFP 32 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 8 40 8 50 X1 0 40 0 50 C2 8 40 8 50 Y1 1 25 1 35 0 80 BSC Notes General 1 All dimensions shown are in millimeters mm unless otherwise noted 2 This Land Pattern Design is based on the IPC 7351 guidelines Solder Mask Design 3 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60um minimum all the way around the pad Stencil Design 4 Astainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125mm 5 mils 6 The ratio of stencil aperture to land pad size should be 1 1 for all peri
84. 9th and most significant bit is the DIV9 bit LINOMUL O The valid range for the divider is 200 to 511 LIN Register Definition 21 10 LINOMUL LINO Multiplier Register Bit 7 6 5 4 3 2 1 0 Name PRESCL 1 0 LINMUL 4 0 DIV9 Type R W R W R W Reset 1 1 1 1 1 1 1 1 Indirect Address 0 00 Bit Name Function 7 6 PRESCL 1 0 LIN Baud Rate Prescaler Bits These bits are the baud rate prescaler bits 5 1 LINMUL 4 0 LIN Baud Rate Multiplier Bits These bits are the baud rate multiplier bits These bits are not used in slave mode 0 DIV9 LIN Baud Rate Divider Most Significant Bit The most significant bit of the baud rate divider The 8 least significant bits are in LINODIV The valid range for the divider is 200 to 511 229 Rev 1 3 SILICON LABS 8051 58 59 LIN Register Definition 21 11 LINOID LINO Identifier Register These bits form the data identifier Bit 7 6 4 3 Name ID 5 0 Reset 0 0 0 0 Indirect Address Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 0 ID 5 0 LIN Identifier Bits If the LINSIZE bits LINOSIZE 3 0 are 1111b bits ID 5 4 are used to determine the data size and are interpreted as follows 00 2 bytes 01 2 bytes 10 4 bytes 11 8 bytes SILICON LABS Rev 1 3 230 8
85. ACK from the master at the end of each byte At the end of the data transfer the master generates a STOP condition to terminate the transaction and free the bus Figure 23 3 illustrates a typical SMBus transaction 111 SDA SLA6 SLA5 0 i R W D7 y D6 0 START Slave Address R W ACK Data Byte NACK STOP Figure 23 3 SMBus Transaction 23 3 1 Transmitter Vs Receiver On the SMBus communications interface a device is the transmitter when it is sending an address or data byte to another device on the bus A device is a receiver when an address or data byte is being sent to it from another device on the bus The transmitter controls the SDA line during the address or data byte After each byte of address or data information is sent by the transmitter the receiver sends an ACK or NACK bit during the ACK phase of the transfer during which time the receiver controls the SDA line 23 3 2 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see Section 23 3 5 SCL High SMBus Free Timeout on page 242 In the event that two or more devices attempt to begin a transfer at the same time an arbitra tion scheme is employed to force one master to give up the bus The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is o
86. CONTROL LOGIC aok SYSTEM_IRQs INTERRUPT pg N INTERFACE EMULATION IRQ STOP a ATON PS POWER CONTROL Ld IDLE REGISTER ma LJ Figure 11 1 CIP 51 Block Diagram With the CIP 51 s maximum system clock at 50 MHz it has a peak throughput of 50 MIPS The CIP 51 has a total of 109 instructions The table below shows the total number of instructions that require each execu tion time Clocks to Execute 1 2 2 3 3 3 4 4 4 5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 Programming and Debugging Support In system programming of the Flash program memory and communication with on chip debug support logic is accomplished via the Silicon Labs 2 Wire Development Interface C2 The on chip debug support logic facilitates full speed in circuit debugging allowing the setting of hardware breakpoints starting stopping and single stepping through program execution including interrupt service routines examination of the program s call stack and reading writing the contents of registers and mem ory This method of on chip debugging is completely non intrusive requiring no RAM Stack timers or other on chip resources C2 details can be found in C2 Interface on page 351 The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE including editor debugger and programmer The IDE s debug
87. Cycle Using Equation 29 2 the largest duty cycle is 10096 PCA1CPHn 0 and the smallest duty cycle is 0 39 PCA1CPHn OxFF A 0 duty cycle may be generated by clearing the ECOM1n bit to 0 Duty Cycle Rev 1 3 341 SILICON LABS 8051 58 59 Write to PCA1CPLn Reset PCA1CPHn Write to PCA1CPHn 1 COVF1 VES PCA1PWM CA1CPMn P E C C M T P E MZ LIL SJS MOJP P T 1 MIPINIn 1 4 E PCA1CPLn LIL 611 111 1 1 1 11 1 n n n n 1 0 n 0 0 Ax 00 9 0x0 x SZ Enable 8 bit S SET Q L Comparator gt R as PCA1 Timebase b PCA1L Overflow Figure 29 8 PCA1 8 Bit PWM Mode Diagram 342 Rev 1 3 SILICON LABS 8051 58 59 29 3 5 2 9 10 11 bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9 10 11 bit PWM mode should be varied by writing to an Auto Reload Register which is dual mapped into the PCA1CPHn and PCA1CPL n register locations The data written to define the duty cycle should be right justified in the registers The auto reload registers are accessed read or written when the bit ARSEL1 in PCA1PWM is set to 1 The capture compare registers are accessed when ARSEL1 is set to 0 When the least significant N bits of the PCA1 counter match the value
88. Definition 20 14 for the PnMDIN register details The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this is the SMBus SDA SCL pins which are configured as open drain regardless of the PnMDOUT settings When the WEAKPUD bit in XBR2 is 0 a weak pullup is enabled for all Port I O config ured as open drain WEAKPUD does not affect the push pull Port Furthermore the weak pullup is turned off on an output that is driving a to avoid unnecessary power dissipation Registers XBRO XBR1 XBR2 an XBR3 must be loaded with the appropriate values to select the digital I O functions required by the design Setting the bit in XBR2 to 1 enables the Crossbar Until the Crossbar is enabled the external pins remain as standard Port in input mode regardless of the XBRn Register settings For given XBRn Register settings one can determine the pin out using the Priority Decode Table as an alternative the Configuration Wizard utility of the Silicon Labs IDE software will deter mine the Port I O pin assignments based on the XBRn Register settings The Crossbar must be enabled to use Port pins as standard Port I O in output mode Port output drivers are disabled whi
89. Diagram 000 256 Figure 24 2 UARTO Timing Without Parity or Extra Bit 258 Figure 24 3 UARTO Timing With Parity 2 441222 2 2 258 Figure 24 4 Timing With Extra Bit 258 Figure 24 5 Typical UART Interconnect Diagram 259 Figure 24 6 UART Multi Processor Mode Interconnect Diagram 260 Figure 26 1 SPI Block Diagram 40 0 04 4 272 Figure 26 2 Multiple Master Mode Connection Diagram 275 Figure 26 3 3 Wire Single Master and 3 Wire Single Slave Mode Connection Diagram 275 Figure 26 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram 275 Figure 26 5 Master Mode Data Clock 0 277 Figure 26 6 Slave Mode Data Clock Timing CKPHA 0 278 Figure 26 7 Slave Mode Data Clock Timing CKPHA 1 278 Figure 26 8 SPI Master Timing 0 282 Figure 26 9 SPI Master Timing CKPHA 1 282 Figure 26 10 SPI Slave Timing CKPHA 0 283 Figure 26 11 SPI Slave Timing CKPHA 1 283 Fig
90. Flag Key Equal to one period of FCLK Each Sn is equal to one period of the SAR clock Figure 6 3 12 Bit ADC Tracking Mode Example 6 1 4 Burst Mode Burst Mode is a power saving feature that allows ADCO to remain in a very low power state between con versions When Burst Mode is enabled ADCO wakes from a very low power state accumulates 1 4 8 or 16 samples using an internal Burst Mode clock approximately 25 MHz then re enters a very low power state Since the Burst Mode clock is independent of the system clock ADCO can perform multiple conver sions then enter a very low power state within a single system clock cycle even if the system clock is slow e g 32 768 kHz or suspended Burst Mode is enabled by setting BURSTEN to logic 1 When in Burst Mode ADOEN controls the ADCO idle power state i e the state ADCO enters when not tracking or performing conversions If ADOEN is set to logic 0 ADCO is powered down after each burst If ADOEN is set to logic 1 ADCO remains enabled after each burst On each convert start signal ADCO is awakened from its Idle Power State If ADCO is powered down it will automatically power up and wait the programmable Power Up Time controlled by the ADOPWR bits Otherwise ADCO will start tracking and converting immediately Figure 6 4 shows an exam ple of Burst Mode Operation with a slow system clock and a repeat count of 4 Important Note When Burst Mode is enabled only Post Tracking and
91. Function 7 0 SBRLLO 7 0 Low Byte of Reload Value for UARTO Baud Rate Generator This value is loaded into the low byte of the UARTO baud rate generator when the counter overflows from OxFFFF to 0x0000 SILICON LABS Rev 1 3 264 8051 58 59 25 UART1 UART1 is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates details in Section 25 1 Enhanced Baud Rate Generation on page 266 Received data buffering allows UART1 to start reception of a second incoming data byte before software has finished reading the previous data byte UART1 has two associated SFRs Serial Control Register 1 SCON1 and Serial Data Buffer 1 SBUF1 The single SBUF1 location provides access to both transmit and receive registers Writes to SBUF1 always access the Transmit register Reads of SBUF1 always access the buffered Receive register it is not possible to read data from the Transmit register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed is set in SCON 1 or a data byte has been received is set SCON1 The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UART1 interrupt transmit com
92. Given in Table 5 4 on page 48 should not be lower than the Vpp voltage SYSCLK must be at least 32 kHz to enable debugging Based on device characterization data Not production tested Does not include oscillator supply current IDD can be estimated for frequencies 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Ipp for gt 15 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V F 20 MHz Ipp 21 mA 50 MHz 20 MHz 0 46 2 7 2 mA Idle IDD can be estimated for frequencies lt 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Idle Ipp for gt 1 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V F 5 MHz Idle Ipp 19 mA 50 MHz 5 MHz x 0 38 mA MHz 1 9 mA 45 Rev 1 3 SILICON LABS 8051 58 59 4 h Threshold D 1 Unsafe VDD Monitor Threshold Internal VDD Monitor H D D 4 4 4 4 4 D 4 4 a
93. In 8 bit mode TMR2L contains the 8 bit low byte timer value SFR Definition 27 12 TMR2H Timer 2 High Byte Bit 7 6 5 4 3 1 0 Type R W Reset 0 0 0 0 0 0 0 SFR Address OxCD SFR Page 0x00 Bit Name Function 7 0 TMR2H 7 0 Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value 300 Rev 1 3 SILICON LABS 8051 58 59 27 3 Timer 3 Timer 3 is a 16 bit timer formed by two 8 bit SFRs TMR3L low byte and TMR3H high byte Timer 3 may operate in 16 bit auto reload mode or split 8 bit auto reload mode The T3SPLIT bit TMR3CN 3 defines the Timer 3 operation mode Timer 3 may be clocked by the system clock the system clock divided by 12 or the external oscillator source divided by 8 The external clock mode is ideal for real time clock RTC functionality where the internal oscillator drives the system clock while Timer 3 and or the PCA is clocked by an external preci sion oscillator Note that the external oscillator source divided by 8 is synchronized with the system clock 27 3 1 16 bit Timer with Auto Reload When T3SPLIT 3 is zero Timer operates as a 16 bit timer with auto reload Timer can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the
94. In Burst Mode a single convert start can initiate multiple self timed conversions Results in both modes are accumulated in the ADCOH ADCOL register When ADORPT1 0 set to a value other than 00 the ADOLJST bit in the ADCOCN register must be set to 0 right justified 00 1 conversion is performed 01 4 conversions are performed and accumulated 10 8 conversions are performed and accumulated 11 16 conversions are performed and accumulated 0 GAINEN Gain Enable Bit Controls the gain programming Refer to Section 6 3 Selectable Gain on page 60 for information about using this bit 65 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 6 5 ADCO Data Word MSB Bit 7 6 5 4 3 2 1 0 Name ADCOH 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address OxBE SFR Page 0x00 Bit Name Function 7 0 ADCOH 7 0 ADCO Data Word High Order Bits For ADOLJST 0 and ADORPT as follows 00 Bits 3 0 are the upper 4 bits of the 12 bit result Bits 7 4 are 0000b 01 Bits 4 0 are the upper 5 bits of the 14 bit result Bits 7 5 are 000b 10 Bits 5 0 are the upper 6 bits of the 15 bit result Bits 7 6 are 00b 11 Bits 7 0 are the upper 8 bits of the 16 bit result For ADOLJST 1 ADORPT must be 00 Bits 7 0 are the most significant bits of the ADCO 12 bit result SFR Definition 6 6 ADCOL A
95. LABS 8051 58 59 SFR Definition 15 4 Cache Control Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved CHPFEN Reserved Reserved Reserved Reserved CHBLKW Type R W R W R W R W R W R W R W R W Reset 0 0 1 0 0 0 0 0 SFR Address OxE3 SFR Ox0F Bit Name Function 7 6 Reserved Must Write 00b 5 CHPFEN Cache Prefect Enable Bit 0 Prefetch engine is disabled 1 Prefetch engine is enabled 4 1 Reserved Must Write 00000 0 CHBLKW Block Write Enable Bit This bit allows block writes to Flash memory from firmware 0 Each byte of a software Flash write is written individually 1 Flash bytes are written in groups of two SFR Definition 15 5 ONESHOT Flash Oneshot Period Bit 7 6 5 4 3 2 1 0 Name PERIOD 3 0 Type R R R R R W R W R W R W Reset 0 0 0 0 1 1 1 1 SFR Address OxBE SFR Page 0x0F Bit Name Function 7 4 Unused Read 0000b Write don t care 3 0 PERIOD 3 0 Oneshot Period Control Bits These bits limit the internal Flash read strobe width as follows When the Flash read strobe is de asserted the Flash memory enters a low power state for the remainder of the system clock cycle These bits have no effect when the system clocks is greater than 12 5 MHz and FLRT 0 FLASH pmax 515 PERIOD x 5ns Rev 1 3 148 SILICON LA
96. MATn bit is set to 1 the CCFn flag for the channel will be set when the 16 bit PCAO counter and the 16 bit capture compare register for the channel are equal Rev 1 3 320 SILICON LABS 8051 58 59 Write to PCAOCPLn 0 Reset Write to PCAOCPHn PCAOCPLn 8 bit Adder PCAOCPHn PCAO Timebase p PCA0L Figure 28 7 PCA0 Frequency Output Mode 28 3 5 8 bit 9 bit 10 bit and 11 bit Pulse Width Modulator Modes Each module can be used independently to generate a pulse width modulated PWM output on its associ ated CEXn pin The frequency of the output is dependent on the timebase for the PCA0 counter timer and the setting of the PWM cycle length 8 9 10 or 11 bits For backwards compatibility with the 8 bit PWM mode available on other devices the 8 bit PWM mode operates slightly different than 9 10 and 11 bit PWM modes It is important to note that all channels configured for 8 9 10 11 bit PWM mode will use the same cycle length It is not possible to configure one channel for 8 bit PWM mode and another for 11 bit mode for example However other PCAO channels can be configured to Pin Capture High Speed Output Software Timer Frequency Output or 16 bit PWM mode independently 28 3 5 1 8 bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8 bit PWM mode is varied using the module s PCAOCPLn ca
97. Mode Select These bits affect the response time and power consumption for Comparator2 00 Mode 0 Fastest Response Time Highest Power Consumption 01 Mode 1 10 Mode 2 11 Mode 3 Slowest Response Time Lowest Power Consumption 84 Rev 1 3 SILICON LABS 8051 58 59 9 1 Comparator Multiplexer C8051F58x F59x devices include an analog input multiplexer for each of the comparators to connect Port I O pins to the comparator inputs The ComparatorO inputs are selected in the CPTOMX register SFR Defi nition 9 7 The bits select the Comparator0 positive input the CMXONS3 CMXONO bits select the ComparatorO negative input Similarly the Comparator1 inputs are selected in the CPT1MX reg ister using the CMX1P3 CMX1P0 bits and CMX1N3 CMX1NO bits and the Comparator2 inputs are selected in the CPT2MX register using the CMX2P3 CMX2P0 bits and CMX2N3 CMX2N0 bits The same pins are available to both multiplexers at the same time and can be used by all comparators simultane ously Important Note About Comparator Inputs The Port pins selected as comparator inputs should be con figured as analog inputs in their associated Port configuration register and configured to be skipped by the Crossbar for details on Port configuration see Section 20 6 Special Function Registers for Accessing and Configuring Port on page 204 CMXnN1
98. Name CP1EN CP1OUT CPIRIF 1 CP1HYPT1 0 CP1HYN 1 0 Type R W R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x9D SFR Page 0x00 Bit Name Function 7 CP1EN CP1OUT Comparator1 Enable Bit 0 Comparator1 Disabled 1 Comparator1 Enabled Comparator1 Output State Flag 0 Voltage on CP1 CP1 1 Voltage on 1 gt CP1 CP1RIF Comparator1 Rising Edge Flag Must be cleared by software 0 No Comparator1 Rising Edge has occurred since this flag was last cleared 1 Comparator1 Rising Edge has occurred CP1FIF Comparator1 Falling Edge Flag Must be cleared by software 0 No Comparator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge has occurred 3 2 CP1HYPT 1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV CP1HYN 1 0 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV SILICON LABS Rev 1 3 81 8051 58 59 SFR Definition 9 4 CPT1MD Comparator1 Mode Selection Bit 7 6 5 4 3 2 1 0 Name CP1MD 1 0 Type R R RW RW R R R W
99. Output Software Timer Frequency Output or 16 bit PWM mode independently 29 3 5 1 8 bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8 bit PWM mode is varied using the module s PCA1CPLn cap ture compare register When the value in the low byte of the PCA1 counter timer PCA1L is equal to the value in PCA1CPLn the output on the CEXn pin will be set When the count value in PCA1L overflows the CEXn output will be reset see Figure 29 8 Also when the counter timer low byte PCA1L overflows from OxFF to 0x00 PCA1CPLn is reloaded automatically with the value stored in the module s capture compare high byte PCA1CPHn without software intervention Setting the ECOM1n and PWMin bits in the PCA1CPMn register and setting the CLSEL1 bits in register PCA1PWM to 00b enables 8 Bit Pulse Width Modulator mode If the MAT1n bit is set to 1 the CCFn flag for the module will be set each time an 8 bit comparator match rising edge occurs The COVF1 flag in PCA1PWM can be used to detect the overflow falling edge which will occur every 256 PCA1 clock cycles The duty cycle for 8 Bit PWM Mode is given in Equation 29 2 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA1 Cap ture Compare registers the low byte should always be written first Writing to PCA1CPLn clears the 1 bit to 0 writing to PCA1CPHn sets ECOM1n to 1 256 256 Equation 29 2 8 Bit PWM Duty
100. Output Mode Diagram 320 Figure 28 7 PCAO Frequency Output Mode 321 Figure 28 8 8 Bit PWM Mode Diagram 322 Figure 28 9 9 10 and 11 Bit PWM Mode Diagram 323 Figure 28 10 PCAO 16 Bit PWM 324 Figure 28 11 PCAO Module 5 with Watchdog Timer Enabled 325 Figure 29 1 PCA1 Block Diagram atn tb ic RR ac 333 Figure 29 2 PCA1 Counter Timer Block Diagram 334 Figure 29 3 PCA1 Interrupt Block Diagram 335 Figure 29 4 PCA1 Capture Mode Diagram 337 Figure 29 5 PCA1 Software Timer Mode Diagram 338 Figure 29 6 PCA1 High Speed Output Mode Diagram 339 Figure 29 7 PCA1 Frequency Output Mode 2 340 Figure 29 8 PCA1 8 Bit PWM Mode Diagram 342 Figure 29 9 PCA1 9 10 and 11 Bit PWM Mode Diagram 343 Figure 29 10 PCA1 16 Bit PWM Mode 344 Figure 30 1 Typical C2 Pin 355 Rev 1 3 11 SILICO
101. Output ZN PAD Logic Value Port Latch or gt PxMDIN x 1 for digital E GND 0 for analog To From Analog pi gt lt Px x Input Logic Value 2 Reads 0 when pin is configured as an analog I O Figure 20 2 Port I O Cell Block Diagram Rev 1 3 190 SILICON LABS 8051 58 59 20 1 3 Interfacing Port I O in Multi Voltage System All Port are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5 25 V Connect the VIO pin to the voltage source of the interface logic 20 2 Assigning Port I O Pins to Analog and Digital Functions Port I O pins 0 7 can be assigned to various analog digital and external interrupt functions P4 0 P4 7 can be assigned to only digital functions The Port pins assigned to analog functions should be con figured for analog I O and Port pins assigned to digital or external interrupt functions should be configured for digital I O 20 2 1 Assigning Port I O Pins to Analog Functions Table 20 1 shows all available analog functions that require Port I O assignments Port pins selected for these analog functions should have their corresponding bit in PnSKIP set to 1 This reserves the pin for use by the analog function and does not allow it to be claimed by the Crossbar Table 20 1 shows the potential mapping of Port to each analog function Table 20 1 Port Assignment for Analog Funct
102. R R Reset Varies Varies 0 0 0 0 0 0 SFR Address OxFF SFR Page 0x00 Bit Name Function 7 VDMEN Vpp Monitor Enable This bit turns the Vpp monitor circuit on off The Vpp Monitor cannot generate sys tem resets until it is also selected as a reset source in register RSTSRC SFR Defi nition 17 2 Selecting the Vpp monitor as a reset source before it has stabilized may generate a system reset 0 Vpp Monitor Disabled 1 Vpp Monitor Enabled 6 VDDSTAT Vpp Status This bit indicates the current power supply status Vpp Monitor output 0 Vpp is at or below the Vpp monitor threshold 1 Vpp is above the Vpp monitor threshold 5 VDMLVL Vpp Monitor Level Select 0 Vpp Monitor Threshold is set to VRST LOW 1 Vpp Monitor Threshold is set to VRST HIGH This setting is required for any sys tem includes code that writes to and or erases Flash 4 0 Unused Read 00000b Write Don t care 17 3 External Reset The external RST pin provides a means for external circuitry to force the device into a reset state Assert ing an active low signal on the RST pin generates a reset an external pullup and or decoupling of the RST pin may be necessary to avoid erroneous noise induced resets See Table 5 4 for complete RST pin spec ifications The PINRSF flag RSTSRC 0 is set on exit from an external reset 17 4 Missing Clock Detector Reset The Missing Clock Detector MCD is a
103. Rat dose 62 6 4 Programmable Window Detector 68 6 4 1 Window Detector In Single Ended 70 6 5 ADCO Analog Multiplexer np dap 72 7 Temperature Sensor uiae uii nada cs ead 74 B Voltage d ED On or EOD 75 S GOmparalorS Lie 77 9 1 Comparator 444420448 85 10 Voltage Regulator REG0 u u T T 89 11 CIP 51 Nicrocontrollefr 91 m m qs 91 11 2 Instruction 1 93 11 2 1 Instruction and CPU Timing 93 11 3 CIP 51 Register Descriptions rtr tu iet n tr ex eter mr Ro Rene 97 11 4 Serial Number Special Function Registers SFRS 101 12 Memory Organization U U u u 102 12 1 Program 102 12 1 1 MOVX Instruction and Pro
104. SFR Address OxF4 SFR Page OxOF Bit Name Function 7 0 P3MDIN 7 0 Analog Configuration Bits for P3 7 P3 0 respectively Port pins configured for analog mode have their weak pull up and digital receiver disabled For analog mode the pin also needs to be configured for open drain mode in the PSMDOUT register 0 Corresponding P3 n pin is configured for analog mode 1 Corresponding P3 n pin is not configured for analog mode Note Port P3 1 P3 7 are only available on the 48 pin and 40 pin packages SFR Definition 20 27 PSMDOUT Port 3 Output Mode Bit 7 6 5 4 3 2 1 0 Name P3MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address OxAE SFR Page Ox0F Bit Name Function 7 0 PSMDOUT 7 0 Output Configuration Bits for P3 7 P3 0 respectively These bits are ignored if the corresponding bit in register PSMDIN is logic 0 0 Corresponding P3 n Output is open drain 1 Corresponding P3 n Output is push pull Note Port P3 1 P3 7 are only available on the 48 pin and 40 pin packages 211 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 28 P3SKIP Port 3Skip Bit 7 6 5 4 3 2 1 0 Name P3SKIP 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD7 SFR Page OxOF Bit Name Function 7 0 PSSKIP 7 0 Port 3 Crossbar Skip
105. SFRLAST is the third entry The SFR stack bytes may be used alter the context in the SFR Page Stack and will not cause the stack to push or pop Only interrupts and return from interrupts cause pushes and pops of the SFR Page Stack SILICON LABS Rev 1 3 116 8051 58 59 Table 13 1 Special Function Register SFR Memory Map for Pages 0x00 0x10 and 0x0F 2 0 8 1 9 2 3 B 4 C 5 0 6 E F8 SPIOCN PCAOL PCAOH PCAOCPLO PCAOCPHO PCACPL4 PCACPH4 VDMOCN PCA1L PCA1H PCA1CPL6 PCA1CPH6 PCA1CPL10 PCA1CPH10 SNO SN1 SN2 SN3 FO B POMAT POMASK P1MAT P1MASK PSBANK EIP2 All Pages All Pages POMDIN P1MDIN P2MDIN P3MDIN EIP2 E8 ADCOCN PCAOCPL1 1 PCAOCPL2 PCAOCPH2 PCAOCPL3 RSTSRC PCA1CPL7 PCA1CPH7 PCA1CPL8 PCA1CPH8 PCA1CPL9 PCA1CPL9 ACC All Pages XBRO XBR1 CCHOCN ITO1CF PCAOMD PCAOCPMO PCAOCPM1 2 PCA1CN PCA1MD PCA1CPM6 PCA1CPM7 PCA1CPM8 CA1CPM9 CA1CPM10 PCA1CPM11 PCAOPWM PSW REFOCN LINODATA LINOADDR All Pages POSKIP P1SKIP P2SKIP P3SKIP TMR2CN REGOCN TMR2RLL TMR2RLH TMR2L TMR2H PCAOCPL5 PCAOCPH5 TMR4CN TMR4CF TMR4CAPL TMR4CAPH TMR4L TMR4H PCA1CPL11 PCA1CPH11 LINOCF CO S
106. Supply Rejection External Reference REFBE 0 Input Voltage Range Input Current Sample Rate 200 ksps VREF 1 5 V Power Specifications Reference Bias Generator REFBE 1 or TEMPE 1 Rev 1 3 52 SILICON LABS 8051 58 59 Table 5 13 Comparator 0 1 and 2 Electrical Characteristics VIO 1 8 to 5 25 V 40 to 125 C unless otherwise noted Parameter Conditions Response Time CPn 100 mV Mode 0 Vem 1 5 V CPn 100 mV Response Time CPn 100 mV Mode 1 Vom 1 5 V CPn 100 mV Response Time CPn 100 mV Mode 2 Vem 1 5 V CPO 100 mV Response Time CPn 100 mV Mode 3 Vem 1 5 V CPn 100 mV Common Mode Rejection Ratio Positive Hysteresis 1 CPnHYP1 0 00 Positive Hysteresis 2 CPnHYP1 0 01 Positive Hysteresis 3 CPnHYP1 0 10 Positive Hysteresis 4 CPnHYP1 0 11 Negative Hysteresis 1 CPnHYN1 0 00 Negative Hysteresis 2 CPnHYN1 0 01 Negative Hysteresis 3 CPnHYN1 0 10 Negative Hysteresis 4 CPnHYN1 0 11 Inverting or Non Inverting Input Voltage Range Input Capacitance Input Offset Voltage Power Supply Power Supply Rejection Power Up Time Mode 0 Mode 1 Mode 2 Mode 3 Supply Current at DC Note Vcm is
107. TC and TC to calculate the new internal oscillator frequency using the following equation f T 1 TC x T TO X T a TO where f0 is the internal oscillator frequency at 25 and TO is 25 49 Rev 1 3 SILICON LABS 8051 58 59 Table 5 7 Clock Multiplier Electrical Specifications Vpp 1 8 to 2 75 V 40 to 125 C unless otherwise specified Parameter Conditions Input Frequency Output Frequency Power Supply Current Table 5 8 Crystal Oscillator Electrical Characteristics Vpp 1 8 to 2 75 V 40 to 125 C unless otherwise specified Parameter Conditions Crystal Frequency XOSCMD 110b XFCN 000b XFCN 001b XFCN 010b Crystal Drive Current XFCN 011b XFCN 100b XFCN 101b XFCN 110b XFON 111b Table 5 9 Voltage Regulator Electrical Characteristics Vpp 1 8 to 2 75 V 40 to 125 unless otherwise specified Parameter Conditions Min Typ Max Units Input Voltage Range VngaiN 1 8 5 25 V Dropout Voltage Vpo Maximum Current 50 mA 10 mV mA 2 1V ation REGOMD 0 2 0 2 1 2 25 Output Voltage Vpp V 2 6 V operation REG0MD 1 2 5 2 6 2 75 Bias Current 1 9 Dropout Indicator Detection Threshold With respect to 0 21 0 02 V Output Voltage Temperature __ 0 04 __ mV C Coefficient VREG Settling
108. TMR2L TMR2H TL Interrupt z 5 TF2CEN SYSCLK 1 S T5 2 T2XCLK TMR2RLL TMR2RLH Reload Figure 27 4 Timer 2 16 Bit Mode Block Diagram 27 2 2 8 bit Timers with Auto Reload When T2SPLIT is set Timer 2 operates as two 8 bit timers TMR2H and TMR2L Both 8 bit timers oper ate in auto reload mode as shown in Figure 27 5 TMR2RLL holds the reload value for TMR2L TMR2RLH holds the reload value for TMR2H The TR2 bit in TMR2CN handles the run control for TMR2H TMR2L is always running when configured for 8 bit Mode Each 8 bit timer may be configured to use SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 The Timer 2 Clock Select bits T2MH and T2ML in CKCON select either SYSCLK or the clock defined by the Timer 2 External Clock Select bit T2XCLK in TMR2CN as follows SILICON LABS T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source 0 0 SYSCLK 12 0 0 SYSCLK 12 0 1 External Clock 8 0 1 External Clock 8 1 X SYSCLK 1 X SYSCLK Rev 1 3 295 8051 58 59 The TF2H bit is set when TMR2H overflows from OxFF to 0x00 the TF2L bit is set when TMR2L overflows from OxFF to 0x00 When Timer 2 interrupts are enabled IE 5 an interrupt is generated each time TMR2H overflows If Timer 2 interrupts are enabled and TF2LEN TMR2CN 5 is set an interrupt is gener ated each time either TMR2L or TMR2H overfl
109. The selected device should be configured according to Equation 23 1 00 Timer 0 Overflow 01 Timer 1 Overflow 10 Timer 2 High Byte Overflow 11 Timer 2 Low Byte Overflow SILICON LABS Rev 1 3 245 8051 58 59 23 4 2 SMBOCN Conirol Register SMBOCN is used to control the interface and to provide status information see SFR Definition 23 2 The higher four bits of SMBOCN MASTER TXMODE STA and STO form a status vector that can be used to jump to service routines MASTER indicates whether a device is the master or slave during the current transfer TXMODE indicates whether the device is transmitting or receiving data for the current byte STA and STO indicate that a START and or STOP has been detected or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a mas ter Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free STA is not cleared by hardware after the START is generated Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle If STO and STA are both set while in Master Mode a STOP followed by a START will be generated As a receiver writing the ACK bit defines the outgoing ACK value as a transmitter reading the ACK bit indicates the value received during the last ACK cycle ACKRQ is set each t
110. Ti 50 mA load with 2 4 V Vpp load capacitor of 4 8 us Note The minimum input voltage is 1 8 V or Vpp Vpo max load whichever is greater Rev 1 3 50 SILICON LABS 8051 58 59 Table 5 10 ADCO Electrical Characteristics VDDA 1 8 to 2 75 V 40 to 125 C VREF 1 5 V REFSL 0 unless otherwise specified Parameter Conditions DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance 10 kHz s ine wave single ended input 1 dB below Full Scale 200 Signal to Noise Plus Distortion 66 Total Harmonic Distortion Spurious Free Dynamic Range Up to the 5th harmonic Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks clocks Track Hold Acquisition Time VDDA 22 0 V VDDA lt 2 0 V us Throughput Rate VDDA 22 0 V Analog Inputs ADC Input Voltage Range gain 1 0 default VREF VREF n Absolute Pin Voltage with respect to GND Vio Sampling Capacitance Input Multiplexer Impedance Power Specifications Power Supply Current VDDA supplied to ADCO Operating Mode 200 ksps Burst Mode Idle us Power Supply Rejection Ratio
111. VREF is used PO0 1 if the ADC is configured to use the external conversion start signal CNVSTR P0 3 and or P0 2 if the external oscillator circuit is enabled and any selected ADC or Comparator inputs The Crossbar skips selected pins as if they were already assigned and moves to the next unassigned pin P3 1 P3 7 P4 0 E P4 1 P4 7 E available on the 48 pin available on the 48 and 40 pin E pin E PIN OW 2 84 5 6 7 0 12272 4 5 670 1 273 2 5 6 7 0 1234567 1234567 UARTO_TX UARTO_RX CAN_TX CAN_RX SCK MISO MOSI NSS SDA SCL CP1 CP1A SYSCLK CEXO CEX1 CEX2 CEX3 CEX4 5 Figure 20 3 Peripheral Availability on Port I O Pins Registers XBRO XBR1 XBR2 and XBR3 are used to assign the digital I O resources to the physical I O Port pins Note that when the SMBus is selected the Crossbar assigns both pins associated with the SMBus SDA and SCL and similarly when the UART CAN or LIN are selected the Crossbar assigns both pins associated with the peripheral TX and RX 193 Rev 1 3 lt gt SILICON LABS 8051 58 59 PIN UARTO_TX UARTO_RX CAN_TX CAN RX SCK MISO MOSI NSS SDA SCL CP1 CP1A SYSCLK CEXO CEX1 CEX2 CEX3 CEX4 5 P3 1 P3 7 4 0 only P4
112. W Reset 0 0 Varies Varies Varies Varies Varies Varies SFR Address Ox9E SFR Page OxOF Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 0 OSCIFIN 5 0 Internal Oscillator Fine Calibration Bits These bits are fine adjustment for the internal oscillator period The reset value is factory calibrated to generate an internal oscillator frequency of 24 MHz SILICON LABS Rev 1 3 180 8051 58 59 19 3 Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro grammable factor of 1 2 3 2 4 or 1 2 2 5 2 6 or 1 3 or 2 7 The Clock Multiplier s input can be selected from the external oscillator or the internal or external oscillators divided by 2 This produces three possible base outputs which can be scaled by a programmable factor Internal Oscillator x 2 External Oscillator x 2 or External Oscillator x 4 See Section 19 1 on page 176 for details on system clock selec tion The Clock Multiplier is configured via the CLKMUL register SFR Definition 19 5 The procedure for con figuring and enabling the Clock Multiplier is as follows Reset the Multiplier by writing 0x00 to register CLKMUL Select the Multiplier input source via the MULSEL bits Select the Multiplier output scaling factor via the MULDIV bits Enable the Multiplier with the MULEN bit CLKMUL 0x80 Delay for gt 5 us Init
113. WDT Software Reset SWRSF EN Errant FLASH Q s Operation System 51 Microcontroller 5 Reset Core Extended Interrupt Handler Figure 17 1 Reset Sources Rev 1 3 152 SILICON LABS 8051 58 59 17 1 Power On Reset During power up the device is held in a reset state and the RST pin is driven low until Vpp settles above A delay occurs before the device is released from reset the delay decreases as the Vpp ramp time increases Vpp ramp time is defined as how fast Vpp ramps from 0 V to Vnsr Figure 17 2 plots the power on and Vpp monitor reset timing The maximum Vpp ramp time is 1 ms slower ramp times may cause the device to be released from reset before Vpp reaches the level For ramp times less than 1 ms the power on reset delay Tponpeiay is typically less than 0 3 ms On exit from a power on reset the PORSF flag RSTSRC 1 is set by hardware to logic 1 When PORSF is set all of the other reset flags in the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The content of internal data mem ory should be assumed to be undefined after a power on reset The Vpp monitor is enabled following a power on reset Note For devices with a date code before year 2011 wor
114. XBEO 6 5 SOPT 1 0 Parity Type Select Bits 00 Odd Parity 01 Even Parity 10 Mark Parity 11 Space Parity 4 PEO Parity Enable This bit enables hardware parity generation and checking The parity type is selected by bits SOPT 1 0 when parity is enabled 0 Hardware parity is disabled 1 Hardware parity is enabled 3 2 SODL 1 0 Data Length 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data 1 XBEO _ Extra Bit Enable When enabled the value of TBXO will be appended to the data field 0 Extra Bit is disabled 1 Extra Bit is enabled 0 SBLO Stop Bit Length 0 Short stop bit is active for one bit time 1 Long stop bit is active for two bit times data length 6 7 or 8 bits or 1 5 bit times data length 5 bits Rev 1 3 262 SILICON LABS 8051 58 59 SFR Definition 24 3 SBUFO Serial UARTO Port Data Buffer Bit 7 6 5 4 3 2 1 0 Name SBUFO 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0x99 SFR Page 0x00 Bit Name Function 7 0 SBUFO 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUFO it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUFO initiates the transmission A read of SBUFO returns the contents of the receive
115. a match or capture occurs When the CCF9 interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF8 PCA1 Module 8 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF8 interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF7 PCA1 Module 7 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF7 interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF6 PCA1 Module 6 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the interrupt is enabled setting this bit causes the CPU to vector to the PCA1 interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software SILICON LABS Rev 1 3 345 8051 58 59 SFR Definition 29 2 PCA1MD PCA1 Mode Bit 7 6 5 4 3 2 1 0 Name CIDL1 CPS12 CPS11 CPS10 ECF1 Type R W R R W R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addre
116. accessed through the C2 interface using the WriteAR and ReadDR Write DR commands described in Application Note 127 Flash Programming via the C2 Interface C2 Register Definition 30 6 FPSEL C2 Flash Bank Select Bit 7 6 5 4 3 2 1 0 Name BSEL Type R R R R R R R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xC6 SFR Page 0x01 Bit Name Function 7 1 Unused Read 0000000b Write Don t Care 0 BSEL Flash Programming Bank Select 0 The address range 0x0000 OxFFFF accesses Banks 0 1 1 The address range 0x0000 OxFFFF accesses Banks 2 3 354 Rev 1 3 SILICON LABS 8051 58 59 30 2 C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and Flash programming may be performed This is possible because C2 communication is typically performed when the device is in the halt state where all on chip peripherals and user software are stalled In this halted state the C2 interface can safely borrow the C2CK RST and C2D pins In most applications external resistors are required to isolate C2 interface traffic from the user application A typical isolation configuration is shown in Figure 30 1 C8051 Fxxx RST a X C2CK Input b x C2D Output C2 Interface Master Figure 30 1 Typical C2 Pin Sharing The configuration in Figure 30 1 assumes the following 1 The user input
117. any slave node terminates the Sleep Mode of the LIN bus To send a wake up signal the application has to set the WUPREQ bit LINOCTRL 1 After successful trans mission of the wake up signal the DONE bit LINOST O of the master node is set and an interrupt request is generated The LIN slave does not generate an interrupt request after successful transmission of the wake up signal but it generates an interrupt request if the master does not respond to the wake up signal within 150 milliseconds In that case the ERROR bit LINOST 2 and TOUT bit LINOERR 2 are set The application then has to decide whether or not to transmit another wake up signal All LIN nodes that detect a wake up signal will set the WAKEUP LINOST 1 and DONE bits LINOST 0 and generate an interrupt request After that the application has to clear the SLEEP bit LINOCTRL 6 in the LIN slave 21 6 Error Detection and Handling The LIN controller generates an interrupt request and stops the processing of the current frame if it detects an error The application has to check the type of error by processing LINOERR After that it has to reset the error register and the ERROR bit LINOST 2 by writing a 1 to the RSTERR bit LINOCTRL 2 Starting a new message with the LIN controller selected as master or sending a Wakeup signal with the LIN control ler selected as a master or slave is possible only if the ERROR bit LINOST 2 is set to 0 Rev 1 3 220 SILICON LABS C8051F5
118. be achieved by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers or serial buses draw little power when they are not in use Turning off oscillators lowers power consumption considerably at the expense of reduced functionality 16 1 Idle Mode Setting the Idle Mode Select bit 0 causes the hardware to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data All analog and digital peripherals can remain active during Idle mode Idle mode is terminated when an enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the Idle Mode Selection bit 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0 0000 Note If the instruction following the write of the IDLE bit is a single byte instruction and an interrupt occurs during the execution phase of the instruction that sets the IDLE bit the CPU may not wake from Idle mode whe
119. bit TMR2CN 3 defines the Timer 2 operation mode Timer 2 may be clocked by the system clock the system clock divided by 12 or the external oscillator source divided by 8 The external clock mode is ideal for real time clock RTC functionality where the internal oscillator drives the system clock while Timer 2 and or the PCA is clocked by an external preci sion oscillator Note that the external oscillator source divided by 8 is synchronized with the system clock 27 2 1 16 bit Timer with Auto Reload When T2SPLIT TMR2CN 3 is zero Timer 2 operates as a 16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from OxFFFF to 0 0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as shown in Figure 27 4 and the Timer 2 High Byte Overflow Flag TMR2CN 7 is set If Timer 2 interrupts are enabled if IE 5 is set an interrupt will be generated on each Timer 2 overflow Additionally if Timer 2 interrupts are enabled and the TF2LEN bit is set TMR2CN 5 an interrupt will be generated each time the lower 8 bits TMR2L overflow from OxFF to 0x00 T2XCLK M To ADC SYSCLK 12 0 To SMBus SMBus Overflow TR2 4 External Clock 8 1
120. bit is set and a STOP is generated Note that the interface will switch to Master Receiver Mode if SMBODAT is not written following a Master Transmitter interrupt Figure 23 5 shows a typical master write sequence Two transmit data bytes are shown though any num ber of bytes may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode Received by SMBus S START Interface P STOP A ACK Transmitted by W SMBus Interface SLA Slave Address Figure 23 5 Typical Master Write Sequence 250 Rev 1 3 SILICON LABS 8051 58 59 23 5 2 Read Sequence Masier During a read sequence an SMBus master reads data from a slave device The master in this transfer will be a transmitter during the address byte and a receiver during all data bytes The SMBus interface gener ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 1 READ Serial data is then received from the slave on SDA while the SMBus outputs the serial clock The slave transmits one or more bytes of serial data An interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte Writing a 1 to the ACK bit generates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit for the last data tran
121. bit sets the masking of the Timer 3 interrupt 0 Disable Timer 3 interrupts 1 Enable interrupt requests generated by the TF3L or TF3H flags ECP1 Enable Comparator1 CP1 Interrupt This bit sets the masking of the CP1 interrupt 0 Disable CP1 interrupts 1 Enable interrupt requests generated by the CP1RIF or CP1FIF flags ECPO Enable 0 Interrupt This bit sets the masking of the CPO interrupt 0 Disable CPO interrupts 1 Enable interrupt requests generated by the CPORIF or CPOFIF flags Enable Programmable Counter Array PCAO Interrupt This bit sets the masking of the PCAO interrupts 0 Disable all PCAO interrupts 1 Enable interrupt requests generated by PCAO EADCO Enable ADCO Conversion Complete Interrupt This bit sets the masking of the ADCO Conversion Complete interrupt 0 Disable ADCO Conversion Complete interrupt 1 Enable interrupt requests generated by the ADOINT flag EWADCO ESMBO Enable Window Comparison ADCO Interrupt This bit sets the masking of ADCO Window Comparison interrupt 0 Disable ADCO Window Comparison interrupt 1 Enable interrupt requests generated by ADCO Window Compare flag ADOWINT Enable SMBus 5 0 Interrupt This bit sets the masking of the SMBO interrupt 0 Disable all SMBO interrupts 1 Enable interrupt requests generated by SMBO Rev 1 3 132 SILICON LABS 8051 58 59
122. by adding 4 SYSCLK cycles to the timing parameters defined by the EMIOTC register Assuming non multiplexed operation the minimum execution time for an off chip XRAM operation is 5 SYSCLK cycles 1 SYSCLK for RD or WR pulse 4 SYSCLKs For multiplexed operations the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles Therefore the minimum execution time for an off chip XRAM operation in multiplexed mode is 7 SYSCLK cycles 2 for ALE 1 for RD or WR 4 The programmable setup and hold times default to the maximum delay settings after a reset Table 18 3 lists the ac parameters for the External Memory Interface and Figure 18 4 through Figure 18 9 show the timing diagrams for the different External Memory Interface modes and MOVX operations 167 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 18 3 EMIOTC External Memory Timing Control Bit 7 6 5 4 3 2 1 0 5 1 0 EWR 3 0 EAH 1 0 R W R W R W Name Type Reset 1 1 1 1 1 1 1 1 SFR Address SFR Page OxOF Bit Name Function 7 6 EAS 1 0 EMIF Address Setup Time Bits 00 Address setup time 0 SYSCLK cycles 01 Address setup time 1 SYSCLK cycle 10 Address setup time 2 SYSCLK cycles 11 Address setup time 3 SYSCLK cycles 5 2 EWR 3 0 EMIF WR and RD Pulse Width Control Bits 0000 WR and RD pulse width 1 SYSCLK cy
123. capacitor RC or CMOS clock mode Port pin 0 3 is used as XTAL2 The Port I O Crossbar should be configured to skip the Port pins used by the oscillator circuit see Section 20 3 Priority Crossbar Decoder on page 192 for Crossbar configuration Additionally when using the external oscillator circuit in crystal resonator capacitor or RC mode the associated Port pins should be configured as analog inputs In CMOS clock mode the associated pin should be configured as a digital input See Section 20 4 Port I O Initialization on page 195 for details on Port input mode selection Rev 1 3 183 SILICON LABS 8051 58 59 SFR Definition 19 6 OSCXCN External Oscillator Control Bit 7 6 5 4 3 2 1 Name XTLVLD XOSCMD 2 0 XFCN 2 0 Reset 0 0 0 0 0 0 0 SFR Address 0 9 SFR Page OxOF Bit Name Function 7 XTLVLD Crystal Oscillator Valid Flag Read only when XOSCMD 11x 0 Crystal Oscillator is unused or not yet stable 1 Crystal Oscillator is running and stable 6 4 XOSCMD 2 0 External Oscillator Mode Select 00x External Oscillator circuit off 010 External CMOS Clock Mode 011 External CMOS Clock Mode with divide by 2 stage 100 RC Oscillator Mode 101 Capacitor Oscillator Mode 110 Crystal Oscillator Mode 111 Crystal Oscillator Mode with divide by 2 stage 3 Unused Read 0b Write 00
124. chip 8 bit off chip MOVX operations use current contents of the Address high port latches to resolve the upper address byte To access off chip space EMIOCN must be set to a page that is not con tained in the on chip address space 10 Split Mode with Bank Select Accesses below the 8 kB boundary are directed on chip Accesses above the 8 kB boundary are directed off chip 8 bit off chip MOVX operations uses the contents of EMIOCN to determine the high byte of the address 11 External Only MOVX accesses off chip XRAM only On chip XRAM is not visible to the CPU 1 0 EALE 1 0 ALE Pulse Width Select Bits These bits only have an effect when EMD2 0 00 ALE high and ALE low pulse width 1 SYSCLK cycle 01 ALE high and ALE low pulse width 2 SYSCLK cycles 10 ALE high and ALE low pulse width 3 SYSCLK cycles 11 ALE high and ALE low pulse width 4 SYSCLK cycles 163 Rev 1 3 SILICON LABS 8051 58 59 18 4 Multiplexed and Non multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non multiplexed mode depending on the state of the EMD2 EMIOCF 4 bit 18 4 1 Multiplexed Configuration In Multiplexed mode the Data Bus and the lower 8 bits of the Address Bus share the same Port pins AD 7 0 In this mode an external latch 74HC373 or equivalent logic gate is used to hold the lower 8 bits of the RAM address The external latch is controlled by the ALE Address Lat
125. determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper 8 bits A 15 8 of the Address Bus during an off chip access This allows the user to manipulate the upper address bits at will by setting the Port state directly via the port latches This behavior is in contrast with Split Mode with Bank Select described below The lower 8 bits of the Address Bus A 7 0 are driven determined by RO or R1 m 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is on chip or off chip and unlike 8 bit MOVX operations the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction Rev 1 3 166 SILICON LABS 8051 58 59 18 5 3 Split Mode with Bank Select When EMIOCF 3 2 are set to 10 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the internal XRAM size boundary will access on chip XRAM space Effective addresses above the internal XRAM size boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is on chip or off chip The upper 8 bits of the Address Bus A 15 8 are determined by EMIOCN and the lower 8 bits of the Address Bus A 7 0 are determined by RO or R1 All 16 bits of the Address Bus A 15 0 are driven in Bank Select mode m 16 bit MOVX operations use t
126. direct data AND immediate to direct byte 3 3 ORL A Rn OR Register to A 1 1 ORL A direct OR direct byte to A 2 2 ORL Ri OR indirect RAM to A 1 2 ORL A data OR immediate to A 2 2 ORL direct A OR A to direct byte 2 2 ORL direct data OR immediate to direct byte 3 3 XRL A Rn Exclusive OR Register to A 1 1 XRL A direct Exclusive OR direct byte to A 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 Note Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the FLRT setting SFR Definition 15 3 94 Rev 1 3 SILICON LABS 8051 58 59 Table 11 1 CIP 51 Instruction Set Summary Prefetch Enabled Continued Mnemonic Description Bytes Clock Cycles XRL A data Exclusive OR immediate to A 2 2 XRL direct A Exclusive OR A to direct byte 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 CLRA Clear A 1 1 CPLA Complement A 1 2 RLA Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 RRA Rotate A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A MOV A direct Move direct byte to A MOV A Ri Move indirect RAM to A MOV A data Move immediate to A MOV Rn A Move A to Register MOV Rn direct Move direct byte to Register MOV Rn Move immediate to Register MOV direct A Move A to direct
127. each instruction Rev 1 3 93 SILICON LABS 8051 58 59 Table 11 1 CIP 51 Instruction Set Summary Prefetch Enabled Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A Rn Add register to A 1 1 ADD A direct Add direct byte to A 2 2 ADD A Ri Add indirect RAM to A 1 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 1 2 SUBB A data Subtract immediate from A with borrow 2 2 INCA Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 1 2 DECA Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DAA Decimal adjust A 1 1 Logical Operations ANL A Rn AND Register to A 1 1 ANL A direct AND direct byte to A 2 2 ANL A Ri AND indirect RAM to A 1 2 ANL A data AND immediate to A 2 2 ANL direct A AND A to direct byte 2 2 ANL
128. gt 7 ET a 8i X Pto al 1 7 ae P20 gt P27 1 Pao 1 1 P37 P40 Lowest P47 Priority Lowest Prior isters Pot Reg Latches Figure 20 1 Port I O Functional Block Diagram 189 1 3 SILICON LABS 8051 58 59 20 1 Port I O Modes of Operation Port pins PO 0 P3 7 use the Port I O cell shown in Figure 20 2 Each of these Port I O cells can be config ured by software for analog or digital using the PnMDIN registers P4 0 P4 7 use a similar cell except that they can only be configured as digital I O pins and do not have a corresponding PnMDIN or PnSKIP register On reset all Port I O cells default to a high impedance state with weak pull ups enabled until the Crossbar is enabled XBARE 1 20 1 1 Port Pins Configured for Analog I O Any pins to be used as Comparator or ADC inputs external oscillator inputs or VREF should be config ured for analog I O PnMDIN n 0 When a pin is configured for analog I O its weak pullup digital driver and digital receiver are disabled Port pins configured for analog I O will always read back a value of 0 Configuring pins as analog saves power and isolates the Port pin from digital interference Port pins configured as digital inputs may still be used by analog peripherals however this practice is not recom mended and may result in measurement errors 20 1 2 Port Pins Configured
129. i Mc P 202 POMDIN Port 0 Input Mode 203 POMDOUT Port 0 Output Mode 203 POSKIP Port 0 Skip 204 Sd uec c 204 P1MDIN Port 1 Input Mode 205 SFR Definition 20 19 P1MDOUT Port 1 Output Mode 205 SFR Definition 20 20 PTSKIP Port 1 Skip 206 SFR Definition 20 21 P2 Port 206 SFR Definition 20 22 P2MDIN Port 2 Input Mode 207 SFR Definition 20 23 PAMDOUT Port 2 Output Mode 207 SFR Definition 20 24 P2SKIP Port 2 04 000011 208 SFR Definition 20 25 P3 PODES iiie luae uuu uuu CUM 208 SFR Definition 20 26 PSMDIN Port Input Mode 209 SFR Definition 20 27 PSMDOUT Port 3 Output Mode 209 SFR Definition 20 28 P3SKIP Port 3SKID 210 SFR Definition 20 29 P4 4 00 210 SFR Definition 20 30 PAMDOUT Port 4 Output Mode
130. in the associated module s cap ture compare register PCA1CPn the output on CEXn is asserted high When the counter overflows from the Nth bit CEXn is asserted low see Figure 29 9 Upon an overflow from the Nth bit the COVF1 flag is set and the value stored in the module s auto reload register is loaded into the capture compare register The value of is determined by the CLSEL1 bits in register PCA1PWM The 9 10 or 11 bit PWM mode is selected by setting the ECOM1n PWM in bits in the PCA1CPMn reg ister and setting the CLSEL1 bits in register PCA1PWM to the desired cycle length other than 8 bits If the MAT1n bit is set to 1 the CCFn flag for the module will be set each time a comparator match rising edge occurs The COVF1 flag in PCA1PWM can be used to detect the overflow falling edge which will occur every 512 9 bit 1024 10 bit or 2048 11 bit PCA1 clock cycles The duty cycle for 9 10 11 Bit PWM Mode is given in Equation 29 2 where N is the number of bits in the PWM cycle Important Note About PCA1CPHn and PCA1CPLn Registers When writing a 16 bit value to the PCA1CPn registers the low byte should always be written first Writing to PCA1CPLn clears the ECOM1n bit to 0 writing to PCA1CPHn sets ECOMf1n to 1 2N_ PCAICPn Duty Cycle ON Equation 29 3 9 10 and 11 Bit PWM Duty Cycle 0 duty cycle may be generated by clearing the ECOM 1n bit to 0 Write to PCA1CPL 0 R c ur Auto Relo
131. is started immediately following the convert start signal Conversions are started after the pro grammed tracking time ends After a conversion is complete ADCO does not track the input Rather the sampling capacitor remains disconnected from the input making the input pin high impedance until the next convert start signal Dual Tracking Mode is selected when ADOTM is set to 11b A programmable tracking time based on ADOTK is started immediately following the convert start signal Conversions are started after the pro grammed tracking time ends After a conversion is complete ADCO tracks continuously until the next con version is started Depending on the output connected to the ADC input additional tracking time more than is specified in Table 5 10 may be required after changing MUX settings See the settling time requirements described in Section 6 2 1 Settling Time Requirements on page 59 Convert Start j Pre Tracking ADOTM 10 Track Convert Track Convert Post Tracking ADOTM 01 Convert Idle Track Convert Idle Track Dual Tracking ADOTM 11 Track Track Convert Track Track Convert Figure 6 2 ADCO Tracking Modes 6 1 3 Timing ADCO has a maximum conversion speed specified in Table 5 10 ADCO is clocked from the ADCO Subsys tem Clock FCLK The source of FCLK is selected based on the BURSTEN bit When BURSTEN is logic 0 FCLK is derived from the current system clo
132. listed in Table 5 5 on page 48 To change the Vpp Monitor high threshold perform the follow ing steps Disable interrupts Write 0x01 to the SFRPAGE register Copy the value from SFR address 0x93 to SFR address 0x94 Return the SFRPAGE register to its previous value Rev 1 3 138 SILICON LABS 8051 58 59 15 1 2 Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function The Flash Lock and Key Register FLKEY must be written with the correct key codes in sequence before Flash operations may be performed The key codes are 5 OxF1 The timing does not matter but the codes must be written in order If the key codes are written out of order or the wrong codes are written Flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly The Flash lock resets after each write or erase the key codes must be written again before a following Flash operation can be per formed The FLKEY register is detailed in SFR Definition 15 2 15 1 3 Flash Erase Procedure The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands Before writing to Flash memory using MOVX Flash write operations must be enabled by doing the following
133. may individually shut down any or all peripherals for power savings The on chip Silicon Labs 2 Wire C2 Development Interface allows non intrusive uses no on chip resources full speed in circuit debugging using the production MCU installed in the final application This debug logic supports inspection and modification of memory and registers setting breakpoints single stepping run and halt commands All analog and digital peripherals are fully functional while debugging using C2 The two C2 interface pins can be shared with user functions allowing in system debugging with out occupying package pins The devices are specified for 1 8 V to 5 25 V operation over the automotive temperature range 40 to 125 The Port I O and RST pins can interface to 5 V logic by setting the VIO pin to 5 V The C8051F580 1 4 5 devices are available in 48 pin QFP and QFN packages and the C8051F588 9 F590 1 devices are available in a 40 pin QFN package and the C8051F582 3 6 7 devices are available in 32 pin and QFN packages All package options are lead free and RoHS compliant See Table 2 1 for order ing information Block diagrams are included in Figure 1 1 and Figure 1 3 Rev 1 3 18 SILICON LABS 8051 58 59 Power 1 51 8051 Port I O Configuration pad Reset U Digital Peripher
134. mode is not selected these bits select the length of the PWM cycle between 8 9 10 or 11 bits This affects all channels configured for PWM which are not using 16 bit PWM mode These bits are ignored for individual channels config ured to16 bit PWM mode 00 8 bits 01 9 bits 10 10 bits 11 11 bits 329 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 28 4 PCAOCPMn Capture Compare Mode Bit 7 6 5 4 3 2 1 0 Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addresses OxDA PCAOCPM1 OxDB PCAOCPM2 OxDC OxDD PCAOCPM4 OxDE PCAOCPM5 OxDF SFR Page all registers 0x00 Bit Name Function 7 PWM16n 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled 0 8 to 11 bit PWM selected 1 16 bit PWM selected 6 Function Enable This bit enables the comparator function for PCAO module n when set to 1 5 CAPPn Capture Positive Function Enable This bit enables the positive edge capture for PCAO module n when set to 1 4 CAPNn Capture Negative Function Enable This bit enables the negative edge capture for PCAO module n when set to 1 3 MATn Match Function Enable This bit enables the match function for PCAO module n when set to 1 Whe
135. moved to the receive buffer where it can be read by the processor by reading SPIODAT When configured as a master SPIO can operate in one of three different modes multi master mode 3 wire single master mode and 4 wire single master mode The default multi master mode is active when NSS MD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In this mode NSS is an input to the device and is used to disable the master SPIO when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPIOCN 6 and SPIEN 0 are set to 0 to disable the SPI master device and Mode Fault is generated MODF SPIOCN 5 1 Mode Fault will generate an interrupt if enabled SPIO must be manually re enabled in software under these circumstances In multi master systems devices will typically default to being slave devices while they are not acting as the system master device In multi mas ter mode slave devices be addressed individually if needed using general purpose pins Figure 26 2 shows a connection diagram between two master devices in multiple master mode 3 wire single master mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 In this mode NSS is not used and is not mapped to an external port pin through the crossbar Any slave devices that must be addressed in this mode should be selected using general purpose pins Figure 26 3 shows a connection diagram between a master device in 3 wire master
136. of type defined by IT1 is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in the ITO1CF register see SFR Definition 14 7 0 INT1 is level triggered 1 INT1 is edge triggered 1 IEO External Interrupt 0 This flag is set by hardware when an edge level of type defined by IT1 is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine in edge triggered mode 0 ITO Interrupt 0 Type Select This bit selects whether the configured INTO interrupt will be edge or level sensitive INTO is configured active low or high by the INOPL bit in register ITO1CF see SFR Definition 14 7 0 INTO is level triggered 1 INTO is edge triggered Rev 1 3 291 8051 58 59 SFR Definition 27 3 TMOD Timer Mode Bit 7 6 5 4 3 2 1 0 GATE1 C T1 T1M 1 0 GATEO C TO TOM 1 0 Type R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x89 SFR Page All Pages Bit Name Function 7 GATE1 Timer 1 Gate Control 0 Timer 1 enabled when TR1 1 irrespective of INT1 logic level 1 Timer 1 enable
137. on CCFn set to 1 Enable 8th 9th 10th or 11th bit overflow interrupt Depends on setting of CLSEL 1 0 When set 0 the digital comparator is off For high speed and frequency output modes the associated pin will not toggle In any of the PWM modes this generates a 0 duty cycle output 0 D Selects whether the Capture Compare register 0 or the Auto Reload register 1 for the associated channel is accessed via addresses PCAOCPHn and PCAOCPLn When set a match event will cause the CCFn flag for the associated channel to be set All modules set to 8 9 10 or 11 bit PWM mode use the same cycle length setting 28 3 1 Edge triggered Capture Mode In this mode a valid transition on the CEXn pin causes PCAO to capture the value of the PCAO counter timer and load it into the corresponding module s 16 bit capture compare register PCAOCPLn and PCAOCPHn The CAPPn and CAPNn bits in the PCAOCPMn register are used to select the type of transi tion that triggers the capture low to high transition positive edge high to low transition negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser vice routine and must be cleared by software If
138. one shot circuit that is triggered by the system clock If the system clock remains high or low formore than the value specified in Table 5 4 the one shot will time out and gen erate a reset After a MCD reset the MCDRSF flag RSTSRC 2 will read 1 signifying the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock Detec tor writing a O disables it The state of the RST pin is unaffected by this reset 17 5 Comparator0 Reset ComparatorO can be configured as a reset source by writing a 1 to the CORSEF flag RSTSRC 5 Com paratorO should be enabled and allowed to settle prior to writing to CORSEF to prevent any turn on chatter on the output from generating an unwanted reset The Comparator0 reset is active low if the non inverting 155 Rev 1 3 SILICON LABS 8051 58 59 input voltage on is less than the inverting input voltage CPO the device is put into the reset state After Comparator0 reset the CORSEF flag RSTSRC 5 will read 1 signifying ComparatorO as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset 17 6 PCA Watchdog Timer Reset The programmable Watchdog Timer WDT function of the Programmable Counter Array PCAO can be used to prevent software from running out of control during a system malfunction The PCA WDT function can be enabled or disabled by software as described in Section
139. overflows from OxFFFF to 0x0000 When the Timer 2 interrupt is enabled setting this bit causes the CPU to vector to the Timer 2 interrupt service routine This bit is not automatically cleared by hardware 6 TF2L Timer 2 Low Byte Overflow Flag Set by hardware when the Timer 2 low byte overflows from OxFF to 0x00 TF2L will be set when the low byte overflows regardless of the Timer 2 mode This bit is not automatically cleared by hardware 5 TF2LEN Timer 2 Low Byte Interrupt Enable When set to 1 this bit enables Timer 2 Low Byte interrupts If Timer 2 interrupts are also enabled an interrupt will be generated when the low byte of Timer 2 overflows 4 TF2CEN Timer 2 Capture Mode Enable 0 Timer 2 Capture Mode is disabled 1 Timer 2 Capture Mode is enabled 3 T2SPLIT Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload 0 Timer 2 operates in 16 bit auto reload mode 1 Timer 2 operates as two 8 bit auto reload timers 2 TR2 Timer 2 Run Control Timer 2 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR2H only TMR2L is always enabled in split mode 1 Unused Read 06 Write Don t Care 0 T2XCLK 2 External Clock Select This bit selects the external clock source for Timer 2 If Timer 2 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 2 Clock Select bits T2MH and T2ML in r
140. parameter is defined by It is used for determining the value written to the Bit Timing Register and for determining the required oscillator tolerance Since we are using a quartz crystal as the system clock source an oscillator tolerance calculation is not needed SJW minimum 4 Phase Seg1 Equation 22 2 Synchronization Jump Width SJW The value written to the Bit Timing Register can be calculated using Equation 18 3 The BRP Extension register is left at its reset value of 0x0000 BRPE BRP 1 BRP Extension Register 0x0000 SJWp SJW 1 minimum 4 6 1 3 TSEG1 Prop Seg Phase 1 10 6 1 15 TSEG2 Phase Seg2 1 6 Bit Timing Register TSEG2 0x1000 TSEG1 0x0100 Bit Timing Register TSEG2 x 0x1000 TSEG1 x 0x0100 SUWp x 0x0040 BRPE 0x6FCO Equation 22 3 Calculating the Bit Timing Register Value 234 Rev 1 3 SILICON LABS 8051 58 59 22 2 CAN Registers CAN registers are classified as follows 1 CAN Coniroller Protocol Registers CAN control interrupt error control bus status test modes 2 Message Object Interface Registers Used to configure 32 Message Objects send and receive data to and from Message Objects The CIP 51 MCU accesses the CAN message RAM via the Message Object Interface Registers Upon writing a message object number to an IF1 or IF2 Command Request Register the contents of the associated Interface Registers IF1 or IF2 will be
141. pin and 40 pin package devices 100000 101111 Reserved 110000 Temp Sensor 110001 Vpp 110010 111111 GND 73 Rev 1 3 SILICON LABS 8051 58 59 7 Temperature Sensor An on chip temperature sensor is included on the C8051F58x F59x devices which can be directly accessed via the ADC multiplexer in single ended configuration To use the ADC to measure the tempera ture sensor the ADC multiplexer channel should be configured to connect to the temperature sensor The temperature sensor transfer function is shown in Figure 7 1 The output voltage Vrgyp is the positive ADC input is selected by bits ADOMX 4 0 in register ADCOMX The TEMPE bit in register REFOCN enables disables the temperature sensor as described in SFR Definition 8 1 While disabled the tempera ture sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data Refer to Table 5 11 for the slope and offset parameters of the temperature sen sor Slope x Offset Offset Slope H Slope V deg C Voltage 4 Offset V at 0 Celsius Temperature Figure 7 1 Temperature Sensor Transfer Function Rev 1 3 74 SILICON LABS 8051 58 59 8 Voltage Reference The Voltage reference multiplexer on the C8051F58x F59x devices is configurable to use an externally connected voltage reference the on c
142. register whose contents are updated only when the contents of PCA1L are read see Section 29 1 Bit 7 6 5 4 3 2 1 0 Name PCA1 15 8 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address OxFA SFR Page 0x10 Bit Name Function 7 0 PCA1 15 8 1 Counter Timer High Byte SILICON LABS Rev 1 3 349 8051 58 59 SFR Definition 29 7 PCA1CPLn PCA1 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 Name PCA1CPn 7 0 RW R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addresses PCA1CPL6 OxFB PCA1CPL7 OxE9 PCA1CPL8 OxEB PCA1CPL9 OxED PCA1CPL10 OxFD PCA1CPL11 SFR Page all registers 0x10 Bit Name Function 7 0 PCA1CPn 7 0 PCA1 Capture Module Low Byte The PCA1CPLn register holds the low byte LSB of the 16 bit capture module n This register address also allows access to the low byte of the corresponding 1 channel s auto reload value for 9 10 or 11 bit PWM mode ARSEL1 bit in register PCA1PWM controls which register is accessed Note A write to this register will clear module s ECOM1n bit to a 0 SFR Definition 29 8 PCA1CPHn PCA1 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA1CPn 15 8 RW R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addresses PCA1CPH6
143. should be used to assure good solder paste release 7 The stencil thickness should be 0 125 mm 5 mils 8 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads 9 3x3 array of 1 20 mm x 1 10mm openings 1 40 mm pitch should be used for the center pad Card Assembly 10 A No Clean Type 3 solder paste is recommended 11 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components 35 Rev 1 3 SILICON LABS 8051 58 59 4 3 QFN 40 Package Specifications To etail etail 2 in 1 Identifier Perimeter Lead Form TI TO TT p E E C 1 1 DN N lt 5 n m ptio pii ilar rner rner juar Im ilar Edg J SE tT ETT t m m 2 m 1 Figure 4 5 Typical QFN 40 Package Drawing Table 4 5 QFN 40 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0 80 0 85 0 90 E2 4 00 4 10 4 20 1 0 00 0 05 L 0 35 0 40 0 45 b 0 18 0 23 0 28 L1 0 10 D 6 00 BSC aaa 0 10 D2 4 00 4 10 4 20 bbb 0 10 e 0 50 BSC ddd 0 05 E 6 00 BSC eee 0 08 Notes 1 All dimensions shown
144. slave modes C8051 F580 2 4 6 8 F590 m True 12 bit 200 ksps 32 channel single ended ADC with analog multiplexer Precision programmable 24 MHz internal oscillator that is within 0 5 across the temperature range and for VDD voltages greater than or equal to the on chip voltage regulator minimum output at the low setting The oscillator is within 1 0 for VDD voltages below this minimum output setting On chip Clock Multiplier to reach up to 50 MHz m 128 kB C8051F580 1 2 3 8 9 or 96 C8051 F584 5 6 7 F590 1 of on chip Flash memory 8448 bytes of on chip RAM m SMBus l2C Two Enhanced UARTs and Enhanced SPI serial interfaces implemented in hardware m Six general purpose 16 bit timers m External Data Memory Interface C8051F580 1 4 5 with 64 kB address space m Two Programmable Counter Timer Array PCA modules with six capture compare modules each and one with a Watchdog Timer function m Three Voltage Comparators m On chip Voltage Regulator m On chip Power On Reset Vpp Monitor and Temperature Sensor m 40 33 or 25 Port I O 5 V push pull With an on chip Voltage Regulator Power On Reset and Vpp monitors Watchdog Timer and clock oscilla tor the C8051F58x F59x devices are truly stand alone System on a Chip solutions The Flash memory can be reprogrammed even in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and
145. started This bit is cleared at the start of a transmission 1 The current transmission is complete SILICON LABS Rev 1 3 226 8051 58 59 LIN Register Definition 21 7 LINOERR LINO Error Register Bit 7 6 5 4 3 2 1 0 Name SYNCH PRTY TOUT CHK BITERR Type R R R R R R R R Reset 0 0 0 0 0 0 0 0 Indirect Address Ox0A Bit Name Function 7 5 Unused Read 000b Write Don t Care 4 SYNCH Synchronization Error Bit slave mode only 0 No error with the SYNCH FIELD has been detected 1 Edges of the SYNCH FIELD are outside of the maximum tolerance 3 PRTY Parity Error Bit slave mode only 0 No parity error has been detected 1 A parity error has been detected 2 TOUT Timeout Error Bit 0 A timeout error has not been detected 1 A timeout error has been detected This error is detected whenever one of the fol lowing conditions is met master is expecting data from a slave and the slave does not respond slave is expecting data but no data is transmitted on the bus A frame is not finished within the maximum frame length The application does not set the DTACK bit LINOCTRL 4 or STOP bit LINOCTRL 7 until the end of the reception of the first byte after the identifier 1 CHK Checksum Error Bit 0 Checksum error has not been detected 1 Checksum error has been detected 0 BITERR Bit Transmission Erro
146. the Crossbar to skip the selected pin s This is accomplished by setting the associated bit in register XBRO see Section 20 3 Priority Crossbar Decoder on page 192 for complete details on configuring the Crossbar IEO TCON 1 and IE1 TCON 3 serve as the interrupt pending flags for the INTO and INT1 external inter rupts respectively If an INTO or INT1 external interrupt is configured as edge sensitive the corresponding interrupt pending flag is automatically cleared by the hardware when the CPU vectors to the ISR When configured as level sensitive the interrupt pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit INOPL or IN1PL the flag remains logic 0 while the input is inactive The external interrupt source must hold the input active until the interrupt request is recognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated Rev 1 3 136 SILICON LABS 8051 58 59 SFR Definition 14 7 ITO1CF INTO INT1 Configuration Bit 5 2 1 Name IN1SL 2 0 INOPL INOSL 2 0 Type R W R W R W R W Reset 0 0 0 0 SFR Address 0 4 SFR Page Ox0F Bit Name Function 7 6 4 IN1PL IN1SL 2 0 INT1 Polarity 0 INT1 input is active low 1 INT1 input is active high INT1 Port Pin Selectio
147. the INH bit is set all slave events will be inhibited following the next START interrupts will continue for the duration of the current transfer 242 Rev 1 3 SILICON LABS 8051 58 59 Table 23 1 SMBus Clock Source Selection SMBCS1 SMBCSO SMBus Clock Source 0 0 Timer 0 Overflow 0 1 Timer 1 Overflow 1 0 Timer 2 High Byte Overflow 1 1 Timer 2 Low Byte Overflow The SMBCS1 0 bits select the SMBus clock source which is used only when operating as a master or when the Free Timeout detection is enabled When operating as a master overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 23 1 Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times For example Timer 1 overflows may generate the SMBus and UART baud rates simultaneously Timer configuration is covered in Section 27 Timers on page 285 1 T uighMin E ClockSourceOverflow Equation 23 1 Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 23 1 When the interface is operating as a master and SCL is not driven or extended by any other devices on the bus the typical SMBus bit rate is approximated by Equation 23 2 f BitRate EE EE Equation 23 2 Typical SMBus Bit Rate Figure 23 4 show
148. the level required for data retention If the PORSF flag reads 1 the data may no longer be valid The Vpp monitor is enabled after power on resets Its defined state enabled disabled is not altered by any other reset source For example if the Vpp monitor is disabled by code and a software reset is performed the Vpp monitor will still be disabled after the reset To protect the integrity of Flash contents the Vpp monitor must be enabled to the higher setting VDMLVL 1 and selected as a reset source if soft ware contains routines which erase or write Flash memory If the Vpp monitor is not enabled and set to the high level any erase or write performed on Flash memory will cause a Flash Error device reset Important Note If the Vpp monitor is being turned on from a disabled state it should be enabled before it is selected as a reset source Selecting the Vpp monitor as a reset source before it is enabled and stabi lized may cause a system reset Ensure that there are no delays between the time the Vpp monitor is enabled and when it is enabled as a reset source 1 Enable the Vpp monitor VDMEN bit in VDMOCN 1 Ensure that there are no delays before step 2 is executed 2 Select the Vpp monitor as a reset source PORSF bit in RSTSRC 1 See Figure 17 2 for Vpp monitor timing note that the power on reset delay is not incurred after a Vpp monitor reset See Table 5 4 for complete electrical characteristics of the Vpp monitor When pro
149. the system clock divided by 12 depending on the T3ML CKCON 6 and T3XCLK bits When a capture event is generated the contents of Timer TMR3H TMR3L are loaded into the Timer 3 reload registers TMR3RLH TMR3RLL and the TF3H flag is set A capture event is generated by the falling edge of the clock source being measured which is the external oscillator 8 By recording the difference between two successive timer capture values the external oscillator frequency can be determined with respect to the Timer 3 clock The Timer 3 clock should be much faster than the capture clock to achieve an accurate reading Timer 3 should be in 16 bit auto reload mode when using Capture Mode If the SYSCLK is 24 MHz and the difference between two successive captures is 5861 then the external clock frequency is as follows 24 MHz 5861 8 0 032754 MHz or 32 754 kHz This mode allows software to determine the external oscillator frequency when an RC network or capacitor is used to generate the clock source 302 Rev 1 3 SILICON LABS 8051 58 59 gt gt 0 gt Og 2 MMM SYSCLK 12 4 External Clock 8 TMRSL TMR3H SYSCLK Capture External Clock 8 1 Y TMR3RLL TMR3RLH B TRAE gt Interrupt TF3LEN TSSPLIT TSXCLK
150. time after the RENO Receive Enable bit SCONO 4 is set to logic 1 After the stop bit is received the data byte will be stored in the receive FIFO if the following conditions are met the receive FIFO 3 bytes deep must not be full and the stop bit s must be logic 1 In the event that the receive FIFO is full the incoming byte will be lost and a Receive FIFO Overrun Error will be generated OVRO in register SCONO will be set to logic 1 If the stop bit s were logic 0 the incoming data will not be stored in the receive FIFO If the reception conditions are met the data is stored in the receive FIFO and the RIO flag will be set Note when MCEO 1 RIO will only be set if the extra bit was equal to 1 Data can be read from the receive FIFO by reading the SBUFO register The SBUFO register represents the oldest byte in the FIFO After SBUFO is read the next byte in the FIFO is immediately loaded into SBUFO and space is made available in the FIFO for another incoming byte If enabled an interrupt will occur when RIO 259 Rev 1 3 SILICON LABS 8051 58 59 is set RIO only be cleared to 0 by software when there is no more information in the FIFO The recom mended procedure to empty the FIFO contents is as follows 1 Clear RIO to 0 2 Read SBUFO 3 Check RIO and repeat starting at step 1 if RIO is set to 1 If the extra bit function is enabled XBEO 1 and the parity function is disabled PEO 0 the extr
151. to A and jump if not equal 3 3 6 8 CJNE Rn rel Compare immediate to Register and jump if not 3 3 5 7 equal CJNE Ri data rel Compare immediate to indirect and jump if not 3 4 6 8 equal DJNZ rel Decrement Register and jump if not zero 2 2 4 6 DJNZ direct rel Decrement direct byte and jump if not zero 3 3 5 7 NOP No operation 1 1 Note Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the FLRT setting SFR Definition 15 3 96 Rev 1 3 SILICON LABS 8051 58 59 Notes on Registers Operands and Addressing Modes Rn Register RO R7 of the currently selected register bank Ri Data RAM location addressed indirectly through RO or R1 rel 8 bit signed two s complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be direct access Data RAM location 0 00 Ox7F or an SFR 0 80 0 data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 kB page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destination may be anywhere within the 64 kB program memory space There is o
152. to the Flash memory See Section 15 Flash Memory on page 138 for details The instruction accesses XRAM by default 18 1 Accessing XRAM The XRAM memory space is accessed using the MOVX instruction The MOVX instruction has two forms both of which use an indirect addressing method The first method uses the Data Pointer DPTR a 16 bit register which contains the effective address of the XRAM location to be read from or written to The sec ond method uses RO or R1 in combination with the EMIOCN register to generate the effective XRAM address Examples of both of these methods are given below 18 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A MOV DPTR 1234h load DPTR with 16 bit address to read 0x1234 MOVX A DPTR load contents of 0x1234 into accumulator A The above example uses the 16 bit immediate MOV instruction to set the contents of DPTR Alternately the DPTR can be accessed through the SFR registers DPH which contains the upper 8 bits of DPTR and DPL which contains the lower 8 bits of DPTR 18 1 2 8 Bit MOVX Example The 8 bit form of the MOVX instruction uses the contents of the EMIOCN SFR to determine the upper 8 bits of the effective address to be accessed and the contents of RO or R1 to determine the l
153. transferred to or from the message object in CAN RAM 3 Message Handler Registers These read only registers are used to provide information to the CIP 51 MCU about the message objects MSGVLD flags Transmission Request Pending New Data Flags and Interrupts Pending which Message Objects have caused an interrupt or status interrupt condition For the registers other than CANOCFG refer to the Bosch CAN User s Guide for information on the func tion and use of the CAN Control Protocol Registers 22 2 1 CAN Controller Protocol Registers The CAN Control Protocol Registers are used to configure the CAN controller process interrupts monitor bus status and place the controller in test modes The registers are CAN Control Register CANOCN CAN Clock Configuration CANOCFG CAN Status Register CANOSTA CAN Test Register CANOTST Error Counter Register Bit Timing Register and the Baud Rate Prescaler BRP Extension Register 22 2 2 Message Object Interface Registers There are two sets of Message Object Interface Registers used to configure the 32 Message Objects that transmit and receive data to and from the CAN bus Message objects can be configured for transmit or receive and are assigned arbitration message identifiers for acceptance filtering by all CAN nodes Message Objects are stored in Message RAM and are accessed and configured using the Message Object Interface Registers 22 2 3 Message Handler Registers The Message
154. up or down Capture mode and Auto Reload mode are selected using bits in the Timer4 and 5 Control registers TMRnCN Toggle Output mode is selected using the Timer 4 and 5 Configuration registers TMRnCF These timers may also be used to generate a square wave at an external pin As with Timers 0 and 1 Timers 4 and 5 can use either the system clock divided by one two or twelve external clock divided by eight or transitions on an external input pin as its clock source The Counter Timer Select bit CTn bit TMRnCN 1 configures the peripheral as a counter or timer Clearing CTn to 0 configures the Timer to be in a timer mode i e the system clock or transitions on an external pin as the input for the timer When CTn is set to 1 the timer is configured as a counter i e high to low tran sitions at the Tn input pin increment or decrement the counter timer register Refer to Section 20 4 Port Initialization on page 195 for information on selecting and configuring external I O pins for digital peripherals such as the Tn pin The Timers can use either SYSCLK SYSCLK divided by 2 SYSCLK divided by 12 an external clock divided by 8 or high to low transitions on the Tn input pin as its clock source when operating in Counter Timer with Capture mode Clearing the CTn bit TMRnCN 1 selects the system clock external clock as the input for the timer The Timer Clock Select bits and TnM1 in TMRnCF can be used to select the sys
155. 0 Bit Name Function 7 REGDIS Voltage Regulator Disable Bit 0 Voltage Regulator Enabled 1 Voltage Regulator Disabled 6 Reserved Read 1b Must Write 1b 5 Unused Read 0b Write Don t Care 4 REGOMD _ Voltage Regulator Mode Select Bit 0 Voltage Regulator Output is 2 1V 1 Voltage Regulator Output is 2 6V 3 1 Unused Read 000b Write Don t Care 0 DROPOUT Voltage Regulator Dropout Indicator 0 Voltage Regulator is not in dropout 1 Voltage Regulator is in or near dropout 90 Rev 1 3 SILICON LABS 8051 58 59 11 CIP 51 Microcontroller The MCU system controller core is the CIP 51 microcontroller The CIP 51 is fully compatible with the MCS 51 instruction set standard 803x 805x assemblers and compilers can be used to develop soft ware The MCU family has a superset of all the peripherals included with a standard 8051 The CIP 51 also includes on chip debug hardware see description in C2 Interface on page 351 and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control system solution in a single integrated circuit The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 11 1 for a block diagram The CIP 51 includes the following features Fully Compatible with MCS
156. 0 0 0 SFR Addresses PCAOCPLO OxFB PCAOCPL1 OxE9 PCAOCPL2 OxEB OxED PCAOCPLA OxFD PCAOCPL5 OxCE SFR Page all registers 0x00 Bit Name Function 7 0 PCAOCPn 7 0 PCAO Capture Module Low Byte The PCAOCPLn register holds the low byte LSB of the 16 bit capture module n This register address also allows access to the low byte of the corresponding channel s auto reload value for 9 10 or 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed Note A write to this register will clear the module s bit to a 0 SFR Definition 28 8 PCAO Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCAOCPn 15 8 RW R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addresses OxFC PCAOCPH1 OxEA PCAOCPH2 OxEC PCAOCPHS OxEE PCAOCPH4 OxFE PCAOCPH5 OxCF SFR Page all registers 0x00 Bit Name Function 7 0 PCAOCPn 15 8 Capture Module High Byte The PCAOCPHn register holds the high byte MSB of the 16 bit capture module n This register address also allows access to the high byte of the corresponding PCAO channel s auto reload value for 9 10 or 11 bit PWM mode The ARSEL bit in register PCAOPWM controls which register is accessed Not
157. 0 0 0 0 0 TMR4H SFR Address 0xCD TMR5H SFR Address 0x95 SFR Page 0x10 Bit Name Function 7 0 TMRnH 7 0 Timer n High Byte In 16 bit mode the TMRnH register contains the high byte of the 16 bit Timer n In 8 bit mode TMRnH contains the 8 bit high byte timer value Rev 1 3 313 SILICON LABS 8051 58 59 28 Programmable Counter Array 0 The Programmable Counter Array PCAO provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter timers PCAO consists of a dedicated 16 bit counter timer and six 16 bit capture compare modules Each capture compare module has its own associated line CEXn which is routed through the Crossbar to Port when enabled The counter timer is driven by a programmable timebase that can select between eight sources system clock system clock divided by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 4 or 5 over flows or an external clock signal on the ECI input pin Each capture compare module may be configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 to 11 Bit PWM or 16 Bit PWM each mode is described in Section 28 3 Capture Compare Modules on page 317 The external oscillator clock option is ideal for real time clock RTC functionality
158. 0 MHz 20 MHz 0 46 2 7 2 mA Idle IDD can be estimated for frequencies lt 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Idle Ipp for gt 1 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V F 5 MHz Idle Ipp 19 mA 50 MHz 5 MHz x 0 38 mA MHz 1 9 mA Rev 1 3 44 SILICON LABS 8051 58 59 Table 5 2 Global Electrical Characteristics Continued 40 to 125 C 24 MHz system clock unless otherwise specified Parameter Conditions Min Typ Max Digital Supply Current CPU Inactive Idle Mode not fetching instructions from Flash Vpp 2 1 V F 200 kHz 130 Vpp 2 1 V 1 5 MHz 440 2 1 V 25 MHz 5 8 Vpp 2 1 V 50 MHz 11 Vpp 2 6 V F 200 kHz 2 6 V 1 5 MHz Vpp 2 6 V F 25 MHz Vpp 2 6 V F 50 MHz 1 4 Supply Sensitivity F 25 MHz F 1 MHz Ipp Frequency Sensitivity 9 Vpp 2 1V F lt 12 5 MHz T 25 Vpp 2 1V gt 12 5 MHz T 25 Vpp 2 6V lt 12 5 MHz T 25 Vpp 2 6V F gt 12 5 MHz T 25 Digital Supply Current Oscillator not running Stop or Suspend Mode Vpp Monitor Disabled Temp 25 Temp 60 Temp 125
159. 000 P0 0 0001 P0 2 0010 P0 4 0011 P0 6 0100 P1 0 0101 P1 2 0110 P1 4 0111 P1 6 1000 P2 0 1001 P2 2 1010 P2 4 1011 P2 6 1100 1111 Rev 1 3 87 SILICON LABS 8051 58 59 SFR Definition 9 9 CPT2MX Comparator2 MUX Selection Bit 7 6 5 4 3 2 1 0 Name CMX2N 3 0 2 3 0 R W R W Reset 0 1 1 1 0 1 1 1 SFR Address 0x9C SFR Page 0x10 Bit Name Function 7 4 CMX2N 3 0 Comparator2 Negative Input MUX Selection 0000 PO 1 0001 P0 3 0010 P0 5 0011 7 0100 1 1 0101 P1 3 0110 P1 5 0111 P1 7 1000 P2 1 1001 P2 3 1010 P2 5 1011 P2 7 1100 1111 3 0 CMX2P 3 0 Comparator2 Positive Input MUX Selection 0000 P0 0 0001 P0 2 0010 P0 4 0011 P0 6 0100 P1 0 0101 P1 2 0110 P1 4 0111 P1 6 1000 P2 0 1001 P2 2 1010 P2 4 1011 P2 6 1100 1111 88 Rev 1 3 SILICON LABS 8051 58 59 10 Voltage Regulator REGO C8051F58x F59x devices include an on chip low dropout voltage regulator REGO The input to REGO at the Vregin pin can be as high as 5 25 V The output can be selected by software to 2 1 V or 2 6 V When enabled the output of REGO appears on the Vpp pin powers the microcontroller core and can be used to power external devices On reset REGO is enabled and can be disabled by software The Voltage regulator can generate a
160. 051 58 59 22 Controller Area Network CANO Important Documentation Note The Bosch CAN Controller is integrated in the C8051F580 2 4 6 8 F590 devices This section of the data sheet gives a description of the CAN controller as an overview and offers a description of how the Silicon Labs CIP 51 MCU interfaces with the on chip Bosch CAN controller In order to use the CAN controller refer to Bosch s C_CAN User s Manual as an accompanying manual to the Silicon Labs data sheet The C8051 F580 2 4 6 8 F590 devices feature a Control Area Network CAN controller that enables serial communication using the CAN protocol Silicon Labs CAN facilitates communication on a CAN network in accordance with the Bosch specification 2 0A basic CAN and 2 0B full CAN The CAN controller con sists of a CAN Core Message RAM separate from the CIP 51 RAM a message handler state machine and control registers Silicon Labs CAN is a protocol controller and does not provide physical layer drivers i e transceivers Figure 22 1 shows an example typical configuration on a CAN bus Silicon Labs CAN operates at bit rates of up to 1 Mbit second though this can be limited by the physical layer chosen to transmit data on the CAN bus The CAN processor has 32 Message Objects that can be configured to transmit or receive data Incoming data message objects and their identifier masks are stored in the CAN message RAM All protocol functions for transmissio
161. 051 58 59 SFR Definition 25 2 SBUF1 Serial UART1 Port Data Buffer Bit 7 6 5 4 3 1 0 Name SBUF1 7 0 Reset 0 0 0 0 0 0 0 SFR Address 0x99 SFR Page 0x10 Bit Name Function 7 0 SBUF1 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUF1 it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUF1 initiates the transmission A read of SBUF1 returns the contents of the receive latch 270 Rev 1 3 SILICON LABS 8051 58 59 Table 25 1 Timer Settings for Standard Baud Rates Using The Internal 24 MHz Oscillator Target Baud Rate Oscilla i A1 SCAO 1 limer1 Baud Rate Error tor Divide Source pre scale Reload bps Factor select Value hex 230400 SYSCLK 115200 SYSCLK 57600 SYSCLK 28800 SYSCLK 4 14400 SYSCLK 12 9600 SYSCLK 12 2400 SYSCLK 48 1200 SYSCLK 48 Oo 20 xo E V S Notes 0 SCA1 SCAO0 and T1M bit definitions can be found in Section 27 1 2 X Don t care Rev 1 3 271 SILICON LABS 8051 58 59 26 Enhanced Serial Peripheral Interface SPIO The Enhanced Serial Peripheral Interface SPIO provides access to a flexible full duplex syn
162. 1 Note and 1 fully independent peripherals PCAO offers channels CEXO CEX5 and PCA1 offers channels 6 11 and 1 are identical except that PCAO Module 5 may be used as a watchdog timer SYSCLK 12 SYSCLK 4 Timer 0 Overflow SYSCLK External Clock 8 Timer 4 Overflow b 16 Bit Counter Timer Timer 5 Overflow Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Module 6 Module 7 Module 8 Module 9 Module 10 Module 11 9 9 Q i 9 N 5 zi Crossbar Port 2 1 Figure 29 1 1 Block Diagram Rev 1 3 333 SILICON LABS 8051 58 59 29 1 1 Counter Timer The 16 bit PCA1 counter timer consists of two 8 bit SFRs PCA1L and PCA1H 1 is the high byte MSB of the 16 bit counter timer and is the low byte LSB Reading PCA1L automatically latches the value of PCA1H into a snapshot register the following PCA1H read accesses this snapshot register Reading the PCA1L Register first guarantees an accurate reading of the entire 16 bit PCA1 counter Reading PCA1H or PCA1L does not disturb the counter operation The CPS12 CPS10 bits in the PCA1MD register select the timebase for the counter timer as shown in Table 29 1 When the counter timer ove
163. 1 Name POSKIP 7 0 Type R W Reset 0 0 0 0 0 0 0 SFR Address 0xD4 SFR Page OxOF Bit Name Function 7 0 POSKIP 7 0 Port 0 Crossbar Skip Enable Bits SFR Definition 20 17 P1 Port 1 Sets the Port latch logic value or reads the Port pin logic state in Port cells con figured for digital I O LOW 1 Set output latch to logic HIGH LOW HIGH Bit 7 6 5 4 3 2 1 Name P1 7 0 Type R W Reset 1 1 1 1 1 1 1 SFR Address 0x90 SFR Page All Pages Bit Addressable Bit Name Description Write Read 7 0 1 7 0 Port 1 Data 0 Set output latch to logic 0 P1 n Port is logic 1 P1 n Port pin is logic SILICON LABS Rev 1 3 206 8051 58 59 SFR Definition 20 18 P1MDIN Port 1 Input Mode Bit 7 6 5 4 3 2 1 0 Name P1MDIN 7 0 Reset 1 1 1 1 1 1 1 1 SFR Address OxF2 SFR Page OxOF Bit Name Function 7 0 P1MDIN 7 0 Analog Configuration Bits for P1 7 P1 0 respectively Port pins configured for analog mode have their weak pull up and digital receiver disabled For analog mode the pin also needs to be configured for open drain mode in the P1MDOUT register 0 Corresponding P1 n pin is configured for analog mode 1 Corresponding P1 n pin is not configured for analog mode SFR Definition 20 19 P1MDOUT Port 1 O
164. 1 setting the PSWE Program Store Write Enable bit PSCTL O to logic 1 this directs the MOVX writes to target Flash memory and 2 Writing the Flash key codes in sequence to the Flash Lock register FLKEY The PSWE bit remains set until cleared by software A write to Flash memory can clear bits to logic 0 but cannot set them only an erase operation can set bits to logic 1 in Flash A byte location to be programmed should be erased before a new value is written The Flash memory is organized in 512 byte pages The erase operation applies to an entire page setting all bytes in the page to OxFF To erase an entire 512 byte page perform the following steps 1 Disable interrupts recommended 2 If erasing page in Banks 1 2 or 3 set the COBANK 1 0 bits register PSBANK for the appropriate bank Set the FLEWT bit register FLSCL Set the PSEE bit register PSCTL Set the PSWE bit register PSCTL Write the first key code to FLKEY OxA5 Write the second key code to FLKEY OxF1 Using the instruction write a data byte to any location within the 512 byte page to be erased Clear the PSWE and PSEE bits 15 1 4 Flash Write Procedure Flash bytes are programmed by software with the following sequence OMNAAR 1 Disable interrupts recommended 2 If writing to an address in Banks 1 2 or 3 set the COBANK 1 0 register PSBANK for the appropriate bank 3 Erase the 512 byte Flash page containing the
165. 1 PWM Configuration 347 PCON 0x87 Power Control 151 PSBANK OxF5 Program Space Bank Select 104 PSCTL Ox8F Program Store R W Control 145 PSW OxDO Program Status Word 100 REFOCN OxD1 Voltage Reference Control 76 REGOCN 0 01 Voltage Regulator Control 90 RSTSRC OxEF Reset Source Configuration Status 157 SBCONO UARTO Baud Rate Generator Control 263 SBRLHO OxAD UARTO Baud Rate Reload High Byte 264 SBRLLO OxAC UARTO Baud Rate Reload Low Byte 264 SBUFO 0x99 UARTO Data Buffer 263 SCONO 0x98 UARTO Control 261 SBUF1 0x99 UART1 Data Buffer 270 SCON1 0x98 UART1 Control 269 SFROCN 0x84 SFR Page Control 113 SFRLAST 0x86 SFR Stack Last Page 116 SFRNEXT 0x85 SFR Stack Next Page 115 SFRPAGE OxA7 SFR Page Select 114 SMBOCF OxC1 5 50 Configuration 245 SMBOCN 0xCO SMBus0 Control 247 SMBODAT 0xC2 SMBus0 Data 249 SMODO OxA9 UARTO Mode 262 SNO OxF9 Serial Number 0 101 SN1 OxFA Serial Number 1 101 SN2 OxFB Serial Number 2 101 123 Rev 1 3 SILICON LABS 8051 58 59 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page SN3 OxFC Serial Number 3 101 SP 0x81 Stack Pointer 99 SPIOCFG OxA1 SPIO Configuration 279 SPIOCKR 2 SPIO Clock Rate Control 281 SPIOCN OxF8 SPIO Control 280 SPIODAT SPIO Data 281 T
166. 19 4 2 External RC Example If an RC network is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 19 1 Option 2 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To deter mine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register first select the RC network value to produce the desired frequency of oscillation according to Equation where f the frequency of oscillation in MHz C the capacitor value in pF and the pull up resistor value in f 1 23x 10 RxC Equation 19 1 RC Mode Oscillator Frequency For example If the frequency desired is 100 kHz let 246 and C 50 pF f 1 23 103 1 23 103 246 x 50 0 1 MHz 100 kHz Referring to the table in SFR Definition 19 6 the required XFCN setting is 010b 19 4 3 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 19 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register select the capaci tor to be used and find the frequency of oscillation accordin
167. 2 FLKEY Flash Lock and Key 144 SFR Definition 15 3 FLSCL Flash Scale nd it 145 Rev 1 3 14 SILICON LABS C8051F58x F59x SFR Definition 15 4 SFR Definition 15 5 SFR Definition 16 1 SFR Definition 17 1 SFR Definition 17 2 SFR Definition 18 1 SFR Definition 18 2 SFR Definition 18 3 SFR Definition 19 1 SFR Definition 19 2 SFR Definition 19 3 SFR Definition 19 4 SFR Definition 19 5 SFR Definition 19 6 SFR Definition 20 1 SFR Definition 20 2 SFR Definition 20 3 SFR Definition 20 4 SFR Definition 20 5 SFR Definition 20 6 SFR Definition 20 7 SFR Definition 20 8 SFR Definition 20 9 SFR Definition 20 10 SFR Definition 20 11 SFR Definition 20 12 SFR Definition 20 13 SFR Definition 20 14 SFR Definition 20 15 SFR Definition 20 16 SFR Definition 20 17 SFR Definition 20 18 CCHOON Cache 146 ONESHOT Flash Oneshot Period 146 PCGON PoWer Control e px aes eat eto usus mete 149 VDMOCN VDD Monitor Control 153 RSTSRC Reset Source 155 EMIOCN External Memory Interface Control 160 EMIOCF External Memory Configuration 161 EMIOTC External Memory Timing Control
168. 2 SBRLHO UARTO Baud Rate Generator Reload High Byte 262 Serial Port 1 Control 2 267 SBUF1 Serial UART1 Port Data Buffer 268 SPIOCFG SPIO Configuration 277 SPIOCN SPIO Control 278 SPIOCKR SPIO Clock 279 SPIODAT SPI0 Data M Ei IS 279 CKCON Clock Control 284 TCON Timer 0 200 nennen 289 TMOD Timer Mode e 290 TLO Timer 0 Low Byte 291 TL1 Timer 291 THO Timer 0 High Byte 292 Timer 1 High Byte tetra 292 SFR Definition 27 8 TMR2CN Timer 2 296 SFR Definition 27 9 TMR2RLL Timer 2 Reload Register Low Byte 297 SFR Definition 27 10 TMR2RLH Timer 2 Reload Register High Byte 297 SFR Definition 27 11 TMR2L Timer 2 Low Byte 2 2 2 298 SFR Definition 27 12 TMR2H Timer 2 High Byte 42222 1 298 SFR Definition 27 13 Timer Control 302 SFR Definition 27 14 TMR3RLL Timer Reload Register Low Byte 303 SFR Definitio
169. 22 3h moves the Boolean value at 0x13 bit 3 of the byte at location 0x22 into the Carry flag 12 2 1 3 Stack A programmer s stack can be located anywhere in the 256 byte data memory The stack area is desig nated using the Stack Pointer SP SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremented A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also the first regis ter RO of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes 105 Rev 1 3 SILICON LABS 8051 58 59 13 Special Function Registers direct access data memory locations from 0 80 to OxFF constitute the special function registers SFRs The SFRs provide control and data exchange with the C8051F58x F59x s resources and peripher als The CIP 51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub systems unique to the C8051F58x F59x This allows the addition of new functionality while retaining compatibility with the MCS 51 instruction set Table 13 3 lists the SFRs implemented in the C8051F58x F59x device family The SFR registers are a
170. 24 5 CP2102 USB to UART C8051 Fxxx Bridge m TX TX MCU gt C8051Fxxx RX RX Figure 24 5 Typical UART Interconnect Diagram 24 3 1 Data Transmission Data transmission begins when software writes a data byte to the SBUFO register The TIO Transmit Inter rupt Flag SCONO 1 will be set at the end of any transmission the beginning of the stop bit time If enabled an interrupt will occur when TIO is set Note THREO can have a momentary glitch high when the UART Transmit Holding Register is not empty The glitch will occur some time after SBUFO was written with the previous byte and does not occur if THRE is checked in the instruction s immediately following the write to SBUFO When firmware writes SBUFO and SBUFO is not empty TXO will be stuck low until the next device reset Firmware should use or poll on TIO rather than THREO for asynchronous UART writes that may have a random delay in between transactions If the extra bit function is enabled XBEO 1 and the parity function is disabled PEO 0 the value of the SCONO 3 bit will be sent in the extra bit position When the parity function is enabled PEO 1 hardware will generate the parity bit according to the selected parity type selected with SOPT 1 0 and append it to the data field Note when parity is enabled the extra bit function is not available 24 3 2 Data Reception Data reception can begin any
171. 3 2 1 0 Name LINEN MODE ABAUD Type R W R W R W R R R R R Reset 0 1 1 0 0 0 0 0 SFR Address 0xC9 SFR Page 0x0F Bit Name Function 7 LINEN LIN Interface Enable Bit 0 LINO is disabled 1 LINO is enabled 6 MODE LIN Mode Selection Bit 0 LINO operates in slave mode 1 LINO operates in master mode 5 ABAUD LIN Mode Automatic Baud Rate Selection This bit only has an effect when the MODE bit is configured for slave mode 0 Manual baud rate selection is enabled 1 Automatic baud rate selection is enabled 4 0 Unused Read 00000b Write Don t Care SILICON LABS Rev 1 3 222 C8051F58x F59x 21 7 2 LIN Indirect Access SFR Registers Definitions Table 21 4 lists the 15 indirect registers used to configured and communicate with the LIN controller Table 21 4 LIN Registers Indirectly Addressable Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 BitO LINODT1 DATA1 7 0 LINODT2 0x01 DATA2 7 0 LINODT3 0x02 DATA3 7 0 LINODT4 0x03 DATA4 7 0 LINODT5 0x04 DATAS 7 0 LINODT6 0x05 DATA67 0 LINODT7 0x06 DATA7 7 0 LINODT8 0x07 DATAS 7 0 LINOCTRL 0x08 STOP s SLEEP s TXRX DTACK s RSTINT RSTERR WUPREQ STREQ m LINOST 0x09 ACTIVE IDLTOUT ABORT s DTREQ s LININT ERROR WAKEUP DONE LINOERR Ox0A SYNCH s PRTY s TOUT CHK BITERR LINOSIZE 0x0B ENHCHK LINSIZE 3
172. 3 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 13 2 SFRPAGE SFR Page Bit 7 6 5 4 3 2 1 0 Name SFRPAGE 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA7 SFR Page All Pages Bit Name Function 7 0 SFRPAGE 7 0 SFR Page Bits Represents the SFR Page the C8051 core uses when reading or modifying SFRs Write Sets the SFR Page Read Byte is the SFR page the C8051 core is using When enabled in the SFR Page Control Register SFROCN the C8051 core will automatically switch to the SFR Page that contains the SFRs of the correspond ing peripheral function that caused the interrupt and return to the previous SFR page upon return from interrupt unless SFR Stack was altered before a return ing from the interrupt SFRPAGE is the top byte of the SFR Page Stack and push pop events of this stack are caused by interrupts and not by reading writ ing to the SFRPAGE register SILICON LABS Rev 1 3 114 8051 58 59 SFR Definition 13 3 5 SFR Next Bit 7 6 5 4 3 2 1 0 Name SFRNEXT 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0x85 SFR Page All Pages Bit Name Function 7 0 SFRNEXT 7 0 SFR Page Bits This is the value that will go to the SFR Page register upon a return from inter rupt Write Sets t
173. 8x F59x 21 7 LIN Registers The following Special Function Registers SFRs and indirect registers are available for the LIN controller 21 7 1 LIN Direct Access SFR Registers Definitions SFR Definition 21 1 LINOADR LINO Indirect Address Register Bit 7 6 5 4 3 2 1 0 Name LINOADR 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD3 SFR Page 0x00 Bit Name Function 7 0 LINOADR 7 0 LIN Indirect Address Register Bits This register hold an 8 bit address used to indirectly access the LINO core registers Table 21 4 lists the LINO core registers and their indirect addresses Reads and writes to LINODAT will target the register indicated by the LINOADR bits SFR Definition 21 2 LINODAT LINO Indirect Data Register Bit 7 6 5 4 3 2 1 0 Name LINODAT 7 0 Reset 0 0 0 0 0 SFR Address 0xD2 SFR Page 0x00 Bit Name Function 7 0 LINODAT 7 0 LIN Indirect Data Register Bits When this register is read it will read the contents of the LINO core register pointed to by LINOADR When this register is written it will write the value to the LINO core register pointed to by LINOADR 221 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 21 3 LINOCF LINO Control Mode Register Bit 7 6 5 4
174. 98 P0 4 UARTO TX 787 PO 5 UARTO RX 36 6 CANTX 28 P0 7 CAN RX 34 10 32 12 eee 64 4 ee ee ee 44 4 4 4 C 9 1 CNVSTR P1 4 LLL LLL a LLL VIO P1 5 esse m C8051F588 IM p VDD putt 8051 589 1 eR C8051F590 IM is GND 6 8051 591 MCN P2 1 GNDA Top View 24 P2 2 VREGIN P1 6 1 7 P0 0 VREF P2 3 DLL OL Z 1C k1C1lLLLIL A10 D ELLEN LL P4 0 C2D P2 4 RST C2CK P2 5 oo o Le oo s B B iew P3 0 18 x Q T S See PP L Figure 3 3 QFN 40 Pinout Diagram Top lt 29 Rev 1 3 SILICON LABS 8051 58 59 0 4 UARTO TX 1 0 P1 1 EJ P0 5 UARTO RX P0 1 CNVSTR VIO VREGIN C8051F582 IQ yan C8051F583 IQ C8051F586 IQ C8051F587 IQ GND 6 Top View P0 0 VREF 8 8 E amp Figure 3 4 QFP 32 Pinout Diagram Top View RST C2CK P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 Rev 1 3 SILICON LABS 30 8051 58 59 P03 XTAL2 _30 P0 4 UARTO TX _29 P0 5 UARTO RX 28 0 6 _27 P07 CAN RX 232 P02 XTAL1 LLLI LLLLLLLLLLLLLLLLIIT TO III T LtL P0 1 CNVSTR Fo EE s s D EAA
175. 9x 21 4 LIN Slave Mode Operation 2 20222000000 0 000000000000 217 21 5 Sleep Mode and 0 218 21 6 Error Detection and Handling pen ten ten SER gun Ux tok Eee Ec tct 218 21 7 LIN Registe rs u 219 21 7 1 LIN Direct Access SFR Registers Definitions 219 21 7 2 LIN Indirect Access SFR Registers Definitions 221 22 Controller Area Network CANO0 J J J 229 22 1 Bosch CAN Controller Operation 230 22 1 1 CAN Controller Timing auseinander bebe prebuit 230 22 1 2 CAN Register s tue uU ES 231 22 1 3 Example Timing Calculation for 1 Mbit Sec Communication 231 22 2 CAN PBOOISIBIS usan 233 22 2 1 CAN Controller Protocol 233 22 2 2 Message Object Interface 233 22 2 3 Message Handler Registers 233 22 2 4 CAN Register 234 29 SMBUS u Su Sus M DUUM DUE 237 23 1 Supporting Documents MR UU S 238
176. ADCOLTH ADCOLTL 0x0200 512d and ADCOGTH ADCOGTL 0x0100 256d The input voltage can range from 0 to x 4095 4096 with respect to GND and is represented by a 12 bit unsigned integer value The repeat count is set to one In the left example an ADOWINT interrupt will be generated if the ADCO conversion word ADCOH ADCOL is within the range defined by ADCOGTH ADCOGTL and ADCOLTH ADCOLTL if 0x0100 lt ADCOH ADCOL lt 0x0200 In the right example and ADOWINT interrupt will be generated if the ADCO conversion word is outside of the range defined by the ADCOGT and ADCOLT registers if ADCOH ADCOL lt 0x0100 or ADCOH ADCOL gt 0x0200 Figure 6 7 shows an exam ple using left justified data with the same comparison values Rev 1 3 70 SILICON LABS 8051 58 59 ADCOH ADCOL Input Voltage Px x GND VREF x 4095 4096 OxOFFF ADOWINT not affected 0x0201 0x0200 4 ADCOLTH ADCOLTL VREF x 512 4096 ADOWINT 1 VREF x 256 4096 0x0100 ADCOGTH ADCOGTL 0x00FF AD0WINT not affected 0 0x0000 ADC0H ADC0L Input Voltage Px x GND VREF x 1023 1024 AD0WINT 1 VREFx 512 4096 0x0200 lt ADCOGTH ADCOGTL ADOWINT 0 0101 not affected x 256 4096 0x0100 ADCOLTH ADCOLTL ADOWINT 1 Figure 6 6 ADC Window Compare Example Right Justified Data ADCOH ADCOL Input Vol
177. AM FLASH INTERNAL DATA ADDRESS SPACE C8051 F580 1 2 3 8 9 OxFF z 1 Upper 128 RAM Special Function Indirect Addressing Register s 0x1FC00 0x80 Only Direct Addressing Only Ox1FBFF Ox7F Direct and Indirect Addressing Lower 128 RAM Direct and Indirect Addressing 128 kB FLASH 0x30 In System 0 2 Programmable in 512 0x20 Byte Sectors Ox1F 0x00 0x00000 EXTERNAL DATA ADDRESS SPACE OxFFFF C8051 F584 5 6 7 F590 1 Ox17FFF 0x2000 96 kB FLASH Ox1EFE In System XRAM Programmable in 512 Byte Sectors 8K Bytes accessable using MOVX instruction 0x00000 0x0000 Figure 12 1 C8051F58x F59x Memory Map 12 1 Program Memory The C8051F580 1 2 3 8 9 devices have a 128 kB program memory space and the C8051F584 5 6 7 F590 1 devices have 96 kB program memory space The MCU implements this program memory space as in system re programmable Flash memory in either four or three 32 kB code banks common code bank Bank 0 of 32 kB is always accessible from addresses 0x0000 to 0x7FFF The three or two upper code banks Bank 1 Bank 2 and Bank 3 are each mapped to addresses 0x8000 to 0xFFFF depending on the selection of bits in the PSBANK register as described in SFR Definition 12 1 Rev 1 3 102 SILICON LABS C8051F58x F59x The IFBANK bits select which of the upper banks are used for code execution while the COBANK bits select the bank to be used for direct writes and
178. APL captures the low byte of Timer 4 and 5 when Timer 4 and 5 are con figured in capture mode When Timer 4 and 5 are configured in auto reload mode it holds the low byte of the reload value SFR Definition 27 21 TMRnCAPH Timer 4 and 5 Capture Register High Byte Bit 7 6 5 4 3 2 1 0 TMRnRLH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 TMR4CAPH SFR Address 0xCB TMR5CAPH SFR Address 0x93 SFR Page 0x10 Bit Name Function 7 0 TMRnCAPH 7 0 Timer n Reload Register High Byte TMRnCAPH captures the high byte of Timer 4 and 5 when Timer 4 and 5 are configured in capture mode When Timer 4 and 5 are configured in auto reload mode it holds the high byte of the reload value 312 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 27 22 TMRnL Timer 4 5 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMRnL 7 0 Reset 0 0 0 0 0 0 0 0 TMR4L SFR Address 0xCC TMR5L SFR Address 0x94 SFR Page 0x10 Bit Name Function 7 0 TMRnL 7 0 Timer n Low Byte In 16 bit mode the TMRnL register contains the low byte of the 16 bit Timer n In 8 bit mode TMRnL contains the 8 bit low byte timer value SFR Definition 27 23 TMRnH Timer 4 and 5 High Byte Bit 7 6 5 4 3 2 1 0 TMRnH 7 0 Type R W Reset 0 0 0
179. AT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA3 SFR Page 0x00 Bit Name Function 7 0 SPIODAT 7 0 SPIO Transmit and Receive Data The SPIODAT register is used to transmit and receive SPIO data Writing data to SPIODAT places the data into the transmit buffer and initiates a transfer when in Master Mode A read of SPIODAT returns the contents of the receive buffer 281 Rev 1 3 SILICON LABS 8051 58 59 7 is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 26 8 SPI Master Timing CKPHA 0 SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 26 9 SPI Master Timing CKPHA 1 Rev 1 3 282 SILICON LABS 8051 58 59 MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 26 10 SPI Slave Timing CKPHA 0 Tse gt gt gt T 6 gt J Tos phe gt SEZ SOH soz gt MOSI T SEZ gt is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 26 11 SPI Slave Timing CKPHA 1 T SLH gt gt 502 283 Rev 1 3 SILICON LABS 8051 58 59 Table 26 1 SPI Slave Timing Parameters
180. BS 8051 58 59 16 Power Management Modes The C8051 F58x F59x devices have three software programmable power management modes Idle Stop and Suspend Idle mode and Stop mode are part of the standard 8051 architecture while Suspend mode is an enhanced power saving mode implemented by the high speed oscillator peripheral Idle mode halts the CPU while leaving the peripherals and clocks active In Stop mode the CPU is halted all interrupts and timers except the Missing Clock Detector are inactive and the internal oscillator is stopped analog peripherals remain in their selected states the external oscillator is not affected Sus pend mode is similar to Stop mode in that the internal oscillator and CPU are halted but the device can wake on events such as a Port Match or Comparator low output Since clocks are running in Idle mode power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle Stop mode and Suspend mode consume the least power because the majority of the device is shut down with no clocks active SFR Definition 16 1 describes the Power Control Register PCON used to control the C8051F58x F59x devices Stop and Idle power management modes Suspend mode is controlled by the SUSPEND bit in the OSCICN register SFR Definition 19 2 Although the C8051 F58x F59x has Idle Stop and Suspend modes available more control over the device power can
181. Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer 0 Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 low byte uses the system clock 3 T1 Timer 1 Clock Select Selects the clock source supplied to Timer 1 Ignored when C T1 is set to 1 0 Timer 1 uses the clock defined by the prescale bits SCA 1 0 1 Timer 1 uses the system clock 2 TO Timer 0 Clock Select Selects the clock source supplied to Timer 0 Ignored when C TO is set to 1 0 Counter Timer 0 uses the clock defined by the prescale bits SCA 1 0 1 Counter Timer 0 uses the system clock 1 0 SCA 1 0 Timer 0 1 Prescale Bits These bits control the Timer 0 1 Clock Prescaler 00 System clock divided by 12 01 System clock divided by 4 10 System clock divided by 48 11 External clock divided by 8 synchronized with the system clock 286 Rev 1 3 SILICON LABS 8051 58 59 27 1 Timer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate bytes a low byte TLO or TL1 and a high byte THO or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the ETO bit in the IE regis ter Section 14 2 Interrupt Register Descriptions on page 129 Timer 1 interrupts can be enabled by set
182. C Idle T G Idle ADOEN 1 Dual Tracking ADOTM 11 Track T C Track T C Track ADOEN 1 T Tracking C Converting Figure 6 4 12 Bit ADC Burst Mode Example With Repeat Count Set to 4 Rev 1 3 58 SILICON LABS 8051 58 59 6 2 Output Code Formatting The registers ADCOH and ADCOL contain the high and low bytes of the output conversion code When the repeat count is set to 1 conversion codes are represented in 12 bit unsigned integer format and the output conversion code is updated after each conversion Inputs are measured from 0 to Vper x 4095 4096 Data can be right justified or left justified depending on the setting of the ADOLJST bit ADCOCN 2 Unused bits in the ADCOH and ADCOL registers are set to 0 Example codes are shown below for both right justi fied and left justified data Input Voltage Right Justified ADCOH ADCOL Left Justified ADCOH ADCOL ADOLJST 0 ADOLJST 1 VREF x 4095 4096 OxOFFF OxFFFO VREF x 2048 4096 0x0800 0x8000 VREF x 2047 4096 0x07FF Ox7FFO 0 0x0000 0x0000 When the ADCO Repeat Count is greater than 1 the output conversion code represents the accumulated result of the conversions performed and is updated after the last conversion in the series is finished Sets of 4 8 or 16 consecutive samples can be accumulated and represented in unsigned integer format The repeat count can be selected using the ADORPT bits in the ADCOCF register The value must be r
183. CN OxAA External Memory Interface Control 162 EMIOTC External Memory Interface Timing Control 168 FLKEY 0 7 Flash Lock and Key 146 Rev 1 3 120 C8051F58x F59x Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page FLSCL 0 6 Flash Scale 147 IE 0xA8 Interrupt Enable 130 IP 0xB8 Interrupt Priority 131 ITO1CF 0 4 1 Configuration 137 LINOADR 0xD3 LINO Address 221 LINOCF 0xC9 LINO Configuration 221 LINODAT 0 2 LINO Data 222 OSCICN OxA1 Internal Oscillator Control 179 OSCICRS 2 Internal Oscillator Coarse Control 180 OSCIFIN Ox9E Internal Oscillator Fine Calibration 180 OSCXCN Ox9F External Oscillator Control 184 PO 0x80 Port 0 Latch 204 POMASK OxF2 Port 0 Mask Configuration 200 POMAT OxF 1 Port 0 Match Configuration 200 POMDIN OxF 1 Port 0 Input Mode Configuration 205 POMDOUT 4 Port 0 Output Mode Configuration 205 POSKIP 0xD4 Port 0 Skip 206 P1 0x90 Port 1 Latch 206 P1MASK OxF4 Port 1 Mask Configuration 201 P1MAT OxF3 Port 1 Match Configuration 201 P1MDIN OxF2 Port 1 Input Mode Configuration 207 P1MDOUT 0xA5 Port 1 Output Mode Configuration 207 P1SKIP 0xD5 Port 1 Skip 208 P2 0 Port 2 Latch 208 P2MASK 0 2 Port 2 Mask Configuration 202 P2MAT OxB1 Port 2 Match Configura
184. CON 0x88 Timer Counter Control 291 THO 0x8C Timer Counter 0 High 294 TH1 0x8D Timer Counter 1 High 294 TLO 0x8A Timer Counter 0 Low 293 TL1 0 8 Timer Counter 1 Low 293 TMOD 0x89 Timer Counter Mode 292 TMR2CN 0xC8 Timer Counter 2 Control 298 TMR2H OxCD Timer Counter 2 High 300 TMR2L 0xCG Timer Counter 2 Low 300 TMR2RLH 0xCB Timer Counter 2 Reload High 299 TMR2RLL OxCA Timer Counter 2 Reload Low 299 TMR3CN 0x91 Timer Counter 3 Control 304 TMR3H 0x95 Timer Counter 3 High 306 TMR3L 0x94 Timer Counter 3 Low 306 TMRS3RLH 0x93 Timer Counter 3 Reload High 305 TMR3RLL 0x92 Timer Counter 3 Reload Low 305 TMR4CAPH 0xCB Timer Capture 4 Capture High 312 TMR4CAPL OxCA Timer Capture 4 Capture Low 312 TMR4CF 0xC9 Timer Counter 4 Configuration 311 TMR4CN 0xC8 Timer Counter 4 Control 310 TMR4H OxCD Timer Counter 4 High 313 TMR4L 0xCC Timer Counter 4 High 313 TMR5CAPH 0x93 Timer Capture 5 Capture High 312 TMR5CAPL 0x92 Timer Capture 5 Capture Low 312 TMR5CF 0x96 Timer Counter 5 Configuration 311 TMR5CN 0x91 Timer Counter 5 Control 310 TMR5H 0x95 Timer Counter 5 High 313 TMR4L 0x94 Timer Counter 5 High 313 VDM0CN OxFF Vpp Monitor Control 155 XBRO OxE1 Port I O Crossbar Control 0 196 Rev 1 3 124 SILICON LABS C8051F58x F59x Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page XBR1 OxE2 Port Crossbar Control 1
185. CON LABS 8051 58 59 Gain Register Definition 6 1 ADCOGNH ADCO Selectable Gain High Byte Bit 7 6 5 4 3 2 1 0 Name GAINH 7 0 Type W Reset 1 1 1 1 1 1 0 0 Indirect Address 0x04 Bit Name Function 7 0 GAINH 7 0 ADCO Gain High Byte See Section 6 3 1 for details on calculating the value for this register Note This register is accessed indirectly See Section 6 3 2 for details for writing this register Gain Register Definition 6 2 ADCOGNL ADCO Selectable Gain Low Byte Bit 7 6 5 4 3 2 1 0 Name GAINL 3 0 Reserved Reserved Reserved Reserved Type W W W W W Reset 0 0 0 0 0 0 0 0 Indirect Address 0x07 Bit Name Function 7 4 GAINL 3 0 ADCO Gain Lower 4 Bits See Figure 6 3 1 for details for setting this register This register is only accessed indirectly through the ADCOH and ADCOL register 3 0 Reserved Must Write 00000 Note This register is accessed indirectly See Section 6 3 2 for details for writing this register 63 Rev 1 3 SILICON LABS 8051 58 59 Gain Register Definition 6 3 ADCOGNA ADCO Additional Selectable Gain Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD Type
186. CON LABS Rev 1 3 347 8051 58 59 SFR Definition 29 4 PCA1CPMn PCA1 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 PWM161n ECOMin CAPPin CAPNin 1 TOG1n PWMin ECCF1n Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Addresses PCA1CPM6 OxDA PCA1CPM7 OxDB PCA1CPM8 OxDC PCA1CPM9 OxDD PCA1CPM10 OxDE PCA1CPM11 OxDF SFR Page all registers 0x10 Bit Name Function 7 PWM161n 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled 0 8 to 11 bit PWM selected 1 16 bit PWM selected 6 ECOMin Comparator Function Enable This bit enables the comparator function for PCA1 module n when set to 1 5 CAPP1n Capture Positive Function Enable This bit enables the positive edge capture for PCA1 module n when set to 1 4 CAPNin Capture Negative Function Enable This bit enables the negative edge capture for PCA1 module n when set to 1 3 1 Match Function Enable This bit enables the match function for PCA1 module n when set to 1 When enabled matches of the PCA1 counter with a module s capture compare register cause the CCFn bit in PCA1MD register to be set to logic 1 2 TOGin_ Toggle Function Enable This bit enables the toggle function for PCA1 module n when set to 1 When enabled matches of the PCA1 counter with a m
187. Conversion A conversion can be initiated in one of four ways depending on the programmed states of the ADCO Start of Conversion Mode bits ADOCM1 0 in register ADCOCN Conversions may be initiated by one of the fol lowing m Writing a 1 to the ADOBUSY bit of register ADCOCN m Arising edge on the CNVSTR input signal pin PO 1 m A Timer 1 overflow i e timed continuous conversions m A Timer 2 overflow i e timed continuous conversions amp N Writing a 1 to ADOBUSY provides software control of ADCO whereby conversions are performed on demand During conversion the ADOBUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete The falling edge of ADOBUSY triggers an interrupt when enabled and sets the ADCO interrupt flag ADOINT Note that when polling for ADC conversion completions the ADCO interrupt flag ADOINT should be used Converted data is available in the ADCO data registers ADCOH ADCOL when bit ADOINT is logic 1 When Timer 2 overflows are used as the conversion source Low Byte overflows are used if Tim er2 is in 8 bit mode High byte overflows are used if Timer 2 is in 16 bit mode See Section 27 Timers on page 285 for timer configuration Important Note About Using CNVSTR The CNVSTR input pin also functions as Port pin PO 1 When the CNVSTR input is used as the ADCO conversion source Port pin 1 should be skipped by the Digital Crossbar To configure the Cr
188. D 020 specification for Small Body Components 41 Rev 1 3 SILICON LABS 8051 58 59 5 Electrical Characteristics 5 1 Absolute Maximum Specifications Table 5 1 Absolute Maximum Ratings Parameter Conditions Ambient Temperature under Bias Storage Temperature Voltage on with Respect to GND Voltage on Vpp with Respect to GND Voltage on VDDA with Respect to GND Voltage on Vio with Respect to GND Voltage on any Port I O Pin or RST with Respect to GND Maximum Total Current through or GND Maximum Output Current Sunk by RST or any Port Pin 100 mA Maximum Output Current Sourced by any Port Pin 100 mA Note Stresses outside of the range of the Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Rev 1 3 42 SILICON LABS 8051 58 59 5 2 Electrical Characteristics Table 5 2 Global Electrical Characteristics 40 to 125 C 24 MHz system clock unless otherwise specified Parameter Conditions Supply Input Voltage Digital Supply Voltage Vpp System Clock lt 25 MHz System Clock gt
189. DCO Data Word LSB Bit 7 6 5 4 3 2 1 0 Name ADCOL 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address OxBD SFR Page 0x00 Bit Name Function 7 0 ADCOL 7 0 ADCO Data Word Low Order Bits For ADOLJST 0 Bits 7 0 are the lower 8 bits of the ADCO Accumulated Result For ADOLJST 1 ADORPT must be 00 Bits 7 4 are the lower 4 bits of the 12 bit result Bits 3 0 0000b SILICON LABS Rev 1 3 66 8051 58 59 SFR Definition 6 7 ADCOCN ADCO Control Bit 7 6 5 4 3 2 1 0 Name ADOEN BURSTEN ADOINT ADOBUSY ADOWINT ADOLJST 0 Type RW RW RW RW RW R W Reset 0 0 0 0 0 0 0 0 SFR Address 0 8 SFR Page 0x00 Bit Addressable Bit Name Function 7 ADOEN ADCO Enable Bit 0 ADCO Disabled ADCO is in low power shutdown 1 ADCO Enabled ADCO is active and ready for data conversions 6 BURSTEN ADCO Burst Mode Enable Bit 0 Burst Mode Disabled 1 Burst Mode Enabled 5 ADOINT ADCO Conversion Complete Interrupt Flag 0 ADCO has not completed a data conversion since ADOINT was last cleared 1 ADCO has completed a data conversion 4 ADOBUSY ADCO Busy Bit Read Write 0 ADCO conversion is not 0 No Effect in progress 1 Initiates ADCO Conver 1 ADCO conversion isin sion if ADOCM 1 0 00b progress 3 ADOWINT ADCO Window Compare Inter
190. DLTOUT ABORT DTREQ LININT ERROR WAKEUP DONE Type R R R R R R R R Reset 0 0 0 0 0 0 0 0 Indirect Address 0x09 Bit Name Function 7 ACTIVE LIN Active Indicator Bit 0 No transmission activity detected on the LIN bus 1 Transmission activity detected on the LIN bus 6 IDLT Bus Idle Timeout Bit slave mode only 0 The bus has not been idle for four seconds 1 No bus activity has been detected for four seconds but the bus is not yet in Sleep mode 5 ABORT Aborted Transmission Bit slave mode only 0 The current transmission has not been interrupted or stopped This bit is reset to O after receiving a SYNCH BREAK that does not interrupt a pending transmission 1 New SYNCH BREAK detected before the end of the last transmission or the STOP bit LINOCTRL 7 has been set 4 DTREQ Data Request Bit slave mode only 0 Data identifier has not been received 1 Data identifier has been received 3 LININT Interrupt Request Bit 0 An interrupt is not pending This bit is cleared by setting RSTINT LINOCTRL 3 1 There is a pending LINO interrupt 2 ERROR Communication Error Bit 0 No error has been detected This bit is cleared by setting RSTERR LINOCTRL 2 1 An error has been detected 1 WAKEUP Wakeup Bit 0 A wakeup signal is not being transmitted and has not been received 1 A wakeup signal is being transmitted or has been received 0 DONE Transmission Complete Bit 0 A transmission is not in progress or has not been
191. Definition 15 3 SILICON LABS Rev 1 3 95 8051 58 59 Table 11 1 CIP 51 Instruction Set Summary Prefetch Enabled Continued Mnemonic Description Bytes Clock Cycles SETBC Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C bit Move direct bit to Carry 2 2 MOV bit C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 4 6 JNC rel Jump if Carry is not set 2 2 4 6 JB bit rel Jump if direct bit is set 3 3 5 7 JNB bit rel Jump if direct bit is not set 3 3 5 7 JBC bit rel Jump if direct bit is set and clear bit 3 3 5 7 Program Branching ACALL addr11 Absolute subroutine call 2 4 6 LCALL addr16 Long subroutine call 3 5 7 RET Return from subroutine 1 6 8 RETI Return from interrupt 1 6 8 AJMP 11 Absolute jump 2 4 6 LJMP addr16 Long jump 3 5 7 SJMP rel Short jump relative address 2 4 6 JMP A DPTR Jump indirect relative to DPTR 1 3 5 JZ rel Jump if A equals zero 2 2 4 6 JNZ rel Jump if A does not equal zero 2 2 4 6 CJNE A direct rel Compare direct byte to A and jump if not equal 3 4 6 8 CJNE A data rel Compare immediate
192. Dual Tracking modes can be used When Burst Mode is enabled a single convert start will initiate a number of conversions equal to the repeat count When Burst Mode is disabled a convert start is required to initiate each conversion In both modes the ADCO End of Conversion Interrupt Flag ADOINT will be set after repeat count conversions have 57 Rev 1 3 SILICON LABS 8051 58 59 been accumulated Similarly the Window Comparator will not compare the result to the greater than and less than registers until repeat count conversions have been accumulated Note When using Burst Mode care must be taken to issue a convert start signal no faster than once every four SYSCLK periods This includes external convert start signals System Clock Convert Start ADOBUSY or Timer Overflow Post Tracking Vemm Sie emn meme ADOEN 0 Dual Tracking ADOTM 11 ADOEN 0 Powered Power Up Powered Power Up Down and Track and Track Post Tracking ADOTM 01 ADOEN 1 Dual Tracking ADOTM 11 ADOEN 1 T Tracking C Converting Convert Start CNVSTR Post Tracking Powered Power Up Powered Power Up I Down andide Down andide C ADOEN 0 Duel Tracking Powered Power Up Powered Power Up AGENS TI Down and Track Down and Track ADOEN 0 lt Post Tracking ADOTM 01 Idle T
193. Enable Bits These bits select Port 3 pins to be skipped by the Crossbar Decoder Port pins used for analog special functions or GPIO should be skipped by the Crossbar 0 Corresponding P3 n pin is not skipped by the Crossbar 1 Corresponding P3 n pin is skipped by the Crossbar Note Port P3 1 P3 7 are only available on the 48 pin and 40 pin packages SFR Definition 20 29 P4 Port 4 Bit 7 6 5 4 3 2 1 0 Name P4 7 0 Type R W Reset 1 1 1 1 1 1 1 1 SFR Address 0xB5 SFR Page All Pages Bit Name Description Write Read 7 0 4 7 0 Port 4 Data 0 Set output latch to logic 0 P4 n Port is logic Sets the Port latch logic LOW LOW value or reads the Port pin 1 Set output latch to logic 1 P4 n Port pin is logic logic state in Port cells con HIGH HIGH figured for digital I O Note Port 4 0 is only available on the 48 pin and 40 pin packages P4 1 P4 7 is only available on the 48 pin packages Rev 1 3 212 SILICON LABS 8051 58 59 SFR Definition 20 30 PAMDOUT Port 4 Output Mode Bit 7 6 5 4 3 1 0 Name PAMDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 SFR Address OxAF SFR Page 0 0 Bit Name Function 7 0 PAMDOUT 7 0 Note Port 4 0 is only available on the 48 pin and 40 pin packages P4 1 P4 7 is
194. FFCC 57600 57692 OxFF98 28800 28846 OxFF30 14400 14388 OxFE5F 9600 9600 OxFD8F 2400 2400 OxF63C 1200 1200 OxEC78 48 SYSCLK N SYSCLK SYSCLK 12 257 Rev 1 3 SILICON LABS 8051 58 59 24 2 Data Format UARTO has a number of available options for data formatting Data transfers begin with a start bit logic low followed by the data bits sent LSB first a parity or extra bit if selected and end with one or two stop bits logic high The data length is variable between 5 and 8 bits A parity bit can be appended to the data and automatically generated and detected by hardware for even odd mark or space parity The stop bit length is selectable between 1 and 2 bit times and a multi processor communication mode is available for implementing networked UART buses All of the data formatting options can be configured using the SMODO register shown in SFR Definition 24 2 Figure 24 2 shows the timing for a UARTO transaction without parity or an extra bit enabled Figure 24 3 shows the timing for a UARTO transaction with parity enabled PEO 1 Figure 24 4 is an example of a UARTO transaction when the extra bit is enabled XBEO 1 Note that the extra bit feature is not available when parity is enabled and the second stop bit is only an option for data lengths of 6 7 or 8 bits MARK START SPACE BIT 1 BIT 2 BIT TIMES
195. Flash page containing the target location as described in Section 15 1 3 Set the FLEWT bit register FLSCL Set the CHBLKW bit register CCHOCN Set the PSWE bit register PSCTL Clear the PSEE bit register PSCTL Write the first key code to FLKEY 0xA5 9 Write the second key code to FLKEY OxF1 10 Using the MOVX instruction write the first data byte to the desired location within the 512 byte sector 11 Write the first key code to FLKEY OxA5 12 Write the second key code to FLKEY OxF1 13 Using the MOVX instruction write the second data byte to the desired location within the 512 byte sector The location of the second byte must be the next higher address from the first data byte 14 Clear the PSWE bit 15 Clear the CHBLKW bit gt Rev 1 3 140 SILICON LABS 8051 58 59 15 2 Non volatile Data Storage The Flash memory can be used for non volatile data storage as well as program code This allows data such as calibration coefficients to be calculated and stored at run time Data is written using the MOVX write instruction and read using the MOVC instruction Note that MOVX read instructions always target XRAM 15 3 Security Options The CIP 51 provides security options to protect the Flash memory from inadvertent modification by soft ware as well as to prevent the viewing of proprietary program code and constants The Program Store Write Enable bit PSWE in register PSCTL and the Prog
196. Fn flag for the channel will be set when the 16 bit PCA1 counter and the 16 bit capture compare regis ter for the channel are equal Write to 0 Reset Write to PCA1CPMn PCATCPHn MJO P PITIG M C bi 1 M Nln 1 1 F PCA1CPLn 8 bit Adder PCA1CPHn ea 1 1 1 1 n n n n n TOG1n 000 Toggle p i 0 I Y Enable oo Crossbar gt Port vo L Comparator 1 1 Timebase b PCA1L Figure 29 7 PCA1 Frequency Output Mode 340 Rev 1 3 SILICON LABS 8051 58 59 29 3 5 8 bit 9 bit 10 bit and 11 bit Pulse Width Modulator Modes Each module can be used independently to generate a pulse width modulated PWM output on its associ ated CEXn pin The frequency of the output is dependent on the timebase for the PCA1 counter timer and the setting of the PWM cycle length 8 9 10 or 11 bits For backwards compatibility with the 8 bit PWM mode available on other devices the 8 bit PWM mode operates slightly different than 9 10 and 11 bit PWM modes It is important to note that all channels configured for 8 9 10 11 bit PWM mode will use the same cycle length It is not possible to configure one channel for 8 bit PWM mode and another for 11 bit mode for example However other PCA1 channels can be configured to Pin Capture High Speed
197. For Digital I O Any pins to be used by digital peripherals UART SPI SMBus etc external digital event capture func tions or as GPIO should be configured as digital PnMDIN n 1 For digital I O pins one of two output modes push pull or open drain must be selected using the PnMDOUT registers Push pull outputs PNMDOUT n 1 drive the Port pad to the VIO or GND supply rails based on the output logic value of the Port pin Open drain outputs have the high side driver disabled therefore they only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs both high low drivers turned off when the output logic value is 1 When a digital I O cell is placed in the high impedance state a weak pull up transistor pulls the Port pad to the VIO supply voltage to ensure the digital input is at a defined logic state Weak pull ups are disabled when the I O cell is driven to GND to minimize power consumption and may be globally disabled by setting WEAKPUD to 1 The user should ensure that digital I O are always internally or externally pulled or driven to a valid logic state to minimize power consumption Port pins configured for digital I O always read back the logic state of the Port pad regardless of the output logic value of the Port pin WEAKPUD Weak Pull Up Disable PxMDOUT x ae 1 for push pull VIO VIO 0 for open drain XBARE Crossbar gt gt d d WEAK Enable lt A PORT Px x
198. Fora slave transmit operation load the data to transmit into the data buffer 6 Set the DTACK bit LINOCTRL 4 Continue to step 10 7 If DTREQ LINOST 4 is not set check the DONE bit LINOST 0 The transmission was successful if the DONE bit is set 8 If the transmission was successful and the current frame was a receive operation for the slave load the received data bytes from the data buffer 9 If the transmission was not successful check LINOERR to determine the nature of the error Further error handling has to be done by the application 10 Set the RSTINT LINOCTRL 3 and RSTERR bits LINOCTRL 2 to reset the interrupt request and the error flags In addition to these steps the application should be aware of the following 1 If the current frame is a transmit operation for the slave steps 1 through 5 must be completed during the IN FRAME RESPONSE SPACE If it is not completed in time a timeout will be detected by the master 2 If the current frame is a receive operation for the slave steps 1 through 5 have to be finished until the reception of the first byte after the IDENTIFIER FIELD Otherwise the internal receive buffer of the LIN controller will be overwritten and a timeout error will be detected in the LIN controller 219 Rev 1 3 SILICON LABS 8051 58 59 3 The LIN controller does not directly support LIN Version 1 3 Extended Frames If the application detects an unknown identifier e g extende
199. H 0xC3 CANOIF1CML 0xC2 CANOIF1CM 0 0000 0 14 Mask 1 CANOIF1M1H 5 CANOIF1M1L 0xC4 CANOIF1M1 OxFFFF Ox16 Mask 2 CANOIF1M2H 0xC7 CANOIF1M2L OxC6 CANOIF1M2 OxFFFF 0x18 Arbitration 1 CANOIF1A1H 0 CANOIF1A1L CANOIF1A1 0x0000 Ox1A IF1 Arbitration 2 CANOIF1A2H 0 CANOIF1A2L 0 CANOIF1A2 0x0000 Ox1C IF1 Message Control CANOIF1MCH 0xD3 CANOIF1MCL 0xD2 CANOIF1MC 0 0000 0 1 IF1 Data A 1 CANOIF1DA1H 0xD5 CANOIF1DA1L 0xD4 CANOIF1DA1 0 0000 0 20 IF1 Data A 2 CANOIF1DA2H 0 07 CANOIF1DA2L 0xD6 CANOIF1DA2 0x0000 0x22 IF1 Data B 1 CANOIF1DB1H OXDB CANOIF1DB1L OXDA CANOIF1DB1 0x0000 Ox24 Data B2 CANOIF1DB2H 0xDD CANOIF1DB2L OXDC CANOIF1DB2 0x0000 0x40 IF2 Command Request CANOIF2CRH OxDF CANOIF2CRL OxDE CANOIF2CR 0x0001 0x42 IF2 Command Mask CANOIF2CMH 0 CANOIF2CML OxE2 CANOIF2CM 0 0000 Ox44 2 Mask 1 CANOIF2M1H OxEB CANOIF2M1L OXEA CANOIF2M1 OxFFFF 0 46 IF2 Mask 2 CANOIF2M2H OxED CANOIF2M2L OxEC CANOIF2M2 OxFFFF 0x48 IF2 Arbitration 1 CANOIF2A1H OxEF CANOIF2A1L CANOIF2A1 0x0000 Ox4A IF2 Arbitration 2 CANOIF2A2H OxF3 CANOIF2A2L OxF2 CANOIF2A2 0x0000 0 4 F2 Message Control CANOIF2MCH OxCF CANOIF2MCL OxCE CANOIF2MC 0 0000 Ox4E F2 Data A 1 CANOIF2DA1H OxF7 CANOIF2DA1L OxF6 CANOIF2DA1 0x0000 Notes 1 Re
200. Handler Registers are read only registers The message handler registers provide interrupt error transmit receive requests and new data information Rev 1 3 235 SILICON LABS 8051 58 59 22 2 4 CAN Register Assignment The standard Bosch CAN registers are mapped to SFR space as shown below and their full definitions are available in the CAN User s Guide The name shown in the Name column matches what is provided in the CAN User s Guide One additional SFR which is not a standard Bosch CAN register CANOCFG is pro vided to configure the CAN clock All CAN registers are located on SFR Page Ox0C Table 22 2 Standard CAN Registers and Reset Values CAN Name SFR Name SFR SFRName SFR 16 bit Reset Addr High Addr Low Addr SFR Value 0x00 ICAN Control Register CANOCN 0xCO 0x01 0x02 Status Register CANOSTAT 0x94 0 00 0 04 Error Counter CANOERRH 0 97 CANOERRL 0 96 CANOERR 0 0000 0 06 Bit Timing Register CANOBTH 0x9B CANOBTL Ox9A CANOBT 0 2301 0x08 Interrupt Register CANOIIDH 0 9 CANOIIDL 0 9 CANOIID 0 0000 Test Register CANOTST 0x004 OxOC BRP Extension Register CANOBRPE 0xA1 0x00 0x10 IF1 Command Request CANOIF1CRH OxBF CANOIF1CRL OxBE CANOIF1CR 0x0001 0x12 Command Mask CANOIF1CM
201. High Frequency Oscillator Electrical Characteristics 49 Table 5 7 Clock Multiplier Electrical Specifications 50 Table 5 8 Voltage Regulator Electrical Characteristics 50 Table 5 9 ADCO Electrical Characteristics 51 Table 5 10 Temperature Sensor Electrical Characteristics 52 Table 5 11 Voltage Reference Electrical Characteristics 52 Table 5 12 Comparator 0 1 and 2 Electrical Characteristics 53 Table 11 1 CIP 51 Instruction Set Summary Prefetch Enabled 94 Table 13 1 Special Function Register SFR Memory Map for Pages 0x00 0x10 and 0 117 Table 13 2 Special Function Register SFR Memory Map for Page OxOC 119 Table 13 3 Special Function Registers 120 Table 14 1 Interrupt Summary uoo 128 Table 15 1 Flash Security Summary 141 Table 18 1 EMIF Pinout C8051F580 1 4 5 158 Table 18 2 EMIF Pinout 8051 588 9 590 1 159 Table 18 3 AC Parameters for External Memory Interface 173 Table 20 1 Port I O Assignment for Analog Functions 189 Ta
202. IF2DB2L CANOIF2DB2H FO B CANOIF2A2L CANOIF2A2H CANOIF2DA1L CANOIF2DA1H All Pages E8 CANOIF2M1L CANOIF2M1H CANOIF2M2L CANOIF2M2H CANOIF2A1L CANOIF2A1H EO ACC CANOIF2CML CANOIF2CMH EIE1 EIE2 All Pages All Pages All Pages D8 CANOIF1DB1L CANOIF1DB1H CANOIF1DB2L CANOIF1DB2H CANOIF2CRL CANOIF2CRH DO PSW CANOIF1MCL CANOIF1MCH CANOIF1DA1L CANOIF1DA1H CANOIF1DA2L CANOIF1DA2H All Pages C8 CANOIF1A1L CANOIF1A1H CANOIF1A2L CANOIF1A2H CANOIF2MCL CANOIF2MCH CO CANOCN CANOIF1CML CANOIF1CMH CANOIF1M1L CANOIF1M1H CANOIF1M2L CANOIF1M2H B8 IP CANOMV1L CANOMV1H CANOMV2L CANOMV2H CANOIF1CRL CANOIF1CRH All Pages BO P3 CANOIP2L CANOIP2H P4 FLSCL FLKEY All Pages All Pages All Pages All Pages A8 IE CANOND1L CANOND1H CANOND2L CANOND2H CANOIP1L CANOIP1H All Pages 2 CANOBRPE CANOTRIL CANOTR1H CANOTR2L CANOTR2H SFRPAGE All Pages All Pages 98 SCONO CANOBTL CANOBTH CANOIIDL CANOIIDH CANOTST All Pages 90 1 CANOCFG CANOSTAT CANOERRL CANOERRH TCON TMOD TLO TL1 THO TH1 CKCON All Pages All Pages All Pages All Pages All Pages All Pages All Pages 80 SP DPL DPH SFRNEXT SFRLAST PCON All Pages All Pages All Pages All Pages All Pages All Pages All Pages 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F bit addressable 119 1 3 gt SILICON LABS 8051 58 59 Table 13
203. ILICON LABS 8051 58 59 Added Port 2 Event Port 3 Events to wake up sources in 19 2 1 Internal Oscillator Suspend Updated SFR Definition 20 3 with correct names for bits 2 2 Updated 21 Local Interconnect Network LINO with a voltage range specification for the internal oscillator Updated LIN Register Definitions 21 9 and 21 10 with correct reset values Updated 22 Controller Area Network with a voltage range specification for the internal oscillator Updated C2 Register Definitions 30 2 and 30 3 with correct C2 and SFR addresses Revision 1 2 to Revision 1 3 m Updated the note Power Fail Reset VDD Monitor on page 154 to use a larger font m Added the note regarding the voltage regulator and VDD monitor in the high setting from Power Fail Reset VDD Monitor on page 154 to Voltage Regulator REGO on page 89 and Vpp Maintenance and the Vpp monitor on page 143 Also adjusted the language regarding the solution with the highest system reliability m Updated the steps in Vpp Maintenance and the Vpp monitor page 143 to mention using the VDD monitor in the high setting during flash write erase operations m Updated the SUSPEND bit description in OSCICN SFR Definition 19 2 to mention that firmware must set the ZTCEN bit in REFOCN SFR Definition 8 1 before entering suspend m Added a note to the IFRDY flag in the OSCICN register
204. MBOCN SMBOCF SMBODAT ADCOGTL ADCOGTH ADCOLTL ADCOLTH XBR3 XBR2 B8 IP ADCOTK ADCOMX ADCOCF ADCOL ADCOH All Pages BO 2 P2MASK All Pages All Pages EMIOCF 8 IE SMOD0 EMIOCN All Pages EMIOTC SBCONO SBRLLO SBRLHO P3MDOUT AO P2 SPIOCFG SPIOCKR SPIODAT All Pages OSCICN OSCICRS POMDOUT P2MDOUT 98 5 SBUFO CPTOCN CPTOMD CPTOMX CPT1CN CPT1MD SCON1 SBUF1 CPT2CN CPT2MD CPT2MX OSCIFIN OSCXCN 0 8 1 9 2 A 3 B 4 C 5 0 6 7 F bit addressable 117 Rev 1 3 SILICON LABS 8051 58 59 Table 13 1 Special Function Register SFR Memory Map for Pages 0x00 0x10 and OxOF 90 P1 TMR3RLL TMR3RLH All Pages TMR5CN TMR5CAPL TMR5CAPH CLKMUL TCON TMOD TLO TL1 THO TH1 CKCON PSCTL All Pages All Pages All Pages All Pages All Pages All Pages All Pages CLKSEL TMR5CF 88 80 PO SP DPL DPH SFRNEXT SFRLAST PCON All All Pages All Pages All Pages All Pages All Pages All Pages SFROCN 0 8 1 9 2 3 B 4 C 5 0 6 7 F bit addressable Rev 1 3 118 SILICON LABS 8051 58 59 Table 13 2 Special Function Register SFR Memory Map for Page 0x0C All Pages 88 0 8 1 9 2 A 3 B 4 C 5 D 6 E F8 CANOIF2DA2L CANOIF2DA2H CANOIF2DB1L CANOIF2DB1H CANO
205. MCEO bit SMODO 7 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the extra bit is logic 1 RBXO 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned address If the addresses match the slave will clear its MCEO bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCEO bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCEO bit to ignore all trans missions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Slave Device Master Slave Slave Device Device Device OOO RX TX RX TX Figure 24 6 UART Multi Processor Mode Interconnect Diagram Rev 1 3 260 SILICON LABS 8051 58 59 SFR Definition 24 1 SCONO Serial Port 0 Control
206. MD CIC WIC A A AIOWIC C C C C C C C C C LIL SIVIO Sls 1MPN nH t F M tFF F F F F S S S F EIFIV 6 1 1 1 1 1 1 1 9 8 7 6 1 ijijiji LH 1 1 0 1 2 1 0 1 1 n 7 1 0 1 Counter Timer 8 9 10 or 11 bit Overflow gt Set 8 9 10 or 11 bit Operation i Y o PCA1 Counter Timer 16 0 bit Overflow ECCF6 1 EPCA1 d EA d Yo 0 0 Interrupt PCA Module 6 o o o Priority CCF6 1 1 Decoder ECCF7 Y o PCA Module 7 CCF7 ECCF8 PCA Module 8 CCF8 1 ECCF9 PCA Module 9 CCF9 10 Y o PCA Module 10 CCF10 o 11 Y o PCA Module 11 CCF11 Figure 29 3 1 Interrupt Block Diagram Rev 1 3 335 SILICON LABS 8051 58 59 29 3 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes Edge triggered Capture Software Timer High Speed Output Frequency Output 8 to 11 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator Each module has Special Function Registers SFRs associated with it in the CIP 51 system controller These registers are used to exchange data with a module and configure the module s mode of operation Table 29 2 summarizes the bit settings in the PCA1CPMn and PCA1PWM registers used to select the PCA1 capture comp
207. Missing Clock Detector Switch the system clock to the external oscillator Important Note on External Crystals Crystal oscillator circuits are quite sensitive to PCB layout The crystal should be placed as close as possible to the XTAL pins on the device The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation These capacitors are in series as seen by the crystal and parallel with the stray capacitance of the XTAL1 and XTAL2 pins Note The desired load capacitance depends upon the crystal and the manufacturer Refer to the crystal data sheet when completing these calculations For example a tuning fork crystal of 32 768 kHz with a recommended load capacitance of 12 5 pF should use the configuration shown in Figure 19 1 Option 1 The total value of the capacitors and the stray capac itance of the XTAL pins should equal 25 pF With a stray capacitance of 3 pF per pin the 22 pF capacitors yield an equivalent capacitance of 12 5 pF across the crystal as shown in Figure 19 3 Rev 1 3 185 SILICON LABS 8051 58 59 XTAL1 LI 32 768 kHz Capacitor values depend on crystal specifications Figure 19 3 External 32 768 kHz Quartz Crystal Oscillator Connection Diagram
208. Mode write to SMBODAT before clearing SI 1100 254 Rev 1 3 SILICON LABS 8051 58 59 Values Read S ARBLOST Table 23 4 SMBus Status Decoding Current SMbus State A slave byte was transmitted NACK received Typical Response Options No action required expecting STOP condition Valuesto Write Next Status Vector Expected A slave byte was transmitted ACK received Load SMBODAT with next data byte to transmit A Slave byte was transmitted error detected No action required expecting Master to end transfer Slave Transmitter An illegal STOP or bus error was detected while a Slave Transmission was in progress A slave address R W was received ACK requested Clear STO If Write Acknowledge received address If Read Load SMBODAT with data byte ACK received address NACK received address Lost arbitration as master slave address R W received ACK requested If Write Acknowledge received address If Read Load SMBODAT with data byte ACK received address NACK received address Reschedule failed transfer NACK received address A STOP was detected while addressed as a Slave Trans mitter or Slave Receiver Clear STO Lost arbitration while attempt ing a STOP No action required transfer complete aborted A slave byte was received ACK requested Lost arb
209. Mode Register 330 PCAOCPM4 Module 4 Mode Register 330 PCAOCPM5 OxDF PCAO Module 5 Mode Register 330 PCAOH OxFA PCAO Counter High 331 PCAOL OxF9 PCAO Counter Low 331 PCAOMD 0 09 PCAO Mode 328 PCAOPWM OxD9 PWM Configuration 329 PCA1CN 0xD8 PCA1 Control 345 PCA1CPH6 OxFC PCA1 Capture 6 High 350 PCA1CPH7 OxEA PCA1 Capture 7 High 350 PCA1CPH8 OxEC PCA1 Capture 8 High 350 PCA1CPH9 OxEE PCA1 Capture 9 High 350 PCA1CPH10 OxFE PCA1 Capture 10 High 350 PCA1CPH11 OxCF PCA1 Capture 11 High 350 PCA1CPL6 OxFB PCA1 Capture 6 Low 350 PCA1CPL7 OxE9 PCA1 Capture 7 Low 350 PCA1CPL8 OxEB PCA1 Capture 8 Low 350 PCA1CPL9 OxED PCA1 Capture 9 Low 350 PCA1CPL10 OxFD PCA1 Capture 10 Low 350 Rev 1 3 122 SILICON LABS C8051F58x F59x Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page PCA1CPL11 OxCE PCA1 Capture 11 Low 350 PCA1CPM6 OxDA PCA1 Module 6 Mode Register 348 PCA1CPM7 OxDB PCA1 Module 7 Mode Register 348 PCA1CPM8 OxDC PCA1 Module 8 Mode Register 348 PCA1CPM9 OxDD PCA1 Module 9 Mode Register 348 PCA1CPM10 OxDE PCA1 Module 10 Mode Register 348 PCA1CPM11 OxDF PCA1 Module 11 Mode Register 348 PCA1H OxFA PCA1 Counter High 349 PCA1L OxF9 PCA1 Counter Low 349 PCA1MD OxD9 PCA1 Mode 346 PCA1PWM OxDA PCA
210. N LABS 8051 58 59 List of Tables Table 2 1 Product Selection Guide 8 23 Table 3 1 Pin Definitions for the 8051 58 24 Table 4 1 QFP 48 Package Dimensions 32 Table 4 2 QFP 48 Landing Diagram Dimensions 33 Table 4 3 QFN 48 Package Dimensions 34 Table 4 4 QFN 48 Landing Diagram Dimensions 35 Table 4 5 QFN 40 Package Dimensions 36 Table 4 6 QFN 40 Landing Diagram Dimensions 37 Table 4 7 QFP 32 Package Dimensions 38 Table 4 8 QFP 32 Landing Diagram Dimensions 39 Table 4 9 QFN 32 Package Dimensions 0 22 0 1 40 Table 4 10 QFN 32 Landing Diagram Dimensions 41 Table 5 1 Absolute Maximum Ratings 42 Table 5 2 Global Electrical Characteristics 2 43 Table 5 3 Port I O DC Electrical Characteristics 47 Table 5 4 Reset Electrical Characteristics 22 2 11 48 Table 5 5 Flash Electrical Characteristics 48 Table 5 6 Internal
211. N N ET3 PT3 6 EIE1 6 EIP1 6 LINO 0x0073 14 LINOINT LINST 3 N ELINO PLINO EIE1 7 1 7 Voltage Regulator 0x007B 15 N A N A N A EREGO PREGO Dropout EIE2 0 2 0 CANO 0x0083 16 CANOINT N Y ECANO PCANO CANOCN 7 EIE2 1 2 1 Port Match 0x008B 17 None N A N A EMAT PMAT EIE2 2 EIP2 2 Rev 1 3 128 SILICON LABS C8051F58x F59x Table 14 1 Interrupt Summary Enable Priority Flag Control Interrupt Source Interrupt Priority Pending Flag Vector Order Bit addressable Z Cleared by HW UART1 0x0093 18 SCON1 0 ES1 PS1 TH SCON1 1 EIE2 3 EIP2 3 Programmable 0x009B 19 CF PCA1CN n Y N EPCA1 PPCA1 Counter Array 1 CCFn PCA1CN n EIE2 4 EIP2 4 Comparator2 0x00A3 20 CP2FIF CPT2CN 4 N N ECP2 PCP2 CP2RIF CPT2CN 5 EIE2 5 2 5 Timer 4 Overflow Ox00AB 21 TF4H TMR4CN 7 N 4 PT4 TR4L TMR4CN 6 EIE2 6 EIP2 6 Timer 5 Overflow 0x00B3 22 TF5H TMR5OCN 7 N N ET5 PT5 TF5L TMR5CN 6 EIE2 7 2 7 Note The LINOINT bit is cleared by setting RSTINT LINCTRL 3 14 2 Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described in this section Refer to the data sheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior
212. NOPL o9 Figure 27 1 TO Mode 0 Block Diagram 27 1 2 Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 27 1 3 Mode 2 8 bit Counter Timer with Auto Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8 bit counter timers with automatic reload of the start value TLO holds the count and THO holds the reload value When the counter in TLO overflows from all ones to 0x00 the timer overflow flag TCON 5 is set and the counter in TLO is reloaded from THO If Timer 0 interrupts are enabled an interrupt will occur when the TFO flag is set The reload value in THO is not changed TLO must be initialized to the desired value before enabling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TRO bit TCON 4 enables the timer when either GATEO TMOD 3 is logic 0 or when the input signal INTO is active as defined by bit INOPL in register ITO1CF see Section 14 3 External Interrupts INTO and INT1 on page 136 for details on the external input signals INTO and INT1 288 Rev 1 3 SILICON LABS 8051 58 59 Pre scaled Clock 0 SYSCLK 1 Interrupt
213. POSKIP 0x26 P0 1 0 2 and P0 5 skipped The resulting crossbar would look as shown in Figure 20 4 194 8051 58 59 20 4 Port I O Initialization Port initialization consists of the following steps 1 Select the input mode analog or digital for all Port pins using the Port Input Mode register PnMDIN 2 Select the output mode open drain or push pull for all Port pins using the Port Output Mode register PnMDOUT 3 Select any pins to be skipped by the I O Crossbar using the Port Skip registers PnSKIP 4 Assign Port pins to desired peripherals 5 Enable the Crossbar XBARE 1 All Port pins must be configured as either analog or digital inputs Port 4 on C8051F580 1 4 5 and C8051F588 9 F590 1 is a digital only Port Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs When a pin is configured as an analog input its weak pullup digital driver and digital receiver are disabled This process saves power and reduces noise on the analog input Pins configured as digital inputs may still be used by analog peripherals however this practice is not recom mended Additionally all analog input pins should be configured to be skipped by the Crossbar accomplished by setting the associated bits in PnSKIP Port input mode is set in the PnMDIN register where a 1 indicates a digital input and a 0 indicates an analog input All pins default to digital inputs on reset See SFR
214. PS c e p I bbb H B 4 I miim i AA 1 NUN at Z um SECTION B I Figure 4 1 QFP 48 Package Drawing Table 4 1 QFP 48 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 1 20 E 9 00 BSC A1 0 05 0 15 E1 7 00 BSC A2 0 95 1 00 1 05 L 0 45 0 60 0 75 b 0 17 0 22 0 27 aaa 0 20 0 09 0 20 bbb 0 20 D 9 00 BSC ccc 0 08 D1 7 00 BSC ddd 0 08 e 0 50 BSC 0 3 5 7 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC outline MS 026 variation ABC 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Rev 1 3 SILICON LABS 32 8051 58 59 Figure 4 2 48 Landing Diagram Table 4 2 QFP 48 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 8 30 8 40 X1 0 20 0 30 C2 8 30 8 40 Y1 1 40 1 50 E 0 50 BSC Notes General 1 All dimensions shown are in millimeters mm unless otherwise noted 2 This Land Pattern Design is based on the IPC 7351 guidelines Solder Mask Design 3 All metal pads are to be non solder mask de
215. Port pin logic state in Port cells con figured for digital I O 0 Set output latch to logic LOW 1 Set output latch to logic HIGH 0 P2 n Port pin is logic LOW 1 P2 n Port pin is logic HIGH SILICON LABS Rev 1 3 208 8051 58 59 SFR Definition 20 22 P2MDIN Port 2 Input Mode Bit 7 6 5 4 3 2 1 0 Name P2MDIN 7 0 Reset 1 1 1 1 1 1 1 1 SFR Address OxF3 SFR Page OxOF Bit Name Function 7 0 P2MDIN 7 0 Analog Configuration Bits for P2 7 P2 0 respectively Port pins configured for analog mode have their weak pull up and digital receiver disabled For analog mode the pin also needs to be configured for open drain mode in the P2MDOUT register 0 Corresponding P2 n pin is configured for analog mode 1 Corresponding P2 n pin is not configured for analog mode SFR Definition 20 23 P2MDOUT Port 2 Output Mode Bit 7 6 5 4 3 2 1 0 P2MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA6 SFR Page Ox0F Bit Name Function 7 0 P2EMDOUT 7 0 Output Configuration Bits for 2 7 2 0 respectively These bits are ignored if the corresponding bit in register P2MDIN is logic 0 0 Corresponding P2 n Output is open drain 1 Corresponding P2 n Output is push pull 209 Rev 1 3 SILICON LABS
216. RPAGE to page 0x0C and the UART1 PCA1 Comparator2 and Timer4 5 interrupts will switch SFRPAGE to 0x10 Rev 1 3 106 SILICON LABS 8051 58 59 SFRPGCN Bit Interrupt Logic SFRPAGE Figure 13 1 SFR Page Stack Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register SFROCN This function defaults to enabled upon reset In this way the autoswitching function will be enabled unless dis abled in software summary of the SFR locations address and SFR page are provided in Table 13 3 in the form of an SFR memory map Each memory location in the map has an SFR page row denoting the page in which that SFR resides Certain SFRs are accessible from ALL SFR pages and are denoted by the ALL PAGES designation For example the Port I O registers PO P1 P2 and P3 all have the ALL PAGES designa tion indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value 13 3 SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts In this example the SFR Control register is left in the default enabled state i e SFRPGEN 1 and the CIP 51 is executing in line code that is writing values to SPI Data Register SFR SPIODAT located at address on SFR Page 0x00 T
217. RT mode 8 bit or 9 bit is selected by the STMODE bit SCON1 7 Typical UART connection options are shown in Figure 25 3 C8051Fxxx TX TX MCU gt 8051 RX Figure 25 3 UART Interconnect Diagram 25 2 1 8 Bit UART 8 Bit UART mode uses a total of 10 bits per data byte one start bit eight data bits LSB first and one stop bit Data are transmitted LSB first from the TX1 pin and received at the RX1 pin On receive the eight data bits are stored in SBUF1 and the stop bit goes into RB81 SCON1 2 Data transmission begins when software writes a data byte to the SBUF1 register The TI1 Transmit Inter rupt Flag SCON1 1 is set at the end of the transmission the beginning of the stop bit time Data recep tion can begin any time after the REN1 Receive Enable bit SCON1 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met RIO must be logic 0 and if MCEO is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into the SBUF1 receive register and the following overrun data bits are lost If these conditions are met the eight bits of data is stored in SBUF1 the stop bit is stored in RB81 and the flag is set If these conditions are not met SBUF1 and RB81 will not be loaded and the flag will
218. SFR Definition 19 2 that the flag may not accurately reflect the state of the oscillator Added VDD Ramp Time for Power On spec to Table 5 4 Reset Electrical Characteristics on page 48 Added a note regarding programming at cold temperatures on 1 devices to Programming The Flash Memory on page 138 and added Temperature during Programming Operations specification to Table 5 5 Flash Electrical Characteristics on page 48 m Added a note regarding PO O VREF when VDD is used as the reference to Table 20 1 Port Assignment for Analog Functions on page 191 and to the description of the REFSL bit in REFOCN SFR Definition 8 1 m Added note regarding a potential unknown state on GPIO during power up if VIO ramps significantly before VDD to Port Input Output on page 188 and Reset Sources on page 152 m Added steps to set the FLEWT bit in the flash write erase procedures in Flash Erase Procedure on page 139 Flash Write Procedure on page 139 and Flash Write Optimization on page 140 Added the Reprogramming the VDD Monitor High Threshold on page 138 section Added a note regarding fast changes on VDD causing the Vpp Monitor to trigger to Power Fail Reset VDD Monitor on page 154 m Added notes regarding UART TX and RX behavior in Data Transmission on page 259 and Data Reception on page 259 m Added a note regarding an issue with RST low time on some older devices to Power On Reset on page 153 Added Tab
219. SILICON LABS 8051 58 59 23 4 3 Data Register The SMBus Data register SMBODAT holds a byte of serial data to be transmitted or one that has just been received Software may safely read or write to the data register when the SI flag is set Software should not attempt to access the SMBODAT register when the SMBus is enabled and the SI flag is cleared to logic as the interface may be in the process of shifting a byte of data into or out of the register Data in SMBODAT is always shifted out MSB first After a byte has been received the first bit of received data is located at the MSB of SMBODAT While data is being shifted out data on the bus is simultaneously being shifted in SMBODAT always contains the last data byte present on the bus In the event of lost arbi tration the transition from master transmitter to slave receiver is made with the correct data or address in SMBODAT SFR Definition 23 3 SMBODAT SMBus Data Bit 7 6 5 4 3 Name SMBODAT 7 0 Type R W Reset 0 0 0 0 0 SFR Address 0xC2 SMBODAT 0x00 Bit Name Function 7 0 SMBODAT 7 0 SMBus Data The SMBODAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface The CPU can read from or write to this register whenever the SI serial interrupt flag SMBOCN 0 is set to logic 1 The serial dat
220. SRLH 7 0 Type R W Reset 0 0 0 0 0 SFR Address 0x93 SFR Page 0x00 Bit Name Function 7 0 TMR3RLH 7 0 Timer 3 Reload Register High Byte TMR3RLH holds the high byte of the reload value for Timer 3 SILICON LABS Rev 1 3 305 8051 58 59 SFR Definition 27 16 TMR3L Timer 3 Low Byte Bit 7 6 5 4 3 1 0 Name TMR3L 7 0 Reset 0 0 0 0 0 0 0 SFR Address 0x94 SFR Page 0x00 Bit Name Function 7 0 TMR3L 7 0 Timer 3 Low Byte In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer In 8 bit mode TMR3L contains the 8 bit low byte timer value SFR Definition 27 17 TMR3H Timer 3 High Byte Bit 7 6 5 4 3 1 0 Type R W Reset 0 0 0 0 0 0 0 SFR Address 0x95 SFR Page 0x00 Bit Name Function 7 0 TMR3H 7 0 Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value 306 Rev 1 3 SILICON LABS 8051 58 59 27 4 Timer 4 and Timer 5 Timers 4 and 5 are 16 bit counter timers each formed by two 8 bit SFRs TMRnL low byte and TMRnH high byte where n 4 and 5 for timers 4 and 5 respectively Timers 4 and 5 feature auto reload capture and toggle output modes with the ability to count
221. TF2CEN 1b Timer 2 will clock every SYSCLK and capture every external clock divided by 8 If the SYSCLK is 24 MHz and the difference between two successive captures is 5984 then the external clock frequency is as follows 24 2 5984 8 0 032086 MHz or 32 086 kHz This mode allows software to determine the external oscillator frequency when an RC network or capacitor is used to generate the clock source 296 Rev 1 3 SILICON LABS 8051 58 59 gt gt 0 gt Og 2 T2XCLK MMM H SYSCLK 12 4 External Clock 8 TMR2L TMR2H SYSCLK Capture External Clock 8 TMR2RLL TMR2RLH m Em gt Interrupt E TF2LEN T2SPLIT TR2 TMR2CN T2XCLK Figure 27 6 Timer 2 External Oscillator Capture Mode Block Diagram Rev 1 3 297 SILICON LABS 8051 58 59 SFR Definition 27 8 TMR2CN Timer 2 Control Bit 7 6 5 4 3 2 1 0 2 TF2L 2 TF2CEN T2SPLIT TR2 T2XCLK Type R W R W R W R W R W R W R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xC8 Bit Addressable SFR Page 0x00 Bit Name Function 7 TF2H Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 2
222. The function of this bit is dependent on the Serial Port 1 Operation Mode Mode 0 Checks for valid stop bit 0 Logic level of stop bit is ignored 1 will only be activated if stop bit is logic level 1 Mode 1 Multiprocessor Communications Enable 0 Logic level of ninth bit is ignored 1 is set and an interrupt is generated only when the ninth bit is logic 1 4 REN1 Receive Enable 0 UART1 reception disabled 1 UART1 reception enabled 3 TB81 Ninth Transmission Bit The logic level of this bit will be sent as the ninth transmission bit in 9 bit UART Mode Mode 1 Unused in 8 bit mode Mode 0 2 RB81 Ninth Receive Bit RB81 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 1 TH Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART1 after the 8th bit in 8 bit UART Mode or at the beginning of the STOP bit in 9 bit UART Mode When the UART1 interrupt is enabled setting this bit causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared manually by software 0 Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UART1 set at the STOP bit sampling time When the UART1 interrupt is enabled setting this bit to 1 causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared manually by software Rev 1 3 269 8
223. Type Description F580 1 4 5 F588 9 F582 3 6 7 F590 1 48 pin 40 pin 32 pin P3 7 19 11 D or A In Port 3 7 P4 0 18 _ __ DIO Port 4 0 See SFR Definition 20 29 for a description P4 1 17 D I O Port 4 1 P4 2 16 D I O Port 4 2 P4 3 15 D I O Port 4 3 P4 4 14 D I O Port 4 4 P4 5 13 D I O Port 4 5 P4 6 10 D I O Port 4 6 P4 7 9 D I O Port 4 7 Rev 1 3 26 8051 58 59 x z lt EE THEE GN 10 s LO fel fe fe d P0 1 CNVSTR ie P1 7 VREGIN I T C8051F580 IQ i NS C8051F581 IQ ENDA C8051F584 IQ 67 0 0 VREF C8051 585 10 4 7 A P4 6 P3 0 RST C2CK n 3 on N S Figure 3 1 QFP 48 Pinout Diagram Top View 27 Rev 1 3 SILICON LABS 8051 58 59 D AU Pit P12 P0 1 CNVSTR P1 6 VIO P1 7 VREGIN P2 0 VDD P2 1 VDDA I C8051 F580 IM p22 C8051F581 IM C8051F584 IM GND P2 3 GNDA P2 4 C8051F585 IM P0 0 VREF P2 5 P4 7 P2 6 P4 6 P2 7 C2D P3 0 RST C2CK P3 1 ING 100 mo 1 oo n m 1 Figure 3 2 48 Pinout Diagram Top View Rev 1 3 28 SILICON LABS C8051F58x F59x P1 3 z lt 3 P0 3 XTAL2 2
224. W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xC7 SFR 0x0F Bit Name Function 7 WEAKPUD Port I O Weak Pullup Disable 0 Weak Pullups enabled except for Ports whose I O are configured for analog mode 1 Weak Pullups disabled 6 XBARE Crossbar Enable 0 Crossbar disabled 1 Crossbar enabled 5 4 Reserved Always Write to 000 3 CP2AE Comparator2 Asynchronous Output Enable 0 Asynchronous CP2 unavailable at Port pin 1 Asynchronous CP2 routed to Port pin 2 CP2E Comparator2 Output Enable 0 CP2 unavailable at Port pin 1 CP2 routed to Port pin 1 URT1E UART1 I O Output Enable 0 UART1 unavailable at Port pin 1 UART1 routed to Port pins 0 LINOE LIN I O Output Enable 0 LIN I O unavailable at Port pin 1 LIN TX LIN RX routed to Port pins SILICON LABS Rev 1 3 198 8051 58 59 SFR Definition 20 4 XBR3 Port Crossbar Register Bit 7 6 5 4 3 2 1 0 T5E T4EXE T4E 1 2 0 R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xC6 SFR Page OxOF Bit Name Function 7 T5EX Enable 0 T5EX unavailable at Port pin 1 T5EX routed to Port pin 6 T5EX T5E Enable 0 T5E unavailable at Port pin 1 T5E routed to Port pin 5 T4EXE T4EX Enable 0 T4EX unavailable at Port pin 1 T4EX routed to Port pin 4 T5EX T4E Enable 0 T4E unavailable at P
225. W R W R W R W R W R W R Reset 0 0 0 0 0 0 0 0 SFR Address 0 00 SFR Page All Pages Bit Addressable Bit Name Function 7 CY Carry Flag This bit is set when the last arithmetic operation resulted in a carry addition or a bor row subtraction It is cleared to logic 0 by all other arithmetic operations 6 AC Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into addition or a borrow from subtraction the high order nibble It is cleared to logic 0 by all other arith metic operations 5 FO User Flag 0 This is a bit addressable general purpose flag for use under software control 4 3 RS 1 0 Register Bank Select These bits select which register bank is used during register accesses 00 Bank 0 Addresses 0x00 0x07 01 Bank 1 Addresses 0x08 0x0F 10 Bank 2 Addresses 0x10 0x17 11 Bank 3 Addresses 0x18 0x1F 2 OV Overflow Flag This bit is set to 1 under the following circumstances AnADD or SUBB instruction causes a sign change overflow m A MUL instruction results in an overflow result is greater than 255 m ADIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases 1 F1 User Flag 1 This is a bit addressable general purpose flag for use under software control 0 PARITY Parity Flag This bit is set to logic 1 if the sum of the eight bits in the accumu
226. When in 3 wire master or 3 wire slave mode the NSS pin will not be mapped by the crossbar In all other modes the NSS signal will be mapped to a pin on the device See Section 20 Port Input Output on page 188 for general purpose port I O and crossbar information 273 Rev 1 3 SILICON LABS 8051 58 59 26 2 SPIO Master Mode Operation A SPI master device initiates all data transfers on a SPI bus SPIO is placed in master mode by setting the Master Enable flag MSTEN SPIOCN 6 Writing a byte of data to the SPIO data register SPIODAT when in master mode writes to the transmit buffer If the SPI shift register is empty the byte in the transmit buffer is moved to the shift register and a data transfer begins The SPIO master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK The SPIF SPIOCN 7 flag is set to logic 1 at the end of the transfer If interrupts are enabled an interrupt request is generated when the SPIF flag is set While the SPIO master transfers data to a slave on the MOSI line the addressed SPI slave device simultaneously transfers the contents of its shift register to the master on the MISO line in a full duplex operation Therefore the SPIF flag serves as both a transmit complete and receive data ready flag The data byte received from the slave is transferred MSB first into the master s shift register When a byte is fully shifted into the register it is
227. With a divider of 4 the read must wait 3 system clock cycles and with the divider set to 8 the read must wait 7 system clock cycles The delay only needs to be applied when read ing the same register that was written The application can write and read other CAN SFRs without any delay 22 1 3 Example Timing Calculation for 1 Mbit Sec Communication This example shows how to configure the CAN controller timing parameters for a 1 Mbit Sec bit rate Table 18 1 shows timing related system parameters needed for the calculation Table 22 1 Background System Information Parameter Value Description CIP 51 system clock SYSCLK 24 MHz Internal Oscillator Max CAN controller clock fsys 24 MHz CANOCFG divider set to 1 CAN clock period tsys 41 667 ns Derived from 1 fsys CAN time quantum ta 41 667 ns Derived from tsys x BRP CAN bus length 10m 5 ns m signal delay between CAN nodes Propogation delay time 400 ns 2 x transceiver loop delay bus line delay Notes 1 The CAN time quantum is the smallest unit of time recognized by the CAN controller Bit timing parameters are specified in integer multiples of the time quantum 2 The Baud Rate Prescaler BRP is defined as the value of the BRP Extension Register plus 1 The BRP extension register has a reset value of 0x0000 The BRP has a reset value of 1 3 Based on an ISO 11898 compliant transceiver CAN does not specify a physical layer Each bit transmit
228. a bit for the oldest byte in the FIFO be read from the RBXO bit SCONO 2 If the extra bit function is not enabled the value of the stop bit for the oldest FIFO byte will be presented in RBXO When the parity func tion is enabled PEO 1 hardware will check the received parity bit against the selected parity type selected with SOPT 1 0 when receiving data If a byte with parity error is received the PERRO flag will be set to 1 This flag must be cleared by software Note when parity is enabled the extra bit function is not available Note The UART Receive FIFO pointer can be corrupted if the UART receives a byte and firmware reads a byte from the FIFO at the same time When this occurs firmware will lose the received byte and the FIFO receive overrun flag OVRO will also be set to 1 Systems using the UART Receive FIFO should ensure that the FIFO isn t accessed by hardware and firmware at the same time In other words firmware should ensure to read the FIFO before the next byte is received 24 3 3 Multiprocessor Communications UARTO supports multiprocessor communication between a master processor and one or more slave pro cessors by special use of the extra data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic O Setting the
229. a in the register remains stable as long as the SI flag is set When the SI flag is not set the system may be in the process of shifting data in out and the CPU should not attempt to access this register 23 5 SMBus Transfer Modes The SMBus interface may be configured to operate as master and or slave At any particular time it will be operating in one of the following four modes Master Transmitter Master Receiver Slave Transmitter or Slave Receiver The SMBus interface enters Master Mode any time a START is generated and remains in Master Mode until it loses an arbitration or generates a STOP An SMBus interrupt is generated at the end of all SMBus byte frames As a receiver the interrupt for an ACK occurs before the ACK As a transmitter interrupts occur after the ACK Rev 1 3 249 SILICON LABS 8051 58 59 23 5 1 Write Sequence Master During a write sequence an SMBus master writes data to a slave device The master in this transfer will be a transmitter during the address byte and a transmitter during all data bytes The SMBus interface gener ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 0 WRITE The master then trans mits one or more bytes of serial data After each byte is transmitted an acknowledge bit is generated by the slave The transfer is ended when the STO
230. a memory Figure 12 1 illustrates the data memory organization of the C8051F58x F59x 12 2 1 1 General Purpose Registers The lower 32 bytes of data memory locations 0x00 through 0x1 F may be addressed as four banks of gen eral purpose registers Each bank consists of eight byte wide registers designated RO through R7 Only one of these banks may be enabled at a time Two bits in the program status word RSO PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in SFR Definition 11 6 This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers RO and R1 as index registers 12 2 1 2 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through Ox2F are also accessible as 128 individually addressable bits Each bit has a bit address from 0x00 to Ox7F Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at Ox2F has bit address Ox7F A bit access is distinguished from a full byte access by the type of instruction used bit source or destination operands as opposed to a byte source or destina tion The MCS 51 assembly language allows an alternate notation for bit addressing of the form XX B where XX is the byte address and B is the bit position within the byte For example the instruction MOV C
231. ach data byte or slave address that is transferred The point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver When a transmitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the received ACK value when receiving data i e receiving address data sending an this interrupt is generated before the ACK cycle so that software may define the outgo ing ACK value See Section 23 5 for more details on transmission sequences Interrupts are also generated to indicate the beginning of a transfer when a master START generated or the end of a transfer when a slave STOP detected Software should read the SMBOCN SMBus Control register to find the cause of the SMBus interrupt The SMBOCN register is described in Section 23 4 2 Table 23 4 provides a quick SMBOCN decoding reference 23 4 1 SMBus Configuration Register The SMBus Configuration register SMBOCF is used to enable the SMBus Master and or Slave modes select the SMBus clock source and select the SMBus timing and timeout options When the ENSMB bit is set the SMBus is enabled for all master and slave events Slave events may be disabled by setting the INH bit With slave events inhibited the SMBus interface will still monitor the SCL and SDA pins however the interface will NACK all received addresses and will not generate any slave interrupts When
232. ad PCA1CPH Ln Write to right justified PCA1CPHn gt A R W wh x Capture Compare Y i Set N bits lt PCA1CPH Ln 9bi 01 9bits right justified 10 10 bits 11 11 bits P W M 1 6 1 n 0 ME sq Ki Overflow of N Bit N bit Comparator 1 Timebase m I PCA1H L Figure 29 9 PCA1 9 10 and 11 Bit PWM Mode Diagram Rev 1 3 343 SILICON LABS 8051 58 59 29 3 6 16 Bit Pulse Width Modulator Mode A PCA1 module may also be operated in 16 Bit PWM mode 16 bit PWM mode is independent of the other 8 9 10 11 bit PWM modes In this mode the 16 bit capture compare module defines the number of PCA1 clocks for the low time of the PWM signal When the PCA1 counter matches the module contents the out put on CEXn is asserted high when the 16 bit counter overflows CEXn is asserted low To output a vary ing duty cycle new value writes should be synchronized with PCA1 CCFn match interrupts 16 Bit PWM Mode is enabled by setting the ECOM1n PWM1n and PWM161n bits in the PCA1CPMn register For varying duty cycle match interrupts should be enabled ECCF1n 1 AND MAT1n 1 to help synchronize the capture compare register writes If the MAT1n bit is set to 1 the CCFn flag for the module will be set each time a 16 bit comparator
233. ad only register 2 Write enabled by CCE 3 The reset value of CANOTST could also be r0000000b where r signifies the value of the CAN RX pin 4 Write enabled by Test 236 Rev 1 3 SILICON LABS 8051 58 59 Table 22 2 Standard CAN Registers and Reset Values Continued CAN Name SFR Name SFR SFRName SFR 16 bit Reset Addr High Addr Low Addr SFR Value 0x50 IF2 Data A 2 CANOIF2DA2H OxFB CANOIF2DA2L CANOIF2DA2 0 0000 0x52 Data B 1 CANOIF2DB1H OXFD CANOIF2DB1L OxFC CANOIF2DB1 0x0000 0x54 IF2 Data B2 CANOIF2DB2H OxFF CANOIF2DB2L CANOIF2DB2 0x0000 0x80 Transmission Request 1 CANOTR1H 0xA3 CANOTR1L OxA2 CANOTR1 0x0000 0x82 Transmission Request 2 CANOTR2H 5 CANOTR2L 0 4 CANOTR2 0 0000 0x90 New Data 1 CANOND1H CANOND1L OxAA CANOND1 0 0000 0x92 New Data 2 CANOND2H OxAD CANOND2L 0 CANOND2 0x0000 OxAO JInterrupt Pending 1 CANOIP1H CANOIP1L CANOIP1 0 0000 OxA2 Interrupt Pending 2 1 CANOIP2H CANOIP2L 2 CANOIP2 0x0000 OxBO Message Valid 1 CANOMV1H CANOMV1L CANOMV1 0x0000 0 2 Message Valid 2 CANOMV2H OxBD CANOMV2L 0xBC 0 0000 Notes 1 Read only register 2 Write enabled by CCE 3 The reset value of CANOTST could also be r0000000b whe
234. allowing PCAO to be clocked by a precision external oscillator while the internal oscillator drives the system clock PCAO is configured and controlled through the system controller s Spe cial Function Registers The PCAO block diagram is shown in Figure 28 1 Important Note PCAO Module 5 may be used as a watchdog timer WDT and is enabled in this mode following a system reset Access to certain PCAO registers is restricted while WDT mode is enabled See Section 28 4 for details SYSCLK 12 SYSCLK 4 Timer 0 Overflow SYSCLK External Clock 8 b 16 Bit Counter Timer Timer 4 Overflow Timer 5 Overflow Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Module 0 Module 1 Module 2 Module 3 Module 4 Module 5 WDT m Q m m m m m m gt gt gt gt gt gt N wo Crossbar CoD tee 1 Port I O 1 Figure 28 1 PCA0 Block Diagram Rev 1 3 314 SILICON LABS C8051F58x F59x 28 1 PCAO Counter Timer The 16 bit PCAO counter timer consists of two 8 bit SFRs PCAOL and PCAOH PCAOH is the high byte MSB of the 16 bit counter timer and PCAOL is the low byte LSB Reading PCAOL automatically latches the value of PCAOH into a snapshot register the following PCAOH read accesses this snapshot register Reading the PCAOL Register first guarantees an accurate r
235. als P0 1 128 or 96 kB Flash UARTO E Program C2CK RST X Debug 9 y Drivers dii Programming P05 C2D Hardware 256 Byte RAM Timers 0 B 1 2 3 4 5 0 6 E P0 7 8 kB XRAM 2x6 Priority channel Crossbar P1 0 PCA WDT Decoder P1 1 P1 2 Voltage Regulator P1 3 LDO CAN 2 0B P1 4 P1 5 VDD P1 6 GND x P1 7 SFR Crossbar Control P2 0 Bus P2 1 System Clock Setup External Memory Interface 2 2 XTAL1 XTAL2 On F580 4 devices P2 3 P2 4 Analog Peripherals Internal Oscillator External Oscillator 9 dee i Clock Multiplier Reference yREF P3 0 P3 1 P3 2 VDD o o VREF P3 3 VDD P3 4 A VREF P3 5 M P0 P3 6 s Temp P3 7 Sensor GND P4 0 CP0 CP0A 4 P4 1 Comparator 0 ibis VDDA e xcd Drivers P44 GNDA CP2 CP2A q P4 5 L Comparator 2 P4 6 P4 7 Figure 1 1 C8051F580 1 4 5 Block Diagram 19 Rev 1 3 SILICON LABS 8051 58 59 Power On CIP 51 8051 Port I O Configuration v i Reset Digital Peripherals 128 or 96 Flash ARTI LUNES Port 0 P0 3 C2CK RST Debug UARTI le Drivers P0 4 Programming lt P05 Hardware 256 Byte RAM Timers 0 PN 06 1 2 3 4 5 20 x E 8 kB XRAM
236. ame Function 7 0 TLO 7 0 Timer 0 Low Byte The TLO register is the low byte of the 16 bit Timer 0 SFR Definition 27 5 TL1 Timer 1 Low Byte Bit 7 6 5 4 3 2 1 0 Name TL1 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x8B SFR Page All Pages Bit Name Function 7 0 TL1 7 0 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 SILICON LABS Rev 1 3 293 8051 58 59 SFR Definition 27 6 THO Timer 0 High Byte Bit 7 6 5 4 1 0 Name THO 7 0 Reset 0 0 0 0 0 0 SFR Address 0x8C SFR Page All Pages Bit Name Function 7 0 THO 7 0 Timer 0 High Byte The THO register is the high byte of the 16 bit Timer 0 SFR Definition 27 7 TH1 Timer 1 High Byte Bit 7 6 5 4 1 0 Name TH1 7 0 Type R W Reset 0 0 0 0 0 0 SFR Address 0x8D SFR Page All Pages Bit Name Function 7 0 TH1 7 0 Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 294 Rev 1 3 SILICON LABS 8051 58 59 27 2 Timer 2 Timer 2 is a 16 bit timer formed by two 8 bit SFRs TMR2L low byte and TMR2H high byte Timer 2 may operate in 16 bit auto reload mode or split 8 bit auto reload mode The T2SPLIT
237. and Timer 1 are nearly identical and have four primary modes of oper ation Timer 2 and Timer 3 offer 16 bit and split 8 bit timer functionality with auto reload Timer 4 and Timer 5 have 16 bit auto reload and capture and can also produce a 50 duty cycle square wave toggle output at an general purpose port pin Timer 0 and Timer 1 Modes Timer 2 and 3 Modes Timer 4 and 5 Modes 13 bit counter timer 16 bit timer with auto reload 16 bit timer with auto reload 16 bit counter timer 8 bit counter timer with Two 8 bit timers with auto reload 16 bit counter timer with capture auto reload Two 8 bit counter timers Timer 0 Toggle Output only Timers 0 and 1 may be clocked by one of five sources determined by the Timer Mode Select bits 1 TOM and the Clock Scale bits SCA1 SCAO The Clock Scale bits define a pre scaled clock from which Timer 0 and or Timer 1 be clocked See SFR Definition 27 1 for pre scaled clock selection Timer 0 1 may then be configured to use this pre scaled clock signal or the system clock Timer 2 and Timer 3 may be clocked by the system clock the system clock divided by 12 or the external oscillator clock source divided by 8 Timer 4 and Timer 5 may be clocked by the system clock system clock divided by 2 or 12 or the external oscillator clock source divided by 8 Timers 0 1 4 and 5 may also be operated as counters When functioning as a counter a counter timer register
238. any external oscillator source Note Small surface mount crystals can have maximum drive level specifications that are exceeded by the above XFCN recommendations In these cases a software controlled startup sequence may be used to reliably start the crystal using a higher XFCN setting and then lowering the setting once the oscillator has started to reduce the drive level and prevent damage or premature aging of the crystal In all cases the drive level should be measured to ensure that the crystal is being driven within its operational guidelines as part of robust oscillator system design Contact technical support for additional details and recommendations if using surface mount crystals with these devices When the crystal oscillator is first enabled the oscillator amplitude detection circuit requires a settling time to achieve proper bias Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior The rec ommended procedure is 1 Force XTAL1 and XTAL2 to a high state This involves enabling the Crossbar and writing 1 to the port pins associated with XTAL1 and XTAL2 Configure XTAL1 and XTAL2 as analog inputs using Enable the external oscillator Wait at least 1 ms Poll for XTLVLD gt 1 Enable the
239. are module s operating mode All modules set to use 8 9 10 or 11 bit PWM mode must use the same cycle length 8 11 bits Setting the ECCFin bit in a PCA1CPMnh register enables the module s CCFn interrupt Table 29 2 PCA1CPM and PCA1PWM Bit Settings for PCA1 Capture Compare Modules Operational Mode PCA1CPMn PCA1PWM Bit Number 7 6 5 4 3 2 1 0 7 6 5 42 1 0 Capture triggered by positive edge on CEXn X 1 0 0 0 0 0 X B XX Capture triggered by negative edge on CEXn X 0 1 0 0 0 A 0 1 X BI XX Capture triggered by any transition on CEXn X X 1 1 010 X IB XX Software Timer X C 010 11010 0 X B XX High Speed Output X C 0101 11110 A 0 X B XX Frequency Output X C 01 0 01111 A 01 X B XX 8 Bit Pulse Width Modulator Note 7 E 0 1 00 9 Bit Pulse Width Modulator Note 7 E 0 1 Aj XXX 01 10 Bit Pulse Width Modulator Note 7 E0 1 ADD XB XXX 10 11 Bit Pulse Width Modulator Note 7 0 0 0 E 0 1 XXX 11 16 Bit Pulse Width Modulator 11 E 0 1 A 0 X BI XX Notes 1 X Don t Care no functional difference for individual module if 1 or 0 2 A Enable interrupts for this module PCA1 interrupt triggered on CCFn set to 1 3 Enable 8th 9th 10th or 11th bit overflow interrupt Depends on setting of CLSEL1 1 0 4
240. aster The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 26 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMDO bits in the SPIOCN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master 3 Wire Slave Mode SPIO operates in 3 wire mode and NSS is disabled When operating as a slave device SPIO is always selected in 3 wire mode Since no select signal is present SPIO must be the only slave on the bus in 3 wire mode This is intended for point to point communication between a master and one slave 2 NSSMD 1 0 01 4 Wire Slave or Multi Master Mode SPIO operates in 4 wire mode and NSS is enabled as an input When operating as a slave NSS selects the SPIO device When operating as a master a 1 to 0 transition of the NSS signal disables the master function of SPIO so that multiple master devices can be used on the same SPI bus 3 NSSMD 1 0 1x 4 Wire Master Mode SPIO operates in 4 wire mode and NSS is enabled as an output The setting of NSSMDO determines what logic level the NSS pin will output This configuration should only be used when operating SPIO as a master device See Figure 26 2 Figure 26 3 and Figure 26 4 for typical connection diagrams of the various operational modes Note that the setting of NSSMD bits affects the pinout of the device
241. ate of the Port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture PCA1 Interrupt r PCA1CPMn W 1 1 n n x 3 o j U PCA1CPLn PCA1CPHn 0 Co 1 x o o Port X Crossbar gt 1 POM 1 Timebase Figure 29 4 PCA1 Capture Mode Diagram Note The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware Rev 1 3 337 SILICON LABS 8051 58 59 29 3 2 Software Timer Compare Mode In Software Timer mode the PCA1 counter timer value is compared to the module s 16 bit capture com pare register PCA1CPHn and PCA1CPLn When a match occurs the Capture Compare Flag CCFn in PCAICN is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser vice routine and must be cleared by software Setting the ECOM1n and MAT 1n bits in the PCA1CPMn register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA1 Cap ture Compare registers the low byte should always be written first Writi
242. atei S Q Crossbar Port gt bll R CLR Q PCAO Timebase ELT Timebase yh PCAOH L Overflow of N Bit Figure 28 9 PCAO 9 10 and 11 Bit PWM Mode Diagram 28 3 6 16 Bit Pulse Width Modulator Mode A PCAO module may also be operated 16 Bit PWM mode 16 bit PWM mode is independent of the other 8 9 10 11 bit PWM modes In this mode the 16 bit capture compare module defines the number of PCAO clocks for the low time of the PWM signal When the PCAO counter matches the module contents the out put on CEXn is asserted high when the 16 bit counter overflows CEXn is asserted low To output a vary ing duty cycle new value writes should be synchronized with PCAO CCFn match interrupts 16 Bit PWM Mode is enabled by setting the ECOMn PWMn PWM16n bits in the PCAOCPMn register For a vary ing duty cycle match interrupts should be enabled ECCFn 1 AND 1 to help synchronize the capture compare register writes If the MATn bit is set to 1 the CCFn flag for the module will be set each time a 16 bit comparator match rising edge occurs The CF flag in PCAOCN can be used to detect the overflow falling edge The duty cycle for 16 Bit PWM Mode is given by Equation 28 4 Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Cap ture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 wr
243. ation 4 Set the RSTINT LINOCTRL 3 and RSTERR bits LINOCTRL 2 to reset the interrupt request and the error flags 21 4 LIN Slave Mode Operation When the device is configured for slave mode operation it must wait for a command from a master node Access from the firmware to the data buffer and ID registers of the LIN controller is only possible when a data request is pending DTREQ bit LINOST 4 is 1 and also when the LIN bus is not active ACTIVE bit LINOST 7 is set to 0 The LIN controller in slave mode detects the header of the message frame sent by the LIN master If slave synchronization is enabled autobaud the slave synchronizes its internal bit time to the master bit time The LIN controller configured for slave mode will generated an interrupt in one of three situations 1 After the reception of the IDENTIFIER FIELD 2 When an error is detected 3 When the message transfer is completed The application should perform the following steps when an interrupt is detected 1 Check the status of the DTREQ bit LINOST 4 This bit is set when the IDENTIFIER FIELD has been received 2 If DTREQ LINOST 4 is set read the identifier from LINOID and process it If DTREQ LINOST 4 is not set continue to step 7 3 Set the TXRX bit LINOCTRL 5 to 1 if the current frame is a transmit operation for the slave and set to 0 if the current frame is a receive operation for the slave 4 Load the data length into LINOSIZE 5
244. ator Connection Diagram 186 Figure 20 1 Port I O Functional Block Diagram 189 Figure 20 2 Port I O Cell Block Diagram 190 Figure 20 3 Peripheral Availability on Port I O Pins 193 Figure 20 4 Crossbar Priority Decoder in Example Configuration 194 Figure 21 1 LIN Block Diagram mieu Qo ase E ccrte deett 214 Figure 22 1 Typical CAN BUS Configuration 231 Figure 22 2 CAN Controller 232 Figure 22 3 Four segments of a BI auia tnter tnn euet aero anu 234 Figure 23 1 SMBus Block Diagram 000 0 239 Figure 23 2 Typical SMBus Configuration 240 Figure 23 3 SMBus Transaction 02 0 4 4 241 Figure 23 4 Typical SMBus SCL 243 Figure 23 5 Typical Master Write Sequence 2222222222222 250 Figure 23 6 Typical Master Read Sequence 251 Figure 23 7 Typical Slave Write Sequence 252 Figure 23 8 Typical Slave Read Sequence 253 Figure 24 1 UARTO Block
245. ave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE1 bit to ignore all transmis sions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Slave Device Master Slave Slave Device Device Device OOO Figure 25 6 UART Multi Processor Mode Interconnect Diagram 268 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 25 1 SCON1 Serial Port 1 Control SILICON LABS Bit 7 6 5 4 3 2 1 0 Name STMODE MCE1 REN1 TB81 RB81 TH R W R R W R W R W R W R W R W Reset 0 1 0 0 0 0 0 0 SFR Address 0x98 SFR Page 0x10 Bit Addressable Bit Name Function 7 SIMODE Serial Port 1 Operation Mode Selects the UART1 Operation Mode 0 8 bit UART with Variable Baud Rate 1 9 bit UART with Variable Baud Rate 6 Unused Read 1b Write Don t Care 5 MCE1 Multiprocessor Communication Enable
246. b cannot change state while the target device is halted 2 The RST pin on the target device is used as an input only Additional resistors may be necessary depending on the specific application Rev 1 3 355 SILICON LABS 8051 58 59 DOCUMENT CHANGE LIST Revision 0 1 to Revision 1 0 Updated all specification TBDs Clarified and corrected text throughout the document Revision 1 0 to Revision 1 1 Updated Ordering Information on page 22 to include A Automotive devices and automotive qualification information Updated supply current related specifications throughout 5 Electrical Characteristics Updated SFR Definition 8 1 to change VREF high setting to 2 20 V from 2 25 V Updated Table 5 13 on page 53 and Figure 9 1 on Page 77 to indicate that Comparators are powered from Vig and not Updated the Gain Table in Calculating the Gain Value on page 60 to fix the ADCOGNH Value in the last row Updated Table 11 1 on page 94 with correct timing for all branch instructions MOVC and CPL A Updated Programming The Flash Memory on page 138 to clarify behavior of 8 bit MOVX instructions and when writing erasing Flash Updated SFR Definition 15 3 FLSCL to include FLEWT bit definition This bit must be set before writing or erasing Flash Also updated Table 5 5 on page 48 to reflect new Flash Write and Erase timing Updated 17 7 Flash Error Reset with an additional cause of a Flash Error reset
247. bit MOVX with Bank Select EMIOCF 4 2 110 169 18 6 2 Multiplexed Mode 170 18 6 2 1 16 bit MOVX EMIOCF 4 2 001 010 or 011 170 18 6 2 2 8 bit MOVX without Bank Select EMIOCF 4 2 001 or 011 171 18 6 2 3 8 bit MOVX with Bank Select EMIOCF 4 2 010 172 19 Oscillators and Clock Selection T 174 19 T System Clock SONS CWO 174 19 2 Programmable Internal 176 19 2 1 Internal Oscillator Suspend 176 weed user c 179 19 4 External Oscillator Drive 181 19 4 1 External Crystal Example 183 19 4 2 External RC ne 184 19 4 3 External Capacitor Example sss 184 20 Port I put Output 186 20 1 Port I O Modes of 188 20 1 1 Port Pins Configured for Analog 188 20 1 2 Port Pins Configured For Digital 188 20 1 3 Interfacing Port I O in a Mu
248. ble 20 2 Port I O Assignment for Digital Functions 189 Table 20 3 Port I O Assignment for External Digital Event Capture Functions 190 Table 21 1 Baud Rate Calculation Variable Ranges 213 Table 21 2 Manual Baud Rate Parameters Examples 215 Table 21 3 Autobaud Parameters Examples 216 Table 21 4 LIN Registers Indirectly Addressable 221 Table 22 1 Background System Information 2 231 Table 22 2 Standard CAN Registers and Reset Values 234 Rev 1 3 12 SILICON LABS 8051 58 59 Table 23 1 Table 23 2 Table 23 3 Table 23 4 Table 24 1 Table 25 1 Table 26 1 Table 28 1 Table 28 2 Table 28 3 Table 29 1 Table 29 2 SMBus Clock Source Selection 241 Minimum SDA Setup and Hold Times 242 Sources for Hardware Changes to SMBOON 246 SMBUS Status Decoding cacao rne nete 252 Baud Rate Generator Settings for Standard Baud Rates 255 Timer Settings for Standard Baud Rates Using The Internal 24 MHz Oscillator 269 SPI Slave Ti
249. both CAPPn and CAPNn bits are set to logic 1 then the state of the Port pin associated with CEXn can be read directly to determine whether a rising edge or fall ing edge caused the capture 317 Rev 1 3 SILICON LABS 8051 58 59 Interrupt NUN Note The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware 28 3 2 Software Timer Compare Mode In Software Timer mode the PCAO counter timer value is compared to the module s 16 bit capture com pare register and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser vice routine and must be cleared by software Setting the ECOMn and MATn bits in the PCAOCPMn regis ter enables Software Timer mode Timebase Figure 28 4 PCAO Capture Mode Diagram Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Cap ture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 Rev 1 3 318 SILICON LABS 8051 58
250. byte MOV direct Rn Move Register to direct byte MOV direct direct Move direct byte to direct byte MOV direct Ri Move indirect RAM to direct byte MOV direct data Move immediate to direct byte MOV Ri A Move A to indirect RAM MOV direct MOV Ri data Move direct byte to indirect RAM Move immediate to indirect RAM MOV DPTR data16 Load DPTR with 16 bit constant MOVC A A DPTR Move code byte relative DPTR to A MOVC A A PC Move code byte relative PC to A MOVX A Ri Move external data 8 bit address to A MOVX Ri A Move A to external data 8 bit address MOVX A DPTR Move external data 16 bit address to A MOVX DPTR A Move A to external data 16 bit address DOF N G5 N NI DOJ CO NI mo N PO Gd GO CO N PO NI OO N Cd PO NI N NI PO N N PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A Rn Exchange Register with A XCH A direct Exchange direct byte with A XCH A Ri Exchange indirect RAM with A XCHD A Ri Exchange low nibble of indirect RAM with A Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 Note Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and the FLRT setting SFR
251. c ment Change 354 Contact Information u u 356 8 Rev 1 3 SILICON LABS 8051 58 59 List of Figures Figure 1 1 C8051F580 1 4 5 Block Diagram 19 Figure 1 2 C8051F588 9 F590 1 Block Diagram 20 Figure 1 3 C8051F582 3 6 7 Block Diagram 21 Figure 3 1 QFP 48 Pinout Diagram Top 27 Figure 3 2 QFN 48 Pinout Diagram Top View 2 28 Figure 3 3 QFN 40 Pinout Diagram Top View 2 29 Figure 3 4 QFP 32 Pinout Diagram Top View 30 Figure 3 5 QFN 32 Pinout Diagram View 2 31 Figure 4 1 QFP 48 Package 32 Figure 4 2 QFP 48 Landing Diagram 33 Figure 4 3 QFN 48 Package Drawing 34 Figure 4 4 QFN 48 Landing Diagram eene 35 Figure 4 5 Typical QFN 40 Package Drawing 2 2 36 Figure 4 6 QFN 40 Landing Diagram a 37 Figure 4 7 QFP 32 Package Drawing aa 38 Figure 4 8 QFP 32 Package Drawing 000 39 Figure 4 9 OFN 32 Package Drawing
252. caused the overrun is lost Rev 1 3 276 SILICON LABS 8051 58 59 26 5 Serial Clock Phase and Polarity Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPIO Configuration Register SPIOCFG The CKPHA bit SPIOCFG 5 selects one of two clock phases edge used to latch the data The CKPOL bit SPIOCFG 4 selects between an active high or active low clock Both master and slave devices must be configured to use the same clock phase and polarity SPIO should be disabled by clearing the SPIEN bit SPIOCN 0 when changing the clock phase or polarity The clock and data line relationships for master mode are shown in Figure 26 5 For slave mode the clock and data relationships are shown in Figure 26 6 and Figure 26 7 CKPHA must be set to 0 on both the master and slave SPI when communicating between two of the following devices C8051F04x C8051F06x C8051F12x C8051F31x C8051F32x and C8051F33x The SPIO Clock Rate Register SPIOCKR as shown in SFR Definition 26 3 controls the master mode serial clock frequency This register is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the mas
253. ccessed anytime the direct addressing mode is used to access memory locations from 0x80 to OxFF SFRs with addresses ending in 0x0 or 0x8 e g PO TCON SCONO IE etc are bit addressable as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing unoccupied addresses in the SFR space will have an indeterminate effect and should be avoided Refer to the corresponding pages of the data sheet as indicated in Table 13 3 for a detailed description of each register 13 1 SFR Paging The CIP 51 features SFR paging allowing the device to map many SFRs into the 0x80 to OxFF memory address space The SFR memory space has 256 pages In this way each memory location from 0x80 to OxFF can access up to 256 SFRs The C8051F58x F59x family of devices utilizes three SFR pages 0x0 OxC and OxF SFR pages are selected using the Special Function Register Page Selection register SFRP AGE see SFR Definition 11 3 The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page number using the SFRPAGE register 2 Use direct accessing mode to read or write the special function register MOV instruction 13 2 Interrupts and SFR Paging When an interrupt occurs the SFR Page Register will automatically switch to the SFR page containing the flag bit that caused the interrupt The automatic SFR Page switch function conveniently removes the bur
254. ceived The bit counter can only be reset by disabling and re enabling SPIO with the SPIEN bit Figure 26 3 shows a connection diagram between a slave device in 3 wire slave mode and a master device 26 4 SPIO Interrupt Sources When SPIO interrupts are enabled the following four flags will generate an interrupt when they are set to logic 1 All of the following bits must be cleared by software 1 The SPI Interrupt Flag SPIF SPIOCN 7 is set to logic 1 at the end of each byte transfer This flag can occur in all SPIO modes 2 The Write Collision Flag WCOL SPIOCN 6 is set to logic 1 if a write to SPIODAT is attempted when the transmit buffer has not been emptied to the SPI shift register When this occurs the write to SPIODAT will be ignored and the transmit buffer will not be written This flag can occur in all SPIO modes 3 The Mode Fault Flag MODF SPIOCN 5 is set to logic 1 when SPIO is configured as a master and for multi master mode and the NSS pin is pulled low When a Mode Fault occurs the MSTEN and SPIEN bits in SPIOCN are set to logic 0 to disable SPIO and allow another master device to access the bus 4 The Receive Overrun Flag RXOVRN SPIOCN 4 is set to logic 1 when configured as a slave and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer The new byte is not transferred to the receive buffer allowing the previously received data byte to be read The data byte which
255. ch Enable signal which is driven by the External Memory Interface logic An example of a Multiplexed Configuration is shown in Figure 18 1 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are pre sented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning of the second phase the address latch outputs remain fixed and are no longer dependent on the latch inputs Later in the second phase the Data Bus controls the state of the AD 7 0 port at the time RD or WR is asserted See Section 18 6 2 Multiplexed Mode on page 172 for more information Figure 18 1 Multiplexed Configuration Example Rev 1 3 164 SILICON LABS 8051 58 59 18 4 2 Non multiplexed Configuration In Non multiplexed mode the Data Bus and the Address Bus pins are not shared An example of a Non multiplexed Configuration is shown in Figure 18 2 See Section 18 6 1 Non Multiplexed Mode on page 169 for more information about Non multiplexed operation Figure 18 2 Non multiplexed Configuration Example 165 Rev 1 3 SILICON LABS 8051 58 59 18 5 Memory Mode Selection The external data memory space can be configured in one of four modes shown in Figure 18 3 based
256. chronous serial bus SPIO can operate as a master or slave device in both 3 wire or 4 wire modes and supports mul tiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select SPIO in slave mode or to disable Master Mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode 2 SFR Bus 2 SPIOCKR SPIOCFG SPIOCN Zizo zz EEAS 85589058 0552256 209202029 562552256 Divide SPI CONTROL LOGIC SPI IRQ Data Path Pin Interface Control Control TeData MOS 1 E SPIODAT Transmit Data Buffer Control E Port I O Shift Register Logic 7 6 5 4 3 2 1 225 B Receive Data Buffer NSS Lester MEL ZN 2 SFR Bus Figure 26 1 SPI Block Diagram Rev 1 3 272 SILICON LABS 8051 58 59
257. ck When BURSTEN is logic 1 FCLK is derived from the Burst Mode Oscillator an independent clock source with a maximum frequency of 25 MHz When ADCO is performing a conversion it requires a clock source that is typically slower than FCLK The ADCO SAR conversion clock SAR clock is a divided version of FCLK The divide ratio can be configured using the ADOSC bits in the ADCOCF register The maximum SAR clock frequency is listed in Table 5 10 ADCO can be in one of three states at any given time tracking converting or idle Tracking time depends on the tracking mode selected For Pre Tracking Mode tracking is managed by software and ADCO starts conversions immediately following the convert start signal For Post Tracking and Dual Tracking Modes the tracking time after the convert start signal is equal to the value determined by the ADOTK bits plus 2 FCLK cycles Tracking is immediately followed by a conversion The ADCO conversion time is always 13 SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion Figure 6 4 shows timing diagrams for a conversion in Pre Tracking Mode and tracking plus conversion in Post Tracking or Dual Tracking Mode In this example repeat count is set to one Rev 1 3 56 SILICON LABS 8051 58 59 Convert Start Pre Tracking Mode Time ADCO State Convert ADOINT Flag Post Tracking or Dual Tracking Modes ADOTK 007 Time ADCO State ADOINT
258. ck Diagram The LIN controller has four main components LIN Access Registers Provide the interface between the MCU core and the LIN controller LIN Data Registers Where transmitted and received message data bytes are stored LIN Control Registers Control the functionality of the LIN interface Control State Machine and Bit Streaming Logic Contains the hardware that serializes messages and controls the bus timing of the controller Rev 1 3 214 SILICON LABS 8051 58 59 21 1 Software Interface with the LIN Controller The selection of the mode Master or Slave and the automatic baud rate feature are done though the LINO Control Mode LINOCF register The other LIN registers are accessed indirectly through the two SFRs LINO Address LINOADR and LINO Data LINODAT The LINOADR register selects which LIN register is targeted by reads writes of the LINODAT register The full list of indirectly accessible LIN registers is given in Table 21 4 on page 223 21 2 LIN Interface Setup and Operation The hardware based LIN controller allows for the implementation of both Master and Slave nodes with minimal firmware overhead and complete control of the interface status while allowing for interrupt and polled mode operation The first step to use the controller is to define the basic characteristics of the node Mode Master or Slave Baud Rate Either defined manually or using the autobaud feature slave mode only Check
259. cle 0001 WR and RD RD pulse width 2 SYSCLK cycles 0010 WR and RD pulse width 3 SYSCLK cycles 0011 WR and RD pulse width 4 SYSCLK cycles 0100 WR and RD pulse width 5 SYSCLK cycles 0101 WR and RD pulse width 6 SYSCLK cycles 0110 WR and RD pulse width 7 SYSCLK cycles 0111 WR and RD pulse width 8 SYSCLK cycles 1000 WR and RD pulse width 9 SYSCLK cycles 1001 WR and RD pulse width 10 SYSCLK cycles 1010 WR and RD pulse width 11 SYSCLK cycles 1011 WR and RD pulse width 12 SYSCLK cycles 1100 WR and RD pulse width 13 SYSCLK cycles 1101 WR and RD pulse width 14 SYSCLK cycles 1110 WR and RD pulse width 15 SYSCLK cycles 1111 WR and RD pulse width 16 SYSCLK cycles EAH 1 0 EMIF Address Hold Time Bits 00 Address hold time 0 SYSCLK cycles 01 Address hold time 1 SYSCLK cycle 10 Address hold time 2 SYSCLK cycles 11 Address hold time 3 SYSCLK cycles SILICON LABS Rev 1 3 168 8051 58 59 18 6 1 Non Multiplexed Mode 18 6 1 1 16 bit MOVX EMIOCF 4 2 101 110 or 111 Nonmuxed 16 bit WRITE ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD Nonmuxed 16 bit READ ADDR 15 8 ADDR 7 0 DATA 7 0 RD Figure 18 4 Non multiplexed 16 bit MOVX Timing 169 Rev 1 3 SILICON LABS 8051 58 59 18 6 1 2 8 bit MOVX without Bank Select EMIOCF 4 2 101 or 111 Nonmuxed 8 bit WRITE without Bank Se
260. ct 1 Block the processing of LIN communications until the next SYNC BREAK signal 6 SLEEP Sleep Mode Bit slave mode only 0 Wake the device after receiving a Wakeup interrupt 1 Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle timeout 5 TXRX Transmit Receive Selection Bit 0 Current frame is a receive operation 1 Current frame is a transmit operation 4 DTACK Data Acknowledge Bit slave mode only Set to 1 after handling a data request interrupt to acknowledge the transfer The bit will automatically be cleared to 0 by the LIN controller 3 RSTINT Reset Interrupt Bit This bit always reads as 0 0 No effect 1 Reset the LININT bit LINOST 3 2 RSTERR Reset Error Bit This bit always reads as 0 0 No effect 1 Reset the error bits in LINOST and LINOERR 1 WUPREQ_ Wakeup Request Bit Set to 1 to terminate sleep mode by sending a wakeup signal The bit will automati cally be cleared to 0 by the LIN controller 0 STREQ Start Request Bit master mode only 1 Start a LIN transmission This should be set only after loading the identifier data length and data buffer if necessary The bit is reset to 0 upon transmission completion or error detection 225 Rev 1 3 SILICON LABS 8051 58 59 LIN Register Definition 21 6 LINOST LINO Status Register Bit 7 6 5 4 3 2 1 0 ACTIVE I
261. d identifier it has to write a 1 to the STOP bit LINOCTRL 7 instead of setting the DTACK LINOCTRL 4 bit At that time steps 2 through 5 can then be skipped In this situation the LIN controller stops the processing of LIN communication until the next SYNC BREAK is received 4 Changing the configuration of the checksum during a transaction will cause the interface to reset and the transaction to be lost To prevent this the checksum should not be configured while a transaction is in progress The same applies to changes in the LIN interface mode from slave mode to master mode and from master mode to slave mode 21 5 Sleep Mode and Wake Up To reduce the system s power consumption the LIN Protocol Specification defines a Sleep Mode The message used to broadcast a Sleep Mode request must be transmitted by the LIN master application in the same way as a normal transmit message The LIN slave application must decode the Sleep Mode Frame from the Identifier and data bytes After that it has to put the LIN slave node into the Sleep Mode by setting the SLEEP bit LINOCTRL 6 If the SLEEP bit LINOCTRL 6 of the LIN slave application is not set and there is no bus activity for four seconds specified bus idle timeout the IDLTOUT bit LINOST 6 is set and an interrupt request is gener ated After that the application may assume that the LIN bus is in Sleep Mode and set the SLEEP bit LINOCTRL 6 Sending a wake up signal from the master or
262. d only when TR1 1 AND is active as defined by bit INTPL in register ITO1CF see SFR Definition 14 7 6 C T1 Counter Timer 1 Select 0 Timer Timer 1 incremented by clock defined by T1M bit in register CKCON 1 Counter Timer 1 incremented by high to low transitions on external pin T1 5 4 T1M 1 0 Timer 1 Mode Select These bits select the Timer 1 operation mode 00 Mode 0 13 bit Counter Timer 01 Mode 1 16 bit Counter Timer 10 Mode 2 8 bit Counter Timer with Auto Reload 11 Mode 3 Timer 1 Inactive 3 GATEO 0 Gate Control 0 Timer 0 enabled when TRO 1 irrespective of INTO logic level 1 Timer 0 enabled only when TRO 1 AND INTO is active as defined by bit INOPL in register ITO1CF see SFR Definition 14 7 2 C TO Counter Timer 0 Select 0 Timer Timer 0 incremented by clock defined by TOM bit in register CKCON 1 Counter Timer 0 incremented by high to low transitions on external pin TO 1 0 TOM 1 0 0 Mode Select These bits select the Timer 0 operation mode 00 Mode 0 13 bit Counter Timer 01 Mode 1 16 bit Counter Timer 10 Mode 2 8 bit Counter Timer with Auto Reload 11 Mode 3 Two 8 bit Counter Timers 292 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 27 4 TLO Timer 0 Low Byte Bit 7 6 5 4 3 2 1 0 Name TLO 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x8A SFR Page All Pages Bit N
263. d rate generator selects the clock source for the baud rate generator and selects the prescaler value for the timer The baud rate generator must be enabled for UARTO to function Registers SBRLHO and SBRLLO contain a 16 bit reload value for the dedicated 16 bit timer The internal timer counts up from the reload value on every clock tick On timer overflows OxFFFF to 0x0000 the timer is reloaded The baud rate for UARTO is defined in Equation 24 1 where BRG Clock is the baud rate generator s selected clock source For reliable UART operation it is recommended that the UART baud rate is not configured for baud rates faster than SYSCLK 16 Rev 1 3 256 SILICON LABS 8051 58 59 SYSCLK 1 65536 SBRLHO SBRLLO 2 Prescaler Equation 24 1 UARTO Baud Rate A quick reference for typical baud rates and clock frequencies is given in Table 24 1 Baud Rate Table 24 1 Baud Rate Generator Settings for Standard Baud Rates Target Baud Actual Baud Baud Rate Oscillator SBOPS 1 0 Reload Value in Rate bps Rate bps Error Divide Prescaler Bits SBRLHO SBRLLO Factor 230400 230769 OxFF98 115200 115385 OxFF30 57600 57554 OxFE5F 28800 28812 OxFCBF 14400 14397 OxF97D 9600 9600 OxF63C 2400 2400 OxD8FO0 1200 1200 0xB1E0 230400 230769 OxFFCC 115200 115385 OxFF98 57600 57692 OxFF30 28800 28777 OxFE5F 14400 14406 OxFCBF 9600 9600 OxFB1E 2400 2400 OxEC78 1200 1200 OxD8FO0 230400 230769 OxFFE6 115200 115385 Ox
264. d supply current requirements OUT VIN CPn CIRCUIT CONFIGURATION Positive Hysteresis Voltage Programmed with CPnHYP Bits VIN 5 UTS Negative Hysteresis Voltage Programmed by CPnHYN Bits VIN i VOH i OUTPUT s i Negative Hysteresis S Maximum Disabled Negative Hysteresis Positive Hysteresis Maximum Disabled Positive Hysteresis Figure 9 2 Comparator Hysteresis Plot Comparator hysteresis is software programmable via its Comparator Control register CPTnCN The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits As shown in Figure 9 2 various levels of negative hysteresis can be programmed or negative hysteresis can be dis abled In a similar way the amount of positive hysteresis is determined by the setting the CPnHYP bits Comparator interrupts can be generated on both rising edge and falling edge output transitions For Inter rupt enable and priority control see 14 Interrupts The CPnFIF flag is set to 1 upon a Comparator fall ing edge and the CPnRIF flag is set to 1 upon the Comparator rising edge Once set these bits remain set until cleared by software The output state of the Comparator can be obtained at any time by reading the CPnOUT bit The Comparator is enabled by setting the CPnEN bit to 1 and is disabled by clearing this bit to 0 78 Rev 1 3 SILICON LABS 8051 58 59
265. down when Auto reload Mode If EXENn 1 TnEX should be configured as a digital input 0 Transitions on the TnEX pin are ignored 1 Transitions on the TnEX pin cause capture reload or control the direction of timer count up or down as follows Capture Mode 1 to 0 Transition on pin causes TMRnCAPH TMRnCAPL to capture timer value Auto Reload Mode DCENn 0 1 to 0 transition causes reload of timer and sets the EXFn Flag DCENn 1 TnEX logic level controls direction of timer up or down 2 TRn Timer 4 and 5 Run Control 0 Timer is disabled 1 Timer enabled and running counting 1 CTn Timer 4 and 5 Counter Timer Select 0 Timer Function Timer incremented by clocked defined in TnM1 TnMO TMRnCF 1 Counter Function Timer incremented by high to low transitions on TnEX pin 0 CPRLn 4 and 5 Capture Reload Select 0 Timer is in Auto Reload mode 1 Timer is in Capture mode 310 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 27 19 TMRnCF Timer 4 and 5 Configuration Bit 7 6 5 4 3 2 1 0 Name TnM 1 0 TOGn TnOE DCENn Type R W R W R W R W R W R W R R W Reset 0 0 0 0 0 0 0 0 TMRACF SFR Address 0xC9 TMR5CF SFR Address 0x96 SFR Page 0x10 Bit Name Function 7 5 Reserved Must Write 0000 4 3 TnM 1 0 4 and 5 Clock Mode Select Bits 00 Timer clock is SYSCLK 12 01 Timer cl
266. dress is acknowledged zero or more data bytes are transmitted If the received slave address is acknowledged data should be written to SMBODAT to be transmitted The interface enters Slave Transmitter Mode and transmits one or more bytes of data After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMBODAT should be written with the next data byte If the acknowledge bit is a NACK SMBODAT should not be written to before SI is cleared Note an error condition may be generated if SMBODAT is written following a received NACK while in Slave Transmitter Mode The interface exits Slave Transmitter Mode after receiving a STOP Note that the interface will switch to Slave Receiver Mode if SMBODAT is not written following a Slave Transmitter inter rupt Figure 23 8 shows a typical slave read sequence Two transmitted data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode Received by SVBus S START N NACK R READ Transmitted by SLA Slave Address SMBus Interface Figure 23 8 Typical Slave Read Sequence 23 6 SMBus Status Decoding The current SMBus status can be easily decoded using the SMBOCN register In the tables STATUS VECTOR refers to the four upper bits of SMBOCN MASTER TXMODE STA and STO The shown response options are only the typical responses application specific proce
267. dures are allowed as long as they conform to the SMBus specification Highlighted responses are allowed by hardware but do not con form to the SMBus specification Rev 1 3 253 SILICON LABS 8051 58 59 Master Transmitter Master Receiver Values Read SIARBLOST Table 23 4 SMBus Status Decoding Current SMbus State A master START was gener ated Typical Response Options Load slave address R W into SMBODAT Values to Write Next Status Vector Expected 1000 1 0 A master data or address byte was transmitted NACK received A master data or address byte was transmitted ACK received A master data byte was received ACK requested Set STA to restart transfer Abort transfer Load next data byte into SMBO DAT End transfer with STOP End transfer with STOP and start another transfer Send repeated START Switch to Master Receiver Mode clear SI without writing new data to SMBODAT Acknowledge received byte Read SMBODAT 1000 Send NACK to indicate last byte and send STOP Send NACK to indicate last byte and send STOP followed by START 1110 Send ACK followed by repeated START 1110 Send NACK to indicate last byte and send repeated START 1110 Send ACK and switch to Master Transmitter Mode write to SMBODAT before clearing SI 1100 Send NACK and switch to Mas ter Transmitter
268. e RSTSRC 0x02 is correct RSTSRC 0x02 is incorrect Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1 Areas to check are initialization code which enables other reset sources such as the Missing Clock Detector or Comparator for example and instructions which force a Software Reset A global search on RSTSRC can quickly verify this 143 Rev 1 3 SILICON LABS 8051 58 59 15 4 2 PSWE Maintenance 1 Reduce the number of places in code where the PSWE bit b0 in PSCTL is set to a 1 There should be exactly one routine in code that sets PSWE to 1 to write Flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase Flash pages Minimize the number of variable accesses while PSWE is set to a 1 Handle pointer address updates and loop variable maintenance outside the PSWE 1 PSWE 0 area Code examples showing this can be found in AN201 Writing to Flash from Firmware available from the Silicon Laboratories web site Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been reset to 0 Any interrupts posted during the Flash write or erase operation will be serviced in priority order after the Flash operation has been completed and interrupts have been re enabled by software Make certain that the Flash write and erase pointer variables are not located in XRAM See your compiler documentation for
269. e A write to this register will set the module s ECOMn bit to a 1 SILICON LABS Rev 1 3 332 8051 58 59 29 Programmable Counter Array 1 PCA1 The Programmable Counter Array PCA1 provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter timers PCA1 consists of a dedicated 16 bit counter timer and six 16 bit capture compare modules Each capture compare module has its own associated line CEXn which is routed through the Crossbar to Port when enabled The counter timer is driven by a programmable timebase that can select between eight sources system clock system clock divided by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 4 or 5 over flows or an external clock signal on the ECI input pin Each capture compare module may be configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 to 11 Bit PWM or 16 Bit PWM each mode is described in Section 29 3 Capture Compare Modules on page 336 The external oscillator clock option is ideal for real time clock RTC functionality allowing PCA1 to be clocked by a precision external oscillator while the internal oscillator drives the system clock PCA1 is configured and controlled through the system controller s Spe cial Function Registers The PCA1 block diagram is shown in Figure 29
270. e should be used as a reference to configure and use the CAN controller This data sheet describes how to access the CAN controller All of the CAN controller registers are located on SFR Page 0 0 Before accessing any of the CAN regis ters the SFRPAGE register must be set to 0 0 The CAN Controller is typically initialized using the following steps Set the SFRPAGE register to the CAN registers page page 0 0 Set the INIT and the CCE bits to 1 in CANOCN See the CAN User s Guide for bit definitions Set timing parameters in the Bit Timing Register and the BRP Extension Register Initialize each message object or set its MsgVal bit to NOT VALID Reset the INIT bit to 0 af on gt C8051F580 F590 d CAN Controller RX E 8051 MCU Core CANOCFG Message Handler System Clock CAN Core Message CAN Registers RAM mapped to 32 Objects SFR space Figure 22 2 CAN Controller Diagram 22 1 1 CAN Controller Timing The CAN controller s clock fsys is derived from the CIP 51 system clock SYSCLK The internal oscillator is accurate to within 0 5 of 24 MHz across the entire temperature range and for VDD voltages greater than or equal to the minimum output of the on chip voltage regulator so an external oscillator is not required for CAN communication for most systems Refer to Section 4 10 4 Oscillator Tolerance Range in the Bosch CAN User s Guide for further information regarding this topic 232 Re
271. e internal oscillator The clock multiplier can produce three possible base outputs which can be scaled by a programmable factor of 1 2 3 2 4 or 1 2 2 5 2 6 or 1 3 or 2 7 Internal Oscillator x 2 External Oscillator x 2 or External Oscillator x 4 l OSCICRS OSCIFIN OSCICN CLKSEL l zz wt S Sse ig or Pop Em Option 3 H XTAL2 Y CAL EN I Iose f dL I Programmable Internal zn um Option 4 UU AP AI I CLOCK MULTIPLIER MEM losc 2 Option 2 ub pes SYSCLK M EXTOSC PL Option 1 XTAL1 Bd N XTAL2 EN ii Input EN MM Circuit osc EXOSC gt ix L7 XTAL2 pen um 1 hoo 1 1 T I Nix o gt sN See gz 6 22 2am 25166800 E OQ 22555555 PIRI szssssz I OSCXCN CLKMUL 1 Figure 19 1 Oscillator Options 19 1 System Clock Selection The CLKSL 1 0 bits in register CLKSEL select which oscillator source is used as the system clock CLKSL 1 0 must be se
272. e the device from a low power mode such as IDLE or SUSPEND See the Interrupts and Power Options chapters for more details on interrupt and wake up sources SFR Definition 20 5 POMASK Port 0 Mask Register Bit 7 6 5 4 3 2 1 0 Name POMASK 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address OxF2 SFR Page 0x00 Bit Name Function 7 0 POMASK 7 0 Port 0 Mask Value Selects PO pins to be compared to the corresponding bits in POMAT 0 PO n pin logic value is ignored and cannot cause a Port Mismatch event 1 PO n pin logic value is compared to POMAT n SFR Definition 20 6 POMAT Port 0 Match Register Bit 7 6 5 4 3 2 1 0 Name POMATT 7 0 Type R W Reset 1 1 1 1 1 1 1 1 SFR Address OxF1 SFR Page 0x00 Bit Name Function 7 0 7 0 Port 0 Match Value Match comparison value used on Port 0 for bits in POMAT which are set to 1 0 PO n pin logic value is compared with logic LOW 1 PO n pin logic value is compared with logic HIGH Rev 1 3 200 SILICON LABS 8051 58 59 SFR Definition 20 7 P1MASK Port 1 Mask Register Bit 7 6 5 4 3 2 1 0 Name P1 MASK 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0 4 SFR Page 0x00 Bit Name Function 7 0 P1MASK 7 0 Port 1 Mas
273. e upon the overflow or underflow of the respective timer depending on whether the timer is counting up or down The toggle frequency is determined by the clock source of the timer and the values loaded into TMRnCAPH and TMRnCAPL When counting down the auto reload value for the timer is OXFFFF and underflow will occur when the value in the timer matches the value stored in TMRnCAPH TMRCAPL When counting up the auto reload value for the timer is TMRnCAPH TMRCAPL and overflow will occur when the value in the timer transi tions from OxFFFF to the reload value To output a square wave the timer is placed in reload mode the Capture Reload Select Bit in TMRnCN and the Timer Counter Select Bit in TMRnCN are cleared to 0 The timer output is enabled by setting the Timer Output Enable Bit in TMRnCF to 1 The timer should be configured via the timer clock source and reload underflow values such that the timer overflow underflows at 1 2 the desired output frequency The port pin assigned by the crossbar as the timer s output pin should be configured as a digital output see Section 20 Port Input Output on page 188 Setting the timer s Run Bit TRn to 1 will start the toggle of the pin A Read Write of the Timer s Toggle Output State Bit TMRnCF 2 is used to read the state of the toggle output or to force a value of the output This is useful when it is desired to start the toggle of a pin in a known state or to force the pin into a desired state whe
274. eading of the entire 16 bit PCAO counter Reading PCAOH or PCAOL does not disturb the counter operation The CPS2 CPS0 bits in the PCAOMD register select the timebase for the counter timer as shown in Table 28 1 When the counter timer overflows from OxFFFF to 0x0000 the Counter Overflow Flag CF in PCAOMD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCAOMD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Clearing the CIDL bit in the PCAOMD register allows the PCAO to continue normal operation while the CPU is in Idle mode Table 28 1 Timebase Input Options CPS2 CPS1 50 Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions max rate system clock divided by 4 System clock External oscillator source divided by 8 Timer 4 Overflow 1 1 1 Timer 5 Overflow Note External oscillator source divided by 8 is synchronized with the system clock IDLE 4 a O O PCAOMD PCAOCN c c c E c c c c cicicic D TIL S S SF F F F F F F L E c 2 1 o 5 4 3 2 1 0 SFR Bus K PCAOL
275. efault NSS is an input to the device 1x 4 Wire Single Master Mode NSS signal is mapped as an output from the device and will assume the value of NSSMDO 1 TXBMT Transmit Buffer Empty This bit will be set to logic 0 when new data has been written to the transmit buffer When data in the transmit buffer is transferred to the SPI shift register this bit will be set to logic 1 indicating that it is safe to write a new byte to the transmit buffer 0 SPIEN SPIO Enable 0 SPI disabled 1 SPI enabled SILICON LABS Rev 1 3 280 8051 58 59 SFR Definition 26 3 SPIOCKR SPIO Clock Rate Bit 7 6 5 4 3 2 1 0 Name SCR 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA2 SFR Page 0x00 Bit Name Function 7 0 SCR 7 0 SPIO Clock Rate These bits determine the frequency of the SCK output when the SPIO module is configured for master mode operation The SCK clock frequency is a divided ver sion of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPIOCKR is the 8 bit value held in the SPIOCKR register M SYSCLK 2 x SPIOCKR 7 0 1 for 0 lt SPIOCKR lt 255 Example If SYSCLK 2 MHz and SPIOCKR 0x04 _ 2000000 2 x 441 SFR Definition 26 4 SPIODAT SPIO Data Bit 7 6 5 4 3 2 1 0 Name SPIOD
276. egister CKCON may still be used to select between the external clock and the system clock for either timer 0 Timer 2 clock is the system clock divided by 12 1 Timer 2 clock is the external clock divided by 8 synchronized with SYSCLK 298 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 27 9 TMR2RLL Timer 2 Reload Register Low Byte Bit 7 6 5 4 3 Name TMR2RLL 7 0 Reset 0 0 0 0 0 SFR Address SFR Page 0x00 Bit Name Function 7 0 TMR2RLL 7 0 Timer 2 Reload Register Low Byte TMR2RLL holds the low byte of the reload value for Timer 2 SFR Definition 27 10 TMR2RLH Timer 2 Reload Register High Byte Bit 7 6 5 4 3 Name TMR2RLH 7 0 Type R W Reset 0 0 0 0 0 SFR Address OxCB SFR Page 0x00 Bit Name Function 7 0 TMR2RLH 7 0 Timer 2 Reload Register High Byte TMR2RLH holds the high byte of the reload value for Timer 2 SILICON LABS Rev 1 3 299 8051 58 59 SFR Definition 27 11 TMR2L Timer 2 Low Byte Bit 7 6 5 4 3 1 0 Name TMR2L 7 0 Reset 0 0 0 0 0 0 0 SFR Address 0xCC SFR Page 0x00 Bit Name Function 7 0 TMR2L 7 0 Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2
277. el Select 73 SFR Definition 8 1 REFOCN Reference Control 76 SFR Definition 9 1 CPTOCN ComparatorO Control 79 SFR Definition 9 2 CPTOMD ComparatorO Mode Selection 80 SFR Definition 9 3 CPT1CN Comparator1 Control 81 SFR Definition 9 4 CPT1MD Comparator1 Mode Selection 82 SFR Definition 9 5 CPT2CN Comparator2 Control 83 SFR Definition 9 6 CPT2MD Comparator2 Mode Selection 84 SFR Definition 9 7 ComparatorO MUX Selection 86 SFR Definition 9 8 CPT1MX 1 MUX Selection 87 SFR Definition 9 9 CPT2MX Comparator2 MUX Selection 88 SFR Definition 10 1 REGOCN Regulator Control 90 SFR Definition 11 1 DPL Data Pointer Low Byte 98 SFR Definition 11 2 DPH Data Pointer High Byte 98 SFR Definition 11 3 SP Stack Pointer 99 SFR Definition 11 4 ACC Accumulator
278. em clock SYSCLK to operate the LIN controller is 8 MHz Use the following equations to calculate the values for the variables for the baud rate equation 215 Rev 1 3 SILICON LABS 8051 58 59 ar 20000 baud rate prescaler inf X xL multiplier 1 x baud_rate 2001 1 2 SYSCLK X multiplier 1 X baud_rate divider prescaler 1 2 In all of these equations the results must be rounded down to the nearest integer The following example shows the steps for calculating the baud rate values for a Master node running at 24 MHz and communicating at 19200 bits sec First calculate the multiplier aa 20000 multiplier 19200 0 0 0 Next calculate the prescaler prescaler 22000000 ead 1 644 1 0 1 19200 x 200 102 Finally calculate the divider 24000000 divider 121 312 5 312 21 D X 0 1 19200 These values lead to the following baud rate baud_rate Gh ce 19230 77 2 X 0 1 312 The following code programs the interface in Master mode using the Enhanced Checksum and enables the interface to operate at 19230 bits sec using a 24 MHz system clock LINOCF 0x80 Activate the interface LINOCF 0x40 Set the node as a Master LINOADR 0 Point to the LINOMUL register Initialize the register prescaler multiplier and bit 8 of divider LINODAT 0 01 lt lt 6 0x00 lt lt 1 0x138 amp 0 0100
279. er SPIODAT Data Register SPIOCFG Configuration Register and SPIOCKR Clock Rate Register The four special function registers related to the operation of the SPIO Bus are described in the following figures SILICON LABS Rev 1 3 Figure 26 7 Slave Mode Data Clock Timing CKPHA 1 278 8051 58 59 SFR Definition 26 1 SPIOCFG SPIO Configuration Bit 7 6 5 4 3 2 1 0 SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT Type R R W R W R W R R R R Reset 0 0 0 0 0 1 1 1 SFR Address 0xA1 SFR Page 0x00 Bit Name Function 7 SPIBSY SPI Busy This bit is set to logic 1 when a SPI transfer is in progress master or slave mode MSTEN Master Mode Enable 0 Disable master mode Operate in slave mode 1 Enable master mode Operate as a master CKPHA SPIO Clock Phase 0 Data centered on first edge of SCK period 1 Data centered on second edge of SCK period CKPOL SPIO Clock Polarity 0 SCK line low in idle state 1 SCK line high in idle state SLVSEL Slave Selected Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPIO is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input NSSIN NSS Instantaneous Pin Input This bit mim
280. er need to be calculated prescaler 4000000 in2 divider f Prescaler 1 20000 The following example calculates the values of these variables for a 24 MHz system clock 24000000 1 prescaler 4000000 Ec 1 585 1 divider 24000000 _ _ 300 20 20000 Table 21 3 presents some typical values of system clock and baud rate along with their factors 217 Rev 1 3 SILICON LABS 8051 58 59 Table 21 3 Autobaud Parameters Examples System Clock MHz Prescaler Divider 25 1 312 24 5 1 306 24 1 300 22 1184 1 276 16 1 200 12 25 0 306 12 0 300 11 0592 0 276 8 0 200 21 3 LIN Master Mode Operation The master node is responsible for the scheduling of messages and sends the header of each frame con taining the SYNCH BREAK FIELD SYNCH FIELD and IDENTIFIER FIELD The steps to schedule a mes sage transmission or reception are listed below 1 Load the 6 bit Identifier into the LINOID register 2 Load the data length into the LINOSIZE register Set the value to the number of data bytes 1111b if the data length should be decoded from the identifier Also set the checksum type classic or enhanced in the same LINOSIZE register 3 Set the data direction by setting the TXRX bit LINOCTRL 5 Set the bit to 1 to perform a master transmit operation or set the bit to O to perform a master receive operation 4
281. er paste release 7 The stencil thickness should be 0 125 mm 5 mils 8 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads 9 A 4x4 array of 0 80 mm square openings on a 1 05 mm pitch should be used for the center ground pad Card Assembly 10 A No Clean Type 3 solder paste is recommended 11 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components 37 Rev 1 3 SILICON LABS 8051 58 59 44 32 Package Specifications SILICON LABS 1 1 I E E t El A A SECTION A A 1 TIPS A I 1 bbb H A PB I qu SES J LIE lt 222 6 j SECTION B B doa C A B D Figure 4 7 QFP 32 Package Drawing Table 4 7 QFP 32 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 1 60 E
282. erations Target Bank 0 note that Bank 0 is also mapped between 0x0000 to Ox7FFF 01 Constant operations target Bank 1 10 Constant operations target Bank 2 11 Constant operations target Bank 3 3 2 Reserved Read 00b Must Write 00b 1 0 IFBANK 1 0 Instruction Fetch Operations Bank Select These bits select which Flash bank is used for instruction fetches involving address 0x8000 to OxFFFF These bits can only be changed from code in Bank 0 00 Instructions fetch from Bank 0 note that Bank 0 is also mapped between 0x0000 to Ox7FFF 01 Instructions fetch from Bank 1 10 Instructions fetch from Bank 2 11 Instructions fetch from Bank 3 Note COBANK 1 0 and IFBANK 1 0 should not be set to select Bank 3 11b on the C8051F584 5 6 7 F590 1 devices 12 1 1 MOVX Instruction and Program Memory The MOVX instruction in an 8051 device is typically used to access external data memory On the C8051F58x F59x devices the MOVX instruction is normally used to read and write on chip XRAM but can be re configured to write and erase on chip Flash memory space MOVC instructions are always used to read Flash memory while MOVX write instructions are used to erase and write Flash This Flash access feature provides a mechanism for the C8051F58x F59x to update program code and use the program memory space for non volatile data storage Refer to Section 15 Flash Memory on page 138 for further deta
283. errupt 1 1 Enable interrupt requests generated by the input ETO Enable Timer 0 Interrupt This bit sets the masking of the Timer 0 interrupt 0 Disable all Timer 0 interrupt 1 Enable interrupt requests generated by the TFO flag Enable External Interrupt 0 This bit sets the masking of External Interrupt 0 0 Disable external interrupt 0 1 Enable interrupt requests generated by the INTO input Rev 1 3 130 SILICON LABS 8051 58 59 SFR Definition 14 2 IP Interrupt Priority Bit 7 6 5 4 3 2 1 0 Name PSPIO PT2 PSO 1 1 R R W R W R W R W R W R W R W Reset 1 0 0 0 0 0 0 0 SFR Address 0xB8 Bit Addressable SFR Page All Pages Bit Name Function 7 Unused Read 1b Write Don t Care 6 PSPIO Serial Peripheral Interface SPIO Interrupt Priority Control This bit sets the priority of the SPIO interrupt 0 SPIO interrupt set to low priority level 1 SPIO interrupt set to high priority level PT2 Timer 2 Interrupt Priority Control This bit sets the priority of the Timer 2 interrupt 0 Timer 2 interrupt set to low priority level 1 Timer 2 interrupt set to high priority level PSO UARTO Interrupt Priority Control This bit sets the priority of the UARTO interrupt 0 UARTO interrupt set to low priority level 1 UARTO interrupt set to high pr
284. errupt Priority Control This bit sets the priority of the Timer 5 interrupt 0 Timer 5 interrupts set to low priority level 1 Timer 5 interrupts set to high priority level 6 PT4 Timer 4 Interrupt Priority Control This bit sets the priority of the Timer 4 interrupt 0 Timer 4 interrupts set to low priority level 1 Timer 4 interrupts set to high priority level 5 2 Comparator1 CP1 Interrupt Priority Control This bit sets the priority of the CP1 interrupt 0 CP1 interrupt set to low priority level 1 CP1 interrupt set to high priority level 4 PPCA1 Programmable Counter Array PCA1 Interrupt Priority Control This bit sets the priority of the PCA1 interrupt 0 1 interrupt set to low priority level 1 PCA1 interrupt set to high priority level 3 PS1 UART1 Interrupt Priority Control This bit sets the priority of the UART1 interrupt 0 UART1 interrupt set to low priority level 1 UART1 interrupt set to high priority level 2 Port Match Interrupt Priority Control This bit sets the priority of the Port Match interrupt 0 Port Match interrupt set to low priority level 1 Port Match interrupt set to high priority level 1 PCANO Interrupt Priority Control This bit sets the priority of the CANO interrupt 0 CANO interrupt set to low priority level 1 CANO interrupt set to high priority level 0 PREGO Voltage Regulator Dropout Interrupt Priority Control T
285. errupt with the higher priority is serviced first If both interrupts have the same priority level a fixed prior ity order is used to arbitrate given in Table 14 1 14 1 2 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority decoded each system clock cycle Therefore the fastest possible response time is 5 system clock cycles 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction In this case the response time is 18 system clock cycles 1 clock cycle to detect the interrupt 5 clock cycles to execute the RETI 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction 127 Rev 1 3 SILICON LABS 8051 58 59 Table 14 1 Interrupt Summary
286. es to SPIODAT are double buffered and are placed in the transmit buffer first If the shift register is empty the contents of the transmit buffer will immediately be transferred into the shift register When the shift register already contains data the SPI will load the shift register with the transmit buffer s contents after the last SCK edge of the next or current SPI transfer When configured as a slave SPIO can be configured for 4 wire or 3 wire operation The default 4 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In 4 wire mode the NSS signal is routed to a port and configured as a digital input SPIO is enabled when NSS is logic 0 and disabled when NSS is logic 1 The bit counter is reset on a falling edge of NSS Note that the NSS sig nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer Figure 26 4 shows a connection diagram between two slave devices in 4 wire slave mode and a master device 3 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPIO must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been re
287. ev 1 3 SILICON LABS 8051 58 59 Write to PCAOCPLn 0 p Seb PCAOCPHn Write to Hd gt PCAOPWM PCAOCPMn COVF PCAOCPLn 1 Enable 8 bit 1 l SQ I Crossbar Port I O mS R CLR Q PCAO Timebase b PCA0L Overflow Figure 28 8 PCA0 8 Bit PWM Mode Diagram 28 3 5 2 9 10 11 bit Pulse Width Modulator Mode The duty cycle ofthe PWM output signal in 9 10 11 bit PWM mode should be varied by writing to an Auto Reload Register which is dual mapped into the PCA0CPHn and PCA0CPLn register locations The data written to define the duty cycle should be right justified in the registers The auto reload registers are accessed read or written when the bit ARSEL in PCA0PWM is set to 1 The capture compare registers are accessed when ARSEL is set to 0 When the least significant N bits of the PCAO counter match the value in the associated module s cap ture compare register PCA0CPn the output on CEXn is asserted high When the counter overflows from the Nth bit CEXn is asserted low see Figure 28 9 Upon an overflow from the Nth bit the COVF flag is set and the value stored in the module s auto reload register is loaded into the capture compare register The value of is determined by the CLSEL bits in register PCAOPWM The 9 10 or 11 bit PWM mode is selected by setting the ECOMn and PWMhn bits in the PCAOCPMn re
288. evision A 352 Rev 1 3 SILICON LABS 8051 58 59 C2 Register Definition 30 4 FPCTL C2 Flash Programming Control Bit 7 6 5 4 3 2 1 0 Name FPCTL 7 0 Reset 0 0 0 0 0 0 0 0 C2 Address 0x02 Bit Name Function 7 0 FPCTL 7 0 Flash Programming Control Register This register is used to enable Flash programming via the C2 interface To enable C2 Flash programming the following codes must be written in order 0x02 0x01 Note that once C2 Flash programming is enabled a system reset must be issued to resume normal operation C2 Register Definition 30 5 FPDAT C2 Flash Programming Data Bit 7 6 5 4 3 2 1 0 Name FPDAT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 C2 Address 0xB4 Bit Name Function 7 0 FPDAT 7 0 C2 Flash Programming Data Register This register is used to pass Flash commands addresses and data during C2 Flash accesses Valid commands are listed below Code Command 0x06 Flash Block Read 0x07 Flash Block Write 0x08 Flash Page Erase 0x03 Device Erase Rev 1 3 353 SILICON LABS 8051 58 59 The FPSEL register is a Special Function Register SFR that is only accessible through the C2 interface When reading writing or erasing Flash through the C2 interface this register must be set first in order to access the different banks SFRs are
289. f physical I O pins This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder Note that the state of a Port I O pin can always be read in the corresponding Port latch regardless of the Crossbar settings The Crossbar assigns the selected internal digital resources to the I O pins based on the Priority Decoder Figure 20 3 and Figure 20 4 The registers XBRO XBR1 XBR2 and XBR3 are used to select internal digital functions Port 4 on the C8051F580 1 4 5 and C8051F588 9 F590 1 is a digital only port which is not assigned through the Crossbar All Port I Os are 5 V tolerant refer to Figure 20 2 for the Port cell circuit The Port cells are configured as either push pull or open drain in the Port Output Mode registers PnRMDOUT where n 0 1 Complete Electrical Specifications for Port I O are given in Table 5 3 on page 47 Note When VIO rises faster than VDD which can happen when VREGIN and VIO are tied together a delay created between GPIO power VIO and the logic controlling GPIO VDD results in a temporary unknown state at the GPIO pins Cross coupling VIO and VDD with a 4 7 uF capacitor mitigates the root cause of the problem by allowing VIO and VDD to rise at the same rate Rev 1 3 188 SILICON LABS 8051 58 59 Highest T Priority 1 Extemal I Pins CY X 0 Highest g Priority 2
290. fined NSMD Clearance between the solder mask and the metal pad is to be 60 um minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads Card Assembly 7 A No Clean Type 3 solder paste is recommended 8 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components 33 Rev 1 3 SILICON LABS 8051 58 59 4 2 QFN 48 Package Specifications EATING PLANE WY imm TU IE SIDE VIEW BOTTO IEW tail rimeter Lead Forr NAH vem DI CIE m m XS m n ilar rner rner ptior Optior ptior Figure 4 3 QFN 48 Package Drawing Table 4 3 QFN 48 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0 80 0 90 1 00 E2 3 90 4 00 4 10 A1 0 00 0 05 L 0 30 0 40 0 50 b 0 18 0 23 0 30 L1 0 00 0 10 D 7 00 BSC aaa 0 10 D2 3 90 4 00 4 10 bbb
291. following a Flash error reset The state of the RST pin is unaffected by this reset 17 8 Software Reset Software may force a reset by writing a 1 to the SWRSF bit RSTSRC 4 The SWRSF bit will read 1 fol lowing a software forced reset The state of the RST pin is unaffected by this reset Rev 1 3 156 SILICON LABS 8051 58 59 SFR Definition 17 2 RSTSRC Reset Source Bit 7 6 5 4 3 2 1 0 Name FERROR CORSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Type R R R W R W R R W R W R Reset 0 Varies Varies Varies Varies Varies Varies Varies SFR Address OxEF SFR Page 0x00 Bit Name Description Write Read 7 Unused Unused Don t care 0 6 FERROR Flash Error Reset Flag N A Set to 1 if Flash read write erase error caused the last reset 5 CORSEF Reset Enable Writing 1 enables Com Set to 1 if ComparatorO and Flag paratorO as a reset source caused the last reset active low 4 SWRSF Software Reset Force Writing a 1 forces sys Setto 1 if last reset was Flag tem reset caused by a write to SWRSF 3 WDTRSF Watchdog Timer Reset Flag N A Set to 1 if Watchdog Timer overflow caused the last reset 2 MCDRSF Missing Clock Detector Writing a 1 enables the Set to 1 if Missing Clock Enable and Flag Missing Clock Detector Detector timeout caused The MCD triggers a reset the last reset
292. g to Equation where f the frequency of oscil lation in MHz the capacitor value in pF and Vpp the MCU power supply in volts 186 Rev 1 3 SILICON LABS 8051 58 59 f KF R x Vpp Equation 19 2 C Mode Oscillator Frequency For example Assume Vpp 2 1 V and f 75 kHz f KF C x VDD 0 075 MHz KF C x 2 1 Since the frequency of roughly 75 kHz is desired select the K Factor from the table in SFR Definition 19 6 OSCXCN as KF 7 7 0 075 MHz 7 7 C x 2 1 2 1 7 7 0 075 MHz 102 6 2 0 pF 51 3 pF Therefore the XFCN value to use in this example is 010b Rev 1 3 187 SILICON LABS 8051 58 59 20 Port Input Output Digital and analog resources are available through 40 C8051F580 1 4 5 33 C8051F588 9 F590 1 or 25 C8051F582 3 6 7 pins Port pins 0 0 4 7 on the C8051F580 1 4 5 Port pins 0 4 0 on the C8051F588 9 F590 1 and Port pins 0 0 0 on the C8051F582 3 6 7 can be defined as general pur pose I O GPIO assigned to one of the internal digital resources or assigned to an analog function as shown in Figure 20 3 Port pin P3 0 on the C8051F582 3 6 7 can be used as GPIO and is shared with the C2 Interface Data signal C2D Port pin P4 0 on the C8051F588 9 F590 1 can be used as GPIO and is shared with the C2 Interface Data signal C2D The designer has complete control over which functions are assigned limited only by the number o
293. ger and programmer interface to the CIP 51 via the C2 interface to provide fast and efficient in sys tem device programming and debugging Third party macro assemblers and C compilers are also avail able 92 Rev 1 3 SILICON LABS 8051 58 59 11 2 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruc tion set Standard 8051 development tools can be used to develop software for the CIP 51 All CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opcodes addressing modes and effect on PSW flags However instruction timing is different than that of the stan dard 8051 11 2 1 Instruction and CPU Timing In many 8051 implementations a distinction is made between machine cycles and clock cycles with machine cycles varying from 2 to 12 clock cycles in length However the CIP 51 implementation is based solely on clock cycle timing All instruction timings are specified in terms of clock cycles Due to the pipelined architecture of the CIP 51 most instructions execute in the same number of clock cycles as there are program bytes in the instruction Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken Table 11 1 is the CIP 51 Instruction Set Summary which includes the mnemonic number of bytes and number of clock cycles for
294. gis ter and setting the CLSEL bits in register PCAOPWM to the desired cycle length other than 8 bits If the bit is set to 1 the CCFn flag for the module will be set each time a comparator match rising edge occurs The COVF flag in PCAOPWM can be used to detect the overflow falling edge which will occur every 512 9 bit 1024 10 bit or 2048 11 bit PCAO clock cycles The duty cycle for 9 10 11 Bit PWM Mode is given in Equation 28 2 where N is the number of bits in the PWM cycle Important Note About PCAOCPHn and PCAOCPLn Registers When writing a 16 bit value to the PCAOCPn registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMnh to 1 _ 2N PCA0CPn Duty Cycle ON Equation 28 3 9 10 and 11 Bit PWM Duty Cycle 0 duty cycle may be generated by clearing the bit to 0 Rev 1 3 322 SILICON LABS 8051 58 59 Write to PCAOCPLn 0 R W when Reset ARSEL 1 Auto Reload PCAOPWM PCAOCPH Ln ATEIG Cle Write to right justified Riclo LIL PCAOCPHn 5 EH sls 1 LIL 110 R W when x ARSEL 0 Set bits lt J PCAOCPH Ln 01 9bits right justified gt 10 10 bits 11 11 bits r Enable ae N bit Comparator gt m
295. gis ters PCA1CPn or the Auto Reload registers at the same SFR addresses This function is used to define the reload value for 9 10 and 11 bit PWM modes In all other modes the Auto Reload registers have no function 0 Read Write Capture Compare Registers at PCA1CPHn and PCA1CPLn 1 Read Write Auto Reload Registers at PCA1CPHn and PCA1CPLn ECOV1 Cycle Overflow Interrupt Enable This bit sets the masking of the Cycle Overflow Flag COVF1 interrupt 0 COVF1 will not generate PCA1 interrupts 1 A PCA1 interrupt will be generated when COVF1 is set COVF1 Cycle Overflow Flag This bit indicates an overflow of the 8th 9th 10th or 11th bit of the main PCA1 counter PCA1 The specific bit used for this flag depends on the setting of the Cycle Length Select bits The bit can be set by hardware or software but must be cleared by software 0 No overflow has occurred since the last time this bit was cleared 1 An overflow has occurred since the last time this bit was cleared 4 2 Unused Read 000b Write Don t care 1 0 CLSEL1 1 0 Cycle Length Select When 16 bit PWM mode is not selected these bits select the length of the PWM cycle between 8 9 10 or 11 bits This affects all channels configured for PWM which are not using 16 bit PWM mode These bits are ignored for individual chan nels configured to16 bit PWM mode 00 8 bits 01 9 bits 10 10 bits 11 11 bits SILI
296. gram Memory 104 12 2 Data uuu u u usa Rp enn ODER PAIS SU ALIUS De 104 12 21 intemal RAM eden Sepe tee Fade 105 12 2 1 1 General Purpose Registers 105 Rev 1 3 3 SILICON LABS 8051 58 59 12 2 1 2 Bit Addressable 105 122 119 t 105 13 Special Function Registers J U J J J J J J 106 13 1 SFR Paging mtm 106 13 2 Interrupts and SFR Paging 106 13 3 SFR Page Stack 107 EM ug 126 14 1 MCU Interrupt Sources and 126 14 1 1 Interrupt Priorities 127 Interrupt Lateriby LIL ri eae EAEE EEEa 127 14 2 Interrupt Register Descriptions eere 129 14 3 External Interrupts INTO and 136 15 Flash uui TTTT 138 15 1 Programming The Flash 2 2 4 1 138 15 1 1 Flash Lock and Key Functions ate irt Rp Rau 138 15 1 2 Flash Erase Procedure eec
297. gramming the Flash in system the Vpp Monitor must be set to the high threshold setting For the highest system reliability firmware can change the Vpp Monitor high threshold and the system must use an external supply monitor For instructions on how to do this see Reprogramming the VDD Monitor High Threshold on page 138 Note The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event The output of the un calibrated internal regulator could be below the high threshold setting of the VDD Monitor If this is the case and the MCU receives a non power on reset POR when the VDD Monitor is set to the high threshold setting the MCU will remain in reset until a POR occurs i e VDD Monitor will keep the device in reset A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un calibrated output of the internal regulator The device will then exit reset and resume normal operation It is for this reason Silicon Labs strongly recommends that the Vpp Monitor is always left in the low threshold setting i e default value upon POR Note The VDD Monitor may trigger on fast changes in voltage on the VDD pin regardless of whether the voltage increased or decreased Rev 1 3 154 SILICON LABS 8051 58 59 SFR Definition 17 1 VDMOCN Vpp Monitor Control Bit 7 6 5 4 3 2 1 0 VDMEN VDDSTAT VDMLVL R W R R W R R R
298. he MCU receives a non power on reset POR when the VDD Monitor is set to the high threshold setting the MCU will remain in reset until a POR occurs i e VDD Monitor will keep the device in reset A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un calibrated output of the internal regulator The device will then exit reset and resume normal operation It is for this reason Silicon Labs strongly recommends that the Vpp Monitor is always left in the low threshold setting i e default value upon POR If the system contains routines to modify flash contents follow the recommendations in Reprogramming the VDD Monitor High Threshold on page 138 REGO X lt VREGIN 4 7 UF 1 uF O 4 Vpp 4 7 1 uF Figure 10 1 External Capacitors for Voltage Regulator Input Output Regulator Enabled Rev 1 3 89 SILICON LABS C8051F58x F59x If the internal voltage regulator is not used the VREGIN input should be tied to VDD as shown in Figure 10 2 VnEGIN O Vpp 4 7 uF Figure 10 2 External Capacitors for Voltage Regulator Input Output Regulator Disabled SFR Definition 10 1 REGOCN Regulator Control Bit 7 6 5 4 3 2 0 REGDIS Reserved REGOMD DROPOUT Type R W R W R R W R R R Reset 0 1 0 1 0 0 SFR Address 0xC9 SFR Page 0x0
299. he SFR Page contained in the second byte of the SFR Stack This will cause the SFRPAGE SFR to have this SFR page value upon a return from interrupt Read Returns the value of the SFR page contained in the second byte of the SFR stack SFR page context is retained upon interrupts return from interrupts in a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and SFRLAST is the third entry The SFR stack bytes may be used alter the context in the SFR Page Stack and will not cause the stack to push or pop Only interrupts and return from interrupts cause pushes and pops of the SFR Page Stack 115 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 13 4 SFRLAST SFR Last Bit 7 6 5 4 3 2 1 0 Name SFRLASTT 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0xA7 SFR Page All Pages Bit Name Function 7 0 SFRLAST 7 0 SFR Page Stack Bits This is the value that will go to the SFRNEXT register upon a return from inter rupt Write Sets the SFR Page in the last entry of the SFR Stack This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt Read Returns the value of the SFR page contained in the last entry of the SFR stack SFR page context is retained upon interrupts return from interrupts in a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and
300. he contents of DPTR to determine whether the memory access is on chip or off chip and the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 18 5 4 External Only When EMIOCFT 3 2 are set to 11 all MOVX operations are directed to off chip space On chip XRAM is not visible to the CPU This mode is useful for accessing off chip memory located between 0x0000 and the internal XRAM size boundary m 8 bit MOVX operations ignore the contents of EMIOCN The upper Address bits A 15 8 are not driven identical behavior to an off chip access in Split Mode without Bank Select described above This allows the user to manipulate the upper address bits at will by setting the Port state directly The lower 8 bits of the effective address A 7 0 are determined by the contents of RO or R1 m 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 18 6 Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements The Address Setup time Address Hold time RD and WR strobe widths and in multiplexed mode the width of the ALE pulse are all programmable in units of SYSCLK periods through EMIOTC shown SFR Definition 18 3 and EMIOCFT 1 0 The timing for an off chip MOVX instruction can be calculated
301. he device is also using the CAN peripheral CANO and the Programmable Counter Array PCAO peripheral to generate PWM output The PCA is timing a critical control function in its interrupt service round so its associated ISR that is set to low priority At this point the SFR page is set to access the SPIODAT SFR SFRPAGE 0x00 See Figure 13 2 107 Rev 1 3 SILICON LABS 8051 58 59 SFR Page Stack SFR s SFRPAGE SFRNEXT SFRLAST Figure 13 2 SFR Page Stack While Using SFR Page 0x0 To Access SPIODAT While CIP 51 executes in line code writing values to SPIODAT in this example the CANO Interrupt occurs The CIP 51 vectors to the CANO ISR and pushes the current SFR Page value SFR Page 0x00 into SFRNEXT in the SFR Page Stack The SFR page needed to access CAN s SFRs is then automatically placed in the SFRPAGE register SFR Page 0 0 SFRPAGE is considered the top of the SFR Page Stack Software can now access the CANO SFRs Software may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the CANO ISR to access SFRs that are not on SFR Page 0 0 See Figure 13 3 Rev 1 3 108 SILICON LABS 8051 58 59 SFR Page 0xC Automatically pushed on stack in SFRPAGE on CANO interrupt SFRPAGE SFRPAGE pushed to SFRNEXT SFRNEXT SFRLAST Figure 13 3 SFR Page Stack After CANO Interrupt Occurs While in the CANO ISR a PCA inter
302. hip reference voltage generator routed to the VREF or the Vpp power supply voltage see Figure 8 1 The REFSL bit in the Reference Control register REFOCN SFR Definition 8 1 selects the reference source for the ADC For an external source or the on chip reference REFSL should be set to 0 to select the VREF pin To use Vpp as the reference source REFSL should be set to 1 The BIASE bit enables the internal voltage bias generator which is used by the ADC Temperature Sensor and internal oscillator This bias is automatically enabled when any peripheral which requires it is enabled and it does not need to be enabled manually The bias generator may be enabled manually by writing a 1 to the BIASE bit in register REFOCN The electrical specifications for the voltage reference circuit are given in Table 5 12 The on chip voltage reference circuit consists of a temperature stable bandgap voltage reference genera tor and a gain of two output buffer amplifier The output voltage is selectable between 1 5 V and 2 25 V The on chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REFOCN to a 1 The maximum load seen by the VREF pin must be less than 200 uA to GND Bypass capacitors of 0 1 and 4 7 are recommended from the VREF pin to GND If the on chip reference is not used the REFBE bit should be cleared to 0 Electrical specifications for the on chip voltage reference are given in Table 5 12 Impor
303. his bit sets the priority of the Voltage Regulator Dropout interrupt 0 Voltage Regulator Dropout interrupt set to low priority level 1 Voltage Regulator Dropout interrupt set to high priority level 135 Rev 1 3 SILICON LABS 8051 58 59 14 3 External Interrupts INTO and INT1 The INTO and INT1 external interrupt sources are configurable as active high or low edge or level sensi tive The INOPL INTO Polarity and IN1PL INT1 Polarity bits in the ITO1CF register select active high or active low the ITO and IT1 bits in TCON Section 27 1 Timer 0 and Timer 1 on page 287 select level or edge sensitive The table below lists the possible configurations ITO INTO Interrupt IT1 INTPL INT1 Interrupt 1 0 Active low edge sensitive 1 0 Active low edge sensitive 1 1 Active high edge sensitive 1 1 Active high edge sensitive 0 0 Active low level sensitive 0 0 Active low level sensitive 0 1 Active high level sensitive 0 1 Active high level sensitive INTO and and INT1 are _are assigned to Port pins as defined in the ITO1CF register see SFR Definition 14 7 Note that INTO and INTO Port pin assignments are independent of any Crossbar assignments INTO and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar To assign a Port pin only to INTO and or INT1 configure
304. ialize the Multiplier with the MULINIT bit CLKMUL 0 0 Poll for MULRDY gt 1 Important Note When using an external oscillator as the input to the Clock Multiplier the external source must be enabled and stable before the Multiplier is initialized See 19 4 External Oscillator Drive Circuit on page 183 for details on selecting an external oscillator source Dir OU COA oux The Clock Multiplier allows faster operation of the CIP 51 core and is intended to generate an output fre quency between 25 and 50 MHz The clock multiplier can also be used with slow input clocks However if the clock is below the minimum Clock Multiplier input frequency FCMmin the generated clock will consist of four fast pulses followed by a long delay until the next input clock rising edge The average frequency of the output is equal to 4x the input but the instantaneous frequency may be faster See Figure 19 2 below for more information if gt FCM min Femin Fomout if lt Fommin Fem Femout Figure 19 2 Example Clock Multiplier Output Rev 1 3 181 SILICON LABS 8051 58 59 SFR Definition 19 5 CLKMUL Clock Multiplier Bit 6 5 4 3 2 1 0 Name MULEN MULINIT MULRDY MULDIV 2 0 MULSEL 1 0 Type R W R W R R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x97 SFR Page
305. ic 1 for n 0 to 2 PCAOCPMn cIc c c cicicic F F F F F F 5 4 3 2 10 PCAOMD PCAOPWM DEMORO PCAO Counter Timer 8 9 10 or 11 bit Overflow T Set 8 9 10 or 11 bit Operation Counter Timer 16 0 bit Overflow 1 ECCFO 1 5 EPCAO d EA d 0 0 Interrupt PCA Module 0 oo oo o o gt Priority CCFO 1 Z 1 1 Decoder ECCF1 v PCA Module 1 0 CCF1 x o ECCF2 Y PCA Module 2 0 CCF2 oo ECCF3 Y PCA Module 3 0 ECCF4 v PCA Module 4 0 CCFA b oo ECCF5 Y PCA Module 5 0 CCF5 Figure 28 3 PCAO Interrupt Block Diagram Rev 1 3 316 SILICON LABS 8051 58 59 28 3 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes Edge triggered Capture Software Timer High Speed Output Frequency Output 8 to 11 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator Each module has Special Function Registers SFRs associated with it in the CIP 51 system controller These registers are used to exchange data with a module and configure the module s mode of operation Table 28 2 summarizes the bit settings in the PCAOCPMn and PCAOPWM regis
306. ics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched SRMT Shift Register Empty valid in slave mode only This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the receive buffer It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK SRMT 1 when in Master Mode RXBMT Receive Buffer Empty valid in slave mode only This bit will be set to logic 1 when the receive buffer has been read and contains no new information If there is new information available in the receive buffer that has not been read this bit will return to logic 0 RXBMT 1 when in Master Mode Note In slave mode data on MOSI is sampled in the center of each data bit master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device See Table 26 1 for timing parameters 279 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 26 2 SPIOCN SPIO Control Bit 7 6 5 4 3 2 1 0 Name SPIF WCOL RXOVRN NSSMDJ 1 0 TXBMT SPIEN Type R W R W R W R W R W R R W Reset 0 0 0 0 0 1 1 0 SFR Address O
307. if a missing clock condition is detected 1 PORSF Power On Vpp Monitor Writing a 1 enables the Set to 1 anytime a power Reset Flag and Vpp monitor Monitor as reset or monitor reset Reset Enable source occurs Writing 1 to this bit When set to 1 all other before the monitor RSTSRC flags are inde is enabled and stabilized terminate may cause a system reset 0 PINRSF HW Pin Reset Flag N A Set to 1 if RST pin caused the last reset Note Do not use read modify write operations on this register 157 Rev 1 3 SILICON LABS 8051 58 59 18 External Data Memory Interface On Chip XRAM For C8051F58x F59x devices 8 kB of RAM are included on chip and mapped into the external data mem ory space XRAM Additionally an External Memory Interface EMIF is available on the C8051F580 1 4 5 and C8051F588 9 F590 1 devices which can be used to access off chip data memories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX and the data pointer DPTR or using the MOVX indirect addressing mode using RO or R1 If the MOVX instruction is used with an 8 bit address operand such as QR1 then the high byte of the 16 bit address is provided by the External Memory Interface Control Register EMIOCN shown in SFR Definition 18 1 Note The instruction can also be used for writing
308. ight jus tified ADOLJST 0 and unused bits in the ADCOH and ADCOL registers are set to 0 The following example shows right justified codes for repeat counts greater than 1 Notice that accumulating 2 samples is equivalent to left shifting by n bit positions when all samples returned from the ADC have the same value Input Voltage Repeat Count 4 Repeat Count 8 Repeat Count 16 Vngr 4095 4096 Ox3FFC Ox7FF8 OxFFFO Vngr X 2048 4096 0x2000 0x4000 0x8000 2047 4096 Ox1FFC Ox3FF8 Ox7FFO 0 0x0000 0x0000 0x0000 6 2 1 Settling Time Requirements A minimum tracking time is required before an accurate conversion is performed This tracking time is determined by any series impedance including the resistance the ADCO sampling capacitance and the accuracy required for the conversion Figure 6 5 shows the equivalent ADCO input circuit The required ADCO settling time for a given settling accuracy SA may be approximated by Equation 6 1 When measuring the Temperature Sensor output use the tracking time specified in Table 5 11 on page 52 When measuring Vpp with respect to GND TAL reduces to See Table 5 10 for ADCO minimum settling time requirements as well as the mux impedance and sampling capacitor values on t Z X RroTALCSAMPLE Equation 6 1 ADC0 Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle wi
309. ils 12 2 Data Memory The C8051F58x F59x devices include 8448 bytes of RAM data memory 256 bytes of this memory is mapped into the internal RAM space of the 8051 The other 8192 bytes of this memory is on chip exter nal memory The data memory map is shown in Figure 12 1 for reference Rev 1 3 104 SILICON LABS 8051 58 59 12 2 1 Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through OxFF The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory Either direct or indirect addressing may be used to access the lower 128 bytes of data memory Locations 0x00 through Ox1F are addressable as four banks of general purpose registers each bank consisting of eight byte wide registers The next 16 bytes locations 0x20 through Ox2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode The upper 128 bytes of data memory are accessible only by indirect addressing This region occupies the same address space as the Special Function Registers SFR but is physically separate from the SFR space The addressing mode used by an instruction when accessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs Instructions that use direct addressing will access the SFR space Instructions using indirect addressing above Ox7F access the upper 128 bytes of dat
310. ime a byte is received indicat ing that an outgoing ACK value is needed When is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to the ACK bit however SCL will remain low until SI is cleared If a received slave address is not acknowledged further slave events will be ignored until the next START is detected The ARBLOST bit indicates that the interface has lost an arbitration This may occur anytime the interface is transmitting master or slave A lost arbitration while operating as a slave indicates a bus error condi tion ARBLOST is cleared by hardware each time SI is cleared The SI bit SMBus Interrupt Flag is set at the beginning and end of each transfer after each byte frame or when an arbitration is lost see Table 23 3 for more details Important Note About the SI Bit The SMBus interface is stalled while SI is set thus SCL is held low and the bus is stalled until software clears SI 246 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 23 2 SMBOCN SMBus Control SILICON LABS Rev 1 3 Bit 7 6 5 4 3 2 1 0 Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK Sl Type R R R W R W R R R W R W Reset 0 0 0 0 0 0 0 0 SFR Address
311. in are trademarks of their respective holders Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 USA SILICON LABS
312. instructions regarding how to explicitly locate variables in different memory areas Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash 15 4 3 System Clock 1 If operating from an external crystal be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature If the system is operating in an electrically noisy environment use the internal oscillator or use an external CMOS clock If operating from the external oscillator switch to the internal oscillator during Flash write or erase operations The external oscillator can continue to run and the CPU can switch back to the external oscillator after the Flash operation has completed Additional Flash recommendations and example code can be found in 201 Writing to Flash from Firm ware available from the Silicon Laboratories web site Rev 1 3 144 SILICON LABS 8051 58 59 SFR Definition 15 1 PSCTL Program Store R W Control Bit 7 6 5 4 3 2 1 0 Name PSEE PSWE Type R R R R R R R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0 8 SFR Page 0x00 Bit Name Function 7 2 Unused Read 000000b Write don t care 1 PSEE Program Store Erase Enable Setting this bit in combination with PSWE allow
313. ions Analog Function Potentially Assignable SFR s used for Port Pins Assignment ADC Input P0 0 P3 7 ADCOMX PnSKIP or Compartor1 Input P0 0 P2 7 CPTOMX CPT1MX PnSKIP Voltage Reference VREFO P0 0 REF0CN PnSKIP External Oscillator in Crystal Mode XTAL1 P0 2 OSCXCN PnSKIP External Oscillator in RC C or Crystal Mode XTAL2 P0 3 OSCXCN PnSKIP Notes 1 1 7 are only available on the 48 and 40 pin packages 2 If VDD is selected as the voltage reference in the REF0CN register and the ADC is enabled in the ADCOCN register the PO 0 VREF pin cannot operate as a general purpose pin in open drain mode With the above settings this pin can operate in push pull output mode or as an analog input 20 2 2 Assigning Port I O Pins to Digital Functions Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO Most digital functions rely on the Crossbar for pin assignment however some digital functions bypass the Crossbar in a manner similar to the analog functions listed above Port pins used by these digital func tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set to 1 Table 20 2 shows all available digital functions and the potential mapping of Port I O to each digital function 191 Rev 1 3 SILICON LABS 8051 58 59 Table 20 2 Port I O Assignment f
314. iority level 1 Timer 1 Interrupt Priority Control This bit sets the priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupt set to high priority level PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level PTO Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupt set to low priority level 1 Timer 0 interrupt set to high priority level PX0 External Interrupt 0 Priority Control This bit sets the priority of the External Interrupt 0 interrupt 0 External Interrupt 0 set to low priority level 1 External Interrupt 0 set to high priority level 131 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 14 3 EIE1 Extended Interrupt Enable 1 Bit 1 Name ELINO ET3 ECP1 ECPO EADCO EWADCO ESMBO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 SFR Address OxE6 SFR Page All Pages Bit Name Function 7 ELINO ET3 Enable LINO Interrupt This bit sets the masking of the LINO interrupt 0 Disable LINO interrupts 1 Enable interrupt requests generated by the LINOINT flag Enable Timer 3 Interrupt This
315. is attempted while these operations are disabled the Flash will be perma nently locked from writes or erasures until the next device reset If an application never writes to Flash it can intentionally lock the Flash by writing a non 0xA5 value to FLKEY from software Read When read bits 1 0 indicate the current Flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases disabled until the next reset Rev 1 3 146 8051 58 59 SFR Definition 15 3 FLSCL Flash Scale Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved FLRT Reserved Reserved FLEWT Reserved Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xB6 SFR Page All Pages Bit Name Function 7 5 Reserved Must Write 000b 4 FLRT Flash Read Time Control This bit should be programmed to the smallest allowed value according to the system clock speed 0 SYSCLK lt 25 MHz Flash read strobe is one system clock 1 SYSCLK gt 25 MHz Flash read strobe is two system clocks 3 2 Reserved Must Write 000 1 FLEWT Flash Erase Write Time Control This bit should be set to 1b before Writing or Erasing Flash 0 Short Flash Erase Write Timing 1 Extended Flash Erase Write Timing 0 Reserved Must Write Ob 147 Rev 1 3 SILICON
316. is bit is set Timer 3 operates as two 8 bit timers with auto reload 0 Timer 3 operates in 16 bit auto reload mode 1 Timer 3 operates as two 8 bit auto reload timers 2 TR3 Timer 3 Run Control Timer 3 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables only TMR3L is always enabled split mode 1 Unused Read Ob Write Don t Care 0 T3XCLK Timer 3 External Clock Select This bit selects the external clock source for Timer 3 If Timer 3 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 3 Clock Select bits T3MH and T3ML in register CKCON may still be used to select between the external clock and the system clock for either timer 0 Timer 3 clock is the system clock divided by 12 1 Timer 3 clock is the external clock divided by 8 synchronized with SYSCLK 304 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 27 14 TMR3RLL Timer 3 Reload Register Low Byte Bit 7 6 5 4 3 Name TMR3RLL 7 0 Reset 0 0 0 0 0 SFR Address 0x92 SFR Page 0x00 Bit Name Function 7 0 TMR3RLL 7 0 Timer 3 Reload Register Low Byte TMR3RLL holds the low byte of the reload value for Timer SFR Definition 27 15 TMR3RLH Timer 3 Reload Register High Byte Bit 7 6 5 4 3 Name TMR
317. is incremented on each high to low transition at the selected input pin Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sam pled Rev 1 3 285 SILICON LABS 8051 58 59 SFR Definition 27 1 CKCON Clock Control Bit 7 6 5 4 3 2 Name T2MH T2ML TOM SCA 1 0 Type R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 SFR Address 0 8 SFR Page All Pages Bit Name Function 7 Timer 3 High Byte Clock Select Selects the clock supplied to the Timer 3 high byte split 8 bit timer mode only 0 Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN 1 Timer 3 high byte uses the system clock 6 T3ML_ Timer 3 Low Byte Clock Select Selects the clock supplied to Timer 3 Selects the clock supplied to the lower 8 bit timer in split 8 bit timer mode 0 Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN 1 Timer 3 low byte uses the system clock 5 T2MH Timer 2 High Byte Clock Select Selects the clock supplied to the Timer 2 high byte split 8 bit timer mode only 0 Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 high byte uses the system clock 4 T2ML Timer 2 Low
318. is set SCL is held low and the SMBus is stalled 247 8051 58 59 Table 23 3 Sources for Hardware Changes to SMBOCN Bit Set by Hardware When Cleared by Hardware When MASTER m A START is generated m ASTOP is generated m Arbitration is lost TXMODE START is generated m A START is detected SMBODAT is written before the start of an m Arbitration is lost SMBus frame m SMBODAT is not written before the start of an SMBus frame STA m A START followed by an address byte is m Must be cleared by software received STO m A STOP is detected while addressed asa m A pending STOP is generated slave m Arbitration is lost due to a detected STOP ACKRQ m Abyte has been received and an ACK m After each ACK cycle response value is needed ARBLOST m Arepeated START is detected as a m Eachtime Sl is cleared MASTER when STA is low unwanted repeated START m SCLis sensed low while attempting to generate a STOP or repeated START condition m SDAis sensed low while transmitting a 1 excluding ACK bits ACK m Theincoming ACK value is low m Theincoming ACK value is high ACKNOWLEDGE NOT ACKNOWLEDGE SI m A START has been generated m Must be cleared by software Lost arbitration m Abyte has been transmitted and an ACK NACK received m Abyte has been received m ASTART or repeated START followed by a slave address R W has been received m ASTOP has been received 248 Rev 1 3
319. iting to PCAOCPHn sets ECOMn to 1 65536 PCAOCPn 65536 Equation 28 4 16 Bit PWM Duty Cycle Using Equation 28 4 the largest duty cycle is 10096 PCAOCPn 0 and the smallest duty cycle is 0 001596 PCAOCPn OxFFFF A 0 duty cycle may be generated by clearing the ECOMn bit to 0 Duty Cycle 323 Rev 1 3 SILICON LABS 8051 58 59 Write to PCAOCPLn 0 Reset gt Write to gt 1 yPCAOCPMn 1 6 TT OOxO0 x NZ SZ posean 1 E 16 bit Comparator match Q CEXnI Crossbar P Port VO 1 P 4 R Timebase PCAOH PCAOL Overflow Figure 28 10 PCAO 16 Bit PWM Mode 28 4 Watchdog Timer Mode A programmable watchdog timer WDT function is available through the PCAO Module 5 The WDT is used to generate a reset if the time between writes to the WDT update register PCAOCPH2 exceed a specified limit The WDT can be configured and enabled disabled as needed by software With the WDTE bit set in the PCAOMD register Module 5 operates as a watchdog timer WDT Mod ule 2 high byte is compared to the PCAO counter high byte the Module 2 low byte holds the offset to be used when WDT updates a
320. itration while attempt ing a repeated START Acknowledge received byte Read SMBODAT NACK received byte Abort failed transfer Reschedule failed transfer Lost arbitration due to a detected STOP Abort failed transfer Reschedule failed transfer Bus Error Condition Slave Receiver SILICON LABS Lost arbitration while transmit ting a data byte as master Rev Abort failed transfer Reschedule failed transfer 1 3 255 8051 58 59 24 UARTO UARTO is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with a 16 bit timer and selectable prescaler is included which can generate a wide range of baud rates details in Section 24 1 Baud Rate Generator on page 256 A received data FIFO allows to receive up to three data bytes before data is lost and an overflow occurs UARTO has six associated SFRs Three are used for the Baud Rate Generator SBCONO SBRLHO and SBRLLO two are used for data formatting control and status functions SCONO SMODO and one is used to send and receive data SBUFO The single SBUFO location provides access to both transmit and receive registers Writes to SBUFO always access the Transmit register Reads of SBUFO always access the buffered Receive register it is not possible to read data from the Transmit register With UARTO interru
321. k Value Selects P1 pins to be compared to the corresponding bits in P1MAT 0 P1 n pin logic value is ignored and cannot cause a Port Mismatch event 1 P1 n pin logic value is compared to P1MAT n SFR Definition 20 8 P1MAT Port 1 Match Register Bit 7 6 5 4 3 2 1 0 1 7 0 R W Reset 1 1 1 1 1 1 1 1 SFR Address OxF3 SFR Page 0x00 Bit Name Function 7 0 1 7 0 Port 1 Match Value Match comparison value used on Port 1 for bits in PIMAT which are set to 1 0 P1 n pin logic value is compared with logic LOW 1 P1 n pin logic value is compared with logic HIGH 201 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 9 P2MASK Port 2 Mask Register Bit 7 6 5 4 3 2 1 0 Name P2MASK 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0xB2 SFR Page 0x00 Bit Name Function 7 0 P2MASK 7 0 Port 2 Mask Value Selects P2 pins to be compared to the corresponding bits in P2MAT 0 P2 n pin logic value is ignored and cannot cause a Port Mismatch event 1 P2 n pin logic value is compared to P2MAT n SFR Definition 20 10 P2MAT Port 2 Match Register Bit 4 3 2 1 0 2 7 0 R W Reset 1 1 1 Bit Name SFR Address
322. k week 24 1124 if the RST pin is held low for more than 1 second while power is applied to the device and then RST is released a percentage of devices may lock up and fail to execute code Toggling the RST pin does not clear the condition The condition is cleared by cycling power Most devices that are affected will show the lock up behavior only within a narrow range of temperatures a 5 to 10 window Parts with a date code of year 2011 work week 24 1124 or later do not have any restrictions on RST low time The date code is included in the bottom most line of the package top side marking The date code is a four digit number with the format YYWW where YY is the two digit calendar year and WW is the two digit work week VDD 2 45 2 25 2 0 1 0 t Logic HIGH Logic LOW VDD Power On Monitor Reset Reset Figure 17 2 Power On and Vpp Monitor Reset Timing 153 Rev 1 3 SILICON LABS 8051 58 59 17 2 Power Fail Reset Vpp Monitor When a power down transition or power irregularity causes Vpp to drop below the power supply monitor will drive the RST pin low and hold the CIP 51 in a reset state see Figure 17 2 When Vpp returns to a level above Vnsr the CIP 51 will be released from the reset state Note that even though internal data memory contents are not altered by the power fail reset it is impossible to determine if Vpp dropped below
323. latch SFR Definition 24 4 SBCONO UARTO Baud Rate Generator Control Bit 7 6 5 4 3 2 1 0 Name Reserved SBORUN Reserved Reserved Reserved Reserved SBOPS 1 0 Type R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address OxAB SFR Page OxOF Bit Name Function 7 Reserved Read 0b Must Write Ob 6 SBORUN Baud Rate Generator Enable 0 Baud Rate Generator disabled UARTO will not function 1 Baud Rate Generator enabled 5 2 Reserved Read 00006 Must Write 00006 1 0 SBOPS 1 0 Baud Rate Prescaler Select 00 Prescaler 12 01 Prescaler 4 10 Prescaler 48 11 Prescaler 1 263 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 24 5 SBRLHO UARTO Baud Rate Generator Reload High Byte Bit 7 6 5 4 3 2 1 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address OxAD SFR Page OxOF Bit Name Function 7 0 SBRLHO 7 0 High Byte of Reload Value for UARTO Baud Rate Generator This value is loaded into the high byte of the UARTO baud rate generator when the counter overflows from OxFFFF to 0x0000 SFR Definition 24 6 SBRLLO UARTO Baud Rate Generator Reload Low Byte Bit 7 6 5 4 3 2 1 0 Name SBRLLO 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address SFR Page OxOF Bit Name
324. lator and scaled per the IFCN bits in reg ister OSCICN 01 SYSCLK derived from the External Oscillator circuit 10 SYSCLK derived from the Clock Multiplier 11 reserved 177 Rev 1 3 SILICON LABS 8051 58 59 19 2 Programmable Internal Oscillator All C8051F58x F59x devices include a programmable internal high frequency oscillator that defaults as the system clock after a system reset The internal oscillator period can be adjusted via the OSCICRS and OSCIFIN registers defined in SFR Definition 19 3 and SFR Definition 19 4 On C8051F58x F59x devices OSCICRS and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency Note that the system clock may be derived from the programmed internal oscillator divided by 1 2 4 8 16 32 64 or 128 as defined by the IFCN bits in register OSCICN The divide value defaults to 128 following a reset 19 2 1 Internal Oscillator Suspend Mode When software writes a logic 1 to SUSPEND OSCICN 5 the internal oscillator is suspended If the sys tem clock is derived from the internal oscillator the input clock to the peripheral or CIP 51 will be stopped until one of the following events occur Port 0 Match Event Port 1 Match Event Port 2 Match Event Port 3 Match Event Comparator 0 enabled and output is logic 0 When one of the oscillator awakening events occur the internal oscillator CIP 51 and affected peripherals resume normal operation
325. lator is odd and cleared if the sum is even 100 Rev 1 3 SILICON LABS 8051 58 59 11 4 Serial Number Special Function Registers SFRs The C8051F58x F59x devices include four SFRs SNO through SN3 that are pre programmed during pro duction with a unique 32 bit serial number The serial number provides a unique identification number for each device and can be read from the application firmware If the serial number is not used in the applica tion these four registers can be used as general purpose SFRs SFR Definition 11 7 SNn Serial Number n Bit 7 6 5 4 3 2 1 0 Name SERNUMn 7 0 Type R W Reset Varies Unique 32 bit value SFR Addresses SNO OxF9 SN1 SN2 OxFB SN3 OxFC SFR Page 0x0F Bit Name Function 7 0 SERNUMn 7 0 Serial Number Bits The four serial number registers form a 32 bit serial number with SN3 as the most significant byte and SNO as the least significant byte Rev 1 3 101 SILICON LABS 8051 58 59 12 Memory Organization The memory organization of the CIP 51 System Controller is similar to that of a standard 8051 There are two separate memory spaces program memory and data memory Program and data memory share the same address space but are accessed via different instruction types The memory organization is shown in Figure 12 1 PROGRAM DATA MEMORY DATA MEMORY R
326. le 5 8 Crystal Oscillator Electrical Characteristics on page 50 Added a paragraph in External Crystal Example on page 185 regarding surface mount crystals and drive current m Removed recommendations to introduce a delay after enabling the VDD Monitor before enabling it as a reset source in Power Fail Reset VDD Monitor on page 154 357 Rev 1 3 SILICON LABS Simplicity Studio One click access to MCU and wireless tools documentation software source code libraries amp more Available for Windows Mac and Linux loT Portfolio SW HW Quality Support and Community www silabs com loT www silabs com simplicity www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laborat
327. le Ipp for gt 1 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V 5 MHz Idle Ipp 19 mA 50 MHz 5 MHz x 0 38 mA MHz 1 9 mA 43 Rev 1 3 SILICON LABS 8051 58 59 Table 5 2 Global Electrical Characteristics Continued 40 to 125 C 24 MHz system clock unless otherwise specified Parameter Conditions Vpp 2 6 V F 200 kHz Vpp 2 6 V F 1 5 MHz Vpp 2 6 V F 25 MHz Vpp 2 6 V F 50 MHz Ipp Supply Sensitivity4 F 25 MHz F 1 MHz Ipp Frequency Sensitivity 5 Vpp 2 1V F lt 12 5 MHz T 25 2 1V F gt 12 5 MHz T 25 2 6V lt 12 5 MHz T 25 Vpp 2 6V F gt 12 5 MHz T 25 C gt Given in Table 5 4 on page 48 Vio should not be lower than the Vpp voltage SYSCLK must be at least 32 kHz to enable debugging Based on device characterization data Not production tested Does not include oscillator supply current IDD can be estimated for frequencies lt 15 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range When using these numbers to estimate Ipp for gt 15 MHz the estimate should be the current at 50 MHz minus the difference in current indicated by the frequency sensitivity number For example Vpp 2 6 V F 20 MHz Ipp 21 mA 5
328. le the Crossbar is disabled 195 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 1 XBRO Port I O Crossbar Register 0 Bit 7 6 5 4 3 2 1 0 CP1AE CP1E CPOAE CPOE SMBOE SPIOE CANOE URTOE Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0 1 SFR Page Ox0F Bit Name Function 7 1 Asynchronous Output Enable 0 Asynchronous CP1 unavailable at Port pin 1 Asynchronous CP1 routed to Port pin 6 CP1E Comparator1 Output Enable 0 CP1 unavailable at Port pin 1 CP1 routed to Port pin 5 Comparator0 Asynchronous Output Enable 0 Asynchronous unavailable at Port pin 1 Asynchronous routed to Port pin 4 CPOE Comparator0 Output Enable 0 CPO unavailable at Port pin 1 CPO routed to Port pin 3 SMBOE SMBus I O Enable 0 SMBus I O unavailable at Port pins 1 SMBus routed to Port pins 2 SPIOE SPII O Enable 0 SPI I O unavailable at Port pins 1 SPI I O routed to Port pins Note that the SPI can be assigned either 3 or 4 GPIO pins 1 I O Output Enable 0 CAN unavailable at Port pins 1 CAN TX CAN routed to Port pins P0 6 and 0 7 0 URTOE UARTO I O Output Enable 0 UARTO I O unavailable at Port pin 1 UARTO TXO routed to Port pins P0 4 and P0 5 SILICON LABS Rev 1 3 196
329. lect ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD Nonmuxed 8 bit READ without Bank Select ADDR 15 8 ADDR 7 0 DATA 7 0 RD Figure 18 5 Non multiplexed 8 bit MOVX without Bank Select Timing Rev 1 3 170 SILICON LABS C8051F58x F59x 18 6 1 3 8 bit MOVX with Bank Select EMIOCF 4 2 110 Nonmuxed 8 bit WRITE with Bank Select ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD Nonmuxed 8 bit READ with Bank Select ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR Figure 18 6 Non multiplexed 8 bit MOVX with Bank Select Timing 171 Rev 1 3 SILICON LABS 8051 58 59 18 6 2 Multiplexed Mode 18 6 2 1 16 bit MOVX EMIOCF 4 2 001 010 or 011 Muxed 16 bit WRITE ADDR 15 8 AD 7 0 i lt y gt WR RD Muxed 16 bit READ ADDR 15 8 AD 7 0 Figure 18 7 Multiplexed 16 bit MOVX Timing Rev 1 3 172 SILICON LABS 8051 58 59 18 6 2 2 8 bit MOVX without Bank Select EMIOCF 4 2 001 or 011 Muxed 8 bit WRITE Without Bank Select ADDR 15 8 AD 7 0 Muxed 8 bit READ Without Bank Select ADDR 15 8 AD 7 0 ALE RD y WR Figure 18 8 Multiplexed 8 bit MOVX without Bank Select Timing 173 Rev 1 3 SILICON LABS 8051 58 59 18 6 2 3 8 bit MOVX with Bank Select EMIOCF 4 2
330. ler Master and Slave capable no crystal required Two Hardware enhanced UARTs SMBus and enhanced SPI serial ports Six general purpose 16 bit counter timers Two 16 Bit programmable counter array PCA peripherals with six capture compare modules each and enhanced PWM functionality Clock Sources Internal 24 MHz with 0 5 accuracy for CAN and master LIN operation External oscillator Crystal RC C or clock 1 or 2 pin modes Can switch between clock sources on the fly useful in power saving modes Packages 48 Pin QFP QFN C8051F580 1 4 5 40 Pin QFN C8051F588 9 F590 1 82 Pin QFP QFN C8051F582 3 6 7 ANALOG PERIPHERALS DIGITAL I O UART 0 1 External Memory Interface Voltage VREG Comparators 0 2 VREF 24 MHz PRECISION m INTERNAL OSCILLATOR 2x Clock Multiplier HIGH SPEED CONTROLLER CORE 8051 CPU 128 kB ISP FLASH 50 MIPS IKE AAM FLEXIBLE DEBUG WDT INTERRUPTS CIRCUITRY Rev 1 3 10 15 Copyright 2015 by Silicon Laboratories C8051F580 1 2 3 4 5 6 7 8 9 F590 1 8051 58 59 Table of Contents 1 System OVvervieW J u U UTU UUS uuu 18 2 Ordering Information UU rond uada a aru s 22 3 It iiDjL 24 4 Package Specifications
331. less of the interrupt s enable disable state Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR IE EIE1 or EIE2 However interrupts must first be globally enabled by setting the EA bit IE 7 to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable settings Note Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruc tion that has two or more opcode bytes Using EA global interrupt enable as an example in C EA 0 clear EA bit EA 0 this is a dummy instruction with two byte opcode in assembly CLR EA clear EA bit CLR EA this is a dummy instruction with two byte opcode For example if an interrupt is posted during the execution phase of a CLR EA opcode or any instruction which clears a bit to disable an interrupt source and the instruction is followed by a single cycle instruc tion the interrupt may be taken However a read of the enable bit will return a 0 inside the interrupt service routine When the bit clearing opcode is followed by a multi cycle instruction the interrupt will not be taken Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR However most are not cleared by the hardware and must be cleared by
332. lti Voltage System 189 20 2 Assigning Port I O Pins to Analog and Digital Functions 189 20 2 1 Assigning Port I O Pins to Analog Functions 189 20 2 2 Assigning Port Pins to Digital Functions 189 20 2 3 Assigning Port Pins to External Digital Event Capture Functions 190 20 3 Priority Crossbar Decoder 190 20 4 Port I O Initialization 193 20 5 Port Male 198 20 6 Special Function Registers for Accessing and Configuring Port I O 202 21 Local Interconnect Network LINO0 J J 212 21 1 Software Interface with the LIN Controller 213 21 2 LIN Interface Setup and 213 21 21 Mode 213 21 2 2 Baud Rate Options Manual or Autobaud 213 21 2 3 Baud Rate Calculations Manual 213 21 2 4 Baud Rate Calculations Automatic Mode 215 21 3 LIN Master Mode 216 Rev 1 3 5 SILICON LABS C8051F58x F5
333. match rising edge occurs The CF1 flag in PCA1CN can be used to detect the overflow falling edge The duty cycle for 16 Bit PWM Mode is given by Equation 29 4 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA1 Cap ture Compare registers the low byte should always be written first Writing to PCA1CPLn clears the 1 bit to 0 writing to PCA1CPHn sets ECOM1n to 1 65536 PCAICPn 65536 Equation 29 4 16 Bit PWM Duty Cycle Using Equation 29 4 the largest duty cycle is 10096 PCA1CPn 0 and the smallest duty cycle is 0 001596 PCA1CPn OxFFFF A 0 duty cycle may be generated by clearing the 1 bit to 0 Duty Cycle Write to PCA1CPLn 0 Reset D Write to PCA1CPHn P 1 wPCA1CPMn P E C C MIT PIE MO ta referee PCA1CPHn PCA1CPLn 1MPINIn 1 CAIC caie 6 111 1 1 1 1 1 00x0 x 1 16 bit Comparator mate s EX Crossbar F Port O 1 gt Ran 1 Timebase PCA1H PCA1L Overflow Figure 29 10 PCA1 16 Bit PWM Mode 344 Rev 1 3 SILICON LABS 8051 58 59 29 4 Register Descriptions for PCA1 Following are detailed descriptions of the special function registers related to the operation of the PCA SFR Definition 29 1 PCA1CN PCA1 Control Bit
334. mer 3 External Clock Select bit T3XCLK as follows T3MH T3XCLK TMR3H Clock Source T3ML T3XCLK TMR3L Clock Source 0 0 SYSCLK 12 0 0 SYSCLK 12 0 1 External Clock 8 0 1 External Clock 8 1 X SYSCLK 1 X SYSCLK Rev 1 3 301 SILICON LABS 8051 58 59 The bit is set when TMR3H overflows from OxFF to 0x00 the TF3L bit is set when TMR3L overflows from OxFF to 0x00 When Timer 3 interrupts are enabled an interrupt is generated each time TMR3H over flows If Timer 3 interrupts are enabled and TF3LEN 5 is set an interrupt is generated each time either TMR3L or TMR3H overflows When TF3LEN is enabled software must check the and TFSL flags to determine the source of the Timer interrupt The TF3H interrupt flags are not cleared by hardware and must be manually cleared by software T3XCLK SYSCLK 12 External Clock 8 ae oad To SMBus TMR3CN E c5 F E Interrupt F3LEN TMR3RLL eload SYSCLK B I L TSXCLK D TCLK TMR3L gt 2 Figure 27 8 Timer 3 8 Bit Mode Block Diagram 27 3 3 External Oscillator Capture Mode Capture Mode allows the external oscillator to be measured against the system clock Timer 3 can be clocked from the system clock or
335. meter pads Card Assembly 7 No Clean Type 3 solder paste is recommended 8 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components 39 Rev 1 3 SILICON LABS 8051 58 59 4 5 32 Package Specifications pi Las EL pp 4 lt 2 E J 5 2 S dew JIE IDE VIEW T IE 1il tail 2 it Identifier rimeter Lead 095 mt 5 _ u 3 ption ptior Ir lar Corner rner juare por ption 2 Edge Exposed E4 ill Back Figure 4 9 QFN 32 Package Drawing Table 4 9 QFN 32 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0 80 0 9 1 00 E2 3 20 3 30 3 40 A1 0 00 0 02 0 05 L 0 30 0 40 0 50 b 0 18 0 25 0 30 L1 0 00 0 15 D 5 00 BSC aaa 0 15 D2 3 20 3 30 3 40 bbb 0 15 e 0 50 BSC ddd 0 05 5 00 5 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variatio
336. ming Parameters 4224122 282 PCAO Timebase Input Options 313 PCAOCPM and PCAOPWM Bit Settings for Capture Compare Modules 315 Watchdog Timer Timeout Intervals1 324 PCA1 Timebase Input Options 2 332 PCA1CPM and PCA1PWM Bit Settings for PCA1 Capture Compare Modules 334 Rev 1 3 SILICON LABS 8051 58 59 List of Registers SFR Definition 6 4 ADCOCF ADCO Configuration 22 65 SFR Definition 6 5 ADCOH ADCO Data Word MSB 66 SFR Definition 6 6 ADCOL ADCO Data Word LSB 66 SFR Definition 6 7 ADCOCN ADCO Control 67 SFR Definition 6 8 ADCOTK ADCO Tracking Mode Select 68 SFR Definition 6 9 ADCOGTH ADCO Greater Than Data High Byte 69 SFR Definition 6 10 ADCOGTL ADCO Greater Than Data Low Byte 69 SFR Definition 6 11 ADCOLTH ADCO Less Than Data High Byte 70 SFR Definition 6 12 ADCOLTL ADCO Less Than Data Low Byte 70 SFR Definition 6 13 ADCOMX ADCO Chann
337. mode and a slave device 4 wire single master mode is active when NSSMD1 SPIOCN 3 1 In this mode NSS is configured as an output pin and can be used as a slave select signal for a single SPI device In this mode the output value of NSS is controlled in software with the bit NSSMDO SPIOCN 2 Additional slave devices can be addressed using general purpose I O pins Figure 26 4 shows a connection diagram for a master device in 4 wire master mode and two slave devices Rev 1 3 274 SILICON LABS 8051 58 59 Figure 26 2 Multiple Master Mode Connection Diagram Figure 26 3 3 Wire Single Master and 3 Wire Single Slave Mode Connection Diagram Figure 26 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram 275 Rev 1 3 SILICON LABS 8051 58 59 26 3 SPIO Slave Mode Operation When SPIO is enabled and not configured as a master it will operate as a SPI slave As a slave bytes are shifted in through the MOSI pin and out through the MISO by a master device controlling the SCK sig nal A bit counter in the SPIO logic counts SCK edges When 8 bits have been shifted through the shift reg ister the SPIF flag is set to logic 1 and the byte is copied into the receive buffer Data is read from the receive buffer by reading SPIODAT A slave device cannot initiate transfers Data to be transferred to the master device is pre loaded into the shift register by writing to SPIODAT Writ
338. mpt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration It is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address Bit0 R W direction bit one or more bytes of data and a STOP condition Bytes that are received by a master or slave are acknowledged ACK with a low SDA during a high SCL see Figure 23 3 If the receiving device does not ACK the transmitting device will read a NACK not acknowl edge which is a high SDA during a high SCL The direction bit R W occupies the least significant bit position of the address byte The direction bit is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation 240 Rev 1 3 SILICON LABS 8051 58 59 All transactions are initiated by a master with or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the trans action is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte For READ operations the slave transmits the data waiting for an
339. multiplexed and non multiplexed modes and the C8051F588 9 F590 1 devices support only multiplexed modes Accessing off chip memory is not sup ported by the C8051F582 3 6 7 devices 159 Rev 1 3 SILICON LABS 8051 58 59 Table 18 1 EMIF Pinout C8051F580 1 4 5 Multiplexed Mode Non Multiplexed Mode Signal Name Port Pin Signal Name Port Pin RD P1 6 RD P1 6 WR P1 7 WR 1 7 ALE P1 5 DO P4 0 DO AO P4 0 D1 P4 1 D1 A1 P4 1 D2 P4 2 D2 A2 4 2 D3 P4 3 D3 A3 P4 3 D4 P4 4 D4 A4 P4 4 D5 P4 5 D5 A5 P4 5 D6 P4 6 D6 A6 4 6 D7 P4 7 D7 A7 P4 7 AO P3 0 A8 P3 0 Al P3 1 AQ P3 1 A2 P3 2 A10 P3 2 11 4 4 12 4 5 5 1 5 A6 P3 6 14 6 7 7 15 7 A8 P2 0 E A9 P2 1 A10 P2 2 A11 P2 3 A12 P2 4 A13 P2 5 A14 P2 6 EE 15 2 7 SILICON LABS Rev 1 3 160 C8051F58x F59x Table 18 2 EMIF Pinout C8051F588 9 F590 1 Multiplexed Mode Signal Name Port Pin RD P1 6 WR 1 7 ALE P1 5 D0 AO P3 0 D1 A1 P3 1 D2 A2 P3 2 D3 A3 P3 3 D4 A4 P3 4 D5 A5 P3 5 D6 A6 P3 6 D7 A7 P3 7 A8 P2 0 A9 P2 1 A10 P2 2 A11 P2 3 A12 P2 4 A13 P2 5 A14 P2 6 A15 P2 7 161 Rev 1 3
340. n 27 15 TMR3RLH Timer 3 Reload Register High Byte 303 SFR Definition 27 16 TMR3L Timer 3 Low Byte 304 SFR Definition 27 17 TMR3H Timer 3 High Byte 304 SFR Definition 27 18 TMRnCN Timer 4 and 5 Control 308 SFR Definition 27 19 TMRnCF Timer 4 and 5 Configuration 309 SFR Definition 27 20 TMRnCAPL Timer 4 and 5 Capture Register Low Byte 310 SFR Definition 27 21 TMRnCAPH Timer 4 and 5 Capture Register High Byte 310 SFR Definition 27 22 TMRnL Timer 4 and 5 Low Byte 311 SFR Definition 27 23 TMRnH Timer 4 and 5 High Byte 311 SFR Definition 28 1 SFR Definition 28 2 SFR Definition 28 3 SFR Definition 28 4 SILICON LABS PCAO Control 325 PCAOMD PCAO Mode 326 PCAOPWM PCAO PWM Configuration 327 PCAOCPMn Capture Compare Mode 328 Rev 1 3 16 C8051F58x F59x SFR Definition 28 5 PCAOL PCAO Counter Timer Low Byte 329 SFR Definition 28 6 PCAOH PCAO Counter Timer High Byte 329 SFR Definition 28 7 PCAOCPLn PCAO Capture Mod
341. n Bits These bits select which Port pin is assigned to INT1 Note that this pin assignment is independent of the Crossbar INT1 will monitor the assigned Port pin without disturb ing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin 000 Select P1 0 001 Select P1 1 010 Select P1 2 011 Select P1 3 100 Select P1 4 101 Select P1 5 110 Select P1 6 111 Select P1 7 INOPL INTO Polarity 0 INTO input is active low 1 INTO input is active high 2 0 INOSL 2 0 INTO Port Pin Selection Bits These bits select which Port pin is assigned to INTO Note that this pin assignment is independent of the Crossbar INTO will monitor the assigned Port pin without disturb ing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin 000 Select P1 0 001 Select P1 1 010 Select P1 2 011 Select P1 3 100 Select P1 4 101 Select P1 5 110 Select P1 6 111 Select P1 7 137 Rev 1 3 SILICON LABS 8051 58 59 15 Flash Memory On chip re programmable Flash memory is included for program code and non volatile data storage The Flash memory can be programmed in system a single byte at a time through the C2 interface or by soft ware using the MOVX in
342. n VGGD except for custom features D2 E2 and L which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components SILICON LABS Rev 1 3 40 8051 58 59 1 1 Figure 4 10 QFN 32 Package Drawing Table 4 10 QFN 32 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 4 80 4 90 X2 3 20 3 40 C2 4 80 4 90 Y1 0 75 0 85 e 0 50 BSC Y2 3 20 3 40 X1 0 20 0 30 Notes General 1 All dimensions shown are in millimeters mm unless otherwise noted 2 This Land Pattern Design is based on the IPC 7351 guidelines Solder Mask Design 3 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 um minimum all the way around the pad Stencil Design 4 Astainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads 7 3x3 array of 1 0 mm openings on 1 20 mm pitch should be used for the center ground pad Card Assembly 8 No Clean Type 3 solder paste is recommended 9 The recommended card reflow profile is per the JEDEC IPC J ST
343. n WDLCK is set the WDT cannot be disabled until the next system reset If WDLCK is not set the WDT is disabled by clearing the WDTE bit The WDT is enabled following any reset The PCAO counter clock defaults to the system clock divided by 12 PCAOL defaults to 0x00 PCAOCPL5 defaults to 0x00 Using Equation 28 5 this results in WDT timeout interval of 256 PCAO clock cycles or 3072 system clock cycles Table 28 3 lists some example tim eout intervals for typical system clocks Table 28 3 Watchdog Timer Timeout Intervals System Clock Hz PCA0CPL5 Timeout Interval ms 24 000 000 255 32 8 24 000 000 128 16 5 24 000 000 32 4 2 3 000 000 255 262 1 3 000 000 128 132 1 3 000 000 32 33 8 187 5002 255 4194 187 5002 128 2114 187 5002 32 541 Notes 1 Assumes SYSCLK 12 as the PCAO clock source and a PCAOL value of 0x00 at the update time 2 Internal SYSCLK reset frequency Internal Oscillator divided by 128 Rev 1 3 326 SILICON LABS C8051F58x F59x 28 5 Register Descriptions for PCAO Following are detailed descriptions of the special function registers related to the operation of the PCA SFR Definition 28 1 PCAO Control Bit 7 6 5 4 3 2 1 0 Name CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCFO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD8 Bit Addressable SFR Page 0x00 Bit Name Functi
344. n a future interrupt occurs Therefore instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes for example in Crs PCON 0x01 set IDLE bit PCON PCON followed by a 3 cycle dummy instruction in assembly ORL PCON 01h set IDLE bit MOV PCON PCON Po followed by 3 cycle dummy instruction If enabled the Watchdog Timer WDT will eventually cause an internal watchdog reset and thereby termi nate the Idle mode This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register If this behavior is not desired the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation This pro vides the opportunity for additional power savings allowing the system to remain in the Idle mode indefi nitely waiting for an external stimulus to wake up the system Refer to Section 17 6 PCA Watchdog Timer Reset on page 156 for more information on the use and configuration of the WDT Rev 1 3 149 SILICON LABS 8051 58 59 16 2 Stop Mode Setting the Stop Mode Select bit PCON 1 causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution In Stop mode the internal oscillator CPU and all digital peripherals are stopped the state of the external oscillator circuit is not affected Each anal
345. n and g l l A 40 pin packages I ADOBUSY W P0 0 Hm VDD Stat Conversion Conversion Timer 1 Overflow SYSCLK Burst Mode CNVSTR Input Logic I Timer 2 Overflow Burst Mode Oscillator 25 MHz Max Accumulator P3 0 ADCOGNH ADCOGNL ADCOGNA ADOWINT Window Compare VDD Temp Sensor 5 8 E 6 ADCOLTL Ene 58888885 ADCOCF ADCOGTH ADCOGTL Figure 6 1 ADCO Functional Block Diagram Rev 1 3 54 SILICON LABS 8051 58 59 6 1 Modes of Operation In atypical system ADCO is configured using the following steps If a gain adjustment is required refer to Section 6 3 Selectable Gain on page 60 Choose the start of conversion source Choose Normal Mode or Burst Mode operation If Burst Mode choose the ADCO Idle Power State and set the Power Up Time Choose the tracking mode Note that Pre Tracking Mode can only be used with Normal Mode Calculate the required settling time and set the post convert start tracking time using the ADOTK bits Choose the repeat count Choose the output word justification Right Justified or Left Justified 9 Enable or disable the End of Conversion and Window Comparator Interrupts 6 1 1 Starting a
346. n enabled matches of the PCAO counter with a module s capture compare register cause the CCFn bit in PCAOMD register to be set to logic 1 2 TOGn Toggle Function Enable This bit enables the toggle function for PCAO module n when set to 1 When enabled matches of the PCAO counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module oper ates in Frequency Output Mode 1 PWMn Pulse Width Modulation Mode Enable This bit enables the PWM function for PCAO module n when set to 1 When enabled a pulse width modulated signal is output on the CEXn pin 8 to 11 bit PWM is used if PWM16n is cleared 16 bit mode is used if 1 is set to logic 1 If the TOGn bit is also set the module operates in Frequency Output Mode 0 ECCFn Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCFn interrupt 0 Disable CCFn interrupts 1 Enable a Capture Compare Flag interrupt request when CCFn is set Note When the WDTE bit is set to 1 the PCAOCPM5 register cannot be modified and module 5 acts as the watchdog timer To change the contents of the PCAOCPM5 register or the function of module 5 the Watchdog Timer must be disabled Rev 1 3 330 SILICON LABS 8051 58 59 SFR Definition 28 5 PCAOL PCAO Counter Timer Low Byte Bit 7 6 5 4 3 2 1 0 Name PCAO 7 0
347. n interrupt if enabled by EREGO EIE2 0 that is triggered whenever the Vreain input voltage drops below the dropout threshold voltage This dropout interrupt has no pending flag and the recommended procedure to use it is as follows 1 Wait enough time to ensure the input voltage is stable 2 Enable the dropout interrupt EREGO EIE2 0 and select the proper priority PREGO EIP2 0 3 If triggered inside the interrupt disable it clear EREGO EIE2 0 execute all procedures necessary to protect your application put it in a safe mode and leave the interrupt now disabled 4 In the main application now running in the safe mode regularly checks the DROPOUT bit REGOCN 0 Once it is cleared by the regulator hardware the application can enable the interrupt again EREGO EIE1 6 and return to the normal mode operation The input and output Vpp of the voltage regulator should both be bypassed with a large capaci tor 4 7 uF 0 1 to ground as shown in Figure 10 1 below This capacitor will eliminate power spikes and provide any immediate power required by the microcontroller The settling time associated with the voltage regulator is shown in Table 5 9 on page 50 Note The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event The output of the un calibrated internal regulator could be below the high threshold setting of the VDD Monitor If this is the case and t
348. n of data and acceptance filtering is performed by the CAN controller and not by the CIP 51 MCU In this way minimal CPU bandwidth is needed to use CAN communication The CIP 51 configures the CAN controller accesses received data and passes data for transmission via Special Function Registers SFRs in the CIP 51 C8051F580 F590 CAN Protocol Device CAN Protocol Device CAN Transceiver Isolation Buffer Optional CANTX CANRX CAN Transceiver Isolation Buffer Optional CAN Transceiver Isolation Buffer Optional CAN L Figure 22 1 Typical CAN Bus Configuration Rev 1 3 231 SILICON LABS 8051 58 59 22 1 Bosch CAN Controller Operation The CAN Controller featured in the C8051 F580 2 4 6 8 F590 devices is a full implementation of Bosch s full CAN module and fully complies with CAN specification 2 0B A block diagram of the CAN controller is shown in Figure 22 2 The CAN Core provides shifting CANTX and CANRX serial parallel conversion of messages and other protocol related tasks such as transmission of data and acceptance filtering The message RAM stores 32 message objects which can be received or transmitted on a CAN network The CAN registers and message handler provide an interface for data transfer and notification between the CAN controller and the CIP 51 The function and use of the CAN Controller is detailed in the Bosch CAN User s Guide The User s Guid
349. n the Reload Cap ture Registers TMRnCAPH and TMRnCAPL This is considered an underflow event and will cause the timer to load the value OxFFFF The timer is automatically restarted when an underflow occurs Counter Timer with Auto Reload mode is selected by clearing the CPRLn bit Setting TRn to logic 1 enables and starts the timer In Auto Reload Mode the External Flag EXFn toggles upon every overflow or underflow and does not cause an interrupt The EXFn flag can be used as the most significant bit MSB of a 17 bit counter 308 Rev 1 3 SILICON LABS 8051 58 59 TMRnCF D TITITIT E njnjO n 110 1 n a Es Toggle Logic 99 9 0 2 OxFF OxFF 1 U L gt Port Pin SYSCLK 4 12 1 1 C External Clock E ob XTAL1 8 Z 1 OVE pese TCLK TMRnL TMRnH Tn Crossbar H n gt ae ea TRn EXENn EXENn EXFn Interrupt pese M w eload ThE TMRnCAPL TMRnCAPH x Ll Figure 27 11 Timer 4 and 5 Auto Reload and Toggle Mode Block Diagram 27 4 4 Toggle Output Mode Timers 4 and 5 have the capability to toggle the state of their respective output port pins T4 or T5 to pro duce a 50 duty cycle waveform output The port pin state will chang
350. n the toggle mode is halted p 008 54 2x 65536 TMRnCAP Equation 27 1 Square Wave Frequency Rev 1 3 309 SILICON LABS 8051 58 59 SFR Definition 27 18 TMRnCN Timer 4 and 5 Control Bit 7 6 5 4 3 2 1 0 Name TFn EXFn EXEn TRn CTn CPRLn Type R W R W R W R W R W R W R R W Reset 0 0 0 0 0 0 0 0 TMR4CN SFR Address 0 8 Bit Addressable SFR Page 0x10 TMRS5CN SFR Address 0x91 SFR Page 0x10 Bit Name Function 7 TFn Timer 4 and 5 16 bit Overflow Underflow Flag Set by hardware when either the Timer overflows from OxFFFF to 0x0000 under flows from the value placed in TMRnCAPH TMRnCAPL to OxFFFF in Auto reload Mode or underflows from 0x0000 to OxFFFF in Capture Mode When the Timer interrupt is enabled setting this bit causes the CPU to vector to the Timer interrupt service routine This bit is not automatically cleared by hardware 6 EXFn Timer 4 and 5 External Flag Set by hardware when either a capture or reload is caused by a high to low transition on the TnEX input pin and EXENn is logic 1 This bit is not automatically cleared by hardware 5 4 Reserved Must Write 000 3 EXEn Timer 4 and 5 External Enable Enables high to low transitions on TnEX to trigger captures reloads and control the direction of the timer counter up or down count If DCENn 1 TnEX will determine if the timer counts up or
351. ndividual pages change Os to 15 in the Lock Byte Not Permitted Flash Error Reset Flash Error Reset Read Write or Erase Reserved Area Not Permitted Flash Error Reset Flash Error Reset reset C2 Device Erase Erases all Flash pages including the page containing the Lock Byte Flash Error Reset Not permitted Causes Flash Error Device Reset FERROR bit in RSTSRC is 1 after All prohibited operations that are performed via the C2 interface are ignored do not cause device reset Locking any Flash page also locks the page containing the Lock Byte Once written to the Lock Byte cannot be modified except by performing a C2 Device Erase If user code writes to the Lock Byte the Lock does not take effect until the next device reset SILICON LABS Rev 1 3 142 C8051F58x F59x 15 4 Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of Vpp system clock frequency or temperature This accidental execution of Flash modi fying code can result in alteration of Flash memory contents causing a system failure that is only recover able by re Flashing the code in the device The following guidelines are recommended for any system which contains routines which write or erase Flash from c
352. ne unused opcode 0xA5 that performs the same function as NOP All mnemonics copyrighted Intel Corporation 1980 11 3 CIP 51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP 51 System Controller Reserved bits should not be set to logic 1 Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0 selecting the feature s default state Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys tem function Rev 1 3 97 SILICON LABS 8051 58 59 SFR Definition 11 1 DPL Data Pointer Low Byte Bit 7 6 5 3 1 0 Name DPL 7 0 Type R W Reset 0 0 0 0 0 0 SFR Address 0x82 SFR Page All Pages Bit Name Function 7 0 DPL 7 0 Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indi rectly addressed Flash memory or XRAM SFR Definition 11 2 DPH Data Pointer High Byte Bit 7 6 5 3 1 0 DPH 7 0 Type R W Reset 0 0 0 0 0 0 SFR Address 0x83 SFR Page All Pages Bit Name Function 7 0 DPH 7 0 Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indi rectly addres
353. ng the following equation ADOPWR orTstartup ADOPWR 1 200ns 3 2 ADOTM 1 0 ADCO Tracking Mode Enable Select Bits 00 Reserved 01 ADCO is configured to Post Tracking Mode 10 ADCO is configured to Pre Tracking Mode 11 ADCO is configured to Dual Tracking Mode 1 0 ADOTK 1 0 ADCO Post Track Time 00 Post Tracking time is equal to 2 SAR clock cycles 2 FCLK cycles 01 Post Tracking time is equal to 4 SAR clock cycles 2 FCLK cycles 10 Post Tracking time is equal to 8 SAR clock cycles 2 FCLK cycles 11 Post Tracking time is equal to 16 SAR clock cycles 2 FCLK cycles 6 4 Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADCO output registers to user pro grammed limits and notifies the system when a desired condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag ADOWINT in register ADCOCN can also be used in polled mode The ADCO Greater Than ADCOGTH ADCOGTL and Less Than ADCOLTH ADCOLTL registers hold the comparison values The window detector flag can be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADCO Less Than and ADCO Greater Than registers Rev 1 3 68 SILICON LABS 8051 58 59
354. ng to PCA1CPLn clears the 1 bit to 0 writing to PCA1CPHn sets ECOM1n to 1 Write to PCA1CPLn Reset Write to PCA1CPHn 1 Interrupt W PCA1CN M C C C C C C C C 1 PCA1CPLn PCA1CPHn 6 1 1 1 1 1 918 7 6 n 1 0 00100 Enabl Match Yo able gt 16 bit Comparator ate oo 1 Timebase PP PCA1L PCA1H Figure 29 5 PCA1 Software Timer Mode Diagram 338 Rev 1 3 SILICON LABS 8051 58 59 29 3 3 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCA1 Counter and the module s 16 bit capture compare register PCA1CPHn and PCA1CPLn When a match occurs the Capture Compare Flag CCFn in PCA1ON is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Setting the TOG1n MAT1n and ECOMh1n bits in the PCA1CPMn register enables the High Speed Output mode If ECOM1n is cleared the associated pin will retain its state and not toggle on the next match event Important Note About Capture Compare Registers When writing a 16 bit value to the PCA1 Cap ture Compare registers
355. not be set An interrupt will occur if enabled when either or is set MARK START BIT 1 DO Y D1 Y D2 D3 D4 D5 D6 D7 STOP SPACE BIT A A A A A A A A A A SAMPLING Figure 25 4 8 Bit UART Timing Diagram 25 2 2 9 Bit UART 9 bit UART mode uses total of eleven bits per data byte a start bit 8 data bits LSB first a programma ble ninth data bit and a stop bit The state of the ninth transmit data bit is determined by the value in TB81 SCON1 3 which is assigned by user software It can be assigned the value of the parity flag bit P in reg ister PSW for error detection or used in multiprocessor communications On receive the ninth data bit goes into RB81 SCON1 2 and the stop bit is ignored Rev 1 3 267 SILICON LABS 8051 58 59 Data transmission begins when an instruction writes a data byte to the SBUF1 register The TI1 Transmit Interrupt Flag SCON1 1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the REN1 Receive Enable bit SCON1 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met 1 must be logic 0 and 2 if MCE1 is logic 1 the 9th bit must be logic 1 when MCE1 is logic 0 the state of the ninth data bit is unimportant If these conditions are met the eight bits of data a
356. nue to access SFRs as it did prior to the PCA interrupt Likewise the con tents of SFRLAST are moved to the SFRNEXT register Recall this was the SFR Page value 0x00 being used to access SPIODAT before the CANO interrupt occurred See Figure 13 5 Rev 1 3 110 SILICON LABS 8051 58 59 SFR Page 0 0 Automatically popped off of the stack on return from interrupt SFRPAGE SFRNEXT popped to SFRPAGE SFRNEXT SFRLAST popped to SFRNEXT SFRLAST Figure 13 5 SFR Page Stack Upon Return From PCA Interrupt On the execution of the RETI instruction in the CANO ISR the value in SFRPAGE register is overwritten with the contents of SFRNEXT The CIP 51 may now access the SPIODAT register as it did prior to the interrupts occurring See Figure 13 6 111 Rev 1 3 SILICON LABS 8051 58 59 SFR Page 0xC Automatically popped off of the stack on return from interrupt SFRPAGE Figure 13 6 SFR Page Stack Upon Return From CANO Interrupt SFRNEXT popped to SFRPAGE In the example above all three bytes in the SFR Page Stack are accessible via the SFRPAGE SFRNEXT and SFRLAST special function registers If the stack is altered while servicing an interrupt it is possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call Direct access to the SFR Page stack can be useful to enable real time operating systems to control and manage conte
357. ock is SYSCLK 10 Timer clock is External Clock 8 synchronized to system clock 11 Timer clock is SYSCLK 2 2 TOGn Timer 4 and 5 Toggle Output State When Timer 4 or 5 are used to toggle a port pin this bit can be used to read the state of the output or can be written to force the state of the output 1 TnOE Timer 4 and 5 Output Enable This bit enables the timer to output a 50 duty cycle output to the timer s assigned external port pin The Timer is configured for Square Wave Output as follows CPRLn 0 0 TnOE 1 Load TMRnCAPH TMRnCAPL 0 Output of toggle mode not available at Timer s assigned port pin 1 Output of toggle mode available at Timer s assigned port pin 0 DCENn Decrement Enable This bit enables the timer to count up or down as determined by the state of 0 Timer will count up regardless of the state of TnEX 1 Timer will count up or down depending on the state of TnEX as follows If TnEx 0 the timer counts down If TnEx 1 the timer counts up SILICON LABS Rev 1 3 311 8051 58 59 SFR Definition 27 20 TMRnCAPL Timer 4 and 5 Capture Register Low Byte Bit 7 6 5 4 3 2 1 0 TMRnRLI 7 0 Reset 0 0 0 0 0 0 0 0 TMR4CAPL SFR Address 0xCA TMR5CAPL SFR Address 0x92 SFR Page 0x10 Bit Name Function 7 0 TMRnCAPL T7 0 Timer n Reload Register Low Byte TMRnC
358. ode 15 4 1 Vpp Maintenance and the Vpp monitor 1 If the system power supply is subject to voltage or current spikes add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded Make certain that the minimum rise time specification of 1 ms is met If the system cannot meet this rise time specification then add an external Vpp brownout circuit to the RST pin of the device that holds the device in reset until Vpp reaches the minimum threshold and re asserts RST if Vpp drops below the minimum threshold Enable the on chip Vpp monitor to the high setting and enable the Vpp monitor as a reset source as early in code as possible This should be the first set of instructions executed after the Reset Vector For C based systems this will involve modifying the startup code added by the C compiler See your compiler documentation for more details Make certain that there are no delays in software between enabling the Vpp monitor and enabling the Vpp monitor as a reset source Code examples showing this can be found in AN201 Writing to Flash from Firmware available from the Silicon Laboratories web site As an added precaution explicitly enable the Vpp monitor and enable the Vpp monitor as a reset source inside the functions that write and erase Flash memory The Vpp monitor enable instructions should be placed just af
359. odule s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module oper ates in Frequency Output Mode 1 PWM1n Width Modulation Mode Enable This bit enables the PWM function for PCA1 module n when set to 1 When enabled a pulse width modulated signal is output on the CEXn pin 8 to 11 bit PWM is used if PWM16n is cleared 16 bit mode is used if 1 is set to logic 1 If the TOGn bit is also set the module operates in Frequency Output Mode 0 ECCF1n Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCFn interrupt 0 Disable CCFn interrupts 1 Enable a Capture Compare Flag interrupt request when CCFn is set 348 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 29 5 PCA1L 1 Counter Timer Low Byte The PCA1L register holds the low byte LSB of the 16 bit PCA1 Counter Timer Bit 7 6 5 4 3 2 1 0 Name PCA1 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0 9 SFR Page 0x10 Bit Name Function 7 0 PCA1 7 0 1 Counter Timer Low Byte SFR Definition 29 6 PCA1H PCA1 Counter Timer High Byte The PCA1H register holds the high byte MSB of the 16 bit PCA1 Counter Timer Reads of this register will read the contents of a snapshot
360. of its interrupt pending flag s 129 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 14 1 IE Interrupt Enable Bit 7 Name EA ESPIO ET2 ESO ET1 1 R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA8 Bit Addressable SFR Page All Pages Bit Name Function 7 EA ESPIO Enable All Interrupts Globally enables disables all interrupts It overrides individual interrupt mask settings 0 Disable all interrupt sources 1 Enable each interrupt according to its individual mask setting Enable Serial Peripheral Interface SPIO Interrupt This bit sets the masking of the SPIO interrupts 0 Disable all SPIO interrupts 1 Enable interrupt requests generated by SPIO ET2 Enable Timer 2 Interrupt This bit sets the masking of the Timer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable interrupt requests generated by the TF2L or TF2H flags ESO Enable UARTO Interrupt This bit sets the masking of the UARTO interrupt 0 Disable UARTO interrupt 1 Enable UARTO interrupt Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1 flag EX1 Enable External Interrupt 1 This bit sets the masking of External Interrupt 1 0 Disable external int
361. og peripheral including the external oscillator circuit may be shut down individually prior to entering Stop Mode Stop mode can only be terminated by an internal or external reset On reset the device performs the normal reset sequence and begins program execution at address 0x0000 If enabled the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 us 16 3 Suspend Mode Setting the SUSPEND bit OSCICN 5 causes the hardware to halt the CPU and the high frequency inter nal oscillator and go into Suspend mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data Most digital peripherals are not active in Sus pend mode The exception to this is the Port Match feature Suspend mode can be terminated by three types of events a port match described in Section 20 5 Port Match on page 200 a Comparator low output if enabled or a device reset event When Suspend mode is terminated the device will continue execution on the instruction following the one that set the SUSPEND bit If the wake event was configured to generate an interrupt the interrupt will be serviced upon waking the device If Suspend mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begin
362. omparator2 CP2 Interrupt This bit sets the masking of the CP2 interrupt 0 Disable CP2 interrupts 1 Enable interrupt requests generated by the CP2RIF or CP2FIF flags EPCA1 ES1 Enable Programmable Counter Array PCA1 Interrupt This bit sets the masking of the PCA1 interrupts 0 Disable all PCA1 interrupts 1 Enable interrupt requests generated by PCA1 Enable UART1 Interrupt This bit sets the masking of the UART1 interrupt 0 Disable UART1 interrupt 1 Enable UART1 interrupt EMAT Enable Port Match Interrupt This bit sets the masking of the Port Match interrupt 0 Disable all Port Match interrupts 1 Enable interrupt requests generated by a Port Match ECANO EREGO Enable CANO Interrupts This bit sets the masking of the CANO interrupt 0 Disable all CANO interrupts 1 Enable interrupt requests generated by CANO Enable Voltage Regulator Dropout Interrupt This bit sets the masking of the Voltage Regulator Dropout interrupt 0 Disable the Voltage Regulator Dropout interrupt 1 Enable the Voltage Regulator Dropout interrupt Rev 1 3 134 SILICON LABS 8051 58 59 SFR Definition 14 6 EIP2 Extended Interrupt Priority Enabled 2 Bit 7 6 5 4 3 2 1 0 Name PMAT PCANO PREGO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address OxF7 SFR Page All Pages Bit Name Function 7 PT5 Timer 5 Int
363. on 7 CF PCAO Counter Timer Overflow Flag Set by hardware when the PCAO Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CR PCAO Counter Timer Run Control This bit enables disables the PCAO Counter Timer 0 Counter Timer disabled 1 PCAO Counter Timer enabled CCF5 PCAO Module 5 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF5 interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF4 PCAO Module 4 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF4 interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF3 PCAO Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCAO interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software CCF2 PCAO Module
364. on the EMIF Mode bits in the EMIOCF register SFR Definition 18 2 These modes are summarized below More information about the different modes can be found in Section 18 6 Timing on page 167 EMIOCF 3 2 00 EMIOCF 3 2 01 EMIOCF 3 2 10 EMIOCF 3 2 11 OxFFFF OxFFFF OxFFFF OxFFFF On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM 0x0000 0x0000 0x0000 Figure 18 3 EMIF Operating Modes 0x0000 18 5 1 Internal XRAM Only When bits EMIOCF 3 2 are set to 00 all MOVX instructions will target the internal XRAM space on the device Memory accesses to addresses beyond the populated space will wrap on 8 kB boundaries As an example the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on chip XRAM space m 8 bit MOVX operations use the contents of EMIOCN to determine the high byte of the effective address and RO or R1 to determine the low byte of the effective address m 16 bit MOVX operations use the contents of the 16 bit DPTR to determine the effective address 18 5 2 Split Mode without Bank Select When bit EMIOCF 3 2 are set to 01 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the internal XRAM size boundary will access on chip XRAM space Effective addresses above the internal XRAM size boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to
365. only available on the 48 pin packages Output Configuration Bits for P4 7 P4 0 respectively 0 Corresponding P4 n Output is open drain 1 Corresponding P4 n Output is push pull 213 Rev 1 3 SILICON LABS 8051 58 59 21 Local Interconnect Network LINO Important Note This chapter assumes an understanding of the Local Interconnect Network LIN proto col For more information about the LIN protocol including specifications please refer to the LIN consor tium http www lin subbus org LIN is an asynchronous serial communications interface used primarily in automotive networks The Sili con Laboratories LIN controller is compliant to the 2 1 Specification implements a complete hardware LIN interface and includes the following features Selectable Master and Slave modes Automatic baud rate option in slave mode The internal oscillator is accurate to within 0 5 of 24 MHz across the entire temperature range and for VDD voltages greater than or equal to the minimum output of the on chip voltage regulator so an external oscillator is not necessary for master mode operation for most systems Note The minimum system clock SYSCLK required when using the LIN controller is 8 MHz C8051F580 2 4 6 8 F590 LIN Controller 8051 MCU Core LIN Data LIN Control LINOADR Registers Registers LINODAT Indirectly Addressed Registers Control State Machine LINOCF Figure 21 1 LIN Blo
366. or Digital Functions Digital Function Potentially Assignable Port Pins SFR s used for Assignment UARTO UART1 SPIO Any Port pin available for assignment by the XBRO XBR1 XBR2 SMBus LINO CPO Crossbar This includes 0 0 4 7 pins which XBR3 CPOA CP1 CP1A CP2 have their PnSKIP bit set to 0 CP2A SYSCLK PCAO Note The Crossbar will always assign UARTO pins 5 PCA1 to P0 4 and P0 5 and always assign CANO to 6 11 ECI1 TO T1 T4 6 and PO 7 or T5 Any pin used for GPIO P0 0 P4 7 POSKIP P1SKIP P2SKIP P3SKIP Note P3 1 P3 7 and P4 0 are only available on the 48 pin and 40 pin packages P4 1 P4 7 are only available on the 48 pin packages A skip register is not available for P4 20 2 3 Assigning Port I O Pins to External Digital Event Capture Functions External digital event capture functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital I O pin The digital event capture functions do not require dedicated pins and will function on both GPIO pins PnSKIP 1 and pins in use by the Crossbar PnSKIP 0 External digital event capture functions cannot be used on pins configured for analog I O Table 20 3 shows all available external digital event capture functions Table 20 3 Port Assignment for External Digital Event Capture Functions Digital Function Po
367. or details on Port configuration see Section 20 1 Port I O Modes of Operation on page 190 CPTnCN 93 i C Y C lo tor Input s ns Crossbar CPnA Reset L Decision loa Bes CPn CPnEN EA 0 Y o Interrupt 1 1 Figure 9 1 Comparator Functional Block Diagram Rev 1 3 77 SILICON LABS 8051 58 59 Comparator outputs can be polled in software used as an interrupt source and or routed to a Port pin When routed to a Port pin Comparator outputs are available asynchronous or synchronous to the system clock the asynchronous output is available even in STOP mode with no system clock active When dis abled the Comparator output if assigned to a Port I O pin via the Crossbar defaults to the logic low state and the power supply to the comparator is turned off See Section 20 3 Priority Crossbar Decoder on page 192 for details on configuring Comparator outputs via the digital Crossbar Comparator inputs can be externally driven from 0 25 V to Vpp 0 25 V without damage or upset The complete Comparator elec trical specifications are given in Table 5 13 The Comparator response time may be configured in software via the CPTnMD registers see SFR Defini tion 9 2 Selecting a longer response time reduces the Comparator supply current See Table 5 13 for complete timing an
368. ories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trademark Information Silicon Laboratories Inc Silicon Laboratories Silicon Labs SiLabs and the Silicon Labs logo CMEMS EFM EFM32 EFR Energy Micro Energy Micro logo and combinations thereof the world s most energy friendly microcontrollers Ember EZLink EZMac EZRadio amp EZRadioPRO DSPLL ISOmodem 6 Precision328 ProSLIC SIPHY USBXpress and others are trademarks or registered trademarks of Silicon Laboratories Inc ARM CORTEX Cortex M3 and THUMB are trademarks or registered trademarks of ARM Holdings Keil is a registered trademark of ARM Limited All other products or brand names mentioned here
369. ort 1 LDO CAN 2 0B Drivers X SP GND RS c Vv SFR Crossbar Control Bus System Clock Setup XTAL1 XTAL2 On F582 F586 devices Port 2 i Drivers Internal Oscillator External Oscillator Analog Peripherals Y Y Clock Multiplier Voltage Port 3 Reference Drivers VDD I lt VREF lt 2 P3 0 Temp Sensor lt GND lt Comparator 0 VDDA Comparator 1 d GNDA IX lt 24 lt 7 Comparator 2 Figure 1 3 C8051F582 3 6 7 Block Diagram 21 Rev 1 3 SILICON LABS 8051 58 59 2 Ordering Information The following features are common to all devices in this family 50 MHz system clock and 50 MIPS throughput peak 8448 bytes of RAM 256 internal bytes and 8192 XRAM bytes 5 2 Enhanced SPI Two UARTs Six Timers 12 Programmable Counter Array channels 12 bit 200 ksps ADC Internal 24 MHz oscillator Internal Voltage Regulator Internal Voltage Reference and Temperature Sensor Three Analog Comparators Table 2 1 shows the feature that differentiate the devices in this family Rev 1 3 22 SILICON LABS 8051 58 59 Table 2 1 Product Selection Guide Ordering Part Number C8051F580 IQ Flash Memory kB Digital Port I Os Ordering Part Number C8051F585 IQ Flash Memory kB Digital Port I Os 8051 580 C8051F581 IQ 2 0 8051 585 8051 586 1 S Ex
370. ort pin 1 T4E routed to Port pin 3 PCA1 External Counter Input Enable 0 ECI1 unavailable at Port pin 1 routed to Port pin 2 0 PCA1ME 2 0 PCA1 Module I O Enable Bits 000 All PCA1 I O unavailable at Port pins 001 CEX6 routed to Port pin 010 CEX6 CEX7 routed to Port pins 011 CEX6 CEX7 CEX8 routed to Port pins 100 CEX6 CEX7 CEX8 CEX9 routed to Port pins 101 CEX6 CEX7 CEX8 CEX9 CEX10 routed to Port pins 110 CEX6 CEX7 CEX8 CEX9 CEX10 CEX11 routed to Port pins 111 RESERVED 199 Rev 1 3 SILICON LABS 8051 58 59 20 5 Port match functionality allows system events to be triggered by a logic value change on PO P1 P2 or P3 A software controlled value stored in the registers specifies the expected or normal logic values of PO P1 P2 and P3 A Port mismatch event occurs if the logic levels of the Port s input pins no longer match the software controlled value This allows Software to be notified if a certain change or pattern occurs on PO P1 P2 or P3 input pins regardless of the XBRn settings The PnMASK registers can be used to individually select which of the port pins should be compared against the PnMATCH registers A Port mismatch event is generated if Pn amp PnMASK does not equal PnMATCH amp PnMASK where is 0 1 2 or 3 A Port mismatch event may be used to generate an interrupt or wak
371. ossbar to skip 0 1 set to 1 Bit1 in register POSKIP See Section 20 Port Input Output on page 188 for details on Port I O configuration 6 1 2 Tracking Modes Each ADCO conversion must be preceded by a minimum tracking time for the converted result to be accu rate as shown in Figure 6 1 ADCO has three tracking modes Pre Tracking Post Tracking and Dual Tracking Pre Tracking Mode provides the minimum delay between the convert start signal and end of con version by tracking continuously before the convert start signal This mode requires software management in order to meet minimum tracking requirements In Post Tracking Mode a programmable tracking time starts after the convert start signal and is managed by hardware Dual Tracking Mode maximizes tracking time by tracking before and after the convert start signal Figure 6 3 shows examples of the three tracking modes Pre Tracking Mode is selected when ADOTM is set to 10b Conversions are started immediately following the convert start signal ADCO is tracking continuously when not performing a conversion Software must allow at least the minimum tracking time between each end of conversion and the next convert start signal The minimum tracking time must also be met prior to the first convert start signal after ADCO is enabled 55 Rev 1 3 SILICON LABS 8051 58 59 Post Tracking Mode is selected when ADOTM is set to 01b A programmable tracking time based on ADOTK
372. ot be read See Gain Register Definition 6 1 Gain Register Definition 6 2 and Gain Register Definition 6 3 for more information The gain is programmed using the following steps Set the GAINEN bit ADCOCF 0 Load the ADCOH with the ADCOGNH ADCOGNL or ADCOGNA address Load ADCOL with the desired value for the selected gain register Reset the GAINEN bit ADCOCF 0 gt Notes 1 An ADC conversion should not be performed while the GAINEN bit is set 2 Even with gain enabled the maximum input voltage must be less than and the maximum voltage of the signal after gain must be less than or equal to VREF In code changing the value to 0 44 gain from the previous example looks like Il in ADCOCF 0x01 GAINEN 1 ADCOH 0x04 Load the ADCOGNH address ADCOL 0x6C Load the upper byte of Ox6CA to ADCOGNH ADCOH 0x07 Load the ADCOGNL address ADCOL 0xAO0 Load the lower nibble of OX6CA to ADCOGNL ADCOH 0x08 Load the ADCOGNA address ADCOL 0x01 Setthe GAINADD bit ADCOCF amp 0x01 GAINEN 0 in assembly ORL ADCOCF 01H GAINEN 1 MOV ADCOH 04H Load the ADCOGNH address MOV ADCOL 06CH Load the upper byte of Ox6CA to ADCOGNH MOV ADCOH 07H Load the ADCOGNL address MOV ADCOL 0A0H Load the lower nibble of Ox6CA to ADCOGNL MOV ADCOH 08H Load the ADCOGNA address MOV ADCOL 01H Set the GAINADD bit ANL ADCOCF 0FEH GAINEN 0 Rev 1 3 62 SILI
373. oted in the SFR detailed descriptions The contents of internal data memory are unaffected during a reset any previously stored data is preserved However since the stack pointer SFR is reset the stack is effectively lost even though the data on the stack is not altered The Port I O latches are reset to OxFF all logic ones in open drain mode Weak pullups are enabled during and after the reset For Vpp Monitor and power on resets the RST is driven low until the device exits the reset state Note When VIO rises faster than VDD which can happen when VREGIN and VIO are tied together a delay created between GPIO power VIO and the logic controlling GPIO VDD results in a temporary unknown state at the GPIO pins Cross coupling VIO and VDD with a 4 7 uF capacitor mitigates the root cause of the problem by allowing VIO and VDD to rise at the same rate On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator The Watchdog Timer is enabled with the system clock divided by 12 as its clock source Pro gram execution begins at location 0x0000 VDD Power On Reset VDD Monitor Reset Supply Monitor or 0 RST Comparator 0 gt Enable J wired OR pq m Px x 4 CORSEF Y Missing gt gt Clock Detector one shot PCA EN
374. ow With Timer 3 enabled and configured to Rev 1 3 241 SILICON LABS 8051 58 59 overflow after 25 ms SMBTOE set the Timer 3 interrupt service routine can be used to reset disable and re enable the SMBus in the event of an SCL low timeout 23 3 5 SCL High SMBus Free Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 us the bus is designated as free When the SMBFTE bit in SMBOCF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods as defined by the timer configured for the SMBus clock source If the SMBus is waiting to generate a Master START the START will be generated following this timeout Note that a clock source is required for free timeout detection even in a slave only implementation 23 4 Using the SMBus The SMBus can operate in both Master and Slave modes The interface provides timing and shifting con trol for serial transfers higher level protocol is determined by user software The SMBus interface provides the following application independent features Byte wise serial data transfers Clock signal generation on SCL Master Mode only and SDA data synchronization Timeout bus error recognition as defined by the SMBOCF configuration register START STOP timing detection and generation Bus arbitration Interrupt generation Status information SMBus interrupts are generated for e
375. ower 8 bits of the effective address to be accessed The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A MOV EMIOCN 12h load high byte of address into EMIOCN MOV RO 34h load low byte of address into RO or R1 MOVX a GRO load contents of 0x1234 into accumulator A Rev 1 3 158 SILICON LABS 8051 58 59 18 2 Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps 1 Configure the Output Modes of the associated port pins as either push pull or open drain push pull is most common and skip the associated pins in the crossbar 2 Configure Port latches to park the EMIF pins in a dormant state usually by setting them to logic 1 3 Select Multiplexed mode or Non multiplexed mode 4 Select the memory mode on chip only split mode without bank select split mode with bank select or off chip only 5 Set up timing to interface with off chip memory or peripherals Each of these five steps is explained in detail in the following sections The Port selection Multiplexed mode selection and Mode bits are located in the EMIOCF register shown in SFR Definition 18 3 Port Configuration The External Memory Interface appears on Ports 1 2 3 and 4 when it is used for off chip memory access When the EMIF is used the Crossbar should be configured to skip over the RD control line P1 6 and the WR cont
376. ows When TF2LEN is enabled software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software T2XCLK SYSCLK 12 External Clock 8 mp Cad To SMBus gt Interrupt F2LEN TMReRLL 29080 SYSCLK B rax TCLK TMR2L elem SMBus Figure 27 5 Timer 2 8 Bit Mode Block Diagram TMR2CN yy d 27 2 3 External Oscillator Capture Mode Capture Mode allows the external oscillator to be measured against the system clock Timer 2 can be clocked from the system clock or the system clock divided by 12 depending on the T2ML CKCON 4 and T2XCLK bits When a capture event is generated the contents of Timer 2 TMR2H TMR2L are loaded into the Timer 2 reload registers TMR2RLH TMR2RLL and the TF2H flag is set A capture event is generated by the falling edge of the clock source being measured which is the external oscillator 8 By recording the difference between two successive timer capture values the external oscillator frequency can be determined with respect to the Timer 2 clock The Timer 2 clock should be much faster than the capture clock to achieve an accurate reading Timer 2 should be in 16 bit auto reload mode when using Capture Mode For example if T2ML 1b and
377. p ture compare register When the value in the low byte of the PCAO counter timer PCAOL is equal to the value in PCAOCPLn the output on the CEXn pin will be set When the count value in PCAOL overflows the CEXn output will be reset see Figure 28 8 Also when the counter timer low byte PCAOL overflows from OxFF to 0x00 PCAOCPLn is reloaded automatically with the value stored in the module s capture compare high byte PCAOCPHn without software intervention Setting the ECOMn and PWMn bits in the register and setting the CLSEL bits in register PCAOPWM to 00b enables 8 Bit Pulse Width Modulator mode If the MATn bit is set to 1 the CCFn flag for the module will be set each time an 8 bit comparator match rising edge occurs The COVF flag in PCAOPWM can be used to detect the overflow falling edge which will occur every 256 PCAO clock cycles The duty cycle for 8 Bit PWM Mode is given in Equation 28 2 Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Cap ture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 256 256 Equation 28 2 8 Bit PWM Duty Cycle Using Equation 28 2 the largest duty cycle is 10096 PCAOCPHn 0 and the smallest duty cycle is 0 3996 PCAOCPHn OxFF 0 duty cycle may be generated by clearing the ECOMn bit to 0 Duty Cycle 321 R
378. pen drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and lose the arbitration The winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer if addressed This arbitration scheme is non destructive one device always wins and no data is lost 23 3 3 Clock Low Extension SMBus provides a clock synchronization mechanism similar to 2 which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency 23 3 4 SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line high to correct the error condition To solve this problem the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communi cation no later than 10 ms after detecting the timeout condition When the SMBTOE bit in SMBOCF is set Timer 3 is used to detect SCL low timeouts Timer 3 is forced to reload when SCL is high and allowed to count when SCL is l
379. plete or receive complete 2 SFRBus Write to 7 SBUF T PS Z UART Baud Rate Generator REN TB8 RB8 TI RI H RI TB8 7 SBUF TX Shift mu 1 gt Crossbar s 1 Zero Detector Stop Bit Shift REN Md Tx Control Y x Clock Send Tx IRQ SCON y Serial Port Interrupt Port I O Rx IRQ R Clock Rx Control Load N 1 0 X Sun Shift OxiFF 8 SBUF A Input Shift Register 9 bits N Load SBUF N 4 N Read SBUF SZ 2 SFRBus Figure 25 1 UART1 Block Diagram Rev 1 3 265 SILICON LABS 8051 58 59 25 1 Enhanced Baud Rate Generation The UART1 baud rate is generated by Timer 1 in 8 bit auto reload mode The TX clock is generated by TL1 the RX clock is generated by copy of TL1 shown as RX Timer in Figure 25 2 which is not user accessible Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates The RX Timer runs when Timer 1 is enabled and uses the same reload value TH1 However an RX Timer reload is forced when a START condition is detected on the RX pin This allows a receive to begin any time a START is detected independent of the TX Timer state
380. pts enabled an interrupt is generated each time a transmit is completed TIO is set in SCONO or a data byte has been received RIO is set in SCONO The UARTO interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UARTO interrupt transmit complete or receive complete If additional bytes are available in the Receive FIFO the RIO bit cannot be cleared by software Baud Rate Generator Data Formatting Lf TXO SBRLHO SBRLLO iudi gt TX Holding E gt Register SYSCLK 9 Timer 16 bit di py 9 1 4 12 48 Write to SBUFO SBUFO Control Status Read of SBUF0 gg loc SBCONO UARTO Interrupt Figure 24 1 UARTO Block Diagram 24 1 Baud Rate Generator The UARTO baud rate is generated by a dedicated 16 bit timer which runs from the controller s core clock SYSCLK and has prescaler options of 1 4 12 or 48 The timer and prescaler options combined allow for a wide selection of baud rates over many clock frequencies The baud rate generator is configured using three registers SBCONO SBRLHO and SBRLLO The UARTO Baud Rate Generator Control Register SBCONO SFR Definition 24 4 enables or disables the bau
381. puts and should be skipped by the Digital Crossbar To configure a Port pin for analog input set to 0 the corresponding bit in register PnMDIN To force the Crossbar to skip a Port pin set to 1 the corresponding bit in register PnSKIP See Section 20 Port Input Output on page 188 for more Port configuration details Rev 1 3 72 SILICON LABS 8051 58 59 SFR Definition 6 13 ADCOMX ADCO Channel Select Bit 7 6 4 3 2 1 Name ADCOMX 5 0 Type R R R W Reset 0 0 1 1 1 1 SFR Address 0xBB SFR Page 0x00 Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 0 AMXOP 5 0 AMUXO Positive Input Selection 000000 P0 0 000001 P0 1 000010 P0 2 000011 P0 3 000100 P0 4 000101 P0 5 000110 P0 6 000111 P0 7 001000 P1 0 001001 P1 1 001010 P1 2 001011 P1 3 001100 P1 4 001101 P1 5 001110 P1 6 001111 P1 7 010000 P2 0 010001 P2 1 010010 P2 2 010011 P2 3 010100 P2 4 010101 P2 5 010110 P2 6 010111 P2 7 011000 P3 0 011001 P3 1 Available on 48 pin and 40 pin package devices 011010 P3 2 Available on 48 pin and 40 pin package devices 011011 P3 3 Available on 48 pin and 40 pin package devices 011100 P3 4 Available on 48 pin and 40 pin package devices 011101 P3 5 Available on 48 pin and 40 pin package devices 011110 P3 6 Available on 48 pin and 40 pin package devices 011111 P3 7 Available on 48
382. r Bit 0 No error in transmission has been detected 1 The bit value monitored during transmission is different than the bit value sent 227 Rev 1 3 SILICON LABS 8051 58 59 LIN Register Definition 21 8 LINOSIZE LINO Message Size Register Bit 7 6 5 4 3 2 1 0 Name ENHCHK LINSIZE 3 0 Type R W R R R R W Reset 0 0 0 0 0 0 0 0 Indirect Address 0x0B Bit Name Function 7 ENHCHK Checksum Selection Bit 0 Use the classic specification 1 3 compliant checksum Checksum covers the data bytes 1 Use the enhanced specification 2 0 compliant checksum Checksum covers data bytes and protected identifier 6 4 Unused Read 000b Write Don t Care 3 0 LINSIZE 3 0 Data Field Size 0000 0 data bytes 0001 1 data byte 0010 2 data bytes 0011 3 data bytes 0100 4 data bytes 0101 5 data bytes 0110 6 data bytes 0111 7 data bytes 1000 8 data bytes 1001 1110 RESERVED 1111 Use the ID 1 0 bits LINOID 5 4 to determine the data length SILICON LABS Rev 1 3 228 8051 58 59 LIN Register Definition 21 9 LINODIV LINO Divider Register Bit 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 Indirect Address 0 0 Bit Name Function 7 0 DIVLSB LIN Baud Rate Divider Least Significant Bits The 8 least significant bits for the baud rate divider The
383. r2 Rising Edge has occurred since this flag was last cleared 1 Comparator2 Rising Edge has occurred CP2FIF Comparator2 Falling Edge Flag Must be cleared by software 0 No Comparator2 Falling Edge has occurred since this flag was last cleared 1 Comparator2 Falling Edge has occurred 3 2 CP2HYPT 1 0 Comparator2 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV CP2HYN 1 0 Comparator2 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV SILICON LABS Rev 1 3 83 8051 58 59 SFR Definition 9 6 CPT2MD Comparator2 Mode Selection Bit 7 6 5 4 3 2 1 0 Name CP2RIE CP2FIE CP2MD 1 0 Type R R RW RW R R R W Reset 0 0 0 0 0 0 1 0 SFR Address 0x9B SFR Page 0x10 Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 CP2RIE Comparator2 Rising Edge Interrupt Enable 0 Comparator2 Rising edge interrupt disabled 1 Comparator2 Rising edge interrupt enabled 4 CP2FIE Comparator2 Falling Edge Interrupt Enable 0 Comparator2 Falling edge interrupt disabled 1 Comparator2 Falling edge interrupt enabled 3 2 Unused Read 00b Write don t care 1 0 CP2MD 1 0 Comparator2
384. ram Store Erase Enable bit PSEE in register PSCTL bits protect the Flash memory from accidental modification by software PSWE must be explicitly set to 1 before software can modify the Flash memory both PSWE and PSEE must be set to 1 before soft ware can erase Flash memory Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access reads writes or erases by unprotected code or the C2 interface The Flash security mechanism allows the user to lock n 512 byte Flash pages starting at page 0 addresses 0x0000 to 0x01FF where n is the ones complement number represented by the Security Lock Byte Note that the page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked all bits of the Lock Byte are 1 and locked when any other Flash pages are locked any bit of the Lock Byte is 0 See example in Figure 15 1 Locked when any other FLASH Lock Byte Page pages are locked Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Locked Flash Pages Security Lock Byte 11111101b 1s Complement 00000010b Flash pages locked 3 First two Flash pages Lock Byte Page Figure 15 1 Flash Program Memory Map 141 Rev 1 3 SILICON LABS 8051 58 59
385. re signifies the value of the CAN RX pin 4 Write enabled by Test SILICON LABS Rev 1 3 237 8051 58 59 SFR Definition 22 1 CANOCFG CAN Clock Configuration Bit 7 6 5 4 3 2 1 0 Name Unused Unused Unused Unused Unused Unused SYSDIV 1 0 Type R R R R R R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x92 SFR Page 0x0C Bit Name Function 7 2 Unused Read 000000b Write Don t Care 1 0 SYSDIV 1 0 CAN System Clock Divider Bits The CAN controller clock is derived from the CIP 51 system clock The CAN control ler clock must be less than or equal to 25 MHz 00 CAN controller clock System Clock 1 01 CAN controller clock System Clock 2 10 CAN controller clock System Clock 4 11 CAN controller clock System Clock 8 238 Rev 1 3 SILICON LABS 8051 58 59 23 SMBus The SMBus interface is a two wire bi directional serial bus The SMBus is compliant with the System Management Bus Specification version 1 1 and compatible with the 12 serial bus Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data Data can be transferred at up to 1 20th of the system clock as a master or slave this can be faster than allowed by the SMBus specification depending on the system clock used A method of extending
386. re performed The Watchdog Timer is enabled on reset Writes to some PCAO registers are restricted while the Watchdog Timer is enabled The WDT will generate a reset shortly after code begins execution To avoid this reset the WDT should be explicitly disabled and option ally re configured and re enabled if it is used in the system 28 4 1 Watchdog Timer Operation While the WDT is enabled PCAO counter is forced on Writes to PCAOL and PCAOH are not allowed PCAO clock source bits 52 50 are frozen PCAO Idle control bit CIDL is frozen PCAO Module 5 is forced into software timer mode Writes to the Module 5 mode register 5 are disabled While the WDT is enabled writes to the CR bit will not change the PCAO counter state the counter will run until the WDT is disabled The PCAO counter run control bit CR will read zero if the WDT is enabled but user software has not enabled the PCAO counter If a match occurs between PCAOCPH5 and PCAOH while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updated with a write of any value to PCAOCPH5 Upon PCAOCPHS write PCAOH plus the offset held in is loaded into PCAOCPH5 See Figure 28 11 Rev 1 3 324 SILICON LABS 8051 58 59 PCAOMD 5 PCAOL Overflow 5 Write to 2 Figure 28 11 PCAO Module 5 with Watchdog Timer Enabled 8 bit Adder
387. re stored in SBUF1 the ninth bit is stored in RB81 and the flag is set to 1 If the above conditions are not met SBUF1 and RB81 will not be loaded and the flag will not be set to 1 A UART1 interrupt will occur if enabled when either or is set to 1 MARK START BIT 00 D1 D2 D3 D4 D5 D6 D7 D8 STOP SPACE BIT err Tues SAMPLING Figure 25 5 9 Bit UART Timing Diagram 25 3 Multiprocessor Communications 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic 0 Setting the MCE1 bit SCON1 5 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the ninth bit is logic 1 RB81 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned 8 bit address If the addresses match the slave will clear its MCE1 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed le
388. reads of the Flash memory On the C8051F580 1 2 3 8 9 devices the upper 1024 bytes of the memory in Bank OxFCOO to OxFFFF are reserved and are not available for user program or data storage Figure 12 2 show the Flash as a consecutive block of address space using a 17 bit address to illustrate the location of the lock byte lock byte page and reserved space C8051 F580 1 2 3 8 9 0x1 FFFF Reserved Area 0 1 00 Lock Byte Page Flash Memory Space 128 kB Flash Device Figure 12 2 Flash Program Memory Map Internal Address IFBANK 0 IFBANK 1 IFBANK 2 IFBANK 3 OxFFFF EB 0x8000 7 0 0000 Figure 12 3 Address Memory Map for Instruction Fetches Ox1FBFE C8051F584 5 6 7 F590 1 E N 0x1FA00 Ox17FFE 55 Lock Byte Page og 0x17E00 52 2 ES I LO Flash Memory Space o 96 kB Flash Device ul 0x00000 103 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 12 1 PSBANK Program Space Bank Select Bit 7 6 5 4 3 2 1 0 Name COBANK 1 0 IFBANK 1 0 Type RW RW RW RW R W R W R W R W Reset 0 0 0 1 0 0 0 1 SFR Address 0 5 SFR Page All Pages Bit Name Function 7 6 Reserved Read 00b Must Write 00b 5 4 COBANK 1 0 Constant Operations Bank Select These bits select which Flash bank is targeted during constant operations MOVC and Flash MOVX involving address 0x8000 to OxFFFF 00 Constant Op
389. resis 10 mV 11 Positive Hysteresis 20 mV CPOHYN 0 Comparator0 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV SILICON LABS Rev 1 3 79 8051 58 59 SFR Definition 9 2 CPTOMD Comparator0 Mode Selection Bit 7 6 5 4 3 2 1 0 Name CPORIE CPOFIE CPOMD 1 0 Type R R RW RW R R R W Reset 0 0 0 0 0 0 1 0 SFR Address 0x9B SFR Page 0x00 Bit Name Function 7 6 Unused Read 00b Write Don t Care 5 CPORIE 0 Rising Edge Interrupt Enable 0 Rising edge interrupt disabled 1 Rising edge interrupt enabled 4 CPOFIE Comparator0 Falling Edge Interrupt Enable 0 Falling edge interrupt disabled 1 Falling edge interrupt enabled 3 2 Unused Read 00b Write don t care 1 0 CPOMD 1 0 ComparatorO Mode Select These bits affect the response time and power consumption for ComparatorO 00 Mode 0 Fastest Response Time Highest Power Consumption 01 Mode 1 10 Mode 2 11 Mode 3 Slowest Response Time Lowest Power Consumption 80 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 9 3 1 Comparator1 Control Bit 6 5 4 3 2 1 0
390. rflows from OxFFFF to 0x0000 the Counter Overflow Flag CF1 in PCA1MD is set to logic 1 and an interrupt request is generated if CF1 interrupts are enabled Setting the ECF1 bit in PCA1MD to logic 1 enables the CF1 flag to generate an interrupt request The CF1 bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Clearing the CIDL1 bit in the PCA1MD register allows the PCA1 to continue normal operation while the CPU is in Idle mode Table 29 1 PCA1 Timebase Input Options CPS12 CPS11 CPS10 Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions on ECI1 max rate system clock divided by 4 System clock External oscillator source divided by 8 Timer 4 Overflow 1 1 1 Timer 5 Overflow Note External oscillator source divided by 8 is synchronized with the system clock IDLE 4 a O O PCA1CN c c c E c c c c cicicic D S S S F 1H F FIF F F F 1 1 7 6 8 1 2 110 1 0 PCA1L Snapshot Register SYSCLK 12 000 SYSCLK 4 001 Timer 0 Overflow 010 vo 011 SYSCLK 100 External Clock 8 101 To PCA1 Modules SYSCLK 110 External Clock 8
391. rol line P1 7 using the P1SKIP register When the EMIF is used in multiplexed mode the Cross bar should also skip over the ALE control line P1 5 For more information about configuring the Crossbar see Section 20 6 Special Function Registers for Accessing and Configuring Port I O on page 204 The EMIF pinout is shown in Table 18 1 on page 160 The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches or to the Crossbar settings for those pins See Section 20 Port Input Out put on page 188 for more information about the Crossbar and Port operation and configuration The Port latches should be explicitly configured to park the External Memory Interface pins in a dormant state most commonly by setting them to a logic 1 During the execution of the MOVX instruction the External Memory Interface will explicitly disable the driv ers on all Port pins that are acting as Inputs Data 7 0 during a READ operation for example The Output mode of the Port pins whether the pin is configured as Open Drain or Push Pull is unaffected by the External Memory Interface operation and remains controlled by the PnMDOUT registers In most cases the output modes of all EMIF pins should be configured for push pull mode C8051F580 1 4 5 devices support both the
392. rupt Flag This bit must be cleared by software 0 ADCO Window Comparison Data match has not occurred since this flag was last cleared 1 ADCO Window Comparison Data match has occurred 2 ADOLJST ADCO Left Justify Select Bit 0 Data in ADCOH ADCOL registers is right justified 1 Data in ADCOH ADCOL registers is left justified This option should not be used with a repeat count greater than 1 when ADORPTT 1 0 is 01b 10b or 11b 1 0 ADOCM 1 0 ADCO Start of Conversion Mode Select 00 ADCO start of conversion source is write of 1 to ADOBUSY 01 ADCO start of conversion source is overflow of Timer 1 10 ADCO start of conversion source is rising edge of external CNVSTR 11 ADCO start of conversion source is overflow of Timer 2 67 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 6 8 ADCOTK ADCO Tracking Mode Select Bit 7 6 5 3 2 1 0 Name ADOPWR 3 0 ADOTM 1 0 ADOTK 1 0 Type R W R W R W Reset 1 1 1 1 1 1 1 SFR Address SFR Page 0x00 Bit Name Function 7 4 ADOPWR 3 0 ADCO Burst Power Up Time For BURSTEN 0 ADCO Power state controlled by ADOEN For BURSTEN 1 ADOEN 1 ADCO remains enabled and does not enter the very low power state For BURSTEN 1 ADOEN 0 ADCO enters the very low power state and is enabled after each convert start signal The Power Up time is programmed accord i
393. rupt occurs Recall the PCA interrupt is configured as a high priority interrupt while the CANO interrupt is configured as a ow priority interrupt Thus the CIP 51 will now vector to the high priority PCA ISR Upon doing so the CIP 51 will automatically place the SFR page needed to access the PCA s special function registers into the SFRPAGE register SFR Page 0x00 The value that was in the SFRPAGE register before the PCA interrupt SFR Page 0 0 for CANO is pushed down the stack into SFRNEXT Likewise the value that was in the SFRNEXT register before the PCA interrupt in this case SFR Page 0x00 for SPIODAT is pushed down to the SFRLAST register the bottom of the stack Note that a value stored in SFRLAST via a previous software write to the SFRLAST register will be overwritten See Figure 13 4 109 Rev 1 3 SILICON LABS 8051 58 59 SFR Page 0 0 Automatically pushed on stack in SFRPAGE on PCA interrupt SFRPAGE SFRPAGE pushed to SFRNEXT SFRNEXT SFRNEXT pushed to SFRLAST SFRLAST Figure 13 4 SFR Page Stack Upon PCA Interrupt Occurring During a CANO ISR On exit from the PCA interrupt service routine the CIP 51 will return to the CANO ISR On execution of the RETI instruction SFR Page 0x00 used to access the PCA registers will be automatically popped off of the SFR Page Stack and the contents of the SFRNEXT register will be moved to the SFRPAGE register Soft ware in the CANO ISR can conti
394. s an entire page of Flash program memory to be erased If this bit is logic 1 and Flash writes are enabled PSWE is logic 1 a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter 0 Flash program memory erasure disabled 1 Flash program memory erasure enabled 0 PSWE Program Store Write Enable Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction The Flash location should be erased before writing data 0 Writes to Flash program memory disabled 1 Writes to Flash program memory enabled the MOVX write instruction targets Flash memory 145 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 15 2 FLKEY Flash Lock and Key Bit 7 6 5 4 3 2 1 0 Name FLKEY 7 0 Reset 0 0 0 0 0 0 0 0 SFR Address 0xB7 SFR Page All Pages Bit Name Function 7 0 FLKEY 7 0 Flash Lock and Key Register SILICON LABS Write This register provides a lock and key function for Flash erasures and writes Flash writes and erases are enabled by writing 0xA5 followed by OxF1 to the FLKEY regis ter Flash writes and erases are automatically disabled after the next write or erase is complete If any writes to FLKEY are performed incorrectly or if a Flash write or erase operation
395. s program execution at address 0x0000 Note When entering Suspend mode firmware must set the ZTCEN bit in REFOCN SFR Definition 8 1 150 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 16 1 Power Control Bit 7 6 5 4 3 2 1 0 Name GF 5 0 STOP IDLE Reset 0 0 0 0 0 0 0 0 SFR Address 0x87 SFR Page All Pages Bit Name Function 7 2 GF 5 0 General Purpose Flags 5 0 These are general purpose flags for use under software control 1 STOP Stop Mode Select Setting this bit will place the CIP 51 in Stop mode This bit will always be read as 0 1 CPU goes into Stop mode internal oscillator stopped 0 IDLE IDLE Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 1 CPU goes into Idle mode Shuts off clock to CPU but clock to Timers Interrupts Serial Ports and Analog Peripherals are still active SILICON LABS Rev 1 3 151 8051 58 59 17 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur CIP 51 halts program execution Special Function Registers SFRs are initialized to their defined reset values External Port pins are forced to a known state m Interrupts and timers are disabled All SFRs are reset to the predefined values n
396. s programmed at a cold temperature below 0 may exhibit weakly programmed flash memory bits If programmed at 0 or higher there is no problem reading Flash across the entire temperature range of 40 to 125 This temperature restriction does not apply to A Auto motive Grade devices 15 1 1 Reprogramming the VDD Monitor High Threshold The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event The output of the un calibrated internal regulator could be below the high threshold setting of the VDD Monitor If this is the case and the MCU receives a non power on reset POR when the VDD Monitor is set to the high threshold setting the MCU will remain in reset until a POR occurs i e Vpp Monitor will keep the device in reset A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un calibrated output of the internal regulator The device will then exit reset and resume normal operation It is for this reason Silicon Labs strongly recommends that the VDD Monitor is always left in the low threshold setting i e default value upon POR When programming the Flash in system the VDD Monitor must be set to the high threshold setting To prevent this issue from happening and ensure the highest system reliability firmware can change the VDD Monitor high threshold and the system can use an external supply monitor that meets the Flash VDD requirement
397. s the typical SCL generation described by Equation 23 2 Notice that Tijg is typically twice as large as ow The actual SCL output may vary due to other devices on the bus SCL may be extended low by slower slave devices or driven low by contending master devices The bit rate when operating as a master will never exceed the limits defined by equation Equation 23 1 Timer Source Overflows SCL T SCL High Timeout High Figure 23 4 Typical SMBus SCL Generation Rev 1 3 243 SILICON LABS 8051 58 59 Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns respectively Table 23 2 shows the min imum setup and hold times for the two EXTHOLD settings Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz Table 23 2 Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time 0 4 system clocks 3 sy
398. scillator x 4 11 External Oscillator External Oscillator x 4 Notes The maximum system clock is 50 MHz and so the Clock Multiplier output should be scaled accordingly If Internal Oscillator x 2 or External Oscillator x 2 is selected using the MULSEL bits MULDIV 2 0 is ignored 182 Rev 1 3 SILICON LABS 8051 58 59 19 4 External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal ceramic resonator capacitor or RC network A CMOS clock may also provide a clock input For a crystal or ceramic resonator configuration the crys tal resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19 1 A 10 MQ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal resonator configura tion In RC capacitor or CMOS clock configuration the clock source should be wired to the XTAL2 pin as shown in Option 2 3 or 4 of Figure 19 1 The type of external oscillator must be selected in the OSCXCN register and the frequency control bits must be selected appropriately see SFR Definition 19 6 Important Note on External Oscillator Usage Port pins must be configured when using the external oscillator circuit When the external oscillator drive circuit is enabled in crystal resonator mode Port pins P0 2 and are used as XTAL1 and XTAL2 respectively When the external oscillator drive circuit is enabled in
399. sed Flash memory or XRAM 98 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 11 3 SP Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incre mented before every PUSH operation The SP register defaults to 0x07 after reset Bit 7 6 5 4 3 2 1 0 Name SP 7 0 Type R W Reset 0 0 0 0 0 1 1 1 SFR Address 0x81 SFR Page All Pages Bit Name Function 7 0 SP 7 0 Stack Pointer SFR Definition 11 4 ACC Accumulator This register is the accumulator for arithmetic operations Bit 7 6 5 4 3 2 1 0 Name ACC 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xE0 SFR Page All Pages Bit Addressable Bit Name Function 7 0 ACC 7 0 Accumulator SFR Definition 11 5 B B Register This register serves as a second accumulator for certain arithmetic operations Bit 7 6 5 4 3 2 1 0 Name B 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address OxF0 SFR Page All Pages Bit Addressable Bit Name Function 7 0 B 7 0 B Register SILICON LABS Rev 1 3 99 8051 58 59 SFR Definition 11 6 PSW Program Status Word Bit 7 6 5 4 3 2 1 0 Name CY AC FO RS 1 0 OV 1 PARITY Type R
400. set to 1 When enabled the interface constantly monitors the SDA and SCL pins 6 INH SMBus Slave Inhibit When this bit is set to logic 1 the SMBus does not generate an interrupt when slave events occur This effectively removes the SMBus slave from the bus Master Mode interrupts are not affected 5 BUSY SMBus Busy Indicator This bit is set to logic 1 by hardware when a transfer is in progress It is cleared to logic 0 when a STOP or free timeout is sensed 4 EXTHOLD SMBus Setup and Hold Time Extension Enable This bit controls the SDA setup and hold times according to Table 23 2 0 SDA Extended Setup and Hold Times disabled 1 SDA Extended Setup and Hold Times enabled 3 SMBTOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication 2 SMBFTE SMBus Free Timeout Detection Enable When this bit is set to logic 1 the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods 1 0 SMBCS 1 0 SMBus Clock Source Selection These two bits select the SMBus clock source which is used to generate the SMBus bit rate
401. sfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMBODAT is written while an active Master Receiver Figure 23 6 shows a typical master read sequence Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur before the ACK cycle in this mode Received by SMBus S START A ACK N NACK Transmitted by R READ SMBus Interface SLA Slave Address Figure 23 6 Typical Master Read Sequence Rev 1 3 251 SILICON LABS 8051 58 59 23 5 3 Write Sequence Slave During a write sequence an SMBus master writes data to a slave device The slave in this transfer will be a receiver during the address byte and a receiver during all data bytes When slave events are enabled INH 0 the interface enters Slave Receiver Mode when a START followed by a slave address and direc tion bit WRITE in this case is received Upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK If the received slave address is ignored slave interrupts will be inhibited until the next START is detected If the received slave address is acknowledged zero or more data bytes are received Software must write the ACK bit a
402. software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after the completion of the next instruction 14 1 MCU Interrupt Sources and Vectors The C8051F58x F59x MCUs support 23 interrupt sources Software can simulate an interrupt by setting any interrupt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be gener ated and the CPU will vector to the ISR address associated with the interrupt pending flag MCU interrupt Sources associated vector addresses priority order and control bits are summarized in Table 14 1 Refer to the datasheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s Rev 1 3 126 SILICON LABS 8051 58 59 14 1 1 Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels low or high A low prior ity interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in an SFR IE EIP1 or EIP2 used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously the int
403. ss 0xD9 SFR Page 0x10 Bit Name Function 7 CIDL1 1 Counter Timer Idle Control Specifies PCA1 behavior when CPU is in Idle Mode 0 PCA1 continues to function normally while the system controller is in Idle Mode 1 PCA1 operation is suspended while the system controller is in Idle Mode 6 4 Unused 000b Write Don t care 3 1 CPS1 2 0 PCA1 Counter Timer Pulse Select These bits select the timebase source for the PCA1 counter 000 System clock divided by 12 001 System clock divided by 4 010 Timer 0 overflow 011 High to low transitions on ECI max rate system clock divided by 4 100 System clock 101 External clock divided by 8 synchronized with the system clock 110 Timer 4 overflow 111 Timer 5 overflow 0 EC1F 1 Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA1 Counter Timer Overflow CF1 interrupt 0 Disable the CF1 interrupt 1 Enable a PCA1 Counter Timer Overflow interrupt request when CF1 PCA1CN 7 is set 346 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 29 3 PCA1PWM PCA1 PWM Configuration Bit 7 2 1 0 Name ARSEL1 ECOV1 COVF1 CLSEL1 1 0 Type R W R W R W R W Reset 0 0 0 SFR Address OxDA SFR Page OxOF Bit Name Function 7 ARSEL1 Auto Reload Register Select This bit selects whether to read and write the normal PCA1 capture compare re
404. stem clocks or 1 system clock s w delay 1 11 system clocks 12 system clocks Note Setup Time for ACK bit transmissions and the MSB of all data transfers When using software acknowledgement the s w delay occurs between the time SMBODAT or ACK is written and when SI is cleared Note that if SI is cleared in the same write that defines the outgoing ACK value s w delay is zero With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts see Section 23 3 4 SCL Low Timeout on page 241 The SMBus interface will force Timer 3 to reload while SCL is high and allow Timer 3 to count when SCL is low The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re enabling the SMBus SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods see Figure 23 4 244 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 23 1 SMBOCF SMBus Clock Configuration Bit 7 6 5 4 3 2 1 0 Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS 1 0 Type R W R W R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xC1 SFR Page 0x00 Bit Name Function 7 ENSMB SMBus Enable This bit enables the SMBus interface when
405. struction Once cleared to logic 0 a Flash bit must be erased to set it back to logic 1 Flash bytes would typically be erased set to OxFF before being reprogrammed The write and erase operations are automatically timed by hardware for proper execution data polling to determine the end of the write erase operation is not required Code execution is stalled during a Flash write erase oper ation Refer to Table 5 5 for complete Flash memory electrical characteristics 15 1 Programming The Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor This is the only means for programming a non initial ized device For details on the C2 commands to program Flash memory see Section 30 C2 Interface on page 351 The on chip Vpp Monitor must be enabled and set to the high threshold when executing code that writes and or erases Flash memory from software Systems that reprogram the Flash memory from software must use an external supply monitor and reprogram the high monitor threshold to ensure no issues with the uncalibrated internal regulator See Section 15 4 for more details Before performing any Flash write or erase procedure set the FLEWT bit in Flash Scale register FLSCL to 1 Also note that 8 bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than OxOOFF For l Industrial Grade parts part
406. sum Type Select between classic or enhanced checksum both of which are implemented in hard ware 21 2 1 Mode Definition Following the LIN specification the controller implements in hardware both the Slave and Master operating modes The mode is configured using the MODE bit LINOCF 6 21 2 2 Baud Rate Options Manual or Autobaud The LIN controller can be selected to have its baud rate calculated manually or automatically A master node must always have its baud rate set manually but slave nodes can choose between a manual or auto matic setup The configuration is selected using the ABAUD bit LINOCF 5 Both the manual and automatic baud rate configurations require additional setup The following sections explain the different options available and their relation with the baud rate along with the steps necessary to achieve the required baud rate 21 2 3 Baud Rate Calculations Manual Mode The baud rate used by the LIN controller is a function of the System Clock SYSCLK and the LIN timing registers according to the following equation SYSCLK baud rate prescalerz1 2 x divider x multiplier 1 The prescaler divider and multiplier factors are part of the LINODIV and LINOMUL registers and can assume values in the following range Table 21 1 Baud Rate Calculation Variable Ranges Factor Range prescaler 0 3 multiplier 0 31 divider 200 511 Important Note The minimum syst
407. t that time to ACK or NACK the received byte The interface exits Slave Receiver Mode after receiving a STOP Note that the interface will switch to Slave Transmitter Mode if SMBODAT is written while an active Slave Receiver Figure 23 7 shows a typical slave write sequence Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur before the ACK in this mode Received by SMBus S SIAHT Interface P STOP A ACK W WHITE Transmitted by SLA Slave Address SMBs Interface Figure 23 7 Typical Slave Write Sequence 252 Rev 1 3 SILICON LABS 8051 58 59 23 5 4 Read Sequence Slave During a read sequence an SMBus master reads data from a slave device The slave in this transfer will be a receiver during the address byte and a transmitter during all data bytes When slave events are enabled INH 0 the interface enters Slave Receiver Mode to receive the slave address when a START followed by a slave address and direction bit READ in this case is received Upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK The interrupt will occur after the ACK cycle If the received slave address is ignored slave interrupts will be inhibited until the next START is detected If the received slave ad
408. t to 01b for the system clock to run from the external oscillator however the exter nal oscillator may still clock certain peripherals timers PCA when the internal oscillator is selected as the system clock The system clock may be switched on the fly between the internal oscillator external oscilla tor and Clock Multiplier so long as the selected clock source is enabled and has settled The internal oscillator requires little start up time and may be selected as the system clock immediately fol lowing the register write which enables the oscillator The external RC and C modes also typically require no startup time External crystals and ceramic resonators however typically require a start up time before they are settled and ready for use The Crystal Valid Flag XTLVLD in register OSCXCN is set to 1 by hardware when the external crystal or ceramic resonator is settled In crystal mode to avoid reading a false XTLVLD soft ware should delay at least 1 ms between enabling the external oscillator and checking XTLVLD Rev 1 3 176 SILICON LABS 8051 58 59 SFR Definition 19 1 CLKSEL Clock Select Bit 7 6 5 4 3 2 1 0 CLKSL 1 0 Type R R R R R R R W Reset 0 0 0 0 0 0 0 0 SFR Address 0x8F SFR Page OxOF Bit Name Function 7 2 Unused Read 000000b Write Don t Care 1 0 CLKSL 1 0 System Clock Source Select Bits 00 SYSCLK derived from the Internal Oscil
409. ta Memory Interface On Chip 156 18 1 Accessing 156 18 1 1 16 Bit MOVX Example aerario totae aru nte Bee etat 156 18 12 B Bit MOV S P 156 18 2 Configuring the External Memory 157 18 3 Port Configuration rii sens decida 157 18 4 Multiplexed Non multiplexed Selection 162 18 4 1 Multiplexed 162 4 Rev 1 3 SILICON LABS 8051 58 59 18 4 2 Non multiplexed Configuration 163 18 5 Memory Mode 164 18 5 1 WS Ral XRAM Only uu u ta Dim rex a Rex Cep ex dd meis 164 18 5 2 Split Mode without Bank 164 18 5 3 Split Mode with Bank Select 165 18 5 4 External Only 165 165 18 6 1 Non Multiplexed 000 0400 167 18 6 1 1 16 bit MOVX EMIOCF 4 2 101 110 or 111 167 18 6 1 2 8 bit MOVX without Bank Select EMIOCF 4 2 101 or 111 168 18 6 1 3 8
410. tage Px x GND VREF x 4095 4096 OxFFFO ADOWINT not affected 0x2010 VREF x 512 4096 0x2000 ADCOLTH ADCOLTL ADOWINT 1 0x1000 ADCOGTH ADCOGTL OxOFFO ADOWINT not affected 0 0x0000 ADCOH ADCOL Input Voltage Px x GND VREF x 4095 4096 ADOWINT 1 VREF x 512 4096 0x2000 T ADCOGTH ADCOGTL 0x1FF0 0x1010 AD0WINT not affected 0x1000 ADCOLTH ADCOLTL ADOWINT 1 Figure 6 7 ADC Window Compare Example Left Justified Data 71 Rev 1 3 SILICON LABS 8051 58 59 6 5 ADCO Analog Multiplexer ADCO includes an analog multiplexer to enable multiple analog input sources Any of the following may be selected as an input 0 7 the on chip temperature sensor the core power supply Vpp or ground GND ADCO is single ended and all signals measured are with respect to GND The ADCO input channels are selected using the ADCOMX register as described in SFR Definition 6 13 ADCOMX CO QN O gt xXx x X gt gt gt gt S O O olololo lojo 2 2 12 2 2 5 lt lt lt lt lt lt l J P3 1 P3 7 available as inputs on 48 pin and 40 pin packages Figure 6 8 ADCO Multiplexer Block Diagram Important Note About ADCO Input Configuration Port pins selected as ADCO inputs should be config ured as analog in
411. tage Regulator Input Output Regulator Disabled t o 90 Figure 11 1 CIP 51 Block Diagram eeesseeeseesseeeeeeeeeeeee nennen 92 Figure 12 1 C8051F58x F59x Memory 102 Figure 12 2 Flash Program Memory 103 Figure 12 3 Address Memory Map for Instruction Fetches 103 Figure 13 1 SFR Page Stack pan 107 Figure 13 2 SFR Page Stack While Using SFR Page 0x0 To Access SPIODAT 108 Figure 13 3 SFR Page Stack After CANO Interrupt Occurs 109 Rev 1 3 9 SILICON LABS C8051F58x F59x Figure 13 4 SFR Page Stack Upon PCA Interrupt Occurring During a CANO ISR 110 Figure 13 5 SFR Page Stack Upon Return From PCA Interrupt 111 Figure 13 6 SFR Page Stack Upon Return From CANO Interrupt 112 Figure 15 1 Flash Program Memory 8 141 Figure 17 1 Reset SourceS RUD M MEE 152 Figure 17 2 Power On and VDD Monitor Reset Timing 153 Figure 19 1 Oscillator Options ccce SQ EDS UD ES 176 Figure 19 2 Example Clock Multiplier Output 181 Figure 19 3 External 32 768 kHz Quartz Crystal Oscill
412. tant Note about the VREF Pin When using either an external voltage reference or the on chip ref erence circuitry the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar Refer to Section 20 Port Input Output on page 188 for the location of the VREF pin as well as details of how to configure the pin in analog mode and to be skipped by the crossbar Internal Reference Recommended Bypass Capacitors To ADC Internal Oscillators VDD External Voltage Reference To Analog Mux Sai Circuit VREF 4 1 A VREF gt ADC IUDA 1 1 REFBE 1 D NF A 57 1 1 1 1 Figure 8 1 Voltage Reference Functional Block Diagram Rev 1 3 75 SILICON LABS 8051 58 59 SFR Definition 8 1 REFOCN Reference Control Bit 7 6 5 4 3 2 1 0 Name ZTCEN REFLV REFSL TEMPE BIASE REFBE Type R R R R R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xD1 SFR Page 0x00 Bit Name Function 7 6 Unused Read 00b Write don t care 5 ZTCEN Temperature Coefficient Bias Enable Bit This bit must be set to 1b before entering oscillator suspend mode 0 ZeroTC Bias Generator automatically enabled when required 1 ZeroTC Bias Generator forced on 4 REFLV Voltage Reference O
413. target location as described in Section 15 1 3 4 Set the FLEWT bit register FLSCL 5 Set the PSWE bit register PSCTL 6 Clear the PSEE bit register PSCTL 7 Write the first key code to FLKEY OxA5 8 Write the second key code to FLKEY OxF1 9 Using the instruction write a single data byte to the desired location within the 512 byte sector 10 Clear the PSWE bit 139 Rev 1 3 SILICON LABS 8051 58 59 Steps 5 7 must be repeated for each byte to be written After Flash writes are complete PSWE should be cleared so that MOVX instructions do not target program memory 15 1 5 Flash Write Optimization The Flash write procedure includes a block write option to optimize the time to perform consecutive byte writes When block write is enabled by setting the CHBLKW bit CCHOCN 0 writes to two consecutive bytes in Flash require the same amount of time as a single byte write This is performed by caching the first byte that is written to Flash and then committing both bytes to Flash when the second byte is written When block writes are enabled if the second write does not occur the first data byte written is not actually written to Flash Flash bytes with block write enabled are programmed by software with the following sequence 1 Disable interrupts recommended 2 If writing to an address in Banks 1 2 or 3 set the COBANKT 1 0 bits register PSBANK for the appropriate bank Erase the 512 byte
414. ted on a CAN network has 4 segments Sync Seg Prop Seg Phase Seg1 and Phase Seg2 as shown in Figure 18 3 The sum of these segments determines the CAN bit time 1 bit rate In this example the desired bit rate is 1 Mbit sec therefore the desired bit time is 1000 ns Rev 1 3 233 SILICON LABS 8051 58 59 4 CAN Bit Time 4 to 25 tj Sync Seg Prop Seg Phase Segl1 Phase Seg2 1t 1 to 8 t 1 to 8t 1 to 8 t gt 11 F lt Sample Point Figure 22 3 Four segments of a CAN Bit The length of the 4 bit segments must be adjusted so that their sum is as close as possible to the desired bit time Since each segment must be an integer multiple of the time quantum tq the closest achievable bit time is 24 tq 1000 008 ns yielding a bit rate of 0 999992 Mbit sec The Sync_Seg is a constant 1 tq The Prop_Seg must be greater than or equal to the propagation delay of 400 ns and so the choice is 10 tq 416 67 ns The remaining time quanta 13 tq in the bit time are divided between Phase_Seg1 and Phase_Seg2 as shown in Based on this equation Phase Seg1 6 tq and Phase Seg 7 tq Phase Seg Phase Seg 2 Bit Time Synch Seg Prop Seg 1 If Phase Seg Phase Seg 2 is even then Phase Seg2 Phase Segl If the sum is odd Phase 5 02 Phase Segl 1 2 Phase Seg should be at least 2 tq Equation 22 1 Assigning the Phase Segments The Synchronization Jump Width SJW timing
415. tem clock undivided system clock divided by two system clock divided by 12 or an external clock provided at the XTAL1 XTAL2 pins divided by 8 see SFR Definition 27 19 When CTn is set to logic 1 a high to low transition at the Tn input pin increments the counter timer register i e configured as a counter 27 4 1 Configuring Timer 4 and 5 to Count Down Timers 4 and 5 have the ability to count down When the timer s Decrement Enable Bit DCENn in the Timer Configuration Register see SFR Definition 27 19 is set to 1 the timer can then count up or down When DCENn 1 the direction of the timer s count is controlled by the TnEX pin s logic level When TnEX 1 the counter timer will count up when TnEX 0 the counter timer will count down To use this feature must be enabled in the digital crossbar and configured as a digital input Note When DCENn 1 other functions of the TnEX input i e capture and auto reload are not available TnEX will only control the direction of the timer when DCENn 1 27 4 2 Capture Mode In Capture Mode Timers 4 and 5 will operate as a 16 bit counter timer with capture facility When the Timer External Enable bit see SFR Definition 27 18 is set to 1 a high to low transition on the TnEX input pin causes the 16 bit value in the associated timer THn TLn to be loaded into the capture registers TMRn CAPH TMRnCAPL If a capture is triggered in the counter timer the Timer External Flag
416. tentially Assignable Port Pins SFR s used for Assignment External Interrupt 0 1 0 1 7 ITO1CF External Interrupt 1 1 0 1 7 1 Port Match P0 0 P3 7 POMASK POMAT P1MASK P1MAT P2MASK P2MAT P3MASK P3MAT Note P3 1 P3 7 are only available on the 48 pin and 40 pin packages 20 3 Priority Crossbar Decoder The Priority Crossbar Decoder Figure 20 3 assigns a priority to each I O function starting at the top with UARTO When a digital resource is selected the least significant unassigned Port pin is assigned to that resource excluding UARTO which is always assigned to pins P0 4 and P0 5 and excluding CANO which is always assigned to pins P0 6 and 7 If a Port pin is assigned the Crossbar skips that pin when assign ing the next selected resource Additionally the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set The PnSKIP registers allow software to skip Port pins that are to be used for analog input dedicated functions or GPIO Because of the nature of Priority Crossbar Decoder not all peripherals can be located on all port pins Figure 20 3 maps peripherals to the potential port pins on which the peripheral I O can appear Rev 1 3 192 SILICON LABS 8051 58 59 Important Note on Crossbar Configuration If a Port pin is claimed by a peripheral without use of the Crossbar its corresponding PnSKIP bit should be set This applies to P0 0 if
417. ter issues SCK NSS in 4 wire slave mode and the serial input data synchronously with the slave s system clock If the master issues SCK NSS and the serial input data asynchronously the maximum data transfer rate bits sec must be less than 1 10 the system clock frequency In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave i e half duplex operation the SPI slave can receive data at a maximum data transfer rate bits sec of 1 4 the system clock frequency This is provided that the master issues SCK NSS and the serial input data synchronously with the slave s system clock CKI 1 L I L LI LI LI LOI Le CKPOL 0 CKPHA 0 CKPOL 0 CKPHA 1 CK Wd dE LE CKPOL 1 CKPHA 0 CK LILI LI LI LI LI LJ LI CKPOL 1 CKPHA 1 MISO MOSI PX VVVVVV NSS Must Remain High in Multi Master Mode Figure 26 5 Master Mode Data Clock Timing 277 Rev 1 3 SILICON LABS 8051 58 59 SCK eeo oceo LT LT LI LI LI LI LI Le SCK CKPOL 1 CKPHA 0 MOSI MISO NSS 4 Wire Mode SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MOSI MISO NSS 4 Wire Mode 26 6 SPI Special Function Registers SPIO is accessed and controlled through four special function registers in the system controller SPIOCN Control Regist
418. ter the instruction to set PSWE to a 1 but before the Flash write or erase operation instruction Note The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event The output of the un calibrated internal regulator could be below the high threshold setting of the VDD Monitor If this is the case and the MCU receives a non power on reset POR when the VDD Monitor is set to the high threshold setting the MCU will remain in reset until a POR occurs i e VDD Monitor will keep the device in reset A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un calibrated output of the internal regulator The device will then exit reset and resume normal operation It is for this reason Silicon Labs strongly recommends that the VDD Monitor is always left in the low threshold setting i e default value upon POR When programming the Flash in system the VDD Monitor must be set to the high threshold setting To prevent this issue from happening and ensure the highest system reliability firmware can change the Vpp Monitor high threshold and the system must use an external supply monitor For instructions on how to do this see Reprogramming the VDD Monitor High Threshold on page 138 5 Make certain that all writes to the RSTSRC Reset Sources register use direct assignment operators and explicitly DO NOT use the bit wise operators such as AND or OR For exampl
419. ternal Memory Interface 8051 581 C8051F582 IQ t gt o E Li gt ui Y Y Y Y C8051F586 IM C8051F587 IQ C8051F582 IM C8051F583 IQ C8051F587 IM C8051F588 IM C8051F583 IM C8051F584 IQ C8051F589 IM C8051F590 IM C8051F584 IM C8051F591 IM Note The suffix of the part number indicates the device rating and the package All devices are RoHS compliant All of these devices are also available in an automotive version For the automotive version the I in the ordering part number is replaced with A For example the automotive version of the C8051F580 IM is the C8051F580 AM The AM and AQ devices receive full automotive quality production status including AEC Q100 qualifica tion registration with International Material Data System IMDS and Part Production Approval Process PPAP documentation PPAP documentation is available at www silabs com with a registered and NDA approved user account The AM and AQ devices enable high volume automotive OEM applications with their enhanced testing and processing Please contact Silicon Labs sales for more information regarding AM and AQ devices for your automotive project 23 Rev 1 3 SILICON LABS 8051 58 59 3 Pin Definitions Table 3 1 Pin Definitions for the C8051F58x F59x
420. ters used to select the PCAO capture compare module s operating mode All modules set to use 8 9 10 or 11 bit PWM mode must use the same cycle length 8 11 bits Setting the ECCFn bit in a PCAOCPMnh register enables the module s CCFn interrupt Table 28 2 PCAOPWM Bit Settings for PCAO Capture Compare Modules Operational Mode PCAOCPMn PCAOPWM Bit Number 5 4 2 1 0 apture triggered by positive edge on CEXn Capture triggered by negative edge on CEXn Capture triggered by any transition on CEXn Software Timer High Speed Output Frequency Output 8 Bit Pulse Width Modulator Note 7 9 Bit Pulse Width Modulator Note 7 10 Bit Pulse Width Modulator Note 7 11 Bit Pulse Width Modulator Note 7 16 Bit Pulse Width Modulator NI N gt X X X X X X D w w w J w w J Jj UJ 3 gt gt gt gt gt gt gt gt gt gt gt O gt lt gt gt lt gt lt gt lt gt lt O O O O X X x gt x O O O O O O O O x gt O o o o o o Of o f o o o o o o m m m m m o o S Of Of ol O O O oj ol o o o o O O O O 9 o O o X Don t Care no functional difference for individual module if 1 or 0 A Enable interrupts for this module PCAO interrupt triggered
421. the clock low duration is available to accommodate devices with different speed capabilities on the same bus The SMBus interface may operate as a master and or slave and may function on a bus with multiple mas ters The SMBus provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation A block diagram of the SMBus peripheral and the associated SFRs is shown in Figure 23 1 SMBOCN SMBOCF MTSSAAAS 1 NINIUIXIMIMIMIM SIHIS T B BIBIB TO RIL M ED 5 D AAAAAAA TO Overflow T1 Overflow TMR2H Overflow TMR2L Overflow 4 FILTER SMBUS CONTROL LOGIC Interrupt e Arbitration Request e SCL Synchronization e SCL Generation Master Mode SCL SDA Control Control e IRQ Generation gt Port VO Control Control gt sQ Qo O x oO Data Path SDA SMBODAT 7 6 5 4 S 2 1 0 Figure 23 1 SMBus Block Diagram Rev 1 3 239 SILICON LABS 8051 58 59 23 1 Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents 1 The and How to Use It including specifications
422. the common mode voltage on CP0 and CPO 53 Rev 1 3 SILICON LABS 8051 58 59 6 12 Bit ADC ADCO The ADCO on the C8051 F58x F59x consists of an analog multiplexer AMUXO with 35 28 total input selec tions and a 200 ksps 12 bit successive approximation register SAR ADC with integrated track and hold programmable window detector programmable attenuation 1 2 and hardware accumulator The ADCO subsystem has a special Burst Mode which can automatically enable ADCO capture and accumulate sam ples then place ADCO in a low power shutdown mode without CPU intervention The AMUXO data con version modes and window detector are all configurable under software control via the Special Function Registers shows in Figure 6 1 ADCO inputs are single ended and may be configured to measure 0 0 P3 7 the Temperature Sensor output Vpp or GND with respect to GND The voltage reference for ADCO is selected as described in Section 7 Temperature Sensor on page 74 ADCO is enabled when the ADOEN bit in the ADCO Control register ADCOCN is set to logic 1 or when performing conversions in Burst Mode ADCO is in low power shutdown when ADOEN is logic 0 and no Burst Mode conversions are taking place ADCOMX ADCOTK ADCOCN ADCOMX1 ADCOMXO ADOPWR3 ADOPWR1 ADOEN BURSTEN ADOINT gt ADOBUSY WNT ADOLJST ADOMI L ADOCMO Available on 48 pi
423. the low byte should always be written first Writing to PCA1CPLn clears the ECOM1n bit to 0 writing to PCA1CPHn sets ECOM1n to 1 Write to PCA1CPLn Reset Write to PCA1CPHn 1 Interrupt PCA1CPLn PCA1CPHn 16 bit Comparator PCA1 pe PCAIL Figure 29 6 PCA1 High Speed Output Mode Diagram Rev 1 3 339 SILICON LABS C8051F58x F59x 29 3 4 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCA1 clocks to count before the output is toggled The frequency of the square wave is then defined by Equation 29 1 Fo CEXn 3X PCAICPHn Note A value of 0x00 in the PCA1CPHnh register is equal to 256 for this equation Equation 29 1 Square Wave Frequency Output Where is the frequency of the clock selected by the CPS12 0 bits in the PCA1 mode register PCA1MD The lower byte of the capture compare module is compared to the PCA1 counter low byte ona match is toggled and the offset held in the high byte is added to the matched value PCA1CPLn Frequency Output Mode is enabled by setting the ECOM1n TOG1n and PWM 1n bits in the PCA1CPMn register Note that the MAT1n bit should normally be set to 0 in this mode If the MAT 1n bit is set to 1 the CC
424. thin 1 4 LSB tis the required settling time in seconds Rota is the sum of the AMUXO resistance and any external source resistance nis the ADC resolution in bits 10 59 Rev 1 3 SILICON LABS 8051 58 59 MUX Select x p ss Ruux 2 CsaAwvPLE RCinput Csampce Figure 6 5 ADC0 Equivalent Input Circuit 6 3 Selectable Gain ADCO on the C8051F58x F59x family of devices implements a selectable gain adjustment option By writ ing a value to the gain adjust address range the user can select gain values between 0 and 1 016 For example three analog sources to be measured have full scale outputs of 5 0 V 4 0 V and 3 0 V respectively Each ADC measurement would ideally use the full dynamic range of the ADC with an internal voltage reference of 1 5 V or 2 2 V set to 2 2 V for this example When selecting the first source 5 0 V full scale a gain value of 0 44 5 V full scale x 0 44 2 2 V full scale provides a full scale signal of 2 2 V when the input signal is 5 0 V Likewise a gain value of 0 55 4 V full scale x 0 55 2 2 V full scale for the second source and 0 73 3 V full scale x 0 73 2 2 V full scale for the third source provide full scale ADCO measurements when the input signal is full scale Additionally some sensors or other input sources have small part to part variations that must be accounted for to achieve accurate results In this case the programmable gain
425. tion 202 P2MDIN OxF3 Port 2 Input Mode Configuration 209 P2MDOUT OxA6 Port 2 Output Mode Configuration 209 P2SKIP OxD6 Port 2 Skip 210 P3 0 0 Port 3 Latch 210 P3MASK OxAF Port 3 Mask Configuration 203 P3MAT OxAE Port 3 Match Configuration 203 P3MDIN OxF4 Port 3 Input Mode Configuration 211 P3MDOUT OxAE Port 3 Output Mode Configuration 211 P3SKIP 0 07 Port 3 Skip 212 P4 0 5 Port 4 Latch 212 121 Rev 1 3 SILICON LABS 8051 58 59 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page P4MDOUT OxAF Port 4 Output Mode Configuration 213 PCAOCN OxD8 PCAO Control 327 PCAOCPHO OxFC PCAO Capture 0 High 332 PCAOCPH1 OxEA PCAO Capture 1 High 332 PCAOCPH2 OxEC PCAO Capture 2 High 332 OxEE PCAO Capture 3 High 332 PCAOCPH4 OxFE PCAO Capture 4 High 332 5 OxCF PCAO Capture 5 High 332 PCAOCPLO OxFB PCAO Capture 0 Low 332 PCAOCPL1 OxE9 PCAO Capture 1 Low 332 PCAOCPL2 OxEB PCAO Capture 2 Low 332 PCAOCPL3 OxED PCAO Capture 3 Low 332 PCAOCPL4 OxFD PCAO Capture 4 Low 332 PCAOCPL5 OxCE PCAO Capture 5 Low 332 PCAOCPMO OxDA PCAO Module 0 Mode Register 330 PCAOCPM1 OxDB PCAO Module 1 Mode Register 330 2 OxDC PCAO Module 2 Mode Register 330 PCAOCPM3 OxDD PCAO Module 3
426. trol This bit sets the priority of the ADCO Conversion Complete interrupt 0 ADCO Conversion Complete interrupt set to low priority level 1 ADCO Conversion Complete interrupt set to high priority level PWADCO PSMBO ADCO Window Comparator Interrupt Priority Control This bit sets the priority of the ADCO Window interrupt 0 ADCO Window interrupt set to low priority level 1 ADCO Window interrupt set to high priority level SMBus SMBO Interrupt Priority Control This bit sets the priority of the SMBO interrupt 0 SMBO interrupt set to low priority level 1 SMBO interrupt set to high priority level 133 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 14 5 EIE2 Extended Interrupt Enable 2 Bit Name 5 4 2 1 51 EREGO Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 SFR Address OxE7 SFR Page All Pages Bit Name Function 7 ET5 ET4 Enable Timer 5 Interrupt This bit sets the masking of the Timer 5 interrupt 0 Disable Timer 5 interrupts 1 Enable interrupt requests generated by the TF5L or TF5H flags Enable Timer 4 Interrupt This bit sets the masking of the Timer 4 interrupt 0 Disable Timer 4 interrupts 1 Enable interrupt requests generated by the TF4L or TF4H flags ECP2 Enable C
427. ule Low Byte 330 SFR Definition 28 8 PCAOCPHn PCAO Capture Module High Byte 330 SFR Definition 29 1 PCATON PONAT Control 343 SFR Definition 29 2 PCA1MD PCA1 Mode 344 SFR Definition 29 3 PCA1PWM PCA1 PWM Configuration 345 SFR Definition 29 4 PCA1CPMn PCA1 Capture Compare Mode 346 SFR Definition 29 5 PCA1L PCA1 Counter Timer Low Byte 347 SFR Definition 29 6 PCA1H PCA1 Counter Timer High Byte 347 SFR Definition 29 7 PCA1CPLn PCA1 Capture Module Low Byte 348 SFR Definition 29 8 PCA1CPHn PCA1 Capture Module High Byte 348 17 Rev 1 3 SILICON LABS 8051 58 59 1 System Overview C8051F58x F59x devices are fully integrated mixed signal System on a Chip MCUs Highlighted features are listed below Refer to Table 2 1 for specific product feature selection and part ordering numbers High speed pipelined 8051 compatible microcontroller core up to 50 MIPS In system full speed non intrusive debug interface on chip Controller Area Network CAN 2 0B Controller with 32 message objects each with its own indentifier mask C8051 F580 2 4 6 8 F590 LIN 2 1 peripheral fully backwards compatible master and
428. ure 27 1 TO Mode 0 Block 288 10 Rev 1 3 SILICON LABS 8051 58 59 Figure 27 2 TO Mode 2 Block 289 Figure 27 3 TO Mode Block Diagram 290 Figure 27 4 Timer 2 16 Bit Mode Block Diagram 295 Figure 27 5 Timer 2 8 Bit Mode Block Diagram 296 Figure 27 6 Timer 2 External Oscillator Capture Mode Block Diagram 297 Figure 27 7 Timer 16 Bit Mode Block Diagram 301 Figure 27 8 Timer 8 Bit Mode Block Diagram 302 Figure 27 9 Timer External Oscillator Capture Mode Block Diagram 303 Figure 27 10 Timer 4 and 5 Capture Mode Block Diagram 308 Figure 27 11 Timer 4 and 5 Auto Reload and Toggle Mode Block Diagram 309 Figure 28 1 PCAO Block Diagram esee 314 Figure 28 2 PCAO Counter Timer Block Diagram 315 Figure 28 3 PCAO Interrupt Block Diagram 00 316 Figure 28 4 PCAO Capture Mode 2 318 Figure 28 5 PCAO Software Timer Mode Diagram 319 Figure 28 6 PCAO High Speed
429. ut Mode registers PnMDIN Each Port cell can be configured for analog or digital I O This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this is P4 which can only be used for digital I O The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this is the SMBus SDA SCL pins which are configured as open drain regardless of the PnMDOUT settings SFR Definition 20 13 PO Port 0 Bit 7 6 5 4 3 2 1 0 Name PO 7 0 Reset 1 1 1 1 1 1 1 1 SFR Address 0x80 SFR Page All Pages Bit Addressable Bit Name Description Write Read 7 0 PO 7 0 Port 0 Data 0 Set output latch to logic 0 PO n Port is logic Sets the Port latch logic LOW LOW value or reads the Port pin 1 Set output latch to logic 1 PO n Port pin is logic logic state in Port cells con HIGH HIGH figured for digital I O Rev 1 3 204 SILICON LABS 8051 58 59 SFR Definition 20 14 POMDIN Port 0 Input Mode Bit 7 6 5 4 3 2 1 0 Name POMDIN 7 0 Type R W Reset 1 1 1 1 1 1 1 1
430. utput Level Select This bit selects the output voltage level for the internal voltage reference 0 Internal voltage reference set to 1 5 V 1 Internal voltage reference set to 2 20 V 3 REFSL Voltage Reference Select This bit selects the ADCs voltage reference 0 Vref pin used as voltage reference 1 Vpp used as voltage reference If Vpp is selected as the voltage reference and the ADC is enabled in the ADCOCN register the PO O VREF pin cannot operate as a gen eral purpose I O pin in open drain mode With the above settings this pin can operate in push pull output mode or as an analog input 2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor off 1 Internal Temperature Sensor on 1 BIASE Internal Analog Bias Generator Enable Bit 0 Internal Bias Generator off 1 Internal Bias Generator on 0 REFBE Reference Buffer Enable Bit 0 On chip Reference Buffer off 1 On chip Reference Buffer on Internal voltage reference driven on the pin 76 Rev 1 3 SILICON LABS 8051 58 59 9 Comparators C8051F58x F59x devices include three on chip programmable voltage Comparators A block diagram of the comparators is shown in Figure 9 1 where n is the comparator number 0 1 or 2 The three Com parators operate identically except that ComparatorO can also be used a reset source Each Comparator offers programmable response time and hysteresis an analog input multiple
431. utput Mode Bit 7 6 5 4 3 2 1 0 P1MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 SFR Address 0xA5 SFR Ox0F Bit Name Function 7 0 PIMDOUTT 7 0 Output Configuration Bits for 1 7 1 0 respectively These bits are ignored if the corresponding bit in register P1MDIN is logic 0 0 Corresponding P1 n Output is open drain 1 Corresponding P1 n Output is push pull 207 Rev 1 3 SILICON LABS 8051 58 59 SFR Definition 20 20 P1SKIP Port 1 Skip These bits select Port 1 pins to be skipped by the Crossbar Decoder Port pins used for analog special functions or GPIO should be skipped by the Crossbar Bit 7 6 5 4 3 2 1 Name P1SKIP 7 0 Type R W Reset 0 0 0 0 0 0 0 SFR Address 0xD5 SFR Page OxOF Bit Name Function 7 0 15 7 0 Port 1 Crossbar Skip Enable Bits 0 Corresponding P1 n pin is not skipped by the Crossbar 1 Corresponding P1 n pin is skipped by the Crossbar SFR Definition 20 21 P2 Port 2 Bit 7 6 5 4 3 2 1 Name P2 7 0 Type R W Reset 1 1 1 1 1 1 1 Bit Name Description SFR Address 0 0 SFR Page All Pages Bit Addressable Write Read 7 0 P2 7 0 Port 2Data Sets the Port latch logic value or reads the
432. v 1 3 SILICON LABS 8051 58 59 The CAN controller clock must be less than or equal to 25 MHz If the 1 51 system clock is above 25 MHz the divider in the CANOCFG register must be set to divide the CAN controller clock down to an appropriate speed 22 1 2 CAN Register Access The CAN controller clock divider selected in the CANOCFG SFR affects how the CAN registers can be accessed If the divider is set to 1 then a CAN SFR can immediately be read after it is written If the divider is set to a value other than 1 then a read of a CAN SFR that has just been written must be delayed by a certain number of cycles This delay can be performed using a NOP or some other instruction that does not attempt to read the register This access limitation applies to read and read modify write instructions that occur immediately after a write The full list of affected instructions is ANL ORL MOV XCH and XRL For example with the CANOCFG divider set to 1 the CANOCN SFR can be accessed as follows MOV CANOCN 041 Enable access to Bit Timing Register MOV R7 CANOCN Copy CANOCN to R7 With the CANOCFG divider set to 2 the same example code requires an additional NOP MOV CANOCN 041 Enable access to Bit Timing Register NOP Wait for write to complete MOV R7 CANOCN Copy CANOCN to R7 The number of delay cycles required is dependent on the divider setting With a divider of 2 the read must wait for 1 system clock cycle
433. value could be used as a calibration value to eliminate these part to part variations 6 3 1 Calculating the Gain Value The ADCO selectable gain feature is controlled by 13 bits in three registers ADCOGNH contains the 8 upper bits of the gain value and ADCOGNL contains the 4 lower bits of the gain value The final GAINADD bit ADCOGNA O controls an optional extra 1 64 0 016 of gain that can be added in addition to the ADCOGNH and ADCOGNL gain The ADCOGNA O bit is set to 1 after a power on reset The equivalent gain for the ADCOGNH ADCOGNL and ADCOGNA registers is as follows _ GAI 4 gain E GAINADD x 2 Equation 6 2 Equivalent Gain from the ADCOGNH and ADCOGNL Registers Where GAIN is the 12 bit word of ADCOGNH 7 0 and ADCOGNL 7 4 GAINADD is the value of the GAINADD bit ADCOGNA 0 gain is the equivalent gain value from 0 to 1 016 Rev 1 3 60 SILICON LABS 8051 58 59 For example if ADCOGNH OxFC ADCOGNL 0x00 and GAINADD 1 GAIN 0 4032 and the resulting equation is as follows GAIN E 4096 xz x a 0 984 0 016 1 0 The table below equates values in the ADCOGNH ADCOGNL ADCOGNA registers to the equivalent gain using this equation ADCOGNH Value ADCOGNL Value GAINADD Value GAIN Value Equivalent Gain OxFC default 0x00 default 1 default 4032 64 1 0 default 0 7 0 00 1 1984 64 0 5 0 0 00 1 3008 64 0 75 0x3G 0x00 1 960 64 0
434. xF8 Bit Addressable SFR Page 0x00 Bit Name Function 7 SPIF SPIO Interrupt Flag This bit is set to logic 1 by hardware at the end of a data transfer If interrupts are enabled setting this bit causes the CPU to vector to the SPIO interrupt service rou tine This bit is not automatically cleared by hardware It must be cleared by soft ware 6 WCOL Write Collision Flag This bit is set to logic 1 by hardware and generates a SPIO interrupt to indicate a write to the SPIO data register was attempted while a data transfer was in progress It must be cleared by software 5 MODF Mode Fault Flag This bit is set to logic 1 by hardware and generates a SPIO interrupt when a mas ter mode collision is detected NSS is low MSTEN 1 and NSSMD 1 0 01 This bit is not automatically cleared by hardware It must be cleared by software 4 RXOVRN _ Receive Overrun Flag valid in slave mode only This bit is set to logic 1 by hardware and generates a SPIO interrupt when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPIO shift register This bit is not automatically cleared by hardware It must be cleared by software 3 2 NSSMD 1 0 Slave Select Mode Selects between the following NSS operation modes See Section 26 2 and Section 26 3 00 3 Wire Slave or 3 Wire Master Mode NSS signal is not routed to a port pin 01 4 Wire Slave or Multi Master Mode D
435. xer and two outputs that are optionally available at the Port pins a synchronous latched output CP1 CP2 or an asynchronous raw output CPOA CP1A CP2A The asynchronous signal is available even when the system clock is not active This allows the Comparators to operate and generate an output with the device in STOP mode When assigned to a Port pin the Comparator outputs may be configured as open drain or push pull see Section 20 4 Port I O Initialization on page 195 ComparatorO may also be used as a reset source see Section 17 5 Comparator0 Reset on page 155 The inputs are selected in the CPTOMX register SFR Definition 9 7 The 1 bits select the ComparatorO positive input the CMXON1 CMXONO bits select the ComparatorO negative input The Comparator1 inputs are selected in the CPT1MX register SFR Definition 9 8 The CMX1P1 CMX1P0 bits select the Comparator1 positive input the CMX1N1 CMX1NO bits select the Comparator1 negative input The Comparator2 inputs are selected in the CPT2MX register SFR Definition 9 9 The 2 1 2 bits select the Comparator1 positive input the CMX2N1 CMX2NO bits select the Com parator2 negative input Important Note About Comparator Inputs The Port pins selected as Comparator inputs should be con figured as analog inputs in their associated Port configuration register and configured to be skipped by the Crossbar f
436. xt switching between multiple tasks Push operations on the SFR Page Stack only occur on interrupt service and pop operations only occur on interrupt exit execution on the RETI instruction The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit SFRPGEN in the SFR Page Control Register SFROCN See SFR Definition 13 1 Rev 1 3 112 SILICON LABS 8051 58 59 SFR Definition 13 1 SFROCN SFR Page Control Bit 7 6 5 4 3 0 Name SFRPGEN Type R R R R R R W Reset 0 0 0 0 0 1 SFR Address 0x84 SFR Page Ox0F Bit Name Function 7 1 Unused Read 00000006 Write Don t Care 0 SFRPGEN SFR Automatic Page Conirol Enable Upon interrupt the C8051 Core will vector to the specified interrupt service routine and automatically switch the SFR page to the corresponding peripheral or function s SFR page This bit is used to control this autopaging function 0 SFR Automatic Paging disabled The C8051 core will not automatically change to the appropriate SFR page i e the SFR page that contains the SFRs for the periph eral function that was the source of the interrupt 1 SFR Automatic Paging enabled Upon interrupt the C8051 will switch the SFR page to the page that contains the SFRs for the peripheral or function that is the source of the interrupt 11

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