User Manual, Guide Book, Application Notes and Some
Contents
1. MCU AN 500078 E 10 Page 2 16 bit PPG Timer V1 0 Contents FUJITSU CONTENTS 2 iE fedus qc M 3 MEN Us 4 2 5 2 1 RCO UN 5 22 RN 5 9 16bit PPG Timer Description ua sa ERU 6 3 1 Block Diagram of 16bit PPG 080 7 3 2 16bit PPG TIMET Tt 7 3 3 Registers List of 16bit PPG 7 3 4 16bit PPG Down Counter Registers 8 3 5 16bit PPG Cycle Setting Buffer Registers 9 3 6 16bit PPG Duty Setting Buffer 2 4 4 1 10 3 7 16bit PPG Status Control Registers 2 2 FRE 11 3 8 16bit PPG trigger source control 13 3 9 PPG Macro general setting procedure 14 4 Interrupts of 16bit PPG Timer iria ain ere ther Ee ttt ru norat rto sr seas ecsedestevacaniecasaste 15 4 1 Interrupt Control Bits and Interrupt Sources of 16 bit PPG Timer 15 4 2 Register and Vect2. void PPGClose DDR7_P73 1 PCNTHO_PGMS 1 void PPGSet WORD usCycle WORD usDuty DDR7 P73 1 PPGO PCSRHO BYTE_HI usCycle Upper Byte PCSRLO BYTE_LO usCycle Lower Byte PDUTHO BYTE Hl usDuty Upper Byte PDUTLO BYTE LO usDuty Lower Byte PCNTHO 0xF7 Mask 1 1 000us MCLK 8 OneShot Soft Trigger PCNTLO 0x0E OSEL L IREN 0 void main void __DI set il 3 InitlrqLevels WDTH z0xA5 WDTL 0x96 WATR SYCC 0xF0 Main Clock SYCC2 0xF4 Main Clock SYSC 0xBC BUZZ P01 MCU AN 500078 E 10 Page 24 16 bit PPG Timer V1 0 Chapter 10 Sample Code FUJITSU SYSC2 0x02 PPG P73 Disable 2 while ISTBC MRDY El PTGS0 0x05 VCO rising edge start PPG VC1 rising edge stop PPG PPGSet 200 10 PPGOpen PPGClose VECTORS C THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS FUJITSU SEMICONDUCTOR ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES Fujitsu Semiconductor Europe GmbH VECTORS C Interrupt level priority setting Interrupt vector definition 29 09 04 1 00 HWe V30L29 InitlrqLevels This function all interrupt control registers It can be used to set all interrupt priorities in static applications If this file contains assignments to dedicated resources verify that the appropriate controller is used NOTE value OxFF disables
3. Page 20 7 Typical Application 7 1 HW Design In this application we will use the PPG to drive a buzzer VCO rising edge start PPG VC1 rising edge stop PPG PTGS0 0x05 The MCU used is MB95F430K The HW is designed as below MB95F430K mu CMP1_N Figure 13 Hardware design 7 2 Sample Code void main void Return none Parameters Description system main programm Example main void main void SDE InitIrqLevels WDTH 0xA5 Disable WDTL 0x96 WATR SYCC 0xF0 Main Clock SYCC2 0xF4 Main Clock SYSC 027 01 002 PEGES Disable while STBC MRDY Ima re PTGS0 0x05 VCO0 rising edge start PPG VCl rising edge stop PPGSet 200 10 PPGOpen PPGClose MCU AN 500078 E 10 Page 21 FU ITSU 16 bit PPG Timer V1 0 Chapter 8 More Information 8 More Information For more Information on FUJITSU Semiconductor products visit the following websites English version http www fujitsu com cn fsp services mcu mb95 application_notes html Simplified Chinese Version http www fujitsu com cn fss services mcu mb95 application notes html MCU AN 500078 E 10 Page 22 16 bit PPG Timer V1 0 Chapter 9 Appendix FUJITSU 9 Appendix Figure 1 PPG cT 5 Figur 2 TObIt PPG TIMET E BO 6 Figure Block Di
4. T ns m Value of PCSRHO amp PCSRLO registers 2 m x T ns n Value of PDUTHO amp PDUTLO registers Figure 11 Trigger from VC in PWM Mode Condition 2 PPG start triggering and stop triggering occur simultaneously When STS1 and 5 50 are set to 01B SPS2 SPS1 and SPSO to 001B and if the hardware trigger from a rising edge of VC ch 0 and another rising edge of VC ch 1 occur simultaneously the PPG will halt the stop trigger has higher priority than the start trigger MCU AN 500078 E 10 Page 17 FU ITSU 16 bit PPG Timer V1 0 Chapter 5 PPG Trigger STS 1 0 SPS 2 0 Counter value 1 Rising edge detected Rising edge detected PPG Normal polarity The 16 bit PPG timer stops operating if a start trigger and a stop trigger occur simultaneously Figure 12 Triggers Start and Stop Occur Simultaneously in PWM Mode MCU AN 500078 E 10 Page 18 6 PPG Driver 16 bit PPG Timer V1 0 Chapter 6 PPG Driver FUJITSU This chapter describes the PPG driver 6 1 Peripheral Usage The MCU pins used as below PPGO used as PPG wave output TRGO used as PPG trigger 6 2 Driver Code 6 2 1 General Definition typedef unsigned char typedef unsigned char BOOLEAN INT8U Unsigned 8 bit quantity typedef signed char _ INT8S Signed 8 bit quantity typedef unsigned int INT16U Unsigned 16 bit quantity typedef signed 165 Signed 16 bit quantity typedef unsigned long IN
5. as PPG stop trigger Figure 9 16bit PPG Trigger Source Control Register PTGSO MCU AN 500078 E 10 Page 13 FU ITSU 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description 3 9 PPG Macro general setting procedure Initial setup 1 Set the interrupt level ILR3 ILR4 2 Enable the hardware trigger and interrupts select the interrupt type and enable output PCNTLO 3 Select the count clock and the mode and enable timer operation PCNTHO 4 Set the cycle PCSRHO PCSRLO 5 Set the duty PDUTLO 6 Start the PPG by the software trigger STRG 1 Interrupt processing 1 Process any interrupt 2 Clear the interrupt request flag PCNTLO IRQF MCU AN 500078 E 10 Page 14 16 bit PPG Timer V1 0 Chapter 4 Interrupts of 16bit PPG Timer FUJITSU 4 Interrupts of 16bit PPG Timer PPG interrupt will be described The 16 bit PPG timer can generate interrupt requests in the following cases When a trigger or counter borrow occurs When a rising edge of PPG is generated in normal polarity When a falling edge of PPG is generated in inverted polarity The interrupt operation is controlled by IRS1 bit3 and IRSO bit2 in the PCNTL register 4 1 Interrupt Control Bits and Interrupt Sources of 16 bit PPG Timer Interrupt flag bit Interrupt request enable bit Interrupt type select bits Interrupt sources PCNTLO IRS1 IRSO 00 Hardware trigger by TRG Pin input of
6. down counter register hterrupt htarrupt sdection 2 d 16 01 PPG Start trigger selection CH1 P CH2 P Sbp trigger CH2 N selection P CH3 N gesz ses eso Figure 3 Block Diagram of 16 bit PPG Timer 3 2 Pins of 16bit PPG Timer The pin related to the 16 bit PPG timer is namely the PPGO pin TRGO pin PPGO is output pin The PPG waveform can be outputted by using the 16 bit PPG status control register to enable output PCNTLO POEN 1 TRGO is used to start 16 bit PPG timer by hardware trigger 3 3 Registers List of 16bit PPG Timer Register Description PDCRHO 16 bit PPG down counter register upper PDCRLO 16 bit PPG down counter register lower PCSRHO 16 bit PPG cycle setting buffer register upper PCSRLO 16 bit PPG cycle setting buffer register lower PDUTHO 16 bit PPG duty setting buffer register upper PDUTLO 16 bit PPG duty setting buffer register lower 16 bit PPG status control register upper PCNTLO 16 bit PPG status control register lower PTGSO 16 bit PPG trigger source control register MCU AN 500078 E 10 Page 7 16 bit PPG Timer V1 0 FUJITSU Chapter 3 16bit PPG Timer Description 3 4 16bit PPG Down Counter Registers The 16 bit PPG down counter registers upper lower PDCRHO PDCRLO form a 16 bit register which is used to read the count value from the 16 bit PPG down counter The initial
7. intvect DefaultIRQHandler 20 IRQ20 Watch timer pragma DefaultIRQHandler 21 IRQ21 none pragma intvect DefaultIRQHandler 22 IRQ22 none pragma intvect DefaultIRQHandler 23 IRQ23 Flash Memory DefaultIRQHandler This function is a placeholder for all vector definitions Either use your own placeholder or add necessary code here the real used resource interrupt handlers should be defined in the main c ieee ee sees seats E ease tae tee eee se oes eee oe eae ae CU __ interrupt void DefaultIRQHandler void DI disable interrupts while 1 wait halt system MCU AN 500078 E 10 Page 27
8. the interrupt and value 0 sets highest priority NOTE For all resource interrupts exists Interrupt level registers ILRx Each register sets the level for 4 different resources IRQx NOTE This list is prepared for the 8FX emulation MB95FV100 Horn Not all resources will be supported by all 8FX devices a ee a ee E void InitlrqLevels void ILRx IRQs defined by ILRx ILRO OxFF RQO external interrupt ch4 RQ1 external interrupt 1 ch5 RQ2 external interrupt 1 external interrupt ch3 ch7 ILR1 OxFF RQ4 UART SIO RQ5 8 16 bit timer chO lower 1806 8 16 bit timer chO upper MCU AN 500078 E 10 Page 25 FU ITSU 16 bit PPG Timer V1 0 Chapter 10 Sample Code RQ7 Output Compare ILR2 OxFF RQ8 Output Compare ch1 RQ9 none 18010 Voltage Compare RQ11 Voltage Compare ch1 ILR3 OxFF RQ12 Voltage Compare ch2 18013 Voltage Compare ch3 RQ14 16 bit free run timer 18015 16 bit PPGO ILR4 OxFF RQ16 12C 17 none RQ18 10 bit A D converter 18019 Timebase timer ILR5 OxFF RQ20 Watch timer RQ21 none RQ22 none RQ23 Flash Memory Prototypes Add your own prototypes here Each vector definition needs is proto type Either do it here or include a header file containing them Vector definiton Use following statement
9. upper PDUTHO Address 515 54 biti2 biti1 5810 bit8 Initial value OFAE PDUTHO 0015 5014 0013 DU12 DUTT DUTO 5009 0008 111111118 RW RW RW RW RW RW 16 bit PPG duty setting buffer register lower PDUTLO Address bit7 bite bit5 bit4 bit3 bit2 bit1 Initial value OFAF4PDUTLO DUO7 2406 0005 0004 0003 DUO2 DUO1 DU01 111111118 RW RW RW RW RW RW RW Figure 6 16bit PPG Duty Register MCU AN 500078 E 10 Page 10 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description FUJITSU 3 7 16bit PPG Status Control Registers The 16 bit PPG status control register is used to enable and disable the 16 bit PPG timer and also to set the operating status for the software trigger retrigger control interrupt and output polarity This register can also check the operation status bit7 bit4 bit2 bitd Initial value PCNTHO Torsa ers oar Poms 00000000 RW ROW RW RW RW RW R W PGMS PPG output mask enable bit Disables PPG output mask Enables PPG output mask t 1 of o mike iloji wes e Machine clock Main clock RTRG Software retrigger enable bit Disables software retrigger Enables software retrigger Software trigger bit e
10. values of the register are all 0 Always use one of the following procedures to read from this register Use the MOVW instruction use a 16 bit access instruction to read the PDCRHO register address Use the MOV instruction and read PDCRHO first and PDCRLO second reading PDCRHO automatically copies the lower 8 bits of the down counter to PDCRLO These registers are read only and writing has no effect on the operation 16 bit PPG down counter register upper PDCRHO Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value PDCRHO DC15 DC14 DC13 DC12 DC11 DC10 DCO9 0 08 000000005 R WX R WX R WX RWX 16 bit PPG down counter register lower PDCRLO Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 Initial value PDCRLO 0 07 0 06 0 05 0 04 0803 0 01 00 000000005 R WX R WX R WX R WX R WX R WX R WX R WX Figure 4 16bit PPG Down Counter Register MCU AN 500078 E 10 Page 8 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description FUJITSU 3 5 16bit PPG Cycle Setting Buffer Registers The 16 bit PPG cycle setting buffer registers are used to set the cycle for the output pulses generated by the PPG These registers form a 16 bit register which sets the period for the output pulses generated by the PPG The values set in these registers are loaded to the down counter When writing to these registers always us
11. 16 bit down counter software trigger and retrigger PCNTLO IRS1 IRSO 01 Counter borrow of 16 bit down counter PCNTLO IRS1 IRS0 1 0p Rising edge of 1 output in normal polarity or falling edge of 1 output in inverted polarity PCNTLO IRS1 IRSO 1 1g Counter borrow of 16 bit down counter rising edge of output in normal polarity or falling edge of output in inverted polarity 4 2 Register and Vector Table Addresses Related to Interrupts of 16bit PPG Timer Interrupt source Interrupt Interrupt level setting register Vector table address dee EUN NM ae 16 bit PPG timerch 1 _ 1017 dis MCU AN 500078 E 10 Page 15 16 bit PPG Ti V1 0 FUJITSU Copier 5 PPG Trigger 5 PPG Trigger PPG trigger is described here PPG activation by signal input to the TRG input pin or internal voltage comparator VC input Condition 1 PPG start triggering and stop triggering do not occur simultaneously 1 TRG When STS1 and 5 50 are set to 00B SPS2 SPS1 and 5 50 to 000B and EGS1 and EGSO to 11B and the hardware trigger input from TRG is used the 16 bit PPG timer starts operating at a rising edge and stops upon the detection of a falling edge Moreover the 16 bit PPG timer also starts operating at the following rising edge from the beginning The operation can be re triggered by a valid TRG input hardware trigger regardless of the retrigger setting of the RTRG bit when the TRG input har
12. Fujitsu Semiconductor Shanghai Ltd MCU AN 500078 E 10 Application Note F2MC 8FX FAMILY 8 BIT MICROCONTROLLER MB95F430 SERIES 16 BIT PPG TIMER APPLICATION NOTE co FUJITSU FU ITSU 16 bit PPG Timer V1 0 Revision History Revision History Date Author Change of Records 2010 03 16 V1 0 First draft ea a This manual contains 27 pages The products described in this manual and the specifications thereof may be changed without prior notice To obtain up to date information and or specifications contact your Fujitsu sales representative or Fujitsu authorized dealer Fujitsu will not be liable for infringement of copyright industrial property right or other rights of a third party caused by the use of information or drawings described in this manual The contents of this manual may not be transferred or copied without the express permission of Fujitsu The products contained in this manual are not intended for use with equipment which require extremely high reliability such as aerospace equipments undersea repeaters nuclear control systems or medical equipments for life support Some of the products described in this manual may be strategic materials or special technology as defined by the Foreign Exchange and Foreign Trade Control Law In such cases the products or portions thereof must not be exported without permission as defined under the law 2010 Fujitsu Semiconductor Shanghai Co Ltd
13. T32U Unsigned 32 bit quantity typedef signed INT32S Signed 32 bit quantity define BOOL BOOLEAN define BYTE INT8U define UBYTE INT8U define WORD INT16U define UWORD INT16U define LONG INT32S define ULONG INT32U define UCHAR INT8U define UINT INT16U define DWORD INT32U define TRUE 1 define FALSE 0 define BYTE_LO w UBYTE w define BYTE_HI w UBYTE UWORD w 8 amp 0xFF MCU AN 500078 E 10 Page 19 16 bit PPG Timer V1 0 FUJITSU 6 PPG Driver 6 2 2 PPG Routine void PPGOpen Return none Parameters none Description open the PPG function Example PPGOpen void PPGOpen DDR7_P73 1 PCNTHO PGMS 0 Open PPG void PPGClose Return none Parameters none Description close the PPG function Example PPGClose void PPGClose DDR7_P73 1 PCNTHO PGMS 1 Close PPG void PPGSet WORD usCycle WORD usDuty Return none Parameters usCycle is PPG cycle us usDuty is PPG duty us Description set the PPG function Example PPGSet 40 10 void PPGSet WORD usCycle WORD usDuty DDR7_P73 1 PPGO PCSRHO BYTE usCycle Upper Byte PCSRLO BYTE LO usCycle Lower Byte PDUTHO BYTE usDuty Upper Byte PDUTLO BYTE LO usDuty Lower Byte PCNTHO OxF7 Mask 1 1 000us MCLK 8 OneShot Soft Trigger PCNTLO 0x0E OSEL L IREN 0 MCU AN 500078 E 10
14. agram of 16 bit PPG sess enne 7 Figure 4 16bit PPG Down Counter Heglster 8 Figura 5 16bit PPG Gycle Registe 9 Figure 6 16bit PPG Duty Register uina du toD cud 10 Figure 7 16bit PPG Status Control Register Upper Byte 11 Figure 8 16bit PPG Status Control Register Lower Byte 12 Figure 9 16bit PPG Trigger Source Control Register 0 sss 13 Figure 10 Trigger from TRG PWM MOD erri Rae tb co Rte Rn kt tah 16 Figure 11 Trigger from VC m PWM rep me 17 Figure 12 Triggers Start and Stop Occur Simultaneously in PWM 18 Figure 13 Hardware desig ssec o a a a E E AN E E a ea 21 MCU AN 500078 E 10 Page 23 16 bit PPG Timer V1 0 FUJITSU 5 10 1 Code 10 Sample Code main c a Title Sample main program for sensorless DC inverter control Aurthor Folix Li Date 26th Nov 2999 include mb95430 h include TypeDef h void PPGOpen DDR7_P73 1 PCNTHO PGMS 0
15. by the PPG Transfer of the data from the 16 bit PPG duty setting buffer registers to the duty setting registers is performed at the same timing as the down counter read When writing to these registers always use one of the following procedures Use the MOVW instruction use a 16 bit access instruction to write to the PDUTHO register address Use the MOV instruction and write to PDUTHO first and PDUTLO second If a down counter load occurs after writing data to PDUTHO but before writing data to PDUTLO the value of the 16 bit PPG duty setting buffer registers is not transferred to the duty setting registers The relation between the value of the 16 bit PPG duty setting registers and output pulse is as follows When the same value is set in both the 16 bit PPG cycle setting buffer registers and duty setting registers the H level will always be outputted if normal polarity is set or the L level will always be outputted if inverted polarity is set When the duty setting registers are set to the L level will always be outputted if normal polarity is set or the H level will always be outputted if inverted polarity is set When the value set in the duty setting registers is greater than the value in the 16 bit PPG cycle setting buffer registers the L level will always be outputted if normal polarity is set and the H level will always be outputted if inverted polarity is set 16 bit PPG duty setting buffer register
16. dware trigger has been selected STS 1 0 SPS 2 0 EGS 1 0 Counter value Falling edge detected Hardware tri ser PPG Normal polarity Lc PPG Werdp dy __ i 2 i 2 T Count clock cycle 1 x T ns m Value of PCSRHO amp PCSRLO registers 2 x T ns n Value of PDUTHO amp PDUTLO registers Figure 10 Trigger from TRG in PWM Mode Rising edge detected 2 Voltage comparator VC When STS1 and STSO are set to 01B SPS2 SPS1 and SPSO to 101B and the hardware trigger input from the VC ch 0 is used the 16 bit PPG timer starts operating at a rising edge of VC ch 0 and stops upon the detection of a falling edge of VC ch 1 2 3 Moreover the 16 bit PPG timer also starts operating at the following rising edge of VC ch 0 from the beginning The operation can be re triggered by a valid rising edge of VC ch 0 input hardware trigger regardless of the retrigger setting of the RTRG bit when the VC ch 0 input hardware trigger has been selected MCU AN 500078 E 10 Page 16 16 bit PPG Timer V1 0 Chapter 5 PPG Trigger FUJITSU STS 1 0 SPS 2 0 Counter value Rising edge detected i 1 I 1 1 i I VC ch 0 i 1 14 Falling edge detected 1 i 1 VC 2 i I I o VC ch 3 PPG PPG 1 Inverted polarity 1 1 1 Count clock cycle 1 x
17. e one of the following procedures Use the MOVW instruction use a 16 bit access instruction to write to the PCSRHO register address Use the MOV instruction and write to PCSRHO first and PCSRLO second If a down counter load occurs after writing data to PCSRHO but before writing data to PCSRLO the previous valid PCSRHO PCSRLO value will be loaded to the down counter If the PCSRHO PCSRLO value is modified during counting the modified value will become effective from the next load of the down counter Do not set PCSRHO and PCSRLO to 00H or PCSRHO to 01H and PCSRLO to 01H 16 bit PPG cycle setting buffer register upper PCSRHO Address bitlb biti4 biti3 biti2 biti1 biti0 bit8 Initial value OFAC PCSRHO CS15 CS14 CS13 CS12 CS11 CS10 509 CS08 111111118 RW RW RW RW RW RAW RW RW 16 bit PPG cycle setting buffer register lower PCSRLO Address bit7 bits bit4 bit bit2 bito Initial value OFAD PCSRLO 507 506 05 504 503 502 501 00 111111118 RW RW RW RW RW RW RW Figure 5 16bit PPG Cycle Register MCU AN 500078 E 10 Page 9 FU ITSU 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description 3 6 16bit PPG Duty Setting Buffer Registers The 16 bit PPG duty setting buffer registers control the duty ratio for the output pulses generated by the PPG These registers form a 16 bit register which controls the duty ratio for the output pulses generated
18. ect on operation aay raas 0 Generates software trigger CNTE Timer enable bit R W Readable writable Read value is the same as write value Stops PPG timer RO W Write only Writable 0 is read Enables PPG timer Initial value Figure 7 16bit PPG Status Control Register Upper Byte STRG MCU AN 500078 E 10 Page 11 FU ITSU 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description 513 512 510 Initial value Esso men mar eo mm AW RW R RMI W RAW Output inversion bit Inverted polarity Output enable bit General purpose port IRS1 IRSO Interrupt type select bit Start trigger by TRGO input VC input sofware trigger or retrigger of TRGO input or VC ch 0 o Rising edge of PPG output in normal polarity or falling edge of PPG output in inverted polarity Duty match Counter borrow rising edge of PPG output in normal polarity or falling edge of PPG output in inverted polarity PPG interrupt flag bit Ex No PPG interrupt Clears this bit No effect on PPG interrupt request enable flag Disables interrupt request Enables interrupt request Esso Hardware trigger erabe wio o The rising edge of TRGO has no effect on operation The operation is started by the rising edge of TRGO The falling edge of TRGO has no effect on opera
19. n switching power supply In automation it can use to control motors 2 2 PPG Formats PPG format consists of frequency and duty PPG s wave is below Figure 1 PPG Formats MCU AN 500078 E 10 Page 5 16 bit PPG Ti V1 0 FUJITSU Chapter 3 PPG Timer Description 3 16bit PPG Timer Description 16 bit PPG timer can output the PWM output and the one shot The output wave form can be reversed by setting the register Normal polarity lt gt Inverted polarity PWM waveform Normal polarity Inverted polarity HI H L One shot waveform Normal polarity ty H L Inverted polarity H L H Figure 2 16bit PPG Timer MCU AN 500078 E 10 Page 6 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description FUJITSU 3 1 Block Diagram of 16bit PPG Timer When upper 8 bits of duty setting register written vid ed 16 D8PPG 16 DIPPG written the value 18717 butler register ting butler rege T8 bIPPG 1 51 duly otherwise it is 0 upper bits bas 91 i Sier E Ber CKS1 ckso oes 1PP L duty s duty 5 utlar reg ster duller reg peting butler reg ste for upper 8 bits butler for lower B bits buffer upper B bits butter Comparator Internal data bus MDSE PGMS OSEL POEN START BORROW 16 54 PPG
20. or Table Addresses Related to Interrupts of 16bit PPG Timer 15 PPG diee o 16 PPG 19 6 1 Peripheral Usage Mh 19 62 19 6 2 1 General Definition 19 6 22 PPO DD odit doge sch 20 4 e 21 21 72 Sample A e ERE 21 Information e M 22 ee eee eee ee ee ee re 23 10 OS 24 MCU AN 500078 E 10 Page 3 16 bit PPG Ti V1 0 FUJITSU 2 1 Introduction In this document we will introduce how to use the PPG function on the MB95F430 series Chapter 2 introduces background and PPG formats Chapter 3 introduces PPG block PPG registers and the setting procedure Chapter 4 introduces PPG interrupt Chapter 5 introduces PPG drivers Chapter 6 introduces PPG application demo MCU AN 500078 E 10 Page 4 16 bit PPG Timer V1 0 Chapter 2 PPG Overview FUJITSU 2 PPG Overview This chapter gives an overview on PPG 2 1 Background It normally is used in communication electronic automation and so on In communication the duty or frequency can be used to identify the protocol In electronic it can use to desig
21. s to define vectors All resource related vectors are predefined Remaining software interrupts can be added hereas well intvect DefaultIRQHandler 0 pragma intvect DefaultIRQHandler 1 pragma intvect DefaultIRQHandler 2 pragma intvect DefaultIRQHandler 3 pragma intvect DefaultIRQHandler 4 pragma intvect DefaultIRQHandler 5 pragma intvect DefaultIRQHandler 6 pragma intvect DefaultIRQHandler 7 pragma intvect DefaultIRQHandler 8 pragma intvect DefaultIRQHandler 9 pragma DefaultIRQHandler 10 pragma intvect DefaultIRQHandler 11 pragma intvect DefaultIRQHandler 12 pragma DefaultIRQHandler 13 external interrupt 0 ch4 external interrupt ch1 ch5 external interrupt ch2 ch6 external interrupt ch3 ch7 UART SIO 8 16 bit timer chO lower 8 16 bit timer chO upper Output Compare 0 Output Compare ch1 none Voltage Compare Voltage Compare ch1 Voltage Compare ch2 Voltage Compare ch3 MCU AN 500078 E 10 Page 26 16 bit PPG Timer 1 0 Chapter 10 Sample Code FUJITSU pragma intvect DefaultIRQHandler 14 IRQ14 16 bit free run timer pragma intvect DefaultIRQHandler 15 IRQ15 16 bit PPGO pragma intvect DefaultIRQHandler 16 IRQ16 12C pragma DefaultIRQHandler 17 IRQ17 none pragma intvect DefaultIRQHandler 18 IRQ18 10 bit A D converter pragma intvect DefaultIRQHandler 19 IRQ19 Timebase timer pragma
22. tion The operation is stoped by the falling edge of TRGO VC Voltage comparator R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction ER Initial value Figure 8 16bit PPG Status Control Register Lower Byte PCNTLO IRQF MCU AN 500078 E 10 Page 12 16 bit PPG Timer V1 0 Chapter 3 16bit PPG Timer Description FUJITSU 3 8 16bit PPG trigger source control Register The 16 bit PPG trigger source control register controls the trigger source of the 16 bit PPG timer bit bit 515 bit2 bito Initial value seso srs stso 000000008 RO WX RO WX RO WX R W RAW RW RW STSO hardware start trigger select bits Enable select rising edge of TRGO as PPG start trigger 1 Select rising edge of VC ch 0 as PPG start trigger 0 Select falling edge of ch 0 as PPG start trigger 1 Select both edges of VC ch 0 as PPG start trigger 5 52 spsi sPso hardware stop trigger select bits Enable select falling edge of TRGO as PPG stop trigger Fo 1 Select rising edge of VC ch 1 as PPG stop trigger Select falling edge of VC ch 1 as PPG stop trigger Select both edges of VC ch 1 as PPG stop trigger Select rising edge of VC ch 1 ch 2 ch 3 as PPG stop tigger Select falling edge of VC ch 1 ch 2 ch 3
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