hytec electronics ltd vtd1612 transient recorder user manual issue 3
Contents
1. VTD 1612A Transient Digitiser User Manual GND GND CLMUX CLKCONV CLKCNVA TRISEQA TRISEQB CKMXSCN ENABLE CLKMUX VCC Enable outputs Clears multiplexer address and SCANBUSY Clocks ADC data into buffer and requests memory write cycle Clocks the memory counter Allows memory address to increment Low enables POSTOFFS and clears memory address Allows CLKCNVA to increment channel address when low Enables ADC data output Increments misc counter and starts conversion 5 3 3 1029 31 32 MEMORY ADDRESS COUNTER PLS159s CA00 CA23 Outputs memory address CA 13 CA16 Outputs have special significance channel number NOCH 1 NOCH 2 NOCH 4 NOCH 8 16WS 32WS 64WS 128WS RESET INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT No of channels F 16 Buffer size 4K 64K Reset counter to 0 when low all outputs high 5 3 4 IC101 ADDRESS SELECT PAL18P8 VALID MESPACE TSPACE RGSPACE IMESPACE A18 ITSPACE A18 A17 A16 A15 A14 RGSPACE A18 A17 A1 6 A15 A14 A13 A1 2 A11 A10 A09 A08 A07 A06 A05 5 3 5 IC103 AM PAL18P8 PIN 1 PINS 2 7 PIN 8 PIN 9 PIN 11 PIN 12 INPUT INPUTS INPUT INPUT INPUT OUTPUT AS Address strobe 5 Address modifier code ILWORD Long word cycle VALID Correct address selected BASEADDRESS Boards address selected ADDROK Address is correct ADDROK LWORD VALID BASE ADDRESS2. 4 5 5 NEAR AND FAR POST TRIGGER CLOCK COUNTS Write D16 15 00 Count value ones complement binary value of clock count 0001 to FFFF FFFF or ones complement of zero value will set zero clock counts Eg if a near post trigger count of 1 and no far post trigger count are required load FFFE and FFFF respectively 4 5 6 PRE TRIGGER NEAR AND FAR POST TRIGGER FREQUENCIES FO F1 F2 F3 F4 Write D16 ES 1 eee E 5 bit code which defines the frequency division for the internal clock Code 2 1MHz Code 3 500KHz Code 4 250KHz etc to Code 31 1 86 x 10 3 Hz Code 0 and 1 provide the full or half clock frequencies when an external clock is used 15 VTD 1612A Transient Digitiser User Manual 4 5 7 UPPER LOWER TRIGGER THRESHOLD LO L7 8 bit code determines lower trigger threshold 0 to 10V UO U7 8 bit code determines upper trigger threshold 0 to 10V When the analog trigger is implemented these two values determine the upper and lower voltage levels for the analog trigger criteria eg if LO L7 is set 7F the lower level would be 5V if UO U7 is set 3F the upper level would be 2 5V 4 5 8 MODULE DESCRIPTOR 15 08 07 06 05 04 03 02 01 00 Read D16 All 178 D7 DO DO D7 patched code which can be used as a board descriptor 4 5 9 RESET MEMORY ADDRESS POINTER A D16 write operation with any data clears the memory address pointer This is particularly useful in Single Scan m
3. Base 30000 Base 2C000 Base 28000 Base 24000 Base 20000 Base 1C000 Base 18000 Base 14000 Base 10000 Base 0C00 Base 08000 Base 04000 Base 00000 VTD 1612A Transient Digitiser User Manual 4 3 TIME STAMP MEMORY When the board is triggered the address of the next location in memory to be updated is stored in the time stamp memory pointed to by the Event Counter thus after initialisation and start up the first recorded time stamp will be stored in location zero of the time stamp memory The next will be stored in location 1 and so on up to a maximum of 8K values If this is exceeded wrap around will occur and the next time stamp will be stored in location zero Location zero resides at the Base Address BA plus 40000 bytes The time stamp memory occupies from BA 40000 to BA 43FFE 44 REGISTER SPACE The control and status registers of the board occupy 16 words at the top of the memory area These are allocated as follows BYTE ADDRESS REGISTER READ WRITE 4 5 BA 4401E BA 4401C BA 4401A BA 44018 BA 44016 BA 44014 BA 44012 BA 44010 BA 4400E BA 4400C BA 4400A BA 44008 BA 44006 BA 44004 BA 44002 BA 44000 Reserved Reserved Reset memory address pointer to zero Module descriptor Upper lower trigger threshold Far post trigger frequency Near post trigger frequency Pre trigger frequency Far post trigger clock count Near post trigger clock count
4. No of channels segment size ADC memory address pointer MS ADC memory address pointer LS Mask and control Interrupt status Interrupt vector Read during the IACK cycle DATA FORMATS EE ADE E eo z 4 5 1 INTERRUPT VECTOR Data Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Write D16 12 VTD 1612A Transient Digitiser User Manual Bits 00 07 8 bit vector Bits 08 15 all 1s if 8 bit vector required 4 5 2 INTERRUPT STATUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Write D16 Bits 0 2 Read D16 bits 0 2 15 Busy Trigger has occurred and the board is in the post trigger phase EE End of event Trigger has occurred and the board is in the post trigger phase has been completed i e both near post trigger and fast post trigger counts have finished HF Half full conversion data has been stored in the lower half of memory and the halfway boundary has been crossed F Full The memory has been completely filled Unless continuous mode is set conversions will be disabled Status bits 0 2 can be reset by writing Os to each bit The Busy bit can only be read A logic 1 indicates that the condition read is true Eg if B 1 the triggered event is busy 4 5 5 MASK AND CONTROL Data Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Write Read D16 ST XMI XMO IP XC AT2 ATI ATO ARM C XT TI EE EH EF EF Enable Full interrupt The top conversion dat
5. STSCAN the sequencer initialises HOLD and provides a series of clock pulses which step the multiplexer counter initiate conversion clocking the data into the buffer register and incrementing the memory address once the data has been written to memory The end of sequence is controlled by a status signal from the conversion address counter to the sequencer SEG LIM which is determined by the number of channels programmed to be scanned 5 2 3 SAMPLING RATE CONTROL There are three sampling phases pre trigger near post trigger far post trigger The sampling rate of each phase can be programmed by a five bit code which controls the division of the basic clock frequency These codes are held in registers PT freq NPT Freq and FPT freq Their outputs are gated to the frequency divider under control fo the RATECON sequencer The number of post trigger samples are controlled by the NPT Counter and FPT Counter These contain buffer registers which hold the number of counts and transfer them to counters when the board is triggered Each sample clocks the relevant counter until overflow occurs The rate control circuit starts in pre trigger mode When triggered the near post trigger frequency and counter are enabled When overflow from the near post counter is received the sequencer commences the far post trigger phase and enables the relevant frequency and counter registers When overflow is received from the far post counter end of event is signalled back to the
6. board jumpers in accordance with Appendix A and the component layout diagram Appendix C 3 1 2 BASE ADDRESS The word address can be selected from 080000 to F80000 hex defined by the five jumpers J12 J16 Insertion of a jumper selects a logical O at that position Thus if J12 J15 are made and J16 is left open base address 800000 is selected 3 1 3 INTERRUPT ACKNOWLEDGE PRIORITY Interrupt priority from 0 to 7 can be selected with J17 J19 Insertion of a jumper selected a logical 0 If J18 J19 are made and J17 is left open priority level 1 is selected This priority corresponds to selection of IRQ1 in the following paragraph 3 1 4 INTERRUPT REQUEST The interrupt request line to be driven by the interrupt is selected by inserting one of jumpers J20 J26 Insertion of J20 selects IRQI 3 1 5 ANALOG INPUT VOLTAGE RANGE The input voltage range is selected using jumpers J1 J4 Jumper J5 selects straight binary conversion or two s complement sign extended to sixteen bits 3 1 6 INTERNAL CLOCK Jumpers J6 and J7 select the internal clock frequency to be used In current versions J7 83MHz is selected 3 1 7 SEQUENCER CLOCK PHASE The jumpers J8 and J9 select the phase relationship between the clock signals of the logic sequencers and their set up buffer registers The jumper is factory set and should be maintained at the current setting 3 1 8 TRIGGER TIMING MONOSTABLE Insituations where only one channel is used
7. AM5 AM4 AM3 AM1 AMO 5 3 6 IC107 RDDEC PAL18P8 PIN 1 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 INPUTS INPUT INPUT INPUT INPUT INPUT BUS ADDRESS A01 A04 IRGSPACE ENEVA VMECYCLE ENAVME WRITE Register addressed VME cycle in progress VME cycle enabled VME write cycle 24 VTD 1612A Transient Digitiser User Manual PIN 11 INPUT ISYSRST PIN 12 OUTPUT RESET PIN 13 OUTPUT WRVEC PIN 14 OUTPUT WRSTATS PIN 15 OUTPUT IRDMODS PIN 16 OUTPUT IRDMAMS PIN 17 OUTPUT IRDMALS PIN 18 OUTPUT IRDMASK PIN 19 OUTPUT IRDSTATS 5 3 7 IC108 COMDEC PAL18P8 PIN 1 INPUT MESPACE PIN2 INPUT ITSPACE PIN 3 INPUT WRMEMO PIN 4 INPUT WRITS PIN 5 INPUT ENAVME PIN 6 INPUT VMEREQ PIN 7 INPUT VME CYCLE PIN 8 INPUT IRGSPACE PIN 9 INPUT WRITE PIN 11 INPUT ISYSRST PIN 12 OUTPUT WRMEM PIN 13 OUTPUT WRTS PIN 14 OUTPUT IBTOA PIN 15 OUTPUT ENDATAB PIN 16 OUTPUT VMEMEMA PIN 17 OUTPUT ENTSA PIN 18 OUTPUT RDTS PIN 19 OUTPUT IRDMEM 5 3 8 IC109 WRDEC PAL18P8 PIN 1 4 INPUT A01 A04 PIN 5 INPUT IRGSPACE PIN 6 INPUT VMEREQ PIN 7 INPUT VMECYC PIN 8 INPUT ENAVME PIN 9 INPUT WRITE PIN 11 INPUT ISYSRST PIN 12 INPUT PIN 13 OUTPUT WRNPTF PIN 14 OUTPUT WRPTF PIN 15 OUTPUT WRFPTC PIN 16 OUTPUT WRNPTC PIN 17 OUTPUT WRSEG PIN 18 OUTPUT WRMASK PIN 19 OUTPUT WRTHRES 5 3 9 IC106 VME PLS159 PIN 1 INPUT CLK8M PIN2 INPUT PRIORITY OK PIN 3 INPUT IACKIN PIN 4 INPUT DSI PIN 5 INPUT DSO PIN 6 INPU
8. CON sequencer performs arbitration of the various requests for use of the internal data bus It also controls the refresh of the conversion data memory Four requests are made TS store store the time stamp REFIN refresh CCKCONV store conversion data VMEREQ VME cycle 5 2 10 POWER SUPPLIES The 15V supplies for the ADC and non inverting amplifier are provided by a DC DC converter supplied by 12V 5 3 PROGRAMMED DEVICES 5 3 1 DEVICES USED Two types of programmed device are used on the board The first a PAL 18P8 is a programmable array which provides combinatoriallogic The second a PLS 159 is a programmed logic sequencer which is used as a state counter control sequencer and software programmed counter 5 3 2 IC26 CONBCON PLS159 PIN 1 INPUT CLK8M 8MHz clock PIN 2 INPUT EOC Goes low at the end of ADC conversion PIN 3 INPUT ENFPTF Low during the far post trigger phase PIN 4 INPUT ENNPTF Low during the near post trigger phase PIN 5 INPUT ENPTF Low during the pre trigger phase PIN 6 INPUT CLRCS Low when conversion accepted by the memory PIN 7 INPUT ISTSCAN Low initiates a scan and conversion sequence PIN 8 INPUT MC12 Single scan mode inhibits pre trigger mode PIN 9 INPUT ISEGLIM Low indicates end of scan 23 PIN 10 PIN 11 PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 PIN 20 INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT
9. HYTEC ELECTRONICS LTD VTD1612 TRANSIENT RECORDER USER MANUAL ISSUE 3 Hytec Electronics Ltd 5 Cradock Road Reading RG2 0JT U K Tel 44 0 118 9757770 Fax 44 0 118 9757566 Email sales hytec electronics co uk CONTENTS Section Page 1 Product Description 3 2 Specification 4 3 Installation 6 4 Operation 8 5 Circuit Description 20 Apendix A Jumper Settings Appendix B Link Settings Appendix D Use of Analogue Triggers VTD 1612A Transient Digitiser User Manual 1 PRODUCT DESCRIPTION 1 1 DESCRIPTION The 1612A Transient Digitiser is a dual height single width VME slave board which provides the digitisation and storage of analog waveforms present on up to sixteen differential input channels it is an upgraded version of the 1612 with a 10MHz convertor in place of the original 2MHz part Each input is provided with a track hold circuit so that all channels can be simultaneously sampled The sampled voltages are multiplexed into a fast 12 bit ADC which has its own sample hold amplifier The ADC digitises the voltage and stores the resultant binary information in a 128K word RAM A 512K version is available Memory can be allocated according to the number of inputs selected 1 e 1 2 4 8 or 16 inputs use 128K 64K 32K 16K or 8K words per input The RAM is dual ported and provides access for both the ADC and VME bus The board has programmable operating modes Its main modes are 12 TR
10. IGGERED BUFFER MODE Three clock frequencies can be selected for pre trigger near post trigger and far post trigger digitisation rates Memory is equally divided between the pre trigger and post trigger buffers When the module is armed by software command clocking occurs at the pre trigger frequency in the pre trigger buffer A trigger causes digitisation to occur at the near post trigger frequency for a specified number of samples from the start of the post trigger buffer followed by the far post trigger frequency for a second specified number of samples On completion acquisition is halted 13 CONTINUOUS MODE Normally when the full flag interrupts digitisation is inhibited However it is possible to set up a continuous mode wherein digitisation occurs continuously The halffull and full flags can then be used as an indication of where in the memory digitisation has reached so that alternate halves of memory can be read whilst still acquiring data Samples clocked at the pre trigger clock frequency and the whole memory is used as a pre trigger buffer 14 SINGLE SCAN MODE In this mode the pre trigger clock is inhibited When the VTD is triggered the input voltages are sampled and converted the memory address pointer is incremented and the of event interrupt status bit is set It is possible to trigger multiple scans using post trigger counts of greater than one The board can interrupt for one or all of thre
11. T ADDRESS OK PIN 7 INPUT ENABLEVME PIN 8 INPUT INTREQ PIN 9 INPUT SYSRST 25 System reset System or programmed reset Write vector register Write status register Read module status Read MS memory address register Read LS memory address register Read mask register Read status register Memory addressed Time stamp memory addressed Write to memory Write to time stamp VME cycle enabled VME cycle requested VME cycle granted Register addressed VME write cycle System reset Write to memory VME or ADC Write time stamp VME or ADC Data buffer direction counted Enable data onto bus Memory addressed by VME Enable time stamp address Read time stamp Read memory VME address bus Register addressed VME cycle in requested VME cycle in progress VME cycle enabled VME write cycle VME system reset Write far post trigger frequency Write near post trigger frequency Write pre trigger frequency Write far post trigger count Write near post rigger count Write segment channel register Write mask control register Write threshold register 8MHz clock Interrupt priority OK VME interrupt acknowledge Data strobe 1 Data strobe 0 Board addressed correctly VME cycle granted Interrupt request VME system reset PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT VTD 1612A Transient Di
12. TPUT ITRIG Trigger pulse 5 3 13 IC59 FULLNESS DETECTOR 18P8 PIN 1 INPUT CA17 Memory address counter bit 17 PINS 2 7 INPUTS CA16M CA11M Modified address count bits from POSTOFFS PINS 8 9 INPUTS CA10 CA09 Memory address counter bits 10 and 09 PINS 11 12 13 18 INPUTS NOCH8 NOCH1 Number of channels programmed PIN 19 INPUT FLGSTR Clock flags signal from RATECON PIN 16 OUTPUT SETHF Clock half full flag PIN 17 OUTPUT SETFF Clock full flag 5 3 14 IC122 POSTOFFS 18P8 PINS 1 6 INPUTS CA16 CA11 Memory address counter bits 11 16 PINS 7 11 INPUTS 16WS 128WS Sector size PIN 12 INPUT TRISEQB Post trigger PIN 13 INPUT MC12 Supplies pre trigger operation PINS 14 19 OUTPUTS ICA1IM CA16M Modified address counter bits post trigger offset 27 APPENDIX APPENDIX A VTD 1612 JUMPER SETTINGS BASE ADDRESS J12 J16 J12 800000 A23 JUMPER OPEN LOGIC 1 400000 A22 JUMPER CLOSED LOGIC 0 200000 A21 100000 A20 080000 A19 e g for address 900000 insert J12 J14 J15 INTERRUPT ACKNOWLEDGE PRIORITY J17 J19 is JUMPER OPEN LOGIC 1 J19 e g for priority 1 insert J18 J19 INTERRUPT REQUEST J20 J26 IRQ4 JUMPER CLOSED SELECTS IRQX insert only one at a time IRQ1 IRQ2 28 APPENDIX ANALOGUE INPUT VOLTAGE RANGE J1 J5 VOLTAGE RANGE 0 to SV 0 to 10V 0 to 10V 5V 10V Notes 1 JUMPER INSERTED J5 4 J5 1 4 left to right J5 2 3 straight gt bina
13. a memory location has been overwritten by the ADC EH Enable Half Full interrupt The halfway point of the highest memory sector has been reached EE Enable End of event interrupt The near post trigger and far post trigger phase have been completed and the ADC is in the pre trigger phase TI Trigger Internal Trigger from channel 1 amplifier XT Enable external digital trigger via the front panel co axial socket and enables software triggers C Continuous mode Digitisation continues regardless of the status of the Full flag If Full is set memory storage wrap around will occur ARM Digitisation is enabled when set ATO 2 Three bit analog trigger code determines mode of trigger see Appendix D for details of usage These codes are not implemented in early versions of the TRIGGER PLD XC External clock The basic clock rate is derived from the signal applied to the Clock In socket and the internal clock is inhibited The settings of the trigger frequencies 4 5 6 define the frequency division IP Inhibit pre trigger clocking Digitisation will not occur until the board is triggered 13 VTD 1612A Transient Digitiser User Manual XMO 2 bit code reserved for memory paging on future versions of the VTD 1612 ST Software trigger A write Mask and Control transfer with bit 15 will trigger an event Busy will be set until the end of the end of the event 4 5 4 ADC Memory Address Point
14. at the highest clock rate to ensure greatest trigger accuracy the timing monostable can be enabled by making J10 3 1 9 POST TRIGGER MONOSTABLE Jumper J11 is provided for test purposes it is normally left open When made the jumper disables the TRIGSEQB monostable This monostable resets the memory address counter when the board is triggered so that the post trigger buffer commences at its zero address Therefore when the jumper is made conversions are stored in the post trigger buffer commencing at the current address plus the post trigger offset 32 LINK SETTINGS 3 2 1 GENERAL The printed circuit board link settings are shown in Appendix B They are generally factory set and need not be changed for normal operation 3 2 2 DATA LOGIC Link LK1 determines the sense of the ADC data when pins 2 and 3 are linked the ADC provided positive logic Data is complemented when pins 1 and 2 are linked VTD 1612A Transient Digitiser User Manual 32 3 OFFSET ADJUSTMENT POTENTIOMETER VOLTAGE Link LK2 allows either a positive or negative bias voltage to be connected to the front end amplifiers according to which type of amplifier is used Normally OP64 amplifiers are used which require a negative voltage and pins 2 and 3 are connected 32 4 CHANNEL 1 AND 4 ISOLATION Link LK3 isolates sample and hold channels 1 and 4 for test purposes Opening the link across pins 1 and 2 isolates sample hold channel 1 Opening the link across pins 3 and 4 iso
15. cycle Request for VME cycle Clear time stamp request Memory access VME cycle in progress Handshake back to VME request Enable VME access Acknowledge end of memory write Refresh cycle Write time stamp Enable conversion address Write to memory Enable conversion data to bus 8MHz clock Trigger request Far post trigger count overflow 0 Near post trigger count overflow 0 Continuous full flag is ignored Arm clock in pre trigger mode Full flag set High frequency sample clock Low frequency sample clock Clear frequency divider Clock half full and full flags Enable pre trigger frequency Enable near post trigger frequency Enable far post trigger frequency End of triggered event handshake Not used Start channel scan and conversion 8MHz clock Upper threshold level trigger Lower threshold level trigger Logic trigger End of event handshake returned from RATECON MC04 enables logic trigger Trigger mode MC08 Trigger mode 9 Trigger mode MC10 VTD 1612A Transient Digitiser User Manual PIN 12 OUTPUT ICLOG Clear logic trigger PIN 13 OUTPUT EVNTCLK Request time stamp cycle PIN 14 OUTPUT MISDTRI Not used PIN 15 OUTPUT EVNTTRI Event trigger Starts post trigger phase PIN 16 OUTPUT CLOW Clear lower threshold level trigger PIN 17 OUTPUT CLUP Clear upper threshold level trigger PIN 18 OUTPUT BUSY Low when event is in progress post trigger PIN 19 OU
16. d control register are then Bit 10 9 8 Ext Trigger Ch 1 Trigger 0 0 0 No analogue trigger No analogue trigger 0 0 1 Positive slope Negative slope 0 1 0 Negative slope Positive slope 0 1 1 Pos slope neg hysteresis Neg slope pos hysteresis 1 0 0 Neg slope pos hysteresis Pos slope neg hysteresis 1 0 1 Window trigger Window trigger If pins 17 and 36 are reversed then external triggering and channel triggering will have the same phase UPPER AND LOWER TRIGGER LEVELS The positive level is controlled by bits 0 7 The negative leve is controlled by bits 8 15 31 APPENDIX EXAMPLES Threshold register set to 8080 halfway levels Code 01 10V eg mask amp control 1128 Channel 1 10V 5V Busy OV Code 02 10V eg mask amp control 1228 Channel 1 10V 5V Busy OV Code 03 eg mask amp control 1328 10V Channel 1 10V 5V Busy OV 32 APPENDIX Code 04 eg mask amp control 1428 10V AAA ari MS RICH MU Channel 1 RS rs fee 5 Busy OV Code 05 eg mask amp control 1528 10V Channel 1 10V 45V Busy OV NB Also set mask and control bit 7 to arm the module and commence triggering 33
17. d in location 0 of the time stamp memory through 1FFF and back to 0000 and up to TS value 1 If pre trigger clocking is enabled then at the end of the event the full flag is set in additin to the end of event flag to indicate that the upper half of the memory above 2000 has been altered This example did not use interrupt If interrupt is required at the end of the event the mask and control register should originally be set to 0814 If it is required to use the internal clock the mask and control should be be set to 0010 instead of 0810 However the frequency division values should be increased to take into account the increased clock frequency Typically Pre trigger frequency 0006 65KHz Near post 0007 Far post 0008 4 6 2 CONTINUOUS MODE In continuous mode the board continues to sample until disarmed A typical set up is 1 Interrupt Vector FFC9 2 Mask and Control 0031 interrupt full 3 No of channels 009F 16 channels no limit 4 Near post trigger count XXXX don t care 5 Far post trigger count XXXX don t care 6 Pre trigger frequency 0007 32KHz 7 Near post frequency 0007 32KHz 8 Far post frequency 0007 32KHz 9 Upper and lower levels FFFF not used The board will interrupt when the Full flag is set but will continue to scan from zero address again Normally in this mode the Half full interrupt would first be enabled When the board interrupts the Half full status bi
18. de CMRR Amplifier bandwidth Trigger signal Acquisition time Aperture jitter Aperture delay ADC resolution ADC conversion Linearity error Channel error ADC error Drift 37 way D type socket 1 16 analog positive inputs 20 35 analog negative inputs 17 analog trigger positive input 36 analog trigger negative input 18 19 37 Gnd 10V Gains 1 10 may be ordered on a channel by channel basis 40K ohms differential 20K ohms common mode 300V overvoltage for 1 second 100V for linear operation 70db at 100KHz SMHZ small signal As for analog inputs luS to 0 025 for a 10V transition in multichannel mode single channel 625nS to 0 025 InS max 70nS 12 bits 625nS max to hold digitise and store Internal converter 100nS 1 2 LSB 1 2 LSB 1 2 LSB 30 ppm per C max VTD 1612A Transient Digitiser User Manual DIGITAL SIGNALS Trigger input Lemo 00250 socket Negative going TTL pulse 200nS min width Trigger output Lemo 00250 socket Negative going TTL signal Clock in Lemo 00250 socket Negative going TTL signal 10MHz frequency max Clock out Lemo 00250 socket Negative going TTL signal generated by internal clock or Clock In Busy out Lemo 00250 socket Negative going TTL signal generated when a trigger has occurred until the end of event FRONT PANEL INDICATORS Armed LED which illuminates when the input waveforms ar
19. e being digitised commencing at the pre trigger rate Continuous LED which illuminates when Continuous mode is set Trigger LED which illuminates for 200mS when a trigger occurs Full LED which illuminates when the memory is full Half full LED which illuminates when the memory is half full Module address LED which illuminates for 200mS when the module is accessed from the VMEbus Busy LED which indicates the status of the Busy status signal An event is being recorded Error LED which illuminates when the module is addressed and bus timeout occurs BACKPLANE CONNECTORS The board uses the J1 P1 connector of the VMEbus It is equipped with a jumper selectable base address and interrupt priority level It recognises standard 24 bit addressing The memory map of the module is shown below Reserved two words Reset memory address Board descriptor Upper lower trigger threshold Far post trigger frequency Near post trigger frequency Far post trigger clock count Near post trigger clock count No of channels memory allocation ADC memory address pointer MS ADC memory address pointer LS Interrupt status Interrupt vector Time stamp data memory 8K words Conversion data memory 128K words Base address jumper selectable 16 words 2 r S VTD 1612A Transient Digitiser User Manual 3 INSTALLATION 31 JUMPER SETTINGS 3 1 1 GENERAL Install the printed circuit
20. e states a the memory is full completion of post trigger or b the memory is half full or c the end of a triggered event record has been reached Itis possible to read the contents of an addressed memory location via the VME bus whilst the board is digitising This concurrent access mode is permitted once per ADC conversion i e not exceeding a read rate of one megaword per second At the trigger point the current memory address will be recorded in a time stamp buffer Up to 8192 time stamps can be recorded The board can be triggered from an external analog source from channel 1 by an external logic pulse or by software command The clock frequency can be programmed from 1MHz down to 0 01Hz using either an internal or external clock source with a maximum frequency of 8MHz The clock is buffered and is transmitted via a front panel connector Provision is made for connecting Clock Out to Clock In of another module Trigger is also buffered and transmitted as a logic pulse via a connector so that one module can trigger another VTD 1612A Transient Digitiser User Manual 2 SPECIFICATIONS Operating temperature range 0 to 45 ambient Power requirements 5V at 2 5A from the VMEbus 5V STDBY maintains the RAM in the event of power failure SV is generated on board FRONT PANEL CONNECTORS ANALOG INPUTS Connector type Pin allocation Signal Input impedance Input Protection Common mo
21. ecode 1C86 101 103 Base address 1C102 Base address selector J12 J16 Add buffer IC98 100 Interrupt priority IC105 Priority selector J17 19 Power Supplies IC116 Indicator driver IC60 Front Panel skts C01 05 N WN A A A tn A Ur A CA ON CA Vi A RR Q amp RARAN UUU RRR RRR iS tS 21 VTD 1612A Transient Digitiser User Manual 52 OUTLINE 5 2 1 ANALOG SAMPLING The outputs from the sixteen differential amplifiers are sampled and held when the S H bistable is set by CLKHOLD and then multiplexed into the input of the non inverting amplifier which amplifies the signal to be compatible with the full scale input of the ADC The analog signals are initially attennuated by 50 to be compatible with the 5V max signal capability of the sample and hold amplifiers Conversion is initiated by the START signal At the end of conversion the ADC register is strobed to store the conversion data and the CLKCONV signal requests access to the internal tri state data bus When it is granted access the conversion address buffer is gated to address the conversion data memory the output of the ADC data register is enabled and the data gated onto the bus is written to the memory 5 2 2 CONVERSION CONTROL The ADC conversion timing multiplexer scanning and memory addressing are controlled by the conversion control sequencer CONBCON and the conversion address counter On receipt of
22. er LS Address Data 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 X X X X X X X X R 22 21 20 19 18 17 16 Read Memory Address D16 MS Address Data Read Memory Address D16 The memory address counter is a 24 bit address counter The 128K word memory is addressed by bits 00 to 16 If continuous is set bits 17 to 23 give an indication of how many times memory wrap around has occurred The address bits 00 16 are used according to the memory segment allocation No of channels Sector size Memory address bits Segment address bits 16 8K 00 12 13 16 8 16K 00 13 14 16 4 32K 00 14 15 16 2 64K 00 15 16 1 128K 00 16 Note bits 08 15 of the MS data will be set to all 1s The memory address read buffer has a latching arrangement such that data cannot change during a read This has two side effects After initialisation the memory address must be read twice to obtain the current zero value of the address counter After end of event when the address passes from post trigger to the pre trigger buffer the address must be read twice for the first read This proves useful in that it can be checked that the end of post trigger address is reached and then the corresponding address in the pre trigger buffer is pointed to for the second read The memory address read buffer is updated at the end of a channel scan Theref
23. gitiser User Manual WRISTB INTVEN VMEREQ VMECYCLE IACKOUT DTACK BERR IRQ 5 3 10 IC110 DPCON PLS159 PIN 1 PIN2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CLK8M TSSTORE CLKCONV RFRSH VMEREQ CLTS CHIPEN ENEVA VMECYCLE ENABLEVME ENAVME CLRCS CKCNVAD WRTS ENCNVAD WRMEM ENACONV 5 3 11 IC52 RATECON PLS159 PIN 1 PIN2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 12 PIN 13 PIN 14 PIN 15 PIN 16 PIN 17 PIN 18 PIN 19 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CLK8M EVNTTRI FPTCOF NPTCOF MCO5 MC07 FULL HICK LOCK CLRDIV FLGSTR ENPTF ENNPTF ENFPTF EOEVNT ISTSCAN 5 3 12 IC58 TRIGGER PLS159 PIN 1 PIN2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT CLK8M UTHRESH LTHRESH LOGITRIG EOEVNT ENEXTRIG TRIMI TRIM2 TRIM 4 26 Write strobe Interrupt vector enable Request arbitration for internal bus VME cycle in progress Daisy chain 1ACK to next device Generate DTACK Not used Not used 8MHz clock Request for time stamp write cycle Request to write conversion to memory Request for memory refresh
24. icate a sequence of incremented values From initial conditions 0 1FFF Variants of Single Scan mode can be achieved by increasing the Near and Far post trigger count values 19 VTD 1612A Transient Digitiser User Manual 5 CIRCUIT DESCRIPTION 51 GENERAL The circuit is shown in block diagram form in diagram 5 1 The blocks and their related circuit references are shown in the following table 20 VTD 1612A Transient Digitiser User Manual Table 5 1 Circuit References NAME OF BLOCK IC REFERENCE C D PAGE Internal clock XTI Rate control 1C52 Trigger IC58 Trig in IC21 Trig sw IC44 Dual comparator 1C47 48 ULDAC 1C36 LLDAC 1C37 Analog input amplifiers ICI IC16 S H 1 16 IC17 IC20 MUX IC22 24 MUX count 1C27 S H bistable 1C21 Non inverting amp 1C25 ADC 1C28 REG 1C33 34 Conversion control 1C26 Counter 1C29 3 1 32 Post Trigger Offset 1C122 Memory address read buffer 1C66 68 Conversion address buffer 1C62 63 Fullness detector IC59 FPT freq IC77 NPT freq IC78 PT freq IC79 FPT counter IC80 81 NPT counter IC84 85 Refresh clock IC51 104 Conversion data memory IC64 65 Memory address buffer IC75 76 Event counter IC69 70 Time stamp memory IC71 72 TS address buffer IC73 74 Patch RN4 Module status buffer 82 Status register 1C53 89 Mask control reg 1C90 91 Int vector reg 1C96 97 VMEbus control IC106 Selector switch J20 26 Data buffers IC113 114 Arbiter DPCON IC110 Command decode 1C107 109 Address d
25. is allocated as below Full Post Half full Pre Ist Post Pre Ist Post Pre Ist Post Pre Ist mt channel 2 channel 1 channel 4 channel 3 channel 2 channel 1 Base 3FFFE Base 30000 Base 20000 Base 10000 Base 00000 Base 3FFFE Base 30000 Base 20000 Base 10000 Base 00000 For eight channels channels 1 8 there are 8 segments VTD 1612A Transient Digitiser User Manual 10 Full Half full Ist Ist Ist Ist 1st 1st Ist Ist lt w channel 8 channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 Base 3FFFE Base 38000 Base 30000 Base 28000 Base 20000 Base 18000 Base 18000 Base 10000 Base 8000 Base 00000 For sixteen channels channels 1 16 Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre Post Pre VTD 1612A Transient Digitiser User Manual Full Half full uu uu w x w w Nal Na channel 16 channel 15 channel 14 channel 13 channel 12 channel 11 channel 10 channel 9 channel 8 channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 Base 3FFFE Base 3C000 Base 38000 Base 34000
26. lates sample hold channel 4 32 5 MISSED TRIGGER Hardware logic is included for detection of missed triggers However in current versions this has not been implemented in firmware and link LK4 is not used 32 6 ADC AMPLIFIER Link LK5 connects the output of the multiplexer to the input of the ADC non inverting amplifier It is normally made 32 7 HOLD TIMING Link LK6 is normally made by connecting pins 1 and 2 VTD 1612A Transient Digitiser User Manual 4 OPERATION 4 1 MEMORY MAP The conversion data memory occupies a space of 128K words starting at the base address A memory of 8K words resides above this followed by a further 16 words used for control and status registers The memory map is shown below Register Space 16 words Base address 44000 Time Stamp 8K words Memory Base address 40000 Conversion Data 128K words Memory Base address 800000 F80000 4 2 CONVERSION DATA MEMORY For a single channel channel 1 the memory is totally allocated Full la Base 3FFFE Post trigger Buffer 64K Half full Base 20000 Pre trigger 64K Buffer b i 00000 0 15 conversion VTD 1612A Transient Digitiser User Manual For two channels channels 1 and 2 the memory is divided into two segments thus Full Post trigger Buffer Half full Pre trigger Buffer 32K Ist Post trigger 32K Buffer Pre trigger 32K Buffer Ist For four channels channel 1 4 the memory
27. ode 4 5 10 ADDRESS MODIFIER CODES Codes 39 and 3D are used 4 5 11 CONVERSION DATA FORMAT 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Read D16 2 877 ES Write D16 is available for testing the memory Unipolar 10V 0000 1 1 1 1 1 1 1 1 1 1 1 1 5V 00001000000 0 0V 0000000000000000 Bipolar 10V 000001 1 1 1 1 1 1 1 1 1 1 0V 0000000000000000 0 005V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10V 11111000 0 0 00 16 VTD 1612A Transient Digitiser User Manual 4 5 12 TIME STAMP DATA FORMAT 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Read D16 Memory Address up to FFFF Write D16 is available for testing the memory 4 6 MODES OF OPERATION 4 6 1 TRIGGERED BUFFER MODE When armed the board scans the selected input channels digitises the analog values and stores the data in the pre trigger buffer continuously looping within the memory range of the pre trigger buffer A trigger causes the memory address to jump to the start of the post trigger buffer Converted values are then stored in this buffer until the near post and far post counts expire The acquisition is halted with the address pointer set in the pre trigger buffer range An example of the set up for this is 1 Interrupt Vector FFC9 if used 2 Mask and Control external clock 100KHz 0810 3 No of channels segment size 0028 8 channels 4 Near post trigger count 1s complement of 0C00 5 Far post trigger count 1
28. ore the appropriate segment address bits are zero and the address points to the next location to be updated 4 5 5 NUMBER OF CHANNELS SEGMENT SIZE 15 14 12 10 09 08 07 06 05 04 03 02 01 00 Write D16 S3 S2 SI SO C3 Ci CO Code1 Sample channel 1 C1 Code 2 Sample channel 1 and 2 C2 Code 4 Sample channel 1 4 C3 Code8 Sample channel 1 8 Code Sample all 16 channels 14 50 51 52 53 1 2 Code 3 4 5 8 D VTD 1612A Transient Digitiser User Manual 4K pre trigger buffer 8K pre trigger buffer 16K pre trigger buffer 32K pre trigger buffer 64K pre trigger buffer Disable the pre trigger buffer limit when armed digitisation will continue until Full is set or until disarmed if Continuous is set Valid combinations for no of channels segment size 1F 28 34 42 51 16 channels 4K pre trigger buffer 4K post trigger buffer 8 channels 8K pre trigger buffer 8K post trigger buffer 4 channels 16K pre trigger buffer 16K post trigger buffer 2 channel s 32K pre trigger buffer 32K post trigger buffer 1 channel 64K pre trigger buffer 64K post trigger buffer 8F 9F 16 channels 8K per channel pre trigger buffer 88 A8 8 channels 16K per channel pre trigger buffer 84 B4 4 channels 32K per channel pre trigger buffer 82 C2 2 channels 64K per channel pre trigger buffer 81 D1 1 channel 128K per channel pre trigger buffer
29. ry J5 1 2 3 4 2s complement 1 INTERNAL CLOCK J6 J7 J6 closed 16MHz for future use leave as set J7 closed 8MHz normal connection SEQUENCER CLOCK PHASE J8 J9 J8 closed in phase select on test leave as set J9 closed 1800 shift select on test TRIGGER TIMING MONOSTABLE J10 Normally open POST TRIGGER MONOSTABLE J11 Normally open 29 APPENDIX APPENDIX B VTD 1612 LINK SETTINGS LINK LKI LK2 LK3 LK4 LK5 LK6 SETTING 2 3 ADC data positive logic 1 2 complements 2 3 Connects 12V to OP64 offset adjust wiper 1 2 Normally made isolates S H 1 3 4 Normally made isolates S H 4 1 2 Missed trigger not used made Connects MUX to ADC amplifier 1 2 Normally made hold on CLKHOLD 30 APPENDIX APPENDIX D VTD 1612 USE OF ANALOGUE TRIGGER PRE REQUISITES 1 IC58 should be TRIGA V2 2 Inverter IC51 1 should be by passed 3 Comparators IC47 and IC48 should have 68K resistors fitted between pins 2 and 7 4 Issue 3 boards should be to modification status 4 TRIGGER PHASE The trigger amplifier IC40 is connected such that its positive input is connected to pin 36 and its negative input to pin 17 This is the opposite phase from channels 1 to 16 odd pins even pins Therefore this phase difference exists between external trigger and channel trigger if the connection sense is maintained The analogue trigger code of bits 8 10 of the mask an
30. s and written to the time stamp memory The time stamp memory can be read via the VMEbus using the relevant address gated via the VME address buffer 22 VTD 1612A Transient Digitiser User Manual 5 2 6 INTERRUPTS The interrupt status register comprises the Full Half full and End of event flags These are And gated with corresponding mask bits in the control and mask status register The resultant signals are Or gated to form a single interrupt request This is connected to one of the lines 1 7 as determined by the interrupt request selected switch When the master responds with IACK at the correct priority level the interrupt vector enable signal gates the interrupt vector stored in the interrupt vector register onto the data bus The interrupt is reset by clearing the appropriate interrupt status bit which can be determined by reading the status Resetting the interrupt mask bits would also clear the interrupt request 5 2 7 VMEBUS CONTROL Access to from the VMEbus is controlled by this sequencer It requests access to the internal data bus by hand shaking with the arbiter sequencer When the access is granted the appropriate VMEbus address is decoded and the selected register clocked or enabled onto the bus 5 2 8 VMEBUS ADDRESS DECODE The VME address is compared with the base address jumper setting If there is a match the address and command decoders are enabled for the duration of the VME cycle 5 2 9 ARBITRATION The DP
31. s complement of 0100 6 Pre trigger frequency 0000 100KHz 7 Near post trigger frequency 0001 50KHz 8 Far post trigger frequency 0002 25KHz 9 Upper and lower levels not used FFFF The board is armed by adding 80 to mask and control The board will accept an external trigger in the front panel coaxial socket or by software command add 8000 to mask and control The pre trigger clock frequency is that of the external clock Near post frequency will be half of this and far post half again When the board is triggered the Busy LED will be illuminated Half Full and then Full will be illuminated and Busy extinguished in that order If the memory address is read twice the first read will give 2D00 and the second read DOO indicating that scanning has halted with the address set in the pre trigger buffer The first location ofthe time stamp memory will hold the memory address pointed to when trigger caused a jump to the post trigger buffer Shown diagramatically 17 VTD 1612A Transient Digitiser User Manual For channel 1 PRE TRIGGER TRIGGER POST TRIGGER END OF EVENT address 2D00 Post trigger 8K buffer address DOO Pre trigger buffer rotate 0000 store address in T S jump At the end of the event the post trigger buffer will hold the data in sequence from the trigger point and the pre trigger buffer will hold the pre trigger data with the oldest recorded data starting at the location store
32. t would be cleared and disabled and the Full interrupt enabled When the board interrupts again the Full status bit would be cleared and disabled and the Half full interrupt re enabled After the Half full interrupt the lower buffer segment of memory would be read while accumulating data in the upper buffer segment Similarly after interrupt the upper buffer segment would be read 18 VTD 1612A Transient Digitiser User Manual 4 6 3 SINGLE SCAN MODE In this mode the board samples at the trigger rate An example of a set up is 1 Interrupt Vector FFC9 2 Mask and Control 1014 single mode 3 No of channels 009F 4 Near post trigger count 0001 ones complement FFFE 5 Far post trigger count 0000 ones complement FFFF 6 Pre trigger frequency 0008 don t care 7 Near post frequency 0008 don t care 8 Far post frequency 0008 don t care 9 Upper and lower levels FFFF not used The board is armed by adding 80 to the mask and control register Each trigger will causes values to be stored in successive locations of the memory until it is full E Last trig 2nd trig N Ist trig loc IFFF loc IFFF Channel 1 Time Segment Stamp Memory nee lt 2nd trig 1000 Ist trig 2 3rd trigger 1 2nd trigger O Ist trigger loco Interrupt will occur at the end of each triggered event The single scan operation can be checked by reading the time stamp memory which will ind
33. trigger circuit and the pre trigger phase is entered once again The sampling rate may be derived from an internal oscillator or from an externally supplied pulse train determined by MC11 and gate IC30 5 2 4 ADDRESS COUNTER The conversion address counter provides the scan number address and memory segment number address combined to address the conversion address memory and if continuous mode is programmed counts the complete number of memory scans in bits 18 to 24 Bits 1 to 17 address the memory When the board is triggered the post trigger offset PAL circuit introduces an offset equal to half the address space into the memory address so that data is acquired into the upper half segment of the memory The fullness detector provides Half full and Full signals according to the state of the memory address Half full occurs when the half segment boundary is crossed and Full is set when the top most location has been addressed in the continuous mode The memory address is read out onto the internal bus and thence to the VMEbus by enabling the memory address read buffer 5 2 5 TIME STAMP Each time the board is triggered the current memory address is stored at the location in the time stamp memory addressed by the eventcounter Atthe end of the event this counteris incremented to point at the next location When a time stamp cycle is requested the arbiter grants control of the data bus the LS memory address is read onto the data bu
Download Pdf Manuals
Related Search