V850ES/Jx3-L Sample Program (Watchdog Timer 2 (WDT2)) Reset
Contents
1. interrupt vord Et Ant rmtpOUt void unsigned int loop wait 10 ms wait to eliminate chattering for loop counter for loop wait 0 loop wait lt LIMIT 10ms WAIT loop wait 2 mop D3 if PO amp 0x08 0x00 SW ON TMOCE 0 TMOCMPO VAL_55ms_CNT TMOEQIFO 0 TMOCE 1 while PO amp 0x08 0x00 Lt TMOEQLFO T WDTE OxAC PCM 3 1 TMOEOIFO 0 SW OFF E WDTE OxAC TMOCE 0 TMOCMPO VAL 120ms CNT TMOCE 1 PIFO 0 return yos Js Identifies that SW1 has been pressed after the wait Stops the count operation Sets the LED1 blinking cycle to 55 ms Clears the TMMO compare match interrupt request Starts the count operation Is there an interrupt request signal Clears the WDT2 count Inverts the LED1 output Clears the TMMO compare match interrupt request Clears the WDT2 counter Stops the count operation Sets the LED1 blinking cycle to 120 ms Starts the count operation Failsafe Multiple requests Cleared Processing moves to reti depending on the interrupt modifier 32 Application Note U19543EJ1VOAN 7 SI ul ui 2 uri ui ud T Taj 5 87 Teh 2 B For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kaw2. 0x01F800 for products with 128 KB internal ROM Difference from the default link directive file additional code EH For MINICUBE2 MROMSEG LOAD R V xO3F800K MonitorROM SPBOGBETS A MonitorROM A reserved area for MINICUBE2 is secured i 24 Application Note U19543EJ1VOAN APPENDIX A PROGRAM LIST SIDATA LOAD RW VOx3ffb000 tidata byte SPROGBITS tibss byte SNOBITS tidata word SPROGBITS tibss word SNOBITS tidata SPROGBITS Llbs8s SNOBITS sidata SPROGBITS Sibss s SNOBITS DATA LOAD RW V0x3ffb100 data SPROGBITS sdata SPROGBITS sbss s SNOBITS bss SNOBITS For MINICUBE2 MRAMSEG LOAD RW VOxO3FEFEFFO AW AW AW AW AW AW AW AW AW AWG AWG AW MonitorRAM SNOBITS AW MonitorRAM I tp TEXT STP SYMBOL gp DATA GP SYMBOL amp tp TEXT DATA ep DATA SEP SYMBOL tidata byte tibss byte tidata word tibss word tidata tibss sidata Sibss data sdata Sbss bss Difference from the default link directive file additional code A reserved area for MINICUBE2 is secured Application Note U19543EJ1VOAN 25 APPENDIX A PROGRAM LIST main c js ie ya T ya ya js n ya z ja ya T ya P ya s T ys T i T ya ya P T n ya m ya 7s 7 ya ya ya T ya ya ji j ya 26 NEC Electronics V850ES Jx3 L m
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5. WDCS22 WDCS21 WDCS20 WDM21 WDM20 Selection of watchdog timer 2 operation mode 00 4 Non maskable interrupt request mode WDT2 generates the INTWDT2 signal Reset mode WDT2 generates the WDT2RES signal WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selection of watchdog timer 2 clock Ls em ios or or LL eese Note Either O or 1 Remark e The red values in the table indicate the values set in the sample program WDTM2 0x5B e fxr 32 768 kHz Application Note U19543EJ1VOAN 15 CHAPTER 4 SETTING REGISTERS 41 2 Watchdog timer enable register WDTE Writing OxAC to the WDTE register clears the counter of watchdog timer 2 and causes the counter to start counting up again This register can be read and written in 8 bit units Writing WDTE using a 1 bit memory manipulation instruction will cause an overflow to occur Reset sets this register to Ox9A Figure 4 2 Format of WDTE Register Watchdog timer enable register WDTE Address OxFFFFF6D1 7 Cautions 1 Writing a value other than OxAC to the WDTE register will trigger forcible generation of the overflow signal To deliberately trigger generation of the overflow signal write a value other than OxAC to the WDTE register once or write to the WDTM2 register twice Note however that if operation of watchdog timer 2 has been stopped writing a value other than OxAC to the WDTE register once or writing to the WDTM2 register twice will not trigger generation of the overflow
6. 0x800 Oxff Securing an interrupt Wector for debugging section DBG Space 4 Ukir Securing a reception interrupt vector for serial communication section INTCBOR Space 4 Oxff Securing a 16 byte space as the monitor RAM section section MonitorRAM bss lcomm monitorramsym 16 4 Application Note U19543EJ1VOAN 23 APPENDIX A PROGRAM LIST AppNote INT dir Sample link directive file not use RTOS use internal memory only Copyright C NEC Electronics Corporation 2002 All rights reserved by NEC Electronics Corporation This is a sample file NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of this file Generated PM V6 31 9 Jul 2007 Sample Version E1 00b 12 Jun 2002 Device UPD70F3738 C Program Files NEC Electronics i Tools DEV DF3738 800 Internal RAM Ox3t b000 Ox3ftetff NOTICE Allocation of SCONST CONST and TEXT depends on the user program If interrupt handler s are specified in the user program then the interrupt handler s are allocated from address 0 and SCONST CONST and TEXT are allocated after the interrupt handler s SCONST ILOAD R ScConst SPROGBITS 2A sconst rs CONST ILOAD R const SPROGBITS PA const 13 TEXT ILOAD RX pro epi runtime SPROGBITS AX pro epi runtime text SPROGBITS AX text
7. overflow of watchdog timer 2 is likely to cause the CPU to enter an infinite processing loop lt is therefore recommended to set watchdog timer 2 to the reset mode by setting the WDM21 bit to 1 so that the CPU is reset when WDT2 overflows If you choose to set watchdog timer 2 to non maskable interrupt request mode by setting the WDM21 bit to 0 and the WDM20 bit to 1 however be sure to stop the system after the system error processing has been completed by the INTWDT2 interrupt servicing routine The system cannot be returned to the main processing routine by using the RETI instruction after the servicing of a non maskable interrupt generated by the INTWDT2 signal has finished To return the system to the main processing routine following the servicing of an INTWDT2 interrupt execute the software reset processing shown below Note that in this software reset processing registers that can be set only once following the release of reset such as the WDTM2 register cannot be set again These registers must be initialized by executing a hardware reset by means such as inputting a signal to the reset pin INTWDT2 is generated Software reset processing address set to FEPC Value that sets NP bit to 1 and EP bit to O set to FEPSW INTWDT2 servicing V routine RETI RETI executed 10 times FEPC EIPC FEPSW and EIPSW settings required V Initialization processing Software reset processing routine Note A value that sets the NP bit to O the E
8. signal 3 The value read from the WDTE register is 0x9A which differs from the value written OxAC 16 Application Note U19543EJ1VOAN CHAPTER 4 SETTING REGISTERS e Using the detection of a watchdog timer 2 overflow as a trigger to generate a reset Same contents as sample program e Setup procedure Set WDTM2 to Ox5B in the program example this sets reset mode and an operating clock of 212 fxr 125 ms Set WDTE to OxAC before the overflow detection time elapses clearing the watchdog timer 2 count value to stop the occurrence of a reset If the watchdog timer 2 count value is not cleared before the overflow detection time elapses a reset will occur In the program example the operating clock is set to 212 fxr so the overflow detection time of watchdog timer 2 is 125 ms e Program example same contents as sample program define VAL 120ms CNT 4688 Cycle in which WDT2 count is cleared 120 ms 9 Section of initialization processing 1 l l Initialization processing for other than WDT2 is omitted here l H _ 4 Using detection of WDT2 overflow as a reset trigger WDIM2 0x55 Starts watchdog timer 2 operation 2 epe Section of main processing WDTE Clears WDT2 count m Sa Application Note U19543EJ1VOAN 17 CHAPTER 4 SETTING REGISTERS e Using the detection of a watchdog timer 2 overflow as a trigger to generate an interrupt The
9. 6 554 ms with the option byte Application Note U19543EJ1VOAN 11 CHAPTER 3 SOFTWARE e Interrupt servicing flow INTPO 10 ms wait No TMM operation disabled TMOCE 0 TMM compare register set to 55 ms TMOCMPO 55 ms TMM compare match interrupt reguest cleared TMOEQIFO 0 TMM operation enabled TMOCE 1 No Yes WDT2 cleared TMM operation disabled TMOCE 0 TMM compare register set to 120 ms TMOCMPO 120 ms TMM operation enabled TMOCE 1 INTPO interrupt reguest cleared PIFO 0 RETI Application Note 12 TMM 55 ms No TMOEQIFO 1 WDT2 cleared LED1 output inverted TMM compare match interrupt request cleared TMOEQIFO 0 U19543EJ1VOAN CHAPTER 3 SOFTWARE Q Column Contents of the startup routine The startup routine is a routine that is executed before executing the main function after reset of the V850 is released Basically the startup routine executes initialization so that the program written in C language can start operating Specifically the following are performed e Securing the argument area of the main function e Securing the stack area e Setting the RESET handler when reset is issued e Setting the text pointer tp e Setting the global pointer gp e Setting the stack pointer sp e Setting the element pointer ep e Setting mask values to the mask registers r20 and r21 e Clearing the sbss and bss areas to 0 e Setting
10. Application Note V850ES Jx3 L NEC Sample Program Watchdog Timer 2 WDT2 Reset Generated by Infinite Loop Detection This document summarizes the operations of the sample program and describes how to use the sample program and how to set and use watchdog timer 2 In the sample program an interrupt is generated by detecting the falling edge of the switch input If no WDT2 overflow occurs LED1 blinks in a cycle of approximately 55 ms while SW1 is turned on After SW1 is turned off LED1 blinks in a cycle of approximately 120 ms If a WDT2 overflow occurs a reset signal is generated by WDT2 After the reset is released LED2 is turned on and LED1 blinks in a cycle of approximately 120 ms Target devices V850ES JF3 L microcontroller V850ES JG3 L microcontroller Document No U19543EJ1VOANOO Date Published February 2009 N NEC Electronics Corporation 2008 Printed in Japan CONTENTS CHAPTER 1 OVERVIEW am Oeo ce count aa 3 T1 Initial Setting Se oca en cake neds eere vested edle vete etw eU v EHI 4 1 2 Operation of Watchdog Timer 2 WDTA Woo Woo 5 135 Enabling Interrupts x atte oc EE teo NA ENEE 5 job MA EOO exitu Ae E E O a E R oo tunes Mao AA 5 1 5 Interr pt Servicing 545 exotic pee ROO ese e ANN NN 6 CHAPTER 2 CIRCUIT DIAGRAM Koi ana 7 2 NE ET BIYE GTA cz e UN 7 2 2 Peripheral Hard Wara RR DN Una Bana 7 CHAPTER 3 SOFTWARE see ee ama 8 cu MEE SCONMTQUIPATION sex co es aan Ed 8 3 2 On Chip Peripheral Function
11. Chip Microcontroller Hardware Users Manual e V850ES JF3 L 32 bit Single Chip Microcontroller Hardware Users Manual See the following users manuals for details of extended descriptions in C and assembly languages e CA850 C Compiler Package C Language Users Manual e CA850 C Compiler Package Assembly Language User s Manual 14 Application Note U19543EJ1VOAN CHAPTER 4 SETTING REGISTERS 4 1 Settings of Watchdog Timer 2 WDT2 Watchdog timer 2 operates in the following two modes e A mode in which WDT2 is used as a reset trigger e A mode in which WDT2 is used as an interrupt trigger Watchdog timer 2 is mainly controlled by the following two registers e Watchdog timer mode register 2 WDTM2 e Watchdog timer enable register WDTE 411 Watchdog timer mode register 2 WDTM2 Watchdog timer mode register 2 WDTMO2 is used to set the overflow time and operating clock of watchdog timer 2 WDTM2 can be read and written in 8 bit units This register can be read any number of times but it can be written only once following reset release Reset sets this register to 0x67 Caution Accessing the WDTM2 register is prohibited in the following statuses e When the CPU is operating on the subclock and main clock oscillation is stopped e When the CPU is operating on the internal oscillation clock Figure 4 1 Format of WDTM2 Register Watchdog timer mode register 2 WDTM2 Address OxFFFF6DO 7 6 5 4 3 2 1 0 L8 WDM21 WDM20 WDCS24 WDCS23
12. P bit to O and the ID bit to 1 is set to FEPSW A value that sets the NP bit to O the EP bit to O and the ID bit to 1 is set to EIPSW 18 Application Note U19543EJ1VOAN e Example of program CHAPTER 4 SETTING REGISTERS P KKK K K K K K K ck k ck k k k ck ck k ck kCk Ck Ck Ck k ck ck ck k ck ck k k k ck ck KKK KKK KK KH 4 Interrupt initialization processing PK KKK K K K K K k K A k k AAA A Z kCk K Ck K k Z K ck Z Z ck k k ck ck ck ck ck KKK KK KKH global ani tint sand al ee mov ldsr mov kost reti Tni C Loop mov Last Tdsr mov dsr ldsr mov reti initloop2 sub bz initend initloop1 r6 rO 2 Oka r6 re 3 0x20 r6 66 5 r6 1 Init logo r6 2 r6 0 0x0b r6 1216 intend Sets the processing routine address Set LO FEPC NPSI EP20 Set to FEPSW Processing restored from NMI and returned to initloop1 PSW NP set to 0 by next RETI instruction Set to FEPSW Set to EIPSW Sets processing routine address 2 set to FERC Set co ETEC Count initial value 10 times Loop count 1 End of interrupt initialization Application Note U19543EJ1VOAN 19 CHAPTER 4 SETTING REGISTERS 4 2 Checking Detection of WDT2 Reset When a WDT2 reset occurs the WDT2RF bit of the reset source flag register RESF is set On the other hand when a reset is generated by an input to the RESET pin the WDT2RF bit is cleared Therefore by checking the WDT2HEF bit after the reset is relea
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14. ate the bits to be checked in the sample program Clearing the reset source flag As mentioned in Note 2 on the previous page there are cases when the reset source flag has to be cleared after checking the reset source In this sample program however the reset source flag does not have to be cleared because only the watchdog timer 2 WDT2 is used 20 Application Note U19543EJ1VOAN CHAPTER 5 RELATED DOCUMENTS Application Note U19543EJ1VOAN 21 APPENDIX A PROGRAM LIST The V850ES Jx3 L microcontroller source program is shown below as a program list example History NEC Electronics V850ES Jx3 L microcontroller ZOUO Ldbg Released Overview 22 This sample program sets the option byte section byte byte byte byte byte byte 0b00000101 0b00000000 0b00000000 0b00000000 0b00000000 0b00000000 YOPTION BYTES 0x7a 0x7b 0x7c 5 MHz Sets the oscillation stabilization time to 6 551 ms i 0x7d 0x00 must be set to addresses 0x7b to Ox7f 0x7e 0x7tf Application Note U19543EJ1VOAN APPENDIX A PROGRAM LIST minicube2 s K NEC Electronics V850ES Jx3 L microcontroller History 2008 11 Released Overview This sample program secures the resources required when using MINICUBE2 Example of using MINICUBE2 via CSIBO S ee re Ce 8 EN E 3 a ee Securing a 2 KB space as the monitor ROM section Section MonitorROM const space
15. ck frequency setting of WDT2 setting of the I O ports and external interrupt pins setting of a TMM count clock setting of interrupts and ROMization processing are performed in the initial settings After initial setup is complete LED1 blinks about every 120 ms and interrupts are generated and serviced upon detection of the falling edge of the switch input SW1 If no WDT2 overflow occurs during interrupt servicing LED1 blinks about every 55 ms while SW1 is turned on When SWI is turned off LED1 blinks about every 120 ms If a WDT2 overflow occurs during interrupt servicing watchdog timer 2 generates a reset signal After the reset is released LED2 turns on and LED1 blinks about every 120 ms The details are described in the state transition diagram shown below Application Note U19543EJ1VOAN 9 CHAPTER 3 SOFTWARE Non WDT2 reset WDT2 reset Referencing the option byte e Referencing the oscillation stabilization time after releasing reset Settings of on chip peripheral functions e Setting a bus wait for on chip peripheral I O registers e Setting on chip debugging to normal operation mode e Stopping the internal oscillator e Setting watchdog timer 2 to reset mode e Setting the subclock and internal system clock and setting the PLL mode Pin settings e Setting unused pins e Setting the external interrupt pins switch input e Setting the output pins LED control e Both LED1 and LED are turned off e LED2 is turned o
16. f such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customers eguipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC
17. icrocontroller History 2008 11 Released Overview This sample program presents an example of using the watchdog timer 2 WDT2 The WDT2 overflow time is set to 125 ms and an internal reset signal WDT2RES is generated when an overflow occurs After initial setup is complete interrupts are generated and serviced upon detection of the falling edge of the switch input While the switch is being pressed LED1 blinks in a cycle of 55 ms and the count of WDT2 is cleared When a reset is generated by WDT2 the initial settings specify that LED2 turns on Among the peripheral functions that are stopped after reset is released those that are not used in this sample program are not set lt Main setting contents gt e Using pragma directives to enable setting the interrupt handler and describing peripheral I O register names e Defining a wait adjustment value of 10 ms for chattering e Defining the LED1 blinking time to be set to TMMO 120 ms 55 ms e Performing prototype definitions e Setting a bus wait for on chip peripheral I O registers starting the WDT2 operation and setting the clock e Initializing unused ports e Initializing external interrupt ports falling edge and LED output ports e The TMMO compare match interrupt request flag is monitored and when an interrupt request occurs the WDT2 count is cleared the output of LED1 is inverted and the TMMO compare match interrupt request flag is cleared Interrup
18. ling edge of the INTPO pin caused by switch input In interrupt servicing the LED1 blinking cycle is changed by confirming that the switch is on after about 10 ms have elapsed after the falling edge of the INTPO pin was detected The switch being off after about 10 ms have elapsed after the falling edge of the INTPO pin was detected is identified as chattering noise and the LED1 blinking cycle is not changed lt Input gt LED1 LED2 V850ES Jx3 L microcontroller The reset source is confirmed RESF 0x00 LED1 blinks 120 ms LED turns off A switch input interrupt occurs LED1 blinks 55 ms A reset occurs triggered by a WDT2 overflow The reset source is confirmed RESF 0x10 LED2 turns on LED1 blinks 120 ms Caution See each product user s manual V850ES Jx3 L for cautions when using the device Column What is chattering Chattering is a phenomenon that an electric signal alternates between being on and off when a connection flip flops mechanically immediately after a switch is switched 6 Application Note U19543EJ1VOAN CHAPTER 2 CIRCUIT DIAGRAM This chapter describes a circuit diagram and the peripheral hardware to be used in this sample program 21 Circuit Diagram The circuit diagram is shown below Vpp INTPO P03 V850ES Jx3 L microcontroller Cautions 1 Connect the EVpp AVrero and AVREF1 pins directly to Voo 2 Connect the EVss and AVss pins direct
19. ly to GND Connect the FLMDO pin to GND in normal mode Connect REGC to GND via a capacitor recommended value 4 7 LF Leave all unused ports open because they will be handled as output ports 2 2 Peripheral Hardware The peripheral hardware to be used is shown below 1 Switch SW1 This switch is used as an interrupt input to control the lighting of LED1 2 LEDs LED1 LED2 LED1 is used as outputs corresponding to switch inputs When a reset signal is generated by watchdog timer 2 LED2 turns on following reset release Application Note U19543EJ1VOAN CHAPTER 3 SOFTWARE This chapter describes the file configuration of the compressed files to be downloaded on chip peripheral functions of the microcontroller to be used and the initial settings and an operation overview of the sample program A flowchart is also shown 31 File Configuration The following table shows the file configuration of the compressed files to be downloaded File Name Tree Structure Description Compressed zip Files Included criE s Startup routine file AppNote WDT2 dir Link directive file AppNote WDT2 prj Project file for integrated development environment PM AppNote WDT2 prw Workspace file for integrated development environment PM C language source file including descriptions of hardware initialization processing and main processing of microcontroller minicube2 s Source file for reserving area for MINICUBE2 o
20. n function Static void f init port func void J Port alternate function initialization function Static void init int tmm void TMMO initialization function Application Note U19543EJ1VOAN n s n a ou Sah sh ur 27 APPENDIX A PROGRAM LIST A x xkkkkkkkkkkkkkk kk kkkkkk kkkk k k kkkkk Main module LRERREERREERERRE RE RE RE RRR KKR RK EK KR KK void main void f init Executes initialization m BE es Enables interrupts T while 1 Main loop infinite loop Kz if TMOEQIFO Is there an INTTMOEQO interrupt request signal WDTE O0xAC Clears the WDT2 count 2 PCM 3 s Inverts the LED1 output x TMOEQIFO 0 Clears the TMMO compare match interrupt request return Porty l Lg ob a n Ol NS a o de Initialization module E TUS a ED E za UC CET ELE J static void f init void Kanit elk bus wdt2 tr Sets a bus wait for on chip peripheral I O registers stops WDT2 and sets the clock f inrt portcrunc s Sets the port alternate function T LI rnt dmt tmm Sets the TMMO timer 2 return 8 Application Note U19543EJ1VOAN APPENDIX A PROGRAM LIST aa ee E aU mn M TEN Initializing clock bus wait WDT2 static void init clk bus wdt2 void VSWC 0x01 Sets a bus wait for on chi
21. n when a reset triggered by WDT2 occurs Setting timer M e Selecting fxx 512 as the count clock e Setting the TMM count e Masking interrupts from timer M e Enabling operation of TMM Enabling interrupts Interrupt input is awaited No interrupt LED1 blinks every 120 ms Infinite loop Interrupt servicing is terminated when switch input turns off The falling edge of INTPO n is detected 10 ms chattering is detected INTPO pin High level The blinking cycle is changed An on is LED1 is blinking in a koa cycle of 55 ms An interrupt is generated by switch input 10 Application Note U19543EJ1VOAN CHAPTER 3 SOFTWARE 3 4 Flowchart A flowchart for the sample program is shown below e Main processing flow The option byte is referenced Startup routine processing Startup using a sample The clock bus waits and watchdog timer are initialized Unused ports are initialized The ports used including interrupts Initialization are initialized Timer M is initialized Interrupts enabled El Enabling interrupts TMM 120 ms TMOEQIFO 1 YES WDT2 is cleared The LED1 output is inverted The TMM compare match interrupt request is cleared TMOEQIFO 0 Note The option byte is automatically referenced by the microcontroller after reset is released In this sample program the oscillation stabilization time after releasing reset is set to
22. p peripheral I O registers Specifies normal operation mode for OCDM ROTOP 13 Stops the internal oscillator x5B Starts the operation of watchdog timer 2 E O HJ S O I Sets not to divide the clock Sets the use of the subclock pragma asm SED r0 PRCMD st b ru PCC pragma endasm PLLCTL 0x03 Sets to PLL mode return Application Note U19543EJ1VOAN ira oy E rd m ind APPENDIX A PROGRAM LIST CEN ACUMEN NE E SR RE Setting the port alternate function n S EN EE E eee ey ee ee eee Lc static void f init port func void PO 0x00 Sets P02 to P06 to output low level PMO Dx8B Connects P03 to an input latch m PMCO 0x08 Sets P03 to INTPO input as P1 0x00 Sets P10 and Pll to output low level PM1 P3 Sets to output low level PM3 uds With V850ES JF3 L P30 to P35 P38 and P39 are set 1 0 To use P4 as CSIBO when using MINICUBE2 E P4 is not initialized as an unused pin QB V850ESJG3L TB P4 0x00 Sets P40 to P42 to output low level M PM4 OxP3 PMC4 0x00 endif P5 0x00 Sets P50 to P55 to output low level m PM5 Nor PMC5 0x00 P70 and P711 to output low level Sets y With V850ES JF3 L these are not set because the registers do not With V850ES JF3 L P70 to P77 are set exist P9 0x0000 Sets P90 to P915 to output low level PM9 PMC9 Wi
23. pplication Note U19543EJ1VOAN CHAPTER 1 OVERVIEW This sample program describes the usage of watchdog timer 2 WDT2 The overflow time of WDT2 is specified as 125 ms based on the subclock When an overflow occurs an internal reset signal WDT2RES is generated After initial setup is complete an interrupt is generated and serviced when the falling edge of the switch input is detected LED1 blinks and the WDT2 counter is cleared in a cycle of 55 ms while the switch is being pressed When a reset is generated by WDT2 the initial settings specify that LED2 turns on The settings for peripheral functions that remain stopped after reset is released and that are not used in this sample program have not been specified The main software operations are shown below WDT2 reset occurs Non WDT2 reset occurs 1 1 Initial Settings Clocks Bus waits 1 2 Operation of Watchdog Timer 2 WDT2 Setting up ports and alternate functions LED2 turns on LED2 turns off 1 3 Enabling Interrupts 1 4 Main Loop 1 5 Interrupt Servicing Application Note U19543EJ1VOAN 3 CHAPTER 1 OVERVIEW 11 Initial Settings lt Referencing option byte gt e Referencing the oscillation stabilization time after releasing reset Settings of on chip peripheral functions e Setting wait operations wait 1 gt for bus access to on chip peripheral I O registers e Setting on chip debug mode normal operation mode e Stopping the internal oscilla
24. pt b s Source file for setting option byte Notes 1 This is the startup file copied when Copy sample for use C is selected when Specify startup file selected when creating a new workspace lf the default installation path is used the startup file will be a copy of C Program Files NEC Electronics ToolsiPM Version useaNib850N 32 crtE s 2 This is the link directive file automatically generated when Copy sample for use C Memory usage Internal memory only 1 is checked when Specify link directive file is selected when creating a new workspace and to which a segment for MINICUBE2 is added If the default installation path is used C Program Files NEC Electronics Tools PM Version usea bin w_data V850_i dat is used as the reference file is selected and Remark Bi Only the source file is included The files to be used with integrated development environment PM are included 8 Application Note U19543EJ1VOAN CHAPTER 3 SOFTWARE 3 2 On Chip Peripheral Functions Used The following on chip peripheral functions of the microcontroller are used in this sample program e Watchdog timer 2 used to generate an overflow WDT2 e 16 bit interval timer M used to generate the LED blinking cycle TMM e External interrupt input for switch input INTPO SW1 e Output ports for lighting LEDs PCM2 LED2 PCM3 LED1 3 3 Initial Settings and Operation Overview In this sample program the selection of the clo
25. s Used ooooo oooWoWoom XXX 9 3 3 Initial Settings and Operation Overview 2 ee ee een 9 SR MEL o cai ne AE MEI AAA 11 3 5 Differences Between V850ES JG3 L and V850ES JF3 L 13 26 SOC Dod ipai ete ac e e o m pa NS UR 13 CHAPTER 4 SETTING REGISTERS eere aan aa 14 4 1 Settings of Watchdog Timer 2 WDT2 ssseeeeeeeeee 15 4 2 Checking Detection of WDT2 Reset WWW WWW 20 CHAPTER 5 RELATED DOCUMENTS ena 21 APPENDIX A PROGRAM LIST an 22 e The information in this document is current as of November 2008 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use o
26. sed it is possible to ascertain whether the reset source was an WDT2 reset or an input to the RESET pin 4 2 1 Reset source flag register RESF The RESF register stores information on which reset signal the reset signal from which source generated a reset This register can be read or written in 8 bit or 1 bit units Note however that the RESF register can only be written using a combination of specific seguences A reset generated by an input to the RESET pin sets this register to 0x00 A reset generated by any other source such as watchdog timer 2 WDT2 the low voltage detector LVI or the clock monitor CLM sets the flag of the corresponding source WDT2RF CLMRF LVIRF bits the other source flags hold their previous values Figure 4 3 Format of RESF Register Reset source flag register RESF Address OxFFFFF888 7 6 5 4 3 2 1 0 WDT2RF Occurrence of reset signal from WDT2 TNT 0 foes OOS o O CLMRF Occurrence of reset signal from CLM Didmtogu o 3 focus S LVIRF Occurrence of reset signal from LVI TC S 3 foes SSCS Notes 1 Only 0 can be written to each bit If writing O conflicts with the flag being set due to the occurrence of a reset flag setting takes precedence If watchdog timer 2 WDT2 the low voltage detector LVI and the clock monitor CLM are being used at the same time the relevant reset source flag must be cleared after checking the reset source Remark The blue values indic
27. t servicing e The LED1 blinking cycle is set to 55 ms e The TMMO compare match interrupt request flag is monitored and when an interrupt request occurs the WDT2 count is cleared the output ot LED1 is inverted and the TMMO compare match interrupt request flag is cleared Application Note U19543EJ1VOAN 7 sa 2 T Ps T ie T n i A f APPENDIX A PROGRAM LIST e When the switch is off the WDT2 count is cleared and the LED1 blinking cycle is set to 120 ms Chattering elimination time during switch input 10 ms I O port settings Input port PO3 INTPO Output Ports PCM2 PCM3 Unused ports P02 P04 to P06 P10 and P11 P30 to P39 P50 to P55 P70 to P711 P90 to P915 PCMO and PCM1 PCTO PCT1 PCT4 PCT6 PDHO to PDH5 Preset all unused ports as output ports pragma ioreg PDLO to PDL15 low level output Enables describing to peripheral I O registers pragma interrupt INTPO f int intpO Specifies the interrupt handler cet E i Constant definitions ay Pen me Na E na x define LIMIT 10ms WAIT 28391 Defines the constant for a 10 ms wait adjustment define VAL 55ms CNT 2149 LED1 blinking cycle 55 ms define VAL 120ms CNT 4688 LED blinking cycle 120 ms M Prototype definitions 7 E R RE Static yvoid T Init void 5 Initialization function static void f init clk bus wdt2 void Clock bus WDT2 initializatio
28. th V850ES JF3 L the setting value With V850ES JF3 L P90 P91 P96 to P99 and P913 is OX1C3C to P915 are set 30 Application Note U19543EJ1VOAN APPENDIX A PROGRAM LIST PCM 0x0C Sets PCMO and PCM 1 to output low level and values to turn off the LEDs to PCM2 and PCM3 m If RESP S5 1 PCM 0x08 Sets that LED2 is turned on when the reset source is WDT2 PMCM 0xF0 PMCCM 0x00 PCT 0x00 Sets PCTO 1 4 and 6 to output low level y PMCT OxAC PMCCT 0x00 PDH Sets PDHO to PDH5 to output low level Er PMDH PMCDH With V850ES JF3 L the setting With V850ES JF3 L PDHO and PDH1 are set value is OxFC PDL 0x0000 Sets PDLO to PDL15 to output low level PMDL 0x0000 PMCDL 0x0000 Setting rhe interrupt function INTFO 0x08 Specifies the falling edge of INTPO INTRO 0x00 4 PICO 0x07 Sets the priority of INTPO to level 7 and unmasks INTPO y return ee ee ae SME O sn 5 Setting timer M Pa static void f init int tmm void TMOCTLO 0x04 Disables TMMO operation ut Count clock fxx 512 t TMOCMPO VAL 120ms CNT Sets TMMO count ur TMOEOMKO 1 Masks timer M interrupts i TMOCE 1 Enables TMMO operation d Application Note U19543EJ1VOAN 31 APPENDIX A PROGRAM LIST KKK KKK K KKK K K K K ckckckckckckckckck ckckckckck ko ko Interrupt module 7 A x kkkkkkkkkk kkkkkk kkkkk kkkkk kkkkxk
29. the CTBP value for the prologue epilogue runtime library of the function e Setting r6 and r7 as argaments of the main function e Branching to the main function 3 5 Differences Between V850ES JG3 L and V850ES JF3 L The V850ES JG3 L is the V850ES JF3 L with its functions such as 1 Os timer counters and serial interfaces expanded In this sample program the initialization range of P1 P3 P7 P9 and PDH in I O initialization differs See APPENDIX A PROGRAM LIST for details of the sample program 3 6 Security ID The content of the flash memory can be protected from unauthorized reading by using a 10 byte ID code for authorization when executing on chip debugging using an on chip debug emulator For details of ID security see the V850ES Jx3 L Sample Program Interrupt External Interrupt Generated by Switch Input Application Note Application Note U19543EJ1VOAN 13 CHAPTER 4 SETTING REGISTERS This chapter describes the watchdog timer 2 WDT2 settings For other initial settings refer to the V850ES Jx3 L Sample Program Initial Settings LED Lighting Switch Control Application Note For interrupt refer to the V850ES Jx3 L Sample Program Interrupt External Interrupt Generated by Switch Input Application Note Among the peripheral functions that are stopped after reset is released those that are not used in this sample program are not set For how to set registers see each product users manual e V850ES JG3 L 32 bit Single
30. tor setting watchdog timer 2 mode reset mode e Setting the use of the subclock and setting the internal system clock e Setting to PLL mode and setting to 20 MHz operation 5b MHz x 4 Pin settings e Setting unused pins e Setting external interrupt pins edge specification priority specification unmasking e Setting LED output pins Settings of 16 bit interval timer M TMM e Selecting the count clock fxx 512 e Setting the TMM count e Masking interrupts from timer M e Enabling operation of TMM 4 Application Note U19543EJ1VOAN CHAPTER 1 OVERVIEW 1 2 Operation of Watchdog Timer 2 WDT2 Watchdog timer 2 generates an internal reset signal WDT2RES when an overflow occurs When a WDT2 reset occurs LED2 turns on and LED1 blinks about every 120 ms When a reset other than a WDT2 reset occurs LED2 turns off and LED1 blinks about every 120 ms WDT2 reset Output Blinks about every 120 ms Turns on LED1 LED2 LED1 LED2 Reset other than WDT2 reset Output Blinks about m every 120 ms Turns off Reset occurrence s l L LED1 LED2 1 3 Enabling Interrupts e Enabling interrupts by using the EI instruction 1 4 Main Loop e Executing an infinite loop LED1 blinks about every 120 ms while the system is waiting for an interrupt generated by switch input Application Note U19543EJ1VOAN 5 CHAPTER 1 OVERVIEW 1 5 Interrupt Servicing Interrupts are serviced by detecting the fal
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