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1. 80H Status Control 81H 82 83H 85H 86H 2 88H 89H 8BH 8CH I O Port 5 _ 8DH 8FH 90H DIO Module I O Interface Block XVME 240 Manual October 1984 The DIO Jumpers and Switch Definitions Function J2 Address Space selection jumper 1 Short Address Space or Standard Address Space 73 35 36 J7 J8 Interrupt input edge detection option jumpers 19 and 51 Selects VMEbus Interrupt Request Level for module I1 17 S2 switches 1 6 Selects Module Base Address S2 switch 7 This switch works in conjunction with jumper J2 to determine whether the board operates with address modifiers for Short I O Address Space or those for Standard Memory space S2 switch 8 This switch determines whether the module will respond to only supervisory accesses or to both supervisory and non privileged accesses D 2 XVME 240 Manual October 1984 Base Address Switch Options Switches VME base address in VME 6 15 XAI 3A12 2 A11 Short VO Address space 0 0 0 0 0 0 0000H 0 0 0 0 0 1 0400H 0 0 0 0 1 0 0800H 0 0 0 0 1 1 0 0 0 1 0 0 1000H 0 0 0 1 0 1 1400H 0 0 0 1 1 0 1800 0 0 0 1 1 1 1 00 0 0 1 0 0 0 2000 0 0 1 0 0 1 2400H 0 0 1 0 1 0 2800H 0 0 1 0 1 1 2C00H 0 0 1 1 0 0 3000H 0 0 1 1 0 1 3400H 0 0 1 1 1 0 3800H 0 0 1 1 1 1 3C00H 0 1 0 0 0 0 4000H 0 1 0 0 0
2. AS 65 76 6108 861 2940120 Tenue W 052 d1WAX 2102 33946 OIC 052 3WAX 20105 00 90 22 Hai 010 946475 1588 SILUM3H2S SONIAVYO 08191200809 051 een 05 197 1353 6 2 sen lt b 169135 9851 9 0 6101509 lt 9 1 9 lt z S e ed 308 et7 aud lt ec 2Qu4 46 4084 lt 9088 lt C 91608 1 9 lt elund lt egiuna lt v lt eviUAd lt e91UAd 119184 Cy C 5 1 9 oyvswiua lt eaisun 9 17 1 1 lt a 1298 t 198 v eSiuAd lt lt 15192 n 508 2 C 18152 vaste d P 038 9 2 0319 94 NED 5746 485191 ani L 13311 lt C NANI LJ D C S1NIM 9 8 514 bb sinin 9 1 9 C um 9 865191 Dy C 9 ONdINI C 9 C T 133 6 335 459119 h C oinin 9 wo vo sivo wo 01083 033 ja 7 9 42018 NOISIA3U 4861 1940120 jenuewW 092 XVME 240 Manual October 1984 Appendix D QUICK REFERENCE GUIDE BASE 00H Module Undefined Identification 40H Undefined
3. 9 9 FRONT VIEW amp Figure 2 6 Connector Pin Numbering Scheme 2 11 XVME 240 Manual October 1984 CAUTION Do not attempt to attach external connections with out first removing power from the module Table 2 8 lists the pin definitions for connectors JKl and JK2 Notice that connector JKl contains ports 0 3 and connector JK2 contains ports 4 7 Each interrupt input line corresponds to a single bit position in an interrupt input register and each flag output line corresponds to a single bit position in a flag output register Table 2 8 JK 1 and JK2 Pin Definitions CONNECTOR JK CH gt Ov gt 2 DO po 10 11 12 13 Interrupt Input Line Bit 0 of Interrupt Input Register Flag Output Line Bit O of Flag Output Register GND Data Data Data Data Data Data Data Data GND Data Data Data Data Data Data Data Data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 a ee p x Interrupt Input Line Bit 1 of Interrupt Input Register X x BO BO Flag LE Bit 1 of Flag Output Register Interrupt Input Line Bit 2 of Interrupt Input Register 2 12 GND Data Data Data Data Data Data Data Data Bit 0 Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
4. 0 9 ans QNS 1 QNS 1 1 M 100298 11 814 9 ase 1 1598 91 814 304 14081 GNS 100298 814 gt QNS N1298 79 614 A8CiS 6 1n0 98 81d QNS 198 9 814 100998 25 824 79 814 AS 1 824 A21 21614 1 94 25 214 2 94 eed lt 914 25 814 26 9139 56 814 16 613 48015 C vid 01 99 14 914 16 919 azi 8 14 1 69951 4 AE 18 214 88334308 508 89190 311UA LN 1 214 2 316 CJ lt 214 CJ 198 9 314 lt 2t4 29 514 CJ 24 214 CJ 29 214 dA 1 69957 4 0319 805191 C 91353898 4 912519 sn K 101504 10318 N31INI KJ 154135 4 153135 55 2 4 88 3 KJ 95 2 L 95 26 65 2 amp essa 16 401943499 439 2257 925194 32012 ZHH 9 ecs sice 83151938 501915 C 3125458 5 83151938 10 1 02 2081 12 814 964 52 814 5841 92 814 etos 92 814 ANT 22221 86 814 EE e 11171 rs 4300230 1408831 1 X81 PL 861 1940120 Tenuew Qt
5. XXX Status Control Bits LEDs 3 2 1 0 Green Red SYSFAIL Status 0 OFF ON Module not yet tested 1 OFF ON Module failed test 1 Inactive module 0 1 Red LED Module undergoing test 1 Module plassed test all others Invalid and undefined Green LED Status Contro Bits LEDs 1 0 Green Red SYSFAIL Status 0 0 OFF ON ON Module failed not yet tested 0 1 OFF OFF OFF Inactive module 1 0 ON ON Module undergoing test 1 1 ON OFF OFF Module passed test NON INTELLIGENT MODULE STATUS FRONT VIEW Figure A 2 Module LED Status XVME 240 Manual October 1984 The module status control register found at module base address 81H intelligent XVME I O modules provides the current status of the module self test in conjunction with the current status of the front panel LEDs The status register on intelligent modules is a Read Only register and it can be read by software to determine if the board is operating properly On non intelligent XVME 10 modules status control register is used to indicate the state of the front panel LEDs and to set and verify module generated interrupts The LED status bits are Read Write locations which provide the user with the indicators to accomodate diagnostic software The Interrupt Enable bit is also a Read Write location which must be written to in order to enable module generated interrupts The Interrupt Pending bit is a Read Only bit which in
6. OIC 052Z 3WAX 2710106 1422 00 90 22 e 010 d 2 3HAX 2119 3 35 100 96 224 8951 940 03149120885 lt 598 1 1noxou1 22 814 ds Y ir t 29 2 9 33 1007291 4 c lt 221 LNY Gs C 1508 1 0 7 C essas 1 t sas 80492 T PITA wiosasat 13508 x 7 C exovid8 C eus388 1 C 08 1 B3IINONHJNAS 3803 8314 95 123135 08908 9 111981 123135 08908 gt t ants KJ sen 5 NINIV 88491 913501 C 4 90392 sve 4 i 391 dasn 4 p prae L lt IN 3291080 6 C 1261080 4 C euim 1 815 1998 Lon 3 C 498 LON ave L 1 uou C a oaan 198 1 133 5 335 aot 77 Imwo xo aiwo vo woniejwoeso 023 jamu 77 301943439 9NIMIL 31242 Eres gt ONY 300230 5534009 342018 NOISIA3U 861 1940120 enueW 092 1 30 19945 OIA 052 3WAX 710165 010 992 3 2110H3H2S wem wm ee Ts 358 6880 _______ 032 12018 NOISIA3U 00919120880 6 26 c
7. XVME 240 Manual October 1984 Table 2 8 JK1 and JK2 Pin Definitions continued CONNECTOR 1 94 27 Flag Output Line Bit 2 of Flag Output Register 95 GND 90 GND 91 Data Bit 0 98 9 Data Bit 39 Data Bit 2 40 Data Bit 9 4 9 Data Bit 4 42 Data Bit 5 43 Data Bit 6 44 Data Bit 7 45 9 Interrupt Input Line Bit 3 of Interrupt Input Register 46 9 Flag Output Line Bit 3 of Flag Output Register 47 GND 48 GND 49 GND 50 GND CONNECTOR JK 2 4 Data Bit 0 2 4 Data Bit 3 4 Data Bit 2 4 4 Data Bit 3 5 4 Data Bit 4 6 4 Data Bit 5 1 4 Data Bit 0 8 4 Data Bit 7 0 4 Interrupt Input Line Bit 4 of Interrupt Input Register 10 4 Flag Output Line Bit 4 of Flag Output Register 11 GND 12 GND 13 5 Data Bit 0 14 5 Data Bit 15 5 Data Bit 2 16 5 Data Bit 3 17 5 Data Bit 4 18 5 Data Bit 5 19 5 Data Bit 6 20 9 Data Bit 7 21 9 Interrupt Input Line Bit 5 of Interrupt Input Register XVME 240 Manual October 1984 Table 2 8 and JK2 Pin Definitions continued CONNECTOR JK 2 22 5 Hag Output Line Bit 5 of Flag Output Register 23 GND 24 GND 25 6 Data Bit 0 26 6 Data Bit 24 6 Data Bit 2 28 6 Data Bit 3 29 6 Data Bit 4 30 6 Data Bit 5 3 6 Data Bit 6 32 6 Data Bit 7 33 6 Interrupt Input Line Bit 6 of Interrupt Input Register 34 6 Hag Output Line Bit 6 of Flag Output Register 35 GND 36
8. Bit Bit Bit j 4 3 2 1 0 Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch Interrupt Input Latch 4 OQ BW Writing a 1 wil pass an interrupt Writng a 0 will mask out an interrupt Figure 3 6 Interrupt Mask Register For example in order to mask out all latched interrupts except those latched on Interrupt Input 3 a value of must be written to the module base address 83H This wil put a I in the fourth bit interrupt input 3 and O s in all other bits As long as this mask 15 in the register the only latched interrupts that will be passed through are those occurring on interrupt input 3 The only way to change the mask 15 to write a new value to the module base address 83H Writing to the Interrupt Mask Register would pass all latched interrupts writing OOH to the register would mask out all latched interrupts NOTE The Interrupt Mask Register is set to all 0 all interrupts masked out immediately following SYSRESET or Soft Reset order to properly enable interrupts the user software firmware will have to write the correct masks to the Mask Reg ister 3 3 7 Interrupts Pending Register Base Address 82H The contents of this read only register can be studied by user provided software firmware to determine if there are latched interrupts which have pa
9. Block The DIO occupies IK block of the Short I O Address space called the module I O Interface Block Within this block in standard locations are found the I O registers the module status and control register and the module identification data Module Status Control register This register provides the user with the hardware means for developing module self diagnostic software to verify the module operational status In addition two bits in this register are used to enable the module interrupt capability and to perform a soft module reset to a default configuration Module Identification Data This facet provides a unique method of registering module specific information in an ASCII encoded format This information can be studied by the system processor on power up to verify the system configuration and operational status Additional information on the XYCOM Standard I O Architecture can be found in Appendix A of this manual 14 SPECIFICATIONS The following is a list of operational and environmental specifications for the DIO module 1 3 XVME 240 Manual October 1984 Table DIO Module Specifications Characteristic Specification Number of Channels Number of Flag Output Lines Number of Interrupt Input Lanes 64 arranged in 8 logical ports 9 9 Output Characteristics Flag Outputs Vol Low level output voltage lol 24mA lol 12 mA Iol Low level output current Voh High level output
10. Memory the Standard Memory Space Which Interrupt Request Level the module will operate at 1e 11 17 Whether the Interrupt Inputs will latch on the rising or falling edge of the interrupt input signal 5 Which Address Modifier codes the module will respond to ie 29 2D 2D only 39 or 3D or 3D only 2 3 MAJOR COMPONENT LOCATIONS The components relevent to installation are shown in Figure 24 2 1 XVME 240 Manual October 1984 Red LED FAIL Green LED PASS JK2 5 52 E JK 1 43 34 222 45 Gi 46 215 Ro J10 J9 J8 J7 GI 89 is Ni Figure 2 1 Major Component Locations 2 2 XVME 240 Manual October 1984 2 4 JUMPERS SWITCHES The DIO module has 9 jumpers and 2 sets of DIP switches The jumpers and switches are defined in Table 2 1 Table 24 The DIO Jumpers and Switch Definitions J2 Address Space selection jumper ie Short I O Address Space or Standard Address Space J3 44 J5 96 47 J8 Interrupt input edge detection option jumpers J9 and 10 Sl Selects VMEbus Interrupt Request Level for module 11 17 59 switches 1 6 Selects Module Base Address 52 switch 7 This switch determines whether the module will respond to only supervisory accesses or to both supervisory and non privileped accesses 52 switch 8 This switch works in conjunction with jumper 32 to determin
11. as an input port not both at the same time The direction of each port 15 determined by the contents of the read write Port Direction Register Base address 87H Each bit in the Port Direction register corresponds to one of the I O ports Bit 0 corresponds to Port 0 bit 1 corresponds to Port 1 and soon When a logic 0 is written to a specific bit in the Port Direction register the port corresponding to that bit will be configured as an input port When a logic 1 1s written to a specific bit in the register the corresponding port will be configured as an output port Figure 3 3 is a bit map of the Port Direction register PORT DIRECTION REGISTER module Base 87H 7 6 9 4 3 2 0 Lectt Port 0 L 1 0 Port I O Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 logic 1 configures Port for output logic 0 configures a Port for input Figure 3 3 Port Direction Register Bit Map 3 7 XVME 240 Manual October 1984 The Port Direction register is cleared to all O s all ports are inputs by VME SYSRESET or by Soft Reset see Section 3 3 2 for information on performing a Soft Reset Thus when the module is powered up or when it is reset the ports will all automatically be configured as inputs After power up or reset it will be necessary to write to the port direction register to configure any ports for output For example if a DIO module base address is set
12. bits are ignored This arrangement provides the correct address configuration to allow each module address to Begin on a 1K boundary Non intelhgent XVME modules allow the use of six base address jumpers representing bits 10 15 and thus they are able to reside on any of the 64 boundaries available in the short I O address space Intelligent XVME modules will only allow the use of four base address jumpers representing bits AI0 A13 which limits their selection of 1K boundaries to one of 16 possible choices Figure 1 shows an abbreviated view of the short I O memory BASE Short I O AddressSpace 0400H 0800H 0C00H 1000H 1400H Ub ow Figure 1 64K Short I O Address Space XVME 240 Manual October 1984 Standardized Module Map The block of short addresses called the I O Interface Block allocated to each XVME module is mapped with a standardized format in order to simplify programming and data access The locations of frequently used registers and module specific identification information are uniform For example the module identification information is always found in the first 32 odd bytes of the module memory block with these addresses being relative to the jumpered base address 1 e Module I D data address base address odd bytes byte located at base address 81H each module contains a Status Control register which provides the results of diagnostics for verifica
13. ports 8 interrupt input lines and 8 flag output lines Each bidirectional port can be programmed to either input or output data The 8 interrupt input lines can be used in conjunction with the module interrupt masking and handling capabilities to generate of VMEbus interrupt on level Typical applications for the DIO module include TTL level peripheral control of printers and other parallel port devices Interfacing with OPTO 22 compatible devices to control switch inputs indicator outputs and AC DC applications 1 MANUAL STRUCTURE The purpose of this first chapter is to introduce the user to the general specifications and functional capabilities of the DIO module Successive chapters will develop the various aspects of module installation and operation in the following progression Chapter One A general description of the DIO module including complete functional and environmental specifications VMEbus compliance information and a block diagram Chapter Two Module installation information covering the location of pertinant module components switch and jumper options external connector pin locations and standard board installation information Chapter Three General information needed to use the DIO module including module base addressing module identification data the Status and Control register data port addressing data direction programming 1e Input or Output and the interrupt scheme The Append
14. provided interrupt service routines As mentioned in the previous section each interrupt input has its own Interrupt Edge Detection circuitry and Interrupt Latch Once an input has detected and latched and interrupt the latch will remain set to a logic I until the latch is cleared Clearing the interrupt input latches is accomplished by using the Interrupt Clear Register Figure 3 5 shows a bit map of the write only Interrupt Clear Register INTERRUPT CLEAR REGISTER Base Address 84H Bit Bit Bit Bit Bit Bit Bit Bit 7 6 4 3 2 1 0 Interrupt Input Latch 0 Interrupt Input Latch 1 Interrupt Input Latch 2 Interrupt Input Latch 3 Interrupt Input Latch 4 Interrupt Input Latch 5 Interrupt Input Latch 6 Interrupt Input Latch 7 Figure 3 5 Interrupt Clear Register 3 9 XVME 240 Manual October 1984 Each bit of the Interrupt Clear Register 15 connected to a specific interrupt input latch By writng I to a particular bit position the Clear Register you will clear the corresponding interrupt input latch and register For example if a module base address is set to Short I O Address Space and it is necessary to clear interrupt input latches for input O and input 2 then you would write to address 1084H This will put a logic 1 in bit positions and 2 in the Interrupt Clear Register and thus clear the interrupt input latches for inputs O and 2 The Interrupt Clear Register resets
15. to only Supervisory access or to both Non Privileged and Supervisory accesses by selecting the position of Switch 7 located in Switch Bank 2 see Figure 2 3 as shown in Table 2 4 below Table 24 Privilege Options Privilege Mode Selected Closed Supervisory or Non Privileged Open Supervisory Only 2 4 4 Address Modifier Reference The following table Table 2 5 indicates the actual VMEbus Address Modifier code that the DIO will respond to based on the position of the two options discussed in the previous two sections Table 2 5 Address Modifier Code Options D Jumper Address Modifier Code J2 DIO will respond to Short Closed Closed 2H or 2DH VO Open Closed 2DH only Standard Closed Open 39H or 3DH Address Open Open 3DH only 2 7 XVME 240 Manual October 1984 2 4 5 IACKIN IACKOUT Daisy Chain The DIO has the ability to generate a VMEbus interrupt Therefore jumper Jl 15 hardwired in position to enable the IACKIN IACKOUT daisy chain CAUTION The jumper shorting to IACKOUT for DIO s slot in the backplane must be removed or the DIO may be damaged 2 4 6 Interrupt Level Switches Figure 2 4 shows Switch Bank 1 with its three interrupt level select switches Table 2 6 illustrates their use OPEN Figure 2 4 Switch Bank Interrupt Level Select Switches 2 8 XVME 240 Manual October 1984 Table 2 6 Interrupt Level Options Switches 3 2 Level No Level selecte
16. voltage loh High level output current Voh 24V Ioh 20 Channel Outputs Vol Low level output voltage lo 48mA 05V max lol 16 mA 04V max ll Low level output current 48 mA max Voh High level output voltage 24V min loh High level output current 24V 3 mA max loh 20 15 mA max Slave Data Transfer Options A16 D16 STAT A24 D16 STAT Interrupter Options Any one of 40 STAT Power Requirements channels configured as inputs Typ 27A Max 34 channels high outputs 3 6A max load Max 42 channels low outputs Typo 27 Max 34 1 4 XVME 240 Manual October 1984 Table 1 1 DIO Module Specifications continued Characteristic Specification Temperature Operating 0 659 C 329 to 14995 Non Operating 40 to 85 C 40 to 158 F Humidity 5 to 95 RH non condensing Note extreme low humidity conditions may require special protection against static discharge Altitude Operating Sea level to 10 000 ft 3048m Non Operating Sea level to 50 000 ft 15240m Vibration Operating 5 to 2000 Hz 0 015 inches peak to peak displacement 2 5 g peak max acceleration Non Operating 5 to 2000 Hz 080 inches peak to peak displacement 5 0 g peak max acceleration Shock Operating 90 g peak acceleration 11 msec duration Non Operating 50 g peak acceleration 11 msec duration VMEbus Compliance e Fully compatible with VMEbus standard e Al
17. 1 1 0 1 1 1 DCOOH 1 1 1 0 0 0 1 1 1 0 0 1 E500H 1 1 0 1 0 E800H 1 1 1 0 1 1 ECOOH 1 1 1 1 0 0 1 1 1 1 0 1 F400H 1 1 1 1 1 0 F800H 1 1 1 1 1 1 FCOOH NOTE Open Logic 1 Closed Logic 0 2 5 XVME240 Manual October 1984 242 Addres Space Selection The user is given the option of placing the DIO in VMEbus Short I O or Standard Memory Space The selection is made by configuring jumper J2 and Switch 8 of Switch Bank 2 see Figure 2 3 as shown in Table 2 3 below Table 2 3 Addressing Options Jumper Option Selected J2A Open Standard Data Access Operation DB Closed Short I O Access Operation If jumper J2A is installed Switch 8 must be set to open If jumper JB is installed Switch 8 must be set to closed The Standard I O Architecture recommends that the DIO operate within the Short I O Address Space in order to take advantage of the Standard Architecture various features which are described in Appendix A If required the DIO can operate in the Standard Address Space The user should note that this mode the DIO will always reside within the last 64K byte segment of the Standard Memory Address Space i e the address range FFOOOOH through FFFFFFH SUPERVISOR NON PRIVILEGED ADDRESS SPACE SELECTION Figure 2 3 Switch Bank S2 2 6 XVME 240 Manual October 1984 2 4 3 Supervisor Non Privileged Mode Selection DIO be configured to respond
18. 1 4400H 0 1 0 0 1 0 4800 0 1 0 0 1 1 4C00H 0 1 0 1 0 0 5000H 0 1 0 1 0 1 5400H 0 1 0 1 1 0 5800H 0 1 0 1 1 1 5 0 1 1 0 0 9 6000H 0 1 1 0 0 1 6400H 0 1 1 0 1 0 6800H 0 1 1 0 1 1 6CO0H 0 1 1 1 0 0 7000 0 1 1 1 0 1 7400H 0 1 1 1 1 0 7800H 0 1 1 1 1 1 7C00H 1 0 0 0 0 0 8000 1 0 0 0 0 1 8400H 1 0 0 0 1 0 8800H 1 0 0 0 1 1 8 00 1 0 0 1 0 0 9000H 0 0 1 0 1 9400H 1 0 0 1 1 0 9 00 1 0 0 1 1 1 9C00H 1 0 1 0 0 0 000 1 0 1 0 0 1 _ 1 0 1 0 1 0 A800H 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 B400H J 0 1 1 1 0 800 1 0 1 1 1 1 BCOOH 1 1 0 0 0 0 000 1 1 0 0 0 1 C400H 1 1 0 0 1 0 C800H 1 1 0 0 1 1 1 i 9 1 0 0 D000H 1 1 0 1 0 1 D400H 1 1 0 1 1 0 D800H 1 1 0 1 1 1 DCOOH 1 1 1 0 0 0 1 1 1 0 0 1 E400H 1 1 0 1 0 l 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 F400H 1 1 1 1 0 F800H 1 1 1 1 1 1 Open Logic 1 Closed Logic 0 D 3
19. 15 30 address lines that specify memory address XVME 240 Manual October 1984 Table 8 1 VMEbus Signal Identification cont Connector Signal and Pin Number Signal Name and Description BBSY 1 BUS BUSY Open collector driven signal gener ated by the current DTB master to indicate that it is using the bus BCLR IB2 BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the current DTB master in the event that a higher level is requesting the bus BERR IC 11 BUS ERROR Open collector driven signal gener ated by a slave This signal indicates that an unrecoverable error has occurred and the bus cycle must be aborted BGOIN 4 6 BUS GRANT 0 3 IN Totem pole driven signals BG3IN 8 10 generated by the Arbiter or Requesters Bus Grant In and Out signals from a daisy chained bus grant The Bus Grant In signal indicates to this board that it may become the next bus master Refer to Section 2 4 7 BGOOUT 1 5 7 BUS GRANT 0 3 OUT Totem pole driven BG30UT 9 1 signals generated by Requesters Bus Grant In and Out signals form a daisy chained bus grant The Bus Grant Out signal indicates to the next board that it may become the next bus master Refer to Section 2 4 7 BRO BR3 18 12 15 BUS REQUEST 0 3 Open collector driven sig nals generated by Requesters These signals indi cate that a master in the daisy chain requires access t
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21. 42 214 609 D 91 914 311uA 7 A 213 vena A anreve K ONS 4 0 2 698 i ZN 2 JER sin 072 amp 8 20 2 i 82 914 291 D 8 2 ewa 19 91 914 545144 89 22 21 61 814 wv g T1 81 414 i ee d 61 614 H21U1 2 914 uv 27 72 7174 81 214 2 94208 lt 2895794 11391 3019894403 31313 0119 02 214 619 42 514 119 5 92 214 219 71317 52 214 civ 15 6 viv 4 2 314 619 vested 20895141 8019894 03 0 1 22 914 919 ves 12 514 118 A zr g 682 214 919 D D 61 214 619 ssw 61 214 aces 939L 41 214 129 a 5530009 AWON3H 3440 91 214 229 lt 61504 534945 LA a dA E ie esae w2v1090 eva 21 214 1353854 2 esus 1 11 214 4 61 814 55 dedu 91 414 9 910 c 2 412558 61 814 413515 z esos K 21 914 9150 4 1 914 ssa L 2 0500 12 014 ontyour MAL 29g 99391 15511121 29251502 333 50 9411 3 251 4 Aa 330 9n 3010936 2 5 VILAM 32019 NOISIA3U LoT 861 1940120 Tenuen os5z 3WAX 1 10 Z 9996 gt
22. 6 D 16 Data transfer bus slave e Interrupter Options Any of 1 to 7 STAT e Base address jumper selectable within 64K short I O address space e Occupies 1K consecutive byte locations 1 5 XVME 240 Manual October 1984 Chapter 2 INSTALLATION 21 INTRODUCTION This chapter explains how to configure the DIO module prior to installation in a VMEbus system Included in this chapter is information on jumper options jumper locations switch options switch locations and external connector pin descriptions 22 SYSTEM REQUIREMENTS The DIO module is a double height VMEbus compatible digital level input output module such the DIO requires a minimum system component configuration for proper operation The minimum system requirement be met by either one of the following A host processor module properly installed on the same backplane as the DIO and a controller subsystem module which employs a Data Transfer Bus Arbiter Subsystem Clock driver a System Reset driver and a Bus time out module The XYCOM XVME 010 System Resource Module provides a controller subsystem with the components listed TE O R B host processor module which incorporates an on board controller sub system Prior to installing the DIO it will be necessary to configure several jumpers and switch selectable options These options are Module Base Address 2 Whether the module will be addressed in Short
23. 984 Jumpers J3 JIO are all two position jumpers with the two positions labeled and B Figure 2 5 shows an enlarged view of jumper and how the two positions are labeled The remaining 7 jumpers are all identical to jumper J10 Figure 25 Interrupt Input Edge Selection Jumper If a jumper is set in position then that interrupt input line will latch the interrupt input on the low to high transition of the signal Likewise if a jumper is set to posi ton then that interrupt input line will latch the interrupt input on the high to low transition of the signal Table 2 7 reiterates this concept Table 2 7 Edge Selection Jumper Options Jumper Interrupt Input Position Signal Will Latch on the rising edge of the input Latch on the falling edge of the input 2 10 XVME 240 Manual October 1984 2 5 FRONT PANEL CONNECTORS There are two 50 pin dual row header connectors labeled JK 1 and JK2 located on the front panel of the DIO module These connectors provide the 64 I O channels arranged in 8 ports the 8 interrupt input lines the 8 flag output lines and several module ground connections Figure 2 6 shows the connector pin numbering orientation from both a side view and a front view Red LED FAIL i Green LED PASS SIDE VIEW INDICATES THE LOCATION OF PIN 1 9 9 9
24. Acroma THE LEADER IN INDUSTRIAL 1 240 60 80 Channel Digital TTL Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 968B XYCOM REVISION RECORD Revision Description Manual Released Incorporated PCN 090 Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied withou expressed written permission from Xycom The information contained within this documentis subjectto change without notice Xycom does not guarantee the accuracy of the information and makes no commitment toward keeping it up to date Address comments concerning this manual to xycom Technical Publications Dept 750 North Maple Road Saline Michigan 48176 Part Number 4240 001 B XVME 240 Manual October 1984 CHAPTER 1 M mM NNNNNNNNNNNNNNNN N Im V9 APPENDICES 9 gt TABLE OF CONTENTS TITLE MODULE DESCRIPTION Introduction Manual Structure Module Operational Description Specifications INSTALLATION Introduction System Req
25. Bit will be set to logic 07 2 By writing to the Interrupt Mask register 3 By writing a 0 to the Interrupt Enable Bit 3 of Status Control register XVME 240 Manual October 1984 Appendix A XYCOM STANDARD I O ARCHITECTURE INTRODUCTION The purpose of this Appendix is to define XYCOM Standard Architecture for XVME modules This Standard I O Architecture has been incorporated on all XVME I O modules in order to provide a simpler and more consistent method of programming for the entire module line The I O Architecture specifies the logical aspects of bus interfaces as opposed to the physical or electrical aspects as defined in the VMEbus specifications The module elements which are standardized by the XYCOM Architecture are the following l Module Addressing Where a module is positioned the address space and how software can read from it or write to it 2 Module Identification How software can identify which modules are installed in a system 3 Module Operational Status How the operator can through software determine the operational condition of specific modules within the system 4 Interrupt Control How software is able to control and monitor the capability of the module to interrupt the system 5 Communication between Modules How master host processors and intelligent I O modules communicate through shared global memory or the dual access RAM on the I O
26. C Signal Mnemonic Row Signal Mnemonic Row B Signal Mnemonic Pin Number B 6 XVME 240 Manual October 1984 Appendix C SCHEMATICS AND DIAGRAMS Block Diagram FRONT PANEL CONNECTORS 100 PINS PASS FAIL LED s 8 8 64 INTERRUPT BIDIRECTIONAL INPUTS PUTS CHANNELS IDENTIFICATION READ WRITE DATA ADORESS INTERRUPTER BUFFERS DECODE VME bus XVME 240 Manual October 1984 Assembly Drawing gu uu i Sa ee BEBB 5 a 5 5 1 je ju B xw pou 19 5 Sse Pl fere poca 1 3 53 p wrb 076 071 U72 973 974 E vs b 977 2 10 1 19995 OIG 05Z 3WAX 1140102 7 ela 29186 am 9 C a 5 010 Z 3WAX lt 0 s 0039 311U0H3H2S 5 96 914 teu PA NDUI EA P 422414 A LI 4 82 914 cov L e tus wu wee 42 814 vov 02312 s v gs D 2414 909 7 92 914 cov we eve 86 214 sev L C sve Kl L cz H2101 5534009 30 1894 LON I 310N 5
27. GND 37 7 Data Bit 0 38 Data Bit 39 7 Data Bit 2 40 Data Bit 3 4 Data Bit 4 42 Data Bit 5 43 Data Bit 6 44 7 Data Bit 7 45 Interrupt Input Line Bit 7 of Interrupt Input Register 46 Flag Output Line 7 of Flag Output Register 47 GND 48 GND 49 GND 50 GND Although the interrupt inputs and the flag outputs were intended to be logically related to the 8 ports ie for handshaking purposes there are no electrical constraints placed upon their use 2 14 XVME 240 Manual October 1984 CAUTION Whenever instalhng any external devices at connectors JKl JK2 the user must properly ground the external device to one of the available module ground lines there are two per port Failure to ground the external device to the module ground could result in a voltage potential which could damage both the external device and the DIO module 26 AND P2 CONNECTORS Connectors PI and P2 are mounted at the rear edge of the board see Figure 2 The pin connections for 96 3 row connector contain the standard address data and control signals necessary for the operation of VMEbus defined NEXP modules The connector is designed to mechanically interface with VMEbus defined backplane P2 connector is a standard VMEbus P2 backplane connector 1 a 96 3 row connector designed to provide the module with 5V and ground The signal definit
28. I O 3 2 Address Space 3 2 Status Control Register 3 5 3 3 Port Direction Register Bit Map 3 7 3 4 Interrupt Input Register 3 8 3 5 Interrupt Clear Register 3 9 3 6 Interrupt Mask Register 3 11 3 7 Interrupts Pending Register 3 12 3 8 Interrupt Vector Register 3 13 3 9 Flags Outputs Register 3 14 3 10 Interrupt Input Logic 3 15 A 1 64K Short I O Address Space A 2 A 2 Module Address A 4 A 3 Module LED Status A 6 A 4 Status Register Bit Definitions A 8 A 5 Intelligent and Non Intelligent Kernels A 10 i XVME 240 Manual October 1984 TABLE i Ii QN Van gt Ne 0 b B 2 B 3 TABLE OF CONTENTS continued LIST OF TABLES TITLE DIO Module Specifications The DIO Jumpers and Switch Definitions Base Address Switch Options Addressing Options Privilege Options Address Modifier Code Options Interrupt Level Options Edge Selection Jumper Options JK 1 and JK2 Pin Definitions Identification Data Module I O Port Address Module I D Data P1 VMEbus Signal Identification Pin Assignments P2 VMEbus Signal Identification iii B 6 XVME 240 Manual October 1984 Chapter 1 MODULE DESCRIPTION 11 INTRODUCTION The XVME 240 Digital Input Output Module hereafter referred to as the DIO module provides VMEbus systems with 80 TTL level I O channels The I O channels are arranged to provide 9 byte wide bidirectional
29. IC IDENTIFICATION DATA The module identification scheme provides a unique method of registering module specific information in an ASCII encoded format The I D data is provided as thirty two ASCII encoded characters consisting of the board type manufacturer identifica tion module model number number of blocks occupied by the module and model functional revision level information This information can be studied by the system processor on power up to verify the system configuration and operational status Table 1 defines the Identification information locations A 4 XVME 240 Manual October 1984 Table A 1 Module I D Data Offset Relative to Contents ASCII Encoding Descriptions Module Base in hex ID PROM identifier always VMEID 5 characters Manufacturer s I D always XYC for XYCOM modules 3 characters Module Model Number 3 characters and 4 trailing blanks x lt Number of 1K byte blocks of I O space occupied by this module 1 character Major functional revision level with leading blank if single digit Minor functional revision level with trailing blank if single digit Manufacturer Dependent Information Reserved for future use The module has been designed so that it is only necessary to use odd backplane addresses to access the I D data Thus each of the 32 bytes of ASCII data have been assigned to the first 32 odd I O Interface Block bytes i
30. Register Figure 3 10 Interrupt Input Logic 3 15 XVME 240 Manual October 1984 The Interrupt Input signal is buffered before it reaches the Edge Detection circuitry Depending upon how the Edge Detection Jumper is set the Interrupt Input signal will be gated in on either its rising or falling edge refer to Section 2 4 8 After the Interrupt Input signal is gated through the Edge Detection circuitry it be latched providing the Interrupt Input latch 15 cleared The clear line on the Interrupt Input latch corresponds to a particular bit in the Interrupt Clear register By writing a I to the corresponding bit in the Interrupt Clear register an Interrupt Input latch can be cleared refer to Section 3 3 5 The output of the Interrupt Input latch goes directly to its corresponding bit in the Interrupt Input Register Thus the Interrupt Input Register reflects the status of the Interrupt Input latch and not the current state of the Interrupt Input line itself refer to Section 3 3 4 for more information on the Interrupt Input Register The Interrupt Input Register can be read by user software firmware to determine which Interrupt Inputs have actually latched an interrupt from an external device When Interrupt Input latch is cleared the Interrupt Input Register bit for that latch is also cleared The output of the Interrupt Input latch also goes to the input of an AND gate where it 1s logically ANDed with the corre
31. ary for the operation of NEXP modules P2 contains additional volt and ground connections for the module The following tables identify the VMEbus signals by signal mnemonic connector and number and signal characteristic Table VMEbus Signal Identification Connector Signal and Mnemonic Pin Number Signal Name and Description ACFAIL IB3 AC FAILURE open collector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not being met IACKIN 14 21 INTERRUPT ACKNOWLEDGE IN driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknow ledge cycle is in progress Refer to Section 2 4 5 IACKOUT 1 22 INTERRUPT ACKNOWLEDGE OUT Totem pole driven signal IACKIN IACKOUT signals form daisy chained acknowledge The IACKOUT signal indicates to the next board that an acknowledge cycle is in progress Refer to Section 2 4 5 5 1 23 ADDRESS MODIFIER bits O 5 Three state 18 16 17 driven lines that provide additional information 18 19 about the address bus such as size cycle type 1C 14 and or master identification AS 1A 18 ADDRESS STROBE Three state driven signal that indicates valid address 15 the address bus A01 A23 1 A 24 30 ADDRESS bus bits 1 23 Three state driven
32. ask while interrupts disabled will remain pending until the interrupts are enabled cleared or masked out Once a backplane interrupt signal Il I7 as determined by the setting of switch Sl is generated it will remain active until the system software clears the Interrupt Input latch by writing to the Interrupt Clear Register The backplane interrupt signal is not cleared by the Interrupt Acknowledge cycle NOTE The Interrupt Vector Register and the Interrupt Input latches will contain undeterminate data on power up and reset Thus before interrupts are enabled the interrupt latches must be cleared and the Interrupt Vector address must be programmed 3 4 1 Interrupt Sequence The following section covers the interrupt initialization sequence and a typical interrupt execution sequence With the power off 1 Determine and set the correct positions for the Interrupt Edge Detector jumpers 2 Select the desired Interrupt Request level for the DIO module using Switch 51 After system power up or reset 3 Clear Interrupt Input latches and registers by writing to the Interrupt Clears register 4 Write the Vector address which is to be employed by interrupt handling software in the Interrupt Vector register 5 Write an appropriate mask to the Interrupt Mask register to enable the interrupt inputs for the desired input lines 6 Enable the DIO module interrupt capability by writing to 3 of the Status Control regi
33. ce Block If the module base address is set to a value of 1000H then the Status Control register would be accessed at address 1081H Module Base IO Interface Status Control Address Block Offset Register 1000H 081H 1081H For memory mapped CPU modules such as 68000 CPU modules the Short I O Address Space is memory mapped to begin at a specific address For such modules the I O Interface Block offset is an offset from the start of this memory mapped Short I O Address space For example if the Short I O space of 68000 CPU module starts at F90000H and if the base address of the DIO is jumpered to 1000H the actual module base address would be 91000 3 3 THE DIO I O INTERFACE BLOCK The 1K block of Short I O Address space allotted to the DIO see Figure 3 1 is divided into specific areas which are dedicated to performing the following functions Module identification data for the DIO Module status and control Data I O ports and registers for controlling I O and interrupts 3 3 1 Module Identification Data Base 0IH to odd byte locations only The XYCOM module identification scheme provides a unique method of registering module specific information in an ASCII encoded format The LD data is provided as thirty two ASCII encoded characters consisting of the board type manufacturer identification module model number number of 1K byte blocks occupied by the module and module functional revision level information T
34. circuits 12 Vdc Power Used by system logic circuits 4 XVME 240 Manual October 1984 BACKPLANE CONNECTOR Pl The following table lists the PI pin assignments by pin number order The connector consists of three rows of pins labeled rows A B and C Table B 2 P 1 Pin Assignments Row A Row B Row C Signal Signal Signal Mnemonic Mnemonic Mnemonic D00 BBSY DO8 2 DO1 BCLR DO9 3 DO2 ACFAIL DIO 4 DO3 BGOIN Dil 9 DO4 BGOOUT D12 6 DO5 BGIIN D13 T 006 BGIOUT D14 8 007 BG2IN D15 9 GND BG20UT GDN 10 SYSCLK BG3IN SYSFAIL 11 GND BG30UT BERR 12 DSI BRO SYSRESET 13 DSO BRI LWORD 14 WRITE BR2 5 15 GND BR3 A23 16 DTACK AMO A22 17 GND AMI A21 18 AM2 A20 19 GND AM3 A19 20 IACK GND 18 21 IACKIN SERCLK 1 17 22 IACKOUT SERDAT 1 16 28 AMA GND 15 24 07 IRQ7 14 25 A06 IRQ6 A13 26 A05 IRQ5 A12 27 A04 IRQ4 All 28 A03 IRQ3 AIO 29 A02 IRQ2 A09 30 A01 IRQI A08 1 12v 5V STDBY 12v 32 5V 415v 45v B 5 XVME 240 Manual October 1984 Table B 3 P2 VMEbus Signal Identification Connector and Signal Name and Description Power Used by system logic circuits Ground ALL OTHER PINS NOT USED BACKPLANE CONNECTOR P2 The following table lists the P2 pin assignments by pin number order The connector consists of three rows of pins labeled A B and Table B 4 P2 Pin Assignments Row
35. d Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 0 0 0 NOTE Open Logic 1 Closed Logic 0 2 47 BGxIN BGxOUT Daisy Chain The Data Bus Arbitration signals BGxIN and BGxOUT where x can be a number O 3 to represent the three levels of arbitration are not used by the DIO and are hardwired together on the module to allow BGxIN BGxOUT Daisy Chain to pass through the backplane slot occupied by the DIO In each slot of the VMEbus backplane there are four sets of jumpers shorting the signal BGxIN to BGxOUT 0 thru 3 Since these signals are already hardwired on the DIO it is not necessary to insert these VMEbus jumpers on the slot occupied by the DIO 2 4 8 Interrupt Input Edge Detection Option There are 8 interrupt input lines on the DIO module which allow externally connected devices to generate VMEbus interrupts on any level 11 17 The user has the option to control whether the board will latch the interrupt input signals on the low to high transition of the input or on the high to low transition of the input The jumpers which control interrupt input edge selection are labeled J3 J10 refer to Figure 2 for the location of these jumpers The edge select jumpers correspond to the interrupt input lines in the following fashion Edge Select Jumper Interrupt Input Line 33 INTO INTI J5 INT2 6 INT3 INT4 J8 INT5 J9 INTO 910 2 9 XVME 240 Manual Octo ber 1
36. d to receive interrupt input signals from externally connected devices in order to generate a VMEbus Interrupt Request to a system processor There are 8 Interrupt Input lines which logically relate to the 8 I O ports Although these input lines were designed to correspond to specific I O Ports there are no physical electrical restraints placed upon their use e g Interrupt Input line 1 be used with any of the 8 I O ports or by itself with no correlation to external devices connected to the I O ports Figure 3 10 shows a simplified representation of the 8 Interrupt Input lines and the general components involved in controlling and monitoring the interrupt process Each Interrupt Input line has its own corresponding set of register bits and control circuitry represented by black boxes Figure 3 10 shows an enlarged example of the logic used by one of the Interrupt Inputs because all of the Interrupt Inputs are identical only one example is needed 3 14 XVME 240 Manual October 1984 Represents the Interrupt Input Circuitry and Register Bits which are Part of Input Line Interrupt Enable Bit Bit 3 of Register pe as VME bus NP Interrupt Inputs MGE Request E TT Pend nterrupt Pending Flag Bit 2 of AT Status Control Register This Enlarged E xomple Shows the Interrupt Input Circuitry for of interrupt input Register Pending
37. dicates a module generated pending interrupt 7 XVME 240 Manual October 1984 Figure A 4 shows the status control register bit definitions for both intelligent and non intelligent XVME I O modules INTELLIGENT NON INTELLIGENT MODULES MODULES RED LED RED LED GREEN LED GREEN LED TEST STATUS INTERR PENDING TEST STATUS INTERR ENABLE MODULE DEPENDENT Bit Non Intelligent Modules Bit Intelligent Modules 0 Read Write Red LED 0 Read Only Red LED 0 Red LED On 0 Red LED On 1 Red LED Off Red LED Off 1 Read Write Green LED 1 Read Only Green LED 0 Green LED Off 1 0 Green LED Off Green LED On 1 Green LED On 2 Read Only Interrupt Pending 2 amp 3 Read Only Test Status Indicators 0 No Interrupt Bit 3 Bit 2 Interrupt Pending 0 0 Self test not started 0 1 Self test in progress 1 0 Self test failed 1 Self test passed 3 Read Write Interrupt Enable 0 Interrupts Not Enabled Interrupts Enabled Module dependent Module dependent Module dependent Module dependent Module dependent Module dependent Module dependent Module dependent ON V ON Vn amp Figure 4 Status Register Bit Definitions 240 Manual October 1984 INTERRUPT CONTROL Interrupts for non intelligent modules can be enabled or disabled by set ng clearing the Interrupt Enable bit in the module status register The status of pending on board interrupts can also be read f rom th
38. e odd bytes 1H 3FH I D information can be accessed simply by addressing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000H and if you wish to access the module model number I O interface block locations 11H 13H 15H 17H 19H and you will individually add the offset addresses to the base addresses to read the hex coded ASCII value at each location Thus in this example the ASCII values which make up the module model number are found sequentially at locations 1011H 1013H 1015H 1017H 1019H 101BH and 101DH within the system s short I O address space XVME 240 Manual October 1984 MODULE OPERATIONAL STATUS CONTROL All XVME intelligent I O modules are designed to perform diagnostic self tests on power up or reset For non intelligent modules the user must provide the diagnostic program The self test provision allows the user to verify the operational status of a module by either visually inspecting the two LEDs which are mounted on the module front panel see Figure A 3 or by reading the module status byte located at module base address 81H Figure A 3 shows the location of the status LEDs on the module front panel The two tables included with Figure A 3 define the visible LED states for the module test conditions on both the intelligent I O modules and the non intelligent I O modules y XXXX
39. e whether the board operates with address modifiers for Short I O Address Space or those for Standard Memory space 2 4 1 Base Address Switches The DIO module is designed to be addressed within either the VMEbus Short I O or Standard Memory Space Since each I O module connected to the bus must have its own unique base address the base addressing scheme for XVME I O modules has been designed to be switch or jumper selectable When the DIO module is installed in the system it will occupy a 1K byte block of the Short I O Memory called the module I O Interface Block The base address decoding scheme for XYCOM 10 modules is such that the starting address for each I O Interface Block resides on boundary Thus the module base address may be set to any one of 64 possible 1K boundaries within the Short I O Address space The module base address 1s selected by using the switches labeled 1 6 in DIP switch bank 52 Figure 2 2 shows the switch bank 52 and how the individual switches 1 6 relate to the base address bits 2 3 240 Manual October 1984 A10 A11 A12 A13 A14 A15 Figure 2 2 Switch Bank S2 Base Address Switches When a switch is in the closed position i e when it is pushed in on the opposite end of the switch bank from the open label the corresponding base address bit will be interpreted as a logic 0 When a switch is set to the open position the corresponding base address bit will be inte
40. ead Write This bit is for a software module reset If it is toggled between logic 0 and a 1 1 if it is set from 0 to and then back to 0 the module will reset in the following fashion 1 The interrupt mask register will be cleared all inputs masked out 2 ports will be configured as inputs 3 All port latches are reset to OOH 4 flag outputs are reset to 00H Bit 3 Read Write This bit must be set to a logic 1 in order for the module interrupt capability to be enabled 3 5 XVME 240 Manual October 1984 Bit 2 Read Only Bit 1 Bit Read Write Green This bit acts as a flag to show if there are any interrupts pending on the DIO A logic I indicates that at least one interrupt is pending A logic indicates that there are no pending interrupts This bit is valid even when interrupts are disabled These bits control the red LED and green LED The red and green LEDs provide a visual indication of module Status A logic 0 turns on red LED bit DO A logic 1 turns on the green LED bit The LEDs will work with user provided diagnostic soft ware to indicate module operational status in the following manner Status Bits LEDs Red SYSFAIL Status ON ON Module failed or not yet OFF OFF ON ON tested OFF OFF Inactive module ON ON Module undergoing test OFF OFF Module passed test The DIO 15 NOTE a non intelligent module so all diagnos
41. h I O Interface Block must reside on a boundary Thus the module base address will be one of the 64 IK boundaries available within the Short I O Address space refer to Chapter 2 Table 2 2 for a complete list of the 64 1 K boundaries Figure 3 shows the module I O Interface Block for the DIO and how it relates to the Short I O Address space In this example the module base address resides on the boundary at 1000H refer to Chapter 2 Section 241 for information on using base address switches This means that the module would occupy the 1K block from 1000 to 1400H 3 240 Manual October 1984 BASE Short 1 i Address Space Even Odd 01H Module identification 3FH 40H 51H 82H 83H interrupt Clear interrupt Vector 85H Flag Outputs Port Direction 87H Port 1 99 8AH VOPort2 1 0 Port 3 8CH DH VO Port 7 90H 91H 3FFH Figure 3 1 The DIO I O Interface Block and the Short I O Address Space 3 2 XVME 240 Manual October 1984 Any location within the DIO s 1K I O Interface Block can be accessed by adding the module base address to the address of the specific location within the I O Interface Block referred to as the I O Interface Block offset For example the module Status Control register is located at address 81H within the I O Interfa
42. his information can read by the system processor on power up to verify the system configuration and operational status Table 3 1 defines the Identification information locations 9 9 XVME 240 Manual October 1984 Table 3 1 Identification Data Offset Relative to Contents ASCII Encoding Module Base in hex x lt The module has been designed so that it is only necessary to use odd backplane addresses to access the I D data Thus each of the 32 bytes of ASCII data have been assigned to the first 32 odd I O Interface Block bytes i e odd bytes 1H 3FH Thus I D information can be accessed by addressing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000H and if you wish to access the module model number I O interface block locations 11H 13H 15H 17H 19H you will individually add the offset addresses to the base addresses to read the hex coded ASCII value at each location Thus in this example the ASCII values which make up the module model number are found sequentially at locations 1011H 1013H 1015H 1017H 1019H 101BH and 101DH 3 4 Descriptions ID PROM identifier always VMEID 5 characters Manufacturer s I D always XYC for modules 3 characters Module Mode Number 3 characters and 4 trailing blanks Number of 1K byte blocks of space
43. ices are designed to introduce and reinforce a variety of module related topics including XYCOM s Standard I O Architecture backplane signal pin descrip tions a block diagram and schematics and a quick reference section 1 3 MODULE OPERATIONAL DESCRIPTION Figure 1 1 shows an operational block diagram of the DIO module 1 1 XVME 240 Manual October 1984 FRONT PANEL CONNECTORS 100 PINS PASS FAIL LED s 8 8 8 64 INTERRUPT FLAG BIDIRECTIONAL INPUTS OUTPUTS CHANNELS INMASKS IDENTIFICATION READ WHITE DATA ADDRESS INTERRUPTER BUFFERS DECODE VMEbus Figure 1 1 Operational Block Diagram of the DIO Module The XVME 240 DIO is an 80 channel TTL level VMEbus compatible I O module Sixty four of the channels are arranged to form 8 byte wide bidirectional I O ports Each port can be individually programmed for either input or output by simply setting or clearing a single corresponding bit in the Port Direction register The DIO provides 8 interrupt input lines to allow externally connected devices to generate VMEbus interrupts on any level The user has the option by setting jumpers 33 310 to control whether the board will latch the interrupt input signals on the rising edge or on the falling edge Each interrupt input line is also maskable via a programmable Interrupt Mask Register In addition the DIO provides an Interrupt Vector Register to store the interrupt acknowledge vector an Interrupts Pend
44. ing Register which shows if there are any interrupts which need servicing and an Interrupt Clear Register which will clear the m interrupts when a 15 written to the corresponding bit location in the register The user determines the interrupt level for the module by setting the three DIP switches in switch S1 The DIO also has 8 flag output lines which can be employed as external interrupt acknowledge lines or as control signal lines to any externally connected devices 1 2 XVME 240 Manual October 1984 DIO module along with all XYCOM I O modules features the XYCOM Standard I O Architecture This design has been incorporated in order to provide a simpler and more consistent method of programming for the entire line of XYCOM modules central core of the XYCOM Standard Architecture is the kemel DIO uses a non intelligent kernel which provides the circuitry required to receive and generate all of the signals for a VMEbus defined 16 bit slave module The non intelligent kernel has following features Control and Address Buffers Base Address Decode circuitry Interrupt _ Decoder Driver Control Status register Module Identification Data Pass Fail LED indicators These features facilitate the operation of the DIO in the following areas e Base Addressing The DIO can be addressed at any one of 64 IK boundaries Short I O Address space e Interface
45. ions and pin outs for connectors Pl and P2 are found in Appendix B of this manual 2 7 DIO MODULE INSTALLATION The XYCOM VMEbus modules are designed to accommodate typical VMEbus backplane construction Figure 2 6 shows a standard VME chassis and a typical backplane configuration There are two rows of backplane connectors depicted here 1 the backplane and the P2 backplane The DIO requires both the Pl and P2 backplane however the only signals used on the P2 backplane are 5V and ground 2 15 XVME 240 Manual October 1984 SYSTEM CONTROLLER GUIDE SLOT SOLDER SIDE MUST GO P1 BACKPLANE COMPONENT SIDE P2 BACKPLANE Figure 2 7 VMEbus Chassis 2 16 XVME 240 Manual October 1984 2 8 INSTALLATION PROCEDURE To install a board the cardcage first make certain that the particular cardcage slot which you are going to use is clear and accessible on both the top and the bottom of the chassis opening Center the board on the plastic guides so that the solder side is facing to the left and the component side is facing to Push the card slowly toward the rear of the chassis until the connectors engage the board should slide freely in the plastic guides Apply straight forward pressure to the two handles on the outer edge of the board until the the right refer to Figure 2 7 CAUTION Do not attempt to install or remove any boards without first turning off the power to the bus and all related external powe
46. is register Interrupt control for intelligent modules is handled by the Interprocessor Communications Protocol Communications Between Processors Communications between an intelligent master an intelligent slave module is governed by XYCOM s Interprocessor Communication IPC Protocol This protocol involves the use of 20 byte Command Block data structures which can be located anywhere in shared global RAM or dual access RAM on an I O module to exchange commands and data between a host processor and an I O module Interprocessor Communication Protocol is thoroughly explained in Chapter 3 of this manual THE KERNEL To standardize its XVME I O modules XYCOM has designed them around kernels common from module to module Each different module type consists of a standard kernel combined with module dependent application circuitry Module standardiza tion results in more efficient module design and allows the implementation of the Standard I O Architecture biggest benefit of standardization for intelligent modules is that it allows the use of a common command language or protocol Interprocessor Communication Protocol in this case The intelligent kernel is based around 68000 microprocessor This design provides the full complement of VMEbus Requester and Interrupter options for master slave interfacing as well as all of the advantages provided by the various facets of the XYCOM Standard Architecture as c
47. it 2 of the Status Control Register refer to Section 3 3 2 When bit 2 of the Status Control Register is set it indicates that one or more of the Interrupt Input lines have interrupt pending Figure 3 10 shows that the Interrupt Pending Flag bit 2 of the Status Control Register is set whenever 1 of the 8 inputs to an 8 input gate 15 set high Thus user software firmware could read bit 2 of the Status Control register to determine if there are any pending interrupt at all and then read the Interrupt Pending Register to determine which particular input lines are transmitting the interrupts As mentioned in the previous paragraph the Interrupt Input lines are all logically to produce a single output This output determines the state of the Interrupt Pending Flag bit 2 of the Status Control Register and is also logically ANDed with bit 3 of the Status Control Register Le the Interrupt Enable Bit The Interrupt Enable Bit is the master control bit for enabling disabling the interrupts generated by the DIO module refer to Section 3 3 2 for information on accessing the Status Control Register If a logic 1 is written to the Interrupt Enable bit the interrupt capability of the DIO module is enabled If a logic O is written to the Interrupt XVME 240 Manual October 1984 Enable bit the interrupt capability of the DIO module is disabled Any interrupt signals which are latched in and passed through the Interrupt M
48. itself after it has been written to and therefore needs no additional attention from user programs Attempting to read from the register will not affect the interrupt input latches or registers but it will return indeterminate data The Interrupt Clear Register should be used after power up or reset to clear all interrupt input latches and registers prior to enabling interrupts SYSRESET and Soft Reset do not clear interrupt input latches 3 3 6 Interrupt Mask Register Base Address 83H This read write register can be employed by user software firmware to mask certain Interrupt Inputs and thus prevent some devices from generating interrupts temporarily Typically a mask might be employed to keep a group of devices from generating interrupts while the interrupt from another device is being serviced The Interrupt Mask Register is positioned immediately following the interrupt input latch Each bit of the Interrupt Mask Register corresponds to specific interrupt input latch output When a logic 1 is written to a specific bit in the register the corresponding interrupt input line will be able to pass a latched interrupt through the mask When a logic O is written to a specific bit in the register the correspodng latched interrupt input will be blocked Figure 3 6 is a bit map of the Interrupt Mask Register 3 10 XVME 240 Manual October 1984 INTERRUPT MASK REGISTER Address 83H Bit Bit Bit Bit
49. modules 6 The I O Kernel How intelligent and non intelligent kernels facilitate the operation of all XYCOM I O modules MODULE ADDRESSING XYCOM modules are designed to be addressed within the VMEbus defined 64K short I O address space The restriction of I O modules to the short I O address space provides separation of program data address space and the I O address space This convention simplifies software design and minimizes hardware and module cost while at the same time providing 64K of address space for I O modules Base Addressing Since each I O module connected to the bus must have its own unique base address the base addressing scheme for XYCOM VME modules has been designed to be jumper selectable Each XVME module installed in the system requires at least a byte block of the short I O memory This divides the 64K short I O address space into 64 IK segments Thus each I O module has a base address which starts on a IK boundary As a result the XYCOM I O modules have all been implemented to decode XVME 560 Manual September 1984 base addresses in 400H increments an intelligent XVME module address signals Al0 A13 are decoded while and 15 must be zero This implies that only the lowest 16 of the possible 64 1K segments are used for intelligent modules On non intelligent XVME modules the six highest order short I O address bits are decoded while the remaining lower order
50. nes which are designed to signal interrupting devices that their interrupts have been serviced However these lines are not physically elec trically dedicated to this application and they may be employed by the user in other ways Le control or signal lines to external devices etc The Flag Outputs are controlled via the read write Flag Outputs Register Each bit in the Flag Output Register corresponds to one of the Flag Output lines Figure 3 9 shows a bit map of the Flag Outputs Register XVME 240 Manual October 1984 FLAG OUTPUTS REGISTER Base Address 86H Bit Bit Bit Bit Bit Bit Bit 1 6 5 4 3 2 Flag Output 0 Flag Output 1 Flag Output 2 Flag Output 3 Hag Output 4 Flag Output 5 Flag Output 6 Flag Output 7 Writing logic Flag Output of 1 Writing logic Flag Output of 0 Figure 3 9 Flags Outputs Register To make an Output Flag transmit a logic 1 a logic 1 must be written to the corresponding bit in the Flag Outputs Register To make an Output Flag transmit logic 0 a logic 0 must be written to the corresponding bit in the Flag Output Register For example to make output flags 3 and 6 a logic I and all others 0 write 48H to the module base address 86H This will put I s in bit positions 3 and 6 and O s in all other locations On SYSRESET or Software Reset the Flag Outputs Register will contain all 0 3 4 INTERRUPTS SUMMARY The DIO module has been designe
51. nterrupt Input Figure 3 4 Interrupt Input Register The Interrupt Input Register bits reflect whether or not the individual Interrupt Inputs have indeed passed interrupt signals through their interrupt edge detection circuits and latched them This register does not reflect the current status of the Interrupt Input lines m 3 8 XVME 240 Manual October 1984 When an interrupt signal has been detected and latched by interrupt input the bit corresponding to that interrupt input in the Interrupt Input Register will be set to logic 1 This bit will remain set until the interrupt input latch is properly cleared by using the Interrupt Clear Register for information using the Interrupt Clear Register refer to Section 3 3 5 NOTE SYSRESET and Soft Reset do not clear the Interrupt Input Register After power up and reset prior to enabling interrupts this register should be cleared by using the Interrupt Clear Register When the interrupt input latch has been cleared and when an interrupt input has not yet detected and latched an interrupt signal the bit corresponding to that interrupt input will be a logic O 3 3 5 Interrupt Clear Register Base Address 84H The Interrupt Clear Register provides the user with the means to clear interrupt input latches registers These latches and registers will have to be cleared after power up reset prior to enabling interrupts and immediately following completion of user
52. o the bus DSO 1A 13 DATA STROBE 0 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D00 D07 DSI 1A 12 DATA STROBE Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D08 D15 B 2 XVME 240 Manual October 1984 Signal Mnemonic DTACK D00 D15 GND IACK IRQT LWORD Table B l VMEbus Signal Identification cont d Connector and Pin Number 1A 16 IB 24 30 IC 13 RESERVED 2B 3 SERCLK SERDAT IB 21 IB 22 Signal Name and Description DATA TRANSFER ACKNOWLEDGE Open collector driven signal generated by a slave The failing edge of this signal indicates that valid data is available on the data bus during a read cycle or that data has been accepted from the data bus during a write cycle DATA BUS bits O 15 Three state driven bi directional data lines that provide a data path between the DTB master and slave GROUND INTERRUPT ACKNOWLEDGE Open collector or three state driven signal from any Master proces sing an interrupt request Routed via the back plane to Slot 1 where it is looped back to become Slot 1 IACKIN to start the interrupt acknowledge daisy chain INTERRUPT REQUEST 1 7 Open collector dri ven signals generated by an interrupter which carry prioritized interrupt req
53. occupied by this module 1 character Major functional revision leve with leading blank if single digit Minor functional revision leve with trailing blank if single digit Manufacturer Dependent Information Reserved for future use XVME 240 Manual October 1984 3 3 2 Module Status Control Register Base Address 081H A major feature of the XYCOM Standard Architecture is the inclusion of an 8 bit status and control register on all intelligent and non intelligent I O modules On the DIO module a non intelligent module this register provides the user with two indicator bits which control the current status of the self test LEDs on the front panel an interrupt pending bit an interrupt enable bit a module soft reset bit and three read write flag bits which can be employed by the user as software flags The Status Control register is accessed at the module base address offset 081H Figure 9 2 shows the register bit definitions for the DIO Status Control byte STATUS CONTROL REGISTER Base Address 081 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Red LED SYSFAIL Interrupt Pending Interrupt Enable Software Reset User Available Flag Bits Figure 3 2 Status Control Register The following list defines the individual bit positions in the Status Control register Bit 7 Bit 6 Read Write These bits are available to the user to be employed as Bit 5 general purpose flags Bit 4 R
54. overed earlier in this appendix The non intelligent kernel provides the circuitry required to receive and generate all of the signals for a VMEbus defined 16 bit slave module The non intelligent kernel also employs the features of XYCOM Standard Architecture as described earlier in this Appendix The simplified diagrams below show the features of both the intelligent and the non intelligent kernels A 9 X VME 240 Manual October 1984 VMEbus VMEbus VMEbus Master and Request interrupter Address Slave v Si Decode RO R3 11 17 ave Interrupt Decoder Control and Address Circuitry 416919 16 016 Driver Butters Module EPROM socket 1 0 PROM EPROM socket microprocessor Control Self Test Control Status Status Register Register 3 4 Px Fail Pass 0 29 Pass LEDs LEDs INTELLIGENT KERNEL NON INTELLIGENT KERNEL Figure 5 Intelligent and Non Intelligent Kernels A 10 XVME 240 Manual October 1984 Appendix B VMEbus CONNECTOR PIN DESCRIPTION XVME 240 Digital Input Output module is physically configured as non expanded double height VMEbus compatible board There is one 96 pin bus connector on the rear edge of the board labeled Pl and one 96 pin bus connector labeled P2 refer to Chapter 2 Figure 2 1 for the locations The pin connections for Pl contain the standard address data and control signals necess
55. r supplies Prior to installing a module you should determine and verify all relevent jumper configurations and all connections to external devices or power supplies Please check the jumper configuration with the diagram and lists in the manual connectors are fully engaged and properly seated Once the board is properly seated it should be secured by tightening the two machine NOTE It should not be necessary to use excess pressure or force to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage obstructions screws at the extreme top and bottom of the front panel Each slot should have plastic guides XVME 240 Manual October 1984 Chapter 3 USING THE DIO MODULE 31 INTRODUCTION This chapter provides the information needed to program the DIO to perform Input and or Output data transfers and how to use the unique design features which are a part of XYCOM I O modules The chapter is arranged in the following order Module base addressing The Module I O Interface Block and how it is addressed Interrupts 32 MODULE BASE ADDRESSING XYCOM modules are designed to be addressed within the VMEbus defined 64K Short I O Address space When the DIO module is installed it will occupy a byte block of the Short I O Address space referred to as the module I O Interface Block The starting address for eac
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57. rpreted as a logic 1 Table 2 2 shows a list of the 64 boundaries which can be used as module base addresses in the Short I O Address space and the corresponding switch settings switches 1 6 from S2 XVME 250 Manual October 1984 Table 2 2 Base Address Switch Options Switches VME base address in VME 15 10 Short Address space 0 0 0 0 0 0 0000H 0 0 0 0 0 1 0400H 0 0 0 0 1 0 0800 0 0 0 0 1 1 0 0 0 1 0 0 1000H 0 0 0 1 0 1 1400H 0 0 0 1 1 0 1800H 0 0 0 1 1 1C00H 0 0 1 0 0 0 2000 0 0 1 0 0 1 2400H 0 0 1 0 1 0 2800H 0 0 1 0 1 1 2C00H 0 0 1 1 0 0 3000H 0 0 1 1 0 1 3400H 0 0 1 1 1 0 3800H 0 0 1 1 1 1 0 1 0 0 0 0 4000H 0 1 0 0 0 1 amp 500H 0 1 0 0 0 amp 800H 0 1 0 0 1 1 0 1 0 1 0 0 5000H 0 1 0 1 0 1 5400H 0 1 0 1 1 0 5800H 0 1 0 1 1 1 5C00H 0 1 1 0 0 0 6000H 0 1 1 0 0 1 6400H 0 1 1 0 1 0 6800H 0 1 1 0 1 1 6C00H 0 1 1 1 0 0 7000H 0 1 1 1 0 1 7500H 0 1 1 1 1 0 7800 0 1 1 1 1 1 7 00 1 0 0 0 0 0 8000H 1 0 0 0 0 1 8400 1 0 0 0 1 0 8800H 1 0 0 0 1 1 8C00H 1 0 0 1 0 0 9000H 1 0 0 1 0 1 9400H 1 0 0 1 1 0 9800H 1 0 0 1 1 1 9C00H 1 0 1 0 0 0 000 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 ACOOH 1 0 1 1 0 0 1 0 1 1 0 1 B400H 1 0 1 1 1 0 B800H 1 0 1 1 1 1 BCOOH 1 1 0 0 0 0 C000H 1 1 0 0 0 1 C400H 1 1 0 0 1 0 C 00H 1 1 0 0 1 1 1 1 0 1 0 0 D000H 1 1 0 1 0 1 D400H 1 1 0 l 1 0 00
58. sponding Interrupt Mask Register bit for this Interrupt Input line refer to Figure 3 10 If the Interrupt Mask bit for an Interrupt Input is set to a logic I it will pass interrupt through the mask If the Interrupt Mask bit for an Interrupt Input is written a logic 0 it will mask out the interrupt signal and temporarily prevent it from generating a VMEbus Interrupt Request Notice that the Interrupt Mask bit does not clear the Interrupt latch it merely keeps the latched signal from going any farther than the AND gate Thus if an interrupt is latched while the corresponding mask bit is set to 0 it will be prevented from passing through the mask but if the same mask bit is written a I before the latch is cleared the interrupt signal will pass through the mask On power up or system reset the Interrupt Mask Register is automatically set so that all bits contain a 0 Thus user software firmware will enable the desired Interrupt Input lines by writing new masks to the Interrupt Mask Register as they are needed The Interrupt Pending Register Bit is located immediately following the point where the Interrupt Input latch output and the Interrupt Mask Register bit are logically ANDed If an interrupt signal is passed through an Interrupt Mask it will set this bit Le logic 717 thus indicating that this particular interrupt line 1 ready to generate an Interrupt Request to the system processor This register bit is related b
59. ssed through the interrupt mask if any and are waiting to be serviced This register directly relates to Bit 2 of the Status Control register refer to Section 3 3 2 If any bit in this register is set Bit 2 of the Status Control Register will also be set Thus Bit 2 of the Status Control Register shows if there are any pending interrupts at all and the 3 11 XVME 240 Manual October 1984 Interrupts Pending register shows which interrupts in particular input lines are pending As mentioned in the previous section Section 3 3 6 the contents of the interrupt input latch and the Interrupt Mask Register are logically ANDed The Interrupts Register contains the result of this AND operation for each interrupt input ine Each bit in the Interrupts Pending Register corresponds to one of the interrupt input lines Figure 3 7 is a bit map of the Interrupts Pending Register INTERRUPTS PENDING REGISTER Base Address 82H Bit Bit Bit Bit Bit Bit Bit Bit 1 6 5 4 9 Interrupt Input 0 Interrupt Input 1 Interrupt Input 2 Interrupt Input 3 Interrupt Input 4 Interrupt Input 5 Interrupt Input 6 Interrupt Input 7 Logic 1 A Pending Interrupt Logic 0 No Pending Interrupt Figure 3 7 Interrupts Pending Register When reading the Interrupts Pending Register Base address 82H a bit containing a means that the corresponding interrupt input has a pending interrupt When register bit is se
60. ster At this point the module is ready to receive interrupt input signals from externally connected devices Typically user software firmware would be set up to monitor 2 of the Status Control register Interrupt Pending Flag When a pending interrupt is detected the Interrupt Pending register could be read to determine which device s is are sending the interrupt s If more than one interrupt is pending concurrently it is the responsibility of user service routines to prioritize the interrupts As each interrupt is handled the Flag Output lines can be used to notify the interrupting devices that servicing is complete When an interrupt is serviced and the interrupting device is notified the corresponding Interrupt Input latch should be cleared by writing to the Interrupt Clear Register If there are still interrupts pending the procedure can be repeated for each one Once all pending interrupts have been serviced the 3 17 XVME 240 Manual October 1984 Interrupt Input Register could be read to determine if there are any latched interrupts which are being masked out The mask can then be rewritten to allow the masked interrupts to become pending interrupts The pending interrupts can now be serviced by the handler routine in the same fashion as shown above Interrupts can be disabled in one of three ways 1 By resetting the system 1 6 the Mask Register will be reset to mask out all interrupts and the Interrupt Enable
61. t to it means that the corresponding interrupt input has no pending interrupt It is possible for several interrupt inputs to have interrupts pending at one time In this case the user software firmware will have to prioritize the interrupting devices to establish an interrupt handling order 3 3 8 Interrupt Vector Register Base Address 85H This read write register is used to hold the interrupt service vector which will be transmitted to the system processor during the interrupt acknowledge sequence allowing automatic entry into a service routine without device polling This is an 8 bit register arranged with the MSB and the LSB as shown in Figure 3 8 3 12 XVME 240 Manual October 1984 INTERRUPT VECTOR REGISTER Base Address 85H MSB LSB Figure 3 8 Interrupt Vector Register NOTE The Interrupt Vector Register powers up to an indeterminate state and it must be programmed before interrupts are enabled The vector register is programmed by writing the vector address to the module base address 85H The vector register is a latch and a vector address written to it will not change until a new vector is written in The actual vectors and how they are used is dependent upon the system processor Please refer to your system processor operating manual for information on interrupt vectors 3 3 9 Flag Outputs Register Base Address 86H The DIO provides 8 Flag Output li
62. tics and configuration checking must be performed by the system host 3 3 3 Module I O Ports Base Address 88H to SFH The 64 I O channels used by the DIO module are divided into 8 bidirectional ports with 6 channels to a port These I O ports are numbered thru 7 Figure 3 1 shows that the module I O ports are addressed consecutively within the module I O Interface Block from 88H to Table 3 1 lists I O Interface Block addresses assigned to each bidirectional port Table 31 Module I O Port Addresses Module I O Port Any I O port can be accessed I O Interface Block Address by adding the module base address to the particular Interface Block offset for that port For example port 3 is located at address 8 3 6 XVME 240 Manual October 1984 in the I O Interface Block and if the base address of the module 1s set at 10008 then I O Port 8 can be accessed at 108BH Module Base IO Interface I O Address Block Offset Port 3 1000H 8BH 108BH The I O ports are all read write registers and they can be read from or written to at any time The data read will always reflect the state of the actual port lines The data latch for each port 1s cleared to OOH during any VME SYSRESET or software reset 9 9 9 1 Port Direction Register Base Address 87H As mentioned in the previous section the 8 I O ports are bidirectional This means that each port can operate as an output port or
63. tion of the module s operational condition The next area of the module Interface Block base address 82H roughly ROF is module specific and it varies in size from one module to the next It is in this area that the module holds specific status data and pointer registers for use with IPC protocol All intelligent XVME I O modules have an area of their I O Interface Blocks defined as dual access This area of memory provides the space where XVME slave I O modules access their command blocks and where XVME master modules could access their command blocks ie master modules can also access global system memory The remainder of the I O Interface Block is then allocated to various module specific tasks registers buffers ports etc Figure 2 shows an address map of an XVME module interface block and how it relates to the VMEbus short I O address space Notice that any location in the I O Interface Block may be accessed by simply using the address formula Module Base Address Relative Offset Desired Location A 3 XVME 250 Manual October 1984 BASE 1 Short 1 Address Space Even Odd 0000 o meon 2241 Module 01H Identification 1400H 47EH 7 Status Control 81H Module Dependent A For use with Interprocessor Communication Protocol 3FFH Figure A 2 XVME I O Module Address Map MODULE SPECIF
64. to 10008 in the Short Memory and if Ports 4 and 7 need to be configured as outputs after power up it will be necessary to write YOH to address 1087H This write operation will set bits 4 and 7 of the port direction register to logic I and will therefore configure ports 4 and 7 as output ports Changing the direction of a port has no effect on the data stored in the port s data latch 3 3 4 The Interrupt Input Register Base Address This bit register provides a convenient location to allow user software firmware to determine which externally connected device is sending an interrupt Each interrupt input has its own Interrupt Edge Detection circuitry and interrupt latch refer to Section 2 4 8 of this manual for information on interrupt edge detection The Interrupt Input Register is a read only register and it is positioned immediately after the Interrupt Edge Detection circuitry latch Each bit of the Interrupt Input Register corresponds to one of the 8 interrupt input lines refer to Chapter 2 for the physical location of the interrupt input pins in connectors JKI and JK2 Figure 3 4 shows a bit map of the Interrupt Input Register INTERRUPT INPUT REGISTER Base Address 80H Bit Bit Bit Bit Bit Bit Bit 16 5 14 13 2 i Interrupt Input 0 Interrupt Input 1 Interrupt Input 2 Interrupt Input 3 Interrupt Input Interrupt Input Interrupt Input QV I
65. uests Level seven is the highest priority LONGWORD _ Three state driven signal to indi cate that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which will be used as the clock for a serial communication bus protocol which is still being finalized A reserved signal which will be used as the transmission line for serial communication bus messages 3 XVME 240 Manual October 1984 Table B l VMEbus Signal Identification cont d Connector Signal and Mnemoni Pin Number Signal Name and Description SYSCLK SYSTEM CLOCK A constant 16 MHz clock signal that is independent of processor speed or timing This signal is used for general system timing use SYSFAIL SYSTEM FAIL Open collector driven signal indicates that a failure has occurred in the system This signal may be generated by any module on the VMEbus SYSRESET SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation STDBY STANDBY This line supplies 5 to devices requiring battery backup Tv 45 Vdc Power Used by system logic circuits 12 Power Used by system logic
66. uirements Major Component Locations Jumpers Switches Base Address Switches Address Space Selection Super visor Non Privilege Address Modifier Reference IACKIN IACKOUT Daisy Chain Interrupt Level Switches BGxIN BGxOUT Daisy Chain Interrupt Input Edge Detection Option Front Panel Connectors and P2 Connectors DIO Module Installation Installation Procedure USING THE DIO MODULE Introduction Module Base Addressing The DIO Interface Block Module Identification Data Module Status Control Register Module I O Ports Port Direction Register The Interrupt Input Register Interrupt Clear Register Interrupt Mask Register Interrupts Pending Register Interrupt Vector Register Flag Outputs Register Interrupts Interrupt Sequence XYCOM Standard I O Architecture VMEbus Connector Description Schematics and Diagrams Quick Reference Guide PAGE 2 9 2 11 2 15 2 15 2 17 Wee O 1 B 1 C 1 D 1 XVME 240 Manual October 1984 TABLE OF CONTENTS continued LIST OF FIGURES FIGURE TITLE PAGE 1 1 Operational Block Diagram of the DIO Module 1 2 Major Component Locations 2 2 Switch Bank S2 Base Address Switches 2 4 Switch Bank S2 2 6 Switch Bank Interrupt Level Select Switches 2 8 Interrupt Input Edge Selection Jumper 210 2 10 Connector Pin Numbering Scheme 2 11 VMEbus Chassis 2 16 The DIO I O Interface Block and the Short
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