S5U1C33L05D1 USER MANUAL
Contents
1. it enables booting from external 16 bit NAND Flash memory 6 MemoryMap The jumpers JP10 and JP11 control the address mapping of the 16MB NOR Flash memory and the 8MB SRAM to areas 9 10 and area 17 18 See following setting to see the memory map Do not use any combination other than those appearing below JP10 1 2 Short JP10 2 3 Short JP11 1 2 Short JP11 2 3 Short OXOFFF FFFF Area 17 18 050 0000 NOR FLASH SRAM mee 38 rove t ed mm ar Vi T Table 2 Memory Map of S5U1C33L05D1 Area Address Note Because this board supports large memory space the CEFUNC must be set to 1x 7 WO Port Assignments Pin Name Used By Used By po Tio MNCISD soo P14 DCLK Keys Key Inputo LCAS SDRAM SDCAS K51 Key Input ii HCAS SDRAS K52 Key Input2 P21 SDWE K53 Key Input3 SDCKE P03 Key Input4 SDCLK K60 Microphone ADC inputsO Input CE7 SDCE TMO Extend Audio P61 SDA10 Output Ports LDQM TM4 UDQM TM5 LCD Interface FPFRAME P31 FPLINE P32 FPSHIFT Sequential ROM SQCE DRDY SQRD FPDATO PD1 SQLALE FPDAT1 PD2 SQUALE FPDAT2 i FSOUTO FPDAT3 FSINO FPDAT4 SOUT FPDAT5 SIN1 FPDAT6 POWER control FPDAT7 NAND Flash amp SMWE POWER control Smart Media SMRE DOFF control P24 Card CLE Touch Panel ADC input2 P25 LE RY BY CE of NAND Flash Smart Media CE of Smart Media Card Card SM card voltage detector PDS SM card insert detector CE6 Poe SM card protect detector Table 3 Pin assi2. 17 18 But changing the JP10 and JP11 can exchange the address of NOR Flash memory and SRAM Because of lay out problem when using different chips the meaning of JP10 and JP11 is different The following table shows the setting of JP10 and JP11 JP10 1 2 Short JP10 2 3 Short Area anaress JP11 1 2 Short JP11 2 3 Short OXOFFF FFFF Area17 18 ando 0000 NOR FLASH SRAM 0x00FF FFFF Area 9 10 EO SRAM NOR FLASH Table 5 Using KBB05B400M 10 1 2 SDRAM In S5U1C33L05D1 a 32MB SDRAM is used which is located into area 13 14 The following figure shows the connection of SDRAM S1C33L05 32MB SDRAM BCLK P60 FOSC1 SDCLK CLK P20 DRD CKE CKE A 15 14 BA 1 0 A 13 12 10 1 A 12 11 9 0 A10 P61 SDA10 D 15 0 DQ 15 0 P62 LDQM LDQM P63 UDQM UDQM CE7 CE13 P53 SDCE CS UCAS PA1 SDRAS RAS LCAS PAO SDCAS CAS P21 DWE GAAS SDWE WE Figure 3 The Connection of SDRAM Note In SDRAM clock line a 330hm resistor is placed in serial to keep signal integrity 10 1 3 NAND FLASH MEMORY Two kinds of NAND Flash memory are supported in S5U1C33L05D1 They are KBB05B400M and K9F1G16U0M Each one has different size The following table shows the configuration CHIP SIZE KBB05B400M 32MB K9F1G16U0M 128MB Table 6 Size of NAND Flash in S5U1C33LO5D1 In S5U1C33L05D1 JP13 and JP14 are used to select different NAND Flash See following table for JP13 and JP14 setting en JP13 1 2 Short JP13 2 3 Short p JP14 1 2 Sho
3. KEYO 12 8 Q 15 13 BSH Figure 7 Extended Output Ports Implementation The following table shows the register of the extended output ports In order to simplify the circuit of the extended output ports reading the register of the extended output ports is not supported Register name Address Bit A Pots 040 0000 DE SCA data register DD Q13 Qi3outputdata DB KEYOTT KEYOTI outputdata DS REVOS KEVO9 outputdata DB KEVOS REVOS outputdata De KEYS KEVOS outputdata 04 KEYS KEYOG outputdata DO KEVOO KEVOoouiputdaa In S5U1C33L05D1 Q15 is used to drive red LED Q14 is used to drive green LED Q13 is used in audio circuit PWM output module KEYO 12 0 is used in key matrix 10 3 EXTENDED I F In S5U1C33L05D1 an extended interface is provided for adding additional circuits In this extended interface all the bus such as data bus address bus and control bus are isolated with the internal system bus The following diagram shows the architecture of the extended interface D 15 0 A19 ys 4CE788 RD if il amp O CE14 KBE E ko A18 EE q EXT CS0 Ha A17 OF A lt EXT_CS1 EXT_CS2 O Figure 8 The Diagram of Extended Ports Implementation The data bus driver and the chip select decoder is implemented in CPLD while control bus driver is implemented via the bus driver 74LVTH16244 The address of the extended chip select signal is sh
4. PD5 RY BY CD 3V_SW WP_SEN Figure 6 The Connection between S1C33L05 and Smart Media Card Because the smart media is the external card a data bus driver is used to isolate the system data bus The smart media card has some additional signals to indicate the card information to the S1C33L05 The following table shows the additional signal E Signal 07 1 SE 3V SW Not 3V card HWP SEN Write protect Write not protect Table 8 Addition signal of smart media card The smart media card and the NAND Flash can be used simultaneously Because the address of the smart media is also mapped in area 15 16 When access the smart media card to avoid conflicting with the NAND Flash on the board the following steps must be followed Set the P51 output register high D 1 0x300022 1 b1 Set the P51 I O register as output D 1 0x300023 1 b1 Switch to P51 function D 3 2 0x30004A 2 b01 Access the smart media card Switch to CE15 function D 3 2 0x30004A 2 b00 AE Nt 10 2 EXTEND OUTPUT PORTS In S5U1C33L05D1 the I O ports of the S1C33L05 is not enough some output ports are extended via the CPLD XC9572XL Totally16 output ports are extended through CPLD 13 output ports are used for the key matrix 2 output ports are for LED control while 1 output port for audio circuit control The following diagram shows how to extend the output ports in CPLD D 7 0 4CE788 A19 HBSL KEYO 7 0 WR X D 15 8
5. S5U1C33L05D1 USER MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson Seiko Epson reserves the right to make changes to this material without notice Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency O SEIKO EPSON CORPORATION 2004 All rights reserved 10 OVERVIEW A TS 4 PACKAGE si i AAA AA AAA AAA AAA AAA 5 BLOCK DIAGRAM isiciccccsicscccesicdecassscaeedevscvecsesvevesseveedevaesveseccesucvessesuevousesicvecsdsvovessesesveceess 6 POWER SUPPLY sisicisicciacacccesccevescccccvsucdevessctsccesssetesavseedescosccdseestvcves
6. T_BSH 30 Reserved 60 5V 90 EXTA2 120 5V 9 Jumpers Refer to Figure 1 The Layout of S5U1C33L05D1 JP2 Booting selector 1 2 Short Booting from on board NAND Flash 2 3 Short Booting from area 10 NOR FLASH SRAM eo JP3 Internal PLL use or not 1 2 Short PLL OFF 2 3 Short PLL ON e JP4 JP5 JP6 JP7 JP8 JP9 IrDA port is SIO 0 no serial port IrDA port is SIO 0 Serial port is SIO1 Note Other settings are forbidden e JP10 JP11 Using KBBO5B400M or KBBO6A300M JP10 JP11 2 3 Short 2 3 Short Area 9 10 as SRAM Area 17 18 as NOR Flash 1 2 Short 1 2 Short Notes Other settings are forbidden e JP12 Notes 1 SDRAM must be less than 16MB and located into area 13 2 Smart media card can not be used e JP13 JP14 Function JP13 JP14 2 Using NAND Flash in MCP 2 3 Short Using external single device of NAND Flash 1 2 Short 1 2 Short 10 Module Description 10 1 MEMORY 10 1 1 External Memory NOR Flash and SRAM The external memory here means external NOR Flash memory and external SRAM do not include the external NAND Flash memory External NAND Flash memory will be described in another section The SAMSUNG MCP device is used in S5U1C33L05D1 board It is KBBO5B400M The following table shows the configuration CHIP NOR FLASH SRAM KBB05B400M 16MB Table 4 S5U1C33L05D1 Memory Configuration In default setting NOR Flash memory is located into area 9 10 while SRAM is located into area
7. gnment of S1C33L05 P20 BCLK TU a de O O 6 o o o a a o A Ww v w A e gt N o A P62 ros PCO PC1 PC3 PB2 PB5 Pers IC K63 pa v U AJA v o q 8 Connectors JP1 and J1 is for connecting the ICD33 debugging tool J8 is for connecting the S5U1C33L05D1LCD board J9 is for connecting the S5U1C33L05D1PWM or S5U1C33L05D1 DAC board J12 is for connecting the S5U1C33L05D1KEY board J11 and J13 is for connecting the extended circuits 8 1 1 JP1 Connector DCLK DST2 8 1 3 J8 Connector ooooooooj z sn EJ EE tel te ee 5 FPDAT3 14 FPFRAME 23 GND 32 Pos 6 FPDAT2 15 GND 24 31V 33 GND 8 FPDATO 17 Kea 26 5V 35 Pat 9 GND is kes 27 GND 36 P42 8 1 4 J9 Connector Pin Name No GND GND TM1 TMO No Pin Name 2 GND GN 5 TM 6 Tmo ooooooooj c 000000000 KEYO12 6 KEYO7 KEYO2 KEYO11 KEYO6 KEYO1 KEYO10 8 KEYO5 KEYOO KEYO9 9 KEYO4 KEYO8 KEYO3 8 1 6 J11 and J13 Connector 90 0 90 9 90 9 09 00 0 00 0 06 9 99 0 0 0 O O O O Os 0000 0590 O O O O Oro 009 99 0 00 0 0 0000000000000 000000 6 N 36 NC 66 EXT D9 96 EXTAS 8 Nc 38 waT 68 EXT D2 98 EXTA po NG 39 NC 69 EXTD10 99 EXTAS 20 NC 50 ExT Cso 80 EXT DS 110 EXT At9 26 NC 56 ExT CS2 86 EXT BSL 116 NC 291 NO 59 N 89 GND 119 EX
8. ncludes 16MB of FLASH memory 4MB of SRAM 32MB of NAND Flash memory 32MB SDRAM and three connectors for interfacing with the S5U1C33L05D1LCD board 5U1C33L05D1PWM or S5U1C33LO5D1DAC board and the ICD33 debugger It also provides an external interface for additional I O The S5U1C33L05D1 board is thus also the core of a development environment for developing applications for the S1C33L05 JP5 JP7 ee m Crwe4 22 36 v t vem J2 JP2 JP10 211 T 112 Figure 1 The Layout of S5U1C33L05D1 2 Package The S5U1C33L05D1 package contains the following items 1 S5U1C33L05D1 board TTT 2 S5U1 C33L05D1 LCD board LCD display board TTT 3 S5U1C33L05D1 PWM board PWM audio outputboard roo 4 S5U1 C33L05D1 DAC board Optional TIETE III eee 5 S5U1 C33L05D1 KEY board TTT 6 AC adapter 5V DC output with cable sannana 7 USB cable TTT TTK 8 S5U1C33L05D1 user s manual this document III III III III EESTI 3 BlockDiagram POWER LDO POWER 3 1V 1A SV 2A DA converter SPI interface PWM output POWER LDO 1 8V 0 5A MCP ICD interface NOR Flash NAND Flash SRAM SM card Microphone lt 5 NAND interface 3 COMBO S1C33L05 NOR Flash MMC SRAM SPI interface Extended Ports E Bus interface A o LCD Panel NAND Flash a O Es Touch Panel w un Extended Ports Bus interface B Serial Ports IRDA Keys Figure 2 The Block Diagram of S5U1C33L05D1 4 Power Supply Connecting a 5 volt p
9. oesvedsvedsscsscessscdescvsvsvecece 7 CLOCK AND BOOT SETTINGS i cicsccssssccssssssssccsuetcvcestesccedsvctesccsvedseccsiescusssectesevsucdcveessessceess 7 MEMORY MAP isss si Rain a s nina Dan diera iO di dveesdacseessvauescesvevesedssascuessvensieess 8 TO PORT ASSIGNMENTS ss dass NL noi varas asteca save sas duas cia ganda 9 CONNECTORS sistsssev staarita s v ev u sde s rain a a tic an idos alados a a die do cual ev d sv ita 10 8 1 1 TPL CORRECTO a A A SS 10 8 1 2 TLECONNECION LAA ANA A NN 10 8 1 3 TE CIMA A aries itch Banc EC 11 8 1 4 IS CONE CLONE sda sra ar AR Kate PRGA na ia 11 8 1 5 JAD CONNOR SS UT INDL OO ESSE RO bathe Ed ee ek E A RT 1 8 1 6 PLE and ILS Conneolo Esso a a ia sn 12 IO A si 13 MODULE DESCRIPTION ciu cvescievestsesessiccasaecsdccsevcsecadcscsisesdset scsdecscecdesstiestesstdcessesstecse 14 LOL MEMORY A a 14 10 1 1 External Memory NOR Flash and SRAM 0 14 402122 SDRAM tra ta voi ls ska a Sp EUR a SM matat a o O cd ts 15 10 13 NAND FLASH MEMORY a talvel 15 102 EXTEND OUTPUT PORTS 20533 cde nt Teto ds Sa re ERA o Dc Scr tala 18 10 3 EXTENDED sasssa oia 19 IOA REY 14 a nd e 21 105 SOUNDANPU 135 gostas vasta ralis Staten DON a ia bae Tat 21 10 6 SOUND OUTPUT aeaa aee aeania dan aa ole mia kalal lna ad aa Sulestik delo aada 21 1 Overview The S5U1C33L05D1 board demonstrates the S1C33L05 a 32 bit Seiko Epson microcomputer whit a built in STN LCD controller The circuit board i
10. ower supply to the DC IN connector J7 lights the POWER LED and starts the board Because S5U1C33L05D1 is for world wide a power adaptor Input AC 100 240V output DC 5V 2A is selected The board derives its internal 3 1 volt and 1 8 volt power supplies from this single Svolt power supply The S1C33L05 in this board operates at 3 1V for I O and 1 8V for the core while others parts such as memory operates at 3 1V The reason why 3 1V is selected is described as follows Notes 1 The maximum power supply of the memory devices KBBO5B400M is just 3 1V 2 When using USB function of S1C33L05 the I O voltage of S1C33L05 must higher than 3 0V 5 Clock and Boot Settings The S5U1C33L05D1 uses 48MHz ceramic special designed for USB from Murata as the OSC3 clock The 32 768KHz crystal is also used for OSC1 clock The default setting of JP3 1 2 turn off the S1C33L05 internal PLL When setting JP3 to 2 3 the internal PLL is on The S1C33L05 working frequency is depending on the OSC3 clock setting of PLL and 1C33L05 internal register For details please refer to S1C33L05 user s manual The following table shows the recommended clock setting OSC3 PLL CPU Bus divider setting frequenc frequenc Default 24MHz 24MHz 48MHz 24MHz Table 1 Recommendation of Clock Setting The default setting of JP2 2 3 enables S1C33L05 booting from the external Nor Flash that is address 0xC00000 in the Flash memory When setting the JP2 to 1 2
11. own as follows JP10 1 2 Short JP10 2 3 Short Alea sas JP11 1 2 Short JP11 2 3 Short Mesias 20 OT NOR FLASH SRAM 0x0800 0000 0x07FF FFFF Area15 18 0404000000 NAND FLASH NAND FLASH Ox03FF FFFF Area 13 14 0402000000 SDRAM SDRAM 0x01FF FFFF Area 11 12 0x0100 0000 _ NOR FLASH NOR FLASH Area 9 10 ES Sent nay O External Area 2 External Area 2 Area 7 8 AAA AA External Area 1 External Area 1 0x004A_0000 0x0049 FFFF 0x0048 0000 External Area 0 External Area O 0x0047_FFFF 0x0040 0000 _ Extended I O Extended I O Table 9 The Address of the Extended Area 10 4 KEY Totally 65 keys are supported in S5U1C33L05D1 These 65 keys are implemented via a 13x5 matrix In these keys 6 of them has two parts One part is on the main board the other part is on the key board That means in the S5U1C33L05D1 main board there are 6 keys in the main board which has the same function as the keys in the key board The key matrix is shown as follows KEYO 12 0 13x5 6 Keys S1C33L05 er Key Matrix E Main Board ST keyboard Figure 9 Key Matrix Connection Note that the register of the 13 output signals from CPLD is write only Software can not detect the state of the output signals via reading the data register 10 5 SOUND INPUT Please refer to EPSON S1C33 Family APPLICATION NOTES 10 6 SOUND OUTPUT Please refer to EPSON S1C33 Family APPLICATION NOTES
12. rt JP14 2 3 Short KBB05B400M K9F1G16U0M Table 7 NAND Flash Configuration The connection between the S1C33L05 and NAND Flash of SAMSUNG MCP is shown as follows S1C33L05 KBB05B400M D 15 0 D 15 0 CE5S CE15 CE15 amp 16 P51 CE P35 BUSACK SMRE RE WRL WR WE WE P25 TM3 SCLK2 ALE P24 TM2 SRDY2 CLE A25 P40 WP PD5 RY BY Figure 4 The Connection between S1C33L05 and SAMSUNG MCP When using KBBO6A300M or KBBO6A400M the chip select signal can not be used as GPIO Otherwise when CPU access the NAND Flash a writing operation to the external SRAM may cause the NAND Flash reading error Because the NAND Flash use the system write signal instead of SMWE The following diagram shows the the connection between the S1C33L05 and NAND Flash K9F1G16U0M S1C33L05 K9F1G16U0M D 15 0 D 15 0 CE5 CE15 CE15 amp 16 P51 CE P35 BUSACK SMRE RE P34 BUSREQ CE6 SMWE Abs P25 TM3 SCLK2 Gre P24 TM2 SRDY2 WP PDE RY BY A25 P40 4 7K Figure 5 The Connection between S1C33L05 and K9F1G16U0M When using K9F1G16U0M the chip select signal can be used as GPIO because the write signal using the NAND Flash write signal 4SMWE The S5U1C33L05D1 also supports smart media card the connection is shown as follows K9F1G16U0M Data D 15 D 15 0 BUS Drive nee CE8 CE14 P54 CE S1C33L05 P35 BUSACK SMRE RE P34 BUSREQ CE6 SMWE WE P25 TM3 SCLK2 ALE P24 TM2 SRDY2 CLE A25 P40 WP
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