Xilinx Vivado Design Suite Tutorial: Programming and Debugging
Contents
1. Server muscarial 10521 Version 14 4 lt Back Net gt Finish Cancel Figure 20 CSE Hardware Target Chooser Debugging with ChipScope www xilinx com 26 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 6 Leave these settings at their default values as shown in Figure 21 Click Next Open New Hardware Target Set Hardware Target Properties Set properties for the selected hardware target DEVICE 5N 210203338750 TYPE digilent_plugin FREQUENCY 15000000 Hz Figure 21 CSE Hardware Target Parameter Settings 7 Click Finish as shown in Figure 22 Open New Hardware Target Open Hardware Target Summary Server Settings Name muscarial Port 10571 Target Settings Name digilent_plugin SN 210203338750 DEVICE N 210203338750 TYPE digilent_plugin FREQUENCY 15000000 Hz LNA CO i j j i V VA D O To connect to the hardware described above click Finish Figure 22 Open Hardware Summary Debugging with ChipScope www xilinx com 27 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 8 Wait for the connection to the hardware to complete The dialog in Figure 23 appears while hardware is connecting Open Hardware Target id Opening target Figure 23 Open Hardware Target 9 Once the connection to the hardware target is made the dialog shown in Figure 24 ap2. is phase _tdata_sine_mid 3 3 Bus Net Properties Ctri e i Copy Ctrl e Unmark Debug it it it iit iit ib af Assign ta Debug Port won A ee Figure 5 Adding Nets from the Netlist Tab Note With the Debug tab selected you can see the unassigned nets you just selected In Vivado IDE you can also see the green bug icon next to each scalar or bus which indicates that a net has the attribute mark_debug true as shown in Figure 6 Synthesized Design xc7k325tffg900 2 active Debug E a Weer ab ees 23 Name i Unassigned Debug Nets 30 E i GPIO_BUTTONS dbi 2 H ji GPIO_BUTTONS _dly 2 jk GPIO_BUTTONS_IBUF 2 n GPIO_ BUTTONS re 2 H sinegen_demo H Nets 114 E B Primitives 3 E E u aca 0 debounce__ 1 H A U_DEBOUNCE 1 debounce H 2 U_FSM fs 5 i U SINEGEN fsinegen a la Nets 309 Ee ii i 0 20 fe n_O_count_reg 2 amp n_O_sine_h_dly_reg 20 i plusOp__0 20 E plusOp__1 10 R 20 Peers ase tdata_sine_mid FHE Figure 6 Mark_Debug Nets Post synthesis Running the Set Up Debug Wizard 1 From the Debug tab by clicking on the tab or Tools menu select Set Up Debug The Set Up Debug wizard opens 2 Click through the wizard to create Vivado logic analyzer debug cores keeping the default settings Debugging with ChipScope www xilinx com 13 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and
3. Vivado Design Suite Tutorial Programming and Debugging UG936 v2012 4 December 18 2012 amp XILINX 2 XILINX a Notice of Disclaimer The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain pr
4. attribute keep string attribute mark_debug of sine Signal is true attribute mark_debug of sineSel signal is true Verilog true wire sine true wire sineSel mark_debug mark_debug e Right click and select Mark Debug or Unmark Debug on Synthesis netlist e Usea Tcl prompt to set the mark_debug attribute For example set mark_debug true get_nets sine This applies the mark_debug on the current open netlist In this tutorial you will learn how to add debug nets to HDL files and the synthesized design using Vivado IDE 1 From the Synthesis pull down click Open Synthesized Design Note Before proceeding make sure that the Flow Navigator on the left panel is enabled Use CtrI Q to toggle off and on Secondly the window layout must be set to Debug At this point you will get a Synthesis is Out of Date warning Click Open Design 2 Click the Debug tab if it is not already selected 3 Expand Unassigned Debug Nets folder In Figure 4 you should see those debug nets that were tagged in the sinegen_demo vhd with mark_debug attributes as shown in Figure 3 Debugging with ChipScope www xilinx com 11 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP qo attribute mark debug of GPIO BUTTONS db signal is true attribute mark debug of GPIO BUTTONS dly signal is true attribute mark debug of GPIO BUTTONS re signal is true component sinegen
5. 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 2 In the Waveform window verify that there is activity on the 20 bit sine signal as shown In Figure 30 Hardware Session muscarial2 10521 digdent_plugin SW 210203338750 Ta 3 Properties 3 oe O GPIO_BUTTONS_db 1 0 Fae E GPIO_BUTTONS_IUF 1 0 1 Sieg E MU SINEGEN sel 1 0 Capen 0 U_SINEGEN sine 19 0 bl a a 2 x FE Figure 30 Output Sine Wave Displayed in Digital Format Displaying the Sine Wave 1 Right click U_SINEGEN sine 19 0 signals and select Waveform Style gt Analog as shown in Figure 31 Note Notice that the waveform does not look like a sine wave This is because you must change the radix setting from Hex to Signed Decimal as described in the following subsection Figure 31 Output Sine Wave Displayed in Analog Format High Frequency 1 Debugging with ChipScope www xilinx com 31 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 2 Right click on U_LSINEGEN sine 19 0 signals and select Radix gt Signed Decimal You should now be able to see the high frequency sine wave as shown in Figure 32 instead of the square wave Figure 32 Output Sine Wave Displayed in Analog Format High Frequency 2 Correcting Display of the Sine Wave To view the mid and low frequency output sine waves perform the following steps 1 Cycle the sine wa
6. Tutorial design files For details on locating design files see Getting Started page 7 Debugging with ChipScope www xilinx com 6 UG936 v2012 4 December 18 2012 gt XILINX Step 1 Creating and Implementing an RTL Project in the Vivado Integrated Design Environment Board Support and Pinout Information Table 1 1 Pinout Information for the KC705 Board Pinout Locations Function CLK_N AD11 Clock CLK_P AD12 Clock GPIO_BUTTONS 0 AA12 Reset GPIO_BUTTONS 1 AG5 Sine Wave Sequencer GPIO_SWITCH Y28 a Circuit LEDS_n 0 AB8 Sine Wave Selection 0 LEDS_n 1 AA8 Sine Wave Selection 1 LEDS_n 2 AC9 Reserved LEDS_n 3 AB9 Reserved Step 1 Creating and Implementing an RTL Project in the Vivado Integrated Design Environment To create and implement an RTL project do the following e Get started by unzipping the tutorial source files and launching the Vivado Integrated Design Environment IDE e Create a New Project with the New Project Wizard e Synthesize the design Getting Started 1 In your c drive create a folder called Vivado_Debug 2 Find the tutorial source files Design file location http www xilinx com support documentation sw_manuals xilinx2012_3 ug936 vivado debug design files zip The tutorial and design files might be updated or modified in between software releases on the Xilinx website where you can download the latest version of the materials 3 Un
7. port elk in std Logic reset in std Logic sel in std logic_vectoril downto 0 sine out std logic vector 19 downto 0 1 1 end component Figure 3 VHDL Example Using MARK_DEBUG Attributes Synthesized Design xc7k325tffg900 2 active Debug Uo ie i Unassigned Debug Nets 5 6 dew GPIO BUTTONS db jh GPIO BUTTONS db 0 jh GPIO BUTTONS db 1 dew GPIO BUTTONS dly de GPIO_BUTTONS dly O de GPIO BUTTONS dly 1 dew GPIO BUTTONS re de GPIO BUTTONS re 0 de GPIO BUTTONS re 1 Figure 4 Unassigned Debug Nets Post synthesis 4 Select the Netlist tab to expand Nets Select the following nets as shown in Figure 5 for debugging o GPIO_BUTTONS_IBUF 2 Nets folder under the top level hierarchy o sine 20 Nets folder under the U_SINEGEN hierarchy o sel 2 Nets folder under the U_SINEGEN hierarchy Note These signals represent the significant behavior of this design and will be used to verify and debug the design in subsequent steps 5 Right click the selected nets and select Mark Debug Debugging with ChipScope www xilinx com 12 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP 6 Primitives 31 E U DEBOUNCE_0 debounce_ 1 U DEBOUNCE 1 debounce o U FSM fsm El U_SINEGEN sinegen Nets 296 G minusOp 0 20 Ge i n_O count_reg 2 G n_0 sine _h_dly reg 15 Ge it plusOp D 20 G i plusOp 1 10 ch 8 ieee
8. Adding Debug IP Using the HDL Instantiation Method The HDL Instantiation method is one of the two methods that are supported in Vivado Debug Probing For this flow a you will have to generate an ILA 2 0 IP using the Vivado IP Catalog and instantiate the core in a design manually as you would with any other IP If you choose to use this method then you can skip all the instructions described under the Using the Netlist Insertion Method section 1 With this flow use sinegen_demo_inst vhd as the top level VHDL file instead of Sinegen_demo vhd 2 Addila_v2_0 0 xci IP 3 Synthesize the design HDL Debug Flow Using Synopsys Synplify Pro Synthesis Tool Skip this section in its entirety if you are not using the Synopsys Synplify Pro synthesis tool as a part of your design flow This simple tutorial shows how to do the following e Create a Synplify Pro project for the wave generator design e Mark nets for debug in the Synplify Pro constraints file as well as VHDL source files e Synthesize the Synplify Pro project to create an EDIF netlist e Create a Vivado project based on the Synplify Pro netlist Use the Vivado IDE to setup and debug the design from the synthesized design using Synplify Pro Create a Synplify Pro Project 1 Launch Synplify Pro and select File gt New Set File Type to Project File Project as highlighted in Figure 7 In the New File Name box enter synplify_1 Click OK Debugging with ChipScope www xi
9. File button on the right of the dialog box Click Add Files and navigate to the Vivado_debug src folder and select the sinegen_demo_kc705 xdc file This file has the appropriate constraints needed for this Vivado project Ensure that Copy Constraints into Project is checked Click Next 7 Under Default Part select Boards and then select the Kintex 7 KC705 Evaluation Platform Click Next Debugging with ChipScope www xilinx com 21 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP 8 Under New Project Summary ensure that all the settings are correct and click Finish Add Debug Nets to the Project 1 In Vivado IDE in Project Manager in the left panel select Open Synthesized Design from the Synthesis folder 2 You should be able to see all the nets that are marked for debug as shown in Figure 16 Synthesized Design xc7k325tffg900 2 active Jebu n _ow x EEL ECFETIT Hame W Unassigned Debug Mets 8 GPIO_BUTTONS_db a GPIO_BUTTONS_db 0 Sa GPIO_BUTTONS_db 1 i GPIO_BUTTONS_dly_1 See GPIO_BUTTONS_dly_1 0 i GPIO_BUTTONS_dly_1 1 a GPIO_BUTTONS_re_1 a GPIO_BUTTONS_re_1 0 jem GPIO_BUTTONS _re_1 1 Figure 16 Nets added for debug through the Synplify Pro Flow in Vivado IDE Running the Set up Debug Wizard 1 Right click the Debug tab or select the Tools menu select Set up Debug The Set up Debug wizard opens 2 Click through the wizard to create Vivado logic anal
10. T ds Lees id BEMIS gt ERAGE Mii RAROTD BATHI RADII Redd BAM BANI2 Ba i barena PTOA ae Deia si Bitetream seting Pease i Berli Checkwum ditali z apas mai fima fji elapeed Dea ey ER i pii ifii FE p gaia iii 8 Generane Mein BD oer dene Setar ba Largh MP ACT a Lh Figure 18 Window Layout for Program and Debug 2 Click on the Open New Target link in the Hardware view and select Open Hardware Target Wizard 3 Click NEXT in the wizard 4 Type the name of the server in the text field and click Next Debugging with ChipScope www xilinx com UG936 v2012 4 December 18 2012 25 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware Open New Hardware Target CSE Server Name Enter the host name and IP port of the Cse Server application Server name lt host port gt muscarial 10521 lt Back Next gt Finish Figure 19 CSE Server Name and Server Status Note Depending on your connection speed this may take about 10 15 seconds 5 If there is more than one target connected to the cse_server you will see multiple entries in the Select Hardware Target dialog box In this tutorial there is only one target as shown in Figure 20 Select the desired target and click Next Open New Hardware Target Select Hardware Target Select a hardware target from the list of available hardware targets on the Cse Server ge Name ID Code IR Length XC7K325T 33651093 6
11. com 19 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP 3 During synthesis status messages will appear in the Tcl Script tab Warning messages are expected but there should not be any Error messages To see detailed messages click the Messages tab in the bottom left hand corner of the Synplify Pro console 4 When synthesis completes the output netlist is written to the file rev_1 sinegen_demo edef 5 Optional To view the netlist select View gt View Result File The mark_debug attributes can be seen in this netlist 6 Click File gt Save All to save the project then click File gt Exit Create EDIF Netlists for the Black Box Created in Synplify Pro The black box sinegen created in the Synplify Pro project contains the Direct Digital Synthesizer IP You need to create a synthesized design for this block To do this create an RTL type project in Vivado IDE by following the steps outlined below 1 Launch Vivado IDE and select Create New RTL Project This opens up the New Project wizard Click Next 2 Under Project Name set the project name to proj_step3 Click Next 3 Under Project Type select RTL Project Click Next 4 Under Add Sources click Add Files navigate to the Vivado_Debug src folder and select the sinegen vhd file Set Target Language to VHDL Ensure that Copy sources into project box is checked Click Next 5 Under Add Existing IP click Add Files navigate to the V
12. default click the Add Files button navigate to the src directory and select sinegen_demo_kc xdc Click Next to continue Note The synplify_1 sdc file is needed for the Synopsys Synplify Pro flow 9 In the Default Part dialog box specify the xc7k325tffg900 2 part for the KC705 platform It is easiest to specify Boards for this target device and select Kintex 7 KC705 Evaluation Platform and click Next 10 Review the New Project Summary screen Verify that the data appears as expected per the steps above click Finish Debugging with ChipScope www xilinx com 9 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP Note It might take a moment for the project to initialize After you exit the New Project wizard use the Project Manager in the Vivado IDE main window to add IP and to synthesize the design Synthesizing the Design 1 In the Project Manager click Project Settings change Synthesis flatten_hierarchy option to none and click OK Note The reason for changing this setting to none is to prevent the synthesis tool from performing any boundary optimizations for this tutorial 2 In the left panel expand the Synthesis folder and click the Run Synthesis button Note When synthesis runs a progress indicator appears showing that synthesis is occurring This could take a few minutes 3 In the Synthesis Completed dialog box click Cancel You will implement the design later 4 Sele
13. event in the Waveform viewer 1 Set the trigger position of the ILA core to 512 at the midway point of the 1024 sample deep captured window shown in Figure 38 2 Source the rt tcl file in the Tcl command prompt This Tcl commands perform the following tasks o o o o o Sets the trigger position of the ILA core to 512 at the midway point of the 1024 sample deep captured window Looks for a rising edge transition on the GPIO_BUTTONS_IBUF transition Arms the trigger Waits for the trigger Uploads and displays waveforms 3 On the KC705 board press the Sine Wave Sequencer button until you see multiple transitions on the GPIO_BUTTONS_1_IBUF signal this could take 10 or more tries This is a visualization of the glitch that is occurring on the input An example of the glitch is shown in Figure 38 and Figure 39 Note You might not observe signal glitches at exactly the same location as shown in the figure below E hw ila L wefg x Arttel x A create projte P sinegen_ demo ke70S xde Og De Name Value ft oo e 7 U_SINEGEN sine 1S 32768 s MU SIN sell B GPIO BUTTONS IBU fo my GPIO_BUTTONS db T E 7 GPIO_BUTTONS a 0 Figure 38 GPIO_BUTTONS_BUF1 Signal Glitch Debugging with ChipScope www xilinx com 35 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware E hw ila lLwefg amp rttel 3 create proj tel D sinegen_demo_ke TO5 xde Ma U S
14. intellectual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips See the Integrated Logic Analyzer ILA 2 0 product page for details on the latest information on LogiCORE IP ChipScope Pro Integrated Logic Analyzer ILA v2 http www xilinx com products intellectual property ila Atm References These documents provide supplemental material useful with this guide Vivado Design Suite 2012 3 Documentation http www xilinx com cgi bin docs rdoc v 2012 3 t vivado docs ISE Design Suite 14 3 Documentation http www xilinx com cgi bin docs rdoc v 14 3 t ise docs LogiCORE IP ChipScope Pro Integrated Logic Analyzer ILA v2 Datasheet DS875 http www xilinx com cgi bin docs ndoc l en t data sheet d ds875 pdf Debugging with ChipScope www xilinx com 37 UG936 v2012 4 December 18 2012
15. list the requirements Software Vivado Design Suite 2012 3 Hardware Kintex 7 FPGA KC705 Evaluation Kit Base Board User rotary switch lt located under LED Sine Wave Figure 1 KC705 Board Showing Key Components Debugging with ChipScope www xilinx com 5 UG936 v2012 4 December 18 2012 XILINX Getting Started Tutorial Design Components The design includes e A simple control state machine e Three sine wave generators using AXI Streaming interface native DDS Compiler e Common push buttons GPIO_BUTTON e DIP switches GPIO_SWITCH e LED displays GPIO_LED Push Button Switches Serve as inputs to the debounce and control state machine circuits Pushing a button generates a high to low transition pulse Each generated output pulse is then used as an input into the state machine DIP Switch Enables or disables a debounce circuit Debounce Circuit In this example when enabled provides a clean pulse or transition from high to low Eliminates a series of spikes or glitches when a button is pressed and released Sine Wave Sequencer State Machine Captures and decodes input pulses from the two push button switches Provides sine wave selection and indicator circuits sequencing between 00 01 10 and 11 zero to three LED Displays GPIO_LED_0O and GPIO_LED_1 display selection status from the state machine outputs each of which represents a different sine wave frequency high medium and low
16. nets that are needed to be viewed in ILA comment Hark u_sinegen as black box u work sinegen syn_black_box 1 comment Set no prune on sinegen urwork sinegen syn_no_prune yp comment Mark entire bus for debug n sine mark debug 7 true conmment Mark entire bus for debug n sinegen sel mark debug true Figure 15 Synplify Pro Constraints in CDC Files In the above constraints sinegen has been defined as a black box by using the syn_black_box attribute Second the syn_no_prune attribute has been used so that the I Os of this block are not optimized away Finally two nets sine 20 0 and sel 1 0 have been assigned the mark_debug attribute such that these two nets should show up in the synthesized design in Vivado IDE for further debugging For further information on these attributes please refer to the Synplify Pro User Manual and Synplify Pro Reference Manual Synthesize the Synplify Project 1 Before implementing the project you need to set the name for the output netlist file By default the name of the output netlist file is synplify_1 ed To change the name of the output file type the following command at the Tcl command prompt Sproject result_file rev_1 sinegen_demo edf You will use this file in Vivado IDE 2 With all the project settings in place click the Run Button in the left panel of the Synplify Pro window to start synthesizing the design Debugging with ChipScope www xilinx
17. wave generators is selected The input signal button connects to the top level signal GPIO_BUTTONS re 1 which is a low to high transition indicator on the Sine Wave Sequencer button shown in Figure 1 page 5 The output signal Y connects to the top level signal sineSel which selects the sine wave GPIO_BUTTON _ 1 GPIO_BUTTONS ret FSM GPIO_BUTTON_IBUF_1 Figure 37 Sine Wave Sequencer Button Schematic Viewing the State Machine Glitch Viewing the Button Input to the Design You cannot troubleshoot the issue you identified above by connecting a debug probe to the GPIO_BUTTON 1 input signal itself The GPIO_BUTTON 1 input signal is a PAD signal that is not directly accessible from the FPGA fabric Instead you must trigger on Debugging with ChipScope www xilinx com 34 UG936 v2012 4 December 18 2012 amp XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware low to high transitions rising edges on the GPIO_BUTTON_IBUF signal shown in Figure 37 which is connected to the output of the input buffer of the GPIO_BUTTON 1 input signal As described earlier the glitch reveals itself as multiple low to high transitions on the GPIO_BUTTONS_1_IBUF signal but it occurs intermittently Because it could take several button presses to detect it you will now set up the Vivado logic analyzer tool to Repetitive Trigger Run Mode This setting makes it easier to repeat the button presses and look for the
18. INEGEN sel 1 08 0 1 0 GPIO BUTTONS diy MA GPIO BUTTONS dbg O T GPIO BUTTONS relf 0 Figure 39 GPIO Buttons_1_re Signal Glitch Fixing the Signal Glitch and Verifying the Correct State Machine Behavior The multiple transition glitch or bounce occurs because the mechanical button is making and breaking electrical contact just as you press it To eliminate this signal bounce a debouncer circuit is required 1 Enable the debouncer circuit by setting DIP switch position on the KC705 board labeled Debounce Enable in Figure 1 page 5 to the ON or UP position 2 Repeat step 2 page 35 and step 3 page 35 to Ensure that you no longer see multiple transitions on the GPIO_BUTTON_re 1 signal on a single press of the Sine Wave Sequencer button o o Verify that the state machine is working correctly by ensuring that the sineSel signal transitions from 00 to 01 to 10 to 11 and back to 00 with each successive button press Debugging with ChipScope www xilinx com UG936 v2012 4 December 18 2012 36 XILINX Appendix A Additional Resources Xilinx Resources For support resources such as Answers Documentation Downloads and Forums see the Xilinx Support website at www xilinx com support For a glossary of technical terms used in Xilinx documentation see www xilinx com company terms htm Solution Centers See the Xilinx Solution Centers for support on devices software tools and
19. Li B Open Project Project Files Design Hierarchy Open Proj Bi Close Projet synplify_1 rev_1 Xilinx Kintex XC7K70T FBC ST synplify_1 C Designs Vivado_Debt EJ i in P src By Change File VHDL Add Implementation H debounce vhd work gt NOTE ee fsm vhd work gt NOTES 3 H sinegen_demo vhd work gt W GR Add P amp R Implementation 53 Logic Constraints SDC View Log E synplify_lsde gt WARNINGS 9 ag revi Frequency MHz 1 0000 Auto Const Auto Compile Point Continue On Error FSM Compiler bal FSM Explorer Resource Sharing tal Pipelining inl Retiming Figure 12 4 This brings up the Implementation Opening Implementation Options in Synplify Pro Options dialog box as shown in Figure 13 In the Device tab set Technology to Xilinx Kintex7 Part to XC7K325T Package to FFG900 and Speed to 2 Leave all the other Part MC7K325T Device Mapping Options Option Fancut Guide Disable 0 Insertion Disable Sequential Optimizations Update Compile Point Timing Data Click on an option for description System Designer Board File Figure 13 Specifying Implemen Mark Nets for Debug in VHDL options at their default values Click OK E Implementation Options synplify_1 rev_1 F z Device Options Constraints Implementation Results Timing Report Hi
20. and Implementing an RTL Project in the Vivado Integrated Design Environment 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard 3 Select Next to continue to the next screen 4 In the Project Name screen name the new project proj_stepl and provide the project location C Vivado_Debug Ensure that Create Project Subdirectory is checked and click Next 5 In the Project Type screen specify the Type of Project to create as RTL Project and click Next 6 In the Add Sources screen a Set Target Language to VHDL b Click the Add Files button c In the Add Source Files dialog box navigate to the src directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is checked Click Next 7 In the Add Existing IP optional dialog box a Click the Add Files button b In the Add Configurable IP dialog box navigate to the src directory c Select all XCI source files and click OK d Verify that the files are added and Copy Sources into Project is checked Click Next 8 In the Add Constraints optional dialog box the provided XDC file should automatically appear in the main window Another file called synplify_1 sdc should also appear as a part of the included files Select and remove the synplify_l sdc file by clicking the Remove Selected File button If none of the files appear in the dialog box by
21. ct File gt Save Project As and save the project as proj_step2 Saving the project to a new file allows you to more easily resume the tutorial if you do not wish to complete all the steps in one sitting Step 2 Probing and Adding Debug IP Using the Netlist Insertion Method To add a Vivado ILA 2 0 core to the design take advantage of the integrated flows between the Vivado IDE and Vivado logic analyzer Ar IMPORTANT f you are already familiar with adding Debug Nets and adding Debug IP using the Core Insertion method use the provided step_2 tc1 to perform the same tasks as described below Make sure you cd into the same level of the sre folder before sourcing the step_2 tc1 Le cd c Vivado_Debug src You will accomplish the following tasks e Add debug nets to the project e Run the Set Up Debug Wizard e Implement and open the design e Generate the Bitstream Debugging with ChipScope www xilinx com 10 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP Adding Debug Nets to the Project Working in the project_step2 project Following are some examples of how to add debug nets using the Vivado IDE e Add mark_debug attribute to the target XDC file set_property mark_debug true get_nets sine Note Use these attributes in synthesized designs only Do not use then with pre synthesis or elaborated design netlists e Add mark_debug attribute to HDL files VHDL attribute mark_debug string
22. ge of Xilinx ISE Design Suite and Vivado Design Suite tool flows Prerequisites A basic knowledge of Xilinx ISE Design Suite and Vivado Design Suite tool flows Objectives This tutorial e Shows you how to take advantage of integrated Vivado logic analyzer features in the Vivado design environment that make the debug process faster and simpler e Provides specifics on how to use the Vivado Integrated Design Environment IDE and the Vivado logic analyzer to debug some common problems in FPGA logic designs After completing this tutorial you will be able to e Validate and debug your design using the Vivado Integrated Design Environment and the Integrated Logic Analyzer ILA core Debugging with ChipScope www xilinx com 4 UG936 v2012 4 December 18 2012 XILINX Getting Started e Understand how to create an RTL project probe your design insert an ILA 2 0 core and implement the design in the Vivado Integrated Design Environment e Generate and customize an IP core netlist in the Vivado Integrated Design Environment e Debug the design using Vivado logic analyzer in real time and iterate the design using the Vivado Integrated Design Environment and a KC705 Evaluation Kit Base Board that incorporates a Kintex 7 device Getting Started Setup Requirements Before you start this tutorial make sure you have and understand the hardware and software components needed to perform the steps The following subsections
23. gh Reliability VHO gt Implementations f Technology Package Speed rev Value 10000 tation Options in Synplify Pro Use the mark_debug attribute in the VHDL source files as described in Adding Debug Nets to the Project page 11 These attributes are already placed in the sinegen_demo vhd VHDL source files of this tutorial Open the sinegen_demo vhd file Uncomment lines Debugging with ChipScope UG936 v2012 4 December 18 2012 www xilinx com 18 amp XILINX Step 2 Probing and Adding Debug IP 69 72 that specify the attributes for marking debug nets in Synplify Pro as shown in Figure 14 68 Attributes for Synplify Pro 6 attribute syn keep boolean T0 attribute syn_keep of GPIO BUTTONS db z Signal is true 71 attribute syn_keep of GPIO_BUTTONS_dly signal is true i n attribute syn keep of GPIO BUTTONS re Signal is true ia Figure 14 Specifying Implementation Options in Synplify Pro Mark Nets for Debug in CDC The synplify_1 sdc file contains various kinds of constraints such as pin location I O standard and clock definition The synplify_1 cdc file contains directives for the compiler Here is where the nets of interest to us that are marked for debug are located The attribute and the nets selected for debug are shown in Figure 15 H H Attributes that H define_attribute define_attribute define attribute fefine attribute are needed to mark_debug the
24. ing with ChipScope www xilinx com UG936 v2012 4 December 18 2012 33 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware Debugging the Sine Wave Sequencer State Machine Optional As you were correcting the sine wave display the LEDs might not have lit up in sequence as you pressed the Sine Wave Sequencer button With each push of the button there should be a single cycle wide pulse on the GPIO_BUTTONS_re 1 signal If there is more than one the behavior of the LEDs becomes irregular In this section of the tutorial you will use Vivado logic analyzer to probe the sine wave sequencer state machine and to view and repair the root cause of the problem Before starting the actual debug process it is important to understand more about the sine wave sequencer state machine Sine Wave Sequencer State Machine Overview The sine wave sequencer state machine selects one of the four sine waves to be driven onto the sine signal at the top level of the design The state machine has one input and one output Figure 37 shows the schematic elements of the state machine Refer to this diagram as you read the following description and as you perform the steps to view and repair the state machine glitch e The input is a scalar signal called button When the button input equals 1 the state machine advances from one state to the next e The output is a 2 bit signal vector called Y and it indicates which of the four sine
25. ivado_Debug src folder and select the sine high xci sine _low xci and sine _mid xci files Click Next 6 Under Add Constraints two sdc files are automatically added to the project These files are not needed for this step Remove them from this project by clicking the Remove Selected File button on the right of the dialog box Click Next 7 Under Default Part select Boards and then select the Kintex 7 KC705 Evaluation Platform Click Next 8 Under New Project Summary ensure that all the settings are correct and click Finish 9 Once the project has been created in Vivado Flow Navigator under the Project Manager folder click Project Settings In the pop up dialog box in the left panel click Synthesis From the pull down menu on the right panel set flatten_hierarchy to none and check the no _iobuf box 10 In Vivado IDE Project Manager under Synthesis Folder click on Run Synthesis When synthesis completes the Synthesis Completed dialog box appears Select Open Synthesized Design and click OK 11 Now you need to write the netlist file for all the components used in the singen block The four netlist files used in this tutorial are already provided as a part of the source Debugging with ChipScope www xilinx com 20 UG936 v2012 4 December 18 2012 amp XILINX Step 2 Probing and Adding Debug IP files However you can overwrite them by using your own netlist files To do this use the following Tcl command in the Tc
26. l console of Vivado IDE write_edif force Vivado_Debug src sinegen edn Ensure that the path specified to the src folder is correct At this point you should see four edn files in the Vivado_Debug src folder as shown below o dAds_compiler_v5_0_xst edn o dds_compiler_v5_0_xst__parameterized0 edn o dds_compiler_v5_0_xst__parameterizedl edn o Sinegen edn These files are provided in the Vivado_Debug src folder You may choose to overwrite these files using the write edif force command option as shown above 12 Click File gt Exit in Vivado IDE Create a Post Synthesis Project in Vivado IDE 1 Launch Vivado IDE and select Create New Project This opens up the New Project wizard Click Next 2 Set the Project Name to proj_step4 Click Next 3 Under Project Type select Post synthesis Project Click Next 4 Under Add Netlist Sources click Add Files navigate to the Vivado_Debug synplify_pro rev_1 folder and select sinegen_demo edf 5 Add the four netlist files created in the previous section Click on Add Files again navigate to the Vivado_Debug srce folder and select the following files o Sinegen edn dds_compiler_v5_0_xst edn o dds_compiler_v5_0_xst_parameterized0 edn o dds_compiler_v5_0_xst_parameterizedl edn Enure that Copy Sources into Project is checked Click Next 6 Under Add Constraints some xdc files should be automatically populated Remove these files by selecting them and clicking the Remove Selected
27. linx com 14 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP i Verilog File d VHDL File J Text File d Tcl Script Xilinx Options File E FPGA Design Constraints D Add To Project New File Name synplify_1 File Location C Designs Vivado_Debug synplify_pro Full Path C Designs Vivado_Debug synplify_pro synplify_1 prj Figure 7 Synplify Pro New Project Dialog Box 2 In the left panel of the Synplify Pro window click Add File as shown in Figure 8 pro synplify_L pr Synplify Pro G 2012 09 C Designs Vivado_Debug synp D S file Edit View Project Import Run Analysis HDL Analyst Options Window Tech Support Web Help BFtf oea Bees Hath DVvRBUtOErVrBaeaa wn a GSHm PEAR A Acn VihbBo Em E Run Pro B Open Project Project Files Design Hierarchy gt s j syn pify_1 rev_1 Xilinx Kintex XC7K70T FBG676 1 3 synplify 1 C Designs Vivado_Debug synplify_pro synplify_1 prj rev_l Frequency MHz fi f Auto Const Auto Compile Point Continue On Error FSM Compiler Ed FSM Explorer am Resource Sharing ll Pipelining nal aa Retiming Figure 8 Adding Files to a Synplify Pro Project Debugging with ChipScope www xilinx com UG936 v2012 4 December 18 2012 15 XILINX Step 2 Probing and Adding Debug IP This will bring up the Add Files to Project dialog box as shown in Figure 9 a First change the File
28. lity_1 sac Files of type Constraint Files ode z VHOL Verilog lib x Files to add to project 4 file s selected Use relative paths Add files to Folders Folder Options Jjerc debounce vhd src fsm vhd ste sinegen_demo vhd JASrc synplify Lede Figure 10 Adding SDC Constraints File to the Synplify Pro Project c Inthe same dialog box set Files of type to Compiler Directives File This shows the synplify_1 cdc file Select the file and click Add as shown in Figure 11 Click OK SS Add Files to Project lookin l Designs vivado_Debug sre jeooo 8 W My Computer Ae ndutta File nane npl _l cde Files of type Compiler Directives ede N VHDL Verilog lib z Files to add to project 1 file s selected Y Use relative paths Y Add files to Folders Folder Options Figure 11 Adding CDC Constraints File to the Synplify Pro Project Debugging with ChipScope www xilinx com 17 UG936 v2012 4 December 18 2012 amp XILINX Step 2 Probing and Adding Debug IP 3 Now you need to set the implementation options Click Implementation Options in the Synplify Pro window as shown in Figure 12 lt gt Synplify Pro G 2012 09 C Designs Viva synplify_pro synplify_1 B File Edit View Project Import Run Analysis HDL Analyst Optic CE AEE MME T IE O EE A Er By D Eme AAA 2 49 Ble Bw Synplify Pro Run Done O errors 12 warni i F
29. oducts are subject to the terms and conditions of the Limited Warranties which can be viewed at http www xilinx com warranty htm IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Copyright 2012 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zyng and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 07 25 12 2012 2 Initial Xilinx release 10 16 12 2012 3 e Added section for Synplify EDIF flow e Various editorial fixes and updated screen shots to track changes to dialog boxes 12 18 2012 2012 4 Revalidated for the 14 3 release Editorial updates only no technical content updates Debugging with ChipScope www xilinx com 2 UG936 v2012 4 December 18 2012 amp XILINX Table of Contents REVISION HISLONV 2 4 coe etic eteees ees e sath Geese sees eeeesaueeee Debugging with Vivado ILA 2 0 and Integrated Logic Analyzer INC OGUCTION 26 ee
30. ore you do so you need to make sure you have KC705 hardware plugged into a machine and are running a cse_server application on that machine In this step you learn e How to debug the design using the Vivado logic analyzer e How to use the current supported Tcl commands to communicate with your target board KC705 e How to discover and correct a circuit problem by identifying unintended behaviors of the push button switch e Some useful techniques for triggering and capturing design data Debugging with ChipScope www xilinx com 23 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware Verifying Operation of the Sine Wave Generator After doing some setup work you will use Vivado logic analyzer to verify that the sine wave generator is working correctly The two primary objectives are to verify that e All sine wave selections are correct e The selection logic works correctly Setting Up If you plan to connect remotely you will need to make sure you have KC705 hardware plugged into a machine and are running a cse_server application on that machine If you plan to connect locally skip step 1 4 below 1 Connect the Digilent USB JTAG cable of your KC705 board to a Windows machine s USB port 2 Ensure that the board is plugged in and powered on 3 Assuming you are connecting your KC705 board to a 64 bit Windows machine and you will be running the cse_server from
31. pears Note The Hardware tab in the Debug view shows the hardware target and XC7K325T device that was detected in the JTAG chain Hardware Session muscarial 10521 digilent_plugin 5N 210203338750 a oi i E Pi b gt Hame State Trigger Cond Trigger Pos H muscarial2 10521 1 Ehia digilent_plugin 5N 210203338750 1 XC7K325T 0 active Figure 24 Active Target Hardware 10 Next program the XC7K325T device using the BIT bitstream file that was created previously by right clicking on the XC7K325T device and selecting Program Device as shown in Figure 25 Hardware Session muscarial2 10521 digilent_plugin SN 210203338750 A Pl gt Name State Trigger Cond Trigger Pos E i muscarial 10571 1 Be digilent_plugin SN 210203338750 1 XC7K3251 0 active amp Hardware Device Properties Ctrl E Set as Current Device Assign Programming File Program Device Refresh Device Export to Spreadsheet Hardware Device Properties i gt Blk i Figure 25 Program Active Target Hardware Debugging with ChipScope www xilinx com 28 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 11 Verify that the BIT file is correct and click the Program button to program the device as shown in Figure 26 Program Device Parameters Bitstream file 2 Figure 26 Select Bitstream file to Download Note Wait for
32. s of Type to HDL File This shows all the VHDL source files in the Vivado_Debug src folder Select the following three files by pressing the Ctrl key and clicking on them o debounce vhd o tsm vnd o Sinegen_demo vhd Do not add the fourth file sinegen vhd this Synplify Pro project That block is treated as a black box Later in Vivado IDE you will bring in the synthesized design for this black box gt Add Files to Project Look In JoG Designs vivade_Debug src 7 990 Be sl My Computer E debounce vhd B ndutta fsm vhd File pame debounce vid Tsmevhd sinegen_demeo vwhd Files of type HDL Files vhd vindl Sw lay mal VHDL Verilog lib 7 Files to add to project 3 file s selected Use relative paths Add files to Folders Folder Options Jjsrc debounce vhd lt Add All wsrc tsmvid m sre sinegen_demo vhd Remove All gt Ramove gt Figure 9 Adding VHDL Source Files to the Synplify Pro Project Debugging with ChipScope www xilinx com 16 UG936 v2012 4 December 18 2012 XILINX Step 2 Probing and Adding Debug IP b In the same dialog box set Files of type to Constraints File This shows the synplify_1 sdc file Select the file and click Add as shown in Figure 10 Click OK gt Add Files to Project hrn Look in _ C Designs Vivade_Debug sre 1000 El id My Computer BR ndutta File pame synp
33. the network instead of your local drive open a cmd prompt and type the following lt Xilinx Install gt ISE_DS ISE bin nt64 cse_server 4 Leave this cmd prompt open while the cse_server is running Note the machine name that you are using this will be used later when opening a connection to this instance of the cse_server application If you plan to connect locally ensure that you have your KC705 hardware plugged into a Windows machine and then perform the following steps 1 Connect the Digilent USB JTAG cable of your KC705 board to a Windows machine s USB port 2 Ensure that the board is plugged in and powered on 3 Turn DIP switch positions on SW8 Debounce Enable to the OFF position You are now ready to use the Vivado logic analyzer 1 In the Vivado IDE from the Program and Debug drop down list select Open Hardware Session Note Note that the window layout changed to look like the Figure 18 Debugging with ChipScope www xilinx com 24 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware File Edit How Tools Window Layout View Help f2 o BB HUGA LG Soetet eu ke iH E Project smga Mo harhan Eat hi opaa Te api a bargi aar aad ah Add Sources table chch ona of the follower baka Ovs Report pac TR FORE jii cern Foe gt FORE I biwteccen TD Report Pikmin CEDPEESS EEJ l imetences Popp A BSHLOEELS p MAINID Ree ei MA SE ee
34. the program device operation to complete This may take few minutes 12 Ensure that an ILA core was detected in the Hardware panel of the Debug view Hardware Session muscarial12 10521 digilent_plugin SN 210203338750 State Trigger Cond Trigger Pos Data Depth muscariai2 105 Be digilent_pludgi lt _XCTKGIST GF wila i IDL AND 0 Hardware Device Properties Ov e Poli Figure 27 ILA Core Detection Debugging with ChipScope www xilinx com 29 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 13 Next select the ILA Probes tab as shown in Figure 28 and ensure that all of the debug nets added from previous steps are accounted for a Name Compare Value twv_ila_1 ie GPIO_BUTTONS_IBUF B ie GPIO_BUTTONS_db i 0 i GPIO_BUTTONS_dty 1 0 GPIO_BUTTONS_re 1 0 i U_SINEGEN sel 1 0 iw U_SINEGEN sine 19 0 Figure 28 List of Debug Nets under EDA_PROBES Verifying Sine Wave Activity 1 Click the Run Trigger Immediate button to trigger and capture data immediately as shown in Figure 29 Hardware Session muscarial2 10521 digilent_plugin SN 210203338750 Hardware 0 vw x Trigger Pos Data Depth i muscarial 105 Be digilent_pludi Ce rey ee a a GP hw ilai IDLE AND 1074 Figure 29 Run Trigger Immediate Button Debugging with ChipScope www xilinx com 30 UG936 v2012 4 December 18
35. ve sequential circuit by pressing the GPIO_SW_E push button as shown In Figure 33 Figure 33 Sine Wave Sequencer Push Button Debugging with ChipScope www xilinx com 32 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware 2 Click Run Trigger Immediately again to see the new sine selected sine wave You should see the mid frequency as shown in Figure 34 Notice that the sel signal also changed from 0 to 1 as expected B hw ila l wefg gt aU SINEGEN sine 1 131031 MA U_SINEGEN sel 1 0 F H GPIO BUTTONS dbf 2 GPIO BUTTONS rej c A GPIO BUTTONS diy 0 Figure 34 Output Sine Wave Displayed in Analog Format Mid Frequency 3 Repeat step 1 and 2 from above to view other sine wave outputs Bhw ila 1L wdg F Hane Pe ERieer FAP Ale Figure 35 Bhw ila wig i of Name Ww ahue a a a Las ji bl oy a GPiO_BUTTONS_dbe o Mi GPIO BUTTONS roig O a E GIO a a E Figure 36 Output Sine Wave Displayed in Analog Format Mixed Frequency Note As you sequence through the sine wave selections you may notice that the LEDs do not light up in the expected order You will debug this in the next section of this tutorial For now you will verity for each LED selection that the correct sine wave is displayed Also note that the signals in the waveform window have been re arranged in Figure 34 Figure 35 and Figure 36 Debugg
36. wee oe bee oe eee ee eee Oe eee eS Tee eee an PrOreCquUisiles lt a 44 3540 nes Hee oe eee ODICCUVGS lt 4 6c oe cs obese be ee tees ene ee Getting StalleG e224 ota6 ene bes ee hos Boe se tees eee Step 1 Creating and Implementing an RTL Project in the Vivado Integrated Design ENVITONMOCNGs 645006 SOAR SW Ae Cee wee ees Step 2 Probing and Adding Debug IP 1 1 cc ccc cc ce cee cette eee e eee eee enees Step 3 Using the Vivado Logic Analyzer to Debug the Hardware Appendix A Additional Resources POE RESOUT CES lt lt coe gs gee gS 26S we oe aoe ese Se See Ss ee eee ee ore Solution CONTOIS 6k 6 526 606 bir se ow are RETCONCeS acc dee wee eee Ee a eC he Debugging with ChipScope www xilinx com UG936 v2012 4 December 18 2012 amp XILINX Debugging with Vivado ILA 2 0 and Integrated Logic Analyzer Introduction In this tutorial exercise you will quickly learn how to debug your FPGA designs by inserting an Integrated Logic Analyzer ILA core using the Vivado Integrated Design Environment IDE You will take advantage of integrated Vivado logic analyzer functions to debug and discover some potential root causes of your design thereby allowing you to quickly address issues Example RTL designs will be used to illustrate overall integration flows between Vivado logic analyzer ILA 2 0 and Vivado IDE In order to be successful using this tutorial you should have some basic knowled
37. yzer debug cores keeping the default settings Implementing the Design and Generating the Bitstream 1 In the left panel main window of the Vivado IDE click the Run Implementation button 2 In the Save Project pop up menu click Save 3 When the implementation process ends an Implementation Completed dialog box opens Note Implementation could take about 10 minutes 4 In the Implementation Completed dialog box click Cancel 5 Inthe upper right hand corner click on more info and then Force up to date as shown in Figure 17 This step will prevent the tools from re synthesizing and re implementing the design Debugging with ChipScope www xilinx com 22 UG936 v2012 4 December 18 2012 XILINX Step 3 Using the Vivado Logic Analyzer to Debug the Hardware mthesis and Implementation Out of Date More info Synthesis Out of Date Due to Force up to da O Files Modified sinegen demo ke705 xde Figure 17 Synthesis Out of Date 6 Expand the Program and Debug folder and click Generate Bitstream Click OK when the Bitstream Generation Completed pop up appears to let you know the process is finished Step 3 Using the Vivado Logic Analyzer to Debug the Hardware Now that you have added an ILA 2 0 to your design and connected it to your debug nets implemented your design and created a bitstream file you are almost ready to use the integrated Vivado logic analyzer feature to interact with the ILA core However bef
38. zip the tutorial source file to the Vivado_Debug folder 4 When unzipped look in Vivado_Debug src for the files and folder shown in Figure 2 Debugging with ChipScope www xilinx com 7 UG936 v2012 4 December 18 2012 A XILINX Step 1 Creating and Implementing an RTL Project in the Vivado Integrated Design Environment eynplify_ Lede dds compiler va 0 xstedn dds compiler y3 0 xst_parametenzedd dds compiler w5 0 xst_parametenzed inegen edn dds compilerv5_0 xstednsayv dds compiler w5 0 xst_parameterzed dds_compilerv5_0_xst_parameternzed sinegenednsav synplify_lsde init tel rttcl step_L tecl step_2 tel d ebounte vwhd fomivnd snegenvwhd fh sf 8 8 8 amp amp amp sinegen_demo vwnd sine _ high sine_low xci sine midaci sinegen_demo_ke 05xdc sine_highsom ne_lowxml 2 sine_mid som Figure 2 Tutorial Design File Set Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device A IMPORTANT f you are already familiar with creating a new project in Vivado use the script provided in step_1 tcl to perform the tasks described in Step 1 Make sure you cd to the same level of the src folder before sourcing the step_i tcl Le cd c Vivado_Debug srec Debugging with ChipScope www xilinx com 8 UG936 v2012 4 December 18 2012 gt XILINX Step 1 Creating
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