ART2768 User`s Manual
Contents
1. 0 0016 Read DAO data from the RAMI Write the data will be converted by the DAI to the Beijing ART Technology Development Co Ltd 051 Read back Read back Read back Read back Read back Read back Read back 0x0017 0x0018 0x0019 001 0x001b 0x001c 0x001d Read back Read back 0x0020 Read back 0x0021 Read back 0x0022 Read back 0x001e 0x001f Reserved Read back Read back 0x0023 0x0024 0x0025 0x0026 Read DAO data from the RAM2 Read back Read back Read back Read back Read back Read back Read back 0x0027 0x0028 0x0029 0x002a 0x002b 0x002c 0x002d Read back Read back 0x0030 Read back 0x0031 Read back 0x0032 Read back 0x002e 0x001f Reserved Read back Read back 0x0033 0x0034 0x0035 Low 16 bit of the loop start address Reset RAMO output location to the cycle starting location DAI polarity setting 0 unipolar 1 bipolar DAI gain setting 0 single gain 1 double gain DA2 MODE control word the low 6 bit effective DA2 frequency control word 16 bit DA2 enable signal D15 0 disable DA2 conversion D15 1 start DA2 conversion if use the external trigger need to wait for the trigger signal to start DA O allow users access to RAM2 1 disable users do any operation of the RAM2 The current low 16 bit offset address of the RAM2 The current high 2 bit offset address of the RAM2 data low 2 b2. MO nO RR NN RH RF 16 SADAF oral Mod Cc er R UM 16 16 BUTS Ie e NF 17 Chapter 6 Methods of using Internal and External Clock 2 22 06050000000000552 2 8 8 0 0 00000000000000000 19 4 a OU oc ecg ee M PER MD IS 19 6 2 Pera Clock BUCO 19 Chaplet 7 Address FOCAL on Ole YN anrea A al An et na Se Se nas TEE E aan 20 Nomina amp Noles and Warrann Pole 23 BV RI YN 23 8 2 Analog Signal Output Calibration nan 23 ae M s ae 23 Products Rapid Installation Self check toe ce bee brane cue ben t neu ture verbes uero 25 TR AO LI RE bd 25 SY 25 Delete Aron Insta On bni 25 Beijing ART Technology Development Co Ltd V6 051 Chapter I Overview ART2768 15 an arbitrary waveform generator card based on PC104 bus can be connected to the computer s PC104 interface to constitute the laboratory product quality inspection center and other a
3. 5 4 2 8 7 6 2 4 3 2 1 A9 A8 A7 A6 AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 A8 A7 5 A4 A2 8 7 6 5 4 3 2 1 A9 7 A6 AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 A8 A7 5 A4 A2 8 7 6 2 4 3 2 1 A9 A8 A7 5 A4 A2 8 6 2 4 3 2 1 A9 A8 A7 5 A4 A2 8 7 6 2 4 3 2 1 Beijing ART Technology Development Co Ltd V6 051 2 2 5 Indicator 5 VA 5 analog power indicator 5 VD 5 digital power indicator 43 3 VD 3 3V digital power indicator RAM3 AO3 analog output channel RAM status indicator RAM2 AO2 analog output channel RAM status indicator RAMI AOI analog output channel RAM status indicator RAMO AOO analog output channel RAM status indicator Beijing ART Technology Development Co Ltd V6 051 Chapter 3 Signal Connectors 3 1 Analog Input Output Interface ART2768 has five signal interface 0 AOI AO2 AO3 and ATR signal port AOO AOI AO2 AO3 are analog output ports of the 4 channels DA corresponding to AOO AO3 pins of the Pl is analog trigger signal input port corresponding to the ATR pin of the P1 3 2 Analog Signal Connector P1 10 pin definition AGND
4. Beijing ART Technology Development Co Ltd V6 051 Chapter 6 Methods of using Internal and External Clock Function 6 1 Internal Clock Function Internal clock function use the clock signal that generated by the on board clock oscillator to trigger DA conversion ie DA refresh clock The clock of the waveform data that stored in the 15 generated on board logic control circuit and according to the user specified freguency divided by the number the max clock is the same as the trigger DA frequency the min clock is the 65535 times of the DA trigger frequency in this case we can achieve slow playback the waveform in the use the internal clock function the hardware parameters DAPara ClockSouce ART2768 CLOCKSRC IN should be installed in the software The frequency of the clock in the software depends on the hardware parameters DAPara Freguency For example if Freguency 100000 that means the speed of read waveform is 100K Hz but the DA s refresh clock unchanged it is still 40MHz 6 2 External Clock Function External clock function uses the external clock signal to trigger the DA The clock signal is provided by the CLKIN pin To use the external clock function the hardware parameters DAPara ClockSouce ART2768 CLOCKSRC OUT should be installed in the software The clock frequency depends on the external clock frequency In external clock mode both the read waveform data clock and DA refresh frequency are the s
5. 7 6 5 4 3 2 1 9 8 A7 6 5 4 2 8 7 6 5 4 3 2 1 9 8 A7 6 5 4 2 8 1 6 2 4 3 2 1 A9 A8 A7 A6 A5 A4 A3 A2 8 7 6 4 3 2 1 A9 A7 A6 A5 A4 A3 A2 8 2 6 2 4 3 2 1 Beijing ART Technology Development Co Ltd 9 8 A7 A6 5 4 A2 8 7 6 5 4 3 2 1 A9 AS AT AS A4 A3 A2 8 7 6 5 4 3 2 1 9 AS AT AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 AS AT AS A4 A3 A2 8 7 6 3 4 3 2 1 A9 AS A7 A5 A4 A2 8 7 6 gt 4 3 2 1 A9 AS A7 A6 AS A4 A3 A2 8 6 2 4 3 2 1 A9 AS AT AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 8 AT AS A4 A3 A2 8 7 6 2 4 3 2 1 A9 8 A7 A5 A4 A3 A2 8 7 6 5 4 3 2 1 A9 A8 A7 5 V6 051 4 A2 8 7 6 5 4 3 2 1 A9 8 A7 A6 AS 4 A2 8 7 6 2 4 3 2 1 A9 A8 A7
6. 3LSB maximum Output error full scale 2LSB Operating Temperature Range 0 C 50 C VV V Storage Temperature Range 20 70 C BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 3 Beijing ART Technology Development Co Ltd Digital Input Channel No 4 channel Electric Standard TTL compatible High Voltage 2V Low Voltage 0 8V Digital Output gt V Y V Channel No 4 channel Electrical Standard TTL compatible High Voltage 3 8V Low Voltage 0 44V Power on Reset Other Features gt gt On board Clock Oscillator 40MHz Dimension 102mm L 127mm W 16mm 4 Beijing ART Technology Development Co Ltd V6 051 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Component Layout Diagram DODPC POWER a ma 4 ADT AU 4 A03 ATR HT 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors P1 Analog signal output connector P2 Digital signal input output connector AO0 Analog output interface AOI Analog output interface AO2 Analog output interface AO3 Analog output interface ATR Analog trigger signal input interface BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 5 Beijing ART Technology Developm
7. data acquisition in this way See the following figure External Trigger Signal ATR DTR 2768 ATR DTR ART2768 ATR DTR ART2768 When using the common external clock trigger please make sure all parameters of different ART2768 are the same At first configure hardware parameters and use external clock then connect the signal that will be sampled by ART2768 input trigger signal from ART pin or DTR pin then click Start Sampling button at this time ART2768 does not sample any signal but wait for external clock signal When each module is waiting for external clock signal use the 14 Beijing ART Technology Development Co Ltd V6 05 1 common external clock signal to startup modules at last we realize synchronization data acquisition in this way See the following figure External clock signal CLK_IN ART2768 ART2768 an ART2768 Beijing ART Technology Development Co Ltd V6 051 Chapter 5 The Instruction of the DA Trigger Function 5 1 DA Internal Trigger Mode When DA is in the initialization if the DA hardware parameter DAPara TriggerSource ART2768 TRIGMODE SOFT we can achieve the internal trigger acguisition In this function calling the InitDeviceDA function to initial the device then wait EnableDeviceDA function to start DA DA immediately access to the conversion process and not wait for the conditions of any other external hardware It also can be interp
8. 9 ATR AGND 7 AO3 AGND 5 AO2 AGND 3 AOI AGND 1 Pin definition A00 AO3 Analog output pins Analog trigger signal input port AGND Analog ground 3 3 Digital Input Output Connector P2 20 pin definition 5V 1 5V DIO 3 DII DID 5 DI3 DOO 7 DOI DO2 9 DO3 DGND 11 DGND CLKOUT 13 DGND CLKIN 15 DGND DIR 17 DGND DGND 19 DGND Beijing ART Technology Development Co Ltd V6 051 Pin definition External digital trigger signal input pin 5V PWR 5V power output pin Digital ground NC gt we Beijing ART Technology Development Co Ltd V6 051 Chapter 4 Connection Ways for Input and Output 4 1 Analog Output Connection AO0 AUS Device AGND 4 2 External Trigger Signal ART Connection ATR Analog Trigger Signal AGHD 4 3 Clock input Output and Digital Trigger Signal Connection Ag DIR CLKIN CLKOUT DGND 12 Beijing ART Technology Development Co Ltd V6 051 4 4 Digital Signal Input Connection Switch signal 1 switch device switch device DGND 4 5 Digital Signal Output Connection poo Switch signal le switch device switch device DGND Beijing ART Technology Development Co Ltd V6 051 4 6 Methods of Realizing the Multi card Synchronization Three methods can realize the synchronization for the ART2768 the first
9. LVTTL it can be achieved through the computer writes the serial number to the D A the software function 15 SetDevTrigLevelDA Beijing ART Technology Development Co Ltd V6 051 ATR Serial Result Number DAOUT Comparator Figure 5 2 Analog Comparator When DAPara TriggerDir ART2768 TRIGDIR POSITIVE it is positive trigger that is when ATR trigger source signal changes from smaller than trigger level to higher than trigger level DA immediately into the conversion process in this case its follow up changes have no effect on DA acquisition unless the user re initialize the AD When DAPara TriggerDir ART2768 TRIGDIR NEGATIVE it is negative trigger it 1s triggered in the opposite direction with the positive but the others are the same as the positive trigger See the Figure 5 3 DA Start Pulse The first pulse after DA Working Pulse i the DA triggered no 222222 Trigger Signal Trigger Level The falling edge before The first falling edge after the the DA started is invalid AD started is valid fososocscsesecccesesecceecceeceeceececeeeseeoceoeceoesecs tt 0 0 0 0 0 0 0 0 000 00 0 OI RR Figure5 3 Falling Edge Trigger When DAPara TriggerDir ART2768 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger As long as the trigger sources signal across the trigger level it will trigger DA immediately The follow
10. back Single point immediate output DA3 data 16 bit 0x003d Read back Reset RAM3 output location to the cycle starting location Read back polarity setting 0 unipolar 1 bipolar Read back gain setting 0 single gain 1 double gain 0x0042 Version D15 DO firmware Invalid version 0x0043 Version D7 DO hardware version Invalid D15 D8 Reserved Beijing ART Technology Development Co Ltd V6 051 Chapter 8 Notes and Warranty Policy 8 1 Notes In our products packing user can find a user manual a Art2768 module and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using Art2768 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of Art2768 module 8 2 Analog Signal Output Calibration In the manual we introduce how to calibrate ART2768 in 5V input range calibrations of other input ranges are similar 1 Connect the ground both of the digital voltmeter rand Plconnector the input port of the voltmeter connects with the DA which need to be calibrated 2 Zero point Calibration run ART2768 advanced program under Windows select AOO channel the DA output is set to 0 adjust the potentiometer R
11. method is using the cascade master slave card the second one 15 using the common external trigger and the last one is using the common external clock When using master slave cascade card programs the master card generally uses the internal clock source model while the slave card uses the external clock source mode After the master card and the slave card are initialized according to the corresponding clock source mode At first start all the slave cards as the main card has not been activated and there is no output clock signal so the slave card enters the wait state until the main card was activated At this moment the multi card synchronization has been realized When you need to sample more than channels of a card you could consider using the multi card cascaded model to expand the number of channels CLKOUT Master Card Slave Card 1 Slave Card 2 When using the common external trigger please make sure all parameters of different ART2768 are the same At first configure hardware parameters and use analog or digital signal triggering ATR or DTR then connect the signal that will be sampled by ART2768 input triggering signal from ART pin or DTR pin then click Start Sampling button at this time ART2768 does not sample any signal but waits for external trigger signal When each module is waiting for external trigger signal use the common external trigger signal to startup modules at last we can realize synchronization
12. up changes have no effect on DA acquisition This function can be used the case that the acquisition will occur if the exoteric signal changes 5 2 2 DTR Trigger DAPara TriggerDir ART2768 TRIGDIR NEGATIVE that is negative trigger When the trigger signal changes from the high level to low level falling edge signal it will generate a trigger event DA immediately into the conversion process and its follow up changes have no effect on DA acquisition Beijing ART Technology Development Co Ltd V6 051 DA Start Pulse Digital Trigger Signal oo The first falling edge after the the DA started is invalid i DA started is valid Figure5 4 Falling Edge Trigger DAPara TriggerDir ART2768 TRIGDIR POSITIVE that is positive trigger When the trigger signal changes from the low level to high level rising edge signal it will generate a trigger event DA immediately into the conversion process and its follow up changes have no effect on DA acquisition When ADPara TriggerDir ART2768 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger As long as the trigger sources signal appear high level or low level rising edge or falling edge it will trigger DA immediately The follow up changes have no effect on DA acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes
13. ART2768 User s Manual Beijing Technology Development Co Ltd Beijing ART Technology Development Co Ltd V6 051 Contents CO 2 ES a 3 Chapter 2 Components Layout Diagram a Brief Description 5 2 1 The Main Component Layout Diagram 5 2 2 The Function Description for the Main Component 4 5 2 2 1 Signal Inputand Output Connectors ena han an 5 6 20 S TUGIDEE 6 2 24 Board Base Address Selection e e eere e 6 9 Chapter onnee lOS gt 10 3 1 Analog Input Output IBI E dC 10 Analog Signal __________ ______________ 10 268 Die ial Ommput C GONG 10 Chapter 4 Connection Ways for Input and Output 12 Analog 12 4 2 External Trigger Signal ART Connection 4 12 4 3 Clock input Output and Digital Trigger Signal COonnectlon sess 12 AA Digital Signal Input COBDOGLOE gt yny 13 4 5 Digital Signal Output Connection 13 4 6 Methods of Realizing the Multi card Synchronization pp 14 Chapter 5 The Instruction of the DA Trigger 16 Sob DA
14. P1to make AOO channel output OV Adjust the potentiometer RP3 RP5 RP7 to make AOI output OV 3 Full scale Calibration run ART2768 advanced program under Windows select AOO channel the DA output is set to 65535 by adjusting the potentiometer RP2 to make AOO output 4999 84mV and by adjusting the potentiometer RP6 RP to make AO1 AO3 output 4999 84mV 4 Trigger Level Calibration When use the trigger function the user can set the trigger level 0 10V by adjusting the potentiometer RP9 measure the ATR test point that outside the on board BNC5 interface to make the measured trigger level be the same as the trigger level that be set 5 Repeat steps above until meet the requirement 8 3 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data Please ensure the use of proper
15. ame as external Beijing ART Technology Development Co Ltd V6 051 Chapter 7 Address Allocation Table ART2768 register address as follows Base address 0 0 Base address 0x2 write data Base address 0x2 read data write control address 0x0000 Read back DAO MODE control word the low 7 bit effective 0x0001 Read back DAO frequency control word 16bit 0x0002 Read back DAO enable signal D15 0 disable DAO convert D15 1 start DAO to convert if use the external trigger need to wait for the trigger signal to start DA 0 allow users to access RAMO 1 disable users do any operation of the RAMO 0x0004 Read back The current low 16 bit offset address of the RAMO 0x0005 Read back The current high 2 bit offset address of the n eee tee tee 0x0006 Read DAO data from the RAMO Write the data will be converted by the DAO to the 0x000d Read back Reset output location to the cycle starting location DAO polarity setting 0 unipolar 1 bipolar DAO gain setting 0 single gain 1 double gain 0 0012 Read back enable signal D15 0 disable conversion D15 I start DA1 conversion if use the external trigger need to wait for the trigger signal to start DA O allow users access to 1 disable users do any operation of the 0x0014 Read back The current low 16 bit offset address of the RAMI 0x0015 Read back The current high 2 bit offset address of the
16. ent Co Ltd V6 051 2 2 2 Potentiometer RP1 AOO analog output zero point adjustment RP2 AOO analog output full scale adjustment RP3 AOI analog output zero point adjustment RP4 AOI analog output full scale adjustment RP5 AO2 analog output zero point adjustment RP6 AO2 analog output full scale adjustment RP7 AO3 analog output zero point adjustment RP8 AO3 analog output full scale adjustment RP9 ATR trigger level adjustment 2 2 3 Jumper JP2 JP4 AOO AO3 analog output signal reset selection when the 2 3 pins of the jumpers corresponding to the channels are shorted the range reset to the 0 code value 0x000 when 1 2 pins are shorted reset to the middle code value of the range 0x800 Corresponds to the DA range the reset value selection as follows PIRO PDRO reserved 2 2 4 Board Base Address Selection ADDRI board base address DIP switches Board base address can be set to binary code which from 200H to be divided by 16 board base address defaults 300H will occupy the base address of the date of 44 consecutive I O addresses Switch No 3 4 5 6 7 8 correspond to address bits A4 A5 A7 A8 A9 are the base address of selector switch Switch No 1 2 are reserved bits Board base address selection is as follows when the ADDRI switches dial to ON that means the high virtual is 1 the switch to the other side means the low virtual value 15 0 Base address configuration m
17. ethods BENE The third hex bits The second hex bits The first hex bits Note in the table the bit which is labeled O is a fixed value only the bit that labeled x can be changed by the ADDRI BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 6 Beijing ART Technology Development Co Ltd V6 051 For example the default base addresses is300H A8 A9 ON shown as the following A9 A7 A6 A5 A4 A3 A2 8 fi 6 5 4 3 2 1 ADDRI ON Common base address A9 A8 A7 A6 AS A4 A3 A2 8 1 6 5 4 3 2 1 9 AT AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 AS AT AS A4 A3 A2 8 fi 6 3 4 3 2 1 9 A7 A6 A5 A4 A3 A2 8 7 6 5 4 3 2 1 A9 AS A7 A6 AS A4 A3 A2 8 7 6 2 4 3 2 1 9 8 A7 A6 5 A4 A3 A2 8 7 6 3 4 3 2 1 9 A7 A6 A5 A4 A3 A2 8 7 6 4 3 2 1 A9 A7 A6 AS A4 A3 A2 8 7 6 5 4 3 2 1 A9 A8 A7 A6 A5 A4 A3 A2 8 7 6 5 4 3 2 1 9 8 A7 6 5 4 2 8
18. it Write the data will be converted by the DA2 to the RAM2 16 bit Low 16 bit of the loop start address High 2 bit of the loop start address data low 2 bit The cycle end address low 16 bit The cycle end address high 2 bit data low 2 bit The number of cycles 0 indicates an infinite loop Single point immediate output DA2 data 16 bit Reset RAM2 output location to the cycle starting location DA2 polarity setting 0 unipolar 1 bipolar DA2 gain setting 0 single gain 1 double gain DA3 MODE control word the low 6 bit effective frequency control word 16 bit enable signal D15 0 disable DA3 conversion D15 1 start DA3 conversion if use the external trigger need to wait for the trigger signal to start DA O allow users access to RAM3 1 disable users do any operation of the RAM3 The current low 16 bit offset address of the RAM3 The current high 2 bit offset address of the RAM3 NO Beijing ART Technology Development Co Ltd V6 051 0x0036 Read DA3 data from the RAM2 Write the data will be converted by the DA3 to the 16 bit 0x0037 Read back Low 16 bit of the loop start address 0x0038 Read back High 2 bit of the loop start address data low 2 bit 0x0039 Read back The cycle end address low 16 bit 0x003a Read back The cycle end address high 2 bit data low 2 bit 0x003b Read back The number of cycles 0 indicates an infinite loop 0x003c Read
19. ly licensed software with our systems ART does not condone the use of pirated BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 23 Beijing ART Technology Development Co Ltd V6 051 software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service 15 not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments 1 e high temperatures high humidity or volatile chemicals V V Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 24 Beijing ART Technology Development Co Ltd V6 051 Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board ty
20. pe on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start Programs ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD 15 normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch 1s normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others gt SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and
21. reas of data acquisition waveform analysis and processing system And also can constitute industrial process monitoring system Its main applications are Electronic Product Quality Testing m Signal acquisition Process Control m Servo Control Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt _ Art2768 Data Acquisition Board ART Disk a user s manual pdf b drive catalog Warranty Card DA Arbitrary Waveform Output Function Converter Type DAC7641 Output Range 0 5V 0 10V 5V 10V Resolution 16 bit Output Point Rate Frequency up to IMHz lus point software adjustable adjustable range 0 01 Hz IMHz Number of Channels 4 Trigger Source software trigger source hardware analog trigger source hardware digital trigger source DTR Trigger Level 0 10V Trigger Direction TriggerDir negative trigger positive trigger either positive or negative trigger WV Clock Source internal clock and external software selectable Memory Depth each channel is 256K word point RAM Memory Data Transmission program mode DA Set up Time 10us 0 003 accuracy Non linear Error
22. reted as the software trigger As for the specific process please see the figure below the cycle of the DA work pulse is decided by the sampling freguency oo The first working pulse after the DA 3 start pulse Figure 5 1 Internal Trigger Mode 5 2 DA External Trigger Mode When DA is in the initialization if the DA hardware parameter DAPara TriggerSource ART2768 TRIGSRC ATR we can achieve the ATR trigger acquisition if DAPara TriggerSource ART2768 TRIGSRC DTR we can achieve the DTR trigger acquisition In this function calling theInitDeviceDA function to initial the device then wait EnableDeviceDA function to start DA DA will not immediately access to the conversion process but wait for the external trigger source signals accord with the condition then start converting the data It also can be interpreted as the hardware trigger Trigger source includes the DTR Digital Trigger Source and ATR Analog Trigger Source 5 2 1 ATR Trigger Analog trigger source uses the analog signal which can change in a certain range The trigger source signal provided by the ATR and the analog trigger level are into the comparator simultaneously and the do high speed analog comparison in the comparator generate a comparison expected result Result to trigger DA see below Analog trigger signal decided by the voltage that output by the serial D A The analog trigger source signal effective range is
23. then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 10 62991792 609 CN 25
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