ADSP-2104/ADSP-2109 Low Cost DSP Microcomputers
Contents
1. K Grade Parameter Min Max Unit Vpp Supply Voltage 4 50 5 50 V Tams Ambient O perating T emperature 0 70 C See Environmental Conditions for information on thermal specifications ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min Max Unit Vi Hi Level Input Voltage 9 Vpp max 2 0 V Vin Hi Level CLKIN Voltage Vpp max 2 2 V Vu Lo L evel Input Voltage Vpp min 0 8 V Vou Hi Level Output Voltage 7 9 Vpp min lop 0 5 mA 2 4 V 9 Vpp min loy 100 uA Vpp 0 3 V Vo X Lo Level Output Voltage 7 9 Von 2 min lo 2 2 mA 0 4 V liu Hi Level Input Current O Vpp max Vin Vpp max 10 uA lu Lo L evel Input Current O Vpp max Vy OV 10 uA lozu Three State Leakage C urrent Vpp max Vin Vpp max 10 uA loz Three State Leakage Current 9 Vpp max Vy 0 V 10 uA C Input Pin Capacitance Vin 2 5 V fin 1 0 MHz T amg 25 C 8 pF Co Output Pin Capacitance 92 Vi 22 5 V fiy LOMHz T amg 25 C 8 pF NOTES Unput only pins CLKIN RESET IRQ2 BR M MAP DR1 DRO 20utput pins BG PMS DMS BMS RD WR A0 A13 CLKOUT DT1 DTO Bidirectional pins D0 D23 SCLK 1 RFS1 TFS1 SCLKO RFSO TFS0 T hree state pins A0 A13 D0 D23 PMS DMS BMS RD WR DT 1 SCLK1 RSF1 TFS1 DTO SCLK 0 RFSO TFSO Input only pins RESET IRQ2 BR M MAP DR1 DRO 50 V on BR CLKIN Active to force three state condition Although specified2. o E ze LILILILILTILTLILTETETLETLTCTLETLTLETLET le D a D M A SYMBOL mme A um anm anm us a P 0027 0 028 D 0985 0 990 D oss 0 952 p jo e oss zars 22182423 osss osio osos 2273 2311 7350__ e saa a joo op REV 0 35 ADSP 2104 ADSP 2109 ORDERING GUIDE Ambient Temperature Instruction Package Package Part Number Range Rate Description Option ADSP 2104K P 80 0 C to 70 C 20 0 MHz 68 Lead PLCC P 68A ADSP 2109KP 80 0 C to 70 C 20 0 MHz 68 Lead PLCC P 68A ADSP 2104LK P 55 0 C to 70 C 13 824 M Hz 68 Lead PLCC P 68A ADSP 2109L KP 55 0 C to 70 C 13 824 M Hz 68 Lead PLCC P 68A K Commercial T emperature Range 0 C to 70 C P PLCC Plastic Leaded Chip Carrier 36 REV 0 C2145 16 7 96 PRINTED IN U S A
3. dreg lt ALU gt lt MAC gt lt SHIFT gt PM Ix My dreg lt ALU gt lt MAC gt lt SHIFT gt dreg DM Ix My dreg PM Ix My lt ALU gt MAC dreg DM Ix My dreg PM Ix My D ata M emory Read D irect A ddress D ata M emory Read Indirect A ddress Program M emory Read Indirect A ddress D ata M emory W rite D irect A ddress D ata M emory W rite Indirect A ddress Program M emory W rite Indirect A ddress Computation with Register to R egister M ove Computation with M emory Read Computation with M emory Read Computation with M emory W rite Computation with M emory W rite Data amp Program M emory Read ALU MAC with Data amp Program M emory R ead 10 REV 0 ADSP 2104 ADSP 2109 Program Flow Instructions DO lt addr gt UNTIL term Do Until Loop IF cond JUMP 1x Jump IF cond JUMP lt addr gt IF cond CALL Ix Call Subroutine IF cond CALL addr IF NOT FLAG IN JUMP lt addr gt ump Call on Flagln Pin IF NOT FLAG IN CALL addr IF cond SET RESET TOGGLE FLAG OUT M odify Flag Out Pin IF cond RTS Return from Subroutine IF cond RTI Return from Interrupt Service Routine IDLE n dle Miscellaneous Instructions NOP No Operation MODIFY Ix M y M odify Address R egister PUSH STS POP CNTR POP PC POP LOOP Stack Control ENAJDIS SEC REG M ode Control BIT REV AV LATCH AR SAT M MODE TIMER G MODE Notat
4. 6 4 Vpp 3 0V 2 NOMINAL 2 VALID OUTPUT DELAY OR HOLD ns 25 50 75 100 125 150 CL pF Figure 15 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature REV 0 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104L ADSP 2109L TEST CONDITIONS Figure 16 shows voltage reference levels for ac measurements VoD INPUT Zz VoD OUTPUT 2 Figure 16 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state T he output disable time tp s is the difference of tueasurep and tpecay as shown in Figure 17 The time tyeasurep is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 5 V from the measured output high or low voltage REFERENCE SIGNAL Vou MEASURED VoL MEASURED OUTPUT STOPS DRIVING Figure 17 Output T he decay time tpecay is dependent on the capacitative load C and the current load ij on the output pin It can be approximated by the following equation C x0 5V I toecay from which tbis tueasureo toecay is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the las
5. TRANSMIT REG TRANSMIT REG OUTPUT REGS OUTPUT REGS OUTPUT REGS RECEIVE REG RECEIVE REG SERIAL SERIAL PORTO PORT 1 R Bus 5 Hf 5 Hf Figure 1 ADSP 2104 ADSP 2109 Block Diagram ARCHITECTURE OVERVIEW Figure 1 shows a block diagram of the AD SP 2104 AD SP 2109 architecture T he processor contains three independent compu tational units the ALU the multiplier accumulator M AC and the shifter T he computational units process 16 bit data directly and have provisions to support multiprecision computations TheALU performs a standard set of arithmetic and logic operations division primitives are also supported TheM AC performs single cycle multiply multiply add and multiply subtract operations T he shifter performs logical and arithmetic shifts normalization denormalization and derive exponent operations T he shifter can be used to efficiently implement numeric format control including multiword floating point representations The internal result R bus directly connects the computational units so that the output of any unit may be used as the input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units T he sequencer supports conditional jumps subroutine calls and returns in a single cycle With internal loop counters and loop stacks the AD SP 2104 AD SP 2109 executes looped code with zero overhead no explicit jump instructions
6. 10 MHz 22 5 mW RD 1 x10pF x5 V x10MHz 2 5 mW CLKOUT 1 x 10 pF x5 V x20MHz 5 0mW 70 0 mW Total power dissipation for this example Pint 70 0 mW ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tams T case PD x Oca T case Case T emperature in C PD Power Dissipation in W 0c4 T hermal Resistance C ase to A mbient Oja Thermal Resistance Junction to A mbient jc Thermal Resistance J unction to C ase Package 0jA jc Oca PLCC 27 C W 16 C W 11 C W 14 CAPACITIVE LOADING Figures 8 and 9 show capacitive loading characteristics 8 7 Vpp 4 5V RISE TIME 0 8V 2 0V ns 0 0 25 50 75 100 125 150 175 C pF Figure 8 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature Vpp 45V VALID OUTPUT DELAY OR HOLD ns 0 25 50 75 100 125 C pF 150 175 Figure 9 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature REV 0 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104 ADSP 2109 T he decay time tpecay is dependent on the capacitative load C and the current load i on the output pin It can be TEST CONDITIONS approximated by the following equation Figure 10 shows voltage reference levels for ac measurements C x0 5V 3 0V toecay GE ED INPUT 1 5V t 0 0V from w
7. Valid CLKOUT SCLK tscs tscH DR RFSIN TFSIN ta taH lt gt RFSOUT TFSOUT tscpp DT trov TFS ALTERNATE FRAME MODE trov RFS MULTICHANNEL MODE FRAME DELAY 0 MFD 0 Figure 30 Serial Ports REV 0 33 ADSP 2104 ADSP 2109 PIN CONFIGURATIONS 68 Lead PLCC PIN 1 IDENTIFIER ADSP 2104 ADSP 2104L ADSP 2109 ADSP 2109L TOP VIEW PINS DOWN PLCC Pin Number Name 1 D11 2 GND 3 D12 4 D 13 5 D14 6 D15 7 D16 8 D17 9 D18 10 GND 11 D19 12 D20 13 D21 14 D22 15 D23 16 Vpp 17 MMAP es 24 252s Eu ES ES ESET 56 57 F5 3393322202 ER HI So PLCC Pin PLCC Pin Number Name Number Name 18 BR 35 A12 19 RO2 36 A13 20 RESET 37 PMS 21 A0 38 DMS 22 A1 39 BMS 23 A2 40 BG 24 A3 41 XTAL 25 A4 42 CLKIN 26 Vo 43 CLKOUT 27 A5 44 WR 28 A6 45 RD 29 GND 46 DTO 30 A7 47 TFSO 31 A8 48 RFSO 32 A9 49 GND 33 A10 50 DRO 34 All 51 SCLKO 34 PLCC Pin Number Name 52 FO DT1 53 IRQ TFS1 54 ROO RFS1 55 FI DR1 56 SCLK1 57 Vpp 58 DO 59 D1 60 D2 61 D3 62 D4 63 D5 64 D6 65 D7 66 D8 67 D9 68 D10 REV 0 ADSP 2104 ADSP 2109 OUTLINE DIMENSIONS ADSP 210 ADSP 2109 68 Lead Plastic Leaded Chip Carrier PLCC LY e PIN 1 IDENTIFIER o TOP VIEW PINS DOWN BOTTOM VIEW PINS UP
8. are required to maintain the loop N ested loops are also supported T wo data address generators DAGs provide addresses for simultaneous dual operand fetches from data memory and program memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four modify registers A length value may be associated with each pointer to implement automatic modulo addressing for REV 0 circular buffers T he circular buffering feature is also used by the serial ports for automatic data transfers to and from on chip memory Efficient data transfer is achieved with the use of five internal buses Program M emory Address PM A Bus Program M emory Data PM D Bus Data M emory Address DM A Bus Data M emory Data DM D Bus Result R Bus T hetwo address buses PM A DM A share a single external address bus allowing memory to be expanded off chip and the two data buses PM D DM D share a single external data bus T he BMS DMS and PMS signals indicate which memory space is using the external buses Program memory can store both instructions and data permit ting the AD SP 2104 AD SP 2109 to fetch two operands in a single cycle one from program memory and one from data memory T he processor can fetch an operand from on chip program memory and the next instruction in the same cycle T he memory interface support
9. value of the count register reaches zero an interrupt is generated and the count register is reloaded from a 16 bit period register T PERIOD Serial Ports The ADSP 2104 AD SP 2109 processor includes two synchro nous serial ports SPORT s for serial communications and multiprocessor communication T he serial ports provide a complete synchronous serial interface with optional companding in hardware A wide variety of framed or frameless data transmit and receive modes of opera tion are available Each SPORT can generate an internal programmable serial clock or accept an external serial clock Each serial port has a 5 pin interface consisting of the following signals Signal Name Function SCLK Serial Clock 1 0 RFS Receive Frame Synchronization 1 0 TFS T ransmit Frame Synchronization 1 0 DR Serial D ata Receive DT Serial Data T ransmit T he serial ports offer the following capabilities Bidirectional Each SPORT has a separate double buffered transmit and receive function Flexible Clocking Each SPORT can use an external serial clock or generate its own clock internally Flexible Framing T he SPORT s have independent framing for the transmit and receive functions each function can run in a frameless mode or with frame synchronization signals inter nally generated or externally generated frame sync signals may be active high or inverted with either of two pulse widths and timings Differe
10. 13 83 20 00 25 00 30 00 10 00 13 83 20 00 25 00 30 00 FREQUENCY MHz FREQUENCY MHz 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2 IDLE REFERS TO ADSP 2104 ADSP 2109 OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3 MAXIMUM POWER DISSIPATION AT Vpp 5 5V DURING EXECUTION OF DLE n INSTRUCTION Figure 7 ADSP 2104 ADSP 2109 Power Typical vs Frequency REV 0 13 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104 ADSP 2109 POWER DISSIPATION EXAMPLE To determine total power dissipation in a specific application the following eguation should be applied for each output C xVpp x f C load capacitance f output switching frequency Example In an ADSP 2104 application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin T he application operates at Vpp 5 0 V and tex 50 ns Total Power Dissipation Pyyt C xVpp x f Pint internal power dissipation from Figure 7 C x Vpp x f is calculated for each output of Output Pins x C x Vpp x f Address DMS 8 x10pF x5 V x 20 MHz 40 0 mW Data WR 9 x10pF x5 V x
11. A13 PMS DMS BMS Setup before 2 5 ns RD Low TRDA A0 A13 PMS DMS BMS Hold after RD 3 5 ns Deasserted TRWR RD High to RD or WR Low 20 ns Freguency Dependency CLKIN lt 20 MHz Parameter Min Max Unit Timing Reguirement TRDD RD Low to Data Valid 0 5tck 13 w ns taa A0 A13 PMS DMS BMS to Data Valid 0 75tck 18 w ns trp Data Hold from RD High 0 Switching Characteristic trp RD Pulse Width 0 5tc 8 w ns tero CLKOUT High to RD Low 0 25tcK 5 0 25tcx 10 ns tasr A0 A13 PMS DMS BMS Setup before RD Low 0 25tcx 10 ns t pa A0 A13 PMS DMS BMS Hold after RD Deasserted 0 25tcx 9 ns trwr RD High to RD or WR Low 0 5tck 5 ns NOTE w wait states x tck CLKOUT A0 A13 DMS PMS BMS Figure 22 Memory Read 24 REV 0 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 MEMORY WRITE 20 MHz Parameter Min Max Unit Switching Characteristic tow Data Setup before WR High 12 ns tp Data Hold after WR High 2 5 ns twp WR Pulse Width 17 ns twpE WR Low to Data Enabled 0 ns tasw A0 A13 DMS PMS Setup before 2 5 ns WR Low tppR Data Disable before WR or RD Low 2 5 ns tcwr CLKOUT High to WR Low 7 5 22 5 ns taw A0 A13 DMS PMS Setup before WR 15 5 ns Deasserted tyra AO A13 DMS PMS Hold after WR 3 5 ns Deasserted twwrR WR High to RD or WR Low 20 ns Frequency Dependency CLKIN lt 20MHz Parameter Min Max Unit Switching C
12. ANALOG DEVICES Low Cost DSP Microcomputers ADSP 2104 ADSP 2109 SUMMARY 16 Bit Fixed Point DSP Microprocessors with On Chip Memory Enhanced Harvard Architecture for Three Bus Performance Instruction Bus Dual Data Buses Independent Computation Units ALU Multiplier Accumulator and Shifter Single Cycle Instruction Execution amp Multifunction Instructions On Chip Program Memory RAM or ROM amp Data Memory RAM Integrated I O Peripherals Serial Ports and Timer FEATURES 20 MIPS 50 ns Maximum Instruction Rate Separate On Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data Three Bus Performance Dual Data Address Generators with Modulo and Bit Reverse Addressing Efficient Program Sequencing with Zero Overhead Looping Single Cycle Loop Setup Automatic Booting of On Chip Program Memory from Byte Wide External Memory e g EPROM Double Buffered Serial Ports with Companding Hardware Automatic Data Buffering and Multichannel Operation Three Edge or Level Sensitive Interrupts Low Power IDLE Instruction PLCC Package GENERAL DESCRIPTION The ADSP 2104 and AD SP 2109 processors are single chip microcomputers optimized for digital signal processing D SP and other high speed numeric processing applications T he AD SP 2104 AD SP 2109 processors are built upon a common core Each processor combines the core DSP architecture computation units data address generators and pr
13. BMS RD WR Enable to CLKOUT High 8 1 0 25tcy 10 ns NOTES Tf BR meets the tgs and tpy setup hold requirements it will be recognized in the current processor cycle otherwise it is recognized in the following cycle BR requires a pulse width greater than 10 ns Note BG is asserted in the cycle after BR is recognized No external synchronization circuit is needed when BR is generated as an asynchronous signal teu CLKOUT TED co V CLKOUT PMS DMS ee m WR Figure 27 Bus Reguest Grant 30 REV 0 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L MEMORY READ Frequency 13 824 MHz Dependency Parameter Min Max Min Max Unit Timing Requirement trpp RD Low to Data Valid 23 2 0 5tcn 13 w ns TAA A0 A13 PMS DMS BMS to Data Valid 36 2 0 75tck 18 w ns TRDH Data Hold from RD High 0 0 ns Switching Characteristic trp RD Pulse Width 28 2 0 5tcx 8 w ns tcrp CLKOUT High to RD Low 13 1 28 1 0 25tck 5 0 25tcxk 10 ns TASR A0 A13 PMS DMS BMS Setup before RD Low 8 1 0 25tck 10 ns TRDA A0 A13 PMS DMS BMS Hold after RD Deasserted 9 1 0 25tckx 9 ns trwR RD High to RD or WR Low 31 2 0 5tck 5 ns w wait states x tex CLKOUT A0 A13 DMS PMS BMS Figure 28 Memory Read REV 0 31 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L MEMORY WRITE Frequency 13 824 MHz Depen
14. FS0 TFS0 gt 0 Von BR CLKIN Active to force three state condition 6 All outputs are CMOS and will drive to Vpp and GND with no dc loads 7 Guaranteed but not tested 8 Applies to PLCC package type Output pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Voltage eee eee ee 0 3 V to 4 5V Input Voltage a 0 3 V to Vy 0 3 V Output Voltage Swing 0 3 V to Vy 0 3 V Operating T emperature Range Ambient 40 C to 85 C Storage T emperature Range 65 C to 150 C Lead T emperature 5 sec PLCC 000 280 C Stresses greater than those listed above may cause permanent damage to the device T hese are stress ratings only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 16 REV 0 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104L ADSP 2109L SUPPLY CURRENT 6 POWER ADSP 2104L ADSP 2109L Parameter Test Conditions Min Max Unit Ipp Supply Current D ynamic Vpp max tck 72 3 ns 14 mA lop Supply Current Idle 3 9 Vpp max tck 72 3 ns 4 MA NOTES 1Current reflects device operating with no output loads Viy 0 4V and 24 V gt I dle refers
15. IN RFSOUT TFSOUT DT trp RH tscovre tscpe 4 tov tscs tscH TFS ALTERNATE X FRAME MODE RFS MULTICHANNEL MODE X FRAME DELAY 0 MFD 0 Figure 24 Serial Ports 26 tscpp REV 0 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L Timing requirements apply to signals that are controlled by GENERAL NOTES circuitry external to the processor such as the data input for a U se the exact timing information given D o not attempt to read operation T iming requirements guarantee that the derive parameters from the addition or subtraction of others processor operates correctly with other devices While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect cte indes trier devi ificati statistical variations and worst cases C onsequently you cannot 3f d ee Mic AD SP DLOAUIND SP JOE m i meaningfully add parameters to derive longer times p g j g parameters for your convenience TIMING NOTES Switching characteristics specify how the processor changes its signals You have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device conn
16. asp RESET Width Low 250 5tck ns Switching Characteristic tcp CLKOUT Width Low 15 0 5tcx 10 ns to CLKOUT Width High 15 0 5tck 10 ns tekon CLKIN High to CLKOUT High 0 20 ns NOTE Applies after powerup sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator startup time CLKIN CLKOUT Figure 19 Clock Signals REV 0 21 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 INTERRUPTS 6 FLAGS Frequency 20MHz Dependency Parameter Min Max Min Max Unit Timing Requirement t rs IRQx or FI Setup before 27 5 0 25tc 15 ns CLKOUT Low ru IRQx or FI Hold after CLKOUT 12 5 0 25tck ns High 3 Switching Characteristic tron FO Hold after CLKOUT High 0 0 ns trop FO Delay from CLKOUT High 15 ns NOTES TROx TRQO IRQI and IRQ2 If IRQx and FI inputs meet t rs and typy setup hold requirements they will be recognized during the current clock cycle otherwise they will be recognized during the following cycle Refer to the Interrupt Controller section in Chapter 3 Program Control of the ADSP 2100 Family User s M anual for further information on interrupt servicing 3Edge sensitive interrupts require pulse widths greater than 10 ns L evel sensitive interrupts must be held low until serviced CLKOUT ie NEL trou FLAG OUTPUT S rH JRQx FI ties Figure 20 Interrupts a
17. ates a read operation and can be used as a read strobe or output enable signal The AD SP 2104 AD SP 2109 processors support memory mapped I O with the peripherals memory mapped into the data memory address space and accessed by the processor in the same manner as data memory Data Memory Map ADSP 2104 On chip data memory RAM resides in the 256 words beginning at address 0x3800 also shown in Figure 6 D ata memory locations from 0x3900 to the end of data memory at 0x3F F F are reserved Control and status registers for the system timer wait state configuration and serial port operations are located in this region of memory 0x0000 1K EXTERNAL DWAITO 0x0400 1K EXTERNAL DWAIT1 0x0800 10K EXTERNAL EXTERNAL DWAIT2 RAM 0x3000 1K EXTERNAL DWAIT3 0x3400 1K EXTERNAL DWAIT4 0x3800 256 WORDS 0x3900 INTERNAL RAM 0x3C00 MEMORY MAPPED CONTROL REGISTERS amp RESERVED 0x3FFF Figure 6 Data Memory Map The remaining 14K of data memory is located off chip T his external data memory is divided into five zones each associated with its own wait state generator T his allows slower peripherals to be memory mapped into data memory for which wait states are specified By mapping peripherals into different zones you can accommodate peripherals with different wait state require ments All zones default to seven wait states after RESET ADSP 2104 ADSP 2109 Boot Memory Interface Boot memory is an external 16K by 8
18. ching characteristics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing requirements apply to signals that are controlled by circuitry external to the processor such as the data input for a read operation T iming requirements guarantee that the processor operates correctly with other devices MEMORY REQUIREMENTS T hetable below shows common memory device specifications and the corresponding AD SP 2104 A D SP 2109 timing parameters for your convenience Memory ADSP 2104 ADSP 2109 Timing Device Timing Parameter Specification Parameter Definition Address Setup to Write Start tasw A0 A13 DMS PMS Setup before WR Low Address Setup to Write End taw A0 A13 DMS PMS Setup before WR Deasserted Address Hold Time twra A0 A13 DMS PMS Hold after WR Deasserted Data Setup Time tow Data Setup before WR High Data Hold Time tp Data Hold after WR High OE to Data Valid trpp RD Low to Data Valid Address Access Time taa A0 A13 DMS PMS BMS to Data Valid 20 REV 0 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 CLOCK SIGNALS amp RESET Frequency 20MHz Dependency Parameter Min Max Min Max Unit Timing Requirement tek CLKIN Period 50 150 ns tek CLKIN Width Low 20 20 ns teku CLKIN Width High 20 20 ns t
19. computational instruc tions multifunction instructions program flow control instruc tions and miscellaneous instructions M ultifunction instructions perform one or two data moves and a computation The instruction set is summarized below TheADSP 2100 Family U sers M anual contains a complete reference to the instruction set A dd A dd with Carry Subtract X Y Subtract X Y with Borrow Subtract Y X Subtract Y X with Borrow MR X0p x yop MR xop yop M 1 0 IF MV SAT MR Shifter Instructions IF cond SR SR OR ASHIFT xop IF cond SR SR OR LSHIFT xop SR SR OR ASHIFT xopBY lt exp gt SR SR OR LSHIFT xop BY lt exp gt IF cond SE EXP xop IF cond SB EXPAD xop IF cond SR SR OR NORM xop Data Move Instructions reg reg reg data M ultiply A ccumulate M ultiply Subtract Transfer M R Clear Conditional M R Saturation Arithmetic Shift Logical Shift Arithmetic Shift Immediate L ogical Shift Immediate D erive Exponent Block Exponent A djust N ormalize R egister to R egister M ove Load Register Immediate reg DM lt addr gt dreg DM Ix My dreg 2 PM Ix My DM lt addr gt reg DM Ix My dreg PM Ix My dreg Multifunction Instructions lt ALU gt lt MAC gt lt SHIFT gt dreg dreg lt ALU gt lt M AC gt lt SHIFT gt dreg DM Ix My lt ALU gt lt MAC gt lt SHIFT gt dreg PM Ix My DM Ix My
20. dency Parameter Min Max Min Max Unit Switching Characteristic _ tpw Data Setup before WR High 23 2 0 5tck 13 w ns tpu Data Hold after WR High 8 1 0 25tcx 10 ns twp WR Pulse Width 28 2 0 5tck 8 w ns twpE WR Low to Data Enabled mE 0 tasw A0 A13 DMS PMS Setup before WR Low 8 1 0 25tcx 10 ns tppR Data Disable before WR or RD Low 8 1 0 25tck 10 ns tcwn CLKOUT High to WR Low o 13 1 28 1 0 25tck 5 0 25tck 10 ns taw A0 A13 DMS PMS Setup before WR Deasserted 32 2 0 75tck 22 w ns twra A0 A13 DMS PMS Hold After WR Deasserted 9 1 0 25tcx 9 ns twwn WR High to RD or WR Low 31 2 0 5tck 5 ns w wait states x tex CLKOUT NM E NEP AN A0 A13 DMS PMS Figure 29 Memory Write 32 REV O ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L SERIAL PORTS Frequency 13 824 MHz Dependency Parameter Min Max Min Max Unit Timing R equirement tsck SCLK Period 72 3 ns tscs DR TFS RFS Setup before SCLK Low 8 ns tscu DR TFS RFS Hold after SCLK Low 10 ns tscp SCLK in Width 28 ns Switching Characteristic tec CLKOUT High to SCLK out 18 1 33 1 0 25tc 0 25tck 15 ns tscpg SCLK High to DT Enable 0 ns tscoy SCLK High to DT Valid 20 ns tau TFS RF Sout Hold after SCLK High 0 ns tap TFS RF Sout Delay from SCLK High 20 ns tscpu DT Hold after SCLK High 0 ns trpe TFS alt to DT Enable 0 ns troy TFS alt to DT Valid 18 ns tscoo SCLK High to DT Disable 25 ns tkov RFS M ultichannel F rame D elay Zero 20 ns to DT
21. e PLL has locked this does not however include the crystal oscillator start up time During this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the minimum pulse width specification tap To generate the RESET signal use either an RC circuit with an external Schmidt trigger or a commercially available reset IC D o not use only an RC circuit ADSP 2104 or ADSP 2109 SERIAL DEVICE pra TFS1 or IRQ1 DT1 or FO OPTIONAL DR1 or FI The RESET input resets all internal stack pointers to the empty stack condition masks all interrupts and clears the M ST AT register When RESET is released the boot loading sequence is performed provided there is no pending bus request and the chip is configured for booting with M M AP 0 T he first instruction is then fetched from internal program memory location 0x0000 Program Memory Interface Theon chip program memory address bus PM A and on chip program memory data bus PM D are multiplexed with the on chip data memory buses DM A DMD creating a single external data bus and a single external address bus T he external data bus is bidirectional and is 24 bits wide to allow instruction fetches from external program memory Program memory may contain code and data T he external address bus is 14 bits wide T he data lines are bidirectional T he program memory select PMS signal indicates access
22. ecommended Operating Conditions 12 Electrical Characteristics 2 ese eee 12 Supply Current amp Power 0 cece eee eee 13 Power Dissipation Example 00 0 c eee 14 Environmental Conditions 0 0 0 eee eae 14 Capacitive Loading 0 cece eee eee eee 14 Test Conditions aaa 15 windowed user interface A PROM splitter utility generates PROM programmer compatible files EZ ICE in circuit emulators allow debugging of AD SP 2104 systems by providing a full range of emulation functions such as modification of memory and register values and execution breakpoints EZ LAB demonstration boards are complete D SP systems that execute EPROM based programs T he EZ Kit Lite is a very low cost evaluation development platform that contains both the hardware and software needed to evaluate the AD SP 21xx architecture Additional details and ordering information is available in the ADSP 2100 Family Software amp Hardware D evdopment T ools data sheet ADD S 21xx T OOLS T his data sheet can be requested from any Analog D evices sales office or distributor Additional Information T his data sheet provides a general overview of ADSP 2104 AD SP 2109 processor functionality For detailed design information on the architecture and instruction set refer to the ADSP 2100 Family User s M anual available from Analog D evices EZ ICE and EZ LAB are registered trademarks of Analog D evices I
23. ected to the processor such as memory is satisfied ADSP 2104L ADSP 2109L Memory Specification Timing Parameter Timing Parameter Definition Address Setup to Write Start tasw A0 A13 DMS PMS Setup before WR Low Address Setup to Write End taw A0 A13 DMS PMS Setup before WR Deasserted Address Hold Time twra A0 A13 DMS PMS Hold after WR Deasserted Data Setup Time tow Data Setup before WR High Data Hold Time tp Data Hold after WR High OE to Data Valid trpp RD Low to Data Valid Address Access Time taa A0 A13 DMS PMS BMS to Data Valid REV 0 27 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L CLOCK SIGNALS amp RESET Frequency 13 824 MHz Dependency Parameter Min Max Min Max Unit Timing Requirement tck CLKIN Period 72 3 150 ns tckr CLKIN Width Low 20 20 ns texy CLKIN Width High 20 20 ns trsp RESET Width Low 361 5 Steg ns Switching Characteristic tcPL CLKOUT Width Low 26 2 0 5tck 10 ns tcpH CLKOUT Width High 26 2 0 5tck 10 ns tckog CLKIN High to CLKOUT High 0 20 ns NOTE Applies after powerup sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator startup time CLKIN CLKOUT Figure 25 Clock Signals 28 REV 0 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L INTERRUPTS amp FLAGS Frequency 13 824 MHz Dependency Para
24. ed the AD SP 21xx will remain in the IDLE state for up to a maximum of n CLKIN cycles wheren 16 32 64 or 128 before resuming normal operation When theIDLE n instruction is used in systems that have an externally generated serial clock SC LK the serial clock rate may be faster than the processor s reduced internal clock rate U nder these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the IDLE state a maximum of n CLKIN cycles 8 REV 0 ADSP 2104 ADSP 2109 ADSP 2109 Prototyping You can prototype your AD SP 2109 system with the AD SP 2104 RAM based processor When code is fully developed and debugged it can be submitted to Analog D evices for conversion into a ADSP 2109 ROM product TheADSP 2101 EZ ICE emulator can be used for develop ment of AD SP 2109 systems For the 3 3 V ADSP 2109 a voltage converter interface board provides 3 3 V emulation Additional overlay memory is used for emulation of AD SP 2109 systems It should be noted that due to the use of off chip overlay memory to emulate the AD SP 2109 a performance loss may be experienced when both executing instructions and fetching program memory data from the off chip overlay memory in the same cycle T his can be overcome by locating program memory data in on chip memory Ordering Procedure for AD SP 2109 ROM Processor T o place an order for a custom ROM c
25. es to program memory and can be used as a chip select signal T he write WR signal indicates a write operation and is used as a write strobe T he read RD signal indicates a read operation and is used as a read strobe or output enable signal T he processor writes data from the 16 bit registers to 24 bit program memory using the PX register to provide the lower eight bits When the processor reads 16 bit data from 24 bit program memory to a 16 bit data register the lower eight bits are placed in the PX register T he program memory interface can generate 0 to 7 wait states for external memory devices default is to 7 wait states after RESET BOOT MEMORY PROGRAM MEMORY OPTIONAL DATA MEMORY A amp PERIPHERALS OPTIONAL THE TWO MSBs OF THE DATA BUS D23 22 ARE USED TO SUPPLY THE TWO MSBs OF THE BOOT MEMORY EPROM ADDRESS THIS IS ONLY REQUIRED FOR THE 27256 AND 27512 Figure 3 ADSP 2104 ADSP 2109 System 6 REV 0 ADSP 2104 ADSP 2109 Program Memory Maps Program memory can be mapped in two ways depending on the state of the M M AP pin Figure 4 shows the ADSP 2104 program memory maps Figure 5 shows the program memory EXTERNAL 14K maps for the ADSP 2109 0x0000 0x0000 INTERNAL RAM 512 WORDS LOADED FROM EXTERNAL BOOT MEMORY OxO1FF 0x0200 RESERVED 1 5K 0x07FF 0x0800 EXTERNAL 14K MMAP 0 0x37FF 0x3800 INTERNAL RAM 512 WORDS Ox39FF 0x3A00 RESERVED 1 5K O
26. f the following operations Generate the next program address Fetch the next instruction Perform one or two data moves U pdate one or two data address pointers Perform a computation Receive and transmit data via one or two serial ports The ADSP 2104 contains 512 words of program RAM 256 words of data RAM an interval timer and two serial ports TheADSP 2104L isa3 3 volt power supply version of the ADSP 2104 it is identical to the AD SP 2104 in all other characteristics TheADSP 2109 contains 4K words of program ROM and 256 words of data RAM an interval timer and two serial ports TheADSP 2109L is a 3 3 volt power supply version of the AD SP 2109 it is identical to the AD SP 2109 in all other characteristics Analog Devices Inc 1996 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 ADSP 2104 ADSP 2109 The ADSP 2109 isa memory variant version of the AD SP 2104 and contains factory programmed on chip ROM program memory The ADSP 2109 eliminates the need for an external boot EPROM in your system and can also eliminate the need for any external program memory by fitting the entire application program in on chip ROM This device provides an excellent option for volume applications where board space and system cost constraints are of critical concern Development Tools TheADSP 2104 AD SP 2109 processors are supported by a complete set of tools for s
27. feature is not used the BR input should be tied high to Vpp Low Power IDLE Instruction ThelDLE instruction places the processor in low power state in which it waits for an interrupt When an interrupt occurs it is serviced and execution continues with instruction following IDLE Typically this next instruction will be a JUM P back to the IDLE instruction T his implements a low power standby loop ThelDLE n instruction is a special version of IDLE that slows the processor s internal clock signal to further reduce power consumption T he reduced clock frequency a programmable fraction of the normal clock rate is specified by a selectable divisor n given in the IDLE instruction T he syntax of the instruction is IDLE n where n 16 32 64 or 128 T heinstruction leaves the chip in an idle state operating at the slower rate While it is in this state the processor s other internal clock signals such as SCLK CLKOUT and the timer clock are reduced by the same ratio U pon receipt of an enabled interrupt the processor will stay in the ID LE state for up to a maximum of n CLKIN cycles wheren is the divisor specified in the instruction before resuming normal operation When the IDLE n instruction is used it slows the processor s internal clock and thus its response time to incoming interrupts the 1 cycle response time of the standard IDLE state is in creased by n the clock divisor When an enabled interrupt is receiv
28. for TTL outputs all AD SP 2104 AD SP 2109 outputs are C M OS compatible and will drive to V pp and GND assuming no dc loads 8G uaranteed but not tested Applies to PGA PLCC PQFP package types Output pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Voltage eene 0 3V to 7V Input Voltage a 0 3 V to Vy 0 3V Output Voltage Swing 0 3 V toV 0 3V Operating T emperature Range Ambient 55 C to 125 C Storage Temperature Range 65 C to 125 C Lead T emperature 10 sec PGA 000 300 C Lead T emperature 5 sec PLCC PQFP TQFP 280 C Stresses greater than those listed above may cause permanent damage to the device T hese arestress ratings only and functional operation ofthe device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD SP 2104 AD SP 2109 processor features proprietary ESD protection circuitry to dissipate WARNING high energy electrostatic discharges H uman Body M odel per
29. haracteristic tpw Data Setup before WR High 0 5tck 13 w ns tpy Data Hold after WR High 0 25tcy 10 ns twp WR Pulse Width O 5tck 8 w ns typg WR Low to Data Enabled 0 tasw A0 A13 DMS PMS Setup before WR Low 0 25tcx 10 ns toor Data Disable before WR or RD Low 0 25tck 10 ns tcwr CLKOUT High to WR Low 0 25tck 5 0 25tcy 10 ns tay A0 A13 DMS PMS Setup before WR Deasserted 0 75tck 22 w ns twra A0 A13 DMS PMS Hold after WR Deasserted 0 25tcK 9 ns twwr WR High to RD or WR Low 0 5tck 5 ns CLKOUT Lu c cM wc X A0 A13 DMS PMS Figure 23 Memory Write REV 0 25 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 SERIAL PORTS Frequency 13 824 MHz Dependency Parameter Min Max Min Max Unit Timing Reguirement tsck SCLK Period 72 3 ns tscs DR TFS RFS Setup before SCLK Low 8 ns tscy DR TFS RFS Hold after SCLK Low 10 ns tscp SCLK iy Width 28 ns Switching Characteristic tec CLKOUT High to SCLKour 18 1 33 1 0 25tck 0 25tck 15 ns tscoe SCLK High to DT Enable 0 ns tscov SCLK High to DT Valid 20 ns tau TFS RF Sour Hold after SCLK High ns tap TFS RF Sour Delay from SCLK High 20 ns tscoy DT Hold after SCLK High ns toe TFS Alt to DT Enable ns tov TFS Alt to DT Valid 18 ns tscpp SCLK High to DT Disable 25 ns trov RFS M ultichannel Frame D elay Zero 20 ns to DT Valid M aximum serial port operating frequency is 13 824 M Hz CLKOUT SCLK DR RFSIN TFS
30. hich IN tois tueasuren toecay OUTPUT iu is calculated If multiple pins such as the data bus are dis i abled the measurement value is that of the last pin to stop driving Figure 10 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when they have made Output Disable Time l a transition from a high impedance state to when they start Output pins are considered to be disabled when they have driving T he output enable time tea is the interval from stopped driving and started a transition from the measured when a reference signal reaches a high or low voltage level to output high or low voltage to a high impedance state T he when the output has reached a specified high or low trip point output disable time tps is the difference of tweasuren and as shown in Figure 11 If multiple pins such as the data bus toecay as shown in Figure 11 The time tweasuren is the are enabled the measurement value is that of the first pin to interval from when a reference signal reaches a high or low start driving voltage level to when the output voltages have changed by 0 5 V from the measured output high or low voltage REFERENCE SIGNAL Vou MEASURED Vou MEASURED VoL MEASURED VoL MEASURED OUTPUT STARTS D OUTPUT STOPS RIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 11 O
31. ial ports T he interrupts are internally prioritized and individually maskable except for RESET which is nonmaskable T he IRQx input pins can be programmed for either level or edge sensitivity T he interrupt priorities are shown in T ablel Tablel Interrupt Vector Addresses amp Priority ADSP 2104 AD SP 2109 Interrupt Interrupt Source Vector Address RESET Startup 0x0000 IRQ2 0x0004 H igh Priority SPORT 0 Transmit 0x0008 SPORT 0 Receive 0x000C SPORT 1 Transmit or IRQ1 0x0010 SPORT 1 Receive or IRQO 0x0014 Timer 0x0018 Low Priority TheADSP 2104 AD SP 2109 uses a vectored interrupt scheme when an interrupt is acknowledged the processor shifts program control to the interrupt vector address corresponding to the interrupt received Interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine Each interrupt vector location is four instructions in length so that simple service routines can be coded entirely in this space Longer service routines require an additional JUMP or CALL instruction Individual interrupt requests are logically AN D ed with the bits in the IM ASK register the highest priority unmasked interrupt is then selected REV 0 ADSP 2104 ADSP 2109 T he interrupt control register IC N TL allows the external interrupts to be set as either edge or level sensitive D epending on bit 4 in ICNTL in
32. ion Conventions Ix Index registers for indirect addressing My M odify registers for indirect addressing data Immediate data value addr Immediate address value exp Exponent shift value in shift immediate instructions 8 bit signed number lt ALU gt Any ALU instruction except divide lt MAC gt Any multiply accumulate instruction lt SHIFT gt Any shift instruction except shift immediate cond Condition code for conditional instruction term Termination code for DO UNTIL loop dreg Data register of ALU MAC or Shifter reg Any register including dregs A semicolon terminates the instruction Commas separate multiple operations of a single instruction Optional part of instruction Do Optional multiple operations of an instruction option1 option2 List of options choose one Assembly C ode E xample T he following example is a code fragment that performs the filter tap update for an adaptive filter based on a least mean squared algorithm N otice that the computations in the instructions are written like algebraic equations MF MX0 MY1 RND MXO DM I2 M1 MF error beta MR MX0 MF RND AY0 PM I6 M5 DO adapt UNTIL CE AR MR1 AY0 MX0 DM I2 M1 AY0 PM I6 M7 adapt PM I6 M6 AR MR MX0 MF RND MODIFY I2 M3 MODIFY 16 M7 Point to oldest data Point to start of data REV 0 11 ADSP 2104 ADSP 2109 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
33. k signal T he CLKIN input may not be halted or changed in frequency during Operation nor operated below the specified low frequency limit If an external clock is used it should be a T T L compatible signal running at the instruction rate T he signal should be connected to the processor s CLKIN input in this case the XTAL input must be left unconnected Because the processor includes an on chip oscillator circuit an external crystal may also be used T he crystal should be con nected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 2 A parallel resonant fundamen tal frequency microprocessor grade crystal should be used Tablell ADSP 2104 AD SP 2109 Pin Definitions Pin of Input Name s Pins Output Function Address 14 O Address outputs for program data and boot memory Data 24 1 0 Data I O pins for program and data memories Input only for boot memory with two M SBs used for boot memory addresses U nused data lines may be left floating RESET 1 Processor Reset Input IRQ2 1 l External Interrupt Request 2 BR 1 External Bus Request Input BG 1 O External Bus Grant Output PMS 1 O External Program M emory Select DMS 1 O External D ata M emory Select BMS 1 O Boot M emory Select RD 1 O External M emory Read Enable WR l O External M emory Write Enable MMAP 1 M emory M ap Select Input CLKIN XTAL 2 l External Clock or Quartz C rystal Input CLKOUT 1 O Processor Clock Ou
34. manent damage may occur to devices subjected to such discharges Therefore proper ESD precautions are recommended to avoid Ah performance degradation or loss of functionality U nused devices must be stored in conductive foam or shunts and the foam should be discharged to the destination socket before the devices are removed Per method 3015 of MIL ST D 883 the ADSP 2104 AD SP 2109 processor has been classified as Class 1 device ESD SENSITIVE DEVICE 12 REV 0 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104 ADSP 2109 SUPPLY CURRENT amp POWER Parameter Test Conditions Min Max Unit Ipp Supply Current D ynamic Vpp max tek 50 ns 3l mA 9 Vpp max tex 72 3 ns 24 mA lbo X Supply Current Idle 3 9 Vpp max tek 50 ns 11 mA O Vpp max tck 72 3 ns 10 mA NOTES Current reflects device operating with no output loads Viy 20 4 V and 24 V 3Idle refers to AD SP 2104 AD SP 2109 state of operation during execution of ID LE instruction D easserted pins are driven to either V pp or GND For typical supply current internal power dissipation figures see Figure 7 IDD DYNAMIC 220 200 180 160 f 140 5 9 120 100 80 60 10 00 13 83 20 00 25 00 30 00 FREQUENCY MHz IDD IDLE 2 IDD IDLE n MODES 65 60 60mW IDD IDL 55 1 1 50 tc tc E 45 IDLE 16 o o a a 40 35 0 30 10 00
35. meter Min Max Min Max Unit Timing Reguirement t rs IRQx or FI Setup before CLKOUT Low 33 1 0 25tck 15 ns tre IRQx or FI Hold after CLKOUT High 18 1 0 25tcK ns Switching Characteristic trou FO Hold after CLKOUT High 0 ns trop FO Delay from CLKOUT High 15 ns NOTES TRQx IRQO IRQ and IRQ2 If TRQx and FI inputs meet t rs and typy setup hold requirements they will be recognized during the current clock cycle otherwise they will be recognized during the following cycle Refer to the Interrupt Controller section in Chapter 3 Program Control of the ADSP 2100 Family User s M anual for further information on interrupt servicing 3Edge sensitive interrupts require pulse widths greater than 10 ns Level sensitive interrupts must be held low until serviced CLKOUT J s we FOD trou FLAG OUTPUT S tien IRQx FI trs Figure 26 Interrupts amp Flags REV 0 29 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104L ADSP 2109L BUS REQUEST GRANT Frequency 13 824MHz Dependency Parameter Min Max Min Max Unit Timing Requirement tan BR Hold after CLKOUT High 23 1 0 25tcy 5 ns tps BR Setup before CLKOUT Low 38 1 0 25tck 20 ns Switching Characteristic ts CLKOUT High to DMS PMS BMS RD WR Disable 38 1 0 25tck 20 ns tspB DMS PMS BMS RD WR Disable to BG Low 0 0 ns tsE BG High to DMS PMS BMS RD WR Enable 0 0 ns spe DMS PMS
36. mory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin T he application operates at Vpp 3 3 V and tek 100 ns Total Power Dissipation Pint C xVpp x f Pint internal power dissipation from Figure 13 C x Vpp x f is calculated for each output of Output Pins x C x Vpp x f Address DMS 8 x 10 pF x 3 32 V x 10 MHz 8 71 mW Data WR 9 x 10 pF x 3 3 V x5MHz 4 90 mW RD 1 x10pF x3 32V x5 MHz 0 55 mW CLKOUT 1 x 10 pF x 3 3 V x 10 MHz 1 09 mW 15 25 mW Total power dissipation for this example Pint 15 25 mW ENVIRONMENTAL CONDITIONS Ambient T emperature Rating Tame case PD x Oca T case Case T emperature in C PD Power Dissipation in W Oca T hermal Resistance C ase to A mbient 6 4 Thermal Resistance Junction to A mbient jc Thermal Resistance J unction to C ase Package 6A Oc Oca PLCC 27 C W 16 C W 11 C W 18 CAPACITIVE LOADING Figures 14 and 15 show capacitive loading characteristics a 30 c 1 Ss 25 a Vpp 3 0V gt 20 e w 15 ty 10 a 5 25 50 75 100 125 150 C pF Figure 14 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature 8
37. mp Flags 22 REV O ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 BUS REQUEST GRANT Frequency 20 MHz Dependency Parameter Min Max Min Max Unit Timing Re uirement tay BR Hold after CLKOUT High 17 5 0 25tcx 5 ns tps BR Setup before CLKOUT Low 32 5 0 25tcx 20 ns Switching Characteristic tsp CLKOUT High to DMS 32 5 0 25tcx 20 ns PMS BMS RD WR Disable tsps DMS PMS BMS RD WR 0 0 ns Disable to BG Low tsp BG High to DMS PMS 0 0 ns BMS RD WR Enable tsEc DMS PMS BMS RD WR 2 5 0 25tcy 10 ns Enable to CLKOUT High NOTES If BR meets the tgs and tpy setup hold requirements it will be recognized in the current processor cycle otherwise it is recognized in the following cycle BR requires a pulse width greater than 10 ns Note BG is asserted in the cycle after BR is recognized No external synchronization circuit is needed when BR is generated as an asynchronous signal teH CLKOUT ad BR N CLKOUT PMS DMS ii A WR tse Figure 21 Bus Request Grant REV 0 23 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 MEMORY READ 20 MHz Parameter Min Max Unit Timing Reguirement trpp RD Low to Data Valid 12 ns TAA A0 A13 PMS DMS BMS to Data Valid 19 5 ns trpH Data Hold from RD High 0 Switching Characteristic trp RD Pulse Width 17 ns torp CLKOUT High to RD Low 7 5 22 5 ns TASR A0
38. nc SPECIFICATIONS ADSP 2104L ADSP 2109L 16 Recommended Operating Conditions 16 Electrical Characteristics 0 00 eset eee eee 16 Supply Current amp Power a 17 Power Dissipation Example a 18 Environmental Conditions a 18 Capacitive Loading 0 cece eee eee 18 Test Conditions cece 19 TIMING PARAM ETERS ADSP 2104 ADSP 2109 20 Glock Slan ls s nt Ere Ops e RE RO EUR E eee 21 Interrupts amp Flags ee ee 22 Bus Request Bus Grant a 23 Memory Read 1 1 aaa 24 Memory Write cece 25 S rl l POrts icone wlan K Aa r rus 26 TIMING PARAMETERS ADSP 2104L ADSP 2109L 27 Clock Signals 12 ER RR RR RE mE ERA 28 Interrupts amp Flags 2 0 ec m 29 Bus Reguest Bus Grant a 30 Memory Read ccc ett 31 Memory Write 2 0 aaa 32 Serial PORS mesi Mandate equ wis gans whoa disks Ou 33 PIN CONFIGURATIONS 08 l6ad PEGE uui set eus Cueto te a cod ide AU 34 PACKAGE OUTLINE DIMENSIONS 66 l ead PLCG couette RA NUR anata 35 ORDERING GUID E Guvis k nas t ta siens 36 REV 0 ADSP 2104 ADSP 2109 DATA DATA ADDRESS ADDRESS GENERATOR GENERATOR 1 2 1 714 PMA BUS Zo PMD BUS 16 DMD BUS LL i C PROGRAM MEMORY BOOT ADDRESS GENERATOR TIMER E EL ELA PE K 14 EXTERNAL gt ADDRESS BUS EXTERNAL 1 24 K gt DATA DMD BUS PO A INPUT REGS INPUT REGS INPUT REGS ALU MAC SHIFTER
39. nt Word Lengths Fach SPORT supports serial data word lengths from 3 to 16 bits Companding in Hardware Fach SPORT provides optional A law and p law companding according to CCITT recommen dation G 711 Flexible Interrupt Scheme R eceive and transmit functions can generate a unique interrupt upon completion of a data word transfer Autobuffering with Single C ycle Overhead Each SPORT can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word an interrupt is generated after the transfer of the entire buffer is completed Multichannel Capability SPORTO Only SPORT 0 provides a multichannel interface to selectively receive or transmit a 24 word or 32 word time division multiplexed serial bit stream this feature is especially useful for T1 or CEPT interfaces or as a network communication scheme for multiple processors Alternate C onfiguration SPORT 1 can be alternatively configured as two external interrupt inputs IRQO IRQ1 and the Flag In and Flag Out signals FI FO Interrupts The interrupt controller lets the processor respond to interrupts with a minimum of overhead U p to three external interrupt input pins IRQO IRQI and IRQ2 are provided IRQ2 is always available as a dedicated pin IRO1 and IRQO may be alternately configured as part of Serial Port 1 The ADSP 2104 AD SP 2109 also supports internal interrupts from the timer and ser
40. oded ADSP 2109 you must 1 Complete the following forms contained in theADSP ROM Ordering Package available from your Analog D evices sales representati ve ADSP 2109 ROM Specification Form ROM Release Agreement ROM NRE Agreement amp M inimum Quantity Order M QO Acceptance Agreement for Pre Production ROM Products 2 Return the forms to Analog D evices along with two copies of the Memory Image File EXE file of your ROM code T he files must be supplied on two 3 5 or 5 25 floppy disks for thelBM PC DOS 2 01 or higher 3 Place a purchase order with Analog D evices for nonrecurring engineering changes N RE associated with ROM product development REV 0 After this information is received it is entered into Analog Devices ROM Manager System which assigns a custom ROM model number to the product T his model number will be branded on all prototype and production units manufactured to these specifications T o minimize the risk of code being altered during this process Analog D evices verifies that the EXE files on both floppy disks are identical and recalculates the checksums for the EXE file entered into the ROM M anager System T he checksum data in the form of a ROM Memory M ap a hard copy of the EXE file and a ROM Data Verification form are returned to you for inspection A signed ROM Verification Form and a purchase order for production units are required prior to any product being manufactured P ro
41. ogram sequencer with differentiating features such as on chip program and data memory RAM ADSP 2109 contains 4K words of program ROM a programmable timer and two serial ports Fabricated in a high speed submicron double layer metal CM OS process the ADSP 2104 AD SP 2109 operates at 20 MIPS with a 50 ns instruction cycle time T he AD SP 2104L and ADSP 2109L are 3 3 volt versions which operate at 13 824 M IPS with a 72 3 ns instruction cycle time Every instruction can execute in a single cycle F abrication in CM OS results in low power dissipation REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM T DATA ADDRESS MEMORY GENERATORS MEMORY MEMORY is EE Procrammenonvaooress E E E PROGRAM SEQUENCER EXTERNAL ADDRESS DATA MEMORY ADDRESS Procrammenonvoata T EXTERNAL DATA BUS ARITHMETIC UNITS sar N ADSP 2100 CORE SERIAL PORTS The ADSP 2100 F amily s flexible architecture and compre hensive instruction set support a high degree of parallelism In one cycle the AD SP 2104 AD SP 2109 can perform all o
42. processor Bus Interface The ADSP 2104 AD SP 2109 can relinquish control of their data and address buses to an external device When the external device requires control of the buses it asserts the bus request signal BR If the processor is not performing an external memory access it responds to the active BR input in the next cycle by T hree stating the data and address buses and the PMS DMS BMS RD WR output drivers Asserting the bus grant BG signal and halting program execution If the Go mode is set however the AD SP 2104 AD SP 2109 will not halt program execution until it encounters an instruc tion that requires an external memory access If the processor is performing an external memory access when the external device asserts the BR signal it will not three state the memory interfaces or assert the BG signal until the cycle after the access completes up to eight cycles later depending on the number of wait states T he instruction does not need to be completed when the bus is granted the processor will grant the bus in between two memory accesses if an instruction requires more than one external memory access When the BR signal is released the processor releases the BG signal re enables the output drivers and continues program execution from the point where it stopped T he bus request feature operates at all times including when the processor is booting and when RESET is active If this
43. s slow memories and memory mapped peripherals with programmable wait state generation External devices can gain control of the processor s buses with the use of the bus request grant signals BR BG One bus grant execution mode GO M ode allows the AD SP 2104 AD SP 2109 to continue running from internal memory A second execution mode requires the processor to halt while buses are granted ADSP 2104 ADSP 2109 TheADSP 2104 AD SP 2109 can respond to several different interrupts T here can be up to three external interrupts configured as edge or level sensitive Internal interrupts can be generated by the timer and serial ports T here is also a master RESET signal Booting circuitry provides for loading on chip program memory automatically from byte wide external memory After reset three wait states are automatically generated T his allows for example the AD SP 2104 to use a 150 ns EPROM as external boot memory M ultiple programs can be selected and loaded from the EPROM with no additional hardware T he data receive and transmit pins on SPORT 1 Serial Port 1 can be alternatively configured as a general purpose input flag and output flag Y ou can use these pins for event signalling to and from an external device A programmable interval timer can generate periodic interrupts A 16 bit count register T COUNT is decremented every n cycles where n 1 is a scaling value stored in an 8 bit register TSCALE When the
44. space divided into eight separate 2K by 8 pages T he 8 bit bytes are automatically packed into 24 bit instruction words by the processor for loading into on chip program memory T hree bits in the processors System C ontrol Register select which page is loaded by the boot memory interface Another bit in the System Control Register allows the forcing of a boot loading sequence under software control Boot loading from Page 0 after RESET is initiated automatically if MMAP 0 T he boot memory interface can generate zero to seven wait states it defaults to three wait states after RESET T his allows the AD SP 2104 to boot from a single low cost EPROM such as a27C 256 Program memory is booted one byte at a time and converted to 24 bit program memory words The BMS and RD signals are used to select and to strobe the boot memory interface Only 8 bit data is read over the data bus on pins D 8 D 15 To accommodate up to eight pages of boot memory the two M SBs of the data bus are used in the boot memory interface as the two M SBs of the boot memory address D 23 D22 and A13 supply the boot page number The ADSP 2100 Family Assembler and Linker allow the creation of programs and data structures requiring multiple boot pages during execution The BR signal is recognized during the booting sequence T he bus is granted after loading the current byte is completed BR during booting may be used to implement booting under control of a host
45. t pin to stop driving Output Enable Time Output pins are considered to be enabled when they have made atransition from a high impedance state to when they start driving T he output enable time tena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in Figure 17 If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving Vou MEASURED VoL MEASURED UT STARTS RIVING OUTP D HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Enable Disable Von Figure 18 Eguivalent Device Loading for AC Measurements Except Output Enable Disable REV 0 19 ADSP 2104 ADSP 2109 TIMING PARAMETERS ADSP 2104 ADSP 2109 GENERAL NOTES Use the exact timing information given Do not attempt to derive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases C onsequently you cannot meaningfully add parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals You have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Swit
46. terrupt service routines can either be nested with higher priority interrupts taking precedence or be processed sequentially with only one interrupt service active at atime The interrupt force and clear register IF C is a write only register that contains a force bit and a clear bit for each interrupt When responding to an interrupt the ASTAT MSTAT and IMASK status registers are pushed onto the status stack and the PC counter is loaded with the appropriate vector address T he status stack is seven levels deep to allow interrupt nesting T he stack is automatically popped when a return from the interrupt instruction is executed Pin Definitions T able II shows pin definitions for the AD SP 2104 AD SP 2109 processors Any inputs not used must be tied to Vpp SYSTEM INTERFACE Figure 3 shows a typical system for the AD SP 2104 AD SP 2109 with two serial I O devices a boot EPROM and optional external program and data memory A total of 14 25K words of data memory and 14 5K words of program memory is addressable Programmable wait state generation allows the processors to easily interface to slow external memories The ADSP 2104 AD SP 2109 also provides either one external interrupt IRQ2 and two serial ports SPORT 0 SPORT 1 or three external interrupts IRQ2 IRQ1 IRQO and one serial port SPORT 0 Clock Signals The ADSP 2104 AD SP 2109 s CLKIN input may be driven by a crystal or by a TT L compatible external cloc
47. to AD SP 2104L AD SP 2109L state of operation during execution of IDLE instruction D easserted pins are driven to either V pp or GND For typical supply current internal power dissipation figures see Figure 13 IDLE DYNAMIC 12 a o Ss A oa Qe o oa N o POWER mW M a o 0 a 0 5 00 7 00 10 00 13 83 15 00 FREQUENCY MHz IDD IDLE IDD IDLE n MODES IDD IDLE E 9mW l I ri C IDLE 16 Q Q 5mW amW DLE 128 0 5 00 7 00 10 00 13 83 15 00 5 00 7 00 10 00 13 83 15 00 FREQUENCY MHz FREQUENCY MHz 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2 IDLE REFERS TO ADSP 2104L ADSP 2109L OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3 MAXIMUM POWER DISSIPATION AT Vpp 3 6V DURING EXECUTION OF DLE n INSTRUCTION Figure 13 ADSP 2104L ADSP 2109L Power Typical vs Frequency REV 0 17 ADSP 2104 ADSP 2109 SPECIFICATIONS ADSP 2104L ADSP 2109L POWER DISSIPATION EXAMPLE To determine total power dissipation in a specific application the following eguation should be applied for each output C xVpp x f C load capacitance f output switching frequency Example In an ADSP 2104L application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data me
48. totype units may be applied toward the minimum order quantity U pon completion of prototype manufacture Analog D evices will ship prototype units and a delivery schedule update for production units An invoice against your purchase order for the N RE charges is issued at this time T here is a charge for each ROM mask generated and a mini mum order quantity Consult your sales representative for details A separate order must be placed for parts of a specific package type temperature range and speed grade ADSP 2104 ADSP 2109 Instruction Set The ADSP 2104 AD SP 2109 assembly language uses an algebraic syntax for ease of coding and readability T he sources and destinations of computations and data movements are written explicitly in each assembly statement eliminating cryptic assembler mnemonics Every instruction assembles into a single 24 bit word and executes in a single cycle T he instructions encompass a wide variety of instruction types along with a high degree of ALU Instructions IF cond AR AF xop yop C xop yop C 1 yop xop C 1 xopAND yop AND xopOR yop OR xop XOR yop XOR PASS xop Pass Clear Xx0p N egate NOT xop NOT ABSxop Absolute V alue VYOp 1 Increment yop 1 Decrement DIVS yop xop Divide DIVQ xop MAC Instructions IF cond MR MF xop x yop M ultiply operational parallelism T here are five basic categories of instructions data move instructions
49. tput Vpp Power Supply Pins GND Ground Pins SPORTO 5 1 0 Serial Port 0 Pins TFS0 RFSO DTO DRO SCLK0 SPORT 1 5 1 0 Serial Port 1 Pins TFS1 RFS1 DT1 DR1 SCLK1 or Interrupts amp Flags IRQO RFS1 1 External Interrupt Request 0 IRQ TFS1 1 l External Interrupt Request 1 FI DR1 l Flag Input Pin FO DT1 l O Flag Output Pin NOTES 1U nused data bus lines may be left floating BR must be tied high to Vpp if not used REV 0 ADSP 2104 ADSP 2109 XTAL CLKIN CLKOUT ADSP 2104 ADSP 2109 Figure 2 External Crystal Connections A clock output signal CLK OUT is generated by the processor synchronized to the processor s internal cycles Reset The RESET signal initiates a complete reset of the processor The RESET signal must be asserted when the chip is powered up to assure proper initialization If the RESET signal is applied during initial power up it must be held long enough to allow the processor s internal clock to stabilize If RESET is activated at any time after power up and the input clock frequency does not change the processor s internal clock continues and does not require this stabilization time T he power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is applied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 tcx cycles will ensure that th
50. utput Enable Disable loL TO i 1 5V Figure 12 Eguivalent Device Loading for AC Measurements Except Output Enable Disable REV 0 15 ADSP 2104L ADSP 2109L SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter Min Max Unit Vpp Supply Voltage 3 00 3 60 V Tams Ambient O perating T emperature 0 70 C See Environmental Conditions for information on thermal specifications ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min Max Unit Vin Hi Level Input Voltage 9 Vpp max 2 0 V Vu Lo L evel Input Voltage Vpp 2 min 0 4 V Vou Hi Level Output Voltage gt 6 Vpp min loy 0 5 mA 2 4 V VoL Lo L evel Output Voltage 6 9 Vpp 2 min lo 2 mA 0 4 V liu Hi Level Input Current O Vpp max Vin Vpp max 10 uA lu Lo L evel Input Current O Vpp max Vin OV 10 uA lozu T hree State L eakage C urrent 9 Vpp max Vin Vpp max 10 uA loz T hree State L eakage C urrent Vpp max Viy 0 V 10 uA C Input Pin C apacitancel 8 9 Vin 22 5 V fiy 2 1 0M Hz T amp 25 C 8 pF Co Output Pin Capacitance 7 8 9 Vin 22 5 V fy 2 1 0M Hz T amg 25 C 8 pF NOTES ua Input only pins CLKIN RESET IRQ2 BR MMAP DRI DRO 2 Output pins BG PMS DMS BMS RD WR A0 A13 CLKOUT DT1 DTO 3 Bidirectional pins DO D23 SCLK1 RFS1 TFS1 SCLKO RFS0 TFS0 Three stateable pins A0 A13 D0 D23 PMS DMS BMS RD WR DT1 SCLK1 RSF1 TFS1 DTO SCLK0 R
51. x3FFF MMAP 1 No Booting Ox3FFF Figure 4 ADSP 2104 Program Memory Maps 0x0000 2K EXTERNAL 0x07FF 0x0800 2K INTERNAL ROM OxOFFO RESERVED OxOFFF 0x1000 0x0000 4K INTERNAL ROM OxOFFO RESERVED OxOFFF 0x1000 12K EXTERNAL Ox37FF 0x3800 10K EXTERNAL K 2 INTERNAL ROM 0x3FFF Ox3FFF MMAP 0 MMAP 1 Figure 5 ADSP 2109 Program Memory Maps ADSP 2104 When M MAP 0 on chip program memory RAM occupies 512 words beginning at address 0x0000 Off chip program memory uses the remaining 14K words beginning at address 0x0800 In this configuration when M M AP 0 the boot loading sequence described below in Boot M emory Inter face is automatically initiated when RESET is released When M MAP 1 14K words of off chip program memory begin at address 0x0000 and on chip program memory RAM is located in the 512 words between addresses 0x3800 0x39F F In this configuration program memory is not booted although it can be written to and read under program control REV 0 Data Memory Interface The data memory address bus D M A is 14 bits wide T he bidirectional external data bus is 24 bits wide with the upper 16 bits used for data memory data D M D transfers T he data memory select DMS signal indicates access to data memory and can be used as a chip select signal T he write WR signal indicates a write operation and can be used as a write strobe T he read RD signal indic
52. ystem development The ADSP 2100 Family Development Software includes C and assembly language tools that allow programmers to write code for any AD SP 21xx processor The ANSI C compiler generates AD SP 21xx assembly source code while the runtime C library provides AN SI standard and custom DSP library routines The AD SP 21xx assembler produces object code modules which the linker combines into an executable file T he processor simulators provide an interactive instruction level simulation with a reconfigurable TABLE OF CONTENTS GENERAL DESCRIPTION 000 c eee eee 1 Development Tools a 2 Additional Information 00 cee eee eae 2 ARCHITECTURE OVERVIEW 0005 3 Serial POMS is sce eee gp PU get Nar PUR es 4 Interr pts e sts e t te 4 Pin Definitions s dist chee eee eRE eR EP eh eye os ER 5 SYSTEM INTERFACE 0 0 cc cece eee 5 CIOCK Signals nemora ee aig ane e es tod 5 ROCCE 2n eost Akita kus Se AE Mle Ms 6 Program Memory Interface 0 0 0 a 6 Program Memory Maps ccc eee eee eee ee 7 Data Memory Interface aa 7 Data Memory Map aaa 7 Boot Memory Interface a 8 Bus Interface iss usa e Ee Sate Rela SERE 8 Low Power IDLE Instruction 0 0 000s 8 ADSP 2109 Prototyping 0 cece eee eee 9 Ordering Procedure for ADSP 2109 ROM Processors 9 lnistr ction Set io se ar cue ae er aee Hebe tnc 10 SPECIFICATIONS ADSP 2104 AD SP 2109 12 R
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