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TSC695F 32-bit Sparc Processor

1. Type Name Definition Reg n 07 global reg 7 r7 06 global reg 6 r6 g5 global reg 5 r5 g4 global reg 4 r4 global g3 global reg 3 r3 g2 global reg 2 r2 gi global reg 1 ri g0 0 0000 0000 ro For each window register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 413121110 r w X 0x 0000 0000 for 00 Figure 4 1 Overlapping Windows _ 4 56 AIMEL TSC695F User Manual 4148H AERO 12 03 4 7 FPU Registers Table 4 7 FPU Status Register FSR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 1716 5 43121110 tem Ss 6 o8 rd 5S ns 5 ver ftt c fcc DU AE s ssgsgsz esgs gs 65 clo 5 5 ec 5 o c r w r r w r r r r w rir r w r w r w x 00 x 0 00 100 X 0 X TSC695F User Manual E rd Rounding Direction rd field defines the rounding direction used by the TSC695F FPU during a floating point arithmetic operation 0 round to nearest tie even 1 roun zer ound to zero 255 Value lt 0 0 Value gt 0 2 round to infinity i 8 round to infinity roundto found to 475 roundio 09 round to oo B Trap Enable Mask tem fi
2. x Write only with any data A write to this register will cause the system to issue the RESET signal if the software reset function is enabled in the System Control regis ter swr bit f the software reset function is not enabled a write to this register will have no effect Table 4 12 Power down PDOWN address 0x 01f8 0008 Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1 TSC695F User Manual AIMEL 4 63 4148 12 03 Table 4 12 Power down PDOWN Continued address 0x 01f8 0008 Supervisor Write 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 15 14 13 12 11 10 4 3 2 1 0 Ww X Write only with any data A write to this register will cause the system to enter power down mode if the power down function is enabled in the System Control Register prd bit f the power down function is not enabled a write to this register will have no effect Table 4 13 System Fault Status Register SYSFSR
3. 3 50 3 12 5 3 50 Section 4 Register SSC UG WINS oases tines qa dira nena 4 51 42 ROGE OIS 4 51 4 2 Processor State 4 51 4 3 Window Invalid 02200 0 4 53 4 4 Trap Base 4 54 45 Y Registe 4 54 4 6 Window 4 55 44 PPU RGGBIOS AEE 4 57 4 8 FPU Queue Hegisters teret ceti Deere e eti Da te tie 4 59 4 9 tet ER mibi eee 4 60 4 10 System Registers ende 4 60 4 10 1 System Management Registers 4 60 4 11 Configuration Registers 4 69 iii AIMEL TSC695F User Manual 4148H AERO 12 03 TSC695F User Manual Table of Contents 4 12 Access Protection Registers 2 20 22222 24 4 77 4 13 Interrupt 40 4 79 4 14 Timer Beglsters ee oii eni erectae s Ese SEED 4 89 4 15 Interface
4. address 0x 01f8 00a0 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 S 9 gt 18 gt Ss reserved 0000 0000 0000 0000 at S 2 srft 58 g 9 r r w rw uU r r w y r Ww Ww 0000 0000 0000 0000 0000 0 000 0 1111 00 The register is reset by writing any value to it The SYSFSR reset value is 0x00000078 B at Access Type Accesses in the Extented General area are treated as RAM accesses from an access type point of view At Access Type Access Mode ASI 3 0 0000 Load User data RAM ROM System Registers Oxa 1010 0001 Supervisor data RAM ROM System Load Registers Oxb 1011 0010 Not used 0011 Not used 0100 Load DMA RAM ROM System Registers Do not care 0101 Oxa 1010 Load Execute User l O Exchange 0x8 1000 0110 Oxb 1011 Load Execute Supervisor 0 9 1001 0111 Load DMA Do not care 1000 Store User data RAM ROM System Registers Oxa 1010 1001 Supervisor data RAM ROM System Store Registers Oxb 1011 4 64 AIMEL TSC695F User Manual 4148H AERO 12 03 At Access Type Access Mode ASI 3 0 1010 Not used 1011 Not used 1100 Store DMA RAM ROM System Registers Do not care 1101 1010 Store User 0x8 1000 1110 Oxb 1011
5. Memory Accessed Parity a Memory Area Enabled Q Read or Fetch Access Write Access TSC695F ignores DPAR TSC695F generates DPAR 1 5 EDAC generates data parity 5 U FPU generates data parity 2 IU FPU checks data parity 2 EDAC checks data parity PROM 8 bit N Ext PROM TSC695F ignores DPAR TSC695F generates DPAR o w EDAC ignores data parity E IU FPU generates data parity 9 IU FPU ignores data parity but generates 9 EDAC ignores data parity amp its own parity for its internal usage TSC695F samples DPAR TSC695F generates DPAR 1 EDAC checks data parity g IU FPU generates data parity 2 IU FPU checks data parity 2 EDAC checks data parity PROM 40 bit Ext PROM TSC695F samples DPAR TSC695F generates DPAR EDAC checks parity E IU FPU generates data parity D IU FPU ignores data parity but generates EDAC ignores data parity its own parity for its internal usage no TSC695F ignores DPAR TSC695F generates DPAR og 1 E EDAC generates data parity E IU FPU generates data parity E amp IU FPU checks data parity amp EDAC checks data parity pa 0 RAM yes TSC695F samples DPAR TSC695F generates DPAR Ext RAM Toa 1 1 S EDAC checks data parity 8 IU FPU generates data parity cera 8 IU FPU checks data parity 8 EDAC checks data parity Exchange En Memory no TSC695F ignores DPAR T
6. 4 93 Section 5 Signals Description assis 5 98 5 1 IW and FPU enne 5 98 5 2 Memory and System Interface 5 104 5 3 Error DMA Halt and Check 5 105 5 4 Interrupt Clock UART GPI Timer TAP and Test Signals 5 108 5 5 5 110 5 6 Document 5 110 AMEL iv 4148 12 03 AIMEL TSC695F User Manual Section 1 Features B Integer Unit Based on SPARC V7 High Performance RISC Architecture E Optimized and Integrated 32 64 bit Floating point Unit On chip Peripherals EDAC and Parity Generator and Checker Memory Interface Chip Select Generator Waitstate Generation Memory Protection W DMA Arbiter B Timers General purpose Timer GPT Real time Clock Timer RTCT Watchdog Timer WDT B Interrupt Controller with 5 External Inputs B General purpose Interface GPI Dual UART B Speed Optimized Code RAM Interface 8 or 40 bit Boot pROM Flash Interface B IEEE 1149 1 Test Access Port TAP for Debugging and Test Purposes B Fully Static Design B Performance 20 MIPs 5 MFlops Double Precision at SYSCLK 25 MHz 5V B Core Consumption 1 5W Typ at 25 MIPs 0 7W typ at 10 MIPs Vcc 5V
7. 3 13 xn Ecc 3 14 3 6 5 Memory and I O 888 3 15 366 WOM c DC 3 18 2 6 7 WRAPS vineas ta tte a Neu e er ree 3 19 368 TIMOS E 3 31 9 69 WARTS etter Ex e duce 3 36 3 6 10 General purpose 3 37 3 6 11 Execution Modes eei iei neue 3 38 3 5 12 Eror Aner ct e dgio ee dco 3 39 3 6 13 Panty Checking Eden kun 3 40 3 6 14 System 252 lt e RR 3 40 3 6 15 System oce ete etri epic cte Ee nie 3 40 3616 Test 2 ei nr e Rn tL ee Hep asa 3 40 3 7 Test and Diagnostic Hardware 3 41 3 89 Test ACCOSS ie eto er ute gute Ee 3 41 TSC695F User Manual ii 4148H AERO 12 03 Table of Contents 3 841 TAP InterfaGo dvd erin ese eee Sn e 3 41 3 8 2 Board Level Architecture 4 0 4 00 3 41 3 8 3 TAP ArchiteCtUlre at onere ER 3 42 3 9 TAP Controller ccs E 3 42 391 TAP Controler FSM ectetur
8. reserved 000 0000 0000 0000 0000 pol ack edge r rw r w r w 000 0000 0000 0000 0000 0 0000 000 0 0000 B pol External interrupts Polarity TSC695F User Manual AIMEL 4 79 4148 12 03 edge field defines the external interrupts EXINT 7 0 to be either active low or high when level triggered mode is programmed or to be either active on falling edge or rising edge when edge triggered mode is programmed Function pol level triggered mode edge triggered mode x 0 low level falling edge high level rising edge X XX0X low level level triggered xxxix EXTINT 1 high level edge triggered X XOxx low level falling edge EXTINT 2 high level rising edge low level level triggered 1 EXTINT 3 high level edge triggered 0 low level falling edge 1 EXTINT 4 high level rising edge B ack Acknowledge on external interrupt ack field routes the IU interrupt acknowledge of the chosen external interrupt on the EXTINTACK pin ack Function ack Function 000 no action 100 EXTINT 3 acknowledged 001 EXTINT 0 acknowledged 101 EXTINT 4 acknowledged 010 EXTINT 1 acknowledged 110 no action 011 EXTINT 2 acknowledged 111 no action B edge External interrupts EDGE or level triggered edge field
9. 0000 lo 2 SYSCLK periods AIMEL TSC695F User Manual prr Waitstate Read Cycle 0001 1 2 SYSCLK periods XXXX n 1 n SYSCLK periods 1111 15 16 SYSCLK periods Note If PROM8 PROM8 is deasserted PROM Boot 40 bit always a load access byte half word or word or a fetch to PROM Boot will be performed in 1 word fetch W raw RAM nbr of Write Waitstates raw field fixes the number of waitstates in RAM space raw Waitstate Write Cycle 00 0 2 SYSCLK periods 01 1 3 SYSCLK periods 11 2 4 SYSCLK periods 11 3 5 SYSCLK periods Notes 1 Always a byte or half word store access to RAM will be performed in 1 word fetch byte or half word modification into TSC695F 1 word store 2 Raw must be greater or equal than rar W rar RAM nbr of Read Waitstates raw field fixes the number of waitstates in RAM space rar Waitstate Read Cycle 00 0 1 SYSCLK periods 01 1 2 SYSCLK periods 11 2 3 SYSCLK periods 11 3 4 SYSCLK periods Notes 1 Always a load access byte half word or word or a fetch to RAM will be performed in 1 word access 2 Raw must be greater or equal than rar 4 12 Access Protection Registers Table 4 20 Access Protection Segment 1 Base Register APS1BR address 0x 01f8 0020 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
10. The system registers are only writable by IU in the supervisor mode or by DMA during halt mode All the readable registers except UARTAR and UARTBR can be accessed in every access mode UARTAR and UARTBR are only readable by IU in supervisor mode or by DMA during halt mode Byte or half word store access is not allowed A wrong access type will generate a Memory Exception MEXC Only byte half word load access and word access are granted Read Write Access System Control Register SYSCTR Ox 01F8 0000 All R Supervisor W Software Reset SWRST Ox 01F8 0004 Supervisor W Power down PDOWN Ox 01F8 0008 Supervisor W System Fault Status Register SYSFSR 01F8 00A0 All R Supervisor W Failing Address Register FAILAR Ox 01F8 00A4 AllR Error and Reset Status Register ERRRSR Ox 01 8 00 0 All R Supervisor W Test Control Register TESCTR Ox 01F8 00D0 All R Supervisor W Memory Configuration Register MCNFR Ox 01F8 0010 All R Supervisor W Configuration Register IOCNFR Ox 01F8 0014 All R Supervisor W Waitstate Configuration Register WSCNFR Ox 01F8 0018 All R Supervisor W Access Protection Segment 1 Base Register APS1BR Ox 01F8 0020 All R Supervisor W Access Protection Segment 1 End Register APS1ER Ox 01F8 0024 All R Supervisor W Access Protection Segment 2 Base Register APS2BR 0x 01F8 0028 All R Supervisor W Access Protection Segment 2 End Registe
11. Store Supervisor Ox9 1001 1111 Store DMA Do not care B asft Asynchronous Fault Type asft field gives information about some asynchronous faults This information can be extracted by software from Interrupt Pending Register as well ASFT Fault Type 00 Watchdog timeout FAILAR not updated 01 DMA timeout FAILAR not updated or access error FAILAR updated 10 UART error FAILAR not updated 11 memory correctable error FAILAR updated asfv Asynchronous Fault Valid asfv bit indicates that the asft field is valid an asynchronous fault has occurred 0 not valid 1 valid This bit must be reset by software during trap handling to enable further SYSFSR and FAILAR updates on asynchronous fault detection srft Synchronous Fault Type srft field gives information about some synchronous faults srft Fault Type srft Fault Type 0000 parity error on control bus 1000 bus timeout 0001 parity error on data bus 1001 bus error 0010 parity error on address bus 1010 not used 0011 access to protected area 1011 not used 0100 access to unimplemented area 1100 not used 0101 system registers parity error 1101 not used 0110 system registers access violation 1110 not used TSC695F User Manual AIMEL 4 65 4148 12 03 srft
12. 0 halt action in case of system hardware error 1 reset action in case of system hardware error B syshemsk System Hardware Error Mask syshemsk bit masks the internal information which is asserted when the system detects an hardware error 0 error not masked default 1 error masked disabled E rhiuhe Reset or Halt when IU Hardware Error rhiuhe bit enables a reset or an halt action when the IU detects an error enabled by iuhemsk bit 0 halt action in case of IU hardware error 1 reset action in case of IU hardware error E juhemsk IU Hardware Error Mask iuhemsk bit masks the internal information which is asserted when the IU detects an hardware error 0 error not masked default 1 error masked disabled E rhiuem Reset or Halt when IU Error Mode rhiuem bit enables a reset or an halt action when the IU enters the error mode state enabled by iuemmsk bit 0 halt action in case of IU error mode 1 reset action in case of IU error mode E juemmsk U Error Mode Mask iuemmsk bit masks the internal information which is asserted when the IU enters the error mode state 0 error not masked default 1 error masked disabled B wdcs Watchdog Clock Supply wdcs bit adds a 4 bit prescaler in front of the input clock for the internal watchdog timer 4 62 AIMEL TSC
13. ie 3 42 3 10 The Instruction 3 43 3 10 1 Listof 3 43 3 10 2 Mandatory 3 43 3 10 3 Defined Optional 2 3 44 3 10 4 Owner nennen 3 44 3 11 Test Data Registers essences eie 3 45 3 11 1 Bypass Register iiie e eee tut d 3 45 3 11 2 Device ID 44400 611 3 45 3 11 3 Boundary Scan 3 45 3 11 4 Checkers Scan 4 3 45 3 11 5 IU Scan Register 3 45 3 11 6 FPU Scam amp 3 46 3 11 7 System Scan 1 8 3 46 3 11 8 OCD Scan Register Dern 3 47 3 11 9 OCD Control and Status 3 47 3 12 On chip Debugger Resources 3 48 3 12 1 Hardware 3 48 3 12 2 Processor 3 49 3 12 3 Cycle COUNE oec 3 49 3 12 4
14. Interrupt Force on asynchronous INT 1 if 1 bit forces the interrupt on masked hardware errors in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced Table 4 29 Watchdog Timer Register WDOGTR address 0x 01f8 0060 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111 10 9 8 7 6 5 43121 wdr wds wdc rw rw rw 1111 1111 1111 1111 1111 1111 1111 1111 TSC695F User Manual B wdr WatchDog Reset Counter war field fixes the ResetTimeout The ResetTimeout is the time between the loading or re loading and the watchdog reset wds 1 wdr 1 WDCLK Note wdcs bit and WDCLK of the formula are respectively the enable bit of the watchdog 4 bit pre scaler i e SYSCTR and the WDCLK input signal Reading war field gives the loading or re loading value not the effective count value ResetTimeout Timeout 16 E wds WatchDog Scaler wads field fixes the scaler for ResetTimeout and Timeout counting Reading wds field gives the loading or re loading value not the effective count value B wdc WatchDog Counter wdc field fixes the Timeout The Timeout is the time between the loading or re loading and the watchdog in
15. Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 RF Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Biometrics Imaging Hi Rel High Speed Converters RF Datacom Avenue de Rochepleine BP 123 38521 Saint Egreve Cedex France Tel 33 4 76 58 30 00 Fax 33 4 76 58 34 80 Literature Requests www atmel com literature Disclaimer Atmel Corporation makes no warranty for the use of its products other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site The Company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products expressly or by implication Atmel s products are not authorized for use as critical components in life support devices or systems Atmel Corporation 2003 All rights reserved Atmel and combinations thereof are the t
16. and bits of the I O Configu ration Register B INULL Integer Unit Nullify Cycle output The processor asserts INULL to indicate that the current memory access is being nulli fied It is asserted at the beginning of the cycle in which the address being nullified is active INULL is used to disable memory exception generation for the current memory access This means that MDS MDS MEXC MEXC is not be asserted for a memory access in which INULL 1 INULL is asserted under the following conditions 1 During the second data cycle of any store instruction including Atomic Load Store to nullify the second occurrence of the store address 2 On all traps to nullify the third instruction fetch after the trapped instruction For reset it nullifies the error producing address 3 load in which the hardware interlock is activated 4 on JMPL and RETT instructions B INST Instruction Fetch output The INST signal is asserted by the IU whenever a new instruction is being fetched It is used by the FPU to latch the instruction currently on the internal data bus into an FPU instruction buffer The FPU have two instruction buffers D1 and D2 to save the last two fetched instructions When INST is asserted a new instruction enters buffer D1 and the instruction that was in D1 moves to buffer D2 AMEL 4148 12 03 5 4 Interrupt Clock UART GPI Timer TAP and Test Signals 5 108 414
17. 12 11 10 9 8 7 6 4 312 0 reserved 0000 0000 0000 0000 0000 rtcsl rtce rtccl rtcr reserved 0 bhit phit gptsl gpte gptcl gptr r r w 0000 0000 0000 0000 0000 4 92 4148H AERO 12 03 E rics Real time Clock Scaler Load ricsi bit loads the RTC scaler with the preset value and the RTC scaler starts if itis enabled 0 no function 1 load scaler E rice Real time Clock Enabled bit enables the counting for the RTC 0 hold scaler and counter 1 enable counting E riccl Real time Clock Counter Load bit loads the RTC counter with the preset value and the RTC counter starts if it is enabled 0 no function 1 load scaler E rtcr Real time Clock Reload rtcr bit enables the reload mode or one shot mode for the RTC 0 one shot mode 1 reload mode E bhit UART bhit bit gives the possibility to disable the UART B clock for software debugging This effect of this bit is enabled by the DEBUG pin 0 UART B not halted default 1 UART not halted E ahlt UART A ahlt bit gives the possibility to disable the UART A clock for software debugging This effect of this bit is enabled by the DEBUG pin 0 UART A not
18. Check Bits bi directional CB 6 0 is the EDAC checkword over the 33 bit data bus consisting of D 31 0 and the parity bit DPAR When the TSC695F performs a write operation to the main memory it will assert the EDAC checkword on the CB 6 0 During read access from the main memory CB 6 0 are input signals and will be used for checking and correction of the data word and the parity bit During read access to areas which do not generate a parity bit the TSC695F will latch the data from the accessed address and drive the correct parity bit to IU or FPU not observable D 31 0 indicates bit of D 31 0 used in parity calculation Bt Party sS 3 e 8 S e e e e DPAR nxor 1 1 1 1 1 11 6 mm CB 5 XOR mm a a a 4 N XOR mm x 3 x 41 11 CB 2 N XOR 1 XOR m ete x CB 0 XOR ls alela ele ls x mm TSC695F User Manual B RLDSTO Registered Atomic Load Store output input This signal is used to identify an atomic load store LDSTUB instruction only to the sys tem and is asserted by the IU during all t
19. Signal Type Active Description GPI 7 0 Vo GPI input output Input trigger GPIINT High GPI interrupt EXTINT 4 0 External interrupt Input trigger 0 High External interrupt acknowledge IWDE High Internal Watchdog enable EWDINT High External Watchdog input interrupt Input trigger WDCLK Watchdog clock CLK2 Double frequency clock SYSCLK System clock RESET Low Output reset SYSRESET Low System input reset Input trigger TMODE 1 0 1 Factory test mode Functional mode 00 DEBUG High Software debug mode TCK Test JTAG clock TRST Low Test JTAG reset pull up 37 TMS Test JTAG mode select pull up 37 kQ TDI Test JTAG data input pull up 37 kQ TDO Test JTAG data output VCCI VSSI Main internal power VCCO VSSO Output driver power Note If not specified the output buffer type is 150 pF the input buffer type is TTL AMEL TSC695F User Manual The TSC695F is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on board computer All other system support functions are provided by the core 1 4 System Architecture Figure 1 2 TSC695F 32 bit System Architecture DMAA NII Boot PROM T Es DMAREQ BUFFEN DDIR n Xtd General a MEMCtrl Memory Interface rato fd RAMCtrl User Application TSC695F AMEL TSC695F User Manual 4148H AERO
20. 0 Block mode bp 1 Two segments are implemented Each segment is defined by a Segment Base defined in APS1BR or APS2BR registers and a Segment End defined in APS1ER or APS2ER registers The segment access protection can be used as a block protect function by setting the bp bit in the System Control Register The bp bit inverts the address criterion for the protection function so that any access within the segment is detected The TSC695F can also be programmed to detect and mask write accesses in supervisor or and user mode in any part of the RAM The protection scheme is enabled only for data area not for the instruction area The programmable write access protection is segment based B Boot PROM Write Protection The TSC695F supports PROM write only when it is qualified by the external enable pin ROMWRT ROMWRT and the enable bit in the Memory Configuration Register The TSC695F only supports byte write operations for an 8 bit wide PROM and only word write operations for a 40 bit wide PROM If a write access to PROM is attempted when any of the above conditions are not fulfilled the System Fault Status Register and the Failing Address Register is updated as for unimplemented area access Segment 1 RAM and Extended RAM areas RAM and Extended RAM areas 3 6 6 DMA 3 6 6 1 DMA Interface B The TSC695F supports Direct Memory Access DMA The DMA unit requests access to the processor bus by asserting the DMA request signal D
21. Action H H Nothing not ready AMEL 4148 12 03 Figure 5 2 DMAS Timing SYSCLK RA 31 0 asynchronous DMAAS synchronised DMAAS to TSC695F input 5 106 4148H AERO 12 03 Table 5 4 Bus Transaction Response Signals BUSERR BUSRDY Action H L Data Strobe ready L H Nothing not ready L ls System Bus Error E DMAREQ DMAREQ DMA Request input DMAREQ DMAREQ is to be issued by a unit requesting the access to the processor bus as a master The TSC695F can include a DMA session timeout function preventing the DMA unit to lockout the IU FPU by asserting DMA request for a long time B DMAGNT DMA Grant output DMAGNT DMAGNT is generated by the TSC695F as a response to a DMAREQ DMAREQ DMAGNT DMAGNT is sent after that the TSC695F has asserted a Bus Hold A memory cycle started by the processor is not interrupted by a DMA access before it is finished The DMA unit have access to all system registers and all integrated peripherals of the TSC695F It also has access to the memory controlled by the memory access controller of the TSC695F B DMAAS DMA Address Strobe input During DMA transfers when the external DMA is bus master this input is used to inform the TSC695F that the address from the DMA is valid and that the access cycle shall start DMAAS can be asserted multiple times during DMA grant DMAAS must be
22. By writing to the Trap Door Set WDOGST after system reset the timer can be disabled After a write operation to the Watchdog Timer Register WDOGTR starts the timer counting with the value of the Watchdog Timer Register Note that the Watchdog cannot be disabled once the Watchdog Timer Register WDOGTR has been written If the timer is refreshed by writing to Watchdog Timer Register WDOGTR before the counter reaches zero value the timer restarts the counting with the new delay value If the timer is not refreshed reprogrammed before the counter reaches zero value an interrupt is sent Simultaneously the timer starts counting a reset timeout period with the programmed delay time Then if the timer is acknowledged by writing to Watchdog Timer Register WDOGTR with a new programmed value before the reset timeout period elapses again the timer restarts counting with the new delay value but if the timer is not acknowledged before the reset timeout period elapses a reset is applied This updates the rstc field in the Error and Reset Status Register ERRRSR B Programming wdcs scaler 1 x counter 1 Timeout 16 WDCLK wdes scaler 1 x resetcounter 1 WDCLK Two full duplex asynchronous receiver transmitters UART are included ResetTimeout Timeout 16 In software debug mode the UARTs are controlled by Timer Control Register bits phit ahlt and bhlt respectively bit 4 5 6 in TIMCTR and an external pin
23. MEXC signal is asserted during an instruction fetch E Illegal instruction An illegal instruction trap occurs When the UNIMP instruction is encountered When an unimplemented instruction is encountered excluding FPops and CPops any of the situations below where the continued execution of an instruction would result in an illegal processor state 1 Writing a value to the psr s cwp field that is greater than the number of implemented windows with WRPSR assembly instruction 2 Executing an Alternate Space instruction with its i bit set to 1 3 Executing a RETT instruction with traps enabled et 1 4 Executing an IFLUSH instruction Unimplemented floating point instructions do not generate an illegal instruction trap They generate FPU exception Floating point instructions are coded with op 10 and op3 11010x E Privileged instruction This trap occurs when a privileged instruction is encountered while the PSR s supervisor bit is reset s 0 E FPU disabled A FPU disabled trap is generated when an FPop FBfcc or floating point load store instruction is encountered while the PSR s efbit 0 B Coprocessor disabled A coprocessor disabled trap is generated when a CPop CBccc or coprocessor load store instruction is encountered Window overflow This trap occurs when the continued execution of a SAVE instruction would cause the cwp to point to a window marked invalid in the WIM register E
24. RxA and RxB Note that no hardware handshake signals such as CTS or RTS are implemented Any handshaking must be implemented in software e g using XON XOFF General purpose Interface GPI is an 8 bit parallel I O port Each pin can be config ured as an input or an output thanks to the GPI Configuration Register GPICNFR When pin is an input its state is read from GPI Data Register GPIDATR When a pin is an output its state corresponds to the bit value written in GP Data Register GPI DATR this value can be re read in GPI Data Register GPIDATR An edge detection is made on selected GPI inputs Falling or rising edge is chosen in GPI Configuration Register GPICNFR Every input transition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width Figure 3 12 General purpose Interface of GPI Configuration Register GPICNFR eei gt R F i of GPI Configuration Register GPICNFR Glitch Removal GPID i of GPI Data Register GPIDATR l O i of GPI Configuration Register GPICNFR Write to GPI Data Register GPIDATR 3 6 11 Execution Modes 3 6 11 1 Reset Mode 3 6 11 2 Run Mode 3 32 4148H AERO 12 03 After Reset all GPI I O are configured as inputs When the SYSRES input is asserted the TSC695F issues a reset of itself and asserts the RESET output which is intended to be used as a reset signal to all other compo nents in the syste
25. fpuhe bit indicates hardware error on FPU fpuhe bit is only writable when ewe bit in the Test Control Register TESCTR is set 0 no error 1 internal parity error E juhe IU Hardware Error TSC695F User Manual AIMEL 4 67 4148H AERO 12 03 iuhe bit indicates hardware error on IU iuhe bit is only writable when ewe bit in the Test Control Register TESCTR is set 0 no error 1 internal parity error B juem lU Error Mode bit indicates that the IU is in error mode iuem bit is only writable when ewe bit in the Test Control Register TESCTR is set 0 no error 1 error Table 4 16 Test Control Register TESCTR address 0x 01f8 00d0 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 43121 0 reserved 000 0000 0000 a o reserved 00 0000 0000 cb ru ru m r w iw iw Jr r w 000 0000 0000 00 0000 0000 000 0000 4 68 4148H AERO 12 03 W Error Write Enable By enabling ewe bit an error could be simulated by writing syshe fouhe iuhe or and iuem bits in the Error and Reset Status Register ERRRSR 0 writing disable 1 writing enable E jt Interrupt Force Enable it bit enables the using of the Interrupt Force Re
26. received with a parity error only the peb bit is set not the drb bit The peb bit is cleared by the cub bit 0 no error 1 parity error on the receiver of UART B E feb Frame Error on receiver AMEL 4 95 4148H AERO 12 03 feb bit advises a frame error on the receiver of UART B When a byte is received with a frame error only the feb bit is set not the drb bit The feb bit is cleared by the cub bit 0 no error 1 frame error on the receiver of UART B E theb Transmitter Holding Register Empty on UART B theb bit indicates the transmitter holding register of the UART B is empty It is ready to be reloaded with a new data 0 full 1 empty default E seb Transmitter Send Register Empty on UART B tseb bit indicates the transmitter send register of the UART B is empty It has no data to send 0 full 1 empty default E drb Data Ready in UART B drb bit indicates a data has been received by the receiver of the UART B 0 empty default 1 full B cua Clear Errors on UART A cua bit clears the setting errors on the UART It is an auto resetable bit bit read as zero 0 n0 action 1 clear errors on UART A E Overrun Error on receiver bit advises an overrun error on the receiver of UART When a byte is received while the re
27. se2 bit enables the write protection in user mode on the segment 2 defined by seg2base and seg2end 0 write access protection disabled in user mode 1 write access protection enabled in user mode B seg2base Segment 2 BASE Address seg2base field defines the base address for the segment 2 The Segment 2 Base Address is calculated according the formula Segment 2 Base Address 0x02000000 seg2base 4 Table 4 23 Access Protection Segment 2 End Register APS2ER address 0x 0118 002c Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1 reserved 0 0000 0000 segend r r w 0 0000 0000 000 0000 0000 0000 0000 0000 B seg2end Segment 2 END Address seg2end field denotes the first address outside the segment 2 The Segment 2 End Address is calculated according the formula Segment 2 End Address 0x02000000 seg2end 4 4 13 Interrupt Registers Table 4 24 Interrupt Shape Register INTSHR address 0x 01f8 0044 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1
28. 0000 512 bytes 0100 8 Kbytes 1000 128 Kbytes 1100 2 Mbytes 0001 1 Kbytes 0101 16 Kbytes 1001 256 Kbytes 1101 4 Mbytes 0010 2 Kbytes 0110 32 Kbytes 1010 512 Kbytes 1110 8 Mbytes 0011 4 Kbytes 0111 64 Kbytes 1011 1 Mbytes 1111 16 Mbytes B 2 Area 2 Parity Protected pa2 bit only enables an parity protection on the I O Area 2 space If NOPAR NOPAR pin is tied to ground setting pa2 bit has no effect 0 parity protection disabled 1 parity protection enabled TSC695F checks parity B jo2 l O Area 2 Enable 2 bit enables I O Area 2 space from at 1200 0000 0 disable 1 enable B siz2 I O Area 2 Size 4 72 AIMEL TSC695F User Manual 4148H AERO 12 03 5122 field fixes the size in the I O Area 2 space 5122 Size 5122 Size siz2 Size 5122 Size 0000 512 bytes 0100 8 Kbytes 1000 128 Kbytes 1100 2 Mbytes 0001 1 Kbytes 0101 16 Kbytes 1001 256 Kbytes 1101 4 Mbytes 0010 2 Kbytes 0110 32 Kbytes 1010 512 Kbytes 1110 8 Mbytes 0011 4 Kbytes 0111 64 Kbytes 1011 1 Mbytes 1111 16 Mbytes 1 1 Parity Protected bit only enables an parity protection on the I O Area 1 space If NOPAR pin is tied to ground setting pa1 bit has no effect 0 parity protection disabled 1 parity protection enabled TSC695F checks parity B 01 1 Area 1 Enable 101 bi
29. 1 pin This interrupt is associated to the trap type tt 0x13 0 interrupt not pending 1 interrupt pending E 2 Interrupt Pending on asynchronous INT 2 ip 2 bit reflects a pending interrupt on the external interrupt number 0 EXTINT 0 pin This interrupt is associated to the trap type tt 0x12 0 interrupt not pending 4 82 AIMEL TSC695F User Manual 4148H AERO 12 03 1 interrupt pending E 0 1 Interrupt Pending on asynchronous INT 1 ip 1 bit reflects a pending interrupt on masked hardware errors This interrupt is associated to the trap type tf 0x11 0 interrupt not pending 1 interrupt pending Table 4 26 Interrupt Mask Register INTMKR address 0x 01f8 004c Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6151413121110 5 _ o reserved 0 0000 0000 0000 0000 AE 5 5 x JE im r r w r 0 0000 0000 0000 0000 11 1111 1111 1111 0 E 14 Interrupt Mask on asynchronous INT 14 im 14 bit masks the external interrupt number 4 EXTINT 4 pin 0 interrupt not masked 1 interrupt masked default E im 13 Interrupt Mask on asynchronous INT 13 im 13 bit masks the interrup
30. 12 03 Figure 1 3 TSC695F 8 bit System Architecture TSC695F Add Data n ROMCS IPROM8 EN Memory 2 Interface 2 MEMWR EM BUFFEN DDIR BUSRDY optional if no WS i 8 bit 2 Add gt decod SRAM lt Sbitbidir Xtd PROM Area a 7 0 optional GPI 7 0 EXTINT 4 0 User Peripherals RTC I Rx Tx Application Note 1 The SRAM area is emulated by the extended ROM area This area size can be up to 15M bytes from 0x 0100 0000 upto Ox 01EF FFFF This area is BUSRDY controlled for wait states This area is not protected by parity neither by EDAC 4148H AERO 12 03 AIMEL 2 1 The RISC Machine 2 2 The Characteristics of RISC TSC695F User Manual Section 2 Architecture The TSC695F is a 32 bit RISC processor implementing the SPARC architecture V7 specification A Reduced Instruction Set Computer is a microprocessor designed to perform a small number of types of computer instructions so that it can operate at a higher speed per form more MIPS Millions of Instructions Per Second The term itself RISC is credited to David Petersen a teacher at the University of California in Berkeley B Simple instruction set In a RISC machine the instruction set contains simple basic instructions from which more complex instructions can be composed The instruction set can be hardwired to speed instruction execution No microcode is n
31. AERO 12 03 0 interrupt not cleared 1 interrupt cleared ic 9 Interrupt Clear on asynchronous INT 9 ic 9 bit clears as a priority a forced interrupt else a pending interrupt on a DMA timeout 0 interrupt not cleared 1 interrupt cleared ic 8 Interrupt Clear on asynchronous INT 8 ic 8 bit clears as a priority a forced interrupt else a pending interrupt on a DMA access error 0 interrupt not cleared 1 interrupt cleared ic 7 Interrupt Clear on asynchronous INT 7 ic 7 bit clears as a priority a forced interrupt else a pending interrupt on a UART error 0 interrupt not cleared 1 interrupt cleared ic 6 Interrupt Clear on asynchronous INT 6 ic 6 bit clears as a priority a forced interrupt else a pending interrupt on a correctable error in memory 0 interrupt not cleared 1 interrupt cleared ic 5 Interrupt Clear on asynchronous INT 5 ic 5 bit clears as a priority a forced interrupt else a pending interrupt on either UART B data ready or transmitter ready 0 interrupt not cleared 1 interrupt cleared ic 4 Interrupt Clear on asynchronous INT 4 ic 4 bit clears as a priority a forced interrupt else a pending interrupt on either UART A data ready or transmitter ready 0 interrupt not cleared 1 interrupt cleared ic 3 Interrupt Clear on asynchronous INT 3 ic 3 bit clea
32. Binary Value Instruction Name Data Register Scan Chain Accessed 01 1000 CCTEST Checkers Scan Register IU parity checkers scan chain 01 1100 IUTEST IU Scan Register IU registers scan chain 01 1101 FPUTEST FPU Scan Register FPU registers scan chain 01 1110 SYSTEST System Scan Register System registers scan chain 01 1010 OCDTEST OCD Scan Register OCD registers scan chain 01 1001 CTSTEST OCD Ctrl Stat Register OCD control status scan chain 00 000011 EXTEST Boundary Scan Register Boundary scan chain 00 000111 SAMPLE PRELOAD Boundary Scan Register Boundary scan chain 00 0011 INTEST Boundary Scan Register Boundary scan chain 11 11111 BYPASS Bypass Register Bypass register 10 0000 IDCODE Device ID Register ID register scan chain Notes 1 Encoding fixed by IEEE JTAG protocol 2 Data register can be accessed SYSCLK CLK2 running 3 10 2 Mandatory B BYPASS instruction binary coded 11 1111 Instructions TSC695F User Manual AIMEL 3 37 4148 12 03 t is used to speed up shifting at board level through components that are not to be activated B EXTEST instruction binary coded 00 0000 t is used to test connections between components at board level Components output pins are controlled by boundary scan register during Capture DR on the rising edge of TCK B SAMPLE PRELOAD instruction binary coded 00 0001 t is used to get a snapshot of the normal operation by sampling I O states dur
33. Current Window Pointer cwp field contains a pointer to the currently active register file window cwp is decremented by traps and the SAVE instruction and is incremented by RESTORE and RETT instructions 4 3 Window Invalid Mask Table 4 3 Window Invalid Mask WIM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 3121 future expansion for additional windows 00 0000 TSC695F User Manual AIMEL 4 53 4148 12 03 Table 4 3 Window Invalid Mask WIM Continued 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 312 1 X X 4 4 Trap Base Register This register designates which window s will cause generation of an underflow or over flow trap when pointed to by the cwp as the result of a SAVE RESTORE or RETT instruction Each bit in the WIM register corresponds to a window if a bit is set to 1 the window cor responding to that bit is marked as invalid If a SAVE RESTORE or RETT instruction would cause the cwp to point to a window whose WIM bit equals 1 a window overflow SAVE or window underflow RESTORE RETT trap is generated The trap handler uses the local registers of the invalidated window A WIM bit is usually set by the operating system software to identify the boundary between the oldest and newest window The over
34. DEBUG While the halt mode is active the UARTs are temporarily halted AMEL TSC695F User Manual Figure 3 11 UARTS Halt TSC695F User Manual clk enable clk enable TIMCTR Timer Control Register UARTB Halt UARTA Hat Peripherals Halt The data format of the UARTs is eight bits It is possible to choose between even or odd parity or no parity and between one and two stop bits by programming the System Control Register SYSCTR After system reset odd parity and one stop bit are set The baud rate of the UART is set by programming scaler us and ubr fields the System Con trol Register SYSCTR After system reset the baud rate is set to divided by 32 B Programming Clock 24 32 x BaudRate x 2 ubr Scaler us The UARTs provide double buffering i e each UART consists of a transmitter holding register a receiver holding register a transmitter shift register and a receiver shift regis ter Each of these registers are 8 bit wide For each UART a RX and TX Register is provided UARTAR and UARTBR There is also a common UART Status Register UARTSR To output a byte on the serial output the following procedure should be followed First the UART Status Register UARTSR should be read in order to check that the transmit ter holding register thea and theb is empty Otherwise the previous byte to be output may be lost note that the tse bit is not useful for the purpose of c
35. Fault Type srft Fault Type 0111 uncorrectable error in memory 1111 reset value srfv Synchronous Fault Valid srfv bit indicates that the srft field is valid a synchronous fault has occured DMA error cannot overwrite the SYSFSR and FAILAR if srfv bit is set 0 not valid 1 valid This bit must be reset by software during trap handling to enable further SYSFSR and FAILAR updates on asynchronous fault detection and DMA synchronous errors Figure 4 2 FAILAR and SYSFSR Update Diagram Asynchronous fault asft updated asfv 1 occurence FAILAR updated trap generation Synchronous fault srft updated occurence i srfv 1 FAILAR updated Notes 1 After a trap occurence it is the responsibility of the software trap handler to reset or not SYSFSR by writing any value to it 2 This diagram is applicable only to the faults that update the SYSFSR refer to Trap section Table 4 14 Failing Address Register FAILAR address 0x 0118 00a4 Supervisor Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1 0000 0000 0000 0000 0000 0000 0000 0000 E Failing Address fa field contents the failing address of a synchronous or asynchronous fault which has occurred 4148H AERO 12 03 TSC69
36. are used to signal to the application system SYSHALT SYSHALT System Halt input Assertion of this pin will halt the TSC695F freezing IU FPU execution SYSCLK and internal CLK2 are running but all the timers and Watchdog are halted and the UART operation is stopped DMA accesses are allowed during halt mode When SYSHALT is deasserted the previous mode is entered B CPUHALT CPUHALT Processor IU and FPU Halt output This output informs that the IU and the FPU are in halt mode It can be used to halt other units in the system CPUHALT signal is also used to advise the freeze mode generated by the OCD B SYSAV System Availability output This signal is asserted whenever the system is available i e when the sysav bit in the ERRRSR is set and the CPUHALT CPUHALT and SYSERR SYSERR signals are deasserted The sysav bit is cleared by reset and is programmable by software m NOPAR NOPAR No Parity input Assertion of this signal will disable the parity checking of all signals related to the TSC695F internal buses The parity generation on the data bus towards memory and units is not affected by this signal but note that parity checking is disabled if NOPAR is asserted This is a static signal and shall not change when running When this signal is asserted no parity it disables the epa and rpa bits of the Memory Configuration Register MCNFR and the 2
37. dedicated for factory test mode The user functional mode is TMODE 1 0 00 m DEBUG Software Debug mode input DEBUG directly enables the setting of halt bits of the Timer Control Register to freeze integrated peripherals DEBUG phit freeze the internal Watchdog and the 2 internal timers DEBUG phit ahitfreeze the channel A of the internal UART DEBUG phit bhit freeze the channel B of the internal UART For final application this pin must be grounded This allows to keep software included debug facilities B TCK Test Clock input Test clock for scan registers B TRST TRST Test Reset input Asynchronous reset for the TAP controller For final application this pin must be grounded AMEL Hs 4148H AERO 12 03 5 5 Power Signals 5 6 Document History 5 110 4148H AERO 12 03 B TMS Test Mode Select input Selects test mode of the TAP controller B TDI Test Data Input input Test scan register data input B TDO Test Data Output output Test scan register data output B VCCO VCCI Power VCCO pins supply the output and bidirectional pins of the TSC695F VCCI pins supply the input and the main internal circuitry of the TSC695F B VSSO VSSI Ground VSSO pins provide ground return for the output and bidirectional pins of the TSC695F VSSI pins provide ground return for the input and the main internal circuitry of the TSC695F Revision Purpose of Modifications D
38. defines the external interrupts EXINT 7 0 to be either active on edge or levels sensitive edge Function edge Function 0 level triggered X Oxxx level triggered edge triggered 1xxx EXTINT 3 edge triggered X xxOx level triggered 0 xxxx level triggered xxxix EXTINT 1 edge triggered 1 EXTINT 4 edge triggered level triggered EXTINT 2 edge triggered 4 80 4148H AERO 12 03 AMEL TSC695F User Manual Table 4 25 Interrupt Pending Register INTPDR address 0x 01f8 0048 Supervisor and User Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111 10 9 8 61514131211 0 3 a 9 5g 2 z E lt sg 2 Zzlolkiziz E 8 S ltlE Z Zizis reserved 0000 0000 0000 0000 lt 2 5 5 s zu gt 51 5 S 5 6 ip r r r 0000 0000 0000 0000 000 0000 0000 0000 0 E 0 15 Interrupt Pending on asynchronous INT 15 ip 15 bit reflects a pending interrupt on the internal or external Watchdog timeout This interrupt is associated to the trap type tf Ox1F 0 interrupt not pending 1 interrupt pending E 0 14 I
39. enables the Exchange Memory space from at 01f0 0000 0 disable exchange memory space 1 enable exchange memory space B Exchange Memory EDAC Protected eec bit enables an EDAC protection on the Exchange Memory space If eec is set automatically a parity protection is done regardless the epa bit value 0 EDAC protection disabled 1 EDAC protection enabled B Exchange Memory Parity Protected epa bit only enables an parity protection on the Exchange Memory space If eec is set the epa bit value is don t care If NOPAR pin is tied to ground setting epa bit has no effect 0 parity protection disabled 1 parity protection enabled B esiz Exchange Memory Size esiz field fixes the Exchange Memory size in the Exchange Memory space esiz Size esiz Size 000 4 Kbytes 100 64 Kbytes 001 8 Kbytes 101 128 Kbytes 010 16 Kbytes 110 256 Kbytes 011 32 Kbytes 111 512 Kbytes B psiz Boot PROM Size TSC695F User Manual AIMEL 4 69 4148 12 03 psiz field fixes the PROM size in the Boot PROM space psiz Size psiz Size 000 128 Kbytes 100 2 Mbytes 001 256 Kbytes 101 4 Mbytes 010 512 Kbytes 110 8 Mbytes 011 1 Mbyte 111 16 Mbytes B 08 PROM 8 bit wide p8 bit is at reset written with the same value as PROM8 PROMS input A write operation to this bit has no effect is don t care 0 8 bit wide parity g
40. gpid 5 logical level GPI 5 pin gpid 2 logical level GPI 2 pin gpid 6 logical level GPI 6 pin gpid 3 logical level GPI 3 pin gpid 7 logical level 97 GPI 7 pin Table 4 38 UART A Rx and Tx Register UARTAR address 0x 01f8 00e0 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 151 14113112 11110 9 8 7 6 5 41312 1 reserved 0000 0000 0000 0000 0000 0000 r r w 0000 0000 0000 0000 0000 0000 0000 0000 W rida Received or Transmitted Data of UART A rtda field has 2 meanings 1 A write access enables the sending of the written 8 bit data on UART A 2 A read access provides the received 8 bit data UART A 4 94 AIMEL TSC695F User Manual 4148H AERO 12 03 Table 4 39 UART B Rx and Tx Register UARTBR address 0x 01f8 00e4 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 41312 1 reserved 0000 0000 0000 0000 0000 0000 rtdb r r w 0000 0000 0000 0000 0000 0000 0000 0000 ridb Received or Transmitted Data of UART B rt
41. halted default 1 UART A not halted E phit Peripherals HaLT AMEL TSC695F User Manual phit bit gives the possibility to disable the watchdog timer the RTC timer and the GPT timer for software debugging This effect of this bit is enabled by the DEBUG pin 0 peripherals not halted default 1 peripherals not halted B gpts General purpose Timer Scaler Load gptsl bit loads the GPT scaler with the preset value and the GPT scaler starts if it is enabled 0 no function 1 load scaler E gpte General purpose Timer Enabled gpte bit enables the counting for the GPT 0 hold scaler and counter 1 enable counting B gptcl General purpose Timer Counter Load gptcl bit loads the GPT counter with the preset value and the GPT counter starts if it is enabled 0 no function 1 load scaler B gpir General purpose Timer Reload bit enables the reload mode or one shot mode for the GPT 0 one shot mode 1 reload mode 4 15 Interface Registers Table 4 36 GPI Configuration Register GPICNFR address 0x 01f8 00a8 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 3121 reserved 0000 0000 0000 0000 r f i o r rw r w 0000 0000 0000 0000
42. input or output B GPIINT General purpose Interface Interrupt output An edge detection rising or falling is made on each GPI input pin configured as input GPIINT is the result of a logical OR of these detections This output is asserted high for 2 SYSCLK periods B EXTINT 4 0 External Interrupt input The five external interrupt inputs are programmable to be level or edge sensitive and active high rising or active low falling B EXTINTACK External Interrupt Acknowledge output EXTINTACK is used for giving acknowledge to an interrupting unit which requires such a signal It is programmable forthe five external interrupt inputs it is associated It is issued as soon as the IU has recognized the interrupt B IWDE Internal Watchdog Enable input This static signal commands the multiplexer placed in front of the Watchdog timeout interrupt of the Interrupt Pending Register To use the internal Watchdog IWDE must set to high This input set to low enables the input EWDINT for an external Watchdog and disables entirely the internal Watchdog not running The value of IWDE is copied into the System Control Register bit 15 TSC695F User Manual TSC695F User Manual B EWDINT External Watchdog Interrupt input This input enabled by IWDE receives an external Watchdog timeout Another usage of this input can be an NMI This input must asserted high for a minimum of 2 SYSCLK periods B WDCLK
43. internal and boundary scan through JTAG interface 1 2 Block Diagram Figure 1 1 TSC695F Block Diagram DMA Integer Floating point Access Wait State 1 Controller Ready Busy Address Ea Add Size ASI EDAC Data Check bits General purpose Parity m Interface Gen Check Parities GPI Bits RxD TxD Interrupts 1 3 Pin Description Table 1 1 Signal Descriptions Signal Type Active Description RA 31 0 VO 32 bit registered address bus Output buffer 400 pF RAPAR VO High Registered address bus parity RASI 3 0 4 0 registered address space identifier 4148H AERO 12 03 TSC695F User Manual Table 1 1 Signal Descriptions Continued Signal Type Active Description RSIZE 1 0 2 bit registered bus transaction size RASPAR VO High Registered ASI and SIZE parity CPAR VO High Control bus parity D 31 0 32 bit data bus CB 6 0 yo 7 bit check bit bus DPAR VO High Data bus parity RLDSTO VO High Registered atomic load store ALE Low Address latch enable DXFER VO High Data transfer LOCK VO High Bus lock RD VO High Read access WE VO Low Write enable WRT yo High Advanced write MHOLD Low Memory bus hold MHOLD FHOLD BHOLD FCCV MDS Low Memory data strobe Low Memory exception PROM8 Low Select 8 bit wide P
44. is 0001 B icc IU Condition Codes This field is modified by arithmetic and logical instructions whose names end with the letters cc for example ANDcc and can be overwritten by the writing PSR instruction The Bicc and Ticc instructions base their control transfer on these bits which are defined as follows 4 51 Rev 4148H AERO 12 03 B n Negative n bit indicates whether the ALU result was negative for the last icc modifying instruction 0 not negative 1 negative z Zero z bit indicates whether the ALU result was zero for the last icc modifying instruction 0 result was nonzero 1 result was zero E v oVerflow v bit indicates whether an arithmetic overflow occurred during the last icc modifying instruction The overflow bit is also set if a tagged operation TADDcc TSUBcc etc is performed on non tagged operands Logical instructions that modify the icc field always set the overflow bit to O 0 arithmetic overflow did not occur 1 arithmetic overflow did occur B Carry cC bit indicates whether an arithmetic carry out of result bit 31 occurred from the last icc modifying addition or if a borrow into bit 31 resulted from the last icc modifying subtraction Logical instructions that modify the icc field always set the carry bit to 0 0 acarry borrow did not occur 1 a carry borrow did occur B Reserved A WRPSR should write only 0
45. it reflects the internal signal Bus Hold should not be asserted in the processor clock cycle which follows a cycle in which LOCK is asserted LOCK is sent out unregistered and must be latched externally before it is used A DMA unit must supply this signal during a DMA session B RD Read Access output input RD is sent out during the address portion of an access to specify whether the current memory access is a read RD 1 or a write RD 0 operation RD is set low only dur ing the address cycles of store instructions For atomic load store instructions RD is set high during the load address cycle and set low during the two store address cycles RD may be used in conjunction with SIZE 1 0 ASI 7 0 and LDSTO to determine the type and to check the read write access rights of bus transactions in the Extended General area It is sent out unregistered and must be latched externally before it is used A DMA unit must supply this signal during a DMA session B WE WE Write Enable output input WE WE is asserted by the IU during the cycle in which the store data is on the data bus For a store single instruction this is during the second store address cycle the sec ond and third store address cycles of store double instructions and the third load store address cycle of atomic load store instructions To avoid writing to memory during mem ory exceptions WE must be externally qualified by the MHOLD when th
46. loading of the counter do not program rtcc 0 A read access gives the decounting value of the counter The RTCTimeout is the time between the loading or re loading and the RTC interrupt if rtcs gt 0 then RTCTimeout rtcc x rtcs 1 SYSCLK _ Ftcc 1 if rtcs 0 then RTCTimeout SYSCLE Note The SYSCLK of the formula is the SYSCLK output signal Table 4 32 Real time Clock Timer lt Scaler gt Register RTCSR address 0x 01f8 0084 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 76 5 41312 1 0 reserved 0000 0000 0000 0000 0000 0000 rics r r w 0000 0000 0000 0000 0000 0000 1111 1111 TSC695F User Manual 4 90 4148H AERO 12 03 E rtcs Real time Clock Timer Scaler rtcs field has 2 meanings A write access programs the pre loading of the scaler A read access gives the decounting value of the scaler Table 4 33 General purpose Timer Counter Register GPTCR address 0x 01f8 0088 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1 r w 1111 1111 1111 1111 1
47. processor They are not related to any particular instruction and occur between the execution of instructions A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler The base address of the table is established by supervisor and the displacement within the table is determined by the trap type Table 3 4 TSC695F Errors Traps and Priority Assignments Trap Output Sync Type Signal Trap and or error Async Priority tt Observation Comments Reset Sync 1 RESET Sources SYSRESET pin highest OCD reset priority Software reset Watchdog reset IU or System error reset Non restartable 2 21 0 64 SYSERR Severe error requiring a re boot ePC wPC PSR imprecise error if unmasked TSC695F enters if not masked in halt or reset mode Non restartable Sync 2 2 0x62 Error not removable PC and nPC OK dPC WIM TBR precise error TSC695F enters if not masked in halt or reset mode Register file error Sync 2 3 0x65 Special case register file of non restartable precise error TSC695F enters if not masked in halt or reset mode Restartable Sync 2 4 0x63 Retrying instruction but PC and nPC have to be re adjusted data late error load TSC695F enters if not masked in halt or reset mode Restartable
48. shaped close to one SYSCLK high pulse A good way to perform it is to synchronise with SYSCLK the asynchronous signal coming from your DMA controller m DRDY DRDY Data Ready during DMA access output During DMA read transfers when the external DMA is bus master this output is used to inform the DMA unit that the data are valid During DMA write transfers this signal indi cates that data have been written into memory E IUERR IUERR IU Error output This signal is asserted when the master IU enters the error mode state This happens if a synchronous trap occurs while traps are disabled the PSR s et bit 0 Before it enters the error mode state the TSC695F saves the PC and nPC and sets the trap type tt for the trap causing the error mode into the TBR It then asserts the error sig nal and halts The only way to restart a processor which is in the error mode state is to trigger a reset by asserting the RESET RESET signal B SYSERR SYSERR System Error output This signal is asserted whenever an unmasked error is set in the Error and Reset Status Register ERRRSR It stays asserted until the ERRRSR is cleared The error can origi AIMEL TSC695F User Manual TSC695F User Manual nate from either the IU IU error ar IU hardware error or the system registers system hardware error SYSERR and IUERR
49. the Floating point Condition Codes bits freezes the IU pipeline preventing any further compares from entering the pipeline The Floating point Condition Codes bits are reasserted when the compare is completed and the condition codes are valid thus ensuring that the condition codes match the proper compare instruction Bus Hold Bus Hold is asserted during DMA accesses Assertion of this hold signal will freeze the processor pipeline so after deassertion of Bus Hold external logic must guar antee that the data at all inputs to the TSC695F is the same as it was before Bus Hold was asserted This hold signal is tested on the falling edge midpoint of cycle of SYSCLK B MDS MDS Memory Data Strobe output MDS MDS is asserted by the memory access controller of the TSC695F to enable the clock to the IU s instruction register during an instruction fetch or to the load result reg ister during data fetch while the pipeline is frozen with an MHOLD In a system with slow memories MDS MDS tells the processor when the read data is available on the bus MDS MDS is also used to strobe the MEXC MEXC memory exception signal MDS MDS is only asserted when the pipeline is frozen with MHOLD MHOLD B MEXC MEXC Memory Exception output Assertion of this signal by the memory access controller of the TSC695F initiates a memory exception and indicates to the IU that the memo
50. the internal control bus a memory exception is asserted If a memory exception event occurs the System Fault Status Register SYSFSR is updated and reflects the type and location of parity errors All external parity checking can be disabled using the NOPAR signal The TSC695F uses CLK2 clock input directly and creates a system clock signal by dividing CLK2 by two It drives SYSCLK pin with a nominal 50 duty cycle for the appli cation Some output signals are clocked by the CLK2 negative edge which means that the CLK2 duty cycle has a direct impact on the system performance When interfacing peripherals I O interface DMA interface etc it is highly recom mended that only SYSCLK rising edge is used as reference as far as possible The sysav bit in the Error and Reset Status Register ERRRSR can be used by soft ware to indicate system availability The sysav bit is cleared by reset and is programmable by software Note that the SYSAV output signal is asserted only if the sysav bit is set and SYSERR is deasserted i e no error has been detected The TSC695F includes a number of software test facilities such as EDAC test Parity test Interrupt test Error test and a simple Test Access Port These test functions are controlled using the Test Control Register TESCTR Note that TMode 1 0 pins are only dedicated for factory test These pins must be kept grounded AIMEL TSC695F User Manual 3 7 Test and A variety of TSC69
51. trap being taken This field retains its value until the next trap is taken y 4 54 4148H AERO 12 03 AIMEL TSC695F User Manual Table 4 5 Y Register Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 312 1 0 r w X The Y register is used by the instruction set to create 64 bit products overflow flags etc This register is read and written using the non privileged RDY and WRY instructions 4 6 Window Registers Table 4 6 Window Registers Type Name Definition Reg i7 return address r31 fp frame pointer r30 i5 incoming parameter reg 5 r29 i4 incoming parameter reg 4 r28 i i3 incoming parameter reg 3 r27 i2 incoming parameter reg 2 r26 1 incoming parameter reg 1 r25 id incoming parameter reg 0 r24 17 local 7 23 le local reg 6 r22 local reg 5 r21 14 local reg 4 r20 local local reg 3 r19 l2 nPC for RETT r18 1 PC for RETT r17 10 local reg 0 r16 07 temp r15 sp stack pointer 14 05 outgoing parameter reg 5 ri3 04 outgoing parameter reg 4 r12 03 outgoing parameter reg 3 11 02 outgoing parameter reg 2 r10 o1 outgoing parameter reg 1 r9 00 outgoing parameter reg 0 r8 TSC695F User Manual AIMEL 4 55 4148 12 03 Table 4 6 Window Registers Continued
52. 000 0000 000 0000 0000 0000 0 E ic 15 Interrupt Clear on asynchronous INT 15 ic 15 bit clears as a priority a forced interrupt else a pending interrupt on the internal or external Watchdog timeout 0 interrupt not cleared 1 interrupt cleared E ic 14 Interrupt Clear on asynchronous INT 14 ic 14 bit clears as a priority a forced interrupt else a pending interrupt on the external interrupt number 4 EXTINT 4 pin 0 interrupt not cleared 1 interrupt cleared E ic 13 Interrupt Clear on asynchronous INT 13 ic 13 bit clears as a priority a forced interrupt else a pending interrupt on the Real time Clock Timer 0 interrupt not cleared 1 interrupt cleared E 12 Interrupt Clear on asynchronous INT 12 ic 12 bit clears as a priority a forced interrupt else a pending interrupt on the General purpose Timer 0 interrupt not cleared 1 interrupt cleared E ic 11 Interrupt Clear on asynchronous INT 11 ic 11 bit clears as a priority a forced interrupt else a pending interrupt on the external interrupt number 3 EXTINT 3 pin 0 interrupt not cleared 1 interrupt cleared E 10 Interrupt Clear on asynchronous INT 10 ic 10 bit clears as a priority a forced interrupt else a pending interrupt on the external interrupt number 2 EXTINT 2 pin TSC695F User Manual AIMEL 4 85 4148 12 03 4 86 4148H
53. 0000 0000 0000 0000 Falling edge Rising edge f field only configures GPI input pins to generate a interrupt 2xSYSCLK positive pulse on GPIINT pin 0 falling edge 1 rising edge E Input Output configuration i o field configures GPI input output pins as input or output pins A pin declared as output cannot generates an interrupt on GPIINT pin AMEL n 4148H AERO 12 03 TSC695F User Manual 0 input 1 output Table 4 37 GPI Data Register GPIDATR address 0x 0118 00ac Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 312 1 reserved 0000 0000 0000 0000 0000 0000 gpid r r w 0000 0000 0000 0000 0000 0000 GPI 7 0 pins value B gpid GPI Data gpid field contents the bit value of GPI 7 0 input output pins Writing gpid field only sets or resets the GPI 7 0 pins configured as output in i o field of GPI configuration register Reading gpid field indicates the logical level applied to GPI 7 0 pins as well pins declared as input than those declared as output by i o field of configuration register gpid State gpid State gpid 0 logical level GPI 0 pin gpid 4 logical level GPI 4 pin gpid 1 logical level GPI 1 pin
54. 1 Function rbr1 Function 000 MEMCSJ 0 inactive and replaced 100 MEMCS 4 inactive and replaced 001 MEMCS 1 inactive and replaced 101 MEMCSJ 5 inactive and replaced 010 MEMCS 2 inactive and replaced 110 MEMCSJ 6 inactive and replaced 011 MEMCSI3 inactive and replaced 111 MEMCS 7 inactive and replaced E rbs Redundant RAM Block 1 Selected rbs1 bit selects the replacement of any RAM block by the RAM block 1 see rbr1 field description 0 block 1 not selected 1 block 1 selected E rbro Redundant RAM Block 0 Replace field fixes the replacement of any RAM block by the RAM block 0 The MEMCS x MEMCS x signal corresponding to the replaced block will be inactive and MEMCS signal will be active instead If rbrO and rbr1 are set to the same value rbr1 setting will have no effect rbrO Function rbrO Function 000 MEMCSJ 0 inactive and replaced 100 MEMCS 4 inactive and replaced 001 MEMCS 1 inactive and replaced 101 MEMCSJ 5 inactive and replaced 010 MEMCS 2 inactive and replaced 110 MEMCSJ 6 inactive and replaced 011 MEMCSI3 inactive and replaced 111 MEMCS 7 inactive and replaced E rbsO Redundant RAM Block 0 Selected rbs0 bit selects the replacement of any RAM block by the RAM block 0 see rbr0 field description 0 block 0 not selected 1 block 0 selected E rbcs Number of RAM Block Ch
55. 1 64 Kbytes 1011 1 Mbytes 1111 16 Mbytes Table 4 19 Waitstate Configuration Register WSCNFR address 0x 01f8 0018 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 151 14113112 11110 9 8 7 6 5 41312 1 0 io3rw io2rw ioirw ioOrw exrw prw prr raw rar r w r w r w r w r w r w r w r w rw 1111 1111 1111 1111 1111 1111 1111 11 11 E jo3rw I O Area nbr of Read Write Waitstates io3rw field fixes the number of waitstates in the I O Area 3 space The TSC695F always inserts a minimum of 1 waitstate to wait for BUSRDY BUSRDY signal even 0 waitstate is programmed io3rw Waitstate Read or Write Cycle 0000 0 ws 3 SYSCLK periods 0001 1 ws 3 SYSCLK periods XXXX n ws 2 n SYSCLK periods 1111 15 ws 17 SYSCLK periods E jo2rw Area 2 nbr of Read Write Waitstates io2rw field fixes the number of waitstates in the I O Area 2 space The TSC695F always inserts a minimum of 1 waitstate to wait for BUSRDY BUSRDY signal even 0 waitstates is programmed io2rw Waitstate Read or Write Cycle 0000 0 ws 3 SYSCLK periods 0001 1 ws 3 SYSCLK periods XXXX n ws 2 n SYSCLK periods 1111 15 ws 17 SYSCLK periods E joirw I O Area 1 nbr of Read Write Waitstates 4 74 AIMEL TSC695F Us
56. 111 1111 1111 1111 B General purpose Timer Counter gptc field has 2 meanings 1 Anwrite access programs the pre loading of the counter do not program gptc 0 2 Aread access gives the decounting value of the counter The GPTTimeout is the time between the loading or re loading and the GPT interrupt _ X gpts 1 if gpts gt 0 then GPTTimeout SYSCLE GPTTimeout ep SYSCLK Note The SYSCLK of the formula is the SYSCLK output signal if gpts 0 then Table 4 34 General purpose Timer lt Scaler gt Register GPTSR address 0x 01f8 008c Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111 10 9 8 7 6 5 43121 reserved 0000 0000 0000 0000 gpts r r w 0000 0000 0000 0000 1111 1111 1111 1111 B gpts General purpose Timer Scaler gpts field has 2 meanings 1 A write access programs the pre loading of the scaler 2 Aread access gives the decounting value of the scaler AMEL 4148H AERO 12 03 TSC695F User Manual Timer Control Register Table 4 35 Timer Control Register TIMCTR address 0x 01f8 0098 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
57. 13 12 11 10 9 8 7 6 5 41312 1 reserved 000 0000 E E segibase uiu r r w Ww Ww TSC695F User Manual A MEL 4 77 4148 12 03 Table 4 20 Access Protection Segment 1 Base Register APS1BR address 0x 01f8 0020 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 151 14113112 11110 9 8 7 6 5 41312 1 000 0000 0 0 000 0000 0000 0000 0000 0000 B se Supervisor Enable Segment 1 sel bit enables the write protection in supervisor mode the segment 1 defined by seg1base and seg1end 0 write access protection disabled in supervisor mode 1 write access protection enabled in supervisor mode B vei User Enable Segment 1 sel bit enables the write protection in user mode on the segment 1 defined by segibase 0 write access protection disabled in user mode 1 write access protection enabled in user mode B segibase Segment 1 BASE Address segtbase field defines the base address for the segment 1 The Segment 1 Base Address is calculated according the formula Segment 1 Base Address 0x02000000 segibase 4 Table 4 21 Access Protection Segmen
58. 4 97 4148 12 03 AIMEL 5 1 IU and FPU Signals Section 5 Signals Description B RA 31 0 Registered Address Bus output input The address bus for the TSC695F is an output bus Inside the processor the IU address bus is used to perform decoding to generate select signals and to check against the memory access protection scheme It is also used to address the system registers To save board space the address bus is sent out registered for external resources This means that internal D type flip flop s are implemented inside the TSC695F to memorize the IU address bus at each rising edge of SYSCLK enabled by ALE ALE signal This registered address bus is always driven by the TSC695F even during system registers accesses In case of DMA session the address bus for the TSC695F is an input bus The DMA unit must drive itself to the registered address bus for the available parts of the proces sor during a DMA session and for the external resources SRAMs ROMs I Os Organization and addressing of data in memory follows the Big Endian convention wherein lower addresses contain the higher order bytes Attempting to access mis aligned data will generate a memory_address_not_aligned trap tt 0x07 Doubleword Word 0 Word 0 Halfword 1 1 1 5 Halfword 0 5 Halfword 5 Halfword 0 7 Byte 7 Byte 0 7 Byte 0 7 Byte 0 N B
59. 5F User Manual Table 4 15 Error and Reset Status Register ERRRSR address 0x 01f8 00b0 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 43121 0 S gt 9 28 reserved reserved 0000 0000 0000 0000 D 00 0000 5 gt 2 2 5 o o r r r r r r r r w Ww w r w 0000 0000 0000 0000 x 00 0000 1 E rstc Reset Cause rstc field indicates what type of reset has occured 00 system reset or OCD 01 software reset 10 error reset 11 watchdog reset hit Halt hit bit indicates that the IU and FPU is halted 0 not active 1 active B sysav System Availability sysav bit can be used by software to indicate system availability sysav bit is cleared by reset and is programmable by software Note that SYSAV output will be asserted only if sysav bit is set and SYSERR is deasserted i e no error has been detected 0 not active 1 active B syshe System Hardware Error syshe bit indicates hardware error on system registers syshe bit is only writable when ewe bit in the Test Control Register TESCTR is set 0 no error 1 internal parity error E fpuhe FPU Hardware Error
60. 5F test and diagnostic hardware functions including boundary scan Diagnostic internal scan clock control and On chip Debugger are controlled through an IEEE Hardware 1149 1 JTAG standard Test Access Port TAP Commands and data are sent as Functions serial data between the JTAG master and the TSC695F a JTAG slave via a 4 wire serial testability bus JTAG bus 3 8 Test Access Port 3 8 1 TAP Interface The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip These pins are Table 3 7 TAP Signals Pin Name Type Description TCK Test Clock Input Used to clock serial data into scan latches and control sequence of the test state machine TCK can be asynchronous with CLK2 and SYSCLK TMS Test Mode Input Primary control signal for the state machine Synchronous with TCK A sequence of Select values on TMS adjusts the current state of the TAP TDI Test Data Input Input Serial input data to the scan latches Synchronous with TCK TDO Test Data Output Output Serial output data from the scan latches Synchronous with TCK TRST Test Reset Input Resets the test state machine can be asynchronous with TCK Note For more details on the IEEE protocol please refer to the IEEE document IEEE Standard Test Access Port and Boundary scan Architecture 3 8 2 Board Level Any TSC695F based system will contain several JTAG compatible chips These Architecture connected using the minimum single TMS si
61. 695F User Manual 4148H AERO 12 03 0 watchdog clock lt external clock WDCLK no prescaler 1 watchdog clock external clock WDCLK with prescaler divide by 16 E bp Block Protection bp bit defines the write access protection type which is segment based The bp bit inverts the address criterion for the protection function 0 write access allowed within segments and not outside segment mode 1 write access allowed outside segments and not within block mode bto Bus Timeout bto bit enables or no the bus timeout function A bus timeout function of 256 or 1024 SYSCLK cycles is provided for the bus ready controlled memory areas 256 in the Extended RAM Extended General and Extended I O areas and 1024 in the Extended PROM area 0 bus timeout function disabled 1 bus timeout function enabled default B swr Software Reset swr bit allows or no the software reset command the writing to SWRST register 0 software reset not allowed 1 software reset allowed B Power down prd bit allows or no the power down command the writing to PDOWN register 0 power down not allowed 1 power down allowed Table 4 11 Software Reset SWRST address 0x 01f8 0004 Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 41312 1
62. 8H AERO 12 03 B FLUSH FPU Instruction Flush output This signal is asserted by the IU whenever it takes a trap FLUSH is used by the FPU to flush the instructions in its instruction buffers These instructions as well as the instruc tions annulled in the IU pipeline are restarted after the trap handler is finished If the trap was not caused by a Floating point exception instructions already in the Floating point queue may continue their execution If the trap was caused by a Floating point exception the FP queue must be emptied before the FPU can resume execution B DIA Delay Instruction Annulled output This signal is asserted when the delay instruction is annulled See delayed control transfer This signal is used to trace the IU execution pipe B RTC Real time Clock Counter Output output This signal is generated when the delay time has elapsed in the Real time Clock Timer This output is asserted high for 1 5 SYSCLK period Receive Data channel A input RXA is the serial data input for channel A of the UART B RXB Receive Data channel B input RXB is the serial data input for channel B of the UART B TXA Transmit Data channel A output TXA is the serial data output for channel A of the UART B TXB Transmit Data channel B output TXB is the serial data output for channel B of the UART B GPI 7 0 General purpose Interface input output Each pin of the GPI is programmable as
63. B Operating Range 4 5V to 5 5V 55 C to 125 C B Total Dose Radiation Capability Parametric and Functional 300 KRADs Si B SEU Event Rate Better than 1E 8 Error Component Day Worst Case Latch up Immunity Better than LET 100 MeV cm mg 1 1 Rev 4148H AERO 12 03 B Quality Grades ESA SCC QML Q or V B Package 256 MQFPF KGD 1 1 Description The Rad Hard 32 bit SPARC Embedded Processor TSC695F ERC32 Single chip is a highly integrated high performance 32 bit RISC embedded processor implementing the SPARC architecture V7 specification It has been developed with the support of the ESA European Space Agency and offers a full development environment for embedded space applications The processor is manufactured using the Atmel 0 5 um radiation tolerant gt 300 KRADs Si CMOS enhanced process RTP It can operate at a low voltage for optimized power consumption It has been especially designed for space as it has on chip concur rent transient and permanent error detection The TSC695F includes on chip an Integer Unit IU a Floating point Unit FPU a Mem ory Controller and a DMA Arbiter For Real time applications the TSC695F offers a high security watchdog two timer s an interrupt controller Parallel and Serial interfaces Fault tolerance is supported using parity on internal external buses and an EDAC on the external data bus The design is highly testable with the support of an On chip Debug ger OCD an
64. IMEL 5 99 4148 12 03 Figure 5 1 Byte Operand Load and Store 5 100 4148H AERO 12 03 Address N N 1 N 2 N 3 Memory Location 31 24123 16 15 8 7 0 m Y Destination Register 31 Zeroes or Sign Extension 8 7 0 Byte load example from address 1 Address N N 1 N 2 N 3 Data Bus 31 24 23 16 15 817 0 0 A AO Source Register 31 Dont Care 8 7 0 The irrelevant bytes of the data bus are filled with the stored data byte idem for half word Byte store example from address N 2 The Extended general area works without parity as I O areas A DMA unit must drive these bits to 10 since only word transfers are allowed in DMA mode B RASPAR Registered RASI and RSIZE Buses Parity output input This output is the odd parity over the RASI 3 0 and the RSIZE 1 0 signals To save board space this output is sent out registered and has the same timing as RA 31 0 In case of DMA session this signal must be driven by the DMA unit if DMA parity is enabled This input requires the same timing as RA 31 0 B CPAR Control Bus Parity output input This output is the odd parity over the RLDSTO DXFER LOCK WRT RD and WE WE signals This signal is sent out unregistered and must be latched externally before it is used In case of DMA session this signal must be driven by the DMA unit if DMA parity is enabled m D 31 0 D
65. INT 4 0 External INT 0 Async 26 0x12 INT level 2 EXTINTAK on only one of EXTINT 4 0 Masked hardware Async 27 Ox11 IUERR if IU INT level 1 When a hardware error is set in the Error and Reset errors lowest error mode Status Register and the error is masked priority It is the OR IU hardware error masked IU error mode masked System hardware error masked 3 20 4148H AERO 12 03 When synchronous traps and asynchronous traps occur in the same cycle the synchro nous trap with the highest priority is taken and other synchronous traps with lower priority are ignored At the same time the asynchronous traps are reported as pending in the interrupt pending register Once the synchronous trap with the highest priority is AIMEL TSC695F User Manual TSC695F User Manual handled the unmasked asynchronous traps are handled from the highest priority to the lowest priority If a synchronous trap event occurs during memory access the System Fault Status reg ister is updated in accordance with the synchronous condition table see table 3 5 The System Fault Status register SYSFSR also indicates the type of error and whether this type of error is valid At the same time the failing address is stored in the Failing Address Register FAILAR Table 3 5 SYSFSR amp FAILAR Update synchronous condition table Synchronous Instruction access Data acces
66. INTPDR register are cleared automatically when the interrupt is EXTINTACK acknowledged INTACK INTSHR 5 5 INTMKR b 5 EXTINT 4 0 P Maskable Internal Interrupts 4 15 15 and gt 1 4 15 1 15 Internal INTFCR Pe L TESCTR EWDINT bit 19 y cm INTER SYSCTR INTACK from IU Interrupt Request Level to IU INTPDR 6 B When Interrupt test is not enabled Setting or clearing a bit in INTFCR register will only affect INTFCR register The corresponding interrupt will not be forced When the interrupt is acknowledged the TSC695F will automatically clear the corresponding bit in the INTPDR register B When Interrupt test i is enabled Setting a bit in INTFCR register will force the corresponding interrupt if it is not masked in INTMKR register When the interrupt is acknowledged the TSC695F will automatically clear the corresponding bit in the INTFCR register if this bit is set otherwise it will clear the corresponding bit in the INTPDR register In this way no external interrupts are lost 3 26 AIMEL TSC695F User Manual 4148H AERO 12 03 3 6 8 Timers In software debug mode the timers are controlled by a system register bit ph t bit 4 in Timer Control Register TIMCTR and an external pin DEBUG Setting the external IWDE to Voc enables the Watchdog Timer Otherwise the watchdog function must be e
67. MAREQ When the DMA unit receives the DMAGNT signal in response the processor bus is granted In case the processor is in the power down mode the processor is permanent tri stated and a DMAREQ will directly give a DMAGNT A memory cycle started by the processor is not interrupted by a DMA access before it is finished Because the TSC695F provides registered address buses the DMA unit must generate such buses characteristics TSC695F User Manual AIMEL 3 17 4148 12 03 The TSC695F includes a DMA session timeout function preventing the DMA unit from locking out the processor by asserting DMAREQ for more than 1024 system clock cycles after the assertion of DMAGNT Then a memory exception is asserted and the DMAGNT is removed 3 6 6 2 Bus Arbiter The TSC695F always has the lowest priority on the system bus and is denied access to memory in case of a request from a DMA unit unless the IU is performing a locked access or after DMA exception cycle to allow interrupt handling Thus the DMA is granted access to the system bus provided this has been enabled by the processor 3 6 7 Traps The TSC695F supports two types of traps synchronous and asynchronous also called interrupts Synchronous traps are caused by hardware responding to a particular instruction or by the Trap on integer condition code Ticc instructions they occur during the instruction that caused them Asynchronous traps occur when an external event interrupts the
68. PROM8 0 mode Only byte write timeout Extended Ox 0100 Max sony PROM 0000 15M Parity EDAC no CS BUSRDY PROMS 1 40 bit mandatory BUSERR mode Only word write timeout gt e 9 Exchange Ox 01 0 4K Parity EDAC options EXMCS IOWR OE BUFFEN Hid BUSERR zs 1 WR aa LH Memory 0000 512K Only word write MEM and DDIR oen timeout System Ox 01F8 512K Internal parity Registers 0000 124 used Only word write access RAM 0x 0200 8 32K RAMCS internal 8 blocks 0000 8 4M Parity EDAC options 9 0 VEWWR oe WS g All data sizes allowed BUFFEN Extended 0400 Max BUFFEN 0000 192M no CS and BUSRDY BUSERR 0 1000 Area 0 0000 16 0 1100 internal Area 1 0000 Max 16M Parity option WS IOSEL No EDAC 3 0 generation Area 2 Ox 1200 16M All data sizes allowed TOWR BUFFEN and BUSERR 0000 and DDIR BUSRDY timeout Ox 1300 Area 3 0000 Max 16M Extended Ox 1400 Max Same setting as Ac EONI VO Area 0000 1728M for I O Area 3 Does Extended 0 8000 No parity no EDAC BUFFEN Max 2 CS IOWR BUSRDY General 0000 ANS allowed and DDIR TSC695F User Manual AIMEL 3 11 4148 12 03 3 6 2 System Registers Table 3 2 System Registers Address Map System Register Name Address
69. ROM BA 1 0 Latched address used for 8 bit wide boot PROM ROMCS Low PROM chip select ROMWRT Low ROM write enable MEMCS 9 0 O Low Memory chip select Output buffer 400 pF MEMWR Low Memory write strobe Output buffer 400 pF OE Low Memory output enable Output buffer 400 pF Low Data buffer enable DDIR High Data buffer direction DDIR Low Data buffer direction IOSEL 3 0 Low chip select Low and exchange memory write strobe 5 Low Exchange memory chip select BUSRDY Low Bus ready BUSERR Low Bus error DMAREQ Low DMA request DMAGNT Low DMA grant DMAAS High DMA address strobe DRDY Low Data ready during DMA access IUERR Low IU error CPUHALT Low Processor IU and FPU halt and freeze SYSERR Low System error SYSHALT Low System halt SYSAV High System availability NOPAR Low No parity INULL High Integer unit nullify cycle INST High Instruction fetch Used to check the FLUSH High FPU instruction flush execute stage of IU DIA High Delay instruction annulled instruction pipeline RTC High Real time Clock Counter output RxA RxB Receive data UART A and Input trigger TxA TXB Transmit data UART A AMEL 1 3 4148H AERO 12 03 1 4 4148H AERO 12 03 Table 1 1 Signal Descriptions Continued
70. RRRSR are cleared A MEL 3 33 4148 12 03 Figure 3 13 Error Handler Schematic IU trap in tra Drap IU Error Mode internal rap 0x61 jum B arit rap 0x62 pel pea ie rap 0x63 ne checkers rap 0x64 i register file Trap 0x65 checkers E Interrupt Request Level 3 0 o lt 22 o 3 D as D L 5 3 lt mi x 2 parity checkers FPU 3 6 13 Parity Checking 3 6 14 System Clock 3 6 15 System Availability 3 6 16 Test Mode 3 34 4148H AERO 12 03 pins register gt A X HW error and checkers N internal 0x08 SYSERR pin sources IUERR pin X FPU Hardware system hardware error ER R rhiuem m syshemsk rhsyshe RR interrupt system 2 EXINT 4 0 V other Sources X lt RESET HALT System The TSC695F includes parity checking and generation if required on the external data bus DPAR pin It includes parity checking on the external address bus RAPAR pin It also includes parity checking on ASI and SIZE RASPAR pin together with parity gener ation and checking on all system registers The TSC695F also includes parity generation and checking on the internal control bus to the IU CPAR pin If a parity error is detected on the external data bus the external address the external RASI and RSIZE
71. SC695F generates DPAR 0 w EDAC ignores data parity E IU FPU generates data parity ie epa 0 IU FPU ignores data parity but generates EDAC ignores data parity 3 0 0 S its own parity for its internal usage Ext 1 09 TSC695F samples DPAR TSC695F generates DPAR 1 w EDAC checks data parity E IU FPU generates data parity NS epa 1 D IU FPU ignores data parity but generates EDAC ignores data parity pax 1 amp its own parity for its internal usage TSC695F User Manual AIMEL 3 15 4148 12 03 Table 3 3 DPAR and NOPAR Handling See Figure 3 1 Continued Memory Accessed Parity Q Memory Area Enabled Read or Fetch Access Write Access TSC695F ignores DPAR TSC695F doesn t generate DPAR 1 S EDAC checks data parity Gi IU FPU generates data parity 2 IU FPU checks data parity 2 EDAC checks data parity System Yes z Registers TSC695F ignores DPAR TSC695F doesn t generate DPAR EDAC checks data parity E IU FPU generates data parity en IU FPU ignores data parity but generates D EDAC ignores data parity its own parity for its internal usage TSC695F ignores DPAR TSC695F generates DPAR 1 EDAC generates data parity IU FPU generates data parity 2 IU FPU checks data parity 2 EDAC checks data parity Extended No General TSC695F ignores DPAR T
72. SC695F generates DPAR 0 E EDAC ignores data parity E IU FPU generates data parity 9 IU FPU ignores data parity but generates 9 EDAC ignores data parity S its own parity for its internal usage Notes 1 Extended PROM area has the same configuration memory parity enabled disabled than PROM area 2 Extended RAM area has the same configuration memory parity enabled disabled than RAM area 3 Extended I O area has the same configuration memory parity enabled disabled than l O 3 area 3 6 5 4 Memory Redundancy 3 6 5 2 Memory Access Protection 3 16 4148H AERO 12 03 B Programming the Memory Configuration Register The TSC695F provides chip selects for two redundant memory banks for replacement of faulty banks A memory bank is a block composed of 32 bit data parity and a 7 bit check code and controlled with one chip select signal The size of the redundant memory banks are dependent of the memory size register Unimplemented Areas Accesses to all unimplemented memory areas are handled by the TSC695F and detected as illegal The memory and I O configuration registers define the size of memory and I O areas Then if the TSC695F or the DMA Unit access the unused area of the memory space is decoded as illegal a memory exception is asserted AIMEL TSC695F User Manual W RAM Write Access Protection Figure 3 2 RAM Write Access Protection Segment 1 Segment 2 Segment 2 Segment mode bp
73. Sync 2 5 0 61 Retrying instruction fetch i e fPC bi precise error TSC695F enters if not masked in halt or reset mode 3 Error mode Sync IUERR Trap occurs with et psr bit 0 5 SYSERR Trap Masked hardware errors if enabled E if unmasked TSC695F enters if not masked in halt or reset mode 3 18 AIMEL TSC695F User Manual 4148H AERO 12 03 Table 3 4 TSC695F Errors Traps and Priority Assignments Continued Trap Output Sync Type Signal Trap and or error Async Priority tt Observation Comments Instruction access Sync 3 0x01 Error on instruction fetch Parity error on control bus refer to CPAR signal description Parity error on data bus refer to DPAR signal description Parity error on address bus refer to RAPAR signal description Access to protected or unimplemented area Uncorrectable error in memory refer to EDAC section Bus time out refer to Waitstate and Timeout Generator section Bus error refer to BUSERR signal description Illegal Instruction Sync 4 0x02 Privileged instruction Sync 5 0x03 FPU disabled Sync 6 0x04 FPU disabled by ef psr bit 0 Co processor Sync 6 0x24 Co processor not implemented in TSC695F disabled Overflow Sync 7 0x05 During SAVE instruction or trap taken Window Underflow Sync 0x06 During RESTORE instruction or RETT in
74. TSC695F SPARC 32 bit Space Processor User Manual 4148H AERO 12 03 Table of Contents AIMEL Section 1 acte EA 1 1 1 4 Description tete even dias 1 2 1 2 1 3 Pin eee 1 2 1 6 System Architecture ret eret rerit e dene tinued deanna eene Rut 1 5 Section 2 FAN 2 7 2 1 RISC 2 7 2 2 Characteristics of RISG escini en 2 7 2 21 The Advantages of RISC 2 RANAR E 2 8 2 3 The SPARC 2 8 2 9 1 REGISTER WINDOWS 2 8 Section 3 Product Description Ep 3 9 E 3 9 3 2 meger ee ee ener 3 9 3 3 Floating point UDE 3 10 3 4 Cosprocessor Unit eccerre tba 3 10 3 5 Instruction beni 3 10 3 5 3 10 3 6 1 Memory 3 10 3 6 2 SYSTEM REGISTSMS eode D 3 12 3 6 3 Waitstate and Timeout
75. UFFEN It is valid during all memory accesses DDIR is asserted high during store operations DDIR DDIR Data Buffer Direction output DDIR DDIR is used for determining the direction of the data buffers enabled by BUFFEN BUFFEN It is valid during all memory accesses The DDIR is asserted high during fetch or load operations B IOSEL 3 0 IOSEL 3 0 IO Chip Select output These four select signals are used to enable one of four possible I O address areas B IOWR IOWR IO Write output IOWR IOWR is asserted during write operations to the I O area extended I O area and the exchange memory area B EXMCS EXMCS Exchange Memory Chip Select output EXMCS EXMCS is asserted when the exchange memory is accessed m BUSRDY BUSRDY Bus Reagy input BUSRDY BUSRDY is to be generated by a unit the I O area exchange memory area or in the extended areas which requires extended time when accessed in addition to the preprogrammed number of wait states Note however that waitstates can not be preprogrammed for units in the extended general area only for extended I O boot PROM and RAM m BUSERR BUSERR Bus Error input BUSERR BUSERR is to be generated together with BUSRDY BUSRDY by a unit in the I O area exchange memory area or in the extended areas if an error is detected by the accessed unit during an access Table 5 4 Bus Transaction Response Signals BUSERR BUSRDY
76. User Manual A MEL 3 27 4148 12 03 has elapsed If the timer is not programmed with a new value when set to periodical type it restarts from the latest programmed value and continue to count down thus gen erating interrupts periodically It is possible to halt and restart the timers by writing to the Timer Control Register TIMCTR Only the current value of the scaler and counter of the GPT can be read never the pre loaded values After system reset the Real time Clock is not running and must be programmed as required B Programming counter X scaler 1 if scaler gt 0 then Timeout SYSCLK _ counter 1 if scaler 0 then Timeout SYSCLE Do not program counter 0 B Behavior During the 1 0 transition the counter has the value of 0 for one clock cycle and then immediately reloaded The timeout period is not affected the reloaded value will be decremented on the next scaler tick as can be expected and generates a timeout period equal to the reload value When the scaler is rogrammed to 0 a scaler tick is generated every clock and the timeout period will be the counter reload value 1 Figure 3 5 Timer Behavior Example when Scaler gt 0 Reload mode Scaler 1 Counter 3 KTETATATELELAELETETETATA Scaler Tick A A A A A A Counter Valu
77. Watchdog Clock input WDCLK is the WD clock input but this clock can also be used as a clock input for the UART interface The clock frequency of WDCLK must be less than the clock frequency of SYSCLK i e lt B CLK2 Double Frequency Clock input 2 is the input clock to the TSC695F The frequency of this clock must be twice the clock frequency fsysc used to drive the IU and the FPU Note that some external tim ings of the TSC695F can be affected by the duty cycle of CLK2 B SYSCLK System Clock output SYSCLK is a nominally 50 duty cycle clock generated by the TSC695F from CLK2 and is used for clocking the IU and the FPU as well as other system logic Note that the timing of the TSC695F is referenced by SYSCLK B RESET RESET Reset output RESET RESET will be asserted when the TSC695F is to be synchronously reset This occurs when either SYSRESET SYSRESET is asserted or the TSC695F initiate a reset due to an error or a programming command The minimum pulse width of RESET RESET is 1024 SYSCLK periods to authorize the implementation of Flash memories in the application B SYSRESET SYSRESET System Reset input Assertion of this pin will reset the TSC695F Following this assertion RESET RESET is generated for a minimum of 1024 SYSCLK periods SYSRESET must be asserted for a minimum of 4 SYSCLK periods m TMODE 1 0 Test mode input This test mode is only
78. Window underflow This trap occurs when the continued execution of a RESTORE instruction would cause the to point to a window marked invalid in the WIM register The window underflow trap type can also be set in the psr during a RETT instruction but the trap taken is a reset AMEL 3 23 4148H AERO 12 03 3 24 4148H AERO 12 03 B Memory address not aligned Memory address not aligned trap occurs when a load or store instruction generates a memory address that is not properly aligned for the data type or if a JMPL instruction generates a PC value that is not word aligned low order two bits nonzero B FPU exception Non restartable error fsr s f t t field 7 This type of error concerns parity errors that were detected after the state of the FPU was changed and could not be removed by restarting the instruction fsr Register File An hardware error will be asserted and stay asserted until the next FPop encoun tered in the instruction stream after a STDFQ instruction modifies the ftt field of fsr Data bus error fsr s f t t field 5 This type of error concerns parity errors on the internal data bus detected by the FPU Restartable error fsr s f t tfield 6 This type of error concerns parity errors in the FPU that were detected before changing the FPU state and could be removed by restarting the instruction IU to FPU internal control bus Sequence error fsr
79. amming write operations of the boot PROM when EEPROM or FLASH devices are used B MEMCS 9 0 MEMCS 9 0 Memory Chip Select output MEMCS 9 0 MEMCS 9 0 is asserted during an access to the main memory MEMCS 9 8 559 8 are redundant signals used to substitute any of the nomi nal memory banks when memory connected to any of MEMCS 7 0 MEMCS 7 0 malfunctions AIMEL TSC695F User Manual 5 3 Error DMA Halt and Check Signals TSC695F User Manual MEMWR MEMWR Memory Write output MEMWR MEMWR is asserted during write access store to boot PROM area extended PROM area RAM area and extended RAM area It is intended to be used as write strobe to the memory devices m OE OE Output Enable output OE OE is asserted during fetch or load accesses to the main memory It is intended to be used to control memory devices with output enable features B BUFFEN BUFFEN Data Buffer Enable output BUFFEN BUFFEN is asserted during memory accesses excepted in RAM area RAM area does not needs data buffers It is intended to be used as buffer enable for data check and parity bit buffers in the boot PROM area extended PROM area exchange memory area extended RAM area I O area extended I O area and extended general area if these areas share the same buffers B DDIR Data Buffer Direction output DDIR is used for determining the direction of the data buffers enabled by BUFFEN B
80. and floating point instructions is provided by the IU The FPU provides three types of registers f registers FSR and the FP queue The FSR is a 32 bit status and control register It keeps track of rounding modes floating point trap types queue status condition codes and various IEEE exception information The floating point queue contains the floating point instruction currently under execution along with its corresponding address No co processor unit is available on TSC695F Attempting to execute co processor instructions will cause the TSC695F to execute a cp disable trap tt 0x24 TSC695F instructions fall into six functional categories load store arithmetic logi cal shift control transfer read write control registers floating point operate and miscellaneous Note The execution of IFLUSH will cause an illegal instruction trap tt 2 0x02 The TSC695F is designed to allow an easy interface to internal external memory resources AIMEL TSC695F User Manual Table 3 1 Memory Mapping Memory Start Size Data Size Contents Address bytes and Parity Options Access and Waitstate Control 8 bit No parity DBANMA 128K mode Only byte write internal PROMSE Q Boot 0000 ROMCS WS PROM 0000 40 bit Parity EDAC 16 inis mandatory generation PROMS 1 Only word write __ BUFFEN MEMWR OE and 8 bit No parity DDIR
81. ata Bus bidirectional These signals form a 32 bit bidirectional data bus that serves as the interface between the TSC695F and external memory The data bus is not driven by the TSC695F during system registers accesses it is only driven during the execution of integer and floating point store instructions and the store cycle of atomic load store instructions on external memory Store data is valid during the second data cycle of a store single access the second and third data cycle of a store double access and the third data cycle of an atomic load store access Alignment for load and store instructions is performed by the processor Doublewords are aligned on 8 byte boundaries words on 4 byte boundaries and half words on 2 byte boundaries If a doubleword word or half word load or store instruction generates an improperly aligned address a memory address not aligned trap will occur Instruc tions and operands are always expected to reside in a 32 bit wide memory D 31 corresponds to the most significant bit of the most significant byte of a 32 bit word going to or from memory AIMEL TSC695F User Manual B Data Bus Parity bi directional This pin is used by the TSC695F to check and generate the odd parity over the 32 bit data bus during write cycles not D 31 xor D 30 xor xor D 1 xor D O In case of DMA session this signal must be driven by the DMA unit if DMA parity is enabled CB 6 0
82. ate 4148G Reference release 07 2002 4148H Section 3 6 7 Traps 12 2003 Improvement of Comments on Table 3 4 Improvement of Priority specification Addition of SYSFSR update information Addition of FAILAR update information Section 4 11 Configuration Registers SYFSR register description AIMEL TSC695F User Manual AIMEL NENNEN Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Atmel Operations Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 La Chantrerie BP 70602 44306 Nantes Cedex 3 France Tel 33 2 40 18 18 18 Fax 33 2 40 18 19 60 ASIC ASSP Smart Cards Zone Industrielle 13106 Rousset Cedex France Tel 33 4 42 53 60 00 Fax 33 4 42 53 60 01 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759
83. bit event counter that allows to break onto the 15110 the 255 break condition match B Break point for Program Execution A hardware breakpoint for program execution is defined by an breakpoint address register This register value is compared to the Program Counter at the execution stage of the pipeline When a break occurs the instruction is not executed Figure 3 18 Breakpoint for Program Execution Block Diagram Breakpoint Address Count occurrence Breakpoint Register 8 bit Breakpoint from other decounter breakpoints Address Pipe Clock SYSCLK E Breakpoint for Data Memory A hardware breakpoint for data memory works with the informations of the address data ASI busses t is possible to break onto an address range thanks to two comparison address registers one low limit address register and one high limit address register The break condition on the data is given by a data comparison register and a data mask register The last break condition uses one of the following access type qualifier read write code data user space supervisor space and a qualifier mask register 3 42 AIMEL TSC695F User Manual 4148H AERO 12 03 Figure 3 19 Breakpoint for Data Memory Block Diagram RA 31 0 Enable 3 12 2 Processor Reset 3 12 3 Cycle Counter TSC695F User Manual Breakpoint Up Add se Re Breakpoint Lw Add Mask Data 32 Break Breakpoint Data Break
84. ceiver already contents a non read byte only the oea bit is set not the dra bit The last received byte is lost The oea bit is cleared by the cua bit 0 no error 1 overrun error on the receiver of UART A B pea Parity Error on receiver A pea bit advises a parity error on the receiver of UART A When byte is received with a parity error only the pea bit is set not the dra bit The peabit is cleared by the cua bit 0 no error 1 parity error on the receiver of UART B E fea Frame Error on receiver A fea bit advises a frame error on the receiver of UART A When a byte is received with a frame error only the fea bit is set not the dra bit The fea bit is cleared by the cua bit 0 no error 1 frame error on the receiver of UART A 4 96 AIMEL TSC695F User Manual 4148H AERO 12 03 E thea Transmitter Holding Register Empty on UART A thea bit indicates the transmitter holding register of the UART A is empty It is ready to be reloaded with a new data 0 full 1 empty default E sea Transmitter Send Register Empty on UART A sea bit indicates the transmitter send register of the UART A is empty It has no data to send 0 full 1 empty default E dra Data Ready in UART A dra bit indicates a data has been received by the receiver of the UART A 0 empty default 1 full TSC695F User Manual AIMEL
85. cle instruction actually takes four cycles to complete but they are called single cycle because with this type of instruction the processor can com plete one instruction per cycle after the initial four cycle delay The FPU is designed to provide execution of single and double precision floating point instructions concurrently with execution of integer instructions by the IU The FPU is compliant to the ANSI IEEE 754 1985 floating point standard The FPU is designed for highly dependable space and military applications and includes support for concurrent error detection and testability The FPU uses a four stage instruction pipeline consisting of fetch decode execute and write stages F D E and W The fetch unit captures instructions and their addresses from the data and address buses The decode unit contains logic to decode the floating point instruction opcodes The execution unit handles all instruction execution The exe cution unit includes a floating point queue FP queue which contains stored floating point operate FPop instructions under execution and their addresses The execution unit controls the load unit the store unit and the datapath unit The FPU depends upon the IU to access all addresses and control signals for memory access Floating point loads and stores are executed in conjunction with the IU which provides addresses and control signals while the FPU supplies or stores the data Instruction fetch for integer
86. ction trap See SPARC V7 0 Instruction Set Ticc instruction for details The TSC695F handles 15 asynchronous traps It is possible to mask each individual interrupt except for interrupt 15 watch dog by setting the corresponding bit in the Interrupt Mask Register INTMKR The Interrupt Pending Register INTPDR reflects the pending interrupts It is possible to clear pend ing interrupts by setting the corresponding bit in the Interrupt Clear Register INTCLR AMEL 4148 12 03 The interrupts in the Interrupt Pending Register INTPDR are cleared automatically when the interrupt is acknowledged By programming the Interrupt Shape Register INTSHR it is possible to define the external interrupts to be either active low or active high and to define the external inter rupts to be either edge or level sensitive Also by programming the Interrupt Shape Register INTSHR it is possible to make one of the external interrupts generate a pulse on the EXTINTACK output when the IU acknowledges the interrupt Edge sensitive interrupts will be detected only when a transition occurs Level sensitive interrupts will be detected as long as the interrupt line is asserted When the interrupt line is deasserted the corresponding bit in Interrupt Pending Register INTPDR will be cleared Figure 3 3 Interrupt System Overview The external interrupt input is filtered only if it is active for at least 2 SYSCLK The interrupts in the
87. d to the trap type tt 0x19 0 interrupt not pending 1 interrupt pending E 8 Interrupt Pending on asynchronous INT 8 ip 8 bit reflects a pending interrupt on a DMA access error This interrupt is associated to the trap type tt 0x18 0 interrupt not pending 1 interrupt pending E 0 7 Interrupt Pending on asynchronous INT 7 ip 7 bit reflects a pending interrupt on a UART error This interrupt is associated to the trap type tt 0x17 0 interrupt not pending 1 interrupt pending E 6 Interrupt Pending on asynchronous INT 6 10 6 bit reflects a pending interrupt on a correctable error in memory This interrupt is associated to the trap type tt 0x16 0 interrupt not pending 1 interrupt pending E 5 Interrupt Pending on asynchronous INT 5 ip 5 bit reflects a pending interrupt on either UART B data ready or transmitter ready This interrupt is associated to the trap type tt 0x15 0 interrupt not pending 1 interrupt pending E 0 4 Interrupt Pending on asynchronous INT 4 ip 4 bit reflects a pending interrupt on either UART A data ready or transmitter ready This interrupt is associated to the trap type tt 0x14 0 interrupt not pending 1 interrupt pending E 0 3 Interrupt Pending on asynchronous INT ip 3 bit reflects a pending interrupt on the external interrupt number 1 EXTINT
88. data being transferred during an instruction or a data fetch To save board space these outputs are sent out registered and has the same timing as RA 31 0 Table 5 2 RSIZE Assignments RSIZE 1 RSIZE 0 Data Transfer Type 0 0 Byte 0 1 Half word 16 bits 1 0 Word 82 bits 1 1 Word load store double In the ROM area Boot PROM Extended PROM structured in 8 bit mode the load word or instruction fetch is converted in four read accesses Only store byte stb instruc tion is allowed In the ROM area structured in 40 bit mode byte half word and word read access is allowed but only store word st instruction can be supplied In the Exchange Memory area only word access is allowed Only word access to System Registers is allowed In the RAM area RAM Extended RAM a store subword byte or half word is imple mented as a read modify write word since check bits must be generated over word In spite of this implementation RSIZE 1 0 keeps its initial value Byte or half word read access is allowed Since the I O unit never includes EDAC check bits the store subword half word or byte instruction in the I O area is different from the store subword in the RAM area In the I O area I O area 3 0 I O area a store subword is implemented as a store word from a timing point of view but the subword byte or half word is repeated by the IU on the other subwords in the full word TSC695F User Manual A
89. data requires a single 32 bit f register Double precision data requires 64 bits of storage and occupies an even odd pair of adjacent f registers Table 4 10 System Control Register SYSCTR address 0x 01f8 0000 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 43121 x 77 ws x oc o E o o 9 oc SIG 2 St g us 285 8388 E 56 2 2 2 5 2 2 4 26 eS gc 5 r w r rw r rw 0000 0001 1 0 11 0 1 0 1 x 0 0 0000 4 60 4148H AERO 12 03 AMEL TSC695F User Manual TSC695F User Manual us UARTs Scaler us field fixes the division of both UARTs input clock 0 UARTs stopped 1 up to 255 us ucs UARTs Clock Supply ucs bit enables which clock is used to drive both UARTs 0 UARTs clock external watchdog clock WDCLK 1 UARTs clock system clock SYSCLK default usb UARTS Stop Bit usb bit enables the generation checking of the stop bit slot s on serial link messages for both UARTs 0 1 stop bit 1 2 stop bits up UARTs Parity up bit enables odd or even parity on serial link messages for both UARTS if upe bit is set 0 even parity 1 odd parity default u
90. db field has 2 meanings 1 Awrite access enables the sending of the written 8 bit data on UART B 2 Aread access provides the received 8 bit data on UART B Table 4 40 UART Status Register UARTSR address 0x 01f8 00e8 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 21110 reserved 38 2 2 reserved S cic c 21 5 S ow 0000 a a 2g 2 0000 3 S 2 z i o r r r r r r r r r Ww 0000 0000 01010 0 01 11 11 0 0000 0000 010101011 11 0 TSC695F User Manual E cub Clear Errors on UART cub bit clears the setting errors oeb peb feb on the UART B It is an auto resetable bit bit read as zero 0 action 1 clear errors on UART B E Overrun Error on receiver oeb bit advises an overrun error the receiver of UART B When a byte is received while the receiver already contents a non read byte only the oeb bit is set not the drb bit The last received byte is lost The oeb bit is cleared by the cub bit 0 noerror 1 overrun error on the receiver of UART B B Parity Error on receiver peb bit advises a parity error on the receiver of UART B When a byte is
91. e X 1 xX 0X 3 X 2 1 X 0C 3 X 2 Internal INT A A Timeout Counter x Scaler 1 Figure 3 6 Timer Behavior Example when Scaler 0 Reload mode Scaler 0 Counter 3 SYSCLK AL4 A L4 4 Scaler Tick AL4 A 4 4 4 A LA LA La Lf Counter Value A d Ko X2 X T0 084 9 902 o T 6 D A4 X Internal INT 4 Counter 1 Counter 1 Timeout gg ig 2 MH 3 28 AIMEL TSC695F User Manual 4148H AERO 12 03 Figure 3 7 Timer Behavior Example when Counter 0 Initialization of Reload mode Scaler 1 Counter 0 ATELELETELETETAELETATETA Scaler Tick A A A 4 A A Counter Value xx X0 reloading with 0 Internal INT Only INT located during the loading if previous value 0 load and start command 2 after reset counter value OXFFFFFFFF 3 6 8 2 Real time Clock The only functional differences between the two timers are that the Real time Clock Timer Timer RTCT has an 8 bit scaler 16 bit scaler for GPT and that the RTCT interrupt has higher priority than the GPT interrupt RTCT information is available on RTC output pin during 1 5 SYSCLK period Figure 3 8 RTCT Implementation t RTC EE output pin SYSCLK 8 bit Scaler 32 bit Counte
92. e bus ready signal is deasserted the start of the access is put on hold Once the BUS RDY signal is asserted again the access will start with the programmed number of waitstates and finish with two cycles On I O area accesses the processor will provide the programmed number of waitstates after the first two cycles of the access Then the processor will sense the bus ready sig nal BUSRDY If the bus ready signal is deasserted the access is put on hold Once the BUSRDY signal is asserted again the TSC695F will continue with two cycles A bus timeout function of 256 system clock cycles is provided for the bus ready con trolled memory areas i e the Extended PROM Exchange Memory Extended RAM Extended I O and the Extended General areas The btobit of System Control Register is used to select this function The default after system reset is that the bus timeout func tion is enabled The bus timeout counter will start when the access is initiated If the BUSRDY signal is not asserted before a valid number of system clock cycles a memory exception will occur The TSC695F includes a 32 bit EDAC Error Detection And Correction Seven bits CB 6 0 are used as check bits over the data bus The Data Bus Parity signal DPAR is used to check and generate the odd parity over the 32 bit data bus This means that altogether 40 bits are used when the EDAC is enabled AMEL 4148H AERO 12 03 The TSC695F EDAC uses a seven bit Hamming cod
93. e which detects any double bit error on the 40 bit bus as a non correctable error In addition the EDAC detects all bits stuck at one and stuck at zero failure for any nibble in the data word as a non correctable error Stuck at one and stuck at zero for all 32 bits of the data word is also detected as a non correctable error The EDAC corrects any single bit data error on the 40 bit bus However in order to cor rect any error in memory e g Single Event Upset induced the data has to be read and re written by software as the TSC695F does not automatically write back the corrected data Figure 3 1 EDAC System Overview RA 31 0 D 3 1 0 DPAR CB 6 0 NOPAR uncorrectable cb 6 0 et correctable coo et error TEST CONTROL Reg Interrupt Request Level Interrupt Controller 3 6 5 Memory and I O The TSC695F handles parity towards memory and I O in a special way The processor Parity can be programmed to use no parity only parity or parity and EDAC protection towards memory and to use parity or no towards I O The signal used for the parity bit is DPAR This pin is used to check and generate the odd parity over the 32 bit data bus according to the following table 3 14 AIMEL TSC695F User Manual 4148H AERO 12 03 When a correctable error occurs in the RAM or exchange memory parity is generated even if parity is disabled Table 3 3 DPAR and NOPAR Handling See Figure 3 1
94. eation of a pro cessor that can execute instructions at a rate approaching one instruction per processor clock To achieve that rate of execution the employs a four stage instruction pipeline that permits parallel execution of multiple instructions B Fetch The processor outputs the instruction address to fetch the instruction B Decode The instruction is placed in the instruction register and is decoded The processor reads the operands from the register file and computes the next instruction address B Execute The processor executes the instruction and saves the results in temporary registers Pending traps are prioritized and internal traps are taken during this stage B Write If no trap is taken the processor writes the result to the destination register All four stages operate in parallel working on up to four different instructions at a time A basic single cycle instruction enters the pipeline and completes in four cycles By the time it reaches the write stage three more instructions have entered and are moving through the pipeline behind it So after the first four cycles a single cycle instruction exits the pipeline and a single cycle instruction enters the pipeline on every 3 9 Rev 4148H AERO 12 03 3 3 3 4 3 5 3 6 3 6 1 3 10 Floating point Unit Co processor Unit Instruction Set On chip Peripherals Memory Mapping 4148H AERO 12 03 cycle Of course a single cy
95. eeded for single cycle execution B Same length instructions Each instruction is the same length so that it may be fetched in a single operation B Reduced memory access Only load and store instructions access memory There are no computational instructions that access memory Load store instructions operate between memory and a register This simplifies control hardware and minimizes the machine cycle time E Small number of addressing modes The instruction set uses only short displacement long displacement and indexed modes to access memory B 1 machine cycle instructions Most instructions complete one machine cycle which allows the processor to handle several instructions at the same time This pipelining is a key technique used to speed up RISC machines B Pipelining Pipelining is a design technique where the computer s hardware processes more than one instruction at a time and doesn t wait for one instruction to complete before starting the next The four stages are fetch decode execute and write The stages are executed in parallel As soon as one stage completes it passes on the result to the next stage and then begins working on another instruction Pipelining doesn t improve the latency of instructions each instruction still requires the same amount of time to complete but it does improve the overall throughput 2 7 Rev 4148H AERO 12 03 2 2 1 The Advantages of RISC 2 3 The SPARC Architectu
96. een TDI and TDO A single scan chain consisting of all of the scan cells of IU user s registers In the On chip Debugger environment the IU scan allows an internal access to the fol lowing IU user s registers B psr tbr wim windowed registers 128 g0 up g7 00 always 0000 0000 buried program counter registers Fetch Decode Execute and Write PC i e pc Note All windowed registers be read or written by the OCD even if theses regis ters are not in the current window A MEL 3 39 4148 12 03 3 11 6 Scan Register 3 11 7 System Scan Register 3 40 4148H AERO 12 03 IU Scan register is connected between TDI and TDO A single scan chain consisting of all of the scan cells of FPU registers In the On chip Debugger environment the FPU scan allows an internal access to the following PPU user s registers B fsr E ofpQueue f0 up to f31 FPU Scan register is connected between TDI and TDO A single scan chain consisting of all of the scan cells of System registers In the On chip Debugger environment the System scan allows an internal access to the following System user s registers B System Control Register B Software Reset Register B Power down Register B Memory Configuration Register E O Configuration Register B Waitstate Configuration Register Access Protection Segment 1 Base Register Access Protection Segment 1 End Regist
97. eld enables traps caused by FPops These bits are ANDed with the bits of the cexc current exception field to determine whether to force a floating point exception to IU All trap enable fields correspond to the similarly named bit in the cexc field 0 trap disabled 1 trap enabled nvm invalid Operation Trap Mask ofm Overflow Trap Mask ufm Underflow Trap Mask dzm Division by zero Trap Mask nxm iNexact Trap Mask ns Non Standard floating point IEEE mode bit always set to 0 E ver Version The current version number for the TSC695F FPU is 100 ftt Floating point Trap Type ftt field identifies the floating point trap type of the current floating point exception 0 000 none 1 001 IEEE exception invalid operation gt overflow AMEL 4148 12 03 4 58 4148H AERO 12 03 underflow gt division by zero gt inexact 2 010 unfinished FPop Operations on normalized floating point numbers either encounter a denormalized operand or produce a denormalized result 3 011 unimplemented FPop This exception is asserted upon encountering a defined SPARC FPop instruction that is not supported by the TSC695F This includes all operations using extended precision format operands 4 100 sequence error This exception is asserted when a floating point instruction other than FP store is attempted af
98. en performed including setting the tt field to reflect the cause of the error mode Because this field is not changed by the reset trap a post mortem can be conducted on what caused the error mode The processor enters error mode AMEL TSC695F User Manual TSC695F User Manual whenever a synchronous trap occurs while traps are disabled B Hardware error When a hardware error is detected the trap handling routine saves the error information sampled in the Error and Reset Status Register The trap routine then resumes the instruction by returning from the trap routine If the cause of the error was a transient fault it may be removed by just resuming the instruction If the error was caused by a fault that is not removable by resuming the instruction another hardware error trap is generated and the trap handling routine propagates the error to a higher level of the application If the fault is in a critical register or latch which the trap handling routine uses another hardware error trap is generated A synchronous trap during the time when traps are disabled is a critical error and the TSC695F enters the error mode and halts This means that the error detection mechanism has to detect the error when the faulty instruction is in the execute stage in order to handle the trap normally i e correct PC for the faulty instruction E Instruction access An instruction access exception trap is generated if a memory exception occurs
99. enerated internally 1 40 bit wide EDAC and parity B pwr PROM Write Function pwr bit only enables the state of ROMWRT ROMWRT input pin 0 function disabled 1 function enabled if external ROMWRT present rec RAM EDAC Protected rec bit enables an EDAC protection on the RAM and Extended RAM spaces If rec is set automatically a parity protection is done regardless the rpa bit value 0 EDAC protection disabled 1 EDAC protection enabled B rpa RAM Parity Protected rpa bit only enables an parity protection on the RAM and Extended RAM spaces If rec is set the rpa bit value is don t care If NOPAR pin is tied to ground setting rpa bit has no effect 0 parity protection disabled 1 parity protection enabled E rsiz RAM Size rsiz field fixes the RAM size only in the RAM space regardless the number of banks rsiz Size rsiz Size 000 256 Kbytes 100 4 Mbytes 001 512 Kbytes 101 8 Mbytes 010 1 Mbytes 110 16 Mbytes 011 2 Mbyte 111 32 Mbytes E rbri Redundant RAM Block 1 Replace rbr1 field fixes the replacement of any RAM block by the RAM block 1 The MEMCS x MEMCS x signal corresponding to the replaced block will be 4 70 AIMEL TSC695F User Manual 4148H AERO 12 03 inactive and MEMCS 9 signal will be active instead If rorO and rbr1 are set to the same value rbr1 setting will have no effect rbr
100. eption mode The FPU remains in pending exception mode until the FPU encounters another floating point instruction then the FPU enters exception mode In exception mode floating point execution halts until the FP queue is emptied This allows the FPU to store the floating point instructions under execution when the excep tion case occurred Emptying the FP queue frees the FPU for use by the trap handler without losing the pre exception state The FP queue contains the 32 bit address and 32 bit FPop instruction of one instruction under execution Floating point load and store instructions and FP branch instructions are not queued The entry of the FP queue is accessible by executing the store double AMEL 4148H AERO 12 03 49 FPU f Registers Table 4 9 FPU f Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 1211 10 9 8 7 65 4 3 211 floating point queue STDFQ instruction A load FP queue instruction does not exist as the FP queue must be loaded by launching instructions fo f1 f 30 f 31 r w X 4 10 System Registers 4 10 1 System Management Registers The FPU provides 32 registers for floating point operations referred to as f registers These registers are 32 bits in length which can be concatenated to support 64 bit dou ble words Extended precision instructions are not supported in the TSC695F FPU Integer and single precision
101. er Access Protection Segment 2 Base Register B Access Protection Segment 2 End Register B Interrupt Shape Register E Interrupt Pending Register B Interrupt Mask Register B interrupt Clear Register E interrupt Force Register E Watchdog Program and Timeout Acknowledge Register B Watchdog Trap Door Set B Real time Clock Timer Counter B Real time Clock Timer Program Register Counter B Real time Clock Timer lt Scaler gt B Real time Clock Timer Program Register Scaler B General purpose Timer Counter B General purpose Timer Program Register Counter B General purpose Timer lt Scaler gt B General purpose Timer Program Register lt Scaler gt AIMEL TSC695F User Manual 3 11 8 Scan Register 3 11 9 OCD Control and Status Register TSC695F User Manual B Timer Control Register B System Fault Status Register B Failing Address Register E Error and Reset Status Register B Test Control Register B UART A Rx and Tx Register B UART B Rx and Tx Register B UART Status Register B GPI Direction Register B GPI Status Register To each user s register one parity bits is associated Note Read only user s registers can be read or written System Scan register is connected between TDI and TDO A single scan chain consisting of all of the scan cells of OCD breakpoint and cycle counter registers In the On chip Debugger environment the OCD scan allows the only access to the fol lowing OCD re
102. er and carries positive overflows to Underflow fsr s cexc field 0010x The TSC695F s FPU asserts an underflow exception when the rounded result is inexact and would be smaller in magnitude than the smallest normalized number in the specified format E inexact fsr s cexc field 0xx01 The inexact exception is generated whenever there is loss of accuracy or significance the result The TSC695F s FPU computes results to higher precision than the number of fraction bits in the format If any of the fraction bits to the right of the LSB was one prior to rounding the inexact exception is signaled B Unfinished FPop The TSC695F s FPU never asserts this exception since all implemented instructions are executed within hardware Data access exception A data access exception trap is generated if a parity error uncorrectable EDAC error access violation bus timeout or system bus error is detected MEXC signal is asserted during the data cycle of any instruction that moves data to or from memory Tag overflow This trap occurs if execution of a TADDccTV or TSUBccTV instruction causes the overflow bit of the integer condition codes to be set See the instruction definitions of TADDccTV and TSUBccTV for details Trap instructions This trap occurs when a Ticc instruction is executed and the trap conditions are met There are 128 programmable trap types available within the trap instru
103. er Manual 4148H AERO 12 03 io rw field fixes the number of waitstates in the I O Area 1 space The TSC695F always inserts a minimum of 1 waitstate to wait for BUSRDY BUSRDY signal even 0 waitstates is programmed 1 Waitstate Read or Write Cycle 0000 0 ws 3 SYSCLK periods 0001 1 ws 3 SYSCLK periods XXXX n ws 2 n SYSCLK periods 1111 15 ws 17 SYSCLK periods E joOrw Area 0 nbr of Read Write Waitstates ioOrw field fixes the number of waitstates in the I O Area 0 space The TSC695F inserts a minimum of 1 waitstate to wait for BUSRDY BUSRDY signal ioOrw Waitstate Read or Write Cycle 0000 0 3 SYSCLK periods 0001 1 3 SYSCLK periods XXXX n 2 n SYSCLK periods 1111 15 17 SYSCLK periods B exrw EXchange Memory nbr of Read Write Waitstates exrw field fixes the number of waitstates the Exchange Memory space TSC695F always inserts 2 waitstates to wait for BUSRDY BUSRDY signal exrw Waitstate Read Cycle Write Cycle 0000 0 3 SYSCLK periods 4 SYSCLK periods 0001 1 4 SYSCLK periods 5 SYSCLK periods Xxxx n 8n SYSCLK periods 4 SYSCLK periods 1111 15 18 periods 19 SYSCLK periods B prw PROM Boot nbr of Write Waitstates prw field fixes the number of waitstates in the PROM Boot space during write cycles The TSC695F always inserts a minimum of 1 waitstate to wa
104. er changes because the registers and return address do not need to be stored on a stack The RETURN instruction acts in the opposite way AIMEL TSC695F User Manual AIMEL 3 1 Concept 3 2 Integer Unit TSC695F User Manual Section 3 Product Description The objective of the TSC695F is to provide a high performance 32 bit embedded pro cessor with which computers for on board embedded real time applications can be built The component will be characterized by low circuit complexity and power con sumption Extensive concurrent error detection and support for fault tolerance and reconsideration will also be emphasized In addition to the main objective the TSC695F should be used for performance demanding research applications in deep space probes The radiation tolerance and error masking are therefore important For the real time applications the system might be fail operational rather than fail safe By including support for reconfiguration of the error handling the different demands from the applica tions can be optimized for the best purpose in each case The TSC695F will be used as a building block only requiring memory and application specific peripherals to be added to form a complete on board computer All other system support functions are provided by the TSC695F The IU is designed for highly dependable space and military applications and includes support for error detection The RISC architecture makes possible the cr
105. flow or underflow trap prevents previ ous windows from being overwritten or restores previous windows from memory WIM can also be used to mark off register banks for fast context switching WIM is read by the RDWIM instruction and written by the WRWIM instruction Table 4 4 Trap Base Register TBR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 413 12 1 trap base address tba trap type tt 901010 r w r x 0000 4 5 Y Register Table 4 5 Y Register Y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 76 5 4 312 1 0 When a trap occurs the program counter PC is loaded with the contents of the trap base register The TBR contains two fields that together constitute a pointer into the trap table which in turn contains the trap handler address RDTBR can read the entire regis ter however the WRTBR instruction can write only to the Trap Base Address field The Trap Type field can be directly manipulated using the Ticc instruction E tba Trap Base Address tba field contains the most significant 20 bits of the trap table address This field applies to all trap types except reset which forces address 0 The tba is software controlled B tt Trap Type tt field comprises the Trap Type field an eight bit value that provides an offset into the trap table based on the type of
106. gister SYSCTR must be programmed prior to entering power down mode DMA accesses are allowed during power down mode The TSC695F leaves the power down mode if an external interrupt is asserted Error Halt mode is entered under the following circumstances Ainternal hardware parity error IU enters error mode In Error Halt mode the CPUHALT and SYSERR outputs are asserted note that SYSERR is also asserted if a masked error occurs even though Error Halt mode is not entered in this case All timers are halted and the UART operation is stopped in this mode The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET The TSC695F allows DMA accesses during error halt mode The TSC695F has one error output signal SYSERR which indicates that an unmasked error has occurred Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register ERRRSR It is possible to program an error mask in the System Control Register SYSCTR for each type of error excepted for FPU in order to determine whether the specific error shall lead to the pro cessor ignoring the error or asserting a processor halt or processor reset programming the System Control Register SYSCTR As default an error leads to a processor halt All unmasked errors asserts the SYSERR pin and this pin is asserted until all the unmasked error bits in the Error and Reset Status Register E
107. gister INTFCR 0 interrupt force disable 1 interrupt force enable B pt Parity Test Mode pt bit allows fault injection for parity test purposes By enabling parity test mode wrong parity will be generated when any System Register is read 0 test mode disabled 1 test mode enabled E et EDAC Test Mode etbit allows fault injection for memory test purposes and also test of the EDAC function itself By enabling EDAC test mode the bits in the cb field of this Register will substitute the normal checkbits during following store cycles 0 test mode disabled 1 test mode enabled E cb Checks Bits for Test Mode AIMEL TSC695F User Manual cb field allows fault injection for memory and EDAC test purposes if et bit is set 4 11 Configuration Registers Table 4 17 Memory Configuration Register MCNFR address 0x 01f8 0010 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 41312 110 a hel ala reserved gt 2198 esiz 000 psiz o amp rsiz rbri 8 8 rbcs 7 r r w rw r r w r r r w r w r w r w r w 00 01010 000 000 000 110 000 000 0 000 0 00 Enable Exchange Memory eex bit
108. gnal configuration as described in Figure 3 14 This configuration contains three broadcast signals TMS TCK and TRST which are fed from the JTAG master to all JTAG slaves in parallel and a serial path formed by a daisy chain connection of the serial test data pins TDI and TDO of all slaves The TAP supports a BYPASS instruction which places a minimum shift path 1 bit between the chip s TDI and TDO pins This allows efficient access to any single chip in the daisy chain without board level multiplexing Figure 3 14 JTAG Serial Connection Using 1 TMS Signal TSC695F User Manual A MEL Part 1 Part 2 Part 3 Part TDI TOS TMS 7 l l TRST 3 35 4148H AERO 12 03 3 8 3 TAP Architecture The TAP implemented in the TSC695F consists of a TAP interface a TAP controller plus a number of shift registers including an instruction register IR and multiple data registers DR Figure 3 15 JTAG TSC695F TAP Architecture IU Scan Register FPU Scan Register ystem Scan Register Checkers Scan Register OCD Ctrl Stat Register OCD Scan Register o Devi ist V TDI evice egister EN Data Registers TAP Update DR _ is euis TRST Controller Update IR Instruction Register Select TDO Design Specific Data 3 9 TAP Controlle
109. he data cycles the load cycle and both store cycles of atomic load store instructions To save board space LDSTO is sent out registered In case of DMA session this signal must be driven unlatched by the DMA unit B ALE ALE Address Latch Enable output This output is asserted when the internal address bus from the IU is to be latched This latch operation is assumed by the internal latch In case of DMA session this signal is intended to be used to enable the clock input SYSCLK of an external flip flop used to latch the generated address from DMA unit B DXFER Data Transfer output input DXFER is used to differentiate between the addresses being sent out for instruction fetches and the addresses of data fetches DXFER is asserted by the processor during the address cycles of all bus data transfer cycles including both cycles of store single and all three cycles of store double and atomic load store DXFER is sent out unregis tered and must be latched externally before it is used AMEL En 4148H AERO 12 03 5 102 4148H AERO 12 03 A DMA unit must supply this signal during a DMA session B OCK Bus Lock output input LOCK is asserted by the processor when it needs to retain control of the bus address and data for multiple cycle transactions Load Double Store Single and Double Atomic Load Store The bus will not be granted to another bus master as long as LOCK is asserted Note that MHOLD MHOLD when
110. hecking if a character may be written to the Rx and Tx register Then the byte to be output is written in the Rx and Tx register UARTAR and UARTBR The byte written will then automatically be transferred to the transmitter send register and converted to serial form also adding start bit parity bit and stop bit s The above described sequence can be part of a trap han dler for the UART interrupt A correctly received byte is indicated by the Data Ready bit dra or drb in the UART sta tus register UARTSR In case of error framing error stop bit error parity error or overrun error the respective bits fe pe and oe are set in the UART status register UARTSR but not dra or drb bit The UARTs generate an interrupt each time a byte has been received or a byte has been sent There is another interrupt to indicate errors but this interrupt is common for both UART channels The UART uses an internal clock which is 16 times faster than the baud rate and sam ples each bit 16 times to ensure error free reception The clock is derived either from the system clock SYSCLK or can use the watchdog clock WDCLK This is done by AMEL 4148H AERO 12 03 3 6 10 General purpose Interface programming ucs bit in System Control Register SYSCTR If WDCLK input is chosen its frequency must be at least 3 times less than SYSCLK frequency The external UART interfaces consist of transmit data output TxA and TxB and receive data input
111. ication 0 x Division 0 0 or Square root if the operand is less than zero Conversion of a binary floating point number to an integer or decimal format when overflow infinity or NaN precludes a faithful representation in that format and this cannot otherwise be signaled AIMEL TSC695F User Manual 3 6 7 2 Interrupts or Asynchronous Traps TSC695F User Manual Floating point compare operations when one or more of the operands are NaN B Division by zero fsr s cexc field 00010 If the divisor is zero and the dividend is a finite nonzero number then the division by zero exception shall be signaled The result when no trap occurs shall be a correctly signed co E Overflow fsr s cexc field 0100x The exceeded in magnitude by what would have been the rounded floating point result were the exponent range unbounded The result when no trap occurs shall be determined by the rounding mode and the sign of the intermediate result as follows Round to nearest carries all overflows to co with the sign of the intermediate result Round toward 0 carries all overflows to the format s largest finite number with the sign of the intermediate result Round toward oe carries positive overflows to the format s largest positive finite number and carries negative overflows to eo Round toward carries negative overflows to the formats most negative finite numb
112. if 8 bit forces the interrupt a DMA access error test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced if 7 Interrupt Force on asynchronous INT 7 if 7 bit forces the interrupt on UART error in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced if 6 Interrupt Force on asynchronous INT 6 if 6 bit forces the interrupt on a correctable error in memory in test mode bit itof TESCTR 0 interrupt not forced 1 interrupt forced if 5 Interrupt Force on asynchronous INT 5 if 5 bit forces the interrupt on either UART data ready or transmitter ready in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced 4 Interrupt Force on asynchronous INT 4 if A bit forces the interrupt on either UART data ready or transmitter ready in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced if 3 Interrupt Force on asynchronous INT if 3 bit forces the external interrupt number 1 EXTINT 1 pin in test mode bit it of TESCTR TSC695F User Manual 4 14 Timer Registers 0 interrupt not forced 1 interrupt forced E 21 Interrupt Force on asynchronous INT 2 if 2 bit forces the external interrupt number 0 EXTINT 0 pin in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced E 1
113. ing Capture DR on the rising edge of TCK It allows also to preload a value on the output latches during Update DR on falling edge of TCK It do not modify system behavior 3 10 3 Defined Optional E INTEST instruction binary coded 00 0011 Instructions Used to achieve testing of on chip logic on the board Data are shifted through boundary scan register and applied to logic inputs during Update DR Outputs are sampled into the boundary scan register during Capture DR B IDCODE instruction binary coded 10 0000 Value of the IDCODE is loaded during Capture DR 3 10 4 Owner Instructions B CCTEST instruction binary coded 01 1000 Itis a factory test to verify parity checkers in IU internal block B IUTEST instruction binary coded 01 1100 Used to access to the User s IU Register B FPUTEST instruction binary coded 01 1101 Used to access to the User s FPU Register B SYSTEST instruction binary coded 01 1110 Used to access to the User s System Register B OCDTEST instruction binary coded 01 1010 Used to access to the OCD resources as hardware break points and cycle counter B CTSTEST instruction binary coded 01 1001 Used to access to OCD control and status bits 3 38 AIMEL TSC695F User Manual 4148H AERO 12 03 3 11 Test Data Registers 3 11 1 Bypass Register 3 11 2 Device ID Register The following data registers are supported in the TSC695F TAP Bypass reg
114. ip Selects rbcs field enables the number of RAM block chip selects The selected RAM size rsiz field must be divide into 1 2 4 or 8 equally sized RAM blocks rbcs Function rbcs Function 00 MEMCS 0 active 10 MEMCS 3 0 active 01 MEMCS 1 0 active 11 MEMCSJ7 0 active TSC695F User Manual AIMEL 4 71 4148 12 03 Table 4 18 Configuration Register IOCNFR address 0x 01f8 0014 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7615 41312 1 0 Sema i Bs lala Anp i Sess i S 8 9 siz3 5122 5121 S 8 9 5120 r rw r r w r r w r r w 00 010 000 00 0 0 000 00 010 000 00 0 0 000 B Area Parity Protected pa3 bit only enables an parity protection on the I O Area 3 space If NOPAR NOPAR pin is tied to ground setting bit has no effect 0 parity protection disabled 1 parity protection enabled TSC695F checks parity E 03 I O Area 3 Enable 103 bit enables the I O Area space from at 1300 0000 0 disable 1 enable E siz3 I O Area Size Siz3 field fixes the size in the I O Area space siz3 Size siz3 Size siz3 Size siz3 Size
115. is holding reflects the internal signal Memory Hold It is sent out unregistered and must be latched externally before it is used A DMA unit must supply this signal during a DMA session asserted low for write and deasserted high for read accesses B WRT Advanced Write output input WRT is an early write signal asserted by the processor during the first store address cycle of integer single or double store instructions the first store address cycle of float ing point single or double store instructions and the second load store address cycle of atomic load store instructions WRT is sent out unregistered and must be latched exter nally before it is used A DMA unit must supply this signal during a DMA session deasserted low for read and asserted high for write accesses MHOLD Memory Bus Hold output This signal is asserted when a Memory Hold MHOLD or a Floating point Hold FHOLD or a Floating point Condition Codes Valid FCCV or a Bus Hold BHOLD is internally generated Note that MHOLD must be driven HIGH while RESET RESET is LOW Memory Hold Memory Hold is used to freeze the pipeline to both the IU and FPU accessing a slow memory or during memory exception The IU and FPU internal outputs return to and stay at the value they had on the rising edge of SYSCLK in the cycle in which AIMEL TSC695F User Manual TSC695F User Manual Memory Hold wa
116. ister containing a single shift register stage is connected between TDI and TDO ID register is a read only 32 bit register Figure 3 17 TSC695F ID Register Contents 31 28 27 12 11 1 0 Part ID Manufacturer s ID 0000 1011 0110 0100 0100 0000 1011 000 1 3 11 3 Boundary Scan Register 3 11 4 Checkers Scan Register 3 11 5 IU Scan Register TSC695F User Manual E ID register value Ox 0064 4001 B Field Definitions 31 28 Vers Version number 0x 0 27 12 Part ID Represent part number as assigned by Vendor 0x b644 11 01 Manufacturer s ID Represent manufacturer s ID as per 058 0 Const Constant tied to logic 717 Device ID register is connected between TDI and TDO A single scan chain consisting of all of the boundary scan cells input output and in out cells excepted TAP interface pins B The initial purpose of the boundary scan is the support of scan based board testing B in the On chip Debugger environment the boundary scan allows an external memory access memory controlled by the TSC695F This access type can be used for program download or patch data area initialization data area dump and I O control Boundary scan register is connected between TDI and TDO A single scan chain consisting of all of the scan cells of IU parity checkers The checkers scan is only used for factory test Checkers scan register is connected betw
117. it for BUSRDY BUSRDY signal even 0 ws is programmed TSC695F User Manual AIMEL 4 75 4148 12 03 4 76 4148H AERO 12 03 PROM 8 bit configuration prw Waitstate Write Byte Cycle 0000 0 3 SYSCLK periods 0001 1 3 SYSCLK periods XXXX n 2 n SYSCLK periods 1111 15 17 SYSCLK periods Note If PROM8 PROM8 is asserted PROM Boot 8 bit only store byte is available PROM 40 bit configuration prw Waitstate Write Word Cycle 0000 0 3 SYSCLK periods 0001 1 3 SYSCLK periods XXXX n 2 n SYSCLK periods 1111 15 17 SYSCLK periods Note If PROM8 PROMB is deasserted PROM Boot 40 bit only store word or store dou ble word is available B prr PROM Boot nbr of Read Waitstates prr field fixes the number of waitstates in PROM Boot space during read cycles The TSC695F always inserts a minimum of 1 waitstate to wait for BUSRDY BUSRDY signal even 0 ws is programmed PROM 8 bit configuration prr Waitstate Read cycle 0000 0 6 SYSCLK periods 0001 1 6 SYSCLK periods XXXX n 2 4 n SYSCLK periods 1111 15 62 SYSCLK periods Note If PROM8 PROM8 is asserted PROM Boot 8 bit always a load access byte half word or word or a fetch to PROM Boot will be performed in 4 byte fetches to create 1 word PROM 40 bit configuration prr Waitstate Read Cycle
118. ither UART B data ready or transmitter ready 0 interrupt not masked 1 interrupt masked default E 1 4 Interrupt Mask on asynchronous INT 4 im 4 bit masks the interrupt on either UART A data ready or transmitter ready 0 interrupt not masked 1 interrupt masked default jm 3 Interrupt Mask on asynchronous INT im 3 bit masks the external interrupt number 1 EXTINT 1 pin 0 interrupt not masked 1 interrupt masked default E jm 2 Interrupt Mask on asynchronous INT 2 im 2 bit masks the external interrupt number 0 EXTINT 0 pin 0 interrupt not masked 1 interrupt masked default E jm 1 Interrupt Mask on asynchronous INT 1 im 1 bit masks the interrupt on masked hardware errors 0 interrupt not masked 1 interrupt masked default 4 84 AIMEL TSC695F User Manual 4148H AERO 12 03 Table 4 27 Interrupt Clear Register INTCLR address 0x 01f8 0050 Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 615141312110 5 o 2 o k 22 8 lZizis g reserved 0000 0000 0000 0000 lt 2 5 5 s zu Sl wij wi 5 S 5 6 ic w 0000 0000 0
119. m This RESET output has a minimum of 1024 SYCLK width to allow the usage of flash memories After the assertion of SYSRES the processor starts in the reset mode resetting all System registers Reset mode is also entered when the RESET output is asserted from any other reason than SYSRES Software reset which is caused by the software writing to a Software Reset Register OCD reset Watchdog reset which is caused by a Watchdog reset timeout Error reset which is caused by a hardware parity error or an IU error mode Error and Reset Status Register contains the source of the last processor reset OCD reset is seen as SYSRES assertion In this mode the IU FPU is executing all peripherals are running if software enabled AIMEL TSC695F User Manual 3 6 11 3 System Halt Mode 3 6 11 4 Power down Mode 3 6 11 5 Error Halt Mode 3 6 12 Error Handler TSC695F User Manual System Halt mode is entered when the SYSHALT input is asserted The CPUHALT out put is asserted freezing IU FPU execution All timers are halted and the UART operation is stopped When SYSHALT is deasserted the previous mode is entered DMA accesses are allowed during system halt mode in which DMA has permanent access to the system i e DMAGNT is asserted immediately on DMAREQ This mode is entered by writing to the Power down Register PDOWN Then the bus arbiter removes the bus ownership from the IU prd bit in the System Control Re
120. nterrupt Pending on asynchronous INT 14 ip 14 bit reflects a pending interrupt on the external interrupt number 4 EXTINT 4 pin This interrupt is associated to the trap type tt Ox1E 0 interrupt not pending 1 interrupt pending E 2 13 Interrupt Pending on asynchronous INT 13 ip 13 bit reflects a pending interrupt on the Real time Clock Timer This interrupt is associated to the trap type tf 0x1D 0 interrupt not pending 1 interrupt pending E 0 12 Interrupt Pending on asynchronous INT 12 ip 12 bit reflects a pending interrupt on the General purpose Timer This interrupt is associated to the trap type tf Ox1C 0 interrupt not pending 1 interrupt pending B 0 11 Interrupt Pending on asynchronous INT 11 ip 11 bit reflects a pending interrupt on the external interrupt number 3 EXTINT 3 pin This interrupt is associated to the trap type tt Ox1B 0 interrupt not pending 1 interrupt pending E 10 Interrupt Pending on asynchronous INT 10 ip 10 bit reflects a pending interrupt on the external interrupt number 2 EXTINT 2 pin This interrupt is associated to the trap type tt Ox1A TSC695F User Manual AIMEL 4 81 4148 12 03 0 interrupt not pending 1 interrupt pending E 9 Interrupt Pending on asynchronous INT 9 ip 9 bit reflects a pending interrupt on a DMA timeout This interrupt is associate
121. out in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced E 14 Interrupt Force on asynchronous INT 14 if 14 bit forces the external interrupt number 4 EXTINT 4 pin in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced E 13 Interrupt Force on asynchronous INT 13 if 13 bit forces the interrupt on the Real time Clock Timer in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced 12 Interrupt Force on asynchronous INT 12 if 12 bit forces the interrupt on the General purpose Timer in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced TSC695F User Manual AIMEL 4 87 4148 12 03 4 88 4148H AERO 12 03 if 11 Interrupt Force on asynchronous INT 11 if 11 bit forces the external interrupt number 3 EXTINT 3 pin test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced if 10 Interrupt Force on asynchronous INT 10 if 10 bit forces the external interrupt number 2 EXTINT 2 pin in test mode bit itof TESCTR 0 interrupt not forced 1 interrupt forced if 9 Interrupt Force on asynchronous INT 9 if 9 bit forces the interrupt on a DMA timeout in test mode bit it of TESCTR 0 interrupt not forced 1 interrupt forced if 8 Interrupt Force on asynchronous INT 8
122. pe UARTs Parity Enable bit enables parity on serial link messages for both UARTs 0 serial link parity disabled 1 serial link parity enabled default ubr UARTs Baud Rate ubr bit adds an 1 bit prescaler in front of the input clock for both UARTs 0 UARTS clock system clock SYSCLK or external clock WDCLK with prescaler divide by 2 1 UARTs clock system clock SYSCLK or external clock WDCLK no prescaler dst DMA Session Timeout dst bit enables a DMA session timeout function preventing the DMA unit to lockout the processor by asserting DMAREQ for more than 1024 system clock cycles after the assertion of DMAGNT Then a memory exception is asserted and the DMAGNT is removed 0 session timeout disabled 1 DMA session timeout enabled default dpe DMA Parity Enable dpe bit enables parity checking during DMA write accesses 0 DMA parity disabled 1 DMA parity enabled AMEL 4148 12 03 B dmae DMA Enable dmae bit enables DMA accesses 0 DMA access disabled 1 DMA access enabled default E iwde Internal Watchdog Enable iwde bit is the direct image of IWDE pin 0 IWDE pin low EWDINT pin used 1 IWDE pin high internal Watchdog active E rhsyshe Reset or Halt when System Hardware Error rhsyshe bit enables a reset or an halt action when the system detects an hardware error enabled by syshemsk bit
123. point Access Count point occurrence Register 32 5 BD DA N O O 31 0 dWE Breakpoint D from other breakpoints Table 3 8 Breakpoint for Data Memory Access Types 8 bit decounter Clock SYSCLK Size Bit Position Bit Value Function 2 Write access bit 0 WE signal Read access User access bit 1 RASI 0 5 1 Supervisor access 0 Instruction access bit 2 RASI 1 Data access bit 4 3 RASI 4 3 Must remain at 10 Figure 3 20 Breakpoint for Data Memory Masks Mask Type Size Function A bit to 0 indicates the associated data or access bit is compared A bit to 1 indicates the associated data or access bit is ignored during the comparison bit 0 Mask bit for D 0 Mask Data bit 32 Mask bit for D 32 bit 0 Mask bit for read or write access Mask Access 5 bit 4 1 Mask bit for RASI 3 0 The JTAG on chip emulator can reset the microprocessor This reset is the same reset that occurs when asserting the Reset input signal The internal register CYC_CNT only accessed under OCD mode gives the number of elapsed clock cycles between a Run and an Freeze An associated 24 bit counter allows to measure elapse time up to 840ms at 20 MHz CYC_CNT register can be reset or held between during a Freeze phase AMEL 3 43 4148H AERO 12 03 3 124 Freeze R
124. pose timer N N External INT 3 N N External INT 2 N N DMA timeout U N DMA access error U U UART Error U N Correctable memory error U U UARTB N N UARTA N N External INT 1 N N External INT 0 N N Masked hardware errors N N Note U means that the register is updated N means that the register is not updated The fault valid bits are reset by writing any value to the SYSFSR register The register is set to the value 0x00000078 reset value E Reset The reset trap is a special case of the external asynchronous trap type It is asynchronous because it is triggered by asserting the RESET input signal But from that point on its behavior is entirely different from that of an asynchronous interrupt As soon as the IU recognizes the RESET signal it enters reset mode Reset Mode and stays there until the RESET line is deasserted The processor then enters execute mode and then the execute trap procedure Here it deviates from the normal action of a trap by modifying the enable traps bit et 0 and the supervisor bit s 1 It then sets the PC to 0 rather than changing the contents of the TBR the nPC to 4 and transfers control to location 0 All other PSR fields and all other registers retain their values from the last execute mode upon power up reset the state of all registers other than the PSR are undefined If the processor got to reset mode from error mode then the normal actions of a trap have already be
125. r APS2ER 0x 01F8 002C All R Supervisor W Interrupt Shape Register INTSHR Ox 01F8 0044 All R Supervisor W Interrupt Pending Register INTPDR 0x 01F8 0048 AIl R Interrupt Mask Register INTMKR Ox 01F8 004C All R Supervisor W Interrupt Clear Register INTCLR 0x 01F8 0050 Supervisor W Interrupt Force Register INTFCR 0x 01F8 0054 All R Supervisor W Watchdog Timer Register WDOGTR Ox 01F8 0060 All R Supervisor W Watchdog Timer Trap Door Set WDOGST 0x 01F8 0064 Supervisor W Real time Clock Timer lt Counter gt Register RTCCR 0x 01F8 0080 All R Supervisor W Real time Clock Timer lt Scaler gt Register RTCSR 0x 01F8 0084 All R Supervisor W General purpose Timer lt Counter gt Register GPTCR 0x 01F8 0088 All R Supervisor W General purpose Timer lt Scaler gt Register GPTSR Ox 01F8 008C All R Supervisor W Timers Control Register TIMCTR 0x 01F8 0098 All R Supervisor W General purpose Interface Configuration Register GPICNFR 0x 01F8 00A8 All R Supervisor W General purpose Interface Data Register GPIDATR 0x 01 8 00AC All R Supervisor W UART A Rx and Tx Register UARTAR Ox 01 8 00 0 Supervisor R W 3 12 4148H AERO 12 03 AMEL TSC695F User Manual Table 3 2 System Registers Address Map Continued System Register Name Address Read Write Access UART B Rx and Tx Register UARTBR Ox 01F8 00E4 Supervisor R W UART Status Register UARTSR Ox 01 8 00 8 All R Supervisor W Note All reserved bits have to be written wi
126. r The TAP controller is a synchronous finite state machine FSM which controls the sequence of operations of the JTAG test circuitry in response to changes at the JTAG bus Specifically in response to changes at the TMS input with respect to the TCK input 3 9 1 TAP Controller FSM The TAP controller FSM implements the state 16 states diagram as detailed in Figure 3 16 The IR is a 6 bit register which allows a test instruction to be shifted into the TSC695F The instruction selects the test to be performed and the test data register to be accessed The supported instructions are listed in Section 3 10 1 Although any num ber of loops may be supported by the TAP the finite state machine in the TAP controller only distinguishes between the IR and a DR The specific DR can be decoded from the instruction in the IR 3 36 AIMEL TSC695F User Manual 4148H AERO 12 03 Figure 3 16 JTAG TAP Controller State Machine Transitions between states are controlled by TMS input value FSM clock is TCK Note 1 Due to the scan cell layout Capture DR and Update DR are states without associated action during the scanning of internal chains 3 10 The Instruction Register 3 10 1 List of Instructions The instruction listed below are supported by the TSC695F TAP The table contains the bit value and mnemonic as well as which data register is selected by that instruction
127. r ave indication RTC Interrupt Control enable periph_halteDEBUG load re load hold stop at zero Figure 3 9 RTC Pin Functionality SYSCLK RTC counter 1 scaler 3 A A A or counter 2 scaler 1 RTC counter 1 scaler 2 A A A 4 or counter 2 scaler 0 counter T aier 1 or 0 4 4 4 4 3 6 8 8 Watchdog Timer The watchdog is supplied from a separate external input WDCLK pin which must have a frequency which is at least three times lower than SYSCLK This input is divided by 16 in prescaler or routed directly to the scaler of the watchdog as set in the System Con trol Register wdcs bit in SYSCTR The Watchdog Timer Register WDOGTR holds the loaded value both in the scaler and in the counter of the watchdog timer TSC695F User Manual AIMEL 3 29 4148 12 03 Figure 3 10 Watchdog Timer States and Transitions System processor RESET 3 6 9 UARTs 3 30 4148H AERO 12 03 Trap Door WD Program new value WD Timeout Acknowledge new value WD Program new value D Disabled Trap Door Set WD Program refresh Processor Interrupt RESET After reset the timer is enabled and starts running The default value is the scaler set to maximum and the counter set to maximum
128. rademarks of Atmel Corporation or its subsidiaries Other terms and product names may be the trademarks of others Printed on recycled paper 4148H AERO 12 03 xM
129. re 2 3 1 Register Windows 2 8 4148H AERO 12 03 B Dependencies One problem that RISC programmers face is that the processor can be slowed down by a poor choice of instructions Since each instruction takes some amount of time to store its result and several instructions are being handled at the same time later instructions may have to wait for the results of earlier instructions to be stored However a simple rearrangement of the instructions in a program called Instruction Scheduling can remove these performance limitations from RISC programs B Speed Since a simplified instruction set allows for a pipelined the RISC processors often achieve 2 to 4 times the performance of CISC processors using comparable semiconductor technology and the same clock rates B integration Because the instruction set of a RISC machine is so simple it uses up much less chip space Extra functions such as floating point arithmetic unit memory controller standard peripherals can also be placed on the same chip B Software Operating system and application programs who use the microprocessor s instructions will find it easier to develop code with a smaller instruction set The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor B Compilers Higher level language compilers produce more efficient code because they have always tended to use the smaller set of instructions to be found in a RISC comp
130. rs as a priority a forced interrupt else a pending interrupt on the external interrupt number 1 EXTINT 1 pin 0 interrupt not cleared 1 interrupt cleared ic 2 Interrupt Clear on asynchronous INT 2 ic 2 bit clears as a priority a forced interrupt else a pending interrupt on the external interrupt number 0 EXTINT 0 0 interrupt not cleared AIMEL TSC695F User Manual 1 interrupt cleared E 1 Interrupt Clear on asynchronous INT 1 ic 1 bit clears as a priority a forced interrupt else a pending interrupt on masked hardware errors 0 interrupt not cleared 1 interrupt cleared Table 4 28 Interrupt Force Register INTFCR address 0x 01f8 0054 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 ME E o 3 3 9 5 2 6 lt 2 2 5 reserved 0000 0000 0000 0000 lt xx lt 8 Tiz lt lt ils SS 5 8 x if r rw r 0000 0000 0000 0000 000 0000 0000 0000 0 E 15 Interrupt Force on asynchronous INT 15 if 15 bit forces interrupt on the internal or external Watchdog time
131. ry system was unable to supply a valid instruction or data If MEXC MEXC is asserted during an instruction fetch cycle it generates an instruction access exception trap tt 1 If asserted during a data cycle it generates a data access exception trap tt 9 It denotes a parity error uncor rectable EDAC error access violation bus timeout or system bus error is detected MEXC is used as a qualifier for the MDS 5 signal and is asserted when both MHOLD and MDS MDS are already asserted If MDS MDS is AMEL 4148 12 03 5 2 Memory and System Interface Signals 5 104 4148H AERO 12 03 applied without MEXC the TSC695F accepts the contents of the data bus as valid If MEXC MEXC accompanies MDS MDS an exception is generated and the data bus content is ignored MEXC MEXC is latched in the IU on the rising edge of SYSCLK and is used in the fol lowing cycle MEXC MEXC is deasserted in the same clock cycle in which MHOLD MHOLD is deasserted If this signal is asserted during a DMA transfer the DMA must withdraw its DMA request and end the DMA cycle PROMB 8 Select 8 bit Wide PROM input This input indicates that only 8 bit wide PROM is connected to the TSC695F The eight data lines from the PROM is to be connected to the D 7 0 signals The processor will perform a 8 bit to 32 bit conversion when the IU read
132. s Fault Type SYSFSR FAILAR SYSFSR FAILAR parity error on control bus N U U U parity error on data bus N U U U parity error on address bus N U U U access to protected area N U U U access to unimplemented area N U U U system registers parity error N U U U system registers access violation N U U U uncorrectable error in memory N U U U bus timeout N U U U bus error N U U U Note U means that the register is updated N means that the register is not updated If an asynchronous trap event occurs the System Fault Status register is updated and reflects the type of error in accordance with the asynchronous condition table refer to table 3 6 The System Fault Status register SYSFSR also indicates whether the type of error is valid At the same time the failing address is stored in the Failing Address Register FAILAR in accordance with the table 3 6 An asynchronous fault can only update SYSFSR and FAILAR if none of the synchro nous and asynchronous fault valid bit is set in SYSFSR In case one of the fault valid bits is set a trap is generated but information in the SYSFSR and FAILAR are irrelevant A MEL 3 21 4148 12 03 3 6 7 1 Synchronous Traps 3 22 4148H AERO 12 03 Table 3 6 SYSFSR amp FAILAR Update asynchronous condition table Asynchronous Fault Type SYSFSR FAILAR Watchdog timeout U N External INT 4 N N Real time clock timer N N General pur
133. s asserted Memory Hold is tested on the falling edge midpoint of cycle of SYSCLK The memory wait state controller of the TSC695F inserts in this way wait states during external accesses Floating point Hold Floating point Hold is asserted by the FPU if a situation arises in which the FPU cannot continue execution The FPU checks all dependencies in the decode stage of the instruction and asserts a Floating point Hold if necessary in the next cycle If the IU receives a Floating point Hold it freezes the instruction pipeline in the same cycle Once the conditions causing the Floating point Hold are resolved the FPU deasserts its command releasing the instruction pipeline A Floating point Hold is asserted if The FPU encounters an STFSR instruction with one or more FPops pending in the queue Either a resource or operand dependency exists between the FPop being decoded and any FPops already being executed The floating point queue is full Floating point Condition Codes Valid Floating point Condition Codes Valid is a specialized hold used to synchronize FPU compare instructions with floating point branch instructions It is asserted the normal condition whenever the Floating point Condition Codes bits FCC 1 0 are valid The FPU deasserts these bits 07 as soon as a floating point compare instruction enters the floating point queue unless an exception is detected Deas serting
134. s f t t field 4 This exception is asserted by the FPU when a floating point instruction other than FP store is attempted after the FPU has entered either pending exception or excep tion mode The FPU suspends all instruction execution with the exception of FP stores until the FP exception has been acknowledged and the FP queue has been cleared Unimplemented FPop fsr s f t t field 3 This exception is asserted by the FPU upon encountering a defined SPARC FPop instruction that is not supported by the TSC695F This includes all operations using extended precision format operands The trap handler is expected to emulate the unimplemented instruction IEEE exceptions fsr s f t t field 1 This class of exceptions is defined as part of the IEEE 754 Standard The five exceptions defined as IEEE Exceptions are reported in the cexc field and accumu lated in the aexc field of the fsr The only exceptions that can coincide are inexact with overflow and inexact with underflow B Invalid Operation fsr s cexc field 10000 The invalid operation exception is signaled if an operand is invalid for the operation to be performed The result when the exception occurs without a trap shall be a quiet NaN provided the destination has a floating point format The invalid operations are Any operation on a signaling NaN Addition or subtraction Magnitude subtraction of infinities such as Multipl
135. s from the PROM the conversion is not visible on data bus There is no EDAC or parity checking on accesses to the PROM when PROMS is asserted and EDAC and parity bits must be sup plied by the PROM when PROMB8 PROMB8 is deasserted B BA 1 0 Boot PROM Latched Address used for 8 bit Wide PROM output These outputs are used when 8 bit wide PROM is connected to the TSC695F During a fetch or 32 bit load access to the PROM the BA 1 0 will be asserted four times in order to get the four bytes needed to generate a 32 bit word The TSC695F will assert the following sequence Table 5 3 8 bit Wide PROM Read Access Sequence Sequence 1 0 Bits in the 32 bit word Comments 0 00 1 extra cycle 1 00 31 24 Load of n wait states cycles 8 5 2 01 23 16 Load of n wait states cycles 2 B 3 10 15 8 Load of n wait states cycles 4 11 7 0 Load of n wait states cycles 5 00 Internal load 0 wait state During store byte only stb instruction is allowed in 8 bit wide PROM BA 1 0 is equiva lent to RA 0 1 B ROMCS ROMCS ROM Chip Select output This output is asserted whenever there is an access to the boot ROM area It can be connected directly to the ROM chip select pins m ROMWRT ROMWRT ROM Write Enable input Assertion of this signal will enable the pwr bit of the Memory Configuration Register MCNFR This logic allows the on board progr
136. s to this field note ec bit 0 coprocessor is not available E ef Enable Floating point Unit 0 FPU disabled 1 FPU enabled If the FPU is either disabled or enabled but not present an FPop FBfcc or floating point load store instruction will cause a floating point disabled trap When disabled the FPU retains that state until it is re enabled or reset Even when disabled it can continue to execute any instructions in its queue ef bit can be used by the programmer to control FPU use when running multiple processes By disabling the ef bit while running a process that doesn t require the FPU software would not have to save and restore the FPU s registers across context switches If the FPU is not present as signaled by the input signal FP the ef bit can be used to provoke floating point instruction set emulation by generating a floating point disabled trap if execution of a floating point instruction is attempted This technique may be used with the CO processor as well 4 52 AIMEL TSC695F User Manual 4148H AERO 12 03 B pil Processor Interrupt Level pil field identifies the processors external interrupt priority level The processor will only accept asynchronous interrupts whose interrupt level i e INT level in TSC695F Errors Traps and Priority Assignments table is greater than the value in pil Bit 11 of the pil field is the MSB and bit 8 is the LSB B 5 Supervisor S bit de
137. sources B Address enable and 8 bit occurrence counter of breakpoint 1 for program execution B Address enable and 8 bit occurrence counter of breakpoint 2 for program execution B Address enable and 8 bit occurrence counter of breakpoint 3 for program execution B Upper address lower address data data mask enable qualifiers qualifiers mask and 8 bit occurrence counter of breakpoint for data memory B Enable and 24 bit cycle counter B Enable Step by step Mode OCD Scan register is connected between TDI and TDO A single scan chain consisting of all of the scan cells of OCD control and status register In the On chip Debugger environment the OCD control and status scan allows the only access to the following OCD controls B Reset Request B Freeze Request m Run or Step by step and status Reset image of RESET output pin B Freeze Grant System Halt image of SYSHALT input OCD Scan register is connected between TDI and TDO AMEL A 4148H AERO 12 03 3 12 On chip Debugger Resources 3 12 1 Hardware The ODC provides 4 hardware Break points 3 for program execution and 1 for data Breakpoints memory When a breakpoint condition is true a break occurs and the internal clock is frozen It is then possible for an external monitoring system to know whether the proces sor is running or not thanks to SYSCLK and CPUHALT pins The Run command resumes from a break Each hardware breakpoint includes an internal 8
138. struction Memory add not Sync 8 0x07 aligned Non restartable Sync 9 1 0x08 Severe error cannot restart the instruction error Data bus error Sync 9 2 Parity error on FPU data bus Restartable error Sync 9 3 Can be removed by restarting the instruction Sequence error Sync d 9 4 Identified by f t t psr field 4 Unimplemented Sync 9 5 Identified by f t t psr field 3 FPop IEEE exceptions Sync 9 6 Identified by cexc field with field f t t 1 Invalid operation c ius a Division by zero 9 Overflow Underflow x Inexact 2 Unfinished FPop Sync Never asserted No trap nor error Data access Sync 10 0x09 Error on data load Parity error on control bus refer to CPAR signal description Parity error on data bus refer to DPAR signal description Parity error on address bus refer to RAPAR signal description Access to protected or unimplemented area Uncorrectable error in memory refer to EDAC section Bus time out refer to Waitstate and Timeout Generator section Bus error refer to BUSERR signal description System register access violation TSC695F User Manual AIMEL 3 19 4148 12 03 Table 3 4 TSC695F Errors Traps and Priority Assignments Continued Trap Output Sync Type Signal Trap and or error Async Priority tt Observation Comments Tag overflow S
139. t 1 End Register APS1ER address 0x 01f8 0024 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 reserved 0 0000 0000 segtend r 00000 0000 000 0000 0000 0000 0000 0000 B segiend Segment 1 END Address segtend field denotes the first address outside the segment 1 The Segment 1 End Address is calculated according the formula Segment 1 End Address 0x02000000 seg end 4 Table 4 22 Access Protection Segment 2 Base Register APS2BR address 0x 01f8 0028 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 41312 1 reserved 000 0000 9 9 seg2base n uu rw Ww W 000 0000 000 0000 0000 0000 0000 0000 B 5 2 Supervisor Enable Segment 2 AIMEL TSC695F User Manual 4 78 4148H AERO 12 03 se2 bit enables the write protection in supervisor mode on the segment 2 defined by seg2base and seg2end 0 write access protection disabled in supervisor mode 1 2 write access protection enabled in supervisor mode B 2 User Enable Segment 2
140. t enables the I O Area 1 space from at 1100 0000 0 disable 1 enable B 5 21 l O Area 1 Size 5121 field fixes the size in the I O Area 1 space siz1 Size siz1 Size siz1 Size siz1 Size 0000 512 bytes 0100 8 Kbytes 1000 128 Kbytes 1100 2 Mbytes 0001 1 Kbytes 0101 16 Kbytes 1001 256 Kbytes 1101 4 Mbytes 0010 2 Kbytes 0110 32 Kbytes 1010 512 Kbytes 1110 8 Mbytes 0011 4 Kbytes 0111 64 Kbytes 1011 1 Mbytes 1111 16 Mbytes B 0 I O Area 0 Parity Protected bit only enables an parity protection on the I O Area 0 space If NOPAR pin is tied to ground setting bit has no effect 0 parity protection disabled 1 parity protection enabled TSC695F checks parity B 00 Area 0 Enable 00 bit enables the I O Area 0 space from at 1000 0000 0 disable 1 enable B 5 20 I O Area 0 Size 5120 field fixes the size in the I O Area 0 space 5120 Size 5120 Size 5120 Size 5120 Size 0000 512 bytes 0100 8 Kbytes 1000 128 Kbytes 1100 2 Mbytes 0001 1 Kbytes 0101 16 Kbytes 1001 256 Kbytes 1101 4 Mbytes AMEL 4148H AERO 12 03 TSC695F User Manual 5120 Size 5120 Size 5120 Size 5120 Size 0010 2 Kbytes 0110 32 Kbytes 1010 512 Kbytes 1110 8 Mbytes 0011 4 Kbytes 011
141. t on the Real time Clock Timer 0 interrupt not masked 1 interrupt masked default E jm 12 Interrupt Mask on asynchronous INT 12 im 12 bit masks the interrupt on the General purpose Timer 0 interrupt not masked 1 interrupt masked default E im 11 Interrupt Mask on asynchronous INT 11 im 11 bit masks the external interrupt number 3 EXTINT 3 pin 0 interrupt not masked 1 interrupt masked default E 10 Interrupt Mask on asynchronous INT 10 im 10 bit masks the external interrupt number 2 EXTINT 2 pin 0 interrupt not masked 1 interrupt masked default TSC695F User Manual AIMEL 4 83 4148 12 03 E jm 9 Interrupt Mask on asynchronous INT 9 im 9 bit masks the interrupt on DMA timeout 0 interrupt not masked 1 interrupt masked default E im 8 Interrupt Mask on asynchronous INT 8 im 8 bit masks the interrupt on DMA access error 0 interrupt not masked 1 interrupt masked default E im 7 Interrupt Mask on asynchronous INT 7 im 7 bit masks the interrupt on a UART error 0 interrupt not masked 1 interrupt masked default E 6 Interrupt Mask on asynchronous INT 6 im 6 bit masks the interrupt on a correctable error in memory 0 interrupt not masked 1 interrupt masked default E jm 5 Interrupt Mask on asynchronous INT 5 im 5 bit masks the interrupt on e
142. tatus is not lost upon assertion of a floating point exception because instructions following a valid exception are not executed by the TSC695F FPU nvc iNValid Operation Current Exception This is defined as an operation using an improper operand value ofc OverFlow Current Exception The rounded result would be larger in magnitude than the largest normalized number in the specified format ufc UnderFlow Current Exception The rounded result is inexact and would be smaller in magnitude than the smallest normalized number in the indicated format dzc Division by zero Current Exception X 0 where X is subnormal or normalized Note that 0 0 does not set the dzc bit nxc iNeXact Current Exception The rounded result differs from the infinitely precise correct result Table 4 8 FPU Queue Registers FQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 1211 10 9 8 71615 4 3 211 fpop address r X fpop instruction r X TSC695F User Manual The FPU maintains a floating point queue of the instruction that has started execution but has yet to complete execution The FP queue is used to accommodate the multiple clock nature of floating point instructions and to support the handling of FP exceptions When the FPU encounters an exception case it asserts a floating point exception and enters pending exc
143. ter the FPU has entered either pending exception or exception mode The TSC695F suspends all instruction execution with the exception of FP stores until the FP exception has been acknowledged and the FP queue has been cleared 5 101 data bus error Parity error on internal data bus 6 110 restartable error Parity error on address and control internal buses 7 111 non restartable error Parity error on FPU registers B qne Queue Not Empty fcc qne bit signals whether the FP queue is empty 0 queue empty 1 queue not empty Floating point Condition Code fcc field reports the FP condition codes 0 005 1 01 2 10 3 114 unordered lt gt E aexc Accumulated Exception aexc field reports the accumulated FP exceptions that are masked by the tem field All masked exception cases are ORed with the contents of the aexc and accumulated as status All accumulated fields have the same definition as the corresponding field for cexc nva iNValid Operation Accumulated Exception ofa OverFlow Accumulated Exception ufa UnderFlow Accumulated Exception dza Division by zero Accumulated Exception nxa iNexact Accumulated Exception AIMEL TSC695F User Manual 4 8 FPU Queue Registers Current Exception cexc field reports the current FP exceptions This field is automatically cleared upon the execution of the next floating point instruction cexc s
144. termines whether the processor is in supervisor or user mode Because WRPSR is privileged and only available in the supervisor mode supervisor mode can only be entered by a software or hardware trap 0 user mode 1 supervisor mode B ps Previous Supervisor ps bit holds the value that was in the s bit at the time the most recent trap was taken ps bit is the only PSR bit that cannot be restored it is overwritten when the trap is taken B ct Enable Traps et bit determines whether traps are enabled If traps are disabled all asynchronous traps are ignored If a synchronous or floating point trap occurs while traps are disabled the IU halts and enters the error mode 0 traps disabled 1 traps enabled f itis necessary for the software to manually disable traps care must be taken when changing the et bit from enabled et 1 to disabled et 0 since the RDPSR WRPSR instruction sequence is interruptible One way to handle that is to write all interrupt trap handlers so that before they return program control to the supervisor software that was interrupted they restore the PSR to the value it had before the interrupt was taken This will guarantee a correct result when the interrupted RDPSR WRPSR sequence continues An alternative to the RDPSR WRPSR sequence is to generate a trap instruction trap with a Ticc instruction A taken trap automatically sets et to 0 disabling further traps B cwp
145. terrupt ResetTimeout is greater than Timeout wdos wds 1 wde 1 Timeout 16 WDCLK Note The wdcs bit and WDCLK of the formula are respectively the enable bit of the watchdog 4 bit pre scaler i e SYSCTR and the WDCLK input signal AMEL 4148 12 03 Reading wdc field gives the loading or re loading value not the effective count value Table 4 30 Watchdog Trap Door Set WDOGST address 0x 01f8 0064 Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 41312 110 Write only with any data A write to this register after reset but before the watchdog has elapsed will disable the watchdog The watchdog will stay disabled until it is repro grammed by writing to the Watchdog Timer Register WDOGTR Table 4 31 Real time Clock Timer Counter Register RTCCR address 0x 01f8 0080 Supervisor and User Read Supervisor Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 41312 1 rtcc r w 1111 1111 1111 1111 1111 1111 1111 1111 B rtcc Real time Clock Timer Counter rtcc field has 2 meanings A write access programs the pre
146. th zeros in order to avoid parity error resulting in an internal error 3 6 3 Waitstate and Timeout Generator 3 6 4 EDAC TSC695F User Manual It is possible to control the wait state generation by programming a Waitstate Configura tion Register WSCNFR The maximum programmable number of wait states is applied as default at reset It is only possible to program the number of wait states for the following combinations RAM read and RAM write PROM read and PROM write i e EEPROM or FLASH write Exchange Memory read write Four individual I O peripherals read write On RAM accesses the processor will insert the programmed number of waitstates after the first cycle On extended RAM accesses one cycle is inserted at the beginning for permit an exter nal address decoding This area is BUSRDY controlled and no waitstate is available On PROM accesses one cycle is inserted at the beginning ROMCS is generated Then the processor will apply the programmed number of waitstates after the second cycle On extended PROM accesses one cycle is inserted at the beginning for permit an external address decoding This area is BUSRDY controlled and no waitstate is available On exchange memory accesses the processor will sense the bus ready signal BUS RDY after the first two cycles of the access If the bus ready signal is asserted at this time the TSC695F will continue with the programmed number of waitstates However if th
147. un Freeze command freezes the internal clock All peripherals are frozen All the on chip debugger commands are available Run is used to resume from Freeze state due to Freeze command or a breakpoint occurrence 3 12 5 Step by step The step by step command allows to execute a single execute instruction AIMEL TSC695F User Manual 3 44 4148H AERO 12 03 AIMEL 4 1 IU Registers Table 4 1 Register Legend bit number field name bit name access type default value after RESET 4 2 Processor State Register Table 4 2 Processor State Register PSR Section 4 Register Descriptions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 0 field reserved 0x 00 b2 b3 b4 0x00 read value and value to be written read access W write access r w read and write access 1010 x undefined or non affected by RESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 icc impl ver reserved 00 0000 ef pil s ps et cwp n 2 nu uu rn uU jr r r r w r r w rw IW IW W W W 0001 0001 x 00 0000 x 1 0 TSC695F User Manual Implementation The implementation number for the TSC695F IU is 0001 B ver U Version The current version number for the TSC695F IU
148. uter The Scalable Processor Architecture is an open industry standard architecture pio neered by SUN Microsystems in 1987 The SPARC architecture s definition includes the IU Integer Unit which is the CPU the FPU Floating point Unit and the CP Co processor which is optional Other options are memory controller memory management unit and cache An important concept of the SPARC architecture is borrowed from the Berkeley RISC chips This is register windowing concept When a program is running it has access to 32 32 bit processor registers which include 8 global registers plus 24 registers that belong to the current register window B The first 8 registers in the window are called the in registers 0 7 When a function is called these registers may contain arguments that can be used B The next 8 are the local registers 0 7 which are scratch registers that can be used for anything while the function executes B The last 8 registers are the out registers 00 07 which the function uses to pass arguments to functions that it calls When one function calls another the calling function can choose to execute a SAVE instruction This instruction decrements an internal counter the current window pointer cwp shifting the register window downward The caller s out registers then become the calling function s in registers and the calling function gets a new set of local and out registers for its own use Only the point
149. xternally provided While the halt mode is active the timers are temporary halted Figure 3 4 Timers Halt o SYSCTR System Control Register IWDE reset clk DEBUG Watchdog enable Q X Timer i wd int Watchdog Clock aie o gpt int Purpose mmer 3o ge SYSCLK s MC RTC x Timer Control Register UARTB Halt S UARTA Halt Peripherals Halt 3 6 8 1 General purpose The General purpose Timer GPT provides in addition to a generalized counter func Timer tion a mechanism for setting the step size in which actual time counts are performed a two stage counter This timer counter pulse generator consists of two parts B pre SCALER GPTSR it is a counter to adjust the step size in which counter does the actual time count B COUNTER GPTCR itis a counter to actually count time in steps as set by the value in scaler The counter is decremented when the scaler reaches zero Figure 1 GPT Implementation Cnt 16 bit Scaler Zero 32 bit Counter indication Control enable periph halteDEBUG load re load hold stop at zero GPT SYSCLK Interrupt GPT is clocked by the internal system clock The timer is programmable by writing to the Timer Control Register TIMCTR They are possible to program to be either of single shot type or periodical type and in both cases generate an interrupt when the delay time TSC695F
150. ync 11 0x0A TADDccTV and TSUBccTV instructions Trap instructions Sync 12 0x80 Trap on integer condition codes Ticc to OxFF System hardware Sync SYSERR Parity error on system registers error if unmasked Trap Masked hardware errors if enabled Watchdog timeout Async 13 Ox1F INT level 15 No maskable Internal or external EWDINT External INT 4 Async 14 Ox1E EXTINTAK 14 on only one of EXTINT 4 0 Real time clock timer Async 15 Ox1D RTC INT level 13 General purpose Async 16 0x1C INT level 12 timer External INT 3 Async 17 Ox1B EXTINTAK 11 on only of EXTINT 4 0 External INT 2 Async 18 EXTINTAK INT level 10 EXTINTAK on only one of EXTINT 4 0 DMA timeout Async 19 0x19 INT level 9 DMA session exceeds permitted time DMA access error Async 20 0x18 INT level 8 DMA performs an access error access violation or illegal access UART Error Async 21 0x17 INT level 7 Correctable memory Async 22 0x16 INT level 6 EDAC detects and corrects an error Data read OK error but source memory contents not updated UARTB Data Async 23 0x15 INT level 5 Generated by the UARTs each time a data word has ready been correctly received or and sent Trans ready UARTA Data Async 24 0x14 INT level 4 ready Trans ready External INT 1 Async 25 0x13 INT level 3 EXTINTAK on only one of EXT
151. yte 0 7 Byte 0 7 Byte 01 7 Byte 0 Address N TSC695F User Manual N 1 N 2 N 3 N 4 N 5 N 6 N 7 B Registered Address Bus Parity output input This output is the odd parity over the 32 bit IU address bus To save board space this signal is sent out registered and has the same timing as RA 31 0 In case of DMA session this signal must be driven by the DMA unit if DMA parity is enabled This input requires the same timing as RA 31 0 B RASI 3 0 Registered Address Space Identifier output input These four bits constitute the Address Space Identifier ASI which identifies the mem ory address space to which the instruction or data access is being directed The ASI bits 5 98 Rev 4148H AERO 12 03 are provided to detect supervisor or user mode instruction or data access Inside the processor these identifiers are used to control accesses to on chip peripherals To save board space these outputs are sent out registered and has the same timing as RA 31 0 In case of DMA session these signals must be driven by the DMA unit These inputs require the same timing as RA 31 0 Table 5 1 RASI Assignments RASI 3 0 code Definition 1000 0x8 User instruction 1010 0xA User data 1001 0x9 Supervisor instruction 1011 0xB Supervisor data B RSIZE 1 0 Registered Bus Transaction Size output input The coding on these pins specifies the size of the

TSC695F 32-bit Sparc Processor

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