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TB-FMCH-12GSDI Hardware User Manual

1. Test Point Schematic Signal Name Nominal Voltage Component Pin TP1 none 12V U34 11 12 TP2 2V5 2 5V none TP3 3V3 3 3V none TP4 12V 12 0V J10 C35 C37 TP5 3V3_AUX 3 3V J10 D32 TP6 FMC VADJ 1 2V to 3 3V J10 E39 F40 G39 H40 TP8 GND ground TP9 GND ground TP10 GND ground TP11 GND ground TP12 3V3 VDSS 3 3V U3 3 6 11 TP2 TP4 TP6 TP12y J 2222225222 2 HEHE es ELI BME TP10 11 om omo e gt 44 SELL cp A SNL ani WEE RIZZA FM 2 22 22 ue PPP RPP PP Pe Be EME EE VIVAS II at NE RITS un A no J REESE d i Le RARA MANNA x lI M Sane 514645 o a 22322222 2 25 FAL m mm 2227272 ea A 03 04 02 TP9 Figure 14 1 Test Point and LED Locations on HDBNC Connector Side Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 25 inreviun 15 Demonstration An FPGA demonstration load is available on the inrevium website Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 26 inreviun 16 Appendix A FMC I2C EEPROM Contents The following table describes the contents of the FMC 12C EEPROM as programmed at the factory Table 16
2. Ac ii gt Figure 8 1 TB FMCH 12GSDI Front Edge HDBNC Coaxial Connectors Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 20 Inreviun 9 SDI Channels The main function of the TB FMCH 12GSDI card is to enable SDI connectivity To accomplish this there are 5 HDBNC connectors SDI channel 0 consists of two HDBNC connectors 1 dedicated input and 1 dedicated output SDI channels 1 2 and 3 are each provisioned with a single HDBNC connector An SPDT RF switch located at each connector on channels 1 2 and 3 determines the desired functionality i e input or output The system block diagram at the beginning of this document depicts the key components that are present on each channel Table 9 1 SDI Channel Major Components Manufacturer Part Number Description Transmit System MACOM M23145G Multi Rate Digital Re Clocker MACOM M23428G Low Jitter Cable Driver Receive System MACOM M23554G Adapter Equalizer w Re Clocker Transit Receive Peregrine PE42520 SPDT RF Switch 9KHz to 13GHz 50 ohm Each device in the table above is programmable via SPI Each RF switch direction is controlled by the signal CHx_DIR 0 Rx input to FMC 1 Tx output from FMC Although the switch is absorptive and offers good isolation it is recommended that any transmit circuitry be disabled when operating in receive mode Note Exceeding the maximum input level or connecting multiple outputs t
3. Minimum Current Draw 0x0003 In units of 1mA 3mA Maximum Current Draw DC Load Record 3P3V Field 0x0032 Data In units of 1mA BOMA Description Output Information 0x01 Bit map containing output number etc 3 3V Nominal Voltage 0x014A In units of 10mV 3 3V Minimum Voltage 0x0139 In units of 10mV 3 13V Maximum Voltage 0x0154 In units of 10mV 3 4V Ripple and Noise PK PK 0x0032 In units of 1mV 10Hz to 30MHz 50mV Minimum Current Draw 0x0190 In units of 1mA 400mA Maximum Current Draw DC Load Record 12P0V Field 0x03F2 Data In units of 1mA 1 01A Description Output Information 0x02 Bit map containing output number etc 12V Nominal Voltage 0x04B0 In units of 10mV 12V Minimum Voltage 0x0474 In units of 10mV 11 4V Maximum Voltage 0 04 In units of 10mV 12 6V Ripple and Noise PK PK 0x0064 In units of 1mV 10Hz to 30MHz 100mV Minimum Current Draw 0x012C In units of 1mA 300mA Maximum Current Draw 0x0262 DC Output Record VIO B M2C Field Data In units of 1mA 610mA Description Output Information 0x03 Bit map containing output number etc Nominal Voltage 0x0000 In units of 10mV Minimum Voltage 0x0000 In units of 10mV Maximum Voltage 0x000
4. DP2 M2C P EX CH2 SDO N DP2 M2C N IN M2C Channel 2 Input EX CH3 SDO P DP3 M2C P EX CH3 SDO N DP3 M2C N IN M2C Channel 3 Input SPI and I2C Signals D17 EX SPI MOSI LA13 P OUT C2M LVCMOS VADJ SPI MOSI D18 EX SPI MISO LA13 N IN M2C LVCMOS VADJ SPI MISO D20 EX SPI SCLK LA17 CC P OUT C2M LVCMOS VADJ SPI SCLK D11 EX SPI SO LAO5 P OUT C2M LVCMOS VADJ SPI Mux Select 0 D9 EX SPI S1 LAO1 CC N OUT C2M LVCMOS VADJ SPI Mux Select 1 SPI Chip Select for D15 EX SPI CS1 LAO9 N OUT C2M LVCMOS VADJ M23145G SPI Chip Select for D14 EX SPI CS2 LAO9 P OUT C2M LVCMOS VADJ M23428G SPI Chip Select for D12 EX SPI CS3 LAO5 N OUT C2M LVCMOS VADJ M23554G LVCMOS OD H13 EX CTL I2C SCL LAO7 P OUT C2M Control 12C Clock VADJ LVCMOS OD H14 EX CTL I2C SDA LAO7 N BI DIR Control I2C Data VADJ FMC ID EEPROM C30 EX 126 SCL OUT C2M LVCMOS 12C Clock Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 18 inreviun FMC ID EEPROM C31 EX I2C SDA SDA BI DIR LVCMOS I2C Data ontrol and Miscellaneous Signals Channel 0 C10 EX XALARM TX CHO LAO6 P IN M2C LVCMOS VADJ M23145G xALARM Channel 1 C11 EX XALARM TX CH1 LAO6 N IN M2C LVCMOS VADJ M23145G xALARM Channel 2 C14 EX XALARM TX CH2 LA10 P IN M2C LVCMOS VADJ M23145G xALARM Channel 3 C15 EX XALARM TX CH3 LA10 N IN M2C
5. LVCMOS VADJ M23145G xALARM Channel 0 H16 EX XALARM RX CHO LA11 P IN M2C LVCMOS VADJ M23554G xALARM Channel 1 H17 EX_XALARM_RX_CH1 LA11_N IN M2C LVCMOS VADJ M23554G xALARM Channel 2 H19 EX_XALARM_RX_CH2 LA15_P IN M2C LVCMOS VADJ M23554G xALARM Channel 3 H20 EX_XALARM_RX_CH3 LA15_N IN M2C LVCMOS VADJ M23554G xALARM Channel 1 G30 EX_CH1_DIR LA29 P OUT C2M LVCMOS VADJ PE42520 CTRL Channel 2 G33 EX_CH2_DIR LA31_P OUT C2M LVCMOS VADJ PE42520 CTRL Channel 3 C18 EX_CH3_DIR LA14 P OUT C2M LVCMOS VADJ PE42520 CTRL H1 Not connected VREF A M2C IN M2C K1 Not connected VREF B M2C IN M2C D1 Not connected PG C2M OUT C2M Not used F1 10k to VCC_3V3 PG M2C IN M2C Not used H2 EX PRSNT PRSNT M2C N IN M2C LVCMOS Extender Present D29 Not connected TCK OUT C2M D30 Not connected TDI OUT C2M D31 Not connected TDO IN M2C D33 Not connected TMS OUT C2M D34 Not connected TRST N OUT C2M C34 GAO GAO OUT C2M LVCMOS ID EEPROM El D35 GA1 GA1 OUT C2M LVCMOS ID EEPROM EO J39 Not connected VIO B M2C IN M2C K40 Not connected VIO B M2C IN M2C NOTE Direction IN M2C 129501 card FPGA board OUT C2M FPGA board 12GSDI card Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 19 inreviun i 8 3 HDBNC Connectors The SDI connectors use Samtec coaxial High Density BNC HDBNC HDBNC J P GN RA BH2 connectors Figure 8 1 shows the positions and assignments for each front edge connector zu
6. 1 FMC I2C EEPROM Contents Board Information Field Data Language Code 0 Date Time of Manufacture Variable Board Manufacturer FidusSystemsInc Board Product Name TB FMCH 12GSDI Board Serial Number Variable Board Part Number PA 10079 01 FRU File ID 0 Hardware Revision Variable MAC Address 00 00 00 00 00 00 Multi Record Information VITA Subtype 0 Record Field Data Description Vendor OUI 0x0012A2 Fixed value of 0x0012A2 Subtype Version 0x00 7 4 type main definition type 3 0 version current version Size Connectors Clock Dir 0x1C 7 6 size single width 5 4 P1 size HPC 3 2 P2 size not fitted 1 clock dir Mezzanine to Carrier 0 reserved 0 P1 Bank A Number Signals 59 signals P1 Bank B Number Signals P2 Bank A Number Signals P2 Bank B Number Signals P1 P2 Number Transceivers 7 4 P1 GBT 8 3 0 P2 GBT 0 Max Clock for TCK In units of MHz 149MHz Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 27 Inreviun DC Load Record VADJ Field Data Description Output Information 0x00 Bit map containing output number etc VADJ Nominal Voltage 0x00B4 In units of 10mV 1 8V Minimum Voltage 0x0078 In units of 10mV 1 2V Maximum Voltage 0x014A In units of 10mV 3 3V Ripple and Noise PK PK 0x0032 In units of 1mV 10Hz to 30MHz 50mV
7. bet CLKOUT2 N B20 27 4 23 GBTCLK1_M2C_P si OUT1_P IN1_P a CLKOUT3_P GBTCLK1_M2C_N lt OUT1_N IN1 N 4L CLKOUT3_N 24 6 1 OUT2 P IN2 P 4 N C 23 7 148 5MHz AY OUT2 N 1 DS10CP154 531BC148M500 OSC CROSSPOINT SWITCH 22 9 OUT3_P qq N C 21 10 148 35165MHz VY OUT3_N INS 531BC000110DG OSC Figure 13 1 Video Clock Generation Circuit Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 24 inreviun 14 Test Points and LEDs There are 11 test points accessible on the side of the card on which the HDBNC connectors are mounted This includes four through hole ground test points and seven test point pads for voltage rails Table 14 1 lists all the test points and Figure 14 1 shows the locations of the test points Note that TP7 does not exist There are three LEDs on the side of the card on which the HDBNC connectors are mounted The LEDs are on the LMH1983 video clock generator status outputs D2 is on the NO REF output D3 is on the NO ALIGN output and D4 is on the NO LOCK output There are no LEDs for any voltage rail Table 14 1 Test Points
8. block diagram Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 9 E inrev un E Cable Driver Driver T f Y Ex Ch0 SDI p n Cho SDI p n M23145G M23428G ln 140 I Ex Xalarm TX Ch0 Xalarm TX Cho oma SMI SDXHD Ca WI LI AS 2 P LJ CS RCLKR CHO MISO Clio CS DRVR CHO CS RCVR CHO 0 Equalizer Reclocker had ualizer Reclocker I Ex Cho SDO SDO p n PS MESES Deno Ex_Xalarm_RX_ChO RK Cho Jack az Ex_Ch1_DIR Ch1_DIR AN a n Reclocker Cable Driver Ex_Ch1_SDI_p n Ch1_SDI_p n M23145G M23428G Ex_Xalarm_TX_Ch1 Xalarm_TX_Ch1 SDXHD o 5 25 10 2 5V 60mA psum asa y CS_RCLKR_CH1 cs DRVR_CH1 SPDT RF SPI MOSI SCLK MISO CH1 CS_RCVR_CHI Switch PE42520 ualizer Reclocker Ex Ch SDO p n Chi SDO p n M23554G Channel 1 Ex_Xalarm_RX_Ch1 Xalarm_RX_Ch1 2svisoma A E Ex_Ch2_DIR Ch2_DIR Y FT N N Reclocker Cable Driver 4 Ex_Ch2_SDI_p n Ch2_SDI_p n M23145G M23428G Ex_Xalarm_TX_Ch2 Xalarm_TX_Ch2 Ga I SDXHD I J CS_RCLKR_CH2 PI MOSI SCLK MISO CH2 CS_RCVR_CH2 sU E cs DRVR CH SPDT AS mf Switch Jack M PE42520 Soo Il Equalizer Reclocker M23554G Channel 2 j 412 9 LI Ex_Ch2_SDO_p n Ex_Xalarm_RX_Ch2 Ch2_SDO_p
9. located in a row on the front edge of the card Note Only stack FMCs that are identical i e same part number and same revision Do not attempt to stack different FMCs Stacking FMCs of different types or revisions could cause damage 8 1 HPC FMC Connector to Main Board The FMC connector High Pin Count connecting to the main board uses Samtec ASP 134488 01 Table 8 1 shows the FMC connector pin assignment In this table the C2M direction means carrier to mezzanine which is an input to the FMC The M2C direction means mezzanine to carrier which is an output from the FMC BI DIR means bi directional so the signal direction could be either an input or an output Pins not included in the table are unconnected including all HA 0 23 and HB 0 21 signals Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 13 inreviun Table 8 1 HPC FMC Main Board Connector Pin Assignment Schematic Signal Name VITA 57 1 Name Direction Description SDI Differential Pairs CHO SDI P DPO C2M P OUT C2M Channel 0 Output CHO SDI N DPO C2M N CH1 SDI P DP1 C2M P OUT C2M Channel 1 Output CH1 SDI DP1 C2M N CH2 SDI P DP2 C2M P OUT C2M Channel 2 Output CH2 SDI N DP2 C2M N CH3 SDI P DP3 C2M P OUT C2M Channel 3 Output CH3 SDI N DP3 C2M N CHO SDO P DPO M2C P IN M2C Channel 0 Input CHO SDO N DPO M2C N CH1 SDO P DP1 M2C P IN M2C Channel 1 I
10. video clock generator and the DS10CP154 crosspoint switch The LMH1983 is very versatile and can generate almost any required SDI video clocks The LMH1983 and the crosspoint switch are controlled via an 12C bus Two oscillators feed the crosspoint switch to supply common video clock frequencies The LMH1983 FIN HIN and VIN clocks can also be supplied from the LMH1981 sync separator through the FPGA so the SDI channels can be synchronized with an external video source G19 3 LA16 gt gt HIN G18 4 LA16 P c VIN G21 SN74AVC4T245 5 LA20 P gy I FIN G16 6 LA12 Ng I INIT G9 37 LAOS P lt FOUTI G6 30 LAO0 CC P lee 4 FOUT2 G7 SN74AVC8T245 22 LAO0 CC t FOUT3 G10 17 LAO3 N qh lt FOUT4 H10 11 LA04 P eg LOCK H8 12 LAO2 N lt ALIGN H7 SN74AVC4T245 13 LA02_P qq lt NO REF 4 36 CLKO M2C P lt gt CLKOUT1_P CLKO_M2C_N CLKOUT1_N G2 15 CLK1_M2C_P CLKOUTA P N G3 14 CLK1 M2C CLKOUT4_N vc LPF 40 P F g LMP7711MK LAO7_P _ gt SDA H14 PCA9517 9 34 27 0MHz 07 let lt SCL XOIN_P qi ay lt k t HPC FMC HOST SDA 39 LMH1983 VIDEO 357LB31027M0000 CARRIER 27 CLOCK VCXO CONNECTOR J10 SCL GENERATOR D4 29 1 28 GBTCLKO M2C P Te TOP INO 4 2 CLKOUT2_P GBTCLKO_M2C_N 4 OUTO NINO N
11. 0 In units of 10mV Ripple and Noise PK PK 0x0000 In units of 1mV 10Hz to 30MHz Minimum Current Load 0x0000 In units of 1mA Maximum Current Load Rev 2 01 0x0000 TOKYO ELECTRON DEVICE LIMITED In units of 1mA 28 inreviun DC Output Record VREF_A_M2C Field Data Description Output Information 0x04 Bit map containing output number etc Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 0x0000 In units of 10mV Maximum Voltage 0x0000 In units of 10mV Ripple and Noise PK PK 0 0000 In units of mV 10Hz to 30MHz Minimum Current Load 0x0000 In units of 1mA Maximum Current Load 0x0000 In units of 1mA DC Output Record VREF_B_M2C Field Data Description Output Information 0x05 Bit map containing output number etc Nominal Voltage 2 0x0000 In units of 10mV Minimum Voltage 0x0000 In units of 10mV Maximum Voltage 0x0000 In units of 10mV Ripple and Noise PK PK 0x0000 In units of 1mV 10Hz to 30MHz Minimum Current Load 0x0000 In units of 1mA Maximum Current Load 0x0000 In units of 1mA Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 29 inreviun E TOKYO ELECTRON DEVICE Inrevium Company URL http solutions inrevium com http solutions inrevium com jp E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama C
12. 3 LA18 CC N for SDA These signals are connected to J11 C30 SCL and J11 C31 SDA via a PCA9517 12C bus repeater The FMC identification EEPROM is programmed at the factory to enable automated identification verification and configuration of Main Board parameters The contents of the EEPROM are displayed in Appendix A Note The user must be cognizant that the FMC 12 EEPROM is always write enabled As it contains critical information required for correct operation one must never overwrite the factory settings 12 Sync Input The Sync input on the FB FMCH 12GSDI FMC allows the user to synchronize the FPGA FMC system to an external video system The Sync input on HDBNC 49 is first terminated with 75 ohms to ground and then AC coupled before entering the LMH1981 video sync separator The LMH1981 will accept a wide variety of video signals up to 1080p The odd even field horizontal and vertical sync outputs are connected to the FMC carrier board connector The LMH1981 automatically detects the video format and accepts video signals up to 1 2Vpp Please see the LMH1981 data sheet for complete details on its operation Note Exceeding the maximum input level on the Sync input can cause irreparable damage to the TB FMCH 12GSDI FMC Do not exceed 1 2Vpp and 0V DC Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 23 inreviunW 13 Video Clock Generation Figure 13 1 shows the video clock generation circuit It basically consists of the LMH1983
13. ADJ LMH1981 OEOUT F VOUT 08 P LVCMOS VADJ LMH1981 VSOUT F HOUT LAO8 N LVCMOS VADJ LMH1981 HSOUT F FIN LA20 P LVCMOS VADJ LMH1983 FIN F VIN LA16 P LVCMOS VADJ LMH1983 VIN F HIN LA16 N LVCMOS VADJ LMH1983 HIN F_FOUT1 LAO3 P LVCMOS VADJ LMH1983 FOUT1 F_FOUT2 LAOO CC P LVCMOS VADJ LMH1983 FOUT2 F_FOUT3 LAOO CC N LVCMOS VADJ LMH1983 FOUT3 F FOUTA LAOS N LVCMOS VADJ LMH1983 FOUT4 ontrol and Miscellaneous Signals Channel 0 C10 F XALARM TX CHO LAO6 P IN M2C LVCMOS VADJ M23145G xALARM Channel 1 C11 F XALARM TX CH1 LAO6 N IN M2C LVCMOS VADJ M23145G xALARM Channel 2 C14 F XALARM TX CH2 LA10 P IN M2C LVCMOS VADJ M23145G xALARM Channel 3 C15 F XALARM TX LA10 N IN M2C LVCMOS VADJ M23145G xALARM Channel 0 H16 F XALARM RX CHO LA11 P IN M2C LVCMOS VADJ M23554G xALARM Channel 1 H17 F XALARM RX CH1 LA11 N IN M2C LVCMOS VADJ M23554G xALARM Channel 2 H19 F XALARM RX CH2 LA15 P IN M2C LVCMOS VADJ M23554G xALARM Channel 3 H20 F XALARM LA15 N IN M2C LVCMOS VADJ M23554G xALARM Channel 1 G30 F CH1 DIR LA29 P OUT C2M LVCMOS VADJ PE42520 CTRL Channel 2 G33 F CH2 DIR LA31 P OUT C2M LVCMOS VADJ PE42520 CTRL Channel 3 C18 F CH3 DIR LA14 P OUT C2M LVCMOS VADJ PE42520 CTRL G16 F INIT LA12 N OUT C2M LVCMOS VADJ LMH1983 INIT H7 F NO REF LAO2 P IN M2C LVCMOS VADJ LMH1983 NO REF LMH1983 H8 F NO ALIGN LAO2 N IN M2C LVCMOS VADJ NO ALIGN Rev 2 01 TOKYO ELECTR
14. D27 EX XALARM CH3 LA26 N IN M2C LVCMOS VADJ M23554G xALARM Channel 1 G31 EX CH1 DIR LA29 N OUT C2M LVCMOS VADJ PE42520 CTRL Channel 2 G34 EX CH2 DIR LA31 N OUT C2M LVCMOS VADJ PE42520 CTRL Channel 3 C19 EX CH3 DIR LA14 N OUT C2M LVCMOS VADJ PE42520 CTRL H22 EX PRSNT LA19 P IN M2C LVCMOS Extender Present NOTE Direction IN M2C 129501 card FPGA board OUT C2M FPGA board 12GSDI card Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 17 inreviun 8 2 HPC FMC Connector for the Extender TB FMCH 12GSDI Card The FMC connector High Pin Count connecting to the extender FMC uses Samtec ASP 134486 01 Table 8 2 shows the FMC extender connector pin assignment Table 8 2 HPC FMC Extender Board Connector Pin Assignment Schematic Signal Name VITA 57 1 Name Direction Description EK CHO SDI P SDI Differential Pairs DPO_C2M_P EX_CHO_SDI_N DPO_C2M_N OUT C2M Channel 0 Output EX_CH1_SDI_P DP1 C2M P EX CH1 SDI N DP1 C2M N OUT C2M Channel 1 Output EX CH2 SDL P DP2 C2M P EX CH2 SDI N DP2 C2M N OUT C2M Channel 2 Output EX CH3 SDI P DP3 C2M P EX CH3 SDI N DP3 C2M N OUT C2M Channel 3 Output EX CHO SDO P DPO M2C P EX CHO SDO N DPO M2C N IN M2C Channel 0 Input EX CH1 SDO P DP1 M2C P EX CH1 SDO N DP1 M2C N IN M2C Channel 1 Input EX CH2 SDO P
15. O H34 EX SPI SCLK LA30 P OUT C2M LVCMOS VADJ SPI SCLK H25 EX SPI S0 LA21 P OUT C2M LVCMOS VADJ SPI Mux Select 0 H23 EX SPI S1 LA19 N OUT C2M LVCMOS VADJ SPI Mux Select 1 SPI Chip Select for H29 EX SPI CS1 LA24 N OUT C2M LVCMOS VADJ M23145G SPI Chip Select for H28 EX SPI CS2 LA24 P OUT C2M LVCMOS VADJ M23428G Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 16 inreviun Schematic Signal Name VITA 57 1 Name Direction Type Description SPI Chip Select for EX_SPI_CS3 LA21_N OUT C2M LVCMOS VADJ M23554G LVCMOS OD EX CTL I2C SCL LA27 P OUT C2M Control I2C Clock VADJ LVCMOS OD EX I2C SDA LA27 N BI DIR Control I2C Data VADJ LVCMOS OD FMC ID EEPROM EX SCL LA18 CC P OUT C2M VADJ 12 Clock LVCMOS OD FMC ID EEPROM EX SDA LA18 CC N BI DIR VADJ 12C Data Extender Control and Miscellaneous Signals Channel 0 G24 EX XALARM TX CHO LA22 P IN M2C LVCMOS VADJ M23145G xALARM Channel 1 G25 EX XALARM TX CHI LA22 N IN M2C LVCMOS VADJ M23145G xALARM Channel 2 G27 EX XALARM TX CH2 LA25 P IN M2C LVCMOS VADJ M23145G xALARM Channel 3 G28 EX XALARM TX CH3 LA25 N IN M2C LVCMOS VADJ M23145G xALARM Channel 0 D23 EX XALARM RX CHO LA23 P IN M2C LVCMOS VADJ M23554G xALARM Channel 1 D24 EX XALARM CHI LA23 N IN M2C LVCMOS VADJ M23554G xALARM Channel 2 D26 EX XALARM RX CH2 LA26 P IN M2C LVCMOS VADJ M23554G xALARM Channel 3
16. ON DEVICE LIMITED 15 inreviun Schematic Signal Name VITA 57 1 Name Direction Type Description LMH1983 F_NO_LOCK LA04_P IN M2C LVCMOS VADJ NO_LOCK Not connected VREF_A_M2C IN M2C Not connected VREF_B_M2C IN M2C Not connected PG_C2M OUT C2M Not used 10k to VCC_3V3 PG_M2C IN M2C Not used 0 ohm to GND PRSNT_M2C_N IN M2C Not connected TCK OUT C2M 0 ohm to TDO TDI OUT C2M JTAG Bypassed 0 ohm to TDI TDO IN M2C JTAG Bypassed Not connected TMS Not connected TRST_N GAO GAO LVCMOS ID EEPROM El GA1 GA1 LVCMOS ID EEPROM EO Not connected VIO B M2C IN M2C Not connected VIO B M2C IN M2C Extender SDI Differential Pairs EX CHO SDI P DP4 C2M P OUT C2M Channel 0 Output EX CHO SDI N DP4 C2M EX CH1 SDI P DP5 C2M P OUT C2M Channel 1 Output EX CH1 SDI N DP5 C2M N EX CH2 SDI P DP6 C2M P OUT C2M Channel 2 Output EX CH2 SDI N DP6 C2M N EX CH3 SDI P DP7 C2M P OUT C2M Channel 3 Output EX CH3 SDI N DP7 C2M N EX CHO SDO P DP4 M2C P IN M2C Channel 0 Input EX CHO SDO N DP4 M2C N EX CH1 SDO P DP5 M2C P IN M2C Channel 1 Input EX CH1 SDO N DP5 M2C N EX CH2 SDO P DP6 M2C P IN M2C Channel 2 Input EX CH2 SDO N DP6 M2C N EX CH3 SDO P DP7 M2C P IN M2C Channel 3 Input EX CH3 SDO N DP7 M2C N Extender SPI and I2C Sign H31 EX_SPI_MOSI LA28 P OUT C2M LVCMOS VADJ SPI MOSI H32 EX SPI MISO LA28 N IN M2C LVCMOS VADJ SPI MIS
17. PROM Contes ein 27 List of Figures Figure 3 1 FMC HPC Connector Pin Layout from VITA 57 1 8 Figure 4 1 TB FMCH 12GSDI Block Diagram 10 Figure 5 1 External View of TB FMCH 12GSDI Component Side 11 Figure 5 2 External View of TB FMCH 12GSDI Solder Side sss 11 Figure 6 1 TB FMCH 12GSDI Board Dimensions MM 12 Figure 8 1 TB FMCH 12GSDI Front Edge HDBNC Coaxial Connectors 20 Figure 10 1 SPI Multiplexer Connections L n nnne 22 Figure 13 1 Video Clock Generation Circuit a 24 Figure 14 1 Test Point and LED Locations on HDBNC Connector 5 25 List of Tables Table 1 1 ACCOSSOMOS 7 Table 8 1 HPC FMC Main Board Connector Pin Assignment nr rnnnnn cnn 14 Table 8 2 HPC FMC Extender Board Connector Pin Assignment 18 Table 9 1 SDI Channel Major Components cnn rca rra 21 Table 10 1 SPI DES ua aaa 22 Table 14 1 UP Aaa 25 Table 16 1 FMC I2C EEPROM Contents L nennen nennt nennen neni 27 Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 3 inreviunW Introduction Thank you for purchasing the TB FMCH 12GSDI board Before using the product be sure to carefully read this user manual and fully un
18. U RU Figure 6 1 TB FMCH 12GSDI Board Dimensions mm Note The above is for reference only and should not be used for detailed mechanical analysis Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 69 00 63 00 12 inreviunW 7 Supplying Power to the Board The power structure of the TB FMCH 12GSDI is relatively simple The total power dissipation is under 5 watts There is one switching power regulator TPS62130 to produce 2 5 volts from the 12 volt FMC rail 12POV The MACOM ICs and the SPI multiplexers use only the 2 5 volt rail All the other ICs except for the voltage translators and the 12C repeaters use the FMC 3 3 volt rail 3P3V The voltage translators and 12C repeaters use the FMC VADJ voltage which can be range between 1 2 volts to 3 3 volts The FMC 3P3VAUX voltage is used only by the FMC EEPROM and a single 12C repeater The current draw from the 12POV voltage is less than 300 mA The current draw from the 3P3V rail is about 500 mA worst case There is no over current or over voltage protection on the 3P3V or 12P0V rails although both are LC filtered 8 Connectors There are a total of eight connectors on the FMC One HPC FMC connector is for the main board J10 and another HPC FMC connector J11 is for a second TB FMCH 12GSDI to provide double the SDI channels if required The five HDBNC SDI channel connectors are
19. apter cable HDBNC to BNC Belden 1694A Miratec length approximately 20cm 8 Spacer 10mm M2 6 Hirosugi Spacer 25mm M2 6 Hirosugi Screw 6mm M2 6 w washers Hirosugi 2 Overview The TB FMCH 12GSDI FMC has a dedicated SDI input a dedicated SDI output and three SDI channels that are either input or output Each SDI channel supports a data rate up to 11 88 Gbps It also has a video sync input for a video sync separator chip All video signal connections are via 75 ohm HDBNC jacks A video clock generator can also produce common video timing signals from oscillators or from HVF sync signals from the host FPGA The TB FMCH 12GSDI uses Samtec s FMC HPC connector for connection with a platform board having High Pin Count HPC connectors It is a single width air cooled FMC that is compatible with the ANSI VITA 57 1 FPGA Mezzanine Card FMC Standard A second FMC HPC connector allows a second TB FMCH 12GSDI to be stacked to double the number of SDI inputs and outputs The TB FMCH 12GSDI supports SD HD 3G 6G 12G SDI rates to enable next generation UHDTV 4k 60fps video over a single coaxial cable Note Even if your target carrier card supports a single TB FMCH 12GSDI there is no guarantee that stacking will be supported typically due to limited gigabit transceiver connectivity If stacking is a critical feature for you please contact your sales representative to confirm operation prior to ordering stacking No
20. derstand how to correctly use the product First read through this manual and then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to assure correct use e These precautions contain serious safety instructions that must be observed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled i N Warning incorrectly Indicates the possibility of injury or physical damage connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch KG M Do not disassemble the product S Do not attempt this Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 4 inreviun A Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immed
21. e of this product or its unusable state business interruption or others Use of this product against the instructions given in this manual Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 6 Inreviun 1 Related Documents and Accessories All documents relating to this board can be downloaded from the TED Support Web at address http solutions inrevium com In addition to the 12G SDI FMC the following table outlines the included accessories Table 1 1 Accessories Description Manufacturer Quantity Ad
22. ed to the FMC are voltage EX SPI SCLK SPI SCLK MOSI CH 0 3 level shifted to VADJ EX SPI MISO SPI MISO SCLK CH 0 3 bal ed differential signals are EX SPI S0 SPI S0 SPI MISO CH 0 3 pice EX SPI S1 oe gt Multiplexers CS RCLKR CH 0 3 EX SPI CS1 PI CS1 SN74LV4052A x3 E EX_SPI_CS2 SPI_CS2 gt GS DRVA CHOH EX SPI CS3 SPI CS3 a CS_RCVR_CH 0 3 A y I A Figure 4 1 TB FMCH 12GSDI Block Diagram Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 10 TB FMCH 12GSDI Hardware User Manual 5 External View of the Board Figure 5 1 External View of TB FMCH 12GSDI Component Side o o H yaz n iii n Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 11 inreviun 6 Board Specification The following shows the TB FMCH 12GSDI board physical specifications External Dimensions 84 00 mm long x 69 00 mm wide Number of Layers 16 layers Board Thickness 1 6 mm Material Megtron 6 Samtec HDBNC J P GN RA BH2 Samtec ASP 134488 01 Samtec ASP 134486 01 SDI Connectors FMC Main Connector FMC Extender Connector 22 7 4 Sel 3 1 L d FRU 26 Bm an c 19 r c c o Ed om Br d ll mm T e 1 E EXE Ki E ecd 4 h 3 3 o tint E y m e lt e Ed Domui Vif um oF dd i
23. iately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that there is no smoking contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates at high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock 0000000 D fe Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be co
24. inreviun Rev 2 01 TB FMCH 12GSDI Hardware User Manual Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History Version Date Description Publisher 1 00 2015 01 02 Initial release JC 2 00 2015 07 16 Updated Released ST Add list 16 FMC I2C EEPROM Contents 2 01 2015 10 13 Modify Table 8 1 8 2 MY Add 16 Appendix A Amano Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 2 inreviun Table of Contents 1 Related Documents and ACcCESSOrieS nnn r nn nsns nnn snas 7 O ii 7 e MAUA MAUA MAUA MAUA MAUA nn AU SAWA AWA 8 A Block DIA AI u AAA a a 9 5 External View of the Board 11 6 Board elias 12 7 Supplying Power to the eene aaa 13 A AA AA WAA O 13 8 1 HPC FMC Connector to Main Board i 13 8 2 HPC FMC Connector for the Extender TB FMCH 12GSDI 18 8 3 IHDBNG Connectors ail a 20 9 SDINGHANNEIS scans 21 10 Multiplexed PIBES leale 22 11 12 23 12 Syneinput add Ialia 23 13 Video Clock Generation mana 24 14 Test Points and LEDS 25 15 Demonstration 26 16 Appendix A FMC I2C EE
25. ity Kanagawa Japan 221 0056 TEL 81 45 443 4031 FAX 81 45 443 4063 Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 30
26. ltiplexer selection signals and which chip select signal corresponds with which MACOM device Table 10 1 SPI Decoding SDI Ch Selected Chip Select Signal Device Selected SPI CS1 Reclocker M23145G SPI CS2 Cable Driver M23428G SPI CS3 Equalizer M23554G MOSI CHO U17 SCLK CHO MISO CHO CS RCLKR CHO MOSI CH1 MOSI CH2 MOSI CH3 M23145G Reclocker SCLK CH1 SCLK CH2 SCLK_CH3 M23428G Driver CS_DRVR_CHO MISO_CH1 MISO_CH2 MISO_CH3 M23554G Equalizer CS RCLKR CH1 CS RCLKR CH CS RCLKR CH3 CS RCVR CHO SDI Channel 0 SPI Connections shown The other three channels are similar CS DRVR CHI CS DRVR CH2 CS DRVR CH3 CS RCVR CHI CS RCVR CH2 To From J10 FMC CS_RCVR_CH3 connector via voltage translators SN74LV4052A Dual 4 Channel Multiplexers Figure 10 1 SPI Multiplexer Connections Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 22 inreviunW 11 FMC I2C EEPROM A 2kbit 120 EEPROM M24C02 is provided for FMC identification as described in section 5 5 of ANSI VITA 57 1 It is at I2C address 0b1010000x and is connected to the FMC dedicated 12C pins at J10 C30 SCL and J10 C31 SDA The pull up resistors to are populated R163 and R164 The EEPROM is permanently enabled for writing The FMC identification EEPROM for the extender card is connected to J10 C22 LA18 CC P for SCL and J10 C2
27. n Xalarm_RX_Ch2 Ex_Ch3_DIR Ch3_DIR 8 S N C Y 9 Go E chi SDI Reclocker Cable Driver FE pobre SD g gt PA M23145G M23428G 2 poem cM 5 MTC CEA son J PPS Sr ah 5 CS_RCLKR_CH3 CS_DRVR_CH3 SPDT RF I LT TE lt SPI MOSI SCLK MISO CH3 c o CS_RCVR_CH3 Switch j PE42520 T n 8 Equalizer Reclock E E qualizer Reclocker 9 8 Ex_Ch3_SDO_p n 2 8 Ch3_SDO_p n M23554G Channel 3 Ex_Xalarm_RX_Ch3 iL Xalarm RX Ch3 3 3V 200uA C J Fot 14 Sync Separator f hon r La Vout 8 LMH1981 HDBNC J9 O Hout 7 Jack I ni lt q AM Fin Vin Hin b SYNC IN INIT gt No Ref No Align No Lock lt a Fouti Fout2 ra Fout3 Video a cou Clock N Clkout1_p n Generator P_ Clkout4_p n LMH1983 LMP7711MK 7 SCL 12C Repeater amp 12C Repeater gt A PCA9517 a a PCA9517 Je 3 SDA gt lt VCXO 27 0MHz a Extender 12C provided only Y Clkout2 for LMH1983 power down MGT CIkO Clkout3_p n Crosspoint aap Switch MGT_Clk1 GT C DS10CP154 a Osc 148 5MHz Com J EDS EX_SCL SCL gt EEPROM 4 148 35165MHz EX_SDA SDA M24C02 K J lt gt Coe Note All single ended GPIO signals EX_SPI_MOSI SPI_MOSI CAS connect
28. nput CH1 SDO N DP1 M2C N CH2 SDO P DP2 M2C P IN M2C Channel 2 Input CH2 SDO N DP2 M2C N CH3 SDO P DP3 M2C P IN M2C Channel 3 Input CH3 SDO DP3 M2C N SPI and 12C Signals F SPI MOSI LA13 P OUT C2M LVCMOS VADJ SPI MOSI F SPI MISO LA13 N IN M2C LVCMOS VADJ SPI MISO F SPI SCLK LA17 CC P OUT C2M LVCMOS VADJ SPI SCLK F SPI 0 LAO5 P OUT C2M LVCMOS VADJ SPI Mux Select 0 F SPI S1 LAO1 CC N OUT C2M LVCMOS VADJ SPI Mux Select 1 SPI Chip Select for F SPI CS1 LAO9 N OUT C2M LVCMOS VADJ M23145G SPI Chip Select for F SPI CS2 LAO9 P OUT C2M LVCMOS VADJ M23428G SPI Chip Select for F SPI CS3 LAO5 N OUT C2M LVCMOS VADJ M23554G LVCMOS OD F CTL I2C SCL LAO7 P OUT C2M Control I2C Clock VADJ LVCMOS OD F CTL I2C SDA LAO7 N BI DIR Control I2C Data VADJ FMC ID EEPROM NONE SCL OUT C2M LVCMOS 12C Clock FMC ID EEPROM NONE BI DIR LVCMOS I2C Data Video Clocks H4 F_CLKOUT1_P CLKO M2C P LMH1983 IN M2C LVDS H5 F_CLKOUT1_N CLKO M2C N CLKOUT1 Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 14 inreviun Schematic Signal Name VITA 57 1 Name Direction Type Description F CLKOUTA P CLK1 M2C P LMH1983 IN M2C LVDS F_CLKOUT4_N CLK1_M2C_N CLKOUT4 F_CLKOUT2_P GBTCLKO_M2C_P DS10CP154A IN M2C LVDS F_CLKOUT2_N GBTCLKO_M2C_N OUTO F_CLKOUT3_P GBTCLK1_M2C_P DS10CP154A IN M2C LVDS F_CLKOUT3_N GBTCLK1_M2C_N OUTI F_FOUT LA12 P LVCMOS V
29. ntaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 5 Iinreviun A Caution Do not use or place the product in the following locations e Humid and dusty locations S e Airless locations such as closet or bookshelf e Locations which receive oily smoke or steam e Locations exposed to direct sunlight e Locations close to heating equipment e Closed inside of a car where the temperature becomes high e Static prone locations e Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product O Otherwise the product may be damaged B Disclaimer This product is an SDI interface for Xilinx FPGA evaluation boards Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from us
30. ogether can cause irreparable damage to the TB FMCH 12GSDI FMC Always confirm your Tx Rx switch configurations prior to enabling outputs or driving inputs Note All SDI inputs outputs are AC coupled Note Maximum input levels Peregrine Semiconductor PE42520 RF Switch Frequency dependent refer to PE42520 datasheet and remember to consider that this is a 50 ohm specified part operating in a 75 ohm system M23554G Adaptive Cable Equalizer 880mVpp Note The PE42520 is a 50 ohm RF switch Signal integrity assessments have confirmed that this part will work sufficiently in this 75 ohm system Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 21 Inreviun 10 Multiplexed SPI Busses All MACOM devices M23145G M23428G M23554G are configured controlled via four wire SPI busses As there are 12 MACOM devices per TB FMCH 12GSDI there would be many FPGA pins required for just the SPI busses To reduce the number of FMC signal connections to something more desirable at the expense of complexity the busses are multiplexed Structurally each of the four SDI channels has a separate SPI bus Figure 10 1 shows the connections and signals for the SPI busses Three dual SP4T SN74LV4052 multiplexer chips are controlled with two signals SPI_SO SPI_S1 to select which of the four SPI busses is connected to the FPGA The maximum SPI bus clock frequency is 20MHz The following tables show which SPI bus is active based on the state of the mu
31. te Only stack FMCs that are identical i e same part number and same revision Do not attempt to stack different FMCs Stacking FMCs of different types or revisions could cause damage Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 7 inreviun 3 Features SDI Video Reclocker MACOM M23145G SDI Cable Driver MACOM M23428G SDI Cable Equalizer Reclocker MACOM M23554G FMC Main Connector Samtec ASP 134488 01 FMC Extender Connector Samtec ASP 134486 01 SDI Connectors Samtec HDBNC J P GN RA BH2 FPGA GPIO Signal Level 1 2V through 3 3V using voltage level translators or AC coupling Video Sync Separator Texas Instruments LMH1981 Video Clock Generator Texas Instruments LMH1983 K J H G F E C VREF_B_M20 GND VREF A M26 GND Gs GND _ CLK3 BIDIRN GND cLKiM2CN GND GLK2 BIDIR P GND M20P GND GND CLK2 N GND GND CLKO M2CN GND LA00_P_CC LAO0 N CC z gt 2 v v glg GND vio B mac GND LPC Connector LPC Connector VIO B M2C Figure 3 1 FMC HPC Connector Pin Layout from VITA 57 1 Rev 2 01 TOKYO ELECTRON DEVICE LIMITED 8 inreviunW 4 Block Diagram Figure 4 1 shows the TB FMCH 12GSDI block diagram The FMC HPC main connector is mounted on the component side of the board The FMC HPC extender connector is mounted coincident with the main connector on the opposite side of the board Voltage level translators are not shown in the

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