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USER`S MANUAL

1. 13 2 Timer DO Function Description 13 3 Blok Diagrami asiar 13 6 8 Bit mer PEE EE 13 7 OVGIVIOW dt 13 7 Timer D1 Control Register 13 8 Timer D1 Function Description nana a aa san trn nen trenes nnns 13 9 Block Diagram x 13 12 14 Watch Timer COVER VIG W retis tees ree Secon o ett bcr edt A A 14 1 Watch Timer Control Register WTCON sssssssssssseeneneene enne en nennen nnns nn tren nennen nsns 14 2 Watch Timer Circuit 14 3 viii S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER Table of Contents Continued Chapter 15 LCD Controller Driver eect pesce etu LCD RAM Address LCD Control Register 1 Internal Resistor Bias Pin Connection Common COM Signals Segment SEG Signals Chapter 16 10 bit Analog to Digital Converter IIIA E FUNCTION Description eet e PDA EH RE Rr ER RADAR EUM AER REED GONVELSION osea ere A Te p
2. 15 7 15 7 Select No Select Signal 1 3 Duty 1 3 Bias Display 15 7 15 8 LCD Signal Waveforms 1 2 Duty 1 2 15 8 15 9 LCD Signal Waveforms 1 3 Duty 1 3 15 9 15 10 LCD Signal Waveforms 1 4 Duty 1 3 Bias 15 10 15 11 LCD Signal Waveforms 1 8 Duty 1 4 15 11 S3F84UA F84U8 UM REV1 10 MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 16 1 A D Converter Control Register 16 2 16 2 A D Converter Data Register 16 3 16 3 A D Converter Functional Block Diagram sse 16 4 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 5 17 1 Serial Module Control Registers 17 2 17 2 SIO Pre scaler Register SIOPS 1 17 3 17 3 SIO Functional Block Diagram enne nenne 17 3 17 4 Serial I O Timing Transmit Receive Mode Tx at falling SIOCON 4 0 17 4 17 5 Serial I O Timing Transmit Receive Mode Tx at rising SIOCON 4 1 17 4 18 1 UART 0 High Byte Control Register UARTOCONH 18 3 18 2 UART 0 Low Byte Contro Register 18 4 1
3. 4 43 Timer Control 4 44 Timer C Control 4 45 TDOCON Timer DO Control 1 4 46 TD1CON Timer D1 Control Registers 4 47 UARTOCONH UART 0 Control Register High 4 48 UARTOCONL UART 0 Control Register Low 4 49 UART1CONH UART 1 Control Register High 4 50 UART1CONL UART 1 Control Register LOW Byte 2 nenne 4 51 WTCON Watch Timer Control 4 52 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER List of Instruction Descriptions Instruction Full Register Name Mnemonic ADC Add with Garry aiios ite dee ru Bag eae edle dg dt ADD M Le n E uS AU AND Logical AND x23 BAND BIEAND ftne aca nantes BCP qe tm eee tio BITC Bit Gomplement cte tete t e aie BITR Rea eate ta ae Ten BITS a ee Bit OR anie ite aa Meet BTJRF Bit Test Jump Relative on BTJRT Bit Test Jump Relative on BXOR
4. 22 7 22 5 LVR Low Voltage Reset 22 9 22 6 Serial Data Transfer Timing sess enne 22 10 22 7 Waveform for UART Timing 22 11 22 8 Timing Waveform for the UART 22 12 22 9 Clock Timing Measurement al 22 14 22 10 Clock Timing Measurement at XT o rola REOR o 22 14 22 11 Operating Voltage 22 15 23 1 Package Dimensions 44 10108 23 1 23 2 Package Dimensions 42 5 600 23 2 24 1 S3F84UA F84U8 Pin Assignments 44 1010 24 2 24 2 SSF84UA F84U8 Pin Assignments 42 50 600 24 3 24 3 AC Delays EE 24 4 24 4 PCB Design Guide for Board 24 5 25 1 Emulator Product Configuration 25 2 25 2 TB84UA 8 Target Board Configuration 25 3 25 3 50 Pin Connectors J101 for 25 6 25 4 50 Pin Connectors J102 for TB84UAVJ8 2 25 7 25 5 S3E4U0 Cables for 42 SDIP 25 8 25 6 S3E4U0 Cables for 44 QFP 25 8 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER xvii List of Ta
5. 2 2 16 4 Bit Working Register Addressing 22 22 4 0 2 17 8 Bit Working Register Addressing 2 19 System and User Stack iei sere n ih i tite ER Esa 2 21 S3F84UA F84U8 UM REV1 10 MICROCONTROLLER Table of Contents Continued Chapter 3 Addressing Modes e e 3 1 Register Addressing Mode 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode X eee 3 7 Direct Address Mode D J arai ii ea 3 10 Indirect Address Mode 2 24422 A NNa nnne senate nnne 3 12 Relative Address Mode 1 nn ns en nnns 3 13 immediate Mode Mirer 3 14 4 Control Registers QNI ig Sadie leds AP aa eee 4 1 Chapter 5 Interrupt Structure OVERVIOW nta ath a a Dd AM UP ta daha ER 5 1 Interrupt 5 2 SSF84UA F84U8 Interrupt Structure
6. P3 2 External Interrupt S W F6H P3 3 External Interrupt S W F8H P3 4 External Interrupt S W FAH P3 5 External Interrupt S W FCH P3 6 External Interrupt S W P3 7 External Interrupt S W IRQO IRQ3 NOTES 1 Within a given interrupt level the low vector address has high priority For example CEH has higher priority than DOH within the level IRQO the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 SSF84UA F84U8 Interrupt Structure 5 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S8F84UA F84U8 interrupt structure are stored in the vector address area of the internal 48 Kbyte ROM OH BFFFH or 8 Kbyte ROM OH 1FFFH see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 49 151 ELECTRONICS 48K bytes Internal Program Memory Area Available ISP Sector Area S3F84UA Decimal 8 191 8K bytes Internal Program Memory Area Available ISP Sector Area
7. Pasa Alternative function LCD signal Output mode 4 26 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER P3INTH Port 3 Interrupt Control Register High Byte E6H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 External interrupt INT7 Enable Bits 5 4 3 2 P3 5 External interrupt INT5 Enable Bits 9 o io Embemempibytenpeke 1 0 P3 4 External interrupt 4 Enable Bits fo Disable interrupt Enable interrupt by falling edge ESL Enable interrupt by rising edge Enable interrupt by both falling and rising edge ELECTRONICS 4 27 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 P3INTL Port Interrupt Control Register Low Byte E7H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 External interrupt Enable Bits Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge 1 Enable interrupt by both falling and rising edge 5 4 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge 3 2 P3 1 External interrupt INT1 Enable Bits Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge D
8. 19 10 19 9 Timing Diagram for Serial Port Mode Operation 19 11 19 10 Connection Example for Multiprocessor Serial Data Communications 19 13 20 1 Pattern Generation enne nennen nennen nennen ns 20 1 20 2 Pattern Generation Control Register 20 2 20 3 Pattern Generation Circuit 20 2 xvi S3F84UA F84U8 UM 1 10 MICROCONTROLLER List of Figures continued Figure Title Page Number Number 21 1 Flash Memory Control Register 21 3 21 2 Flash Memory User Programming Enable Register 21 4 21 3 Flash Memory Sector Address Register High Byte FMSEQCH 21 5 21 4 Flash Memory Sector Address Register Low Byte FMSECL 21 5 21 5 Program Memory Address 21 6 21 6 Sector Configurations in User Program 21 8 22 1 Input Timing for External Interrupts essen 22 5 22 2 Input Timing for 22 5 22 3 Stop Mode Release Timing Initiated by nRESET 22 7 22 4 Stop Mode Release Timing Initiated by
9. 2 RB8 Only when UARTOCONL 7 0 Location of the 9 data bit that was received in UART 0 mode 2 or 3 0 or 1 NOTE Ifthe UARTOCONL 7 1 This bit is don t care 1 Uart 0 Receive Interrupt Enable Bit Disable Rx interrupt Enable Rx interrupt 0 Uart 0 Receive Interrupt Pending Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read NOTES 1 In mode 2 and 3 if the MCE bit is set to 1 then the receive interrupt will not be activated if the received 9 data bit 0 In mode 1 if MCE 1 the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 4 48 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER UARTOCONL UART Control Register Low Byte EFH Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 3 2 ELECTRONICS 7 6 6 4 8 gt 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only UART 0 Transmit Parity bit Auto Generation Enable Bit Disable parity bit auto generation Enable parity bit auto generation UART 0 Transmit Parity bit Selection Bit for modes 2 and 3 only Even parity bit Odd parity bit NOTE If the UARTOCONL 7 0 This bit is don t care
10. P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 PNE3 bit configuration settings 0 Push pull output mode Open drain output mode Figure 9 13 Port 3 N Channel Open drain Mode Register ELECTRONICS 9 13 PORTS S3F84UA F84U8_UM_REV1 10 PORT 4 Port 4 is an 8 bit port with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location F4H in set 1 bank 1 4 0 4 7 can serve as inputs with or without pull ups and outputs push pull or open drain And the P4 7 P4 0 can serve as segment pins for LCD or you can configure the following alternative functions Low byte pins 4 0 4 3 TCOUT TBPWM TACLK TACAP TAOUT TAPWM High byte pins 4 4 4 7 TxD1 RxD1 RxDO Port 4 Control Register P4CONH P4CONL Port 4 has two 8 bit control registers for P4 4 P4 7 and PACONL for P4 0 P4 3 A reset clears the PACONH and PACONL registers to configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors select push pull or open drain output mode and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 4 control registers must also be enabled in the associated peripheral module Port 4 Pull up Resistor Enable Register PAPUR Using
11. 5 3 Interrupt Vector Addresses ot eee ee Tene eee de ait 5 5 Enable Disable Interrupt Instructions El 5 7 System Level Interrupt Control Registers enne ennt nennen 5 7 Interrupt Processing Control nennen snnt innen ns 5 8 Peripheral Interrupt Control Registers eee 5 9 System Mode Register 2 4 4 1 1100 00000 entes nennt sinn Ane aai EE Taa AE ia 5 11 Interrupt Mask Register IMR meatair aA a a nnne EN nennen 5 12 Interrupt Priority Register UP Riran sah dane eee e oe dde eet te ea 5 13 Interrupt Request Register 2 00 5 15 Interrupt Pending Function 5 16 Interrupt Source Polling 0 nsn nnns intres 5 17 Interrupt Service ROUIIDes 5 17 Generating Interrupt Vector 04 002 00 5 18 Nesting Of Vectored Interrupts nen tenens nnns inten trennt 5 18 Instruction nd Pendet d Tee tte e dt Pee ire dl ee 5 18 Fast interrupt Proces
12. O6 DO5 004 003 002 001 000 Transmit pes N Complete U Set SIOCON 3 Figure 17 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit IRQ4 N Complete E Set SIOCON 3 Figure 17 5 Serial I O Timing Transmit Receive Mode Tx at rising SIOCON 4 1 17 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 UART 0 OVERVIEW The UART 0 block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Serial with baud rate of fy 16 x 1 8 bit UART mode variable baud rate 9 bit UART mode fy 16 9 bit UART mode variable baud rate UART 0 receive and transmit buffers are both accessed via the data register UDATAO is set 1 bank 0 at address FOH Writing to the UART data register loads the transmit buffer reading the UART 0 data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received one of the bytes will be lost In all operating modes transmission is started when any instruction usually a write operation uses the UDATAO register as its destination address In mode 0 serial dat
13. 7 6 Switching the CPU CloCK e ettet t a paste ti EL 7 7 Chapter 11 8 bit Timer To Generate 38 kHz 1 3 duty signal through P4 1 11 11 To Generate one pulse signal through 11 12 Chapter 20 PATTERN GENERATIONMODULE Using the Pattern Generation 20 3 Chapter 21 Embedded Flash Memory Interface Sector Erase cinia aevi tet iet ie ise dud qa o TO 21 9 Mes rp I EP LE 21 11 Reading EE 21 12 21 13 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER xxi List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Register 2 4 5 Basic Timer Control 2 4 enne 4 6 CLKCON System Clock Control 1 2 4 7 FLAGS Set 98 2 ti 4 8 FMCON Flash Memory Control Register 0000000 eene nnns 4 9 FMSECH Flash Memory Sector Address Register High Byte 4 10 FMSECL Flash Memory Sector Address Register Low 4 10 FMUSR Flash Memor
14. S3F84UA S3F84U8 Figure 21 5 Program Memory Address Space 21 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTERFACE Table 21 1 ISP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size oS qp ox J x j Jp 0 AJ oeme Seve Pot 10 8 1 208 Byes NOTE The area of the ISP sector selected by Smart Option bit 003 2 00 0 can not be erased and programmed by LDC instruction in User Program mode ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setting the ISP Enable Disable bit to 0 and the Reset Vector Selection bit to O at the Smart Option you can choose the reset vector address of CPU as shown in Table 19 2 by setting the ISP Reset Vector Address Selection bits Table 21 2 Reset Vector Address Smart Option 003EH Reset Vector Usable Area for ISP Sector Size ISP Reset Vector Address Selection Bit Address After POR ISP Sector Bu ss oH s o s e 1 e 1 5 e 3 NOTE The selection of the ISP reset vector address by Smart Option 003EH 7 00 5 is not dependent of the selection of ISP sector size by Smart Option 003 2 003EH 0 ELECTRO
15. 5 5 4 12 MHz XN frequency i B mew XOUT Ceramic Main oscillation 2 7 V 5 5 V A Oscillator XN frequency m sp External Xin input frequency 2 7V 5 5 Clock 2 0V 5 5V Frequency Table 22 11 Sub Oscillation Characteristics TA 25 to 85 C Clock Configuration Parameter Crystal Sub oscillation 20 5 5 frequency External XT y input 2 0 V 5 5V clock frequency ELECTRONICS 22 13 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 12 Main Oscillation Stabilization Time TA 40 C to 85 C Vpp 2 0 V to 5 5 V Oscillator Test Condition Crystal fx gt 1 MHz Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range Ceramic External clock Xin input high and low width tq Figure 22 9 Clock Timing Measurement at X Table 22 13 Sub Oscillation Stabilization Time TA 40 to 85 Vpp 2 0 V to 5 5 V Aw Figure 22 10 Clock Timing Measurement at XT 22 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Instruction Clock Main oscillation frequency 12 0 MHz 1 05 MHz 100 kHz main 8 2 Hz sub 400 kHz main 32 8 kHz sub 2V 27 Supply Voltage V Minimum instruction clock 1 4n x oscillator frequency n 1 2 8 16 Figure 22 11 Operating Voltage Range Table 22 14 Internal Flash ROM El
16. Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3F84UA F84U8 MICROCONTROLLER The S3F84UA F84U8 single chip CMOS One 8 bit basic timer for oscillation stabilization microcontrollers are fabricated using the highly and watchdog functions system reset advanced CMOS process based on Samsung s Three 8 bit timer counter and two 16 bit newest CPU architecture timer counter with selectable operating modes The S3F84UA S3F84U8 are a microcontroller with a Watch timer for real time 48K byte 8K byte Flash ROM embedded LCD Controller driver respectively A D converter with 8 selectable input pins The S3F84UA is a microcontroller with a 48K byte Synchronous SIO modules Flash ROM embedded Two asynchronous UART modules The S3F84U8 is a microcontroller with a 8K byte Pattern generation module Flash ROM embedded Using a proven modular design approach Samsung They are currently available in 44 pin QFP and 42 engineers have successfully developed the pin SDIP package S3F84UA F84U8 by integrating the following peripheral modules with the powerful SAM8 core Five programmable ports including four 8 bit ports and one 4 bit port for a total of 36 pins E
17. Figure 1 1 Block Diagram S3F84UA F84U8_UM_REV1 10 Watch dog Timer Basic Timer Watch Timer BUZ P3 0 INTO SEG6 P0 0 P0 7 PG0 PG7 Poto lt ADO AD7 P1 0 P1 1 XTOUT XTIN VO Pott __ 512 13 lt gt P2 0 P2 1 COM0 COM1 VO Pot2 2 2 2 7 2 7 SEGO SEG5 P3 0 SEG6 INTO BUZ P3 1 SEG7 INT1 SO P3 2 SEG8 INT2 SI P3 3 SEG9 INT3 SCK lt gt P3 4 SEG10 INT4 TD1CLK P3 5 SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 6 SEG12 INT6 TDOCLK P3 7 SEG13 INT7 TDOOUT TDOPWM TDOCAP Port 3 P4 0 SEG14 TCOUT TCPWM P4 1 SEG15 TBPWM P4 2 SEG16 TACLK P4 3 SEG17 TAOUT TAPWM TACAP P4 4 SEG18 TXD1 P4 5 SEG19 RXD1 P4 6 SEG20 TXDO P4 7 SEG21 RXDO TxDO P4 6 SEG20 UARTO RxDO P4 7 SEG21 gt TxD1 P4 4 SEG18 UARTI RxD1 P4 5 SEG19 Port 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW PIN ASSIGNMENT cv L1 vav vod v Od sav sod s od 7 94 95 9 0 65 04 LeO3S 0QXuH Z S F 02945 00 1 9 te 71 6L93S LOXu S vd 8 1 d3uAV 46 L3 3392AI P0 3 PG3 AD3 P0 2 PG2 AD2 P0 1 PG1 AD1 P0 0 PGO ADO VDD VSS SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP P4 3 SEG16 TACLK P4 2 S3F84UA SEG15 TBPWM P4 1 SEG14 TCOUT TCPWM P4 0 S3 F8 4U 8 SEG13 INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INT6 TDOCLK P3 6 44 QFP 1010B SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 5 SEG10 INT4 TD1CLK P3 4 SEG9 INT3 SCK P3 3 SEG
18. Sub oscillator control OSCCON O register settings select Main clock or Sub clock as system clock After a reset Main clock is selected for system clock because the reset value of OSCCON O is The main oscillator can be stopped or run by setting OSCCON 3 The sub oscillator can be stopped or run by setting OSCCON 2 Oscillator Control Register OSCCON FAH Set 1 Bank 0 R W System clock selection bit 0 Main oscillator select 1 Sub oscillator select Not used for S3F84UA 8 Not used for S3F84UA 8 Sub system oscillator control bit 0 Sub oscillator RUN 1 Sub oscillator STOP Main system oscillator control bit 0 Main oscillator RUN 1 Main oscillator STOP Figure 7 8 Oscillator Control Register OSCCON ELECTRONICS 7 5 CLOCK CIRCUIT S3F84UA F84U8_UM_REV1 10 STOP CONTROL REGISTER STPCON The STOP control register STPCON is located in the bank 0 of set1 address EDH It is read write addressable and has the following functions Enable Disable STOP instruction After a reset the STOP instruction is disabled because the value of STPCON is other values If necessary you can use the STOP instruction by setting the value of STPCON to 10100101B STOP Control Register STPCON EDH Set 1 bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before executing the STOP instruction set the STPCON register as 1010010
19. 7 5 7 9 STOP Control Register STPCON ssesssssssssseseenenneeeen nennen nnns 7 6 9 1 Port 0 High Byte Control Register 9 4 9 2 Port 0 Low Byte Control Register 9 5 9 3 Port 0 Pull up Resistor Enable Register 9 5 9 4 Port 1 Control Register 9 6 9 5 Port 2 High Byte Control Register 2 0 9 7 9 6 Port 2 Low Byte Control Register P2CONL sse 9 8 9 7 Port High Byte Control Register sees 9 10 9 8 Port Low Byte Control Register PSCONL sese 9 10 9 9 Port High Byte Interrupt Control Register 9 11 9 10 Port Low Byte Interrupt Control Register 9 11 9 11 Port Interrupt Pending Register 9 12 9 12 Port 3 Pull up Resistor Enable Register 9 12 9 13 Port N Channel Open drain Mode Register 9 13 9 14 Port 4 High Byte Control Register sse 9 14 9 15 Port 4 Low Byte Control Register 9 15 9 16 Port 4 Pull up Resistor Ena
20. E ACON 2 Lower level when TAOVF data counter 8 Bit Comparator Figure 11 3 Simplified Timer A Function Diagram PWM Mode 11 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER A B Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the values of the timer A capture input selection bits in the port 4 control register PACONL 7 6 set 1 bank 1 When 4 7 6 is 00 the TACAP input is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin see Figure 11 4 TAOVF IRQO 8 Bit Up Counter INTPND O Overflow INT Interrupt Enable Disable TACON 1 TAINT IRQO INTPND 1 Capture INT Match Signal Pending TACON 4 3 4 3 Timer Data Register Figure 11 4 Simplif
21. ELECTRONICS 2 3 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 REGISTER ARCHITECTURE In the SSF84UA F84U8 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3F84UA the total number of addressable 8 bit registers is 631 Of these 631 registers 13 bytes are for CPU and system control registers 22 bytes are for LCD data registers 68 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 512 registers are for general purpose use 0 1 in case of S3F84U8 page 0 You can always address set 1 register locations regardless of which of the ten register pages is currently selected Set 1 location however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3F84UA Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register area two 192
22. uei ste oi eite itte tede ez CALL Call Proced te ERES CCF Complement Carry et une 2 ena aed Hide Ld equ Lr Compare Increment and Jump on CPIJNE Compare Increment and Jump DA Decimal AdjUSt o iet dq d DEC DECW Decremoent Word ia DI Disable Interrupts thc teet ae etes DIV Divide Unsigned a ie eee Ae he ee ae ne DJNZ Decrement and Jump if 2 Enable INtSrru pts aut ENTER IOs dedu IDLE Idle Operation Tt o re dier Incremento eret teet INCW Inerement WOM er Hr aS IRET Interrupt cece ue ded JP Jump d E eed ag dete ee Ae i ae E eg E JR ee E LD Coad aee reer ER T E LDB ERSTER ERN EE S3F84UA F84U8 UM REV1 10 MICROCONTROLLER XXV List of Instruction Descriptio
23. 4 28 PSPND Port 3 Interrupt Pending Register sese 4 29 P3PUR Port Pull up Resistor Enable 4 30 Port 3 N channel Open drain Mode 4 31 P4CONH Port 4 Control Register High 4 32 P4CONL Port 4 Control Register Low 4 33 P4PUR Port 4 Pull up Resistor Enable 4 34 PNE4 Port 4 N channel Open drain Mode 4 35 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER xxiii List of Register Descriptions Continued Register Full Register Name Page Identifier Number PGCON Pattern Generation Module Control 4 36 PP Register Page Pointer E nennen terrens nena 4 37 RPO Register Pointer Os taii i IR nea DESEE BEES XR TE 4 38 RP1 Register Pointer cate at 4 38 SIOCON SIO Gontrol Beglster 4 39 SPH Stack Pointer High Byte c a Rea e 4 40 SPL Stack Pointer LOW Byte oie eet auem es 4 40 STPCON Stop Control Register 4 ide aed dede i dac p dede aie de ed deus 4 41 SYM System Mode 4 42 Timer Control 1
24. ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority Group A 0 IRQO gt IRQ1 eee 1 IRQ1 gt IRQO 0 Undefined Group B 1 gt gt 0 IRQ2 gt IRQ3 IRQ4 0 A gt B gt C 1 IRQ4 gt IRQ2 1 gt gt Subgroup 0 gt gt 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ4 gt IRQ3 0 gt gt 1 Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register IPR 5 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all
25. ELECTRONICS 6 59 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 NEXT next NEXT Operation Flags Format Example Address 0120 0120 44 Address L lt IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 The following diagram shows example of how to use the NEXT instruction Before After Data Address Data 43 Address H 44 Address L 45 Address H Address 43 45 Address H 120 130 Routine Memory Memory ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source o
26. ELECTRONICS 7 1 CLOCK CIRCUIT S3F84UA F84U8_UM_REV1 10 MAIN OSCILLATOR CIRCUITS SUB OSCILLATOR CIRCUITS 32 768 kHz XIN XTour XIN XTIN XOUT XTOUT Figure 7 2 External Oscillator fx Figure 7 5 External Oscillator fxt XIN R XOUT Figure 7 3 RC Oscillator fx 7 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock n Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Sub system Watch Timer Oscillator Oscillator Circuit Circuit LCD Controller Selector 1 fxx OSCCON 3 OSCCON 0 STOP OSC 1 1 1 4096 l inst Basic Timer Frequency Timer Counters A B C 00 01 1 SIO 1 1 1 d 1 ividi Watch Ti STPCON gt Dividing atch Timer Circuit UART 0 1 cLKCON 4 3 Selector 2 LCD Controller 1 1 1 2 1 8 1 16 A D Converter CPU Clo
27. Mode 1 and baud rate fy 16 x BRDATA1 1 ELECTRONICS 19 5 UART 1 S3F84UA F84U8_UM_REV1 10 Table 19 1 Commonly Used Baud Rates Generated by BRDATA1 Baud Rate UART Clock fy BRDATA1 Decimal Hexadecimal 19 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 1 BLOCK DIAGRAM Data Bus UDATA1 Baud Rate Generator Zero Detector Write to 1 Star UART1CONL 3 2 Tx Control Tx Clock TIP IRQ5 Interrupt Rx Clock RIP Receive Rx Control Shift Transition Detector Shift Value UDATA1 Data Bus Figure 19 5 UART 1 Functional Block Diagram ELECTRONICS 19 7 UART 1 S3F84UA F84U8_UM_REV1 10 UART 1 MODE 0 FUNCTION DESCRIPTION In mode 0 UART 1 is input and output through the RxD1 P4 5 pin and TxD1 P4 4 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 2 Setthe UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 3 Select mode 0 by setting UART1CONH 7 and 6 to 4 Write transmission data to the shift register UDATA1 F4H set 1 bank 0 to start the transmission operation Mode 0 Receive Procedure Select the UART 1 clock UART1CONL 3 and 2 Set the UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 Selec
28. Unaffected Unaffected ITO lt ONO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb 0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register O1H 05H BAND 01H 1 R1 5 Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101 and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 BCP Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to O Undefined Unaffected Unaffected IOSONO Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b i
29. and zero LSB determine whether to write one both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement 68H sets RP1 to 68H ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 SU B subtract SUB dst src Operation dst lt dst src The sou
30. seen 9 2 9 2 Port Data Register 9 3 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER xix Table Number 18 1 19 1 XX List of Tables continued Title Page Number Commonly Used Baud Rates Generated by 18 6 Commonly Used Baud Rates Generated by 1 19 6 ISP SectorSIZ8 uod e uus 21 7 Reset Vector Address 21 7 Absolute Maximum 22 2 D C Electrical Characteristics 4 4 0 0000 0 22 2 A C Electrical Characteristics 444 4000 0 22 5 Input Output Capacitance 4 22 6 Data Retention Supply Voltage in Stop 22 6 A D Converter Electrical Characteristics eese 22 8 Low Voltage Reset Electrical Characteristics 22 9 Synchronous SIO Electrical Characteristics sse 22 10 UART Timing Characteristics in Mode 0 12 0MHZz 22 11 Main Oscillator Characteristics 22 13 Sub Oscillation Characteristics 22 13 Main Oscill
31. Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations using working register addressing mode only Examples 1 10 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H _ the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 C3H gt 3 45 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 five high order bits in the register pointer select an 8 byte slice of the register space three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 13 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from th
32. RW Location FCH is not mapped 229 R Location FEH is not mapped Interrupt Priority Register PR 25 _ RW 208 209 224 225 226 227 228 229 230 231 232 233 34 35 236 237 38 39 40 241 42 43 44 245 246 47 248 4 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers Register Name Mnemonic 4 ister ister Port 3 Interrupt Control Register High Byte Port 3 Interrupt Control Register Low Byte P3INTL Port 3 Interrupt Pending Register P3PND 3 4 Port 3 Pull up Resistor Enable Register P3PUR Port 4 Control Register High Byte P4CONH Port 4 Control Register Low Byte P4CONL 20 20 22 22 22 22 22 22 23 23 23 23 23 23 23 2 2 2 PonODataRegsier 74 24 24 24 24 24 24 25 25 252 25 25 5 i Timer DO Data Register High Byte TDODATA Timer DO Data Register Low Byte TDODATAL Timer DO Control Register TDOCON Timer D1 Control Register TD1CON i i i 8 9 5 6 7 8 9 0 1 2 5 6 7 8 9 0 1 7 1 Timer D1 Counter Register High Byte TD1CNTH Timer D1 Counter Register Low Byte TDICNTL Timer D1 Data Register High Byte TD1DATAH Timer D1 Data Register Low Byte TD1DATAL 255 i Timer DO Counter Register Low Byte TDOCNTL 5 6 8 9 0 3 ELECTRONICS 4 3 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 Bit number s that is are
33. S3F84U8 Figure 5 3 ROM Vector Address Area 5 5 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 Table 5 1 Interrupt Vectors Vector Address Interrupt Source Value Value Level Level 206 CEH Timer A match capture 0 208 Timer overflow Eu 1 mo om ma b _ TimerCmatchioverfow _ mo v 216 D8H Timer DO match capture IRQ3 218 DAH Timer DO overflow y y 220 DCH Timer D1 match capture 222 Timer D1 overflow Y V 228 E4H SIO interrupt IRQ4 232 E8H UART 0 data transmit IRQ5 234 UART 0 data receive 236 ECH UART 1 data transmit 238 EEH UART 1data receive 240 FOH P3 0 external interrupt 242 P3 1 external interrupt 244 P3 2 external interrupt 246 P3 3 external interrupt 248 P3 4 external interrupt IRQ7 250 P3 5 external interrupt 252 P3 6 external interrupt P3 7 external interrupt NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware N O on O o e lt 2 2 2 2 2 2 2 E 5 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS DI Execut
34. enne nennen 18 9 Serial Port Mode 2 Function Description nennen nennen 18 10 Serial Port Mode 3 Function Description eene nnne nnns 18 11 Serial Communication for Multiprocessor Configurations 4 2 0 18 12 Chapter 19 UART 1 NI ML 19 1 Programming 19 1 UART 1 High byte Control Register 1 1 enne nennen nnne 19 2 UART 1 Low byte Control Register UART1CONL essent 19 2 UART 1 Interrupt Pending Dits eee 19 4 UART 1 Data Register 19 5 UART 1 Baud Rate Data Register 19 5 BAUD R te Calculations ic 2 reir e paca HET Ro 19 5 EC 19 7 UART 1 Mode 0 Function nennen sn nnne nns 19 8 Serial Port Mode 1 Function nnne 19 9 Serial Port Mode 2 Function Description nennen nennen 19 10 Serial Port Mode Function Description 19 11 Serial Communication for Multiprocessor Configurations 2 19 12 Chapter 20 Pattern Generation Module eil M MH M 20 1 Pattern Generation Flow ent tc et e te cea e de cep de diu cte a rad 20 1 Pattern Generatio
35. 0 Timer D1 Counter Register Low Byte 253 Fon o 0 0 NOTES 1 An x means that the bit value is undefined following reset 2 dash means that the bit is neither used nor mapped but the bit is read as 0 8 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts for more details see Figure 7 6 NOTE Do not use stop mode if you are using an external clock source because XT y input must be restricted internally to Vgs to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routi
36. 0000 src 0000 dst 0001 src 0001 X X a XL XL DA DA DA DA DA Cycles 10 10 12 12 14 14 14 14 14 14 Opcode Hex C3 D3 E7 F7 A7 B7 A7 B7 A7 B7 Addr Mode dst sre r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 Forformats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET LDC LDE Load Memory LDC LDE Examples Continued Given RO 11H R1 34H R2 O1H R3 04H Program memory locations 0103H 0104H 1 0105 6DH and1104H 88H External data memory locations 0103 5FH 0104H 2AH 0105H 7DH and1104H 98 LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 04H LDC note RR2 RO 11H contents of RO is loaded into progr
37. 8 Bit Up Counter lt TAINT IRQO INTPND 1 8 Bit Comparator INTPND 1 Match INT Pending Timer A Buffer Register TACON 4 3 Match Sorel N E TACON TAOVF Timer A Data Register Figure 11 2 Simplified Timer A Function Diagram Interval Timer Mode ELECTRONICS 11 3 8 BIT TIMER S3F84UA F84U8_UM_REV1 10 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tc x 256 see Figure 11 3 0 Capture Signal Interrupt Enable Disable 8 Bit Up Counter lt INTPND O p TACON 1 Overflow INT TAINT IRQO INTPND 1 Match INT Pending TAPWM Output Match Signal data gt counter N
38. COM2 SEGO P2 2 S3F84UA S3F84U8 42 SDIP 600 S3F84UA F84U8 FLASH MCU SEG21 RXDO P4 7 SEG20 TXDO0 P4 6 SEG19 RXD1 P4 5 SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP P4 3 SEG16 TACLK P4 2 SEG15 TBPWM PA 1 SEG14 TCOUT TCPWM P4 0 SEG13 INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INT6 TDOCLK P3 6 SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 5 SEG10 INT4 TD1CLK P3 4 SEG9 INT3 SCK P3 3 SEG8 INT2 SI P3 2 SEG7 INT1 SO P3 1 SEG6 INT0 BUZ P3 0 COM7 SEG5 P2 7 COM6 SEG4 P2 6 COMBS SEG3 P2 5 COM4 SEG2 P2 4 COM3 SEG1 P2 3 Figure 24 2 S3F84UA F84U8 Pin Assignments 42 SDIP 600 ELECTRONICS 24 3 S3F84UA F84U8 FLASH MCU S3F84UA F84U8_UM_REV1 10 Table 24 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip Programming Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port SCLK sa pe Serial clock pin Input only pin Tool mode selection when TEST Vpp pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 etc user should be connected TEST Vpp pin to SSF84UA F84U8 supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET 12 18 Chip Initialization IVCREF IVCREF A capacitor 0 1uF must be connected between IVCngr and Vss Vpp Vss Vpp Vss Power supply pin for logic circuit Vp should be 512 tied to 5V during programming NOTE
39. Hex Normal 1 10 12 internal stack IRET Bytes Cycles Opcode Hex Fast 1 6 In the figure below the instruction pointer is initially loaded with 100H the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a Clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc istrue PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is execute
40. O O L ON 10 D9UUOD 06 DEVELOPMENT TOOLS PE P1 2 P1 3 F4 P0 4 PG4 AD4 L3 P0 5 PG5 AD5 L3 P0 6 PG6 AD6 L3 P0 7 PG7 AD7 L3 AVREF VCREF L3 SEG21 RXDO P4 7 SEG20 TXD0 P4 6 FI SEG19 RXD1 P4 5 SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP PA 3 SEG16 TACLK P4 2 SEG15 TBPWM P4 1 L3 SEG14 TCOUT TCPWM P4 0 E3 SEG13 INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INTe TDOCLK P3 6 SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 5 1 SEG10 INTA TD1CLK P3 4 SEG9 INT3 SCK P3 3 7 SEGS INT2 SI P3 2 N C FI N C FF N C Figure 25 4 50 Pin Connectors J102 for TB84UA 8 ELECTRONICS 25 7 DEVELOPMENT TOOLS S3F84UA F84U8_UM_REV1 10 Target System J101 Target Board J101 Target Cable for 50 Pin Connectors 510 06 5 10 Uld 0S Figure 25 5 S3F84U0 Cable for 42 5 Package Target Board Target System J102 J102 Target Cable for 50 Pin Connectors 5101990009 Uld 0S 2 I 5 9 7 O o 3 3 a Figure 25 6 S3F84U0 Cable for 44 QFP Package 25 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 DEVELOPMENT TOOLS THIRD PARTIES FOR DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In
41. and 3 The types differ in the number of vectors and interrupt Sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S 5 Type 3 One level IRQn multiple vectors V V multiple sources S4 8 4 Spam In the SSF84UA F84US8 microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 81 1 2 2 3 1 3 9 1 number of Sn and Vn value is expandable 2 Inthe SSF84UA 8 implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE S3F84UA F84U8 INTERRUPT STRUCTURE The S3F84UA F84U8 microcontroller supports twenty two interrupt sources All twenty two of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of
42. bank 0 to start the transmit operation Mode 2 Receive Procedure Select the UART 0 clock UARTOCONL 3 and 2 2 Setthe UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 3 Select mode 2 and set the receive enable bit RE in the UARTOCONH register to 1 4 The receive operation starts when the signal at the RxDO P4 7 pin goes to low level Write to Shift Register Snit E JL TL start Bit X D1 02 03 x D4 05 X D6 D7 TB8 Stop Bit _ Transmit TIP Pete peser TI a RIP Figure 18 8 Timing Diagram for Serial Port Mode 2 Operation 18 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 SERIAL PORT MODE 3 FUNCTION DESCRIPTION UART 0 In mode 3 11 bits are transmitted through the TxDO P4 6 pin or received through the RxDO P4 7 pin Mode 3 is identical to mode 2 except for baud rate which is variable Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 Mode 3 Transmit Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 2 Set the UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 3 Select mode 3 operation 9 bit UART
43. e Support Firmware upgrade US pro Portable Samsung OTP MTP FLASH Programmer e Portable Samsung OTP MTP FLASH Programmer e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices Convenient USB connection to any IBM compatible PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under various O S Windows 95 98 2000 XP Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com Flash writing adapter board e Standard flash writing socket 44QFP 42SDIP C amp A technology e TEL 82 2 2612 9027 e FAX 82 2 2612 9044 e E mail wisdom cnatech com e URL http www cnatech com ELECTRONICS 25 11
44. notion 0 3 2 P2 1 COM1 o o mumd Po input mode puke 1 AMemawefeon COsgl 1 0 P2 0 COMO o i mwm ERES Alternative function LCD signal Output mode push pull 4 24 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER P3CONH Port 3 Control Register High Byte E4H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 INT7 TDOOUT TDOPWM TDOCAP SEG13 5 4 Schmitt trigger input mode TDOCLK Not available Alternative function LCD signal 3 2 1 0 Schmitt trigger input mode TD1CLk Not available Alternative function LCD signal ELECTRONICS 4 25 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 P3CONL Port 3 Control Register Low Byte E5H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 INT3 SCK SEG9 0 0 Schmitttiggerinputmode SCK oo O _0 1 Alternative function SCK out 1 Alternative function LCD signal EN Output mode 5 4 P3 2 INT2 SI SEG8 Schmitt trigger input mode SI Not available Alternative function LCD signal 1 1 Output mode 3 2 P3 1 INT1 SO SEG7 7911 Atematvetuncion SO 7119 Memawetmebn CDsgn 1 0 P3 0 INTO BUZ SEG6 Fo 0 Fo r Memaw dogBug
45. varricone 43 FAH o o voaa 204 Fan x x x x x UART 1 Baud Rate Register roata 22 rsa 1 1 1 1 Fash Memory Secr Adress Register Wah Bro FMSECH 246 Fen o o o o o Fash Memory Secr Adress Register Low Bye FECL 247 F7H o o o o Fash Memory User Programming Regier FMusR 248 FAH o o o o o o o o Flash Memory Register FMcoN a8 FS o o o 9 Oscator ContolRegister 250 EAM 9 nterupt Pending Register remo si ren o o o o o o Location FCH is not mapped sron To Location is not mapped FPA x x x x x x x x ofo 144 4 ofo ofo ototo ara a ofo x x x x 1 ofo x x x x ofo ELECTRONICS 8 3 RESET and POWER DOWN S3F84UA F84U8_UM_REV1 10 Table 8 3 S3F84UA F84U8 Set 1 Bank 1 Register and Values after RESET Register Name Bit Values after RESET Dec Hex 7 Port 0 Pull up Resistor Enable Register POPUR 210 2 0 0 0 Port 2 Control Register High Byte P2CONH 224 0 0 0 Port 2 Control Register Low Byte P2CONL 225 E1H 0 0 O Port 1 Control Register High Byte 226 E2H Port 3 N Channel Open drain Mode Regi
46. 1 0 Detection Voltage Selection Bits Timer A match signal trigging Timer B overflow signal trigging lo Timer DO match signal trigging S W trigging 4 36 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER Register Page Pointer DFH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 0 0 pDestmtionpageo 0 0 o 1 Destination page 1 Not used forthe S3F84U8 Destination page 8 Not used for the S3F84UA F84U8 3 0 Source Register Page Selection Bits 0101010 Source pageo 7 0 0 0 1 Source page 1 Not used forthe 8328408 1 0 0 0 Source page 8 Not used for the S8F84UA F84U8 NOTES 1 In the S38F84UA microcontroller the internal register file is configured as three pages pages 0 1 8 The pages 0 1 are used for general purpose register file 2 Inthe 53 8408 microcontroller the internal register file is configured as two pages 0 8 The 0 is used for general purpose register file 3 The page 8 of S8F84UA F84U8 is used for LCD data register 30H 45H ELECTRONICS 4 37 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 RPO Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Registe
47. 1 Bank 0 R W Don t care Flash Memory Sector Address Low Byte NOTE low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 21 4 Flash Memory Sector Address Register Low Byte FMSECL ELECTRONICS 21 5 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program software Boot program code for upgrading application code by interfacing with I O port The ISPTM sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the Tool Program mode by Serial programming tools The size of ISP sector can be varied by settings of Smart Option You can choose appropriate ISP sector size according to the size of On Board Program software Decimal 49 151 Decimal 8 191 48K bytes Internal Program Memory Area 8K bytes Internal Program Memory Area Available Available ISP Sector Area ISP Sector Area 0 0 lt Byte Byte
48. 1 EFH PG Buffer 0 7 0 6 0 5 0 4 P0 3 P0 2 1 poo JUL JUL JU Software PGCON 3 Timer A match signal Timer B overflow signal Timer DO match signal Figure 20 3 Pattern Generation Circuit Diagram 20 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PATTERN GENERATION MODULE 85 Programming Using the Pattern Generation ORG 0000h ORG 0100h INITIAL SBO LD SYM 00h Disable Global Fast interrupt gt SYM LD IMR 01h Enable IRQO interrupt LD SPH 08 High byte of stack pointer gt SPH LD SPL 0FFh Low byte of stack pointer gt SPL LD BTCON 10100011b Disable Watch dog LD 00011000b Non divided fxx SB1 LD POCONH 01010101b Enable PG output LD POCONL 01010101b Enable PG output SBO EI MAIN NOP NOP SB1 LD PGDATA 101010106 PG data setting OR PGCON 000001006 Triggering by Timer A match then pattern data are output SBO NOP NOP JR T MAIN END ELECTRONICS 20 3 S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTERFACE 2 1 EMBEDDED FLASH MEMEORY INTERFACE OVERVIEW The S38F84UA F84U8 has an on chip flash memory internally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in a flash memory area any time you want The SSF84UA F84U8 s embedded 48K 8K bytes memory has two operating features as below User Program Mo
49. 1 Slave 2 Slave n S3F84UA S3F84UA S3F84UA S3F84UA S3F84U8 S3F84U8 S3F84U8 S3F84U8 Figure 19 10 Connection Example for Multiprocessor Serial Data Communications ELECTRONICS 19 13 S3F84UA F84U8_UM_REV1 10 PATTERN GENERATION MODULE PATTERN GENERATION MODULE OVERVIEW PATTERN GNERATION FLOW You can output up to 8 bit through 0 7 by tracing the following sequence First of all you have to change the PGDATA into what you want to output And then you have to set the PGCON to enable the pattern generation module and select the triggering signal From now bits of PGDATA are on the P0 0 P0 7 whenever the selected triggering signal happens Data write to PG DATA Triggering signal selection PGCON 7 0 Triggering signal generation Data output through 0 7 0 0 Figure 20 1 Pattern Generation Flow ELECTRONICS 20 1 PATTERN GENERATION MODULE S3F84UA F84U8_UM_REV1 10 Pattern Generation Module Control Register PGCON EEH Set 1 Bank 1 R W Detection voltage selection bit 00 Timer A match signal triggering 01 Timer B overflow signal triggering Not used for the S3F84UA 8 10 Timer DO match signal triggering 11 S W trggering PG operation disable enable selection bit 0 PG operation disable 1 PG operation enable S W trigger start bit 0 No effect 1 S W trigger start auto clera Figure 20 2 Pattern Generation Control Register PGDATA
50. 18 7 UART 0 S3F84UA F84U8_UM_REV1 10 UART 0 MODE 0 FUNCTION DESCRIPTION In mode 0 UART 0 is input and output through the RxDO P4 7 pin and TxDO P4 6 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 2 Setthe UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 3 Select mode 0 by setting UARTOCONH 7 and 6 to 00B 4 Write transmission data to the shift register UDATAO set 1 bank 0 to start the transmission operation Mode 0 Receive Procedure Select the UART 0 clock UARTOCONL 3 and 2 Set the UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 Select mode 0 by setting UARTOCONH 7 and 6 to 00B Clear the receive interrupt pending bit by writing 0 to UARTOCONH O Set the UART 0 receive enable bit UARTOCONH 4 to 1 The shift clock will now be output to the TxDO P4 6 pin and will read the data at the RxDO P4 7 pin UART 0 receive interrupt occurs when UARTOCONH 1 is set to 1 o gr Qv mw Write to Shift Register UDATAO Shift RxDO Data Out Do X D X pe X X w X TxDO Shift Clock Transmit Clear RIP and set RE Shift RxDO Data In 01 2 D3 D4 05 D6 D7 Tx
51. 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 INDIRECT REGISTER ADDRESSING MODE Concluded Register File MSB Points to RPO or RPO or Selected RP points to start of working register oe ee Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair E NN CERE References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This
52. COMO Figure 15 14 LCD Signal Waveforms 1 8 Duty 1 4 Bias Continued 15 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AVper and Vas values The A D converter has the following components Analog comparator with successive approximation logic D Aconverter logic resistor string type ADC control register ADCON Eight multiplexed analog data input pins 7 10 bit A D conversion data output register ADDATAH L 8 digital input port Alternately port AVper and pins FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set ADCEN signal for ADC input enable at port 0 the pin set with 1 can be used for ADC analog input And you write the channel selection data in the A D converter control register ADCON 4 6 to select one of the eight analog input pins ADO AD7 and set the conversion start or disable bit ADCON O The read write ADCON register is located set 1 bank 0 at address D2H The pins which are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 200H th
53. Characteristics Continued 40 C to 85 C Vpp 2 0 V to 5 5 V Supply current 1 1504 Run mode Vpp 5 0V Crystal oscillator C1 C2 22pF 22 Idle mode Vpp 5 0V Crystal oscillator C1 C2 22pF 4 liga Sub Operating mode 3 0V TA 25 C 32kHz crystal oscillator Sub Idle mode Vpp 3 0V 25 32kHz crystal oscillator 9 Stop mode 25 Vpp 5 0V 85 Vpp 5 0V 40 C to 85 Vpp 5 0V NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads 1501 and 152 include a power consumption of sub clock oscillation 2 lpps and are the current when the main clock oscillation stops and the sub clock is used 4 1605 S the current when the main and sub clock oscillation stops 5 Every value in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B 22 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Table 22 3 A C Electrical Characteristics 40 C to 85 C Vpp 2 0 V to 5 5 V Interrupt input high low tintH tint All interrupt Vpp 5 V 500 ns width P3 0 P3 7 NOTE f width of interrupt or reset pulse is greater than min value pulse is always recognized as valid pulse External
54. Electrical Characteristics TA 40 C to 85 Vpp 2 7 V to 5 5 V Parameter Symbol Resolution Total accuracy Integral linearity error ILE Vpp 9 120 V Differential linearity DLE Vss 0V error CPU clock 12 0 MHz Offset error of top EOT Offset error of bottom EOB Conversion time 1 Toon Analog input voltage VIAN Analog input Ran impedance Analog reference AVREF voltage Analog block current 2 Vpp 5 0 V Vpp 5 0 V 100 500 nA When power down mode NOTES 1 time is the time required from the moment a conversion operation starts until it ends 2 lapc is an operating current during A D converter 22 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Table 22 7 Low Voltage Reset Electrical Characteristics 40 C to 85 C 2 0 V to 5 5 V 25 C Vpp 2 4V rising 2 6 Vpp voltage off time Current consumption NOTE The current of LVR circuit is consumed when LVR is enabled by Smart Option Figure 22 5 LVR Low Voltage Reset Timing ELECTRONICS 22 9 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 8 Synchronous SIO Electrical Characteristics TA 40 C to 85 C Vpp 2 0 V to 5 5 V SCK Cycle time txcy ns SCK high low width m 500 SI setup time to SCK high 250 c u SI hold time to high em 400 Output delay
55. Figure 2 16 8 Bit Working Register Addressing Example 2 20 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S83F84UA F84U8 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 17 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 17 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP
56. IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 18 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When afast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the SSF84UA F84U8 microcontroller the service routine for any one of the eight interrupts levels IRQO IRQ7 can be selected fo
57. OOH ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET COM Complement COM dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 O7HandregisterO7H OF1H COM R1 gt R1 OF8H COM gt R1 07H register O7H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 CP Compare CP dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Setif a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S
58. SPL lt Normally the SPL is set to OFFH by the initialization routine Stack address OFEH Stack address OFDH Stack address OFCH Stack address OFBH TT TT PP RPO RP1 R3 R3 lt Stack address OFBH lt Stack address OFCH RPO lt Stack address OFDH Stack address OFEH ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that
59. Select the timer C operating mode fxx 1 amp PWM mode or fxx 64 amp interval mode Select the timer 3 bits prescaler Clear the timer C counter TCCNT Enable the timer C match overflow interrupt Start the timer C TCCON is located in set 1 Bank 0 at address ECH and is read write addressable using Register addressing mode A reset clears TCCON to 00H This sets timer C to fxx 1 amp PWM timer mode selects 3 bits prescaler of non divided stop timer C and disables all timer C interrupts You can clear the timer C counter at any time during normal operation by writing a 1 to 3 To enable the timer C match overflow interrupt IRQ2 vector DAH you must write TCCON 7 and TCCON 1 to 1 To generate the exact time interval you should write TCCON 3 and 0 which cleared counter and interrupt pending bit To detect an interrupt pending condition when TCINT is disabled the application program poll pending bit When 1 is detected a timer C match overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer C interrupt pending bit TCCON O Timer C Control Register ECH Set 1 Bank 0 R W Timer C start stop bit Timer C interrupt Pending bit 0 Stop timer C 0 Interrupt request is not pending 1 Start timer C Clear pending bit when write 0 1 Interrupt request is p
60. UART 0 Receive Parity bit Selection Bit for modes 2 and 3 only Even parity bit check Odd parity bit check NOTE Ifthe UARTOCONL 7 0 This bit is don t care UART 0 Receive Parity bit Error Status Bit for modes 2 and 3 only No parity bit error Parity bit error NOTE Ifthe UARTOCONL 7 0 This bit is don t care UART 0 Clock Selection Bits UART 0 Transmit Interrupt Enable Bit Disable Tx interrupt Enable Tx interrupt UART 0 Transmit Interrupt Pending Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read 4 49 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 UART1CONH uanr 1 Contro Register High Byte F2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 UART 1 Mode Selection Bits 0 Mode 0 shift register fU 16 x BRDATA1 1 1 Mode 1 8 bit UART fU 16 x BRDATA1 1 1 0 Mode 2 9 bit UART fU 16 1 Mode 3 9 bit UART fU 16 x BRDATA1 1 5 Multiprocessor Communication Enable Bit for modes 2 and 3 only Disable Enable 4 Serial Data Receive Enable Bit Disable 1 Enable 3 TB8 Only when UART1CONL 7 0 Location of the 9th data bit to be transmitted in UART 1 mode 2 or 3 0 or 1 NOTE Ifthe UART1CONL 7 1 This bit is don t care 2 RB8 Only when UART1CONL 7 0 L
61. and Decrement LDCD LDED dst src Operation Flags Format Examples dst src r lt 1 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given 10H R7 8 12H program memory location 1033H and external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 RR6 is decremented by one R8 OCDH R6 10H R7 32H RR6 lt 6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one lt A RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src Ir rmm 1 These instructions are used for user stacks or block transfers of data from program or
62. and stop bits are generated automatically by hardware e Mode 1 Receive Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 Set the UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 Select the baud rate to be generated by BRDATA1 Select mode 1 and set the RE Receive Enable bit in the UART1CONH register to 1 The start bit low 0 condition at the RxD1 P4 5 pin will cause the UART 1 module to start the serial data receive operation Write to Shift Register UDATA1 Shift TxDI Do X X o2 X X D4 X Ds X De X D7 4 Stop Bit Transmit TIP cier RxD1 N Start Bit ra X D1 X D2 X D3 X D4 X D5 X D6 X D7 Stop Bit rime L TET LTTELITTLTITI 1 RIP Figure 19 7 Timing Diagram for Serial Port Mode 1 Operation ELECTRONICS 19 9 UART 1 S3F84UA F84U8_UM_REV1 10 SERIAL PORT MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD1 P4 4 pin or received through the RxD1 P4 5 pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 The 9th data bit to be transm
63. applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in points to Instruction enin working register block Program Memory wod Base Address dst src X Instruction Point to One of the Example Woking Register o 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RPO or RP1 gt RPO or 1 Selected RP points to start of ki Program Memory 2 i NEXT 2 Bits 4 bit Working dst src Register Register Address OPCODE Point to Working Pair block p nM 16 Bit address added to p Program Memory offset L
64. as determined by the current CLKCON register setting divided by 4096 as the BT clock The MCU is resented whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter is always broken by a clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume the normal opera
65. at address F5H and is read write addressable using register addressing mode It has the following control functions LCD duty and bias selection LCD clock selection display control The LCON register is used to turn the LCD display on off to select duty and bias to select LCD clock A reset clears the LCON registers to configuring turns off the LCD display select 1 8 duty and 1 4 bias and select 128Hz for LCD clock The LCD clock signal determines the frequency of COM signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD clock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on NOTE The clock and duty for LCD controller driver is automatically initialized by hardware whenever LCON register data value is re write So the LCON register don t re write frequently LCD Control Register LCON F5H Set 1 Bank 0 R W LCD NN selection bits LCD control bit 00 fw 2 128 Hz 0 All LCD signals are low 01 27 256 Hz Turn display on Not used for the S8F84UA 8 10 fw 2 512 Hz 11 fw 25 1024 Hz LCD duty and bias selection bits 000 1 8 duty 1 4 bias 001 1 4 duty 1 3 bias 010 1 3 duty 1 3 bias 011 1 3 duty 1 2 bias 1xx 1 2 duty 1 2 bias Figure 15 4 LCD Control Register LCON 15 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER
66. bit must then be cleared by software in the interrupt service routine In mode 0 the transmit interrupt pending bit UART1CONL O is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the UART1CONL O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UART1CONL O bit must then be cleared by software in the interrupt service routine 19 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 1 UART 1 DATA REGISTER UDATA1 UART 1 Data Register UDATA1 Set 1 Bank 0 R W Transmit or receive data Figure 19 3 UART 1 Data Register UDATA1 UART 1 BAUD RATE DATA REGISTER BRDATA1 The value stored in the UART 1 baud rate register BRDATAt1 lets you determine the UART 1 clock rate baud rate UART 1 Baud Rate Data Register BRDATA1 F5H Set 1 Bank 0 R W Baud rate data Figure 19 4 UART 1 Baud Rate Data Register BRDATA1 BAUD RATE CALCULATIONS Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the UART 1 baud rate data register BRDATAt in set 1 bank 0 at address F5H Mode 0 baud rate fy 16 x BRDATA1 1 Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fy clock frequency divided by 16 Mode 2 baud rate 8 16 Modes 1 and 3 Baud Rate Calculation In modes 1 3 the baud rate is determined by the UART 1 baud rate data register BRDATA1 in set 1 bank 0 at address
67. bits the bit address b is three bits and the LSB address value is one bit in length Given 06H general register LDB R0 00H2 gt RO LDB 00H 0 R0 gt RO 07H register 05H 06H register 04H In the first example destination working register RO contains the value 06H and the source general register the value 05H The statement LD R0 00H 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 00 0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register OOH ELECTRONICS 6 51 INSTRUCTION SET LDC LDE Load Memory LDC LDE Operation Flags Format 10 dst src dst src S3F84UA F84U8 UM REV1 10 This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or values an even number for program memory and odd an odd number for data memory No flags are affected n a opc NOTES n t o dst src src dst dst src src dst dst
68. byte prime register area and two 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes Table 2 2 S3F84U8 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register area one 192 byte prime register area and one 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes 2 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES Page 0 System and Peripheral Control Set 2 Registers Register Addressing Mode Registers Indirect Register Indexed Mode System Registers and Stack Operations Register Addressing Mode Working Registers Working Register Addressing Only Prime Page 8 Data Registers All Addressing Modes Prime Data Registers All Addressing Modes LCD Display Register Figure 2 3 Internal Register File Organization S3F84UA ELECTRONICS 2 5 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 Page 0 System and Peripheral Control Set 2 Registers Register Addressing Mode Registers Indirect Register Indexed Mode System Registers and Stack Operations Register Addressing Mode Working Registers Working Register Addressing Only Prime Page 8 Data Registers All Add
69. circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer In Circuit Emulator for SAM8 family OPENice i500 SmartKit SK 1200 OTP MTP Programmer SPW uni GW uni AS pro US pro Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice i500 System TEL 82 31 223 6611 FAX 82 331 223 6613 E mail openice aijisystem com URL http www aijisystem com it 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com ELECTRONICS 25 9 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER S3F84UA F84U8_UM_REV1 10 SPW uni Single OTP MTP FLASH Programmer Download Upload and data edit function PC based operation with USB port e Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection Fast programming speed 4Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL h
70. data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H 0C5H external data memory locations 1033H ODDH and 1034 005 LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src r rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loade
71. fo 0 mumede Fo Atematve orione 0 Atematvetuncton 3 2 P0 1 PG1 AD1 o o mumm Fo Atematve io Atematvetuncton ab SSCS 1 0 P0 0 PGO ADO Co o mamd Fo 1 aemaweUmio gag Alternative function ADO Output mode push pull 4 20 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER POPUR Porto Pull up Resistor Enable Register D2H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 PO 7 Pull up Resistor Enable Bit Pull up disable fel Pull up enable 6 0 6 Pull up Resistor Enable Bit Pull up disable Pull up enable fel 5 P0 5 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 0 4 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 3 PO 3 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 2 0 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 1 PO 1 Pull up Resistor Enable Bit Pull up disable Pull up enable 0 0 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable NOTE A pull up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function ELECTRONICS 4 2 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 P1 CON Port 1 Control Register E2H Set 1
72. for the timer D1 clock frequency you can calculate the pulse width duration of the signal that is being input at the TD1CAP pin see Figure 13 9 TD1OVF 1 0 IRQ3 16 Bit Up Counter INTPND 4 Overflow INT Interrupt Enable Disable TD1CON 1 TD1CAP input TD1INT IRQ3 INTPND 5 Se INT Match Signal Pending TD1CON 4 3 TD1CON 4 3 y Timer D1 Data Register Figure 13 9 Simplified Timer D1 Function Diagram Capture Mode ELECTRONICS 13 11 16 00 01 S3F84UA F84U8_UM_REV1 10 BLOCK DIAGRAM TD1CON 0 TD1OVF TD1CON 7 5 OVF INTPND 4 IRQ3 Data Bus fxx 1024 fxx 256 fxx 64 Clear 8 gt 16 bit Up Counter 7 1 TD1CON2 Read Only R TD1CON 1 M 16 bit Comparator 0 INTPND 5 IRQ3 X oe x Timer D1 Buffer Register 1 TDICON 4 3 TD1CON 4 3 Match Signal TD1CON 2 TD1OVF Timer D1 Data Register Data Bus Figure 13 10 Timer D1 Functional Block Diagram 13 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 of the watch timer control register WTCON 1 to 1 And if you want to service watch timer overflow interrupt IRQ4 vector E6H then
73. general purpose register file 2 In the S3F84U8 microcontroller the internal register file is configured as two pages Pages 0 8 The page O0 is used for general purpose register file 3 The page 8 of S83F84UA 8 is used for LCD data register or general purpose regiser Figure 2 5 Register Page Pointer PP ELECTRONICS 2 7 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination lt 0 Source lt 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO LD PP 10H Destination lt 1 Source lt 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO NOTE You should refer page 6 39 and use DJNZ instruction properly when DJNZ instruction is used your program 2 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES REGISTER SET 1 The term set 7 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 68 mapped system and peripheral control registers The lower 32 byte area contains
74. have the same effect as 4 bit working register addressing As shown in Figure 2 15 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 16 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address bits indicate 8 bit 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 15 8 Bit Working Register Addressing ELECTRONICS 2 19 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 RPO Selects RP1 R11 8 bit address Register 1100 011 form instruction 10101 011 address LD R11 R2 OABH Specifies working register addressing
75. in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example 6 26 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT The carry is complemented 1 the value of the carry flag is changed to logic zero 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 CLR Clear CLR dst Operation dst lt 0 Flags Format Examples The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 1 IR Given RegisterOOH 4FH register 01H 02H and register 02H CLR 00H gt Register OOH CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR 00H clears the destination register value to In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to
76. is 1 and in data byte it is The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received 19 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 1 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S3F84UA F84U8 devices masters and slaves to UART 1 mode 2 or Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3F84UA 8 Interconnect TxD1 RxD1 TxD1 RxD1 TxD1 RxD1 TxD1 RxD1 Master Slave
77. is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITR R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS o R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the valu
78. it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 3 2 Program Memory Register File 8 bit Register nets Es OPERAND nia gt Register Register LA One Operand File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot 1 RPO or Selected RP points to start of working register Program Memory 4 bit Working Regi orking Register dst block Point to the OPERAND A Working Register Two Operand 1 048 Instruction Example Sample Instruction ADD R1 R2 Where 1 R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to in
79. microcontroller has twelve bit programmable I O ports 4 The port 1 is a 4 bit port and the others are 8 bit ports This gives a total of 34 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required All ports of the SSF84UA F84U8 except P1 2 and P1 3 be configured to input or output mode All LCD signal pins are shared with normal ports Table 9 1 gives you a general overview of the S8F84UA F84U8 I O port functions ELECTRONICS 9 1 PORTS S3F84UA F84U8_UM_REV1 10 Table 9 1 SSF84UA F84U8 Port Configuration Overview Configuration Options 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups Alternatively 0 0 0 7 be used as ADO AD7 or PGO PG7 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups The P1 2 and P1 3 are only push pull output ports Alternately 1 0 1 1 can be used as 1 bit programmable port Input or push pull output mode selected by software software assignable pull ups Alternatively P2 0 P2 7 can be used as for LCD COM and SEG signal 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups 0 7 can
80. necessary register file address register pointer information El S Q Interrupt Request Register Polling Read only Cycle RESET R IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PERIPHERAL INTERRUPT CONTROL REGISTERS INTERRUPT STRUCTURE For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A match capture Timer A overflow Timer B match Timer C match overflow Timer DO match capture Timer DO overflow Timer D1 match capture Timer D1 overflow SIO interrupt Watch timer overflow UART 0 data transmit UART 0 data receive UART 1 data transmit UART 1 data receive P3 0 external interrupt P3 1 external interrupt P3 2 external interrupt P3 3 external interrupt P3 4 external interrupt P3 5 external interrupt P3 6 external interrupt P3 7 external interrupt IRQ3 IRQ5 TDOCON TDOCNTH TDOCNTL TDODATAH TDODATAL TD1CON TD1CNTH TD1CNTL TD1DATAH TD1DATAL SIOCON SIODATA SIOPS WTCON UARTOCONH UARTOCONL UDATAO BRDATAO UART1CONH UART1CONL U
81. of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 3 14 F6 DA dst 2 12 F4 IRR dst 2 14 D4 IA Examples Given RO 35H R1 21H PC 1A47H andSP 0002H CALL 3521H gt SP 0000 Memory locations OOOOH 0001H where 4AH is the address that follows the instruction RRO gt SP 0000H 0000H 0001H 49H CALL 40H gt SP 0000 OOOOH 0001 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as
82. of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 or 8 you must set the register page pointer PP to the appropriate source and destination values CPU and system control General purpose Page 8 Peripheral and I O LCD Data Register Area LCD data register Figure 2 6 Set 1 Set 2 Prime Area Register and LCD Data Register Map 2 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block i
83. or 3 In these modes 2 and 3 9 data bits are received The 9th bit value is written to UARTOCONH 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTOCONH register When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is receive
84. receive and transmit buffers are both accessed via the data register UDATAT is set 1 bank 0 at address F4H Writing to the UART data register loads the transmit buffer reading the UART 1 data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received one of the bytes will be lost In all operating modes transmission is started when any instruction usually a write operation uses the UDATA1 register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UART1CONH O is 0 and the receive enable bit UART1CONH 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UART1CONH 4 is set to 1 PROGRAMMING PROCEDURE To program the UART 1 modules follow these basic steps 1 Configure P4 5 and P4 4 to alternative function RxD1 P4 5 TxD1 P4 4 for UART 1 module by setting the P1CONH L register to appropriately value Load an 8 bit value to the UART1CONH L control register to properly configure the UART 1 module For interrupt generation set the UART 1 interrupt enable bit UART1CONH 1 or UART1CONL 1 to 1 When you transmit data to the UART 1 buf
85. that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the SSF84UA F84U8 the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H ELECTRONICS 2 21 ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP S3F84UA F84U8_UM_REV1 10 The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP SPL 0FFH PP RPO 1
86. the S3F84UA and S3F84U8 microcontroller The TB84UA 8 target board is operated as target CPU with Emulator SK 1200 OPENice i500 TB84UA 8 To User Vcc U2 A Y1 In Circuit Emulator SK 1200 OPENice i500 RESET C3 sub clock J1 JP1 6 5 5 4 40 1 160 S3E84U0 EVA Chip 42SDIP 44QFP 50 Pin Connector 50 Pin Connector gt Uv 5 S 5 5 n 9 90 Device Selection J101 J102 Smart Option Source Internal AVREF S3F84UA Vcc CN1 Smart Option Selection 0 1 123 4 5 6 7 N e cm Figure 25 2 TB84UA 8 Target Board Configuration NOTE The symbol 4 marks start point of jumper signals ELECTRONICS 25 3 DEVELOPMENT TOOLS S3F84UA F84U8_UM_REV1 10 Table 25 1 Components of TB84UA 8 Symbols Usage Description CN2 100 pin connector Connection between emulator and TB84UA 8 target board J101 J102 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to SSF84UA F84U8 EVA chip VDD GND POWER connector External power connector for TB84UA 8 STOP IDLE LED STOP IDLE Display Indicate the status of STOP or IDLE of S3F84UA F84U8 EVA chip on TB84UA 8 target board EL
87. things are same as using external interrupt How to Enter into Stop Mode Handling STPCON register then writing STOP instruction keep the order LD STPCON 10100101B STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN S3F84UA F84U8_UM_REV1 10 IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS I O PORTS OVERVIEW The S3F84UA F84U8
88. to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 RET Return RET Operation Flags Format Example PC lt SP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH andPC 1234 RET gt 101AH SP OOFEH statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n 0 6 The contents of the destination operand are rotated left on
89. to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 02H R1 R2 SKIP gt R2 04 jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001 to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA Ifdst sre 0 lt PC RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program c
90. 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the SSF84UA F84U8 interrupt structure the timer A overflow interrupt IRQO the timer B match interrupt IRQ1 the timer C overflow interrupt IRQ2 the timer DO D1 overflow interrupt IRQ3 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register d Programming Tip How to clear an interrupt pending bit As the following examples are shown a load instruction should be used to clear an interrupt pending bit Examples 1 SB1 LD P3PND 11111011 Clear P3 2 s interrupt pending bit IRET 2 SBO LD INTPND 11111101 Clear timer A match capture interrupt pending bit IRET 5 16 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows Sog PF OND A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The
91. 0 ADDRESS SPACES SMART OPTION ROM Address 003EH pum used ISP protection size selection bits note ISP reset vector UI enable 00 biles disable bit 0 reset vector address 1 E ior ea 0100H 10 1024 bytes Normal vector address 11 2048 bytes ISP reset vector address selection bits ISP protection enable disable bit 00 200H ISP area size 256 byte 0 Enable not erasable by LDC 01 300H ISP area size 512 byte 1 Disable Erasable by LDC 10 500H ISP area size 1024 byte 11 900H ISP area size 2048 byte ROM Address 003FH Not used These bits should be LVR enable disable bit always logic 110b Criteria Voltage 2 2V 0 Disable LVR 1 Enable LVR ROM Address 003CH Not used ROM Address 003DH Not used NOTES 1 After selecting ISP reset vector address in selecting ISP protection size don t select upper than ISP area size 2 When any values are written the Smart Option area 003 00 by LDC instruction the data of the area may be changed but the Smart Option is not affected The data for Smart Option should be written in the Smart Option area 003CH 003FH by OTP MTP tools SPW2 plus single programmer or GW PRO2 gang programmer Figure 2 2 Smart Option Smart option is the ROM option for start condition of the chip The ROM address used by smart option is from 003CH to 003FH The S8F84UA F84U8 uses 003EH to 003FH
92. 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 3 Not used for the S3FB4UA 8 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt level selection bits 1 Fast interrupt enable bit 2 0 Disable fast interrupts processing 1 Enable fast interrupts processing 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing El instruction not by writing a 1 to SYM O Figure 5 5 System Mode Register SYM ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 INTERRUPT MASK REGISTER IMR Th
93. 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given RegisterOOH O3H registerO1H 05H and register 04H 2AH PUSHUI 900H 04H Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example lt 0 The carry is cleared
94. 1 1100 3CH DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt 0 H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address 27H DR1 ELECTRONICS S3F84UA F84U8_UM_REV1 10 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles dst 2 Given R1 and register 03H DEC Ri gt 1 02H DEG QHR1 gt Register 03H OFH INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if working register R1 contains the value the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC 1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 D ECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the
95. 1 Register Description Format sesers 4 4 5 1 SSF8 Series Interrupt 5 2 5 2 SSF84UA F84U8 Interrupt Structure sse 5 4 5 3 ROM Vector Address Area oir eniro er a 5 5 5 4 interrupt Function DIagrarm rite te tete teen etr pre incen 5 8 5 5 System Mode Register SYM ener entree nennen entren 5 11 5 6 Interrupt Mask Register 5 12 5 7 Interrupt Request Priority Groups nennen 5 13 5 8 Interrupt Priority Register IPR 5 14 5 9 Interrupt Request Register 5 15 6 1 System Flags Register 6 6 7 1 Crystal Ceramic Oscillator fx kia sia asinada e na eade a a anaE Aaaa aE 7 2 T2 External Oscillator titre tte ete n a 7 2 7 3 RG Oscillator 7 2 7 4 Crystal Oscillator 7 2 7 5 External Oscillator arr dites er arid 7 2 7 6 System Clock Circuit entrent 7 3 7 7 System Clock Control Register 2 0 00 400 00 7 4 7 8 Oscillator Control Register 44400 00 00
96. 10 P3PUR Port 3 Pull up Resistor Enable Register E9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 Pull up Resistor Enable Bit Pull up disable o Pull up enable 6 P3 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P3 5 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 P3 4 Pull up Resistor Enable Bit Pull up disable Pull up enable e 3 P3 3 Pull up Resistor Enable Bit Pull up disable e Pull up enable 2 P3 2 Pull up Resistor Enable Bit Pull up disable Pull up enable Pull up Resistor Enable Bit Pull up disable Pull up enable e 0 P3 0 Pull up Resistor Enable Bit Pull up disable e Pull up enable NOTE A pull up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function 4 30 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER Port 3 N channel Open drain Mode Register E3H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 Output Mode Selection Output mode push pull Output mode open drain 1 6 P3 6 Output Mode Selection Bit Output mode push pull Output mode open drain 1 5 P3 5 Output Mode Selection Bit Output mode push p
97. 16 Otherwise the STOP instruction will not be executed and reset will be generated Figure 7 9 STOP Conirol Register STPCON PROGRAMMING How to Use Stop Instruction This example shows how to go STOP mode when a main clock is selected as the system clock LD STOPCON 1010010B Enable STOP instruction STOP Enter STOP mode NOP NOP NOP Release STOP mode LD 00000000 Disable STOP instruction 7 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CLOCK CIRCUIT SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determine whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies OSCCON O selects the main clock fx or the sub clock fxt for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 3 controls the frequency divider circuit and divides the selected fxx clock by 1 2 8 and 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 3 to 11 0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops mai
98. 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 location are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 location is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S8F84UA the set 2 address range is accessible on pages 0 1 S3F84U8 the set 2 address range COH FFH is accessible on pages 0 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 location In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register are is commonly used for stack operations ELECTRONICS 2 9 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 PRIME REGISTER SPACE The lower 192 bytes OOH BFH of the S3F84UA F84U8 s two or one 256 byte register pages is called prime register area Prime registers can be accessed using any
99. 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 8 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 9 RPO points to the upper slice and to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements 2 PROGRAMMING Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt 1 lt nochange RPO lt 1 lt nochange LD RP1 0F8H RPO lt lt OF8H Register File Contains 32 8 Byte Slices 00001 X XX 8 Byte Slice 16 Byte RP 1 Contiguous Working 00000XXX 8 Byte Slice Register block RPO Figure 2 8 Contiguous 16 Byte Working Register Block 2 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 8 Byte Slices working Register block RPO 00000 XXX 8 Byte
100. 42H and register 42H the value 6FH the statement POPUD 02 00 loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src lt IR 1 POPUI instruction is used for user defined stacks the register The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given RegisterOOH 01H and register 01H 70H POPUI 02H 00H gt Register 00H 02H register 01H 70H register 02H 70H If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02 900 loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 PUSH Push To Stack PUSH Operation Flags Format Examples SIC SP 4 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decrement
101. 53 semiconductor products designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page URL Http www samsungsemi com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR PRODUCT NAME DOCUMENT NAME DOCUMENT NUMBER EFFECTIVE DATE SUMMARY DIRECTIONS Samsung Electronics LSI Development Group Gi Heung South Korea S3F84UA F84U8 16 bit CMOS Microcontroller S3F84UA F84U8 User s Manual Revision 1 10 21 10 S3 F84UA F84U8 092008 September 2008 As a result of additional product testing and evaluation some specifications published SSF84UA F84U8 User s Manual Revision 1 10 have been changed These changes for in SSF84UA F84U8 microcontroller which are described in detail in the Revision Descriptions section below are related to the followings Chapter 22 Electrical Data Chapter 21 Embedded Flash Memory Interface Please note the changes in your copy copies of the SSF84UA F84U8 User s Manual Revision 1 10 Or simply attach the Revision Descriptions of the next page to SSF84UA F84U8 User s Manual Revision 1 10 REVISION HISTORY 000 Preliminary Spec for internal release only June 2008 Second edition S
102. 6 bit internal timer e External event counter function PWM and capture function Watch Timer Interval time 1 995mS 0 1255 0 25S 0 55 at 32 768 kHz 0 5 1 2 4 kHz Selectable buzzer output LCD Controller Driver 16segments and 8 common terminals 1 2 1 8 1 4 and 1 8 duty selectable Resistor bias selectable Analog to Digital Converter e 8 channel analog input e 10 bit conversion resolution 2505 conversion time Two Channels UART Full duplex serial interface e Four programmable operating modes Auto generating parity bit 8 bit Serial I O Interface e 8 bit transmit receive mode e 8 bit receive mode e LSB first or MSB first transmission selectable e Internal or external clock source ELECTRONICS S3F84UA F84U8_UM_REV1 10 FEATURES Continued Pattern Generation Module e Pattern generation module triggered by timer match signal and software Low Voltage Reset LVR Criteria voltage 2 2V En Disable by smart option ROM address Two Power Down Modes e Idle only CPU clock stops e Stop selected system clock and CPU clock stop Oscillation Sources e Crystal ceramic or RC for main clock Main clock frequency 0 4 MHz 12 0 MHz e 32 768 kHz crystal oscillation circuit for sub clock Instruction Execution Times e 333 5 at 12 0 MHz fx minimum e 122 1 5 at 32 768 kHz fxt minimum ELECTRONICS PRODUCT OVERVIEW Operating Voltag
103. 8 3 UART 0 Data Register 0 18 5 18 4 UART 0 Baud Rate Data Register 18 5 18 5 UART 0 Functional Block 18 7 18 6 Timing Diagram for Serial Port Mode 0 Operation 2 18 8 18 7 Timing Diagram for Serial Port Mode 1 Operation 18 9 18 8 Timing Diagram for Serial Port Mode 2 18 10 18 9 Timing Diagram for Serial Port Mode Operation 18 11 18 10 Connection Example for Multiprocessor Serial Data Communications 18 13 19 1 UART 1 High Byte Control Register UART1CONH 19 3 19 2 UART 1 Low Byte Control Register 19 4 19 3 UART 1 Data Register 1 19 5 19 4 UART 1 Baud Rate Data Register 1 19 5 19 5 UART 1 Functional Block 19 7 19 6 Timing Diagram for Serial Port Mode 0 19 8 19 7 Timing Diagram for Serial Port Mode 1 Operation 2 19 9 19 8 Timing Diagram for Serial Port Mode 2
104. 8 BIT TIMER A B PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P4 1 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 17 59 16 37 9 kHz 1 3 Duty Timer is used in repeat mode Oscillation frequency is 4 MHz 0 25 us TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 Set P4 1 to TBPWM mode ORG START DI LD LD LD OR ELECTRONICS 0100H TBDATAL 70 2 TBDATAH 35 2 TBCON 00000111B P4CONL 00000100B Reset address Set 17 5 us Set 8 75 us Clock Source lt fxx Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop TBOF high Set P4 1 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P4 1 11 11 8 S3F84UA F84U8_UM_REV1 10 PROGRAMMING TIP To generate a one pulse signal through P4 1 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters are Timer B is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us TBDATAH 40 us 0 25 us 160 TBDATAL 1 Set P4 1 to TBPWM mode ORG 0100H Reset addr
105. 8 INT2 SI P3 2 O XOUT XIN TEST P1 1 XTIN P1 0 XTOUT oO vt 19599 O ed ONOO El eed 0DAS 2eNOO SI L ed sOdS INOO 02 FEd OS LLNI Z93S ec ed IO3S ENOO 9 ved eDAS VNOO CJ ZI Ged EDAS SNOD 81 9 ed vVOdS 9WOO 61 0 9 219 013 9935 Ic Figure 1 2 53 840 8408 Pin Assignments 44 QFP 1010B ELECTRONICS 1 5 PRODUCT OVERVIEW 1 6 IVCREF AVREF P0 7 PG7 AD7 P0 6 PG6 AD6 P0 5 PG5 AD5 P0 4 PG4 AD4 P0 3 PG3 AD3 P0 2 PG2 AD2 P0 1 PG1 AD1 P0 0 PGO ADO VDD Vss XOUT XIN TEST P1 1 XTIN P1 0 XTOUT nRESET 2 0 1 2 1 COM2 SEGO P2 2 S3F84UA S3F84U8 42 SDIP 600 S3F84UA F84U8_UM_REV1 10 SEG21 RXDO P4 7 SEG20 TXDO P4 6 SEG19 RXD1 P4 5 SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP P4 3 SEG16 TACLK P4 2 SEG15 TBPWM P4 1 SEG14 TCOUT TCPWM P4 0 SEG13 INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INT6 TDOCLK P3 6 SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 5 SEG10 INT4 TD1CLK P3 4 SEG9 INT3 SCK P3 3 SEG8 INT2 SI P3 2 SEG7 INT1 SO P3 1 SEG6 INT0 BUZ P3 0 COM7 SEG5 P2 7 COM6 SEG4 P2 6 COMBS SEG3 P2 5 COM4 SEG2 P2 4 COM3 SEG1 P2 3 Figure 1 3 SS3F84UA F84U8 Pin Assignments 42 SDIP 600 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 SSF84UA F84U8 Pin Descriptions Circuit Tom Type rol note port with bit programma
106. ATAH TDODATAL The match signal generates a timer DO match interrupt TDOINT vector D8H and clears the counter If for example you write the value 1087H to TDODATAH TDODATAL the counter will increment until it reaches 1087 At this point the timer DO interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer DO output pin is inverted see Figure 13 2 Interrupt Enable Disable TDOCON 1 16 Bit Up Counter TDOINT IRQ3 INTPND 3 16 Bit Comparator INTPND Match INT Pending Capture Signal TDOOUT Match Signal N TDOCON 2 TDOOVF Figure 13 2 Simplified Timer DO Function Diagram Interval Timer Mode ELECTRONICS 13 3 16 00 01 S3F84UA F84U8_UM_REV1 10 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TDOPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer DO data register PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFFFH and then continues incrementing from 0000 Although you can use the match signal to generate a timer DO overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TDOPWM pin is held to Low level a
107. BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRPO src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being add
108. Bank 1 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the SSF84UA F84U8 3 2 P1 1 XT N fo Input mode Input mode pull up Alternative function Output mode push pull 1 0 1 0 XToyT Input mode ofo Input mode pull up 1 0 Alternative function Output mode push pull 4 22 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER P2CONH Port 2 Control Register High Byte EOH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 SEG5 COM7 ros ERE Alternative function LCD signal Output mode push pull 5 4 P2 6 SEG4 COM6 o i mwm ie Memawefmen Cospa 3 2 P2 5 SEG3 COM5 o i mwm ie Memawefmen Cospa 1 0 P2 4 SEG2 COM4 Alternative function LCD signal Output mode push pull ELECTRONICS 4 23 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 P2CONL Port 2 Control Register Low Byte E1H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 SEG1 COM3 Pos Alternative function LCD signal Output mode push pull 5 4 2 2 5 0 2 fo o mamds Po mwm
109. Bit Watch Timer SIO Disable mask Enable unmask le 3 Inte rupt Level Enable Bit Timer 00 1 Match Capture or Overflow Disable mask Enable unmask le 2 Inte rupt Level 2 IRQ2 Enable Bit Timer Match Overflow Disable mask 1 Enable unmask 1 Inte Level 1 IRQ1 Enable Bit Timer Match Disable mask 1 Enable unmask 0 Inte Level 0 IRQO Enable Bit Timer A Match Capture or Overflow Disable mask 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 4 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER INTPND Interrupt Pending Register FBH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the SSF84UA F84U8 5 Timer D1 Match Capture Interrupt Pending Bit E No interrupt pending when read clear pending bit when write Interrupt is pending when read E Timer D1 Overflow Interrupt Pending Bit EN No interrupt pending when read clear pending bit when write Interrupt is pending when read 3 Timer DO Match Capture Interrupt Pending Bit No interrupt pending when read clear pending bit when write Interrupt is pending when read 2 Timer DO Overflow Interrupt Pending Bit No interrupt pending when read clear pending bit when write In
110. CH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 bank 0 at address E6H and is read write addressable using register addressing mode A reset clears WTCON to 00H This disable the watch timer So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON E6H Set 1 Bank 0 R W Watch timer clock selection bit Watch timer interrupt pending bit 0 Select main clock divided by 27 fx 128 0 Interrupt request is not pending 1 Select sub clock fxt Clear pending bit when write 0 1 Interrupt request is pending Watch timer INT Enable Disable bit Watch timer Enable Disable bit 0 Disable watch timer INT 0 Disable watch timer 1 Enable watch timer INT Clear frequency dividing circuits 1 Enable watch timer Buzzer signal selection bits 00 0 5 kHz Watch timer speed selection bits 01 1 kHz 00 Set watch timer interrupt to 0 5 s 10 2 kHz 01 Set watch timer interrupt to 0 25 s 11 4 kHz 10 Set watch timer interrupt to 0 125 s 11 Set watch timer interrupt to 1 995 ms Figure 14 1 Watch Timer Control Register WTCON 14 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON 7 WTCON 6 m Enable Disable WTCON 5 WTCON 6 em 0547 WTCON
111. COM2 COM7 Controller Driver SEGO SEG5 sng 18 8 SEG6 SEG21 Figure 15 1 LCD Function Diagram ELECTRONICS 15 1 LCD CONTROLLER DRIVER LCD CIRCUIT DIAGRAM SEG Port Driver LCD Display RAM 830H 845H COM Port Driver o 3 e 5 Timing Controller LCD Voltage Control Figure 15 2 LCD Circuit Diagram S3F84UA F84U8_UM_REV1 10 SEG21 P4 7 SEG17 P4 3 SEG13 P3 7 t o SEG6 P3 0 t O COM7 SEG5 P2 7 COM3 SEG1 P2 3 o COM2 SEG0 P2 2 0 COM1 P2 1 COMO P2 0 r O ELECTRONICS S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of 30H 45H page 8 are used as LCD data memory These locations can be addressed by 1 bit or 8 bit instructions When the bit value of a display segment is 1 the LCD display is turned on When the bit value is 0 the display is turned off Display RAM data are sent out through the segment pins SEGO SEG21 using the direct memory access DMA method that is synchronized with the f signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use Figure 15 3 LCD Display Data RAM Organization ELECTRONICS 15 3 LCD CONTROLLER DRIVER S3F84UA F84U8_UM_REV1 10 LCD CONTROL REGISTER LCON ALCON is located in set 1 bank 1
112. CPU checks the sources interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 2 3 4 Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt reques
113. CTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER STPCON Stop Control Register EDH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated ELECTRONICS 4 41 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 SYM System Mode Register DEH Set 1 RESET Value X X X 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S8F84UA F84U8 A 2 Fast Interrupt Level Selection Bits 1 4 Fast Interrupt Enable Bit 2 Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 9 lo Disable all interrupt processing Enable all interrupt processing NOTES 1 You select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM 0 4 42 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER TACON Timer A Control Register E2H
114. D7 Input Pin S3F84UA S3F84U8 Figure 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS S3F84UA F84U8_UM_REV1 10 SERIAL I O INTERFACE SERIAL INTERFACE OVERVIEW Serial I O module SIO can interface with various types of external device that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selector logic 8 bit data buffer SIODATA 8 bit pre scaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input output pins SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure the I O pins at port SO SCK SI by loading the appropriate value to the register if necessary Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial interrupt enable bit SIOCON 1 to 1 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pen
115. DATA1 BRDATA1 P3CONL P3INTL P3PND P3INTH P3PND E2H bank 0 bank 0 E1H bank 0 E3H bank 0 E4H bank 0 E5H bank 0 ECH bank 0 EAH bank 0 EBH bank 0 FAH bank 1 F6H bank 1 F7H bank 1 F8H bank 1 F9H bank 1 FBH bank 1 FCH bank 1 FDH bank 1 FEH bank 1 FFH bank 1 E7H bank 0 E8H bank 0 E9H bank 0 E6H bank 0 EEH bank 0 EFH bank 0 F1H bank 0 F2H bank 0 F3H bank 0 F5H bank 0 E5H bank 1 E7H bank 1 E8H bank 1 bank 1 E6H bank 1 E8H bank 1 NOTE f a interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 During the Port 3 state change the unexpected external interrupts are occurred The unexpected external interrupts are occurred by port 3 state change Therefore before port 3 states are changed to any value you can execute the DI El instructions and pending bit clear The following steps must be taken to change 1 Use DI instruction 2 Change PSCONH L P3INTH L and P3PUR 3 Clear Port 3 Interrupt Pending Register to 00000000B 4 Use El instruction 85 Programming How to prevent the unexpected external interrupts Examples 1 This example shows how to change from the normal port mode to the interrupt port mode
116. DEH x x x 0 0 Register page pointer 223 NOTES 1 An x means that the bit value is undefined following reset 2 A dash means that the bit is neither used nor mapped but the bit is read as 0 8 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 RESET and POWER DOWN Table 8 2 S3F84UA F84U8 Set 1 Bank 0 Register and Values after RESET Register Name ID Convener Data Register Low Byte abbarat 208 DH x x AD Converter ContelRegister 210 o o o Timer A Counter Register TANT 24 o o o v Timer A Cont Regser macon 226 o o Timer B Cont Resister T amp cON 227 o o v o Watch Timer wrcon 230 Esn o o v v 190 Regste 251 EM o o 0 Jo ra fonna sz e o foo SIO Pre scaler SIOPS 233 Finer Counter Regist Troon aoe oo o Cont Register vocon 236 EcH o o STOP regier 257 Eb o o o To UART 0 Register igh Bye oanrocon 238 To o UART 0 Control Register Low Bye vartocone 299 FH o o UART Convoi Register High Bye unemiconn 2 Fen To o UART Control Register Low Bye
117. DO Shift Clock _ Figure 18 6 Timing Diagram for Serial Port Mode 0 Operation 18 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 SERIAL PORT MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxDO 4 6 or received through the RxDO 4 7 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 Set the UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 Select the baud rate to be generated by BRDATAO Select mode 1 8 bit UART by setting UARTOCONH bits 7 and 6 to 01B Write transmission data to the shift register UDATAO set 1 bank 0 The start and stop bits are generated automatically by hardware e Mode 1 Receive Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 Set the UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 Select the baud rate to be generated by BRDATAO Select mode 1 and set the RE Receive Enable bit in the UARTOCONH register to 1 The start bit low 0 condition at the RxDO P4 7 pin will cause the UART 0 module to start the serial data receive operation Write to Shift Register UDATAO Shift S TxDO Do X X o2
118. ECTRONICS S3F84UA F84U8_UM_REV1 10 DEVELOPMENT TOOLS Table 25 2 Setting of the Jumper in TB84UA 8 JP Description 1 2 Connection 2 3 Connection Default Setting CN1 Device Selection Operate with TB84U8 Operate with TB84UA CN4 AVREF power source VDD User power Join 1 2 JP1 Clock source selection When using the internal clock source which is generated from Emulator Emulator join connector 2 3 and 4 5 pin If user wants to use 2 3 the external clock source like a crystal user should change the 4 5 jumper setting from 1 2 to 5 6 and connect J1 to an external clock source J1 External clock source Connecting points for external clock source CN3 Smart option source selection The Smart Option is selected The Smart Option is selected Join 1 2 by external smart option switch by internal smart option area SW1 003EH 0003FH of ROM But this selection is not available SW1 Smart option selection The Smart Option can be selected by this switch when the Smart Option source is selected by external The 2 0 comparable to the 2 0 The B7 B5 are comparable to the 003EH 7 5 The B8 is comparable to the The B4 B3 is not connected The B9 is not used Refer to the page 2 3 To Target System is supplied Vpp Target Board is not supplied Target Board is supplied Vpp Join 2 3 User Vcc Vpp from user System from user System e IDLE LED This is LED is ON when the evaluat
119. ELECTRONICS USER S MANUAL S3F84UA F84U8 8 Bit CMOS MICROCONTROLLERS September 2008 REV 1 10 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2008 Samsung Electronics Inc All Rights Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F84UA F84U8 8 Bit CMOS Microcontrollers User s Manual Revision 1 10 Publication Number 21 10 S3 F84UA F84U8 092008 Copyright 2008 Samsung Electronics Co Ltd Typical parame
120. Enable P Channel Data Pin Circuit Output Out E Disable Output N Channel Disable Data XTI XTO Figure 1 6 Pin Circuit Type C Figure 1 7 Pin Circuit D 2 1 0 1 1 ELECTRONICS 1 11 PRODUCT OVERVIEW S3F84UA F84U8_UM_REV1 10 Pull up 2 Enable Data Circuit Output Type C Disable ADCEN ADC Select Data 4 Figure 1 8 Pin Circuit F 16 PO VLCO VLC1 2 COM SEG Output Disable VLC2 3 Figure 1 9 Pin Circuit Type H 39 1 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW VDD Pull up Resistor Resistor 290 Enable COM SEG Circuit o 1 0 Output Type H 39 Disable Data Figure 1 10 Pin Circuit Type H 44 P2 Pull up Resistor occ Resistor Open drain Enable Data Output Disable Circuit Type H 39 Disable2 Figure 1 11 Pin Circuit Type H 41 P3 ELECTRONICS 1 13 PRODUCT OVERVIEW Open drain Data Output Disable COM SEG Output Disable2 S3F84UA F84U8_UM_REV1 10 Pull up Resistor Resistor Enable Circuit Type H 39 Figure 1 12 Pin Circuit Type H 42 P4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F84UA F84U8 microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bu
121. Enable Register FMUSR to 00000000B Check the Sector erase status bit whether Sector erase is success or not oa ron 59 PROGRAMMING Sector Erase SBO reErase LD FMUSR Tempo User Program mode enable 0A5H variable is must be setting another routine LD FMSECH 10H LD FMSECL 00H Set sector address 1000 107 CP UserlD Code zUser value Check user s ID code written by user User value is any value by user JR NE Not ID Code If not equal jump to Not ID Code LD FMCON Temp1 Start sector erase Tempi 0A1H Temp1 variable is must be setting another routine NOP Dummy Instruction This instruction must be needed NOP Dummy Instruction This instruction must be needed LD FMUSR 0 User Program mode disable FMCON 00001000B Check Sector erase status bit JR NZ reErase Jump to reErase if fail Not ID Code SBO LD FMUSR 0 User Program mode disable LD FMCON 0 Sector erase mode disable NOTE Incase of Flash User Mode the Tmep0 Temp1 s data values are must be setting another routine variables are should be defined by user ELECTRONICS 21 9 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 PROGRAMMING A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH and FMSECL to flash memory sector value The write operation of programming starts by LDC instru
122. Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 9 Port 3 High Byte Interrupt Control Register P3INTH Port 3 Interrupt Control Register Low Byte P3INTL E7H Set 1 Bank 1 R W INT2 INT 1 P3INTL bit pair pin configuration settings Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 10 Port 3 Low Byte Interrupt Control Register P3INTL ELECTRONICS 9 11 PORTS S3F84UA F84U8_UM_REV1 10 Port 3 Interrupt Pending Register P3PND E8H Set 1 Bank 1 R W Tt tt ft ttt PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO P3PND bit configuration settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 11 Port 3 Interrupt Pending Register Port 3 Pull up Resistor Enable Register P3PUR E9H Set 1 Bank 1 R W P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P3PUR bit configuration settings 0 Disable Pull up Resistor 1 Enable Pull up Resistor NOTE A pull up resistor of port is automatically disabled only when the corresponding pin is selected as push pull output or alternative function Figure 9 12 Port 3 Pull up Resistor Enable Register P3PUR 9 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS Port 3 N Channel Open drain Mode Register PNE3 Set 1 Bank 1 R W
123. F84U8_UM_REV1 10 SERIAL PORT MODE 3 FUNCTION DESCRIPTION UART 1 In mode 3 11 bits are transmitted through the TxD1 P4 4 pin or received through the RxD1 P4 5 pin Mode 3 is identical to mode 2 except for baud rate which is variable Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 Mode 3 Transmit Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 2 Setthe UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 3 Select mode 3 operation 9 bit UART by setting UART1CONH bits 7 and 6 to 11B Also select the 9th data bit to be transmitted by writing UART1CONH 3 8 to 0 or 1 4 Write transmission data to the shift register UDATA1 F4H set 1 bank O to start the transmit operation Mode 3 Receive Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 2 Setthe UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 3 Select mode 3 and set the RE Receive Enable bit in the UART1CONH register to 1 4 The receive operation will be started when the signal at the RxD1 P4 5 pin goes to low level fL Write to Shift Register UDATA1 LIL JIL LL IL JL JL JL Shift TIP mE Transmit xD Start Bit DO D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Bit Det
124. F84UA F84U8_UM_REV1 10 A D CONVERTER A D Converter Data Register High Byte ADDATAH DOH Set 1 Bank 0 Read Only A D Converter Data Register Low Byte ADDATAL D1H Set1 Bank 0 Read Only eed pes Figure 16 2 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range Vss to AVpep usually lt Vpp Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVggr ELECTRONICS 16 3 BLOCK DIAGRAM ADCON 6 4 Select one input pin of the assigned pins vy ADCON 0O AD C Enable Input Pins _ ADO AD7 P0 0 P0 7 ADCON O AD C Enable POCONH L Analog Comparator Assign Pins to ADC Input 10 bit D A Converter S3F84UA F84U8 UM REV1 10 ADCON 2 1 NE Clock To ADCON 3 Selector EOC Flag _1 Successive Approximation Logic amp Register Upper 8 bit is loaded to A D Conversion Data Register Conversion Result ADDATAH L Figure 16 3 A D Converter Functional Block Diagram ELECTRONICS S3F84UA F84U8_UM_REV1 10 A D CONVERTER Reference Voltage Input AVnEF lt Analog ADO A
125. Flags Format Example dst src b If src b isa 1 then lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET BXOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst O lt dst 0 src b or dst b lt dst b 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destinat
126. Hard Lock Protection mode disable NOTE Incase of Flash User Mode the 0 1 5 data values are must be setting another routine Temp0 Temp n variables are should be defined by user ELECTRONICS 21 13 S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter S8F84UA F84U8 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode LVR timing characteristics Serial timing characteristics A Dconverter electrical characteristics UART timing characteristics Internal Flash ROM electrical characteristics Operating voltage range ELECTRONICS 22 1 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 1 Absolute Maximum Ratings 25 Parameter Symbol Conditions Um Output current high One I O pin active mA All VO pins active Output current low lo One pin active 30 Peak value Total pin current for ports 100 Peak value Table 22 2 D C Electrical Characteristics 40 C to 85 Vpp 2 0 V to 5 5 V Operating voltage Vop fx20 4 4 2 MHz fxt 32 768 kHz fx 0 4 12 0 MHz Input hig
127. INTERNAL RESISTOR BIAS PIN CONNECTION 1 4 Bias 1 3 Bias VDD VDD VLCD 1 2 Bias VDD NOTES 1 VLCo and VLC1 should be connected at 1 3 bias 2 VLOCO VLC1 and VLC2 should be connected at 1 2 bias Figure 15 6 Internal Resistor Bias Pin Connection ELECTRONICS 15 5 LCD CONTROLLER DRIVER S3F84UA F84U8_UM_REV1 10 COMMON COM SIGNALS The common signal output pin selection COM pin selection varies according to the selected duty cycle In 1 8 duty mode COM0 COM7 SEG6 SEG21 pins are selected In 1 4 duty mode COMO COM3 SEG2 SEG21 In 1 8 duty mode 0 2 SEG1 SEG21 n 1 2 duty mode COMO COM 1 SEGO SEG21 pins are selected pins are selected pins are selected SEGMENT SEG SIGNALS The 22 LCD segment signal pins are connected to corresponding display RAM locations at page 8 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal to the corresponding segment pin 15 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER VLCO0 1 2 VLC3 Vss VLCO0 1 2 VLC3 Vss VLCO 1 2 VLC3 COM SEG Vss VLC3 VLO0 1 2 Figure 15 10 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode ELECTRONICS 15 7 LCD CONTROLLER DRIVER S3F84UA F84U8_UM_REV1 10 Vico
128. ION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 ADC Add with carry ADC dst src Operation dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmet
129. IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only IRQ1 IRQ2 IRQ4 IR IRQ6 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to
130. Input mode TACAP Alternative function TAOUT TAPWM EN Alternative function LCD signal Output mode 5 4 P4 2 TACLK SEG16 0 of mamae 7119 Atematvetuncion LoD sga 3 2 P4 1 TBPWM SEG15 1 Atematve tncion erwy 7119 Atematve function LoD signa 1 0 P4 0 TCOUT TCPWM SEG14 o 1 Alternative function TCOUT TCPWM E EN Alternative function LCD signal Output mode ELECTRONICS 4 33 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 PAPUR Port 4 Pull up Resistor Enable Register ECH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 Pull up Resistor Enable Bit Pull up disable fel Pull up enable 6 P4 6 Pull up Resistor Enable Bit Pull up disable Pull up enable e 5 P4 5 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 4 P4 4 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 3 P4 3 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 2 P4 2 Pull up Resistor Enable Bit Pull up disable fel Pull up enable 4 P4 Pull up Resistor Enable Bit Pull up disable Pull up enable 0 4 0 Pull up Resistor Enable Bit Pull up disable Pull up enable NOTE A pull up resistor of port 4 is automatically disabled only when the corresponding pin is selected
131. Interrupt Figure 22 1 Input Timing for External Interrupts Figure 22 2 Input Timing for nRESET ELECTRONICS 22 5 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 4 Input Output Capacitance TA 2 40 C to 85 C 20 V Input Cin f 1 MHz unmeasured pins 10 pF capacitance are returned to Vas Output Cout capacitance capacitance Table 26 5 Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Parameter Symb Conditions Wm T max Unt Data retention Vpppn 2 0 5 5 V supply voltage Data retention lpppR Stop mode T4 25 1 supply current Vpppn 2 0V 22 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA nRESET Occurs Oscillation Y Stabilization 311 Stop Mode _ 4 gt Time Y Normal Data Retention Mode Operating Mode 4 Execution of STOP Instrction nRESET twalT is the same as 4096 x 16 x 1 fxx Figure 22 3 Stop Mode Release Timing Initiated by nRESET Oscillation Stabillization Tlme Stop Mode IDLE Mode 4 Data Retention Mode VDDDR Normal Execution of Operation Mode STOP Instruction Interrupt NOTE tWAIT is the same as 16 x 1 fBT fBT is the selected clock for basic timer Figure 22 4 Stop Mode Release Timing Initiated by Interrupts ELECTRONICS 22 7 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 6 A D Converter
132. Ji fw 32 1 kHz fw 16 2 kHz WTCON 2 pres fw 8 4 kHz a Enable Disable WTCON 1 2 WTCON 0 WTCON O Pending Bit IRQ4 0 25sec Clock requency 9 125 Dividing Selector 32 768 kHz Circuit 1 995msec 1024 Hz fx Main clock where fx 4 19 MHz fxt Sub clock 32 768 kHz fxt fx 128 fw Watch timer frequency Figure 14 2 Watch Timer Circuit Diagram ELECTRONICS 14 3 S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S8F84UA F84U8 microcontroller can directly drive an up to 128 dot 16 segments x 8 commons LCD panel Its LCD block has the following components controller driver Display RAM 30H 45H for storing display data in page 8 6 common segment output pins COM2 SEGO COM7 SEG5 16 segment output pins SEG6 SEG21 2 common output pins COM0 COM 1 LCD bias by voltage dividing resistors The LCD control register LCON is used to turn the LCD display on and off select frame frequency LCD duty and bias Data written to the LCD display RAM can be automatically transferred to the segment signal pins without any program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even in the main clock stop or idle modes LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control COMO COM1 LCD
133. M_REV1 10 UART 1 Control Register Low Byte UART1CONL F3H Set 1 Bank 0 R W wo 5 2 re UART 1 transmit parity bit auto Uart 1 transmit interrupt pending bit generation enable bit 0 No interrupt pending when read 0 Disable parity bit auto generation clear pending bit when write 1 Enable parity bit auto generation 1 Interrupt is pending when read 1 transmit interrupt enable bit UART 1 transmit parity bit Panty 0 Disable Tx interrupt selection bit 1 Enable Tx interrupt 0 Even parity bit 1 Odd parity bit Uart 1 clock selection bits UART 1 receive parity bit 00 fxx 8 selection bit 01 fxx 4 0 Even parity bit check 10 fxx 2 1 Odd parity bit check 11 fxx 1 UART 1 receive parity bit error status bit 0 No parity bit error 1 Parity bit error NOTES 1 If the UART1CONL 7 0 This bit is don t 2 The bits UART1CONL 6 4 are for mode 2 and 3 only Figure 19 2 UART 1 Low Byte Control Register UART1CONL UART 1 INTERRUPT PENDING BITS In mode 0 the receive interrupt pending bit UART1CONH O is set to 1 when the 8th receive data bit has been shifted In mode 1 the UART1CONH O bit is set to 1 at the halfway point of the stop bit s shift time In mode 2 or the UART1CONH O bit is set to 1 at the halfway point of the 8 bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UART1CONH O
134. NICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER A B TIMER A FUNCTION DESCRIPTION Timer A Interrupts IRQO Vectors and DOH The timer A can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVE is interrupt level IRQO vector DOH TAINT also belongs to interrupt level IRQO but is assigned the separate vector address CEH A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND O interrupt pending bit However the timer A match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a to the INTPND 1 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector CEH and clears the counter If for example you write the value 10H to TADATA the counter will increment until it reaches 10H At this point the timer A interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer A output pin is inverted see Figure 11 2 Interrupt Enable Disable TACON 1 Capture Signal CLK
135. NICS 21 7 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and programmed in User Program Mode is called sector The program memory of S8F84UA F84U8 is divided into 384 64 sectors for unit of erase and programming respectively Every sector has all 128 byte sizes of program memory areas So each sector should be erased first to program a new data byte into a sector Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit 0 Sector Erase is not supported in Tool Program Modes MDS mode tool or Programming tool Sector 383 128 byte Sector 382 128 byte Sector 127 Sector 63 128 byte 128 byte Sector 11 Sector 11 128 byte 128 byte Sector 10 Sector 10 128 byte 128 byte Sector 0 9 Sector 0 9 128 byte x 10 128 byte x 10 S3F84UA S3F84U8 Figure 21 6 Sector Configurations in User Program Mode 21 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTERFACE The Sector Erase Procedure in User Program Mode Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Sector Address Register FMSECH FMSECL Check user s ID code written by user Set Flash Memory Control Register FMCON to 10100001B Set Flash Memory User Programming
136. O shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter Shift clock edge selection bit 0 at falling edges Rx at rising edges 1 TX at rising edges Rx at falling edges SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 17 1 Serial Module Control Registers SIOCON 17 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 SERIAL I O INTERFACE SIO PRE SCALER REGISTER SIOPS The control register for serial I O interface module SIOPS is located at E9H in set 1 bank 0 The value stored in the SIO pre scaler register SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx 4 Pre scaler value 1 or SCK input clock where the input clock is fxx 4 SIO Pre scaler Register SIOPS Set 1 Bank 0 R W Baud rate fxx 4 SIOPS 1 BLOCK DIAGRAM SCK B lt Figure 17 2 SIO Pre scaler Register SIOPS 3 Bit Counter SIOCON 0 Clear Pending SIOCON 1 SIOCON 3 Interrupt Enable SIOCON 7 SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 SIOPS E9H bank 0 fxx 2 ELECTRONICS Mode Select CLK g Bit SIO Shift Buffer gt SIODATA E8H bank 0 B so SIOCON 6 LSB MSB First Mode Select Figure 17 3 SIO Functional Block Diagram 17 3 SERIAL INTERFACE S3F84UA F84U8_UM_REV1 10 SERIAL I O TIMING DIAGRAM
137. Operating mode and baud rate selection bits see table below Multiprocessor communication enable bit for modes 2 and 3 only Uart 1 receive interrupt pending bit 0 No interrupt pending when read clear pending bit when write 1 Interrupt is pending when read Uart 1 receive interrupt enable bit 0 Disable d Enable 0 Disable Rx interrupt 1 Enable Rx interrupt Serial data receive enable bit 0 Disable RB8 Only when UART1CONL 7 0 1 Enable Location of the 9th data bit that was received UART 1 mode 2 or 3 0 or 1 8 9 Only when UART1CONL 7 0 Location of the 9th data bit to be transmitted in UART 1 mode 2 or 3 0 or 1 MS1 MSO Mode Description Baud Rate fu 16 x BRDATA1 1 fu 16 x BRDATA1 1 fu 16 fu 16 x BRDATA1 1 Shift register 8 bit UART 9 bit 9 bit 1 In mode 2 or 3 if the UART1CONH 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UART1CONH 5 1 then the receive interrut will not be activated if a valid stop bit was not received In mode 0 the UART1CONH 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Ifthe UART1CONL 7 1 This bit is don t care Figure 19 1 UART 1 High Byte Control Register UART1CONH ELECTRONICS UART 1 S3F84UA F84U8_U
138. R1 IM r2 b RA DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0O Rb POP POP AND AND AND AND AND BITC 1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0O Rb PUSH PUSH R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 x r2 RL RL POPUD POPUI DIV DIV DIV LD 1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 RAM 12 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r2 Irr2 xL LDC LDW LDW LDW LD 1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrri IR1 IM 1 r2 HR HR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 1 Irr2 xs SWAP SWAP LDCPD LDCPI CALL LD CALL LDC 1 IR1 r2 lrri r2 lrri IRR1 IR2 R1 DA1 r2 111 xs 6 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditiona
139. RFACE Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Sector Address Register High Byte indicates the high byte of sector address The FMSECH is needed for S8F84UA F84U8 because it has 512 sectors respectively One sector consists of 128 bytes Each sector s address starts XXOOH or XX80H that is a base address of sector is or XX80H So FMSECL register 6 0 don t mean whether the value is 1 or 0 We recommend that the simplest way is to load sector base address into FASECH and register When programming the flash memory you should write data after loading sector base address located in the target address to write data into FMSECH and FMSECL register If the next operation is also to write data you should check whether next address is located in the same sector or not In case of other sectors you must load sector address to FMSECH and FMSECL register according to the sector Flash Memory Sector Address Register FMSECH F6H Set 1 Bank 0 R W Flash Memory Setor Address High Byte NOTE The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 21 3 Flash Memory Sector Address Register High Byte FMSECH Flash Memory Sector Address Register FMSECL F7H Set
140. RO R1 XOR 00H 01H XOR 00H 01H RO OC5H R1 RO OE4H R1 02H register 02H 23H Register 29H register 01H 02H Register 08H register 01H 02H register 02H m m 3 XOR 00H 54H Register 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement 1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3F84UA F84U8_UM_REV1 10 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3F84UA F84U8 microcontroller has two oscillator circuits a main clock and a sub clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits The maximum CPU clock frequency of SSF84UA F84U8 is determined by register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON CPU CLOCK NOTATION In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock fxx selected system clock
141. RQO IRQ 7 Interrupt priority register R W _ Controls the relative processing priorities of the interrupt levels The seven levels of SSF84UA F84U8 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An external memory interface is implemented in the S3F84UA F84U8 microcontroller NOTE Before IMR register is changed to any value all interrupts must be disabled Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the
142. S 1 Parentheses indicate pin number for 42 SDIP 600 package 2 The Vpp TEST pin had better connect to Vpp Test Pin Voltage The TEST on socket board for MTP writer must be connected to Vpp 5 0 with RC delay as the figure 24 3 only when SPW 24 and GW pro2 are used to The TEST pin on socket board must not be connected Vpp 12 5V which is generated from MTP Writer So the specific socket board for SSF84UA F84U8 must be used when writing or erasing using MTP writer Figure 24 3 RC Delay Circuit 24 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 S3F84UA F84U8 FLASH MCU ON BOARD WRITING The S3F84UA F84U8 needs only 6 signal lines including Vpp and Vas pins for writing internal flash memory with serial protocol Therefore the on board writing is possible if the writing signal lines are considered when the PCB of application board is designed Circuit design guide At the flash writing the writing tool needs 6 signal lines that Vss nRESET TEST SDAT and SCLK When you design the PCB circuits you should consider the usage of these signal lines for the on board writing In case of TEST pin normally test pin is connected to Vgs but in writing mode the programming these two cases a resistor should be inserted between the TEST pin and Vas The nRESET SDAT and SCLK should be treated under the same consideration Please be careful to design the related circuit of these signal pins because rising falling timi
143. SB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Sample Instructions Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3F84UA F84U8_UM_REV1 10 INDEXED ADDRESSING MODE Concluded Register File gt RPO or 1 gt Register Pair MSB Points to RPO or Program Memory OFFSET OFFSET OPCODE 4 bit Working NEXT 2 Bits Register Address Point to Working Register Pair p Program Memory LSB Selects or Data Memory 8 Bits 16 Bits OPERAND 16 Bits Sample Instructions LDC R4 1000H RR2 are loaded into register R4 LDE R4 1000H RR2 ADDRESSING MODES Selected RP points to start of working register block 16 Bit address added to offset Value used in Instruction The values in the program address RR2 1000H Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and CALL instructions use th
144. SB1 LD P3CONH 10101010B P3 7 4 Alternative function LCD signal LD P3CONL 10101010B P3 3 0 Alternative function LCD signal DI for external interrupt setting mode LD P3CONH 00000000B P3 7 4 Input mode for interrupt LD P3CONL 00000000B P3 3 0 Input mode for interrupt LD P3INTH 01010101B P3 7 4 Enable interrupt falling edge LD P3INTL 01010101B P3 3 0 Enable interrupt falling edge LD P3PUR 11111111B P3 7 0 Enable pull up resistor LD P3PND 00000000B P3 7 0 Interrupt pending bit clear EI 2 This example shows how to change from the interrupt port mode to the normal port mode SB1 LD P3CONH 00000000B P3 7 4 Input mode for interrupt LD P3CONL 00000000B P3 3 0 Input mode for interrupt e e e DI for normal port setting mode LD P3CONH 10101010B P3 7 4 Alternative function LCD signal LD P3CONL 10101010B P3 3 0 Alternative function LCD signal LD P3INTH 00000000B P3 7 4 Disable interrupt falling edge LD P3INTL 00000000B P3 3 0 Disable interrupt falling edge LD P3PUR 00000000B P3 7 0 Disable pull up resistor LD P3PND 00000000B P3 7 0 Interrupt pending bit clear EI 5 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM
145. Sector erase the operation of Sector erase is discontinued and the interrupt is served by CPU Therefore the sector erase status bit should be checked after executing Sector erase The sector erase operation is success if the bit is logic 0 and is failure if the bit is logic 1 NOTE When the ID code is written to the FMUSR register A mode of sector erase user program and hard lock may be executed unfortunately So it should be careful of the above situation ELECTRONICS 21 3 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000 by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101b User Program mode is disabled Flash Memory User Programming Enable Register FMUSR F8H Set 1 Bank 0 R W Flash memory user programming enable bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 21 2 Flash Memory User Programming Enable Register FMUSR 21 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTE
146. Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer Input Clock Selection Bits ofo es of oja MONET 1 1 0 External clock TACLK rising edge 4 3 Timer A Operating Mode Selection Bits EJET Interval mode TAOUT Capture mode Capture on rising edge counter running can occur 1 lo Capture mode Capture on falling edge counter running OVF can occur 1 PWM mode OVF and match interrupt can occur 2 Timer A Counter Enable Bit 3 No effect 1 Clear the timer A counter when write 1 Timer A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer Overflow Interrupt Enable Bit ES Disable overflow interrupt 1 Enable overflow interrupt NOTE The 2 value is automatically cleared to 0 after being cleared counter ELECTRONICS 4 4 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 TBCON Timer B Control Register E3H Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 6 5 4 4 44 _ 5 4 3 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer B Input Clock Selection Bits Timer Interrupt Time Selection Bits Generating after low data is borrowed EJES Generating after high data i
147. Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir opc src dst 3 6 A4 R R 5 R IR dst src 3 6 A6 R IM Examples 1 Given R1 02Hand R2 CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 30 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal Operation Flags Format Example dst src RA Ifdst sre 0 lt RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is the relative address is added to the program counter and control passes
148. Slice RP1 Figure 2 9 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO RI ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R8 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H 80H 82H C ADC 80H 83H 80H 80H 83H C ADC 80H 84H 80H 80H 84H C ADC 80H 85H 80H 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS 2 13 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of sho
149. TDOCON 7 5 to 111B You can clear the timer DO counter at any time during normal operation by writing a 1 to TDOCON 2 The timer DO overflow interrupt TDOOVF is interrupt level IRQ3 and has the vector address DAH When a timer DO overflow interrupt occurs and is serviced interrupt IRQ3 vector DAH you must write TDOCON O to 1 When timer DO overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer DO match capture interrupt IRQ3 vector D8H you must write TDOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 3 When a 1 is detected a timer DO match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing to the timer DO match capture interrupt pending bit INTPND 3 Timer DO Control Register FAH Set 1 Bank 1 R W Timer DO input clock selection bits Timer DO overflow interrupt enable 000 fxx 1024 0 Disable overflow interrupt 001 fxx 256 1 Enable overflow interrupt 010 64 Timer DO match capture interrupt enable bit 011 fxx 8 0 Disable interrupt 100 fxx 1 1 Enable interrupt 101 External clock TDOCLK falling edge 110 External clock TDOCLK rising edge Timer DO counter clear bit 111 Counter stop 0 No effect 1 Clear th
150. TO 2 2 2 3 42 3 41 3 41 3 41 3 41 3 41 3 41 3 8 8 4 4 3 2 2 H 1 D1 external clock input Output pin for buzzer signal Serial interface clock 24 30 P3 3 SEG9 lO Serial interface data input 23 29 P3 2 SEG8 J J AI UO J OJU o 8 93 228 2 77 lO Serial interface data output 22 28 P3 1 SEG7 External interrupts input pins H 41 21 28 0 7 27 34 5 6 5 1 Main oscillator pins a 8 14 7 Crystal oscillator pins for sub clock 10 16 P1 0 11 17 P1 1 INTO INT7 En Test input it must be connected to 9 15 55 NOTE Parentheses indicate pin number for 42 SDIP 600 package ELECTRONICS 1 9 PRODUCT OVERVIEW S3F84UA F84U8_UM_REV1 10 Table 1 1 S3F84UA F84U8 Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Names Type Description Type Numbers Pins 480002 2 Groundpns Internal voltage controller reference 37 1 input pin NOTE Parentheses indicate pin number for 42 SDIP 600 package 1 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW PIN CIRCUITS P Channel Pull up Resistor N Channel Schmitt Trigger Figure 1 4 Pin Circuit Type A Figure 1 5 Pin Circuit Type B Pull up Resistor Pull up
151. TRONICS 6 49 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 LD Load LD Examples Continued Given RO O1H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP and register OFFH LD RO 10H gt RO 10H LD R0 01H gt RO 20H register 01H 20H LD 01H RO gt Register 01H 01H RO 01H LD R1 RO gt R1 20H RO 01H LD RO R1 gt RO 01H R1 OAH register 01H OAH LD 00H 01H gt Register 20H register 01H 20H LD 02H 00H gt Register 02H 20H register OOH 01H LD 00H 0AH gt Register OAH LD OOH 10H gt Register 01H register 01H 10H LD 00H 02H gt Register 01H register 01H 02 register 02 02H LD RO LOOP R1 gt RO OFFH R1 OAH LD LOOP RO R1 gt Register 31H OAH RO 01H R1 OAH ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb 0 NOTE Inthe second byte of the instruction formats the destination or source address is four
152. The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Unaffected Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Always reset to 0 Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO OC7H R1 02H R2 18H register 00 2BH registerO1H 02H register 02H 23H RO R1 gt RO OC7H R1 02H Z 0 RO R1 gt RO OC7H R1 02H registerO2H 23H Z 00H 01H gt RegisterOOH 2BH register 01H 02H 2 00H 901H RegisterOOH 2BH register 01H 02H register 02H 23H Z 0 00 54 gt RegisterOOH 2 2 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 WEI wait for Interrupt WFI Operation Flags Format Examp
153. Timer SIO Not pending Pending Lev 13 IRQ3 Request Pending Timer 00 1 Match Capture or Overflow Not pending Pending fel 2 12 IRQ2 Request Pending Timer Match Overflow Not pending le Pending 41 Lev 11 IRQ1 Request Pending Bit Timer B Match ot pending ending 0 Lev 10 IRQO Request Pending Timer Match Capture or Overflow Not pending B Pending 4 16 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER LCON LCD Control Register F5H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 LCD Clock Selection Bits fw 28 128 Hz waes C e was gran fw 25 1024 Hz 5 3 LCD Duty and Bias Selection Bits UVlbas 0 5 00 0 u3bas 000 0 1 1 Sau 12bias o O 2 1 Not used for the S3F84UA F84U8 0 LCD Display Control Bits Display off Turn display on NOTE The clock and duty for LCD controller driver is automatically initialized by hardware whenever register data value is re write So the LCON register don t re write frequently ELECTRONICS 4 17 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 OSCCON Oscillator Control Register FAH Set 1 Bank 0 RESET Value 0 0 0 Read Write R W R W R W Ad
154. Toggle output at TDOOUT pin Capture input mode with a rising or falling edge trigger at the TDOCAP pin PWM mode TDOPWM PWM output shares their output port with TDOOUT Timer DO has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer External clock input pin TDOCLK 16 bit counter TDOCNTH L a 16 bit comparator and two 16 bit reference data register TDODATAH L pins for capture input TDOCAP or match output TDOOUT Timer DO overflow interrupt IRQ3 vector DAH and match capture interrupt IRQ3 vector D8H generation Timer DO control register TDOCON set 1 Bank 1 FAH read write ELECTRONICS 13 1 16 00 01 S3F84UA F84U8_UM_REV1 10 TIMER DO CONTROL REGISTER TDOCON You use the timer DO control register TDOCON to Select the timer DO operating mode interval timer capture mode or PWM mode Select the timer DO input clock frequency Clear the timer DO counter TDOCNTH T DOCNTL Enable the timer DO overflow interrupt or timer DO match capture interrupt TDOCON is located in set 1 and bank 1 at address FAH and is read write addressable using Register addressing mode A reset clears TDOCON to OOH This sets timer DO to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer DO interrupts To disable the counter operation please set
155. U will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex Opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 DIV Divide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise 2 Setif divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Setif quotientis gt 28 orif divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by ze
156. VLC1 VLC2 VLC3 Vss SEG1 SEG2 SEG3 Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss SEGO COMO V Lco VLC1 VLC2 NOTE Vico VLC1 VLC2 Figure 15 11 LCD Signal Waveforms 1 2 Duty 1 2 Bias 15 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss Vico VLC1 VLC2 VLC3 Vss VLCo VLC1 VLC2 SEG1 COMO NOTE Vico VLC1 Figure 15 12 LCD Signal Waveforms 1 3 Duty 1 3 Bias ELECTRONICS 15 9 LCD CONTROLLER DRIVER S3F84UA F84U8_UM_REV1 10 VLco VLc1 VLc2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 VSS VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 VLC3 Vss VLCO VLC1 VLC2 COMO SEG2 NOTE VLCO VLC1 Figure 15 13 LCD Signal Waveforms 1 4 Duty 1 3 Bias 15 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 LCD CONTROLLER DRIVER 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Q lt E 1 omo oomo E omo oomo L ae SEG6 COMO Figure 15 14 LCD Signal Waveforms 1 8 Duty 1 4 Bias ELECTRONICS 15 11 LCD CONTROLLER DRIVER S3F84UA F84U8_UM_REV1 10 0 4 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SEG7
157. X X X vs X X D7 4 Stop Bit Transmit TIP es 1 RxDO staten DO X D X 592 X D3 X D4 X Ds X De X D7 Stop Bit sample time L FLT LITT T TTL TL LITT shift 1 RIP Figure 18 7 Timing Diagram for Serial Port Mode 1 Operation ELECTRONICS 18 9 UART 0 S3F84UA F84U8_UM_REV1 10 SERIAL PORT MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxDO 4 6 or received through the RxDO 4 7 pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTOCONH 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTOCONH 2 while the stop bit is ignored The baud rate for mode 2 is f 16 clock frequency Mode 2 Transmit Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 2 Setthe UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 3 Select mode 2 9 bit UART by setting UARTOCONH bits 7 and 6 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 4 Write transmission data to the shift register UDATAO set 1
158. a reception starts when the receive interrupt pending bit 0 is and the receive enable bit UARTOCONH 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTOCONH 4 is set to 1 PROGRAMMING PROCEDURE To program the UART 0 modules follow these basic steps 1 Configure P4 7 and P4 6 to alternative function RxDO P4 7 TxDO 4 6 for UART 0 module by setting the register to appropriately value Load an 8 bit value to the UARTOCONH L control register to properly configure the UART 0 I O module For interrupt generation set the UART 0 interrupt enable bit UARTOCONH 1 or UARTOCONL 1 to 1 When you transmit data to the UART 0 buffer write data to UDATAO the shift operation starts When the shift operation receive transmit is completed UART 0 pending bit UARTOCONH O or UARTOCONL 0 is set to 1 and an UART 0 interrupt request is generated Qv m m o ELECTRONICS 18 1 UART 0 S3F84UA F84U8_UM_REV1 10 UART 0 HIGH BYTE CONTROL REGISTER UARTOCONH The control register for the UART 0 is called UARTOCONH in set 1 bank 0 at address EEH It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations modes 2 and 3 only UART 0 r
159. a reset RPO points to Registers locations COH C7H and 1 to locations C8H CFH that is to the common working register area NOTE the SSF84UA F84U8 microcontroller pages 0 1 8 are Pages 0 1 8 contain all of the addressable registers in the internal register file Registers Register Addressing Only Indirect Register Addressing Indexed Addressing Modes Addressing Modes Modes m Can be Pointed by Register Pointer Can be Pointed to By register Pointer Figure 2 11 Register File Addressing ELECTRONICS 2 15 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and 1 point to the common working register area locations COH CFH Page 8 LCD Data 1100 0000 Register Area RP1 1100 1000 Figure 2 12 Common Working Register Area 2 16 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES PROGRAMMING TIP
160. am memory location 0104H RR2 working registers RO R2 RB nochange LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 RB nochange LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H 04H LDC note 01 H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 O1H R3 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H 04H LDC 0 1104 RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H R0 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 LDCD LDED Load Memory
161. appended to Name of individual the register name for bit addressing bit or related bits Register location Register address in the internal Register ID Full Register name hexadecimal register file FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Register addressing modelonly Mode Carry Flag C Operation does not generate a carry or borrow condition 0 Operation generates carry out or borrow into high order bit 7 Zero Flag Z Operation result is a non zero value Operation result is zero Sign Flag S Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 R Read only Description of the Bit number W Write only effect of specific MSB Bit 7 R W Read write bit settings LSB Bit 0 Not used Type of addressing RESET value notation that must be used to Not used address the bit x Undetermined value 1 bit 4 bit or 8 bit 0 Logic zero 1 Logic one Figure 4 1 Register Description Format 4 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER ADCON A D Converter Control Register D2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R R W R W R W Addressing Mode Register addressing mode only 7 Not used for the 53 840 8408 6 4 A D Input Pin Selection Bits 3 End of Conversion Bit Read only C
162. apture mode Capture on rising edge counter running can occur 1 lo Capture mode Capture on falling edge counter running OVF can occur 1 PWM mode OVF and match interrupt can occur 2 Timer D1 Counter Clear Bit 3 No effect 1 Clear the timer D1 counter when write 1 Timer D1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer D1 Overflow Interrupt Enable Bit Ea Disable overflow interrupt 1 Enable overflow interrupt NOTE The TD1CON 2 value is automatically cleared to 0 after being cleared counter ELECTRONICS 4 4 N CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 UARTOCONH UART Contro Register High Byte EEH Set 1 Bank 0 Bit Identifier L7 8e 8 4 3 2 a o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W RAN Addressing Mode Register addressing mode only 7 6 UART 0 Mode Selection Bits 0 0 Mode 0 shift register fU 16 x 1 0 1 Mode 1 8 bit UART fU 16 x BRDATAO 1 1 0 Mode 2 9 bit UART fU 16 Mode 3 9 bit UART fU 16 BRDATAO 1 5 Multiprocessor Communication Enable Bit for modes 2 and 3 only 0 Disable Enable 4 Serial Data Receive Enable Bit Disable Enable 3 TB8 Only when UARTOCONL 7 0 Location of the 9th data bit to be transmitted in UART 0 mode 2 or 3 0 or 1 NOTE Ifthe UARTOCONL 7 1 This bit is don t
163. as push pull output or alternative function 4 34 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER PNE4 Port 4 N channel Open drain Mode Register EDH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 Output Mode Selection Output mode push pull Output mode open drain 1 6 P4 6 Output Mode Selection Bit Output mode push pull Output mode open drain 1 5 P4 5 Output Mode Selection Bit Output mode push pull 1 Output mode open drain 4 P4 4 Output Mode Selection Bit Output mode push pull Output mode open drain 1 3 P4 3 Output Mode Selection Bit Output mode push pull Output mode open drain 1 2 P4 2 Output Mode Selection Bit Output mode push pull 1 Output mode open drain 1 P4 1 Output Mode Selection Bit Output mode push pull Output mode open drain 1 0 P4 0 Output Mode Selection Bit Output mode push pull Output mode open drain 1 ELECTRONICS 4 3 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 PGCON Pattern Generation Module Control Register EEH Set 1 Bank 1 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the SSF84UA F84U8 3 S W Trigger Start Bit 0 No effect 00000 S W trigger start auto clear 2 PG Operation Disable Enable Selection Bit ES PG operation disable 1 PG operation Enable
164. ata output input NOTE Parentheses indicate pin number for 42 SDIP 600 package 1 8 Share Pins P2 0 P2 1 2 2 2 7 SEGO SEG5 P3 0 INTO BUZ P3 1 INT1 SO P3 2 INT2 SI P3 3 INTS SCK P3 4 INT4 TD1CLK P3 5 INT5 TD1OUT TD1PWM TD1CAP P3 6 INT6 TDOCLK P3 7 INT7 TDOOUT TDOPWM TDOCAP P4 0 TCOUT TCPWM P4 1 TBPWM P4 2 TACLK P4 3 TAOUT TAPWM TACAP P4 4 TxD1 P4 5 RxD1 P4 6 TxDO P4 7 RxDO P0 0 P0 3 PGO PG3 P0 4 P0 7 PG4 PG7 0 3 ADO AD3 P0 4 PO 7 P4 6 SEG20 P4 7 SEG21 P4 4 SEG18 P4 5 SEG19 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW Table 1 1 S3F84UA F84U8 Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Names Type Description Type Numbers Pins Timer A clock output and PWM output H 42 P4 3 SEG17 TACAP Timer A capture input H P4 3 SEG17 TAOUT TAPWM 4 O 79 lO Timer carrier frequency output H 42 P4 1 SEG15 32 32 31 30 28 28 7 6 6 5 Timer DO clock output PWM H P3 7 SEG13 output lO A external clock input H 42 P4 2 SEG16 INT7 TDOCAP V O Timer DO capture input P3 7 SEG13 INT7 TDOOUT TDOPWM DO external clock input H P3 6 SEG12 INT6 Timer D1 clock output PWM output Timer D1 capture input P3 5 SEG11 INT5 TD1CAP P3 5 SEG1 1 INT5 TD10UT TD1PWM 2 P3 4 SEG10 INT4 21 27 P3 0 SEG6 IN
165. ation Stabilization 22 14 Sub Oscillation Stabilization Time esses 22 14 Internal Flash ROM Electrical Characteristics 22 15 Descriptions of Pins Used to Read Write the Flash 24 4 Reference Table for Connection sess 24 6 Components for 8 4 4 1 0 000 25 4 Setting of the Jumper 2 00440 00 0 25 5 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the page pointer for RAM clear Page 0 1 2 8 Setting the register 2 12 Using the RPs to calculate the sum of a series of registers 2 13 Addressing the common working register area sss nennen enne 2 17 Standard stack operations using PUSH and 4 nennen nennen 2 22 Chapter 5 Interrupt Structure How to prevent the unexpected external interrupts 2 5 10 How to clear an interrupt pending 4 2 enn nnne nnne nnn 5 16 Chapter 7 Clock Circuit How Tous Stop Inistr ctlon cest tee Rei plotted aA
166. aud Rate Shift register fu 16 x BRDATAO 1 8 bit UART fu 16 x BRDATAO 1 9 bit UART fu 16 9 bit UART fu 16 x BRDATAO 1 1 In mode 2 or 3 if the UARTOCONH S bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTOCONH 5 1 then the receive interrut will not be activated if a valid stop bit was not received In mode 0 the UARTOCONH 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 If the UARTOCONL 7 1 This bit is don t care Figure 18 1 UART 0 High Byte Control Register UARTOCONH ELECTRONICS 18 3 UART 0 S3F84UA F84U8_UM_REV1 10 UART 0 Control Register Low Byte UARTOCONL EFH Set 1 Bank 0 R W wo 5 3 re 8 UART 0 transmit parity bit auto Uart 0 transmit interrupt pending bit generation enable bit 0 No interrupt pending when read 0 Disable parity bit auto generation clear pending bit when write 1 Enable parity bit auto generation 1 Interrupt is pending when read 0 transmit interrupt enable bit UART 0 transmit parity bit party 0 Disable Tx interrupt selection bit 1 Enable Tx interrupt 0 Even parity bit 1 Odd parity bit Uart 0 clock selection bits UART 0 receive parity bit 00 fxx 8 selection bit 01 fxx 4 0 Even parity bit check 10 fxx 2 1 Odd pa
167. aves the value 03H in general register and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats 6 58 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET MULT multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dst x src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Setifresultis gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register 20H register 01H 03H register 02H 09H register 06H MULT 00H 02H gt Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01H gt Register OOH register 01H MULT 00H 30H gt Register 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H
168. baud rate register BRDATAQ lets you determine the UART 0 clock rate baud rate UART 0 Baud Rate Data Register BRDATAO F1H Set 1 Bank 0 R W Baud rate data Figure 18 4 UART 0 Baud Rate Data Register BRDATAO BAUD RATE CALCULATIONS Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the UART 0 baud rate data register BRDATAO in set 1 bank at address F1H Mode 0 baud rate f 16 x BRDATAO 1 Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fy clock frequency divided by 16 Mode 2 baud rate f 16 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3 the baud rate is determined by the UART 0 baud rate data register BRDATAO in set 1 bank 0 at address F1H Mode 1 and baud rate fy 16 x BRDATAO 1 ELECTRONICS 18 5 UART 0 S3F84UA F84U8_UM_REV1 10 Table 18 1 Commonly Used Baud Rates Generated by BRDATAO Baud Rate UART Clock fy BRDATAO Decimal Hexadedmal 18 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 BLOCK DIAGRAM Data Bus TB8 BRDATAO 5 D Q UDATAO CLK MSO gt RxDQ Baud Rate CLK MS1 Generator Zero Detector Write to Start UDATAO UARTOCONL 3 2 Tx Control Tx Clock TIP IRQ5 C Interrupt C Rx Clock RIP Receive Rx Control Start Shift Transition Detector 0 Bit Detector Value UDATAO Data Bus Figure 18 5 UART 0 Functional Block Diagram ELECTRONICS
169. be used as inputs for external interrupts INTO INT7 with noise filter interrupt enable and pending control Alternately P3 0 P3 7 can be used as BUZ SO SI SCK TD1CLK TD1OUT TD1PWM TD1CAP TDOCLK TDOOUT TDOPWM TDOCAP or LCD SEG 1 bit programmable port Input or push pull open drain output mode selected by software software assignable pull ups Alternately 4 0 4 7 be used as TCOUT TCPWM TBPWM TACLK TAOUT TAPWM TACAP TxD1 RxD1 TxDO RxDO 9 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all twelve S83F84UA F84U8 I O port data registers Data registers for ports 0 1 2 3 and 4 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary ELECTRONICS 9 3 PORTS S3F84UA F84U8_UM_REV1 10 PORT 0 Port 0 is 8 bit port with individually configurable pins Port 0 pins are accessed directly by writing or reading the port 0 data register PO at location in set 1 bank1 0 0 7 can serve as inputs with or without pull ups and push pull outputs or you can configure the following alternative functions Low byte pins P0 0 P0 3 PGO PG3 AD0 AD3 High byte pins P0 4 P0 7 PG4 PG7 AD4 AD7 Port 0 Control Register POCONH POCONL Port 0 has two 8 bit control registers POCONH for P0 4 P0 7 and POCONL for 0 3 A reset clears the POCONH and POCONL register
170. bit for global interrupt processing ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 QSP lt IP IP lt lt lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 14 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address Data Address Data 0050 0043 Address Data Address PC Enter PC 0110 40 Enter Address H 41 Address H Address L 42 Address L sp Address H 0020 43 Address 20 IPH 00 110 Routine 21 IPL 50 22 Data Memory 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 EXIT exit EXIT Operation Flags Format Example Address PC 0040 51 SP 0022 20 21 22 IP lt SP SP lt SP 2 lt lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instru
171. ble Register 4 9 15 9 17 Port 4 N Channel Open drain Mode Register 9 16 xiv S3F84UA F84U8 UM 1 10 MICROCONTROLLER List of Figures continued Figure Title Page Number Number 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block Diagram neret e 10 4 11 1 Timer Control Register 11 2 11 2 Simplified Timer Function Diagram Interval Timer 11 3 11 3 Simplified Timer A Function Diagram PWM 11 4 11 4 Simplified Timer A Function Diagram Capture 11 5 11 5 Timer A Functional Block 11 6 11 6 Timer B Gontrol Register tette orte inae t eR ERR 11 7 11 7 Timer B Functional Block 11 8 11 8 Timer B Output Flip Flop Waveforms in Repeat 11 10 12 1 Timer C Control Register 0 2 4 244 00 0 00 0000 12 2 12 2 Timer C Function Block Diagram enne 12 3 13 1 Timer DO Control Register TDOCON sse 13 2 13 2 Simplified Timer DO Fu
172. ble or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fxx 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during the normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O Basic Control Register BTCON D3H Set 1 R W Watchdog timer enable bits Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear dvider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 16 Figure 10 1 Basic Timer Control Register 10 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010 The 1010B value disables the watchdog function A reset clears BTCON to automatically enabling the watchdog timer function A reset also selects the CPU clock
173. ble pins ADO AD3 Input or push pull output and software assignable pull ups AD4 AD7 PG4 PG7 I O port with bit programmable pins Input or push pull output and software assignable pull ups P1 2 1 bit programmable output port 44 P1 3 43 port with bit programmable pins COMO0 COM 1 Input or push pull output and software assignable pull ups COM2 COM7 SEGO SEG5 port with bit programmable pins INTO BUZ SEG6G Schmitt trigger input or push pull open INT1 SO SEG7 drain output and software assignable pull INT2 SI SEG8 ups INT3 SCK SEG9 INT4 TD1CLK SEG10 INT5 TD1OUT TD1PWM TD1CAP SEG 1 1 INTe TDOCLK SEG12 INT7 TDOOUT TDOPWM TDOCAP SEG13 port with bit programmable pins 2 TCOUT Schmitt trigger input or push pull output TCPWM SEG14 and software assignable pull ups TBPWM SEG15 TACLK SEG16 TAOUT TAPWM TACAP SEG17 TxD1 SEG18 RxD1 SEG19 TxDO SEG20 RxDO SEG21 NOTE Parentheses indicate pin number for 42 SDIP 600 package ELECTRONICS 1 7 PRODUCT OVERVIEW S3F84UA F84U8_UM_REV1 10 Table 1 1 S3F84UA F84U8 Pin Descriptions Continued Pin Pin Pin Names Type Description COMO0 COM 1 LCD common signal output LCD segment signal output COM2 COM7 LCD segment signal output ADO AD3 converter analog input channels AD4 AD7 AVREF e A D converter reference voltage PGO PGS3 Pattern generation output PG4 PG7 Uart 0 data output input Uart 1 d
174. bles Table Title Page Number Number 1 1 S3F84UA F84U8 Pin 1 7 2 1 SSF84UA Register Type Summary sse 2 4 2 2 S3F84U8 Register Type Summary sse 2 4 4 1 ERE w 4 1 4 2 Set 1 Bank O Registers oisi vn eua eed eee ean da deo daa edad 4 2 4 3 Set T Bank 1 Reglsters s cocer tero etr ce alludes aiea a Ua eade dd vides 4 3 5 1 interrupt mni c 5 6 5 2 Interrupt Control Register Overview ssssssssseeeneeenneeeen nennen 5 7 5 3 Interrupt Source Control and Data 4 5 9 6 1 Instruction Group Summary sse ener nene 6 2 6 2 Flag Notation 6 8 6 3 Instruction Set 5 2 444 0 000 a i ia iiia 6 8 6 4 Instruction Notation Conventions 1 6 9 6 5 Opocode Quick Reference ERR 6 10 6 6 Condition 6 12 8 1 S3F84UA F84U8 Set 1 Register and Values after 8 2 8 2 S3F84UA F84U8 Set 1 BankO Register and Values after RESET 8 3 8 3 S3F84UA F84U8 Set 1 Bank1 Register and Values after RESET 8 4 9 1 SSF84UA F84U8 Port Configuration Overview
175. by setting UARTOCONH bits 7 and 6 to 11B Also select the 9th data bit to be transmitted by writing UARTOCONH 3 8 to 0 or 1 4 Write transmission data to the shift register UDATAO set 1 bank 0 to start the transmit operation Mode 3 Receive Procedure 1 Select the UART 0 clock UARTOCONL 3 and 2 2 Setthe UART 0 transmit parity bit auto generation enable or disable bit UARTOCONL 7 3 Select mode 3 and set the RE Receive Enable bit in the UARTOCONH register to 1 4 The receive operation will be started when the signal at the RxDO P4 7 pin goes to low level fL Write to Shift Register UDATAO L JL JIL JL JL JL Shift TIP mE Transmit Plows RxDO X Start Bit DO D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Bit Detect Sample Time Shift RIP Receive Figure 18 9 Timing Diagram for Serial Port Mode 3 Operation ELECTRONICS 18 11 UART 0 S3F84UA F84U8_UM_REV1 10 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS S3F8 series multiprocessor communication features lets a master SSF84UA F84U8 send a multiple frame serial message to a slave device in a multi S3F84UA F84U8 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2
176. ced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer A match capture interrupt IRQO vector CEH you must write TACON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 1 When a 1 is detected a timer A match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer A match capture interrupt pending bit INTPND 1 Timer A Control Register TACON E2H Set 1 Bank 0 R W 7 5 41 3 2 a o ise Timer A input clock selection bits Timer A overflow interrupt enable bit 000 fxx 1024 0 Disable oveflow interrupt 001 fxx 256 1 Enable overflow interrupt 010 fxx 64 011 fxx 8 Timer A match capture interrupt enable bit 100 fxx 1 0 Disable interrupt 101 External clock TACLK falling edge 1 Enable interrupt 110 External clock TACLK rising edge 111 Counter stop Timer A counter clear bit 0 No effect Timer A op rating mode selection bits 1 Clear the timer A counter when write 00 Interval mode TAOUT 01 Capture mode capture on rising edge Counter running OVF can occur 10 Capture mode Capture on falling edge Counter running OVF can occur 11 PWM mode OVF and match interrupt can occur Figure 11 1 Timer A Control Register TACON 11 2 ELECTRO
177. ck ss IDLE Instruction Figure 7 6 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT S3F84UA F84U8_UM_REV1 10 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the set 1 address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 7 4 System Clock Control Register CLKCON Set 1 R W MSB 6 5 2 4 0 LSB Not used Not used must keep always 0 must keep always 0 Oscillator IRQ wake up function bit Divide by selection bits for CPU clock frequency 0 Enable IRQ for main wake up in power down mode 00 fxx 16 1 Disable IRQ for main wake up in power down mode 01 fxx 8 10 fxx 2 11 fxx 1 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster speed load the appropriate values to CLKCON 3 4 Figure 7 7 System Clock Control Register CLKCON ELECTRONICS S3F84UA F84U8_UM_REV1 10 CLOCK CIRCUIT OSCILLATOR CONTROL REGISTER OSCCON The oscillator control register OSCCON is located in set 1 bank 0 at address FAH It is read write addressable and has the following functions System clock selection Main oscillator control
178. ction You can write until 128byte because this flash sector s limit is 128byte So if you written 128byte must reset FMSECH and FMSECL The program procedure in User program Mode Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Sector Register FMSECH FMSECL to sector value of write address Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load a transmission data into a working register Check user s ID code written by user Set Flash Memory Control Register FMCON to 01010001 Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode 0 Set Flash Memory User Programming Enable Register FMUSR to 00000000B oO PN OR SB NE gt 21 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PROGRAMMING TIP Programming Not ID Code LDC NOP LD SBO LD FMUSR TempO FMSECH 17H FMSECL 80H R2 17H R3 84H R4 78H UserlD Code ZUser value NE Not ID Code FMCON Temp1 RR2 R4 FMUSR 0 FMUSR 0 FMCON 0 EMBEDDED FLASH MEMORY INTERFACE User Program mode enable 0A5H variable is must be setting another routine Set sector address 1780H 17FFH Set a ROM address in the same sector 1780H 17FFH Temporary data Check user s ID c
179. ction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before 1 After Data Address Data 0052 Address Data Address Data PC 0060 PCL old 60 7 60 Main PCH 00 SP 0022 50 140 Exit 2F IPH J 00 50 Data Memory 22 Data Memory Stack Stack ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6 x Example The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 INC Increment INC dst Operation dst lt dst 1 The contents of the destination operand are incremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycl
180. d 18 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S3F84UA F84U8 devices masters and slaves to UART 0 mode 2 or 3 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3F84UA 8 Interconnect TxDO RxDO TxDO RxDO TxDO RxDO TxDO RxDO Master Slave 1 Slave 2 Slave n S3F84UA S3F84UA S3F84UA S3F84UA S3F84U8 S3F84U8 S3F84U8 S3F84U8 Figure 18 10 Connection Example for Multiprocessor Serial Data Communications ELECTRONICS 18 13 S3F84UA F84U8_UM_REV1 10 UART 1 UART 1 OVERVIEW The UART 1 block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Serial with baud rate of fy 16 x BRDATA1 1 8 bit UART mode variable baud rate 9 bit UART mode fy 16 9 bit UART mode variable baud rate UART 1
181. d Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH AND R1 R2 gt Ri 02H R2 AND R1 R2 gt 1 02 2 AND 01H 02H gt RegisterO1H 01H register 02H AND 01H 02H gt Register 01H register 02H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined
182. d The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst cc opc dst 3 8 ccD DA cc 2 0to F dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag 1 00 O1H andregisterO1 20H JP C LABEL_W gt LABEL_W 1000H PC 1000 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement C LABEL replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 JR Jump Relative JR Operation Flags Format Example cc dst If cc istrue PC PC dst If the condition specified by the condition code cc is true the relative addre
183. d into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes even number for program memory odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 14 2 Irr r Given RO 77 30H andR7 00H LDCPD RR6 R0 RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000 1H RO 77H R6 2FH R7 OFFH LDEPD RR 6 RO RR6 lt 6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src r lt rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes an even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opco
184. d pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory 4 Next Instruction LSB Must be Zero uen urren Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Program Memory Address Used p e
185. d to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET NOTATION Table 6 2 Flag Notation Conventions Carry flag Zero flag O Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Z S V D H 0 1 Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opcode 6 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short off
186. ddress FMSECL Flash Memory Sector Address Register Low Byte F7H Set 1 Bank 0 Bit Identifier 27 6 5 4 3 2 44 o 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Flash Memory Sector Address Low Byte The 7 bit to select a sector of Flash ROM 6 0 Not used for the SSF84UA F84U8 NOTE The low byte flash memory sector address pointer value is lower eight bits of the 16 bit pointer address 4 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER FMUSR Flash Memory User Programming Enable Register F8H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits Others Disable user programming mode ELECTRONICS 4 11 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 IMR Interrupt Mask Register DDH Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts P3 4 P3 7 Disable mask Enable unmask le 6 Inte Level 6 IRQ6 Enable Bit External Interrupts P3 0 P3 3 Disable mask 1 Enable unmask 5 Inte Level 5 IRQ5 Enable Bit UARTO 1 Transmit UARTO 1 Receive Disable mask 1 Enable unmask 4 Inte rupt Level 4 IRQ4 Enable
187. de Tool Program Mode Refer to the chapter 24 SSF84UA F84U8 FLASH MCU ELECTRONICS 21 1 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 USER PROGRAM MODE This mode supports sector erase byte programming byte read and one protection mode Hard lock protection The read protection mode is available only in Tool Program mode So in order to make a chip into read protection you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool The S3F84UA F84U8 has the pumping circuit internally therefore 12 5V into Vpp Test pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions programming reading sector erase and hard lock protection NOTES The user program mode cannot be used when the CPU operates with the subsystem clock 2 Be sure to execute the DI instruction before starting user program mode The user program mode checks the interrupt request register IRQ If an interrupt request is generated user program mode is stopped 3 User program mode is also stopped by an interrupt request that is masked even in the DI status To prevent this Be disable the interrupt by using the each peripheral interrupt enable bit 21 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE Flash Memory Co
188. de Addr Mode Hex dst src 2 14 Irr r Given RO 7 21H andR7 LDCPI RR6 RO RR6 lt RR6 1 7FH contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 LDW Load Word LDW dst src Operation dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 HR IR dst src 4 8 C6 RR IML Examples Given R4 06H R5 1CH R6 05H H7 O2H registerOOH register 01H 02H register 02H and register OFH LDW RR6 RR4 gt O6H R7 1CH R4 O6H R5 1CH LDW 00H 02H gt RegisterOOH register 01H OFH register 02H 03H register 03H OFH LDW RR2 R7 R2 OFH LDW 04H 01H gt Register 04H register 05H OFH LDW RR6 1234H gt 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register OEDH In the second example please note that the statement LDW 00 02 loads the contents of the source word 02H 03H into the destination word 01H This le
189. de Addr Mode Hex dst src 2 4 32 6 33 r Ir src dst 3 6 34 R R 35 R IR dst src 3 6 36 R IM Given R1 10H R2 1 registerO1H 20H register 02H register 03H OAH SBC R1 R2 SBC R1 R2 R1 R2 R1 05H R2 03H register 03H OAH SBC 01H 02H Register 01H 1CH register 02H 03H SBC 01H 02H Register 01H 15H register 02H 03H register 03H OAH SBC O1H 8AH gt Register 01H 5H C S andV 1 E gt 3 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 SCF set Carry Flag SCF Operation Flags Format Example C 1 The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 C lt dst 0 dst n lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag Th
190. destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Given RO 12H R1 R2 register OFH and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 Register OFH register31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO0 JR NZ LOOP ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CP
191. ding bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 17 1 SERIAL INTERFACE S3F84UA F84U8_UM_REV1 10 SIO CONTROL REGISTER SIOCON The control register for serial interface module SIOCON is located at E7H in set 1 bank 0 It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first Serial Module Control Register SIOCON E7H Set 1 Bank 0 R W SIO shift clock selection bit SIO interrupt pending bit 0 Internal clock P S Clock 0 No interrupt pending 1 External clock 5 0 Clear pending condition when write C 1 Interrupt is pending Data direction control bit 0 MSB first mode SIO interrupt enable bit 1 LSB first mode 0 Disable SIO interrupt 1 Enable SIO interrupt SIO mode selection bit 0 Receive only mode 1 Transmit receive mode SI
192. directly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Register File BbtRegster sp ADDRESS OPCODE Point to One gt Register Register One Operand File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example REGISTER Instruction dst References OPCODE Points to Program Register Pair 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 gt RPO or RP1 Selected RP points Program Memory to start fo hi working register 4 bit block Working mm dst e Register gt Point to the ADDRESS Address Working Register po tof Value used OPERAND MEM Sample Instruction Figure
193. dressing Mode Register addressing mode only 7 4 Not used for the SSF84UA F84U8 3 Main Oscillator Control Bit 0 Main oscillator RUN Main oscillator STOP 2 Sub Oscillator Control Bit Sub oscillator RUN 1 Sub oscillator STOP Not used for the SSF84UA F84U8 0 System Clock Selection Bit Select main oscillator for system clock 1 Select sub oscillator for system clock 4 18 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER POCONH Port 0 Control Register High Byte DOH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 PG7 AD7 oofa Po ERE Alternative function AD7 Output mode push pull 5 4 P0 6 PG6 AD6 Co Atematve 7119 Atematvetuncion ADs 3 2 P0 5 PG5 AD5 ofo mam Co Atematve tcron PGs 7119 Atematvetuncion ADs 1 0 P0 4 PG4 ADA Co o mumde Fo 1 AemawewmiogGg Alternative function AD4 Output mode push pull ELECTRONICS 4 19 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 POCONL Port 0 Control Register Low Byte D1H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 PG3 AD3 Alternative function AD3 Output mode push pull 5 4 P0 2 PG2 AD2
194. e approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the start bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH L register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 16 1 S3F84UA F84U8_UM_REV1 10 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conv
195. e or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The flag is cleare
196. e OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to O Undefined Unaffected Unaffected IO cONO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR Ri 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111 and source register 01H the value 0000001 1B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 0000001 1B and the source
197. e Range e 20Vto5 5 V at 0 4 4 2 MHz e 2 7V to 5 5 V at 0 4 12 0 MHz Operating Temperature Range 40 C to 85 C Package Type 40 QFP 1010B 42 SDIP 600 IVC e Internal Voltage Converter for 5 V operations Smart Option Low Voltage Reset LVR level and enable disable are at your hardwired option ROM address 3FH ISP related option selectable ROM address 1 3 PRODUCT OVERVIEW BLOCK DIAGRAM Low Voltage Reset 2 0 2 1 COM2 COM7 SEG0 SEG5 P2 2 P2 7 SEG6 SEG13 P3 0 P3 7 SEG14 SEG21 P4 0 P4 7 lt LCD Driver Controller TACLK P4 2 SEG16 gt TACAP P4 3 SEG17 gt on TAOUT TAPWM P4 3 041 TBPWM P4 1 SEG15 8 0 Timer Counter TCOUT TCPWM Sbit Timer P4 0 SEG14 Counter TDOCLK P3 6 INT6 SEG12 gt TDOCAP P3 7 INT7 SEG13 vebi od TDOOUT TDOPWM P3 7 outer TD1CLK P3 4 INT4 SEG10 gt TD1CAP P3 5 INT5 SEG1 1 aula TD1OUT TD1PWM P3 5 vounter SCK P3 3 INT3 SEG9 gt SI P3 2 INT2 SEG8 SIO SO P3 1 INT1 SEG7 Pattern ADO AD7 P0 0 P0 7 PGO PG7 0 bit ADC INTO INT7 P3 0 P3 7 INTERRUPT PGO PG7 P0 0 P0 7 ADO AD7 1 4 P1 1 P1 0 XOUT XTIN XTOUT y f 1 5 Port and Interrupt Control SAM88 RC Core 48KB 8KB ROM T T f f Tf Fi TEST nRESET IVCREF AVREF VDD Vss 550 294 Byte RAM
198. e bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 4 91 IR Given RegisterOOH registerO1H 02H and register 02H 17H RL 00H gt Register 00H 55H C 1 RL 01H gt Register 01H 2 register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 RLC Rotate Left Through Carry RLC Operation dst dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples Set if the bit rotated from the most significant bit position bit 7 was 1 2 Set if the result is 0 cleared ot
199. e instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 14 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC Re is which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 17 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 Selects RPO or Address OPCODE 4 bit address Register pointer provides three provides five low order bits high order bits 2 210 Together they create 8 bit register address Figure 2 13 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register 01110 address 0110 1110 76H Figure 2 14 4 Bit Working Register Addressing Example 2 18 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 11008 indicates that the remaining four bits
200. e interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W Interrupt level enable 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than o
201. e presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3F84UA F84U8 microcontroller Also included in Part Il are electrical mechanical Flash and development tools data It has 19 chapters Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Clock Circuit RESET and Power Down Ports Basic Timer 8 bit Timer A B 8 bit Timer C 16 bit Timer 00 01 Watch Timer LCD Controller Driver 10 bit Analog to Digital Converter S3F84UA F84U8 UM 1 10 MICROCONTROLLER Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Chapter 25 Serial Interface UART 0 UART 1 Pattern Generator Embedded Flash Memory Electrical Data Mechanical Data S3F84UA F84U8 Flash MCU Development To
202. e timer DO counter when write Timer DO operating mode selection bits 00 Interval mode TDOOUT 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur NOTE Refer to the interrupt pending register INTPND for the timer DO s pending bits Figure 13 1 Timer DO Control Register TDOCON 13 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 TIMER DO FUNCTION DESCRIPTION Timer DO Interrupts IRQ3 Vectors D8H and DAH The timer DO can generate two interrupts the timer DO overflow interrupt TDOOVF and the timer DO match capture interrupt TDOINT TDOOVF is belongs to interrupt level IRQ3 vector DAH TDOINT also belongs to interrupt level IRQ3 but is assigned the separate vector address D8H A timer DO overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND 2 interrupt pending bit However the timer DO match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a to the INTPND 3 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer DO reference data register TDOD
203. e value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Given Register register 02H register OBCH and 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H register 03H 0 In the first example if general register contains the value 10011010B the statement SRA OOH shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 SIC SIC SIC Ifsrc 1 1andsrc 0 Othen 3 7 lt src 3 7 If src 1 Oandsrc 0 1 then 3 7 lt src 3 7 If src 1 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 1 3 lt 1 source data bits
204. eceive interrupt control A reset clears the UARTOCONH value to OOH So if you want to use UART 0 module you must write appropriate value to UARTOCONH UART 0 LOW BYTE CONTROL REGISTER UARTOCONL The control register for the UART 0 is called UARTOCONL in set 1 bank 0 at address EFH It has the following control functions UART 0 transmit and receive parity bit selection UART 0 clock selection UART 0 transmit interrupt control A reset clears the UARTOCONL value to OOH So if you want to use UART 0 module you must write appropriate value to UARTOCONL 18 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 UART 0 Control Register High Byte UARTOCONH EEH Set 1 Bank 0 R W vso vs vso woe e se Operating mode and Uart 0 receive interrupt pending bit baud rate selection bits 0 No interrupt pending when read see table below clear pending bit when write Multiprocessor communication pendingywnentead enable bit for modes 2 and 3 only 0 Disable 1 Enable Uart 0 receive interrupt enable bit 0 Disable Rx interrupt 1 Enable Rx interrupt Serial data receive enable bit 0 Disable RB8 Only when UARTOCONL 7 0 Location of the 9th data bit that was received in UART 0 mode 2 or 3 0 or 1 8 9 Only when UARTOCONL 7 0 Location of the 9th data bit to be transmitted in UART 0 mode 2 or 3 0 or 1 MS1 MSO Mode Description B
205. ect Sample Time Shift RIP Receive Figure 19 9 Timing Diagram for Serial Port Mode 3 Operation ELECTRONICS 19 11 UART 1 S3F84UA F84U8_UM_REV1 10 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3F series multiprocessor communication features lets a master SSF84UA F84U8 send a multiple frame serial message to a slave device in a multi SSF84UA F84U8 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2 or 3 In these modes 2 and 3 9 data bits are received The 9th bit value is written to RB8 UART1CONH 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UART1CONH register When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit
206. ectrical Characteristics 40 to 85 Vpp 2 0 V to 5 5 V Programming Time 1 Ftp Chip Erasing Time 2 Sector Erasing Time 9 2 1 The Programming time is the time during which one byte 8 6 is programmed 2 The Chip erasing time is the time during which all 64K byte block is erased 3 The Sector erasing time is the time during which all 128 byte block is erased 4 The Chip erasing is available in Tool Program Mode only ELECTRONICS 22 15 S3F84UA F84U8_UM_REV1 10 MECHANICAL DATA OVERVIEW MECHANICAL DATA The S38F84UA F84U8 microcontroller is currently available in 44 pin QFP and 42 pin SDIP package N e e e ELECTRONICS 13 20 0 3 44 QFP 1010B 0 10 MAX 0 80 0 20 x 0 05 MIN 2 05 0 10 2 30 MAX NOTE Dimensions are in millimeters Figure 23 1 Package Dimensions 44 QFP 1010B MECHANICAL DATA S3F84UA F84U8_UM_REV1 10 42 SDIP 600 14 00 0 2 39 50 MAX 39 10 0 2 0 50 0 1 3 50 0 2 5 08 AMARE HI 1 00 0 1 0 51 MIN NOTE Dimensions in millimeters Figure 23 2 Package Dimensions 42 SDIP 600 ELECTRONICS S3F84UA F84U8_UM_REV1 10 S3F84UA F84U8 FLASH MCU S3F84UA F84U8 FLASH MCU OVERVIEW The S3F84UA F84U8 single chip CMOS microcontroller is the Flash MCU It has an on chip Flash MCU ROM The Flash ROM is accessed by serial data format NOTE This chapter
207. ed into the destination The stack pointer is then incremented by one Flags No flags affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Examples Given RegisterOOH 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H OFBH and stack register OFBH POP 00H gt RegisterOOH 55H SP OOFCH POP 00H gt RegisterOOH 01H register 01H 55H SP 00 In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 55H into destination register and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given RegisterOOH 42H user stack pointer register register 42H 6FH and register 02H POPUD 02H 00H gt Register 41H register 02H 6FH register 42H 6FH If general register OOH contains the value
208. ed of low period time t and high period time When TBOF 0 ti ow TBDATAL 2 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock TBDATAH 2 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock When TBOF 1 ti ow TBDATAH 2 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock thich TBDATAL 2 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock 24usand 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When 0 li ow 24 us TBDATAL 2 TBDATAL 2 x tus TBDATAL 22 15 us TBDATAH 2 fx TBDATAH 2 x 1us TBDATAH 13 When TBOF 1 tuigH 15 us TBDATAL 2 TBDATAL 2 x tus TBDATAL 13 ti ow 24 us TBDATAH 2 fx TBDATAH 2 x 1us TBDATAH 22 ELECTRONICS 11 9 8 S3F84UA F84U8_UM_REV1 10 Timer B Clock 0 TBDATAL 01 FFH TBDATAH 00H TBOF 0 TBDATAL 00H TBDATAH 01 FFH TBOF 0 TBDATAL 00H TBDATAH 00H 1 TBDATAL 00H TBDATAH 00H Timer B Clock 1 TBDATAL DEH TBDATAH 1EH TBOF 0 TBDATAL DEH TBDATAH 1EH 1 7 TBDATAH 7 0 TBDATAL 7 TBDATAH 7 Figure 11 8 Timer Output Flip Flop Waveforms Repeat Mode 11 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10
209. ed stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH andSPL OOH PUSH 40H gt Register 40H 4FH stack register 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000 and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR lt IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given RegisterOOH O3H registerO1H 05H and register 02H PUSHUD 00H 01H Register 00H 02H register 01H
210. em Se Displacement Current Instruction OPCODE Signed Po Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S3F84UA F84U8 control registers are presented an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this refer
211. en ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst sre 6 63 r Ir src dst 3 6 64 R R 65 R IR dst src 3 6 66 R IM Given RO OC7H R1 02H R2 12H register 00 2BH registerO1H 02H and register 02H 23H TCM RO R1 gt RO 0 7 1 RO R1 gt RO 0 7 1 02H registerO2H 23H Z 0 00H01H gt RegisterOOH 2BH registerO1H 02H Z 1 00H 01H gt RegisterOOH 2 register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt RegisterOOH 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F84UA F84U8_UM_REV1 10 Test Under Mask Operation Flags Format Examples dst src dst AND src INSTRUCTION SET This instruction tests selected bits in the destination operand for a logic zero value
212. ence chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers the S3F84UA F84U8 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Resistor Name mnemonic Decimal Hex Rw ao a o aw ImempRemesRedse ma on n Register Pags Poner m 29 om RW ELECTRONICS 4 1 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 Table 4 2 Set 1 Bank 0 Registers C RegserNome mnemonic Timer B Data Register Low Byte TBDATAL SIO Control Register SIOCON SIO Data Register SIODATA Timer B Control Register TBCON Watch Timer Control Register WTCON Timer B Data Register High Byte TBDATAH SIO Pre Scaler Register SIOPS Timer C Counter Register Timer Control Register TCCON STOP Control Register STPCON Timer C Data Register TCDATA UART 0 Control Register High Byte UARTOCONH UART 0 Baud Rate Data Register BRDATAO UART 1 Control Register High Byte UART1CONH UART 0 Control Register Low Byte UARTOCONL UART 1 Control Register Low Byte UART1CONL 2 2 2 2 UART 0 Data Register UDATAO 2 2 2 2 2 Flash Memory sector Agars Reiter FSECL 2e Fm aw
213. ending Timer C 3 bits prescaler bits Timer C interrupt enable bit 000 Non divided 0 Disable interrupt 001 Divided by 2 1 Enable interrupt 010 Divided by 3 011 Divided B 4 Timer C counter clear bit 100 Divided by 5 0 fxx 1 amp PWM mode 101 Divided by 6 1 fxx 64 amp interval mode 110 Divided by 7 Timer C counter clear bit 111 Divided by 8 0 No effect 1 Clear the timer C counter when write Figure 12 1 Timer C Control Register TCCON 12 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER C BLOCK DIAGRAM TCCON 1 TCINT TCCON 7 TCCON 6 4 overflow Data bus Pending 58 TCCON 0 oot 8 bit up counter TCCON 3 Pre Scaler read only TCCON 1 8 bit comparator Pending 0 TCCON 2 fxx 1 M U X fxx 64 Timer C buffer reg TCCON 2 TCOUT TCPWM Timer C data register Data bus NOTE When PWM mode match signal cannot clear counter Figure 12 2 Timer C Functional Block Diagram ELECTRONICS 12 3 S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 16 BIT TIMER 00 01 16 BIT TIMER DO OVERVIEW The 16 bit timer DO is an 16 bit general purpose timer Timer DO has three operating modes one of which you select using the appropriate TDOCON setting Interval timer mode
214. eptember 2008 REVISION DESCRIPTIONS REV 1 10 CHAPTHER 22 ELECTRICAL DATA Table 22 2 D C Electrical Characteristics Page 22 3 40 C to 85 C 2 0 V to 5 5 V Parameter Symbol Conditions Min Vi 20 V Vpp 5 V 50 100 Vin 0 V Vpp 50 150 Ports 0 4 TA 25 Bu Pull up resistor R4 25 100 25 nRESET 0 Vpp 3 V 300 500 Ty 25 nRESET Table 22 2 D C Electrical Characteristics Page 22 4 40 C to 85 C Vpp 2 0 V to 5 5 V Supply current 1 1548 Sub Idle mode Vpp 3 0V 25 C 32kHz crystal oscillator Table 22 2 D C Electrical Characteristics Page 22 4 TA 2 40 to 85 Vpp 2 0 V to 5 5 V Supply current 1 pos Stop mode 25 5 0V T 85 C Vpp 5 0V CHAPTER 21 EMBEDDED FLASH MEMORY INTERFACE NOTES is added in the page 21 2 Preface The S38F84UA F84U8 Microcontroller User s Manual is designed for application designers and programmers who are using the S3F84UA F84U8 microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Chapter 2 Chapter 3 Product Overview Addre
215. er running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur NOTE Refer to the interrupt pending register INTPND for the timer D1 s pending bits Figure 13 6 Timer D1 Control Register TD1CON 13 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 TIMER D1 FUNCTION DESCRIPTION Timer D1 Interrupts IRQ3 Vectors DCH and DEH The timer D1 can generate two interrupts the timer D1 overflow interrupt TD1OVF and the timer D1 match capture interrupt TD1INT TD1OVF is belongs to interrupt level IRQ3 vector DEH TD1INT also belongs to interrupt level IRQ3 but is assigned the separate vector address DCH A timer D1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND 4 interrupt pending bit However the timer D1 match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a to the INTPND 5 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer D1 reference data register TD1DATAH TD1DATAL The match signal generates a timer D1 match interrupt TD1INT vector DCH and clears the counter If for example you write the
216. er ter edie e aene eui 1 12 1 10 Pin Circuit Type HAA P A e eene c etie tente 1 13 1 11 Pin Circuit Type HAT tee e ter eec kn cube 1 13 1 12 Pin Circuit Type He42 P4 eta a Re e tete rd eere cabe 1 14 2 1 Program Memory Address 2 2 2 2 MEE 2 3 2 3 Internal Register File Organization SSF84UA sse 2 5 2 4 Internal Register File Organization SSF84U8 sess 2 6 2 5 Register Page Pointer PP crie ee t 2 7 2 6 Set 1 Set 2 Prime Area Register and LCD Data Register 2 10 2 7 8 Byte Working Register Areas 2 11 2 8 Contiguous 16 Byte Working Register 2 12 2 9 Non Contiguous 16 Byte Working Register 2 13 2 10 16 Bit Register Pall e t n e tete ds 2 14 2 11 Register File Addressing 2 15 2 12 Common Working Register 2 16 2 13 4 Bit Working Register 0 2 18 2 14 4 Bit Working Register Addressing Example 2 2 18 2 15 8 Bit Working Register Addressing 2 19 2 16 8 Bit Working Regis
217. errupt is pending when read NOTE Watch timer clock frequency fw is assumed to be 32 768 kHz 4 52 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F84UA F84UB interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled b
218. ersion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conversion clock with an 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 50 clocks 50 clock x 1us 50 us at 1 MHz A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address D2H in set 1 bank 0 It has three functions Analog input pin selection ADCON 6 4 End of conversion status detection ADCON 3 ADC clock selection ADCON 2 1 A D operation start or disable ADCON 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD7 can be selected dynamically by manipulating the ADCON 4 6 bits And the pins not used for analog input be used for normal I O function A D Converter Control Register ADCON D2H Set1 Bank 0 R W EOC bit is read only Always logic 0 Start or disable bit 0 Disable operation 1 Start operation A D input pin selection bits 000 Clock Selection bit 001 AD1 0 0 fxx 16 010 AD2 0 1 fxx 8 011 AD3 1 0 fxx 4 100 AD4 11 fxx 1 101 AD5 110 AD6 End of conversion bit 111 AD7 0 Conversion not complete 1 Conversion complete Figure 16 1 A D Converter Control Register ADCON 16 2 ELECTRONICS S3
219. es Opcode Addr Mode Hex dst dst 1 4 rE r r OtoF opc dst 2 20 R 4 21 IR Examples Given RO 1BH registerOOH and register 1BH OFH INC RO gt RO 1CH INC OOH gt RegisterOOH INC RO gt RO 1BH registerO1H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H 6 44 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET INCW Increment Word INCW dst Operation dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR Al IR Examples Given RO 1AH R1 02H register02H register 03H OFFH INCW RRO gt RO 03H INCW gt Register 02H register OBH OOH In the first example the working regis
220. eser A D Converter Control Register ADCON Internal Reference Voltage Levels Block Diagram Chapter 17 Serial Interface OVGIVIOW 5 tat Hes aid e Ede ee a a ee e etd ded Programming 5 A SIO Control Register sinn nass tenen rese SIO PRe Scaler Register SIOPS Block Diagram aiite da ce Serial Timing Diagram S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER Table of Contents Continued Chapter 18 UART 0 OVCIVICW eta ad ad et ae et 18 1 Programming Procedure einai 18 1 UART 0 High byte Control Register 0 0 1 2000000000 18 2 UART 0 Low byte Control Register 18 2 UART 0 Interrupt Pending 1 18 4 UART 0 Data Register UDATAO 18 5 UART 0 Baud Rate Data Register 18 5 BAUD Rate Calculations 2 2 ae RE ee top RE eu xe de Pod 18 5 SBIEICUE 18 7 UART 0 Mode 0 Function 18 8 Serial Port Mode 1 Function Description
221. ess START DI LD TBDATAH 160 2 Set 40 us LD TBDATAL 1 Set any value except OOH LD TBCON 00000001B Clock Source lt fosc Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop TBOF high OR 00000100 8 Set P3 0 to TBPWM mode Pulse_out LD TBCON 00000101B Start Timer B operation make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts 11 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER C 8 BIT TIMER C 8 BIT TIMER C OVERVIEW The 8 bit timer C is an 8 bit general purpose timer counter Timer C has two operating mode you can select one of them using the appropriate TCCON setting Interval timer mode Toggle output at TCOUT TCPWM pin only match interrupt occurs PWM mode TCOUT TCPWM pin match and overflow interrupt can occur Timer C has the following functional components Clock frequency divider with multiplexer 8 bit counter 8 bit comparator and 8 bit reference data register TCDATA PWM or match output TCOUT TCPWM Timer C match overflow interrupt IRQ2 vector D4H generation Timer C control register TCCON set 1 0 read write ELECTRONICS 12 1 8 BIT TIMER S3F84UA F84U8_UM_REV1 10 TIMER C CONTROL REGISTER TCCON You use the timer C control register TCCON to
222. fer write data to UDATAt the shift operation starts When the shift operation receive transmit is completed UART 1 pending bit UART1CONH O or UART1CONL 0 is set to 1 and UART 1 interrupt request is generated Qv m m ELECTRONICS 19 1 UART 1 S3F84UA F84U8_UM_REV1 10 UART 1 HIGH BYTE CONTROL REGISTER UART1CONH The control register for the UART 1 is called UART1CONH in set 1 bank 0 at address F2H It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations modes 2 and 3 only UART 1 receive interrupt control A reset clears the UART1CONH value to OOH So if you want to use UART 1 module you must write appropriate value to UART1CONH UART 1 LOW BYTE CONTROL REGISTER UART1CONL The control register for the UART 1 is called UART1CONL in set 1 bank 0 at address F3H It has the following control functions UART 1 transmit and receive parity bit selection UART 1 clock selection UART 1 transmit interrupt control A reset clears the UART1CONL value to OOH So if you want to use UART 1 module you must write appropriate value to UART1CONL 19 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 1 UART 1 Control Register High Byte UART1CONH F2H Set 1 Bank 0 R W vso vs vso woe re eo e se
223. for SCK to SO lkso Ae Input Data Output Data Figure 22 6 Serial Data Transfer Timing 22 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Table 22 9 UART Timing Characteristics in Mode 0 12 0MHz Unt EE 90 Ta 40 C to 85 Vpp 2 0 V to 5 5 V Load Capacitance 80pF Input data hold after clock rising edge o 8 9 NOTES 1 All timings nanoseconds ns and assume 12 0 MHz CPU clock frequency 2 The unit tcp means one UART clock period Figure 22 7 Waveform for UART Timing Characteristics ELECTRONICS 22 11 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 22 12 lt gt aM I LI K Data 45 Out DO X Di X 02 X D3 X D4 X D5 D6 X D7 85 Data In Valid Valid vai XVandy Valid Xalid NOTE symbols shown in this diagram are defined as follows fSCK Serial port clock cycle time 151 Output data setup to clock rising edge ts2 Clock rising edge to input data valid Output data hold after clock rising edge tH2 Input data hold after clock rising edge Figure 22 8 Timing Waveform for the UART Module ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Table 22 10 Main Oscillator Characteristics 40 C to 85 C Vpp 2 0 V to 5 5 V LEE ee SEE Crystal C1 Main oscillation 2 7
224. h voltage All input pins except Vio 3 Input low voltage All input pins except V 22 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRICAL DATA Table 22 2 D C Electrical Characteristics Continued 40 to 85 C Symbol Conditions Min Output high voltage Vou 4 5V to 5 5V Vpp 1 5 All output ports 1 mA Output low voltage Vpp 4 5V to 5 5V All output ports lop 10 mA Input high leakage lund current All input pins except ILIH2 Vpp XTour Input low leakage hing Vin OV current All input pins except for nRESET l2 Vin OV Xin XTn Output high llon Yout Vpp leakage current All output pins Output low leakage lot Vour 0V current All output pins Pull up resistor Vin 0V Vpp 5 Ports 0 4 TA 25 C Vin 0 V av Vin 0 Voo 5V 25 nRESET Vi 20V Vpp 3V 25 nRESET IVi cp Voltage drop i 0 7 SEGx Voltage drop x 0 21 15 per common pin 15 pA per segment pin LCD voltage Ricp Ta 25 C kQ dividing resistor Oscillator feed Rosct Vpp 5 V Ta 25 1700 back resistors Xin Xour 0 V 2 Vpp 5 V Ta 25 C 2200 4500 9000 XTin Voo XTour 0 V ELECTRONICS 22 3 ELECTRICAL DATA S3F84UA F84U8_UM_REV1 10 Table 22 2 D C Electrical
225. herwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt RegisterOOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C In the first example if general register has the value 10101010B the statement RLC OOH rotates one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register 00H resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst lt dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic ove
226. ic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to H Setif there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR dst src 3 6 16 R IM Examples Given R1 10H R2 C flag 1 register 01H 20H register 02H and register 03H ADC R1 R2 gt R1 14H R2 08H ADC R1 R2 gt R1 1BH R2 ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H ADC 01H 11H gt RegisterO1H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement R1 R2 adds and the carry flag value 1 to the destination value 10H leaving 14H in register R1 6 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET ADD ADD Operation Flags Format Examples dst src dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Set if there is a carry from the most significant bit of the result cleared othe
227. idually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location F2H in set 1 bank 1 2 0 2 7 can serve as inputs with or without pull ups and push pull outputs or you can configure the following alternative functions Low byte pins P2 0 P2 3 COMO COM1 2 5 0 COM3 SEG1 High byte pins P2 4 P2 7 COM4 SEG2 COM5 SEG3 COM6 SEG4 COM7 SEG5 Port 2 Control Registers P2CONH P2CONL Port 2 has two 8 bit control registers for P2 4 P2 7 and P2CONL for 2 0 2 3 A reset clears the P2CONH P2CONL registers to configuring all pins to input mode You use control registers settings to select input with or without pull ups or push pull output mode and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module Port 2 Control Register High Byte P2CONH EOH Set 1 Bank 1 R W P2 7 SEG5 P2 6 SEG4 P2 5 SEG3 2 4 5 2 COM7 COM6 5 COM4 P2CONH bit pair pin configuration settings Input mode Input mode pull up Alternative function LCD signal Output mode push pull Figure 9 5 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 7 PORTS S3F84UA F84U8_UM_REV1 10 Port 2 Control Register Low Byte P2CONL E1H Set 1 Ban
228. ied Timer A Function Diagram Capture Mode ELECTRONICS 11 5 8 BIT TIMER S3F84UA F84U8_UM_REV1 10 BLOCK DIAGRAM 0 7 5 Data Bus INTPND O 10 2 gt fxx 64 fxx 8 Clear fxx 1 8 bit Up Counter Read Only 4 1 Vss 8 bit Comparator M TAINT Match U INTPND 1 X oO TAQUT TACAP Timer A Buffer Register TAPWM TACON 4 3 TACON 4 3 Match Signal PG output signal N TACON 2 TAOVF Timer A Data Register Data Bus Figure 11 5 Timer A Functional Block Diagram 11 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER A B 8 BIT TIMER B OVERVIEW The SSF84UA F84US8 micro controller has an 8 bit counter called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Timer B has two functions Asa normal interval timer generating a timer B interrupt at programmed time intervals To supply a clock source to the 8 bit timer counter module timer B for generating the timer B overflow interrupt Timer B Control Register TBCON E3H Set 1 Bank 0 R W Timer B input clock selection bits Timer B output flip flop control bit 00 fxx 0 is low TBPWM low level for 01 fxx 2 low data high level for high data 10 2 fxx 4 1 is high TBPWM high level for 11 fxx 8 low data low level for high data Time
229. ificant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3F84UA F84U8_UM_REV1 10 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load pr
230. ight bit programmable pins for external interrupts ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM88 RC CPU core Memory e Program Memory ROM 48K x 8 bits program memory S3F84UA 8K x 8 bits program memory S3F84U8 Internal flash memory program memory Sector size 128 bytes 10 years data retention Fast programming time User program and sector erase available Endurance 10 000 erase program cycles External serial programming support Expandable OBP on board program sector Data Memory RAM Including LCD display data memory 550 x 8 bits data memory S3F84UA 294 x 8 bits data memory S3F84U8 22 2 2 2 2 2 Instruction Set 78 instructions e Idle and stop instructions added for power down modes 34 I O Pins Output 2 pins 44 QFP only e 10 pins Sharing with other signal pins e 24 pins Sharing with LCD signal outputs Interrupts 8interrupt levels and 22 interrupt sources Fast interrupt processing feature 8 Bit Basic Timer e Watchdog timer function of clock source 8 Bit Timer Counter A e Programmable 8 bit internal timer External event counter function PWM and capture function SS3F84UA F84U8 UM REV1 10 8 Bit Timer Counter B e Programmable 8 bit internal timer Carrier frequency generator 8 Bit Timer Counter C e Programmable 8 bit internal timer e PWM function Two 16 Bit Timer Counter 00 01 e Programmable 1
231. indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 0 0 0 9 60 1 0 9 0 A F 66 1 0 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 0 0 8 1 6 06 0 1 7 0 0 9 0 60 1 1 6 1 6 9 66 1 Set if there was carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD 1 0 C lt 0 H lt 0 Bits 4 7 3 bits 0 3 R1 lt 3CH 1 R1 lt 3CH 06 If addition is performed using the BCD values 15 27 the result should 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 001
232. ing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register i RW Function Description Interrupt mask register IMR R W Bitsettings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels I
233. ion are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register O1H 0000001 1B BXOR R1 01H 1 gt R1 O6H registerO1H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register 1 has the value 07H 00000111 and source register 01H has the value 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 CALL Call Procedure CALL dst Operation SP lt SP 1 QSP lt PCL SP lt SP 1 QSP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction
234. ion chip S3E84U0 is in idle mode e STOP LED This LED is ON when the evaluation chip S3E84U0 is in stop mode ELECTRONICS 25 5 DEVELOPMENT TOOLS IVCREF AVREF P0 7 PG7 AD7 P0 6 PG6 AD6 P0 5 PG5 AD5 P0 4 PG4 AD4 P0 3 PG3 AD3 P0 2 PG2 AD2 P0 1 PG1 AD1 P0 0 PG0 ADO N C P1 1 XTIN P1 0 XTOUT nRESET 2 0 1 2 1 2 2 2 I 5 z 79 5 5 9 SS3F84UA F84U8 UM REV1 10 SEG21 RXDO P4 7 SEG20 TXD0 P4 6 SEG19 RXxD1 P4 5 SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP P4 3 SEG16 TACLK P4 2 1 SEG15 TBPWM PA 1 SEG14 TCOUT TCPWM P4 0 SEG1S INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INT6 TDOCLK P3 6 SEGT11 INT5S TD1OUT TD1PWM TD1CAP P3 5 F4 SEG10 INT4 TD1CLK P3 4 SEG9 INT3 SCK P3 3 r2 SEGB8 INT2 SI P3 2 SEG7 INT1 SO P3 1 I2 SEG6 INTO BUZ P3 0 COM7 SEG5 P2 7 COM6 SEG4 P2 6 FA COMBS SEG3 P2 5 COM4 SEG2 P2 4 COM3 SEG1 P2 3 N C N C N C N C Figure 25 3 50 Pin Connectors J101 for TB84UA 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 P0 3 PG3 AD3 P0 2 PG2 AD2 P0 1 PG1 AD1 PO 0 PGO ADO VDD P1 1 XTIN P1 0 XTOUT nRESET 2 0 COM1 P2 1 2 5 2 2 COM3 SEG1 P2 3 COM4 SEG2 P2 4 COM5 SEG3 P2 5 COM6 SEG4 P2 6 COM7 SEG5 P2 7 SEG6 INTO BUZ P3 0 SEG7 INT1 SO P3 1 Lj O O O Lj O O O O O O O O
235. is about the Tool Program Mode of Flash MCU If you want to know the User Program Mode refer to the chapter 21 Embedded Flash Memory Interface ELECTRONICS 24 1 S3F84UA F84U8 FLASH MCU P0 3 PG3 AD3 P0 2 PG2 AD2 SDAT P0 1 PG1 AD1 SCLK P0 0 PG0 ADO VDD Vss XOUT XIN TEST P1 1 XTIN P1 0 XTOUT L3 vav vod v Od 17 L2 sav sod s od FO 90V 9Dd 9 0d 68 L1 04 L O3S 00Xu Z vd se L1 02945 00 1 9 ve L1 eroas Laxu s vd 1 d38AV 26 L3 d3399AI S3F84UA S3F84U8 44 QFP 1010B l3sauu cL O ed ONOO C4 1 C4 tt c ed 0O3S eWOO C4 91 ed IOdS eEWOO CJ 91 ved eDAS VPNOD 1 Ged EDAS SNOD CJ 81 9 ed vOdS 9WOO CJ 61 L d SDAS LNOD 02 OEd ZNA OLNI 9DAS 12 FEd OS LLNI Z93S 22 S3F84UA F84U8_UM_REV1 10 SEG18 TXD1 P4 4 SEG17 TAOUT TAPWM TACAP P4 3 SEG16 TACLK P4 2 SEG15 TBPWM PA 1 SEG14 TCOUT TCPWM P4 0 SEG13 INT7 TDOOUT TDOPWM TDOCAP P3 7 SEG12 INT6 TDOCLK P3 6 SEG11 INT5 TD1OUT TD1PWM TD1CAP P3 5 SEG10 INT4 TD1CLK P3 4 SEG9 INT3 SCK P3 3 SEG8 INT2 SI P3 2 Figure 24 1 53 840 8408 Pin Assignments 44 QFP 1010B 24 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 IVCREF AVREF P0 7 PG7 AD7 P0 6 PG6 AD6 P0 5 PG5 AD5 P0 4 PG4 AD4 P0 3 PG3 AD3 P0 2 PG2 AD2 SDAT P0 1 PG1 AD1 SCLK P0 0 PG0 ADO VDD Vss XOUT XIN TEST P1 1 XTIN P1 0 XTOUT nRESET 2 0 1 2 1
236. is addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte or 1 lt _ LSB Selects Program OPCODE Memory or Data Memory Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3F84UA F84U8_UM_REV1 10 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selecte
237. isable interrupt Enable interrupt by falling edge Enable interrupt by rising edge 4 28 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER P3PND Port 3 Interrupt Pending Register E8H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 External Interrupt INT7 Pending Bit Clear pending bit when write 1 P3 7 INT7 interrupt request is pending when read 6 P3 6 External Interrupt INT6 Pending Bit Clear pending bit when write 1 P3 6 INT6 interrupt request is pending when read 5 P3 5 External Interrupt INT5 Pending Bit Clear pending bit when write 1 P3 5 INT5 interrupt request is pending when read E P3 4 External Interrupt INT4 Pending Bit Clear pending bit when write 1 P3 4 INT4 interrupt request is pending when read 3 P3 3 External Interrupt INT3 Pending Bit Clear pending bit when write 1 P3 3 INT3 interrupt request is pending when read 2 P3 2 External Interrupt INT2 Pending Bit Clear pending bit when write 1 P3 2 INT2 interrupt request is pending when read 1 P3 1 External Interrupt INT1 Pending Bit Clear pending bit when write 1 P3 1 INT1 interrupt request is pending when read 0 P3 0 External Interrupt INTO Pending Bit Clear pending bit when write P3 0 INTO interrupt request is pending when read ELECTRONICS 4 2 CONTROL REGISTERS S3F84UA F84U8_UM_REV1
238. ising signal edges When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Interrupt Enable and Pending Registers P3INTL P3PND To process external interrupts at the port 3 pins the additional control registers are provided the port 3 interrupt enable register P3INTH high byte E6H set 1 bank 1 Low byte E7H set1 bank1 and the port 3 interrupt pending register E8H set 1 bank 1 The port 3 interrupt pending register lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P3PND register at regular intervals When the interrupt enable bit of any port 3 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding P3PND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a 0 to the corresponding PSPND bit Port 3 Pull up Resistor Enable Register Using the port 3 pull up resistor enable register E9H bank1 you can configure
239. ite R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer DO Input Clock Selection Bits ofo es External clock 1 falling edge 1 1 0 External clock TDOCLK rising edge 4 3 Timer DO Operating Mode Selection Bits o 0 Interval mode Capture mode Capture on rising edge counter running OVF can occur 1 lo Capture mode Capture on falling edge counter running OVF can occur 1 PWM mode OVF and match interrupt can occur 2 Timer DO Counter Clear Bit No effect 3 1 Clear the timer DO counter when write 1 Timer DO Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer DO Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt NOTE The TDOCON 2 value is automatically cleared to 0 after being cleared counter 4 46 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER TD1CON Timer D1 Control Register FBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer D1 Input Clock Selection Bits ofo ees of oja _ Pt fo fo ft S 1 0 1 Extemal clock TDICLK fallingedge 1 1 0 External clock TD1CLK rising edge 4 3 Timer D1 Operating Mode Selection Bits o 0 Interval mode TD1OUT C
240. itted can be assigned a value of 0 or 1 by writing the TB8 bit UART1CONH 3 When receiving the 9th data bit that is received is written to the RB8 bit UART1CONH 2 while the stop bit is ignored The baud rate for mode 2 is f 16 clock frequency Mode 2 Transmit Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 2 Setthe UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 3 Select mode 2 9 bit UART by setting UART1CONH bits 7 and 6 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 4 Write transmission data to the shift register UDATA1 F4H set 1 bank O to start the transmit operation Mode 2 Receive Procedure Select the UART 1 clock UART1CONL 3 and 2 2 Setthe UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 3 Select mode 2 and set the receive enable bit RE in the UART1CONH register to 1 4 The receive operation starts when the signal at the RxD1 P4 5 pin goes to low level lowe Write to Shift Register UDATA1 Shift L JL dL TxD1 start Bit Do xX X pe X D3 X 54 xX 05 X pe X D7 X Tes Stop Bit EEUU c cc Transmit TIP nen m DT SSC Stat TI a RIP Figure 19 8 Timing Diagram for Serial Port Mode 2 Operation 19 10 ELECTRONICS S3F84UA
241. ity Control Bits for Interrupt Groups A B and C Group prortyundefned 71 oloi esca aeea SSS asse O OC oS SyS 1 0 9 8 8 Fr rejas 68 Group priority undefined Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQe IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 gt 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control 18090 gt IRQ1 gt IRQO NOTE Interrupt group A IRQO IRQ1 Interrupt group B IRQ2 IRQ3 IRQ4 Interrupt group C IRQ5 IRQ6 IRQ7 ELECTRONICS 4 1 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 IRQ Interrupt Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupts P3 4 P3 7 Not pending Pending 6 Lev 16 IRQ6 Request Pending External Interrupts 0 Not pending Pending 5 Lev 15 IRQ5 Request Pending UARTO 1 Transmit UARTO 1 Receive Not pending Pending 4 Lev 14 IRQ4 Request Pending Watch
242. k 1 R W P2 3 SEG1 P2 2 SEGO P2 1 COM1 P2 0 COMO COM3 COM2 P2CONL bit pair pin configuration settings 00 Input mode 01 Input mode pull up 10 Alternative function LCD signal 11 Output mode push pull Figure 9 6 Port 2 Low Byte Control Register P2CONL 9 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS PORT 3 Port is an 8 bit I O port with individually configurable pins Port pins are accessed directly by writing or reading the port data register at location F3H in set 1 bank 1 0 7 can serve as inputs with or without pull ups and outputs push pull or open drain And the P3 7 P3 0 can serve as segment pins for LCD or you can configure the following alternative functions Low byte pins P3 0 P3 3 INTO BUZ INT1 SO INT2 SI INT3 SCK High byte pins P3 4 P3 7 INTA TD1CLK INTS TD1OUT TD1PWM TD1CAP INT6 TDOCLK INT7 TDOOUT TDOPWM TDOCAP Port Control Register P3CONL Port 3 has two 8 bit control registers for P3 4 P3 7 and PSCONL for P3 0 P3 3 A reset clears the and registers to configuring all pins to input mode In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal edges Schmitt trigger input with interrupt generation on rising signal edges Schmitt trigger input with interrupt generation on falling r
243. l jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mmy 0000 Always false 1000 Always true 0111 Carry 1111 note note No carry 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal ll ll ll 1 O O O O O a 2 2 5 V V 2 2 n XOR V 0 XOR V 1 NWN o 1111 note Unsigned greater than or equal 0111 note Unsigned less than 1011 Unsigned greater than 0 2 0 1 C OR 2 1 0011 Unsigned less than or equal NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCT
244. le The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including fast interrupt No flags are affected Bytes Cycles Opcode Hex 1 4 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Operation dst lt dst src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 B3 r Ir opc src dst 3 6 B4 R R B5 R IR opc dst src 3 6 B6 R IM Examples Given RO OC7H R1 02H R2 18H register OOH 2BH registerO1H 02H and register 02H 23H XOR RO R1 02H XOR
245. lection Bit Tx at falling edges Rx at rising edges Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit Disable shifter and clock counter 1 Enable shifter and clock counter 4 SIO Interrupt Enable Bit Disable SIO Interrupt 1 Enable SIO Interrupt 0 SIO nterrupt Pending Bit No interrupt pending when read Clear pending condition when write 1 Interrupt is pending ELECTRONICS 4 3 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 SPH stack Pointer High Byte D8H Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 40 ELE
246. multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 Levels Vectors Sources Reset Clear 100H Basic Timer Overflow Timer A Match Capture S W DOH Timer A Overflow H W S W IRQI D2H Timer B Match IRQ2 D4H Timer C Match Overflow S W D8H Timer 00 Match Capture S W DAH Timer DO Overflow H W S W DCH Timer D1 Match Capture S W DEH Timer D1 Overflow H W S W E4H 810 Interrupt S W E6H Watch Timer Overflow S W E8H UART 0 Data Transmit S W EAH UART 0 Data Receive S W UART 1 Data Transmit S W EEH UART 1 Data Receive S W FOH lt P3 0 External Interrupt S W F2H P3 1 External Interrupt S W
247. n PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input pin TACLK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA pins for capture input PWM or match output TAPWM Timer A overflow interrupt IRQO vector DOH and match capture interrupt IRQO vector CEH generation Timer A control register TACON set 1 Bank 0 E2H read write ELECTRONICS 11 1 8 BIT TIMER S3F84UA F84U8_UM_REV1 10 TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode or PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt TACON is located in set 1 Bank 0 at address E2H and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 2 The timer A overflow interrupt TAOVF is interrupt level IRQO and has the vector address DOH When a timer A overflow interrupt occurs and is servi
248. n Control Register PGCON sssssssssssseseeee eee nnne 20 2 S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER Table of Contents Continued Chapter 21 Embedded Flash Memory Interface Overview User Program Mode Flash Memory Control Registers User Program Mode ISP On Board Programming Sector ISP Reset Vector and ISP Sector Size Sector Erase Programming Reading Hard Lock Protection Chapter 22 Electrical Data Overview Chapter 23 Mechanical Data Overview Chapter 24 S3F84UA F84U8 Flash MCU Overview On Board Writing Chapter 25 Development Tools Overview Target Boards Progrmming Socket Adapter TB84UA 8 Target Board Idle LED Stop LED S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1 1 Block Diagram ttti rer tee Re 1 4 1 2 SSF84UA F84U8 Pin Assignments 44 1010 1 5 1 3 SSF84UA F84U8 Pin Assignments 42 5 600 1 6 1 4 Pin Circuit A ett tete e 1 11 1 5 Pin Circuit Type Bs eee eee teg ut E ee E 1 11 1 6 Pin Circuit TYPO Quz ed oue aeu ute e er tei 1 11 1 7 Pin Circuit D 2 P1 0 P 1 1 eret rct toss 1 11 1 8 Pin Circuit ies cette e eu en ted et ei e cete n cabe 1 12 1 9 Pin Circuit Fype He99 i onu Se th
249. n Modes Stop Mode Idle Mode Chapter 9 Ports ecu tein Pudet ese ite t d dtu ee Cot Port Data Registers Port 0 Chapter 10 Basic Timer HET Basic Timer Bi ct Basic Timer Control Register BTCON Basic Timer Function Description S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 bit Timer A B EE 11 1 ADV SUV LOW m D E Lco 11 1 Timer Control Register TACON 11 2 Timer Function 4 4 1 4 1 1 nene enar nnns 11 3 Block DIagEam s hans 11 6 Bite p ET 11 7 11 7 Dia Qe aris TII 11 8 Timer B Pulse Width 9 11 9 Chapter 12 8 bit Timer SEBUM Occit t cO sue Ded ceed ee eet eae dn gees 12 1 JN LEE 12 1 Timer C Control Register 2 12 2 Block Diagram ai iieri iere 12 3 13 16 bit Timer 00 01 8 Bit Timer DO ui eas acm ted ee 13 1 13 1 Timer DO Control Register
250. n clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then after a certain number of machine cycles have elapsed select the main clock by setting OSCCON O to 0 PROGRAMMING TIP Switching the CPU clock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 01H Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07H Start the main clock oscillation CALL DLY16 Delay 16 ms AND OSCCON 06H Switch to the main clock RET DLY16 SRP 0COH LD R0 4 20H DEL NOP DJNZ RO DEL RET ELECTRONICS 7 7 S3F84UA F84U8_UM_REV1 10 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3F84UA F84U8 into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during no
251. nction Diagram Interval Timer Mode 13 3 13 3 Simplified Timer DO Function Diagram PWM 13 4 13 4 Simplified Timer DO Function Diagram Capture 13 5 13 5 Timer DO Functional Block 13 6 13 6 Timer D1 Control Register 1 sss 13 8 13 7 Simplified Timer D1 Function Diagram Interval Timer Mode 13 9 13 8 Simplified Timer D1 Function Diagram PWM 13 10 13 9 Simplified Timer D1 Function Diagram Capture 13 11 13 10 Timer D1 Functional Block 13 12 14 1 Watch Timer Control Register nennen 14 2 14 2 Watch Timer Circuit Diagram enne nnne nnne 14 3 15 1 LCD Function nh ie Paten cann 15 1 15 2 EGD Gircuit DIaQgEalm riter et rr ph te e ee b t coe 15 2 15 3 LCD Display Data RAM Organization eene 15 3 15 4 LCD Gontrol Register tn 15 4 15 5 Internal Resistor Bias Pin Connection 15 5 15 6 Select No Select Signal 1 2 Duty 1 2 Bias Display
252. ne by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3F84UA F84U8 interrupt structure that can be used to release Stop mode are External interrupts P3 0 P3 7 INTO INT7 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register f you use an internal or external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an Internal Interrupt to Release Stop Mode Activate any enabled interrupt causing Stop mode to be released Other
253. ne interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 IPR IPR IPR Group A Group B Group C A1 A2 B1 B2 C1 C2 B21 B22 C21 C22 IRQO 1 2 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts
254. ng of Vpp SCLK and SDAT is very important for proper programming SCLK I O To Application circuit SDAT I O To Application circuit nRESET nRESET To Application circuit C nRESET and C VPP are used to improve the noise effect Figure 24 4 PCB Design Guide for on Board Programming ELECTRONICS 24 5 S3F84UA F84U8 FLASH MCU Reference Table for Connection S3F84UA F84U8_UM_REV1 10 Table 24 2 Reference Table for Connection Pin Name mode Resistor Required value in Applications need is 10 Kohm 50 Kohm VPP TEST Input Yes is 0 01 0 02uF is 2 Kohm 5 Kohm nRESET Input Yes ChRESET is 0 01uF 0 02 Input Yes R is 2 Kohm 5 Kohm SDAT I O oe Output No Input Yes R is 2 Kohm 5 Kohm SCLK O E mom jk Output No 1 on board writing mode very high speed signal will be provided to SCLK and it will cause some damages to the application circuits connected to SCLK or SDAT port if the application circuit is designed as high speed response such as relay control circuit If possible the I O configuration of SDAT SCLK pins had better be set to input mode 2 The value of R C in this table is recommended value It varies with circuit of system ELECTRONICS S3F84UA F84U8_UM_REV1 10 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development
255. ng the captured data value in TDODATAH TDODATAL and assuming a specific value for the timer DO clock frequency you can calculate the pulse width duration of the signal that is being input at the TDOCAP pin see Figure 13 4 TDOOVF TDOCON O IRQ3 16 Bit Up Counter INTPND 2 Overflow INT Interrupt Enable Disable TDOCON 1 TDOCAP input TDOINT IRQ3 INTPND 3 Se INT Match Signal Pending TDOCON 4 3 TDOCON 4 3 y Timer DO Data Register Figure 13 4 Simplified Timer DO Function Diagram Capture Mode ELECTRONICS 13 5 16 00 01 S3F84UA F84U8_UM_REV1 10 BLOCK DIAGRAM TDOCON O TDOCON 7 5 INTPND 2 IRQ3 Data Bus fxx 1024 fxx 256 fxx 64 M fxx 8 16 bit Up Counter fxx 1 Read Only L X 16 bit Co mparator Timer DO Buffer Register TDOCAP i PG output signal TDOCON 4 3 Match Signal TDOCON 2 TDOOVF Timer DO Data Register Data Bus Figure 13 5 Timer DO Functional Block Diagram 13 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 16 BIT TIMER D1 OVERVIEW The 16 bit timer D1 is a 16 bit general purpose timer Timer D1 has three operating modes one of which you select using the appropriate TD1CON setting Interval timer mode Toggle output at TD1OUT pin Capture input mode with a rising or falling edge trigger at the TD1CAP pin PWM mode TD1PWM PWM output sha
256. ns Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Ts 6 52 LDCD LDED Load Memory and 6 54 LDCI LDEI Load Memory and nennen nnns 6 55 LDCPD LDEPD Load Memory with 6 56 LDCPI LDEPI Load Memory with Pre Increment 6 57 LDW LGC WOK 6 58 MULT Multiply Unsigned s ion Le ene IR rb eate 6 59 NEXT ed ee de aa du d ed et i 6 60 No Operation dente ee nd te A eee 6 61 OR P DEA 6 62 Pop ttomietaek sitse ote tute o t 6 63 POPUD Pop User Stack Decrementing sse enne 6 64 POPUI Pop User Stack Incrementing essen 6 65 PUSH tend eme te au d 6 66 PUSHUD Push User Stack enne 6 67 PUSHUI Push User Stack 6 68 RCF Reset Carry Flag aede fe End d dao ta ed a 6 69 RET siu EE 6 70 RL Rotate onn etre To dod usi d Lc 6 71 RLC Rotate Left through 6 72 Rotate Pight 4i tue tL CERE a E 6 73 RRC Rotate Righitithrougli Garr
257. ntrol Register FMCON register is available only in user program mode to select the Flash Memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON Set 1 Bank 0 R W Flash memory mode selection bits Flash operation start bit 0101 Programming mode 0 Operation stop 1010 Sector erase mode 1 Operation start 0110 Hard lock mode This bit will be cleared automatically others Not available Sector erase status bit just after the corresponding operation 0 Success sector erase completed 1 Fail sector erase Not used for S3F84UA 8 Figure 21 1 Flash Memory Control Register FMCON The bitO of FMCON register FMCON 0O is a start bit for Erase and Hard Lock operation mode Therefore operation of Erase and Hard Lock mode is activated when you set FMCON O to 1 Also you should wait a time of Erase Sector erase or Hard lock to complete it s operation before a byte programming or a byte read of same sector area by using LDC instruction When you read or program a byte data from or into flash memory this bit is not needed to manipulate The sector erase status bit is read only Even if IMR bits are 0 the interrupt is serviced during the operation of Sector erase when the each peripheral interrupt enable bit is set 1 and interrupt pending bit is set 1 If an interrupt is requested during the operation of
258. ocation of the 9 data bit that was received in UART 1 mode 2 or 3 0 or 1 NOTE Ifthe UART1CONL 7 1 This bit is don t care 1 Uart 1 Receive Interrupt Enable Bit Disable Rx interrupt Enable Rx interrupt 0 Uart 1 Receive Interrupt Pending Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read NOTES 1 In mode 2 and 3 if the MCE bit is set to 1 then the receive interrupt will not be activated if the received 9 data bit 0 In mode 1 if MCE 1 the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE bit should be 0 2 descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 4 50 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER UART1CONL UART 1 Control Register Low Byte F3H Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 ELECTRONICS 7 6 6 4 8 gt a o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only UART 1 Transmit Parity bit Auto Generation Enable Bit Disable parity bit auto generation Enable parity bit auto generation UART 1 Transmit Parity bit Selection Bit for modes 2 and 3 only Even parity bit Odd parity bit NOTE If the UART1CONL 7 0 This bit is don t care UART 1 Receive Parity bit Selection Bit for modes 2 and 3
259. ode written by user User value is any value by user If not equal jump to Not ID Code Start program 1 51H Temp1 variable is must be setting another routine Write the data to a address of same sector 1784H Dummy Instruction This instruction must be needed User Program mode disable User Program mode disable Programming mode disable NOTE Incase of Flash User Mode the 0 1 5 data values are must be setting another routine Temp0 Temp n variables are should be defined by user ELECTRONICS 21 11 EMBEDDED FLASH MEMORY INTERFACE S3F84UA F84U8_UM_REV1 10 READING The read operation of programming starts by LDC instruction The reading procedure in User program Mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING Reading LD R2 3H Load flash memory upper address to upper of pair working register LD R3 0 Load flash memory lower address to lower pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0H JP NZ LOOP 21 12 ELECTRONICS S3F84UA F84U8_UM_REV1 10 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User set Hard Lock Pro
260. of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET SBC subtract with Carry SBC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opco
261. ogram memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions
262. ols Table of Contents Part Programming Model Chapter 1 Product Overview SSF8 Series 1 1 SS3F84UA F84U8 Microcontroller 1 1 lt ete sat 1 2 Block ETUR 1 4 ASSIQMIMONG 1 5 EE E 1 7 1 11 2 Address Spaces MEE 2 1 ProgramMemory iie idet eit rete tere de he ot ra ue 2 2 SMart Option IE 2 3 Register Architecture tdem e tete AP I e ed i endet dus epe eeu 2 4 Register Fage Pomer ote treten ed eset 2 7 Register Set 1555 t heim iot EA dept d 2 9 Register te tti eet etis tee UT npe o ced Dd ie ee 2 9 iran ei ee Ret P dpt vd temp de I Repeat 2 10 Workingi Registers test aac Doe aree i et 2 11 Using The Register Polnts zeolite lI t en dere de ire der ebd e 2 12 Register Addressing 5 tip nnde Hee e ene p e n eodem sei eo teu th God dnd nth e 2 14 Common Working Register Area
263. on changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R 4 C1 IR Given Register register 01H 02H register 02H 17H andC 0 RRC 00H gt RegisterOOH 2AH C 1 RRC 01H gt RegisterO1H 02H register 02H OBH C 1 In the first example if general register contains the value 55H 01010101B the statement rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK 0 The SBO instruction clears the bank address flag the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 4 Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 SB1 Select Bank 1 SB1 Operation BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area
264. only Even parity bit check Odd parity bit check NOTE Ifthe UART1CONL 7 0 This bit is don t care UART 1 Receive Parity bit Error Status Bit for modes 2 and 3 only No parity bit error Parity bit error NOTE Ifthe UART1CONL 7 0 This bit is don t UART 1 Clock Selection Bits UART 1 Transmit Interrupt Enable Bit Disable Tx interrupt Enable Tx interrupt UART 1 Transmit Interrupt Pending Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 WTCON Watch Timer Control Register E6H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit 0 Main system clock divided by 27 fxx 128 1 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit ES Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 3 2 Watch Timer Speed Selection Bits fo Set watch timer interrupt to 0 5s fo 1 Set watch timer interrupt to 0 25s Set watch timer interrupt to 0 125s Set watch timer interrupt to 1 995ms 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending ES No interrupt pending when read clear pending bit when write Int
265. onversion not complete Conversion complete 2 41 Clock Source Selection Bits oppe Oopa 0 EN Disable operation Start operation 4 5 ELECTRONICS CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 1 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits 3 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 ES No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to 0 3 Thefxxis selected clock for system main OSC or sub OSC 4 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER System Clock Control Register D4H Set 1 RESET Value 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode onl
266. ounter and control passes to the statement whose address is now in the program counter otherwise the instruction following the instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02 2 and register 03H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET DA Decimal Adjust DA Operation Instruction ADD ADC SUB SBC Flags Format dst dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table
267. ounter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tc 65536 see Figure 13 8 Interrupt Enable Disable TD1CON 1 16 Bit Up Counter lt TD1INT IRQ3 INTPND 5 16 Bit Comparator NTPNDS Match INT Capture Signal Pending 7 TP1PWM Output Match Signal data gt counter TD1CON 2 Lower level when TD1OVF data counter Figure 13 8 Simplified Timer D1 Function Diagram PWM Mode 13 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 Capture Mode In capture mode a signal edge that is detected at the TD1CAP pin opens a gate and loads the current counter value into the timer D1 data register You can select rising or falling edges to trigger this operation Timer D1 also gives you capture input source the signal edge at the TD1CAP pin You select the capture input by setting the values of the timer D1 capture input selection bits in the port control register PSCONH 3 2 set 1 bank 1 E4H When P3CONH 3 2 is 00 the TD1CAP input is selected Both kinds of timer D1 interrupts can be used in capture mode the timer D1 overflow interrupt is generated whenever a counter overflow occurs the timer D1 match capture interrupt is generated whenever the counter value is loaded into the timer D1 data register By reading the captured data value in TD1DATAH TD1DATAL and assuming a specific value
268. ource value 03H from the destination value 12H and stores the result OFH in destination register R1 6 82 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET SWAP Swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R 1 IR Given RegisterOOH register 02H 03H andregisterO3H OA4H SWAP 00H gt Register 00 SWAP 02H gt Register 02H register 03H 4AH In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 TCM Test Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is th
269. ow interrupt TD1OVF is interrupt level IRQ3 and has the vector address DEH When a timer D1 overflow interrupt occurs and is serviced interrupt IRQ3 vector DEH you must write TD1CON 0 to 1 When a timer D1 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer D1 match capture interrupt IRQ3 vector DCH you must write TD1CON 1 to 1 To detect match capture interrupt pending condition the application program polls INTPND 3 When a 1 is detected a timer D1 match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer D1 match capture interrupt pending bit INTPND 5 Timer D1 Control Register TD1CON FBH Set 1 Bank 1 R W Timer D1 input clock selection bits Timer D1 overflow interrupt enable 000 fxx 1024 0 Disable overflow interrupt 001 fxx 256 1 Enable overflow interrupt 010 64 Timer D1 match capture interrupt enable bit 011 fxx 8 0 Disable interrupt 100 fxx 1 1 Enable interrupt 101 External clock TD1CLK falling edge 110 External clock TD1CLK rising edge Timer D1 counter clear bit 111 Counter stop 0 No effect 1 Clear the timer D1 counter when write Timer D1 operating mode selection bits 00 Interval mode TD1OUT 01 Capture mode capture on rising edge count
270. perand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 1 2 RO R2 gt RO 37H R2 O1H registerO1H 37H OR 00H 01H gt RegisterOOH register 01H 37H OR 01H 00H RegisterOOH 08H register 01H OR 00H 02H Register 00H OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result SFH in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET POP Pop From Stack POP dst Operation dst lt SP SP lt SP 1 The contents of the location addressed by the stack pointer are load
271. pull up resistors to individual port 3 pins Port 3 N Channel Open drain Mode Register PNE3 Using the port 3 n channel open drain mode register PNE3 set1 bank1 you can configure push pull or open drain output mode to individual port 3 pins ELECTRONICS 9 9 PORTS S3F84UA F84U8_UM_REV1 10 Port 3 Control Register High Byte E4H Set 1 Bank 1 R W P3 7 INT7 P3 6 INT6 5 5 P3 4 INT4 TDOOUT TDOCLK TD1OUT TD1PWM TD1CLK TDOPWM TDOCAP SEG12 TDICAP SEG11 SEG10 SEG13 P3CONH bit pair pin configuration settings Schmitt trigger input mode TDOCAP TDOCLK TD1CAP TD1CLK Alternative function TDOOUT TDOPWM TD1OUT TD1PWM Alternative function LCD signal Output mode Figure 9 7 Port 3 High Byte Control Register Port Control Register Low Byte E5H Set 1 Bank 1 R W To P3 3 INT3 P3 2 INT2 1 P3 0 INTO SCK SEG9 SI SEG8 SO SEG7 BUZ SEG6 P3CONL bit pair pin configuration settings Schmitt trigger input mode in SI Alternative function SCK out SO BUZ Alternative function LCD signal Output mode Figure 9 8 Port 3 Low Byte Control Register P3CONL 9 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS Port 3 Interrupt Control Register High Byte P3INTH E6H Set 1 Bank 1 R W INT6 5 bit pair pin configuration settings Disable interrupt Enable interrupt by falling edge
272. r B mode selection bit Timer B interrupt time selection bits 0 One shot mode 00 Generating after low data is borrowed 1 Repeating mode 01 Generating after high data is borrowed 10 Generating after low and high data are borrowed Timer B start stop bit 11 Not available 0 Stop timer 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt NOTE Pending condition of timer B is cleared automatically by hardware Figure 11 6 Timer B Control Register ELECTRONICS 11 7 8 S3F84UA F84U8_UM_REV1 10 BLOCK DIAGRAM PG output signal TBCON 6 7 TBCON 2 fxx 1 M fxx 2 8 bit 0 fxx 4 Down Counter TBOF fxx 8 Repeat Control TBCON 3 R Interrupt Control INT GEN To Other Block TBPWM Timer B Data Low Byte Register TBCON 4 5 Timer B Data High Byte Register Data Bus The value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts If a borrow occurs in the counter the value of the TBDATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the 8 bit counter Figure 11 7 Timer B Functional Block Diagram 11 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER A B TIMER B PULSE WIDTH CALCULATIONS tHIGH tLOw tLOW To generate the above repeated waveform consist
273. r fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with ei
274. r pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the SSF84UA F84U8 RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice 8 2 0 Not used for the SSF84UA F84U8 4 38 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER SIOCON sio control Register E7H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit Internal clock P S clock 1 External clock 6 Data Direction Control Bit MSB first mode LSB first mode 5 SIO Mode Selection Receive only mode 1 Transmit Receive mode 4 Shift Clock Edge Se
275. rce operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Setif a borrow occurred cleared otherwise 2 Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r src 6 23 r Ir src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH SUB R1 R2 gt R1 OFH R2 SUB R1 R2 gt 1 08H R2 03H SUB 01H 02H gt Register 01H register 02H SUB 01H 02H Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H 1 SUB 01H 65H gt Register 01H OBCH CandS 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value the statement SUB R1 R2 subtracts the s
276. res their output port with TD1OUT pin Timer D1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer External clock input pin TD1CLK 16 bit counter TD1CNTH L a 16 bit comparator and two 16 bit reference data register TD1DATAH L for capture input TD1CAP or match output TD1OUT Timer D1 overflow interrupt IRQ3 vector DEH and match capture interrupt IRQ3 vector DCH generation Timer D1 control register TD1CON set 1 Bank 1 FBH read write ELECTRONICS 13 7 16 00 01 S3F84UA F84U8_UM_REV1 10 TIMER D1 CONTROL REGISTER TD1CON You use the timer D1 control register TD1CON to Select the timer D1 operating mode interval timer capture mode or PWM mode Select the timer D1 input clock frequency Clear the timer D1 counter TD1CNTH T D1CNTL Enable the timer D1 overflow interrupt or timer D1 match capture interrupt TD1CON is located in set 1 and bank 1 at address FBH and is read write addressable using Register addressing mode A reset clears TD1CON to OOH This sets timer D1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer D1 interrupts To disable the counter operation please set TD1CON 7 5 to 111B You can clear the timer D1 counter at any time during normal operation by writing a 1 to TD1CON 2 The timer D1 overfl
277. ressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W cary tag C Zero flag 2 2 Sign Half carry flag Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotat
278. ressing Modes Prime Data Registers All Addressing Modes LCD Display Register Figure 2 4 Internal Register File Organization S3F84U8 2 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S8F84UA F84U8 microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W MSB 7 5 43 2 4 0 Destination register page selection bits Source register page selection bits Destination Page 0 0000 Source page 0 Destination Page 1 Not used for the S3F84U8 0001 Source page 1 Not used for the S3F84U8 Destination Page 8 0010 Source page 8 Others Not used for the S3F84UA 8 Others Not used for the S3F84UA 8 NOTES 1 In the SSF84UA microcontroller the internal register file is configured as three pages Pages 0 1 8 The pages 0 1 are used for
279. rflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given RegisterOOH register 01H 02H and register 02H 17H RR 00H gt RegisterOOH 98 1 01H gt Register 01H 2 register 02H 8BH C 1 In the first example if general register contains the value 31H 00110001B the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 RRC Rotate Right Through Carry RRC Operation dst dst 7 lt C lt dst 0 dst n lt dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destinati
280. rity bit check 11 fxx 1 UART 0 receive parity bit error status bit 0 No parity bit error 1 Parity bit error NOTES 1 If the UARTOCONL 7 0 This bit is don t 2 The bits UARTOCONL 6 4 are for mode 2 and 3 only Figure 18 2 UART 0 Low Byte Control Register UARTOCONL UART 0 INTERRUPT PENDING BITS In mode 0 the receive interrupt pending bit UARTOCONH O is set to 1 when the 8th receive data bit has been shifted In mode 1 the UARTOCONH O bit is set to 1 at the halfway point of the stop bit s shift time In mode 2 the UARTOCONH O bit is set to 1 at the halfway point of the 8 bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTOCONH O bit must then be cleared by software in the interrupt service routine In mode 0 the transmit interrupt pending bit UARTOCONL O is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the UARTOCONL O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTOCONL O bit must then be cleared by software in the interrupt service routine 18 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 0 UART 0 DATA REGISTER UDATAO UART 0 Data Register UDATAO FOH Set 1 Bank 0 R W Transmit or receive data Figure 18 3 UART 0 Data Register UDATAO UART 0 BAUD RATE DATA REGISTER BRDATAO The value stored the UART 0
281. rmal operation that is when both Vpp and RESET are High level the nRESET pin is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation All interrupt is disabled watchdog function basic timer is enabled Ports 0 4 and set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values program counter is loaded with the program reset address the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed at normal mode by smart option reset address at ROM can be changed by Smart Option in the SSF84UA F84USG full flash device Refer to The Chapter 21 Embedded Flash Memory Interface for more detailed contents NORMAL MODE RESET OPERATION In normal mode the Test pin is tied to Vgs A reset enables access to the 64 Kbyte on chip ROM The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use
282. ro is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 2 40H register40H 80H DIV RRO R2 gt RO 1 40H DIV RRO R2 gt RO 20H DIV RRO 20H gt RO 1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation rer 1 f r 0 PC lt dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affec
283. rter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 10 16 Bit Register Pair 2 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ADDRESS SPACES Special Purpose Registers General Purpose Register 4 I 1 Bank 0 Control Registers System Registers CFH Each register pointer RP can independently point Register Pointers to one of the 24 8 byte slices of the register file LCD Data other than set 2 After
284. rwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to H Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt 1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffecte
285. s three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register 0D5H ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R11 o 1 05 If working register R1 contains the value 07H 00000111B the statement BITC 281 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not the zero flag 2 in the FLAGS register OD5H
286. s 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 Slice 32 Slice 31 11111XXX Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX Figure 2 7 8 Byte Working Register Areas Slices ELECTRONICS 2 11 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and 7 in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 8 and 2 9 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set
287. s automatically disabled only when the corresponding pin is selected as push pull output or alternative function Figure 9 16 Port 4 Pull up Resistor Enable Register P4PUR PORTS 9 15 PORTS S3F84UA F84U8_UM_REV1 10 Port 4 N Channel Open drain Mode Register PNE4 EDH Set 1 Bank 1 R W Tas P4 7 P46 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 4 bit configuration settings 0 Push pull output mode Open drain output mode Figure 9 17 Port 4 N Channel Open drain Mode Register PNE4 9 16 ELECTRONICS S3F84UA F84U8_UM_REV1 10 BASIC TIMER BASIC TIMER OVERVIEW S3F84UA F84U8 has an 8 bit basic timer BASIC TIMER BT You can use the basic timer BT in two different ways Asawatchdog timer to provide an automatic reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT set 1 Bank 0 FDH read only Basic timer control register set 1 D3H read write ELECTRONICS BASIC S3F84UA F84U8_UM_REV1 10 BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to ena
288. s borrowed Generating after low and high data are borrowed 1 1 Not available Timer B Interrupt Enable Bit Disable interrupt Enable interrupt Timer B Start Stop Bit Stop timer B Start timer B 1 Timer Mode Selection Bit One shot mode 1 Repeat mode Timer B Output Flip flop Control Bit TBOF is low TBPWM low level for low data high level for high data is high TBPWM high level for low data low level for high data ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER TCCON Timer Co Control Register ECH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Timer Start Stop Bit Stop Timer Start Timer C 6 4 Timer C 3 Bits Prescaler Bits 7 3 Timer Counter Clear Bit No effect 1 Clear the timer C counter when write 2 Timer C Mode Selection Bit fxx 1 amp PWM mode 1 fxx 64 amp interval mode 1 Timer C Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer Interrupt Pending Bit No interrupt pending when read clear pending bit when write 1 Interrupt is pending when read NOTE The TCCON 3 value is automatically cleared to 0 after being cleared counter ELECTRONICS 4 4 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 TDOCON Timer Do Control Register FAH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Wr
289. s carries addresses and data between the CPU and the register file SSF84UA has an internal 48 Kbyte Flash ROM The S3F84U8 has an internal 8 Kbyte Flash ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 22 byte LCD display register file is implemented ELECTRONICS 2 1 ADDRESS SPACES S3F84UA F84U8_UM_REV1 10 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The SSF84UA has 48K bytes internal Flash program memory and the S3F84U8 has 8K bytes The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H in the SSF84UA F84US8 The reset address of ROM can be changed by a smart option only in the 53 840 8408 Full Flash Device Refer to the chapter 21 Embedded Flash Memory Interface for more detail contents Decimal 49 151 Decimal 8 191 48K bytes Internal Program Memory Area 8K bytes Internal Program Memory Area 2 2 Available ISP Sector Area S3F84UA Available ISP Sector Area S3F84U8 Figure 2 1 Program Memory Address Space ELECTRONICS S3F84UA F84U8_UM_REV1 1
290. s long as the reference data value is than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tc x 65536 see Figure 13 3 Interrupt Enable Disable TDOCON 1 16 Bit Up Counter lt TDOINT IRQ3 INTPND 3 16 Bit Comparator INTPND3 Match INT Capture Signal Pending TDOPWM Output Match Signal data gt counter TDOCON 2 Lower level when TDOOVF data counter Figure 13 3 Simplified Timer DO Function Diagram PWM Mode 13 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 16 BIT TIMER 00 01 Capture Mode In capture mode a signal edge that is detected at the TDOCAP pin opens a gate and loads the current counter value into the timer DO data register You can select rising or falling edges to trigger this operation Timer DO also gives you capture input source the signal edge at the TDOCAP pin You select the capture input by setting the values of the timer DO capture input selection bits in the port control register PSCONH 7 6 set 1 bank 1 E4H When P3CONH 7 6 is 00 the TDOCAP input is selected Both kinds of timer DO interrupts can be used in capture mode the timer DO overflow interrupt is generated whenever a counter overflow occurs the timer DO match capture interrupt is generated whenever the counter value is loaded into the timer DO data register By readi
291. s to 00H configuring all pins to input mode You use control registers settings to select input with or without pull ups or push pull output mode and enable the alternative functions Port 0 Pull up Resistor Enable Register POPUR Using the port 0 pull up resistor enable register POPUR D2H set1 bank1 you can configure pull up resistors to individual port 0 pins Port 0 Control Register High Byte DOH Set 1 Bank 1 R W PO 7 PG7 PO 6 PG6 P0 5 PG5 P0 4 PG4 AD7 AD6 AD5 AD4 POCONH bit pair pin configuration settings Input mode Alternative function PG7 PG4 Alternative function AD7 AD4 Output mode push pull Figure 9 1 Port 0 High Byte Control Register POCONH 9 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS Port 0 Control Register Low Byte POCONL D1H Set 1 Bank 1 R W PO 3 PG3 PO 2 PG2 P0 1 PG1 P0 0 PGO AD3 AD2 AD1 ADO POCONL bit pair pin configuration settings Input mode Alternative function PG3 PGO Alternative function AD3 ADO Output mode push pull Figure 9 2 Port 0 Low Byte Control Register POCONL Port 0 Pull up Resistor Enable Register POPUR D2H Set 1 Bank 1 R W Term 0 7 06 P0 5 04 PO 3 PO2 PO 0 POPUR bit configuration settings 0 Disable Pull up Resistor 1 Enable Pull up Resistor NOTE pull up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push pull outp
292. set addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS Actual Operand Range See list of condition codes in Table 6 6 Rn n 2 0 15 Rn b n 0 15 b 0 7 Rn n 2 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg 0 255 n 0 15 RRp 0 2 14 RRp or reg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 Table 6 5 Opcode Quick Reference OPCODE MAP LT TG LL loedel Jel DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 2 12 R2 R1 IR2 R1 R1 IM r0O Rb RLC RLC ADC ADC ADC ADC ADC BCP 1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r0O Rb JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1
293. set the WTCON 6 to 1 The watch timer overflow interrupt pending condition WTCON 0 must be cleared by software in the application s interrupt service routine by means of writing a 0 to the WTCON O interrupt pending bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON 0 is automatically set to 1 and interrupt requests commence in 1 995 ms 0 125 0 25 and 0 5 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 995 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller Therefore if the watch timer is disabled the LCD controller does not operate Watch timer has the following functional components Real Time and Watch Time Measurement Using a Main Clock Source or Sub clock Clock Source Generation for LCD Controller f pin for Buzzer Output Frequency Generator BUZ Timing Tests in High Speed Mode Watch timer overflow interrupt IRQ4 vector E6H generation Watch timer control register WTCON set 1 bank 0 E6H read write ELECTRONICS 14 1 WATCH S3F84UA F84U8_UM_REV1 10 WAT
294. sing eed ete eet Pte eet tee date anand 5 18 Chapter 6 Instruction Set 6 1 Data TVp6s ert et 6 1 Register AddreSsitg 1 1 6 1 Addressing MOGSS 2 eee tote e 6 1 Flags Register FEAGS uote eta ere eon hee tete tecti uade cea chum adis 6 6 Flag esetre tT orte tet ot nee et a BE Pe it e P bee ri otn n 6 7 Instruction Set eiie te t eter te ie od reete etra due Deci Mx d edo 6 8 Gonditlon GOod6OS ett etie tbe tete ee ber eee ea cd aa o elas 6 12 Instruction Descriptions o et get 6 13 vi S3F84UA F84U8 UM 1 10 MICROCONTROLLER Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit Overview System Clock Circuit Main Oscillator Circuits Sub Oscillator Circuits Clock Status During Power Down Modes ccccccceeeeeeeeeeceeeeecaeeeeeeeeceaeeeeaaeeeeaaeseeeeeseaeeeseaaeseeneeeeaeees System Clock Control Register CLKCON Oscillator Control Register OSCCON Stop Control Register STPCON Switching the CPU Clock Chapter 8 RESET and Power Down System RESET JVerVIGW s cuc xoc ete C o d on bano puer t Normal Mode RESET Operation Hardware RESET Values Power Dow
295. ss Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure Instruction Set Chapter 1 Product Overview is a high level introduction to SSF84UA F84UB8 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the SSF8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the SSF84UA F84UB interrupt structure in detail and further prepares you for additional information presented the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S8F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction ar
296. ss is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst cc dst 2 6 ccB RA cc OtoF NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR CLABELX 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 r IM r8 r R r OtoF opc dst src 2 4 C7 r Ir D7 Ir r src dst 3 E4 R R R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R opc dst src 3 6 87 r x r opc 5 dst 3 6 97 x r r ELEC
297. ster 227 0 0 0 Port 3 Control Register High Byte Port Control Register Low Byte 229 ESH o 0 O Port 3 Interrupt Control Register High Byte Eee Port 3 Interrupt Control Register Low Byte P3INTL 231 E7H Port Interrupt Pending Register 232 0 0 O Port 3 Pull up Resistor Enable Register 233 E9H 0 0 0 Port 4 Control Register High Byte P4CONH 234 EAH 0 0 0 Port 4 Control Register Low Byte P4CONL 235 0 0 0 Port 4 Pullup Resistor Enable Register P4PUR _ 236 ECH o o 0 Port 4 N Channel Open drain Mode Register 4 237 EDH 0 Patern Generation Control Register PGCON 238 Paten Generation Data Register PGDATA 239 0 6 Pon 0 Data Registe Po 240 FoH o 9 Port Data Register For 2 Data Regster P2 FzH 0 o 6 Port3DataRegister P3 243 Pot4DataRegster P4 244 FdH O O O LoD Connor regse icon zes FH o o 0 ToocnTa ae Few o fo Timer D0 Counter Register Low Byte TDocnTL 247 Fm 9 9 9 Timer D0 Gonti Register 250 FAM 9 0 0 Timer D1 Contel Register 251 Fen o 6 0 Timer D1 Counter Register ig Byte 252 Fon o o
298. support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84UA 8 is a specific target board for the development of application systems using S8F84UA F84U8 PROGRAMMING SOCKET ADAPTER When you program S3F84UA F84U8 s flash memory by using an emulator or OTP MTP writer you need a standard programming socket adapter for SSF84UA F84U8 ELECTRONICS 25 1 DEVELOPMENT TOOLS S3F84UA F84U8_UM_REV1 10 IBM PC AT or Compatible Emulator SK 1200 RS 232 USB RS 232C USB or OPENice i 500 RS 232 Target Application System Probe Adapter TB84UA 8 Target Board EVAChip Figure 25 1 Emulator Product Configuration 25 2 ELECTRONICS S3F84UA F84U8_UM_REV1 10 DEVELOPMENT TOOLS TB84UA 8 TARGET BOARD The TB84UA 8 target board can be used for development of
299. t ELECTRONICS 5 17 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR 2 Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP
300. t mode 0 by setting UART1CONH 7 and 6 to 00B Clear the receive interrupt pending bit UART1CONH 0 by writing a 0 to UART1CONH O Set the UART 1 receive enable bit UART1CONH 4 to 1 The shift clock will now be output to the TxD1 P4 4 pin and will read the data at the RxD1 P4 5 pin A UART 1 receive interrupt occurs when UART1CONH 1 is set to 1 o gr Qv mw Write to Shift Register UDATA1 Shift RxD1 Data Out Do X D X pe X X w X TxD1 Shift Clock Transmit Clear RIP and set RE Shift RxD1 Data In DO D1 D2 D3 D4 D5 D6 D7 TxD1 Shift Clock _ Figure 19 6 Timing Diagram for Serial Port Mode 0 Operation 19 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 UART 1 SERIAL PORT MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD1 P4 4 pin or received through the RxD1 P4 5 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the UART 1 clock UART1CONL 3 and 2 Set the UART 1 transmit parity bit auto generation enable or disable bit UART1CONL 7 Select the baud rate to be generated by 1 Select mode 1 8 bit UART by setting UART1CONH bits 7 and 6 to 01B Write transmission data to the shift register UDATA1 F4H set 1 bank 0 The start
301. tection by write 0110 in FMCON 7 4 If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The hard lock protection procedure in User program Mode Set Flash Memory User Programming Enable Register FMUSR to 10100101B Check user s ID code written by user Set Flash Memory Control Register FMCON to 01100001 Set Flash Memory User Programming Enable Register FMUSR to 00000000B 2 PROGRAMMING Hard Lock Protection SBO LD CP JR LD NOP LD Not ID Code SBO LD FMUSR TempO User Program mode enable 0A5H variable is must be setting another routine UserlD Code zUser value Check user s ID code written by user User value is any value by user NE Not ID Code If not equal jump to Not ID Code FMCON Temp1 Hard Lock mode set amp start 1 61H 1 variable is must be setting another routine Dummy Instruction This instruction must be needed FMUSR 0 User Program mode disable FMUSR 0 User Program mode disable FMCON 0
302. ted Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken 8 jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 El Enable Interrupts El Operation Flags Format Example SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM 00H El If the SYM register contains the value that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts is the enable
303. ted borrow into bit 3 1 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read 1 Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected 1 Bank 1 is selected 4 8 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER Fiash Memory Control Register F9H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits Programmingmede S Sectorerasemode Fo v o mmwkmd Others Not available 3 Sector Erase Status Bit Read only Success sector erase 1 Fail sector erase P Not used for the SSF84UA F84U8 0 Flash Operation Start Bit Operation stop bit 1 Operation start bit NOTE The FMCON O will be cleared automatically just after the corresponding operation completed ELECTRONICS 4 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 FMSECH Flash Memory Sector Address Register High Byte F6H Set 1 Bank 0 Bit Identifier _ 5 4 3 2 4 0 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Bits High Byte 15 8 to select a sector of Flash ROM NOTE The high byte flash memory sector address pointer value is higher eight bits of the 16 bit pointer a
304. ter Addressing Example eene 2 20 2 17 Stack Operatlons tire eee itl ce tn RE ODER 2 21 3 1 Register Addressing eiit ie erc RAE DURER RAE DERE XE CORR RARUS 3 2 3 2 Working Register Addressing sessesssssssssseseeennee nennen nnne 3 2 3 3 Indirect Register Addressing to Register File 3 3 3 4 Indirect Register Addressing to Program 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load Instructions ssssssseeeneen 3 10 3 11 Direct Addressing for Call and Jump 3 11 3 12 Indirect Addressirig ket eec tk 3 12 3 13 Relative Addressing ate e ee e ree E D tete ese 3 13 3 14 Immediate Addressirig rre 3 14 53 840 8408 UM REV1 10 MICROCONTROLLER xiii List of Figures Continued Figure Title Page Number Number 4
305. ter pair RRO contains the value in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW Ri uses Indirect Register IR addressing mode to increment the contents of general register from OFFH to 00H and register 02H from OFH to 10H NOTE A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal IRET Fast FLAGS lt SP IP SP lt SP 1 FLAGS lt FLAGS PC lt SP FIS lt 0 SP lt SP 2 SYM 0 lt 1 This instruction is used at the end of an interrupt service routine It restores the register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode
306. terrupt is pending when read 1 Timer A Match Capture Interrupt Pending Bit No interrupt pending when read clear pending bit when write Interrupt is pending when read 0 Timer Overflow Interrupt Pending Bit EN No interrupt pending when read clear pending bit when write Interrupt is pending when read ELECTRONICS 4 13 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 IPH instruction Pointer High Byte DAH Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER IPR Interrupt Priority Register FFH Set 1 Bank 0 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Prior
307. ters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM246
308. the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET POWER DOWN S3F84UA F84U8_UM_REV1 10 HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 SS3F84UA F84U8 Set 1 Register and Values After RESET ReglsterName Mnemonis Adde E ME Dec Hex 7 6 5 4 2 14 0 Locations DOH D2H are not mapped Jp Locations DOH D2H not mapped 0 Basictimercontrolregister BTCON 211 O O O O O System clock control register CLKCON 212 D4H 0 0 O System flags register FLAGS 213 DSH x x x x x x 0 0 Register pointero 1 RPo 214 D6H 1 1 Oo 0 O Register pointeri 215 DzH 1 1 0 0 1 x Interrupt request register 220 DCH 0 o 0 System mode register swm 222
309. the port 4 pull up resistor enable register PAPUR ECH set1 bank1 you can configure pull up resistors to individual port 4 pins Port 4 N Channel Open drain Mode Register PNE4 Using the port 4 n channel open drain mode register PNE4 EDH set1 bank1 you can configure push pull or open drain output mode to individual port 4 pins Port 4 Control Register High Byte EAH Set 1 Bank 1 R W P4 7 SEG21 P4 6 SEG20 P4 5 SEG19 P4 4 SEG18 RxDO TxDO RXxD1 TxD1 P4CONH bit pair pin configuration settings 00 Input mode RxDO RxD1 Alternative function RXDO TxDO RxD1 TxD1 Alternative function LCD signal Output mode Figure 9 14 Port 4 High byte Control Register P4CONH 9 14 ELECTRONICS S3F84UA F84U8_UM_REV1 10 ELECTRONICS Port 4 Control Register Low Byte P4CONL EBH Set 1 Bank 1 R W 4 3 5 17 P4 2 SEG16 P4 1 SEG15 P4 0 SEG14 TAOUT TAPWM TBPWM TCOUT TCPWM P4CONL bit pair configuration settings Input mode Alternative function TAOUT TAPWM TBPWM TCOUT TCPWM Alternative function LCD signal Output mode Figure 9 15 Port 4 Low byte Control Register P4CONL Port 4 Pull up Resistor Enable Register PAPUR ECH Set 1 Bank 1 R W P4 7 P4 6 P4 5 P4 4 P4 2 P4 1 P4 0 P4PUR bit configuration settings 0 Disable Pull up Resistor 1 Enable Pull up Resistor NOTE A pull up resistor of port 4 i
310. ther type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends ELECTRONICS 5 19 S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET INSTRUCTION SET OVERVIEW The 8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least sign
311. tion In summary the following events occur when stop mode is released 1 During the stop mode a power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an interrupt is used to release stop mode the value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTONT 4 overflow occurs the normal CPU operation resumes ELECTRONICS 10 3 BASIC S3F84UA F84U8_UM_REV1 10 RESET or STOP Bits 3 2 Basic Timer Control Register Write 1010xxxxB to Disable Data Bus 1 4096 Y 8 Bit Up Counter Read Only fxx 1024 Start the CPU NOTE NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3F84UA F84U8_UM_REV1 10 8 BIT TIMER A B 8 BIT TIMER A B 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes one of which you select using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TACAP pi
312. ttp www seminix com GW uni Gang Programmer for OTP MTP FLASH MCU 8 devices programming at one time Download Upload and data edit function PC based operation with USB port Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection Fast programming speed 4Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software e Will be developed in March 2008 SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com 25 10 ELECTRONICS S3F84UA F84U8_UM_REV1 10 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER Continued AS pro SEMINIX On board programmer for Samsung Flash MCU e Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e HEX file download via USB port from PC e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter
313. ull 1 Output mode open drain 4 P3 4 Output Mode Selection Bit Output mode push pull Output mode open drain 1 3 P3 3 Output Mode Selection Bit Output mode push pull Output mode open drain 1 2 P3 2 Output Mode Selection Bit Output mode push pull 1 Output mode open drain 1 P3 1 Output Mode Selection Bit Output mode push pull Output mode open drain 1 0 P3 0 Output Mode Selection Bit Output mode push pull Output mode open drain 1 ELECTRONICS 4 3 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 P4CONH Port 4 Control Register High Byte EAH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 RxD0 SEG21 0 Input mode RxDO Alternative function RxDO out Em Alternative function LCD signal Output mode 5 4 P4 6 TxD0 SEG20 Fo Atematve cion ix 7119 Atematve function LoD signa 3 2 P4 5 RxD1 SEG19 9 Atematve uncionar io Atematveuncton CD signa 1 0 P4 4 TxD1 SEG18 fo 70111 ENSE Alternative function LCD signal Output mode 4 32 ELECTRONICS S3F84UA F84U8_UM_REV1 10 CONTROL REGISTER P4CONL Port 4 Control Register Low Byte EBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 TAOUT TAPWM TACAP SEG17 0
314. ut or alternative function Figure 9 3 Port 0 Pull up Resistor Enable Register POPUR ELECTRONICS 9 5 PORTS S3F84UA F84U8_UM_REV1 10 PORT 1 Port 1 is an 4 bit I O port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location F1H in set 1 bank1 P1 0 P1 1 can serve as inputs with or without pull ups and push pull outputs or you can configure the following alternative functions Low nibble Pins P1 0 P1 1 XTOUT XTIN Port 1 Control Register P1CON Port 1 has one 4 bit control registers P1 CON for P1 1 P1 0 A reset clears the P1CON registers to configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors select push pull mode and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Control Register P1 CON E2H Set 1 Bank 1 R W Not used for the SSF84UA 8 1 1 1 0 P1CON bit pair pin configuration settings Input mode Input mode pull up Alternative function XTIN XTOUT Output mode push pull Figure 9 4 Port 1 Control Register 9 6 ELECTRONICS S3F84UA F84U8_UM_REV1 10 PORTS PORT 2 Port 2 is an 8 bit I O port with indiv
315. value 1087H to TD1 DATAH TD1DATAL the counter will increment until it reaches 1087 At this point the timer D1 interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer D1 output pin is inverted see Figure 13 7 Interrupt Enable Disable TD1CON 1 16 Bit Up Counter lt lt TD1INT IRQ3 INTPND 5 16 Bit Comparator INTPND S Match INT Capture Signal Pending TD1OUT Timer D1 Buffer Register TD1CON 4 3 Match Signal lt TD1CON 2 TD1OVF Timer D1 Data Register Figure 13 7 Simplified Timer D1 Function Diagram Interval Timer Mode ELECTRONICS 13 9 16 00 01 S3F84UA F84U8_UM_REV1 10 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TD1PWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer D1 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFFFH and then continues incrementing from 0000H Although you can use the match signal to generate a timer D1 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TD1PWM pin is held to Low level as long as the reference data value is than or equal to lt the c
316. working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F84UA F84U8_UM_REV1 10 INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b isa then lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F84UA F84U8_UM_REV1 10 BTJRT sit Test Jump Relative on True BTJRT Operation
317. y D e teer t Des cte en 6 74 SBO Select Bank O 8s re ate be tetto alt 6 75 SB1 Select Bank Iifar ia ee ee raa ed dae des 6 76 SBC Subtract with Camry isis ir cie ee oreste Hed i de edet 6 77 SCF SEL Canny 6 78 SRA Shift Aight Arithmetica e th e uet terae tet ud 6 79 SRP SRPO SRP1 Set Register 6 80 STOP Stop e d ed TRE uite QU De 6 81 SUB tatto i d A Lum La e Ut 6 82 SWAP 66 6 83 Test Complement under 0 1 1 11100 6 84 Test under Mask eie deed ede d cel 6 85 WFI Walt for 6 86 XOR Eogical Exclusive OR rn a a 6 87 xxvi S3F84UA F84U8_UM_REV1 10 MICROCONTROLLER S3F84UA F84U8_UM_REV1 10 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Among the major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupts
318. y 7 Oscillator IRQ Wake up Function Bit ES Enable IRQ for main wake up in power down mode Disable IRQ for main wake up in power down mode 6 5 Not used for the SSF84UA F84U8 4 3 CPU Clock System Clock Selection Bits note oopen SSCS rots me SSCS rr fo SSCS 2 0 Not used for the S3F84UA F84U8 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3F84UA F84U8_UM_REV1 10 FLAGS System Flags Register D5H Set 1 RESET Value X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 5 1 Operation generates negative number MSB 1 4 Overflow Flag V Operation result is lt 127 gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction genera
319. y IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware SSF84UA F84U8 uses twenty two vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3F84UA F84U8 interrupt structure there are twenty two possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F84UA F84U8_UM_REV1 10 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2
320. y User Programming Enable Register 4 11 IMR Interrupt Mask a nnne neris 4 12 INTPND Interrupt Pending enn 4 13 IPH Instruction Pointer High Byte 4 14 IPL Instruction Pointer Low Byte 4 14 IPR Interrupt Priority Register iaa aAA EAK KE eai PARE mener nennen nnns 4 15 IRQ Interrupt Request Register 4 01 E 4 16 LGD Gontrol Registers 2 eiie vende 4 17 OSCCON Oscillator Control Register sesenta 4 18 POCONH Port 0 Control Register High 4 19 POCONL Port 0 Control Register Low 4 20 POPUR Port 0 Pull up Resistor Enable 4 21 P1CON Port 1 Gontrol Register I er eta 4 22 P2CONH Port 2 Control Register High 4 23 P2CONL Port 2 Control Register Low 2 0 4 404000 4 24 Port Control Register High 4 25 PSCONL Port Control Register Middle 4 26 PSINTH Port Interrupt Control Register High Byte 4 27 PSINTL Port Interrupt Control Register Low 2

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