EP8548A 1.2 (DES0212), User Manual
Contents
1. elec iieee iiie e leen enn ns 27 ga MES ANT M 27 Procesa eer en 27 28 COPF T 28 MNC enal Hp ola RR 29 MME D nie M 29 Aa DE Fma RR 29 ANC COOCOO E E E A 29 S ODO ANON were 33 Sye KESE EP USADIO N aaa aq ere 33 loo C aes anes 33 ale RP 33 Uer 0 6 acti los q etat rere bI daa iu Us Dd errs 34 CODDICCLI ODE as css sation tact asses cowe na 34 P5010000086RA00 Preliminary 2 February 2007 9 AdvancedMC EP8548A 1 2 Contents continued Chapter 7 Board Control and Status Registers cccccseesesseeseeeesseeeeeeeeeeeseeseenseeeeeneesees 35 Chapter 8 Memory and Interrupts enhn ann unes a anna annus 39 IV NORV E 39 Externat O ae E X 8 39 Ap2. 200 pin SODIMM connector e One2x8 header for JTAG COP access e One1x3 header for MMC RS 232 serial port e One2x8 header for MMC debug port e One1x2 header for external 12 VDC fan e AMC bus connector This chapter describes these connectors and headers Refer to Figure 2 2 for the locations of these connectors and headers Power Refer to Table 1 1 for input power requirements Stand Alone When operating in stand alone mode the EP board is powered from 12 VDC supplied through the barrel connector PWR 1 An onboard regulator generates 3 3 VDC to power the MMC The specifications for the mating connector are Inner diameter 2 1 mm 0 083 inches Outer diameter 5 5 mm 0 217 inches Outer shell is GND Inner shell is 12 VDC AMC When operating in AMC mode the EP board is powered from the AMC connector of the carrier card or from the chassis backplane Both 12 VDC to power the board and 13 3 VDC to power the MMC are required Processor Monitor Port The RS 232 monitor port is connector P11 It is an RJ 45 connector Table 5 1 shows the port pinout The monitor port is from UARTO P5010000086RA00 Preliminary 2 February 2007 27 Chapter 5 Connectors and Headers AdvancedMC EP8548A 1 2 Table 5 1 Monitor Port Pinout P11 Function i Function NOTE 1 Pin numbering is from right 1 to left 8 when looking into the RJ 45 jack with the locking tab on top Ethernet Port
3. The CLK_OUT of the processor routes to the CPLD for timing purposes The actual frequency of the CLK_OUT signal depends on the clock selection in the processor An onboard 25 MHz crystal oscillator FX532 or equivalent provides the clock input needed by the Ethernet transceiver The Ethernet controller eTSEC of the processor requires a 125 MHz external clock input The Ethernet transceiver gen erates the 125 MHz clock to the processor EC_GTX_CLK125 from its 25 MHz clock input The high speed SERDES interface of the processor requires either a 100 MHz or 125 MHz LVDS clock reference to operate SRIO at either 1 25 2 5 or 3 125 Gbaud A frequency synthesizer device IC5840001 34 generates the 100 MHz or 125 MHz clock from an onboard 25 MHz crystal oscillator FX532 or equivalent input An LVDS clock fan out buffer ICS8545 selects either the 100 MHz or 125 MHz single ended input and distributes it to the processor as an LVDS refer ence clock SD REF CLK SD REF CLK NOTE An option to clock the SERDES interface from CLK3 of the AMC connector is pro vided Additionally an option to source CLK3 to the AMC connector is provided These options are controlled from a BCSR register refer to Table 7 9 The board has DDR2 SDRAM memory FLASH memory and NVRAM memory Table 1 1 DDR2 SDRAM is supported via an SODIMM socket The memory bus is 64 bit bus width refer to SDRAM Organization in this chapter for additional informa tion Ther
4. AdvancedMC EP8548A 1 2 DES0212 User Manual Developing Embedded Applications and Products Utilizing Freescale PowerQUICC IIl 85xx Processors P5010000086RA00 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Copyright Notice Trademarks P5010000086RA00 Preliminary Copyright 2007 Embedded Planet LLC All Rights Reserved This manual is copyrighted by Embedded Planet LLC No part of this document may be copied or reproduced in any form or by any means without the express written permission of Embedded Planet LLC Embedded Planet LLC reserves the right to modify the information contained herein as necessary Embedded Planet assumes no responsibility for any errors which may appear in this document Information in this document is provided solely to enable system and software implementers to use Embedded Planet products This manual in whole or in part is to be considered the intellectual property of Embedded Planet This document is intended for the sole purpose of the owner of an Embedded Planet product Neither the document nor reproductions of it nor information derived from it is to be given to others nor used for any other purpose other than for development of Embedded Planet computing engine applications by original authorized owners of Embedded Planet products Embedded Planet Linux Planet Blue Planet RPX LITE and RPX LICC are trademarks or registered trademarks of E
5. Memory Clock 1 GByte 2 GByte The DDR SDRAM clock speed is generated internal to the CPU and is equal to 1 2 the e500 core complex bus clock ccb_clk The maximum is 667 MHz data rate 333 33 MHz clock for the MPC8548E processor with a 33 33 MHz SYSCLK 128M x 64 200 Pin DDR2 SDRAM SODIMM Micron MT16HTF12864H or equivalent 2 bit bank address BAO BAT1 14 bit row address A0 A13 10 bit column address A0 A9 2 module rank address S0 51 256M x 64 200 Pin DDR2 SDRAM SODIMM Micron MT16HTS25664H or equivalent 3 bit bank address BAO0 BA2 14 bit row address A0 A13 10 bit column address A0 A9 2 module rank address S0 S1 FLASH Organization The FLASH memory on the EP board is accessed using the general purpose chip select machine GPCM of the processor Figure 2 4 shows the address and data line connections An offset is needed when issuing commands to the FLASH devices due to the address line connections Table 2 1 lists the FLASH memory devices and their device IDs that are currently supported on the board Refer to the Spansion datasheets for detailed information about the FLASH memory devices Command codes for all Spansion devices are the same Device ID varies among the different devices Sector addresses also vary among the different devices The following guidelines apply to x32 ported FLASH memory e FLASH devices configured in 16 bit mode e Sector and chip erases should be performed only on a long
6. Preliminary P5010000086RA00 Getting Started Chapter 3 This chapter describes how to get the EP board up and running in stand alone mode including initial configuration connection and powerup The board comes preprogrammed with u boot firmware An RS 232 serial monitor connection is required to access u boot utilities A network connection is required to transfer files to the EP board using TFTP To start up and begin communicating with the EP board NOTE The EP board does not require any special configuration to operate in stand alone mode 1 Establish a serial connection refer to Serial Monitor Connection in this chap ter 2 Establish a network connection if required refer to Network Connection in this chapter 3 Apply power refer to Power Up in this chapter Serial Monitor Connection A terminal emulator program on the host machine e g minicom Tera Term or HyperTerminal or a dumb terminal is required to interact with the EP board To establish a serial monitor connection with the host system 1 Connect the RJ 45 patch cable to the RJ 45 monitor port Fig 2 2 2 Connect the opposite end of the RJ 45 cable to the RJ 45 to DB 9 adapter 3 Connect the DB 9 adapter to a serial port on the host machine or dumb ter minal The default settings for the monitor port are 115200 baud 8 data bits 1 stop bit No parity No flow control Network Connection P5010000086RA00 Preliminary A network
7. COP Lodel 28 MMC Serial Port Pinout P etes rua e eri aoa aeons 29 MMC Debug Port Pin Ol esce 29 I2 VDC Don Header eatin 29 AMOC Connector 30 33 Ethernet Port J2 J3 LED P 34 DO aso seeks 35 BCSR1 CPLD Code 36 Dy de Fs ene 36 36 BCSR4 FLASH EEPROM LED Control and User Switch Status 37 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 List of Tables continued No 7 6 7 8 7 9 7 10 8 8 2 P5010000086RA00 Preliminary Title Page BCSR5 Monitor Ethernet Reset Control eese eene 37 peso Inte pu DEI dU EM IN 37 PCR IDIBEEHDEIVIAS gies arcsec 38 PCORS DERDES C 38 Ste ca sea nts th m etre dapian cosegiabentehoaca
8. GPCM Unused Unused Unused Unused Unused DDR SDRAM 0x00000000 64 bit DDR controller 0x40000000 64 bit DDR controller Unused Unused CCSRBAR Memory mapped processor registers External Interrupts P5010000086RA00 Preliminary All onboard external interrupts are active low signals Each IRQ line has a 10 Kohm pull up resister All used IRQ lines should be programmed for level sense Table 8 2 identifies the IRQ lines used by the EP board NOTE IRQ_OUT of the processor connects to the MMC Table 8 2 External Interrupts Interrupt Source Unused Unused SRTC STTM 2 February 2007 39 Chapter 8 Memory and Interrupts 40 Table 8 2 External Interrupts continued Interrupt Source Ethernet port 1 Ethernet port 2 Ethernet port 3 Ethernet port 4 Unused Unused Unused Unused 2 February 2007 AdvancedMC EP8548A 1 2 Preliminary P5010000086RA00 Mechanical Dimensions Appendix A P5010000086RA00 Preliminary This appendix contains mechanical dimension drawings for the EP8548A board The board is designed as a single width full height AMC module Figure A 1 shows the dimensions for the EP board NOTE The dimensions in this document are believed correct but if this unit is to be placed into a housing that has cut outs an actual unit
9. 2 Chapter 2 Description Table 2 2 I O Signals continued Interface Signal Ethernet EC_MDC EC_MDIO EC_GTX_CLK125 TSEC1_TXD 3 0 TSEC1_TX_EN TSEC1_GTX_CLK TSEC1_RXD 3 0 TSEC1_RX_DV TSEC1_RX_CLK TSEC2_TXD 3 0 TSEC2_TX_EN TSEC2_GTX_CLK TSEC2_RXD 3 0 TSEC2_RX_DV TSEC2_RX_CLK TSEC3_TXD 3 0 TSEC3_TX_EN TSEC3_GTX_CLK TSEC3_RXD 3 0 TSEC3_RX_DV TSEC3_RX_CLK TSEC4_TXD 3 0 TSECA TX TSECA GTX CLK TSECA RXD 3 0 TSECA RX DV TSECA CLK SD TX 4 7 SD TX 4 7 SD 4 7 SD 4 7 SD REF CLK SD REF CLK l2C Devices The evaluation board has several I2C bus devices STTM SEP SRTC SODIMM Table 2 3 describes the I2C address map P5010000086RA00 Preliminary 2 February 2007 19 Chapter 2 Description 20 AdvancedMC EP8548A 1 2 Table 2 3 12C Address Map Device Function I2C Addressing SDP 2K device 256 x 8 OxA1 0b1010000x Serial EEPROM 4K device 512 x 8 OxAC OxAF 0b1010110x 256 0b1010111x 256 Serial temperature and thermal monitor 0x90 0x91 0b1001000x Serial real time clock OxDO OxD1 0b1101000x Operating Modes Thermal Firmware The EP board can operate in two different modes e Stand alone mode e AdvancedMC mode Stand alone mode is primarily intended for development AMC mode provides the ability to use the same develo
10. connection between the development target i e EP board and host system is needed if planning to use TFIP services to transfer files to the EP board A TFIP server must be running on the host machine to use the network connec tion for file transfer Connect to the EP board in one of two ways directly or through a network hub or switch 2 February 2007 23 Chapter 3 Getting Started 24 Direct Hub or Switch Power Up AdvancedMC EP8548A 1 2 To directly connect to the host machine use a Ethernet crossover cable connected between the RJ 45 Ethernet port on the EP board Fig 2 2 and the Ethernet port on the host machine To connect to the host machine via a hub or switch use a standard Ethernet patch cable connected between the RJ 45 Ethernet port on the EP board Fig 2 2 anda free port on the hub NOTE Most new Ethernet cards hubs and switches have auto crossover capabilities which means the same cable may be able to be used for either direct hub or switch connection NOTE Start the terminal emulation program 6 0 minicom Tera Term or HyperTerminal or make sure the dumb terminal is connected before powering up the EP board When operating stand alone an external cooling fan is required Optionally a 12 VDC fan can be powered from the fan header P1 of the EP board refer to Table 5 6 The fan should be placed next to the board and in a position so as to maximize airflow over the processor After all c
11. highly integrated communications processors Our production proven modules help OEMs eliminate the risky and time intensive design and verification of the CPU module and focus on their value added application Embedded Planet products provide early access to production modules for all members of the engineering team to allow for a parallel development path Soft ware developers get access to turnkey platforms with the operating system of their choice ready to run out of the box Hardware developers gain access to pro duction designs and prototyping systems to test advanced system functionality Fully integrated software and hardware platforms simplify and shorten the devel opment cycle Embedded Planet products are ready to go to market today Our designs are pro duction proven and ready to be manufactured in quantity We offer full lifecycle management to simplify the deployment of your embedded solution Embedded Planet provides complete support for our product line Embedded Planet technical support includes product assistance for EP firmware and hard ware Technical support can assist with setup installation configuration docu mentation product related questions and expansion guidelines Second level software support for SDP s is handled through our partners We also provide development tools for all of our PowerPC boards Using our online support system our technical support engineers can assist you with questions regarding Embed
12. must be procured to verify all required connec tor cut outs In addition the vendor datasheets for the connectors should be referenced to determine the tolerances of the connectors 2 February 2007 41 Appendix A Mechanical Dimensions AdvancedMC EP8548A 1 2 09 80 5 T 169 Z g S 00 S 1610 pa i C Q N N _ Jm 2 E 9 al i Q i og 9 m EN es EE E EE EE 5 6 982 162 10 4 465 113 41 m S E Ha SOR al d eat me x S o o 9 Qo o ONCE END c e j sez o 5600 e p 688 8 0550 i E Sc 02 99 Z E o B 0462 5 v6g zZ D LL o o 000 909 90909 o o 000 0000 0 0 000004 42 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 P5010000086RA00 Preliminary 2 February 2007 43 Embedded Planet 4760 Richmond Road Suite 400 Warrensville Heights OH 44128 www embeddedplanet com Form P5010000086RA00 Preliminary Litho in U S A Feb2007 Copyright 2007 Embedded Planet LLC All Rights Reserved AdvancedMC EP8548A 1 2 Phone 216 245 4180 Fax 216 292 0561
13. ports available at the front panel J2 J3 Two additional 10 100 1000 Ethernet ports are available at the AMC connector The Ethernet ports communicate via eTSECT1 eTSEC2 eTSEC3 and eTSEC4 of the processor and use a Marvell 88E1145 quad transceiver device The interface to the processor is RGMII Port 3 of the transceiver device routes to AMC port 0 and port 4 of the transceiver device routes to AMC port 1 in the common options region of the AMC port map pings The interface to the AMC connector is SERDES using SGMII protocol An external PHY or SERDES device is required to complete the interface to the media The MII management connection MDC MDIO to the processor is for configura tion and monitoring of the transceiver device The default Ethernet PHY addresses are 0b00000 0500001 0b00010 and 0b00011 respectively Board control and status registers BCSR provide hardware control and status to the processor BCSR bits selectively enable disable and configure board features and control LEDs read switch settings and provide status indications The BCSR registers of the EP board are implemented in control logic within a complex pro 2 February 2007 15 Chapter 2 Description SEP SITM SRTC JTAG COP MMC AdvancedMC EP8548A 1 2 grammable logic device CPLD Refer to the Chapter x for BCSR programming information There is one serial EEPROM SEP on the local 126 port 1 bus refer to Table 2 3 for its I
14. word 32 bit basis e Programming should be done on a long word 32 bit basis if possible Processor I O Interface Signals P5010000086RA00 Preliminary Table 2 2 lists the processor I O interface signals used on the EP board 2 February 2007 17 Chapter 2 Description AdvancedMC EP8548A 1 2 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 ILA8 LA7 LAG LA5 LA4 3 3V LCSON U16 WP ACC LD31 DQO LD30 DQ1 LD29 DQ2 LD28 DQS LD27 DQ4 LD26 DQ5 LD25 DQ6 LD24 DQ7 LD23 DQ8 LD22 DQ9 LD21 DQ13 LD17 DQ15 A 1 RY BY st A24 A25 BY TE CE OE WE RESET U17 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 ILA8 LA7 LAG LA5 LA4 A24 A25 3 3V BY TE LCSON CE OE WE RESET WP ACC DQO DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A 1 RY BY st T00327A Figure 2 4 FLASH Address and Data Lines Table 2 1 FLASH Devices Device S29GL128 S29GL256 S29GL512 MFGID Device ID 0x2101 0x2201 0x2301 Table 2 2 I O Signals Interface Serial UART SOUTO UART SINO UART CTSO UART_RTSO 20 SDA IIC1 SCL 18 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1
15. 0000086RA00 Preliminary Function FLASH write protect Definition FLASH write protect disabled 1 FLASH write protect enabled EEPROM write protect 0 EEPROM write protect disabled 1 EEPROM write protect enabled User LEDO User LED1 O LED off 1 LED on User switch Function Monitor port BCSR4 4 is position 1 on switch Switch closed logic 0 on Switch open logic 1 off Definition O disable monitor transceiver 1 enable monitor transceiver Reserved Ethernet PHY 0 enable Ethernet PHY 1 disable Ethernet PHY reset Software reset 1 enable HRESET Reserved Function Interrupt R W Definition 0 Ethernet 0 IRQ active 1 Ethernet 0 IRQ inactive 0 Ethernet 1 IRQ active 1 Ethernet 1 IRQ inactive 0 Ethernet 2 IRQ active 1 Ethernet 2 IRQ inactive 0 Ethernet 3 IRQ active 1 Ethernet 3 IRQ inactive 0 SRTC IRQ active 1 SRTC IRQ inactive 0 STTM IRQ active 1 STTM IRQ inactive Reserved 2 February 2007 37 Chapter 7 Board Control and Status Registers Table 7 8 BCSR7 Interrupt Masking Byte Address BASE ADDRESS Ox7 reset value 1111 1100 Function Interrupt Definition 0 Ethernet 0 IRQ unmasked 1 Ethernet 0 IRQ masked AdvancedMC EP8548A 1 2 0 Ethernet 1 IRQ unmasked 1 Ethernet 1 IRQ
16. 2C address This SEP device is available for user application storage The SEP is a 2 wire AT24C04 device or equivalent There is one serial temperature and thermal monitor STI M device on the local I2C port 1 bus refer to Table 2 3 for its I2C address The STTM part is a 2 wire digital temperature sensor Its functionality is equivalent to the Microchip TCN75 part The minimum resolution provided by this part is a 9 bit temperature conver sion There is one serial real time clock SRTC device on the local I2C port1 bus refer to Table 2 3 for its I2C address It provides clock and calendar functions for the board Counters for tenths hundredths of seconds seconds minutes hours day date month year and century are provided Its functionality is equivalent to the STMicrodevices M41T81 part An onboard battery provides backup power for the SRIC device The P12 header provides access to the COP port of the processor for debug access Additionally P12 can be configured with jumper settings to give access to the CPLD JTAG Refer to JTAG COP Configuration in Chapter 4 The module management controller MMC funtionality required for AMC 0 compliance is implemented in an MCF5213 Coldfire processor The MMC com municates with the ATCA carrier or microTCA carrier hub over the IPMB L bus using I2C protocol The carrier and MMC communicate through a limited set of IPMI commands Two serial temperature sensors and a serial EEPROM implement th
17. Addresses The EP board has four media access control MAC address assigned to it The MAC address is the physical address of a device connected to a network 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 P5010000086RA00 Preliminary Chapter 2 Description expressed as a 48 bit hexadecimal number The EP boards are assigned MAC addresses during manufacture using the following convention Enet controller 1 MAC 0x0010ECxxxxxx ORed with 0x000000000000 Enet controller 2 MAC 0x0010ECxxxxxx ORed with 0x000000800000 Enet controller 3 MAC 0x0010ECxxxxxx ORed with 0x000000400000 Enet controller 4 MAC 0x0010ECxxxxxx ORed with 0x000000C 00000 where XXXXXX EP board serial number The serial number can be found in decimal form on a label affixed to the Ethernet port on the board e g 007573 For example a board with a serial number of 007573 decimal 001D95 hexadeci mal has a MAC address of 00 10 EC 00 1D 95 for Enet controller 1 00 10 EC 80 1D 95 for Enet controller 2 If it becomes necessary to restore a missing or corrupted MAC address use the above procedure to determine the EP board s MAC addresses and issue the fol lowing commands in u boot setenv ethaddr MAC ADDRESS 1 ENTER setenv ethtaddr MAC ADDRESS2 gt ENTER setenv eth2addr MAC ADDRESS3 gt ENTER setenv eth3addr MAC ADDRESS4 gt ENTER saveenv ENTER 2 February 2007 21 22 2 February 2007 AdvancedMC EP8548A 1 2
18. Board LEDs Definition On CR9 AMC hot swap indicator Blue CR10 AMCLED1 Red CHR8 AMC LED2 Green CR11 AMC LEDS3 Amber CR22 12 VDC power OK Green CR20 3 3V power OK Green CR21 2 5V PHY power OK Green CR19 1 8V DDR power OK Green CR18 1 1 e500 power OK Green CH12 User LEDO Green CR13 User LED1 Green CH14 Ethernet port 2 RXD Green CR15 Ethernet port 2 TXD Green CH16 Ethernet port 3 RXD Green CH17 Ethernet port 3 TXD Green NOTE AMC LEDs are under MMC control Ethernet Port LEDs Table 6 2 describes the indications given by the Ethernet port LEDs J2 J3 Refer to Figure 2 2 for the location of the Ethernet port P5010000086RA00 Preliminary 2 February 2007 33 Chapter 6 Operation AdvancedMC EP8548A 1 2 Table 6 2 Ethernet Port J2 J3 LEDs Indication LED1 Yellow LED2 Green Amber No RXD TXD activity 10 Mbps RXD TXD activity 100 Mbps amber 1000 Mbps green User Applications The u boot firmware assumes the board is connected to a dumb terminal or a PC based terminal emulator and requires user intervention for the utilities The dumb terminal or PC serial port should be set as follows 115200 baud default e 8 data bits e 1 stop bit e No parity e No hardware handshake Proper interfacing to the serial port via the correct RS 232 connections must be insured as described in RS 232 Connection in this chapter R
19. ENTER Press Esc V M press and release each key in sequence Press CTRL ALT DEL press all keys in sequence simultaneously File Names Name Indicates a file or directory name Example file h bxn Reference Documents e MPC8548E PowerQUICC III Integrated Host Processor Reference Manual e AMC 0 R2 0 Advanced Mezzanine Card Base Specification e AMCA Rx x Advanced Mezzanine Card Serial RapidIO 12 2 February 2007 Preliminary P5010000086RA00 Description Chapter 2 This chapter provides some description of the EP8548A board features including the PowerPC processor external interfaces and u boot firmware Figure 2 1 is a simplified block diagram of the EP board Figures 2 2 and 2 3 show the top and bottom views of the board layout These figures show the headers unpopulated i e without pins or connectors CPLD mH SWITCH JTAG COP P12 16 67 MHZ FLASH NVRAM 25 MHZ 33 33 MHZ LOCAL BUS DDR BUS SEP i i 1 1 SRTC 32 768 KHZ MPC8548E 201 SWITCH SW1 x e e o H E ne lt 0 5 Lu E o UAD Cr CFG nses a m A O 5 Q SWA4 Q 3 am x en Lu o x SERIAL X 10 100 1000 AMC JTAG SERIAL P11 ETHERNET CONNECTOR BDM J7 J2 J3 P15 P13 T00328A Figure 2 1 Simplified Block Diagram MPC8548E Clocks P5010000086RA00 Preliminary Refer to PowerPC Processor in this chapter All of the clocks used on t
20. S 232 Connection A DB 9 or DB 25 to RJ 45 connection is required for RS 232 communication Table 5 1 provides the pinouts for the RJ 45 connector The EP board has its serial ports wired as DTE A null modem type of connection is required when interfac ing to a DTE port For DTE DB9 3 TXD DB25 2 TXD DB9 2 RXD DB25 3 RXD DB9 8 CTS DB25 5 CTS DB9 7 RTS DB25 4 RTS DB9 5 GND DB25 7 GND 34 2 February 2007 Preliminary P5010000086RA00 Board Control and Status Registers Chapter 7 The EP8548A board has onboard control and status registers These registers are configured as x8 registers Bit 0 is the most significant bit MSB The registers are defined as shown in Tables 7 1 through 7 10 NOTES 1 Any unused or reserved BCSR bits should always write back the value read This will help guarantee that revisions to the board will be backward compatible with existing software 2 The base address of the BCSR is determined by the firmware or application refer to Table 8 1 Register values at reset values in binary Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Table 7 1 BCSRO Board ID Byte Address Function BASE Board ID CPLD code revision FLASH status Reserved FLASH EEPROM LED control and user switch status Monitor Ethernet reset control Interrupt status Interrupt masking SERDES control MMC debug status Definit
21. The 10 100 1000 Ethernet ports are connectors J2 and J3 The connectors are shielded RJ 45 jacks Table 5 2 shows the RJ 45 jack pinout Table 5 2 Ethernet Port Pinout J2 J3 Function i Function NOTE 1 Pin numbering is from right 1 to left 8 when looking into the RJ 45 jack with the locking tab on top JTAG COP Port The JTAG COP port is P12 It is a 2 x 8 0 1 x 0 1 header Table 5 3 shows the COP header pinout Table 5 3 COP Port Pinout P12 Function i Function TDO GND TDI TRST 3 3V 3 3V TCK CHKSTOP_IN TMS SRESET HRESET CHKSTOP_OUT 28 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Chapter 5 Connectors and Headers MMC Serial Port The MMC serial port is connector J7 It is a 1 x 3 0 1 x 0 1 header Table 5 4 shows the pinout Table 5 4 MMC Serial Port Pinout J7 MMC Debug Port The MMC debug port is P13 It is a 2 x 8 0 1 x 0 1 header Table 5 5 shows the utility header pinout Table 5 5 MMC Debug Port Pinout P13 Function i Function TMS GND 4 TRST GND 6 TCK RST IN 8 TDI IPMCV TDO GND ALLPST ALLPST ALLPST ALLPST 12 VDC Fan Header The 12 VDC fan header is connector P1 Itisa 1 x2 0 1 x 0 1 header Table 5 4 shows the pinout Table 5 6 12 VDC Fan Header Pinout P1 AMC Connector Table 5 7 lists the pin assignments for th
22. ded Planet products Via a browser our support team can access your system directly and quickly answer your technical ques tions Please contact us today to learn more refer to Contact Embedded Planet in this chapter Contact Embedded Planet Company E mail Directory P5010000086RA00 Preliminary Embedded Planet 4760 Richmond Road Suite 400 Warrensville Heights OH 44128 Phone 216 245 4180 Fax 216 292 0561 www embeddedplanet com Marketing marketing embeddedplanet com Sales sales embeddedplanet com Information Request info embeddedplanet com Technical Support techsupport embeddedplanet com Webmaster webmaster embeddedplanet com 2 February 2007 11 Chapter 1 Introduction AdvancedMC EP8548A 1 2 Document Conventions This document uses standard text conventions to represent keys display items and user data inputs Display Item Italic Identifies an item that displays on the screen such as a menu option or mes sage e g File gt Open User Data Input Bold Identifies any part of a command or user entry that is not optional or vari able and must be entered exactly as shown Italic Identifies any part of a command or user entry that is a variable parameter Identifies any part of a command or user entry that is an optional parameter text within the brackets follows the previously described conventions KEY Identifies a specific key that is not alphabetic numeric or punctuation Press
23. e AMC connector P15 The AMC con nector signal assignments follow the AMC standard P5010000086RA00 Preliminary 2 February 2007 29 Chapter 5 Connectors and Headers 30 Table 5 7 AMC Connector P15 GND 12V PS1 3 3V IPMCV GAO OINI OO aA c ENABLE 2 February 2007 AdvancedMC EP8548A 1 2 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 P5010000086RA00 Preliminary Table 5 7 AMC Connector P15 continued 2 February 2007 Chapter 5 Connectors and Headers 31 Chapter 5 Connectors and Headers 32 Table 5 7 AMC Connector P15 continued 2 February 2007 AdvancedMC EP8548A 1 2 Preliminary P5010000086RA00 Operation Chapter 6 This chapter describes the reset switch and board LED indications for the EP8548A board It also provides some firmware description and communication information system Reset Pushbutton The system reset pushbutton 5W2 can be used to reset the board This pushbut ton activates a hard reset HRESET to the board Refer to Figure 2 2 for the loca tion of the pushbutton Board LEDs Table 6 1 describes the indications for the EP board LEDs Table 6 1
24. e is no ECC option Access to the SPD functions of the SODIMM module is from I2C port 1 of the processor refer to Table 2 3 for its I2C address 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Chapter 2 Description O Bp E un P14 o W 99 o T00331A Figure 2 3 EP Board Bottom View RS 232 Ethernet BCSR P5010000086RA00 Preliminary The FLASH memory is Spansion MirrorBit The memory bus is 32 bit bus width refer to FLASH Organization in this chapter for additional information The NVRAM memory is battery backed SRAM memory The memory device is an STMicro M68AWxxxD or equivalent The memory bus is 16 bit bus width An onboard battery provides backup power for the NVRAM device NOTE The local bus address and data lines are multiplexed An external demultiplexer con trolled by the address latch enable LALE signal is used to separate the address and data bus The local bus is buffered using a data latch for the address lines SN74LVC32373A or equivalent and a bus transceiver for the data lines SN74LVCH322454 or equivalent There is one RS 232 serial port available at the front panel P11 The port commu nicates via UARTO of the processor The serial port uses an Intersil ICL3225E RS 232 transceiver or equivalent There are two 10 100 1000 Ethernet
25. e serial FLASH programming mode 1 disable serial FLASH programming mode JTAG EN selects between debug and JTAG mode 0 debug mode 1 JTAG mode CLKMOD 1 0 determines the clock mode 00 PLL disabled 10 PLL in normal mode NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MCF5213 Reference Manual for additional information P5010000086RA00 Preliminary 2 February 2007 25 Chapter 4 Setup AdvancedMC EP8548A 1 2 JTAG COP Configuration Jumper J6 configures the JTAG chain and COP mode Table 4 3 describes the con figuration options Refer to Figure 2 2 for the location of the switch Table 4 3 JTAG COP Configuration J6 Purpose Setting Function COP P12 operates in COP mode to support hardware and software development and debugging JTAG CPLD only JTAG chain active at P12 This setting puts only the CPLD in the JTAG chain to support programming JTAG complete JTAG chain active at P12 This setting completes the JTAG chain at P12 and includes AMC gt CPU gt CPLD gt MMC gt ETH_PHY gt AMC 26 2 February 2007 Preliminary P5010000086RA00 Connectors and Headers Chapter 5 The EP8548A board has the following connectors for I O functions and expand ability e One connector for power used for stand alone only e One RJ 45 connector for processor RS 232 monitor port Two RJ 45 connectors for the 10 100 1000 Ethernet ports e
26. e temperature sensor and FRU information storage device requirements for AMC 0 compliance These devices are accessed via the SPI bus of the Coldfire processor Additionally access to the RS 232 serial port and JTAG BDM port of the Coldfire processor are provided for development purposes Refer to Chapter 5 for more information and pinouts for the connectors PowerPC Processor The EP board incorporates an MPC8548E PowerQUICC III integrated host pro cessor This 32 bit processor includes an integrated PowerPC core and peripheral interfaces that can be used in a variety of embedded networking telecom trans mission and switching 3G wireless infrastructure storage and high end imaging applications The MPC8548E processor incorporates e e500 core scaling up to 1 33 GHz e DDR memory controller operating at up to 667 MHz data rate e Local bus controller operating at up to 166 MHz OCeaN switch fabric e Dual UART DUART e Dual I2C interfaces master or slave mode e Serial RapidIO interface unit e PCI Express interface unit not accessible on EP board e Four enhanced three speed Ethernet controllers eTSEC 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Chapter 2 Description e Two PCI PCI X controllers not accessible on EP board e Programmable interrupt controller PIC e Four channel DMA controller e System performance monitor e Integrated security engine SDRAM Organization
27. he EP board are generated locally There are a few dis tinct clocking environments on the board e System clock and real time clock e Ethernet clock SERDES clock An onboard 33 33 MHz clock oscillator ECS 3953C or equivalent generates the system clock SYSCLK input to the MPC8548E processor This is the primary 2 February 2007 13 Chapter 2 Description AdvancedMC EP8548A 1 2 MMC AMC JTAG BDM POWER CONNECTOR MONITOR O fj O z nN E e o g P Z 2 BTI ai p cm T J7 os A 5 P12 J3 J1 P15 d i 5 10 100 1000 0 ETHERNET B EL E 9 o c J2 eso ET E O UU E a 0 5 _1sw2 JTAG DDR2 MMC 12V FAN COP SODIMM SERIAL T00330A Figure 2 2 EP Board Top View Memory clock input to the device A zero delay buffer CY2304 or equivalent is used to distribute the 33 33 MHz clock to the processor and to also divide this clock input to provide a 16 67 MHz real time clock RTC input to the processor The 16 67 MHz clock input can be used to clock the time base of the processor and to clock the global timers in the programmable interrupt controller PIC of the pro cessor
28. i sand 38 DVS VOT SINEAD M 39 FE CTE 39 2 February 2007 7 AdvancedMC EP8548A 1 2 2 February 2007 Preliminary P5010000086RA00 Introduction Functions P5010000086RA00 Preliminary Chapter 1 The EP8548A board is a single width full height advanced mezzanine card AMC based on the Freescale MPC8548E PowerQUICC III processor The EP8548A board can operate as an AdvancedMC module within an AdvancedTCA system when plugged into an ATCA carrier or MicroTCA chassis The board can also operate as a stand alone module for rapid application development outside of the integrated ATCA or MicroTCA environment The functions included on the EP board are listed in Table 1 1 Table 1 1 Hardware Features Entity Form factor Description Single width full height compliant Processor MPC8548A up to 1 33 GHz SDRAM Up to 2 GBytes x64 DDR2 SODIMM FLASH Up to 128 MBytes x32 NVRAM Up to 1 MBytes x16 Ethernet 2 10 100 1000 front panel RJ 45 2 10 100 1000 AMC connector port 0 and port 1 Serial port 2 wire RS 232 front panel RJ 45 Serial RIO AMC 4 compliant x1 x4 data AMC connector port 4 5 6 7 1 25 2 5 or 3 125 Gbaud 8b 10b encoding serial EEPROM Serial temperature Serial real time clock battery backed l2C BCSR Board con
29. ion ID 0x4 EP8548 1 2 ADDRESS OxO reset value ID o Dn O P5010000086RA00 Preliminary 2 February 2007 35 Chapter 7 Board Control and Status Registers Table 7 2 BCSR1 CPLD Code Revision Byte Address BASE ADDRESS Ox1 reset value REV Function CPLD revision Table 7 3 BCSR2 FLASH Status Byte Address BASE ADDRESS 2 reset value 0000 0x00 Function Heserved Jioc ny 0O Definition REV revision of CPLD code Definition AdvancedMC EP8548A 1 2 FLASH ready busy FLASH operation executing and busy 1 FLASH operation complete ready Reserved Table 7 4 BCSR3 Reserved Byte Address BASE ADDRESS 0x3 reset value 0000 0000 36 Function Reserved Jo 2 February 2007 Definition Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Chapter 7 Board Control and Status Registers Table 7 5 BCSR4 FLASH EEPROM LED Control and User Switch Status Byte Address BASE ADDRESS 0x4 reset value 0000 uuuu Table 7 6 BCSR5 Monitor Ethernet Reset Control Byte Address BASE ADDRESS 0x5 reset value 1000 0000 Table 7 7 BCSR6 Interrupt Status Byte Address BASE ADDRESS 0x6 reset value P501
30. l 1 Refer to Chapter 2 for a description of the board features and functions 2 Refer to Chapter 3 for quick start information connection configuration and powerup 3 Refer to Chapter 4 for setup information including switch and jumper settings 4 Refer to Chapter 5 for a description of the connectors and headers available on the board 5 Refer to Chapter 6 for information about the operation of the EP board 6 Refer to Chapter 8 for memory map and interrupt information About Embedded Planet Embedded Planet is a leading single board computer and embedded systems solution provider Our capabilities range from standard off the shelf single board computer products and embedded operating systems to full custom design and intellectual property solutions In 1997 Embedded Planet pioneered the Design Develop Deploy process for embedded systems engineering This process allows our customers to take advan 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Design Develop Deploy Customer Support Chapter 1 Introduction tage of production tested reusable product designs in all phases of system devel opment to reduce time to market project risk and development costs Embedded Planet products help remove risk and shorten the design cycle through production tested integrated hardware and software designs CPU mod ule design is becoming more complicated with advanced memory interfaces and
31. masked 0 Ethernet 2 IRQ unmasked 1 Ethernet 2 IRQ masked 0 Ethernet 3 IRQ unmasked 1 Ethernet 3 IRQ masked 0 SRTC IRQ unmasked 1 SRTC IRQ masked 0 STTM IRQ unmasked 1 STTM IRQ masked Reserved Table 7 9 BCSR8 SERDES Control Byte Address BASE ADDRESS 0x8 reset value 1100 0000 Function Definition SERDES clock O0 R W 0 AMC connector select 1 onboard AMC CLK3 1 RAW O onboard SERDES clock enabled at AMC CLK3 1 onboard SERDES clock disabled at AMC CLK3 NOTE BCSR8 0 1 is required to enable AMC CLK3 Reserved 2 RW 3 R W 4 R W 5 R W 6 RO 7 RO Table 7 10 BCSR9 MMC Debug Status Byte Address BASE ADDRESS 0x9 reset value x000 000 38 Function ALLPST Status of ALLPST at P13 Definition Reserved o O 2 February 2007 Preliminary P5010000086RA00 Memory and Interrupts Chapter 8 This chapter contains memory map and interrupt information for the EP8548A board Memory Map Table 8 1 Memory Map Chip Select Table 8 1 describes the default memory map for the EP board NOTE The address map is recommended for the EP board and is as defined in u boot Other mappings can be utilized for any given application Function Address Size Description OxF8000000 32 bit GPCM Ox 16 bit GPCM Ox 8 bit
32. mbedded Planet Freescale PowerQUICC and QUICC Engine are trademarks of Freescale Semiconductor Inc IBM and PowerPC are registered trademarks of International Business Machines Inc AdvanceTCA and ATCA are registered trademarks of PCI Industrial Computer Manufacturers Group PICMG AdvancedMC and MicroTCA are trademarks of PICMG Wind River Systems VxWorks and Tornado are registered trademarks of Wind River Systems Inc All other names and trademarks are the property of their respective owners and are hereby acknowledged 2 February 2007 3 AdvancedMC EP8548A 1 2 2 February 2007 Preliminary P5010000086RA00 AdvancedMC EP8548A 1 2 Contents Chapter 1 INtroduUC hoN ERROR T 9 0 CG e area 10 16 86 1 15 8 18 10 1 6 10 Gi ice eat SUP DOBL 11 Contact Embedded Planet 499B leere eene tene
33. n nnn 11 Document ConvenlionS osese qat deae bre oon aoi ge cube sa ta 12 Reference Documents e BEER 12 Chapter 2 Description aissxxcxaixxknixix us 13 PowerPC Processor oec tetto allia 1 16 SDRAM OreaniZalioll utn E RN 17 PLA gem 17 Processor I O Interface Signals 17 I RT cuo es a sss etc ee ste sen teeee ee 19 20 erac RT s Sie 20 ET 20 Restoring MAC Addresses paneer 20 Chapter 3 Getting Started ee esee eee eeu rue 23 Serial Monitor 23 Network Connectiogy ein c sssssscscsccccccccccscsssvevssscecscccceecssencvsnsssceccseecececsvsssvscecsecsssensnenenss 23 24 Chapter 25 ILO on Mi A 25 MMC COTS UT A QV o 25 MONE CES Ser uu cr 26 Chapter 5 Connectors and Headers
34. onnections have been properly made connect the 12 VDC power sup ply to the barrel connector P5 Fig 2 2 The EP board will boot up into u boot automatically Refer to online u boot documentation for complete information about u boot and its utilities 2 February 2007 Preliminary P5010000086RA00 setup Chapter 4 This chapter describes the various configuration switches that setup the EP8548A board for operation SRIO Configuration Switches SW1 configure SRIO options Table 4 1 describes the configuration options Refer to Figure 2 3 for the location of the switch Table 4 1 SERDES Port Configuration SW1 1 3 Option 1234 Description x4 SRIO 2 5 Gbaud interface 100 MHz reference clock x4 SRIO 3 125 Gbaud interface 125 MHz reference clock x4 SRIO 1 25 Gbaud interface 100 MHz reference clock Large system size up to 65 536 devices Small system size up to 256 devices NOTES 1 on closed position logic 0 off open position logic 1 2 Refer to the MPC8548E Reference Manual for additional information MMC Configuration Switch SW4 configures the MMC processor options Table 4 2 describes the con figuration options Refer to Figure 2 3 for the location of the switch NOTE This switch is primarily for development purposes It is factory set and should not be changed Table 4 2 MMC Configuration SW4 1 4 Position Description RCON selects serial FLASH programming mode 0 enabl
35. pendix A Mechanical Dimensions ene nhan anna nnn 41 List of Figures No 2 2 2 3 2 4 A 1 List of Tables No 1 1 2 2 2 3 4 2 4 3 5 2 5 3 5 4 5 5 5 7 6 1 7 1 7 2 7 4 7 5 Title Page Simplified Block Diagram 13 EP Board Top View W 5998 14 EP Board Bottom View Wlli eese nennen nnn 15 FLASH Address and Data Lines eee nennen nenne 18 Mechanical Dimensions eren nn nennen enne nnn nnn ones 42 Title Page Hardware MIS OW os rer tpe naues AaS EEE p tU EF MR eva a oU OEE 9 FLASH IDE 18 A a ER A 18 IG lie oo 20 SERDES Port Configuration SW1 1 3 eere tnnt nnn 25 MB onti miration SWA T 4 esee eerte erneuern nnn nnne 25 WAGH OP Configuration J6 ST 26 11 28 Etta ort Pinout J2 3 28
36. pment board in a carrier card or chassis environ ment There are no configuration options to select to switch between stand alone and AMC modes The only real difference is where power is applied Refer to Power in Chapter 5 The MPC8548E processor is fitted with a heat sink The choice of size and type of heat sink is dependant on the environment in which the board is operating Fac tors such as processor speed ambient temperature and air flow all dictate the specific characteristics of the heat sink required Additionally the choice of heat sink is dependant on the space available which is ultimately determined by the mechanical constraints of the system in which the EP board will operate The heat sink used when the card is situated in a chassis environment with forced air flow will differ from that used when the card operates stand alone Refer to the MPCS 548E Reference Manual for the processor thermal characteristics U boot is open source firmware for the embedded PowerPC architecture It can be installed in a boot ROM and used to initialize and test hardware or to download and run application code The EP8548A board is shipped with the u boot firmware residing in FLASH memory U boot loads at the address OxFFF00000 U boot utilities provide the ability to initialize the board and auto execute an operating system or application Refer to online u boot documentation for complete information about u boot and its utilities Restoring MAC
37. trol and status registers CPLD LED Power status 2 user controlled LEDs Ethernet PHY controlled MMC controlled 4 position user switch Processor configuration MMC configuration 2 February 2007 JTAG COP port access for software debug and programming Chapter 1 Introduction First Steps Reminder AdvancedMC EP8548A 1 2 Table 1 1 Hardware Features continued Entity Description Power requirements 12 VDC 3A maximum from barrel connector stand alone or via AMC backplane connector 3 3 VDC 100 mA maximum via AMC backplane connector Operating temperature 0 C to 70 C 32 C to 158 F NOTES 1 Contact Embedded Planet for information about an industrial temperature version board 2 The means of disconnection from the mains power supply is the plug 3 No serviceable parts While it may be tempting to jump right into application development it is recom mended that you take a few minutes to review the Getting Started material pay ing special attention to the following recommended first steps 1 Register your EP board go to Support at www embeddedplanet com 2 Complete the steps in Chapter 3 when ready to connect and powerup the EP board for development You must register your EP board to become eligible for customer assistance or more detailed technical support from Embedded Planet Refer to Customer Sup port in this chapter How to Use This Manua
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