Intro to ARM Cortex-M3 processor and LPC1768 microcontroller
Contents
1. code listing Then three 16 bit instructions load Idr the value of counter increment adds the value and write back str the updated value Finally the procedure returns the original counter Key points Cortex M3 utilizes a mixture of 32 bit and 16 bit instructions mostly the latter and the core interacts with memory solely through load and store instructions While there are instructions that load store groups of registers in multiple cycles there are no instructions that directly operate on memory locations How does an assembly language program get turned into a executable program image Binary program file bin Assembly Object ape le A files files 0 image file L A er gt J S Memory layout Disassembled Linker code lst script ld 14 Outline Overview of ARM Cortex M3 processor Main features pipeline memory space Assembly NXP LPC17xx microcontroller unit MCU APPENDIX A Instruction Set Architecture ISA APPENDIX B ARM Instruction Set Cortex M3 processor vs CM3 based Microcontroller Units Developed by ff ARM Developed by chip manufacturers 15 While there is significant overlap between the families and their peripherals there are also important differences In the lab of this course we focus on the NXP s LPC17xx family Actel a AIMEL POWER MATTERS A SEDUST NETWORKS LPC17xx LPC17xx of NXP is an ARM Co2. control PWM Lares ox400B 4000 13 reserved USB controller 0x5000 C000 oni en a GPOMAconboler asgan 4000 Ethernet controller 70x4400 0000 O Ethernet controller 0x5000 0000 penpheral bit band alias addressing 0x4200 0000 reserved 5 0x4010 0000 APBI peripherals 04008 0000 0x4008 0000 APBO peripherals a 0x4006 0000 reserved Z t J eet ox4a0s cooo 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 40x200A 0000 GPIO Ox2008 C000 rese A rese A 2 4 3x2008 4000 rved 2 i rved P P A 4 aa 7 ax1FFF 2000 8 kB boot ROM cea Z reserved 3x1000 8000 32 kB local static RAM Leode D code anal 0x1000 0000 memory space reserved lt lt a 0x0000 0400 256 words 0x4001 4000 ox0000 000 active interrupt ve t 512 kB on chip flash 0x4001 0000 512 kB on chip 0x0000 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 References amp Credits Joseph Jiu The Definitive guide to the ARM Cortex M3 2007 LPC17xx microcontroller USER MANUAL Cortex M3 Processor TECHNICAL REFERENCE MANUAL Lab manual G Brown Indiana EECS 373 UMich See website of class for links to download any of the above http dejazzer com coen4720 index html Outline Overview of ARM Cortex M3 processor Main features pipeline memory space Assembly NXP LPC17xx microcontroller unit MCU APPENDIX A Instruction Set Architecture ISA APPENDIX B ARM
3. lt Rmb gt 15 14 13 12 11 10 9 8 7 654 32 1 0 1514153121 109876543210 d ean m UInt Rm setflags 5 1 if se 5 A d IN 13 15 m IN 13 15 then UNPREDICTABLE Y then UNPREDICTABLE 12 Ab 7 78 MOVT Move Top writes an immediate value to the top halfword of the destination register It does not affect the contents of the bottom halfword_ Encoding T1 ARMy M HONTec gt lt Rd gt lt inm16 gt 14130211109 7 654352321022853HMiI D119 amp 7 6 5 43 2 ee opeope mm fejes e O m d LH imm imm4 i iimis i 4 15 then UNPREDICTABLE Assembler syntax MOWT lt co lt g gt lt Rd gt lt immlb gt where lt C gt lt l gt See Standard assembler syntax fields on page A6 7 lt Rd gt Specifies the destination register simli Specifies the immediate value to be written to lt Rd gt It must be in the range 0 655535 Operation if ConditionPassed then EncodingSpeci fi cOperations R d lt 31 16 gt immi6 f f Bodj lt 15 8 gt unchanged Example 2 int counter int Counter Inc void return counter Resulting annotated assembly language with corresponding machine code Counter Inc 240 0300 lower16 counter amp counter 2c0 0300 upper16 counter 6818 r3 0 ro r3 1c42 ro 1 r2 r0 1 60la r3 0 r3 4740 return r0 Two 32 bit instructions movw movt are used to load the lower upper halves of the address of counter known at link time and hence 0 in the
4. 1 if the instruction results in an overflow condition for example a signed overflow on an addition Q bit 27 Set to 1 if an SSAT or USAT instruction changes saturates the input value for the signed or unsigned range of the result Conditional Execution Each data processing instruction prefixed by condition code Result smooth flow of instructions through pipeline 16 condition codes eT ea o esa S fo weston kal gp unsigned lower signed less or same than or equal unsigned nee signed greater higher or same i than or equal not equal PL positive or zero LS 28 Conditional Execution Every ARM 32 bit instruction is conditionally executed The top four bits are ANDed with the CPSR condition codes If they do not matched the instruction is executed as NOP The AL condition is used to execute the instruction irrespective of the value of the condition code flags By default data processing instructions do not affect the condition code flags but the flags can be optionally set by using S Ex SUBS ri r1 1 Conditional Execution improves code density and performance by reducing the number of forward branch instructions Normal Conditional CMP r3 0 CMP r3 0 BEQ skip ADDNE r0 r1 r2 ADD r ri r2 skip Conditional Execution and Flags ARM instructions can be made to execute conditionally by post fixing them with the appropriate condition code This can increase code density and i
5. 5 Rb Rd Load store halfword SP relative load store Load address Add offset to stack pointer Push pop registers Multiple load store Conditional branch Software Interrupt Unconditional branch 2 e ooren 15 14 13 12 n 10 9 8 f 66 5 4 3 2 1 0 See 6 THUMB _Instr_Set_pt3 pdf included in lab2_files zip Application Program Status Register APSR 31 30 29 28 27 26 0 sleep em APSR bit fields are in the following two categories Reserved bits are allocated to system features or are available for future expansion Further information on currently allocated reserved bits is available in The special purpose program status registers xPSR on page B1 8 Application level software must ignore values read from reserved bits and preserve their value on a write The bits are defined as UNK SBZP Flags that can be set by many instructions N bit 31 Negative condition code flag Set to bit 31 of the result of the instruction If the result is regarded as a two s complement signed integer then N 1 if the result is negative and N 0 if it is positive or zero Z bit 30 Zero condition code flag Set to 1 if the result of the instruction is zero and to 0 otherwise A result of zero often indicates an equal result from a comparison C bit 29 Carry condition code flag Set to 1 if the instruction results in a carry condition for example an unsigned overflow on an addition V bit 28 Overflow condition code flag Set to
6. COEN 4720 Embedded Systems Design Lecture 3 Intro to ARM Cortex M3 CM3 and LPC17xx MCU Cristinel Ababei Dept of Electrical and Computer Engineering Marquette University Outline Overview of ARM Cortex M3 processor Main features pipeline memory space Assembly NXP LPC17xx microcontroller unit MCU APPENDIX A Instruction Set Architecture ISA APPENDIX B ARM Instruction Set Cortex M3 Processor RISC general purpose 32 bit microprocessor Released in 2006 Cortex M3 differs from previous generations of ARM processors by defining a number of key peripherals as part of the core interrupt controller system timer debug and trace hardware including external interfaces This enables for real time operating systems and hardware development tools such as debugger interfaces be common across the family of processors Various Cortex M3 based microcontroller families differ significantly in terms of hardware peripherals and memory Cortex M3 Processor Greater performance efficiency more work to be done without increasing the frequency or power requirements Implements the new Thumb 2 instruction set architecture e 70 more efficient per MHz than an ARM7TDMI S processor executing Thumb instructions e 35 more efficient than the ARM7TDMI S processor executing ARM instructions for Dhrystone benchmark Low power consumption longer battery life especially critical in portable products including wirele
7. Instruction Set 22 APPENDIX A Instruction Set Architecture ISA e Instruction set Addressing modes Word size Data formats Operating modes Condition codes Thumb 2 Instruction Set Thumb 2 instruction set is a superset of the previous 16 bit Thumb instruction set Provides A large set of 16 bit instructions enabling 2 instructions per memory fetch Asmall set of 32 bit instructions to support more complex operations Specific details of this ISA not our focus we ll mostly program in C Thumb 2 Instruction Set 32 bit and 16 bit Cortex M3 Thumb N Instructions 3 So aeb J 23 Major Elements of ISA mov ro 3 H 1 Private peripheral bus Internal ld ri r0 5 ri mem r 5 Extemal RAM 1 0GB bne loop subs r2 1 Endianess 31 30 29 28 27 26 aeoo l Addressing Big Endian 32 bits Ox FFFFFFFF System 0xE0100000 Private peripheral bus External 0x E0040000 0xE0000000 External device 1 0GB 0xA0000000 0x60000000 0x 40000000 Endianess vs Little Endian e Endian ness ordering of bytes within a word Little increasing numeric significance with increasing memory addresses Big The opposite most significant byte first MIPS is big endian x86 is little endian Register Register Memory OAOBOCOD 0A0 BOCOD Memory Big endian Litthe endian 24 Instruction Encod
8. M Start low Operating Modes e Cortex M3 processor has two modes and two privilege levels e The operation modes determine whether the processor is running a normal program or running an exception handler thread mode handler mode e The privilege levels provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model privileged level mee When running an exception handler Handler mode user level on a 7 en not running an exception er i handler e g main program Thread mode Thread mode Nested Vector Interrupt Controller NVIC e A programmable device that sits between the CM3 core and the microcontroller CM3 uses a prioritized vectored interrupt model the vector table is defined to reside starting at memory location O First 16 entries in this table are defined for all Cortex M3 implementations while the remainder up to 240 are implementation specific NVIC supports dynamic redefinition of priorities with up to 256 priority levels Two entries in the vector table are especially important address 0 contains the address of the initial stack pointer address 4 contains the address of the reset handler to be executed at boot time Nested Vector Interrupt Controller NVIC Provides key system control registers including the System Timer SysTick that provides a regular timer interrupt Provision for a built in timer
9. across the Cortex M3 family has the significant advantage of making operating system code highly portable all operating systems need at least one core timer for time slicing Registers used to control the NVIC are defined to reside at address OxEQOOEOOO and are defined by the Cortex M3 specification These registers are accessed with the system bus Thumb 2 Instruction Set Thumb 2 instruction set is a superset of the previous 16 bit Thumb instruction set Provides Alarge set of 16 bit instructions enabling 2 instructions per memory fetch Asmall set of 32 bit instructions to support more complex operations Specific details of this ISA not our focus we ll mostly program in C See APPENDIX A of these slides for more details on ISA _ Thumb 2 Pai Instruction Set ra 32 bit and 16 bit Cortex M3 Thm NS Instructions 16 bit i 10 Outline Overview of ARM Cortex M3 processor Main features pipeline memory space Assembly NXP LPC17xx microcontroller unit MCU APPENDIX A Instruction Set Architecture ISA APPENDIX B ARM Instruction Set Unified Assembly Language UAL UAL supports generation of either Thumb 2 or ARM instructions from the same source code same syntax for both the Thumb code and ARM code enable portability of code for different ARM processor families Interpretation of code type is based on the directive listed in the assembly file Example Fo
10. at access memory mapped registers can interrupt the core to request attention through peripheral specific interrupt requests routed through the NVIC Data transfers between peripherals and memory can be automated using DMA Labs will cover among others basic peripheral configuration how interrupts can be used to build effective software how to use DMA to improve performance and allow processing to proceed in parallel with data transfer LPC1 68 Peripherals are memory mapped core interacts with the peripheral hardware by reading and writing peripheral registers using load and store instructions The various peripheral registers are documented in the user and reference manuals documentation include bit level definitions of the various registers and info on how to interpret those bits actual physical addresses are also found in the reference manuals Examples of base addresses for several peripherals see page 14 of the LPC17xx user manual 0x40010000 UART1 0x40020000 SPI 0x40028000 GPIO interrupts 0x40034000 ADC No real need for a programmer to look up all these values as they are defined in the library file lpc17xx h as LPC_UART1_BASE LPC_SPI_BASE LPC_GPIOINT BASE LPC_ADC_BASE 18 LPC1 68 e Typically each peripheral has Control registers to configure the peripheral Status registers to determine the current peripheral status Data registers to read data
11. d Addressing The address from the base register is used as the EA The offset is applied to the base and then written back lt Rn gt lt offset gt lt offset gt options e An immediate constant 10 e An index register lt Rm gt e A shifted index register lt Rm gt LSL lt shift gt 35 Block Transfer Instructions e Load Store Multiple instructions LDM STM e Whole register bank or a subset copied to memory or restored with single instruction Swap Instruction e Exchanges a word between registers e Two cycles but single atomic action e Support for RT semaphores 36 Modifying the Status Registers Only indirectly m MSR moves contents R1 from CPSR SPSR_ to MRS selected GPR R7 cPsR MSR P8 SPSR MRS moves contents from selected GPR to CPSR SPSR Only in privileged modes Software Interrupt SWI instruction Forces CPU into supervisor mode Usage SWI n 31 28 27 24 23 0 Maximum 274 calls Suitable for running privileged code and making OS calls 37 Branching Instructions Branch B jumps forwards backwards up to 32 MB Branch link BL same saves PC 4 in LR Suitable for function call return Condition codes for conditional branches Branching Instructions Table A4 1 Branch instructions Instruction Usage Range B on page A6 40 Branch to target address 1 MB CBNZ CBZ on page A6 52 Compare and Branc
12. e control flow such as if and while statements and procedure calls Cortex M3 Pipeline The Cortex M3 Uses the 3 stage pipeline for instruction executions Fetch gt Decode gt Execute Pipeline design allows effective throughput to increase to one instruction per clock cycle Allows the next instruction to be fetched while still decoding or executing the previous instructions Cortex M3 Pipeline Cortex M3 has 3 stage fetch decode execute pipeline a Similar to ARM7 Cortex M3 does more in each stage to increase overall performance 15t Stage Fetch 2 4 Stage Decode 3 Stage Execute Address Data Phase Phase amp Write Load Store amp Multiply amp Divide Register Read t _t Branch forwar ding amp speculation _ Execute stage branch ALU branch amp Load Store Branch This is Slide 27 of ARM Cortex M3 Introduction ARM University Relations Download from http www arm com files pdft CortexM3 Uni Intro pdf Processor Register Set e Cortex M3 core has 16 user visible registers All processing takes place in these registers e Three of these registers have dedicated functions program counter PC holds the address of the next instruction to execute link register LR holds the address from which the current procedure was called the stack pointer SP holds the address of the current stack top CM3 supports multiple execution modes each with t
13. from and write data to the peripheral LPC1 68 e In addition to providing the addresses of the peripherals lpc17xx h also provides C language level structures that can be used to access each peripheral e For example the SPI and GPIO ports are defined by the following register structures typedef struct __I0O uint32_t SPCR _ I uint32_t SPSR __I0O uint32_t SPDR __IO uint32_t SPCCR uint32_t RESERVEDO 3 __I0 uint32_ t SPINT LPC_SPI_ TypeDef 19 typedef struct union __I0O uint32_t FIODIR struct __10 __10 struct __10 __10 __10 __10 uint32_ t union uint16 t FIODIRL uint16 t FIODIRH uint8 t uints t uint8 t uint8 t FIODIRO FIODIR1 FIODIR2 FIODIR3 RESERVEDO 3 __IO uint32_t FIOMASK struct __ 10 __1I0 struct __ 10 __ 10 __I0 uint16_t FIOMASKL uint16_t FIOMASKH uint8 t uint8 t uints t uint8 t FIOMASKO FIOMASK1 FIOMASK2 FIOMASK3 LPC1 68 union __I0O uint32_t FIOPIN struct __I0 uintl6 t FIOPINL __IO uintl6 t FIOPINH F struct __I0 uint8 t FIOPINO __I0 uint8 t FIOPIN1 __I0 uint8 t FIOPIN2 __I0 uint8 t FIOPIN3 union __ IO uint32_t FIOSET struct __IO uintl6 t FIOSETL __IO uintl6 t FIOSETH struct __IO uint8_t FIOSETO __I0 uint8 t FIOSET1 __I uint8 t FIOSET2 __IO uint8 t FIOSET3 LPC1 68 union __O uint32_t FIOCLR
14. h on Nonzero 0 126 B Compare and Branch on Zero BL on page A6 49 Call a subroutine 16 MB BLY register on page A6 50 Call a subroutine optionally change Any instruction set BY on page A6 51 Branch to target address change Any instruction set TBB TBH on page A6 258 Table Branch byte offsets 0 510 B Table Branch halfword offsets 0 131070 B 38 IF THEN Instruction Another alternative to execute conditional code is the new 16 bit IF THEN IT instruction nochange in program flow no branching overhead Can use with 32 bit Thumb 2 instructions that do not support the S suffix Example CMP R1 R2 IfR1 R2 ITEQ execute next 1st instruction ADDEQ R2 R1 RO 1st instruction The conditional codes can be extended up to 4 instructions Barrier instructions Useful for multi core amp Self modifying code ker de U DMB Data memory barrier ensures that all memory accesses are completed before new memory access is committed DSB Data synchronization barrier ensures that all memory accesses are ISB completed before next instruction is executed Instruction synchronization barrier flushes the pipeline and ensures that all previous instructions are completed before executing new instructions 39
15. heir own private stack pointer e Processor Status Register PSR which is implicitly accessed by many instructions Processor Register Set r12 r13 SP r14 LR Cortex M3 Memory Address Space e ARM Cortex M3 processor has n a single 4 GB address space a EP e The SRAM and Peripheral aes ti Peripnera areas are accessed through DECR the System Bus 0x40000000 e The Code region is accessed ree through the ICode instructions and DCode ee constant data buses Ox1FFFFFFF 0x00000000 Memo Y oxFFFFFFFF Private peripherals including build in interrupt controller M a p System level NVIC MPU control registers and debug components Mainly used as external peripherals memory Mainly used for program CODE code Also provides exception wector table after power up External device Memory Map Details Ox41FFFFFF 0x40100000 Program Memory Model e RAM for an executing program is divided into three regions 1 Datain RAM are allocated during the link process and initialized by startup code at reset 2 The optional heap is managed at runtime by library code implementing functions such as the malloc and free which are part of the standard C library The stack is managed at runtime by compiler generated code which generates per procedure call stack frames containing local variables and saved registers RAM End high nd high gt in Stack Heap End lt Heap Start RA
16. ing e Instructions are encoded in machine language ARMv 7 ARM opcodes Instructions Register Value Memory Value movs rO 10 001 00 000 00001010 a 20 00 21 movs r1 0 001 00 001 00000000 Encoding T1 All versions of the Thumb ISA MOVS Rd lt imm8 gt Outside IT block MOVec gt lt Rd gt lt imm gt Inside IT block 15 14 13 13 11 10 9 7 6 5 43221 20 d WInt Rd setflags InITBlock imm32 Zerokxtend imm 32 carry APSR C 16bit Thumb 2 e Some of the changes used to reduce the length of the instructions from 32 bits to 16 bits reduce the number of bits used to identify the register e less number of registers can be used reduce the number of bits used for the immediate value e smaller number range remove options such as S e make it default for some instructions remove conditional fields N Z V C no conditional executions except branch remove the optional shift and no barrel shifter operation e introduce dedicated shift instructions remove some of the instructions e more restricted coding 25 Thumb 2 Implementation The 32 bit ARM Thumb 2 instructions are added through the space occupied by the Thumb BL and BLX instructions 31 0 32 bit Thumb 2 Instruction format The first Halfword Hw1 determines the instruction length and functionality lf the processor decodes the instruction as 32 bit long the processor fetches the second ha
17. lfword hw2 of the instruction from the instruction address plus two 32bit Instruction Encoding Example ADD instruction format e ARM 32 bit encoding for ADD with immediate field 31 28 27 26 25 24 2120 19 16 15 12 11 8 7 0 flags opcode ajor Set 4 bit opcode status rotate field Immediate flag First flag operand Typical settings register Major opcode 00 this indicates data operation instructions Minor opcode 0100 specifically 100 ADD instruction Immediate flag 1 immediate field in operand 2 Set status flag 1 set carry flag after operation register number f t t Condition vinor Destination 8 bit immediate 26 ARM and 16 bit Instruction Encoding ARM 32 bit encoding ADDS r1 r1 2 31 28 2726 25 24 2120 19 16 15 12 11 8 T N Pa i P 15 1312110 87 0 e Equivalent 16 bit Thumb instruction ADD r1 2 No condition flag No rotate field for the immediate number Use 3 bit encoding for the register Shorter opcode with implicit flag settings e g the set status flag is always set 15 14 13 12 1 10 9 8 7 6 5 Th b i O 0 0 Op Offsets Rs Move shifted register une opoe e ee e R aoaea Instruction i da EESE PONDUS MERES ALU operations Set METE pr Hi register operations branch exchange Word8 PC relative load Load store with register offset HIS Load store sign extended byte halfword 1 L Offset5 Load store with immediate offset pope fete Offset
18. ncrease performance by reducing the number of forward branches CMP rQ ri rO r1 compare r0 with r1 and set flags ADDGT r2 r2 1 if gt r2 r2 1 flags remain unchanged ADDLE r3 r3 1 if lt r3 r3 1 flags remain unchanged By default data processing instructions do not affect the condition flags but this can be achieved by post fixing the instruction and any condition code with an S loop ADD r2 r2 r3 SUBS rl rl 0x0f Bee ge Rat e E BNE loop wae if Z flag clear then branch 29 Conditional execution examples ARM instructions unconditional CMP r0 BNE else ADD rl B end else ADD r2 r2 end C source code 5 instructions 3 instructions 5 words 3 words 5 or cycles 3 cycles Outline Overview of ARM Cortex M3 processor Main features pipeline memory space Assembly NXP LPC17xx microcontroller unit MCU APPENDIX A Instruction Set Architecture ISA APPENDIX B ARM Instruction Set 30 ARM Instruction Set Data Processing Instructions Arithmetic and logical operations 3 address format Two 32 bit operands op1 is register op2 is register or immediate 32 bit result placed in a register Barrel shifter for op2 allows full 32 bit shift within instruction cycle 31 Data Processing Instructions Arithmetic operations ADD ADDC SUB SUBC RSB RSC Bit wise logical operations AND EOR ORR BIC Register movement operati
19. ons MOV MVN Comparison operations TST TEQ CMP CMN Data Processing Instructions Conditional codes Data processing instructions Barrel shifter Powerful tools for efficient coded programs 32 Data Processing Instructions e g if 7 1 R1 R2 R3 4 compiles to Arithmetic logic unit EQADDS R1 R2 R3 LSL 2 SINGLE INSTRUCTION Multiply Instructions Integer multiplication 32 bit result Long integer multiplication 64 bit result Built in Multiply Accumulate Unit MAC Multiply and accumulate instructions add product to running total 33 Multiply Instructions Multiply 32 bit result Multiply accumulate 32 bit result Unsigned multiply 64 bit result Unsigned multiply accumulate 64 bit result signed multiply 64 bit result Signed multiply accumulate 64 bit result Data Transfer Instructions Load store instructions Used to move signed and unsigned Word Half Word and Byte to and from registers Can be used to load PC if target address is beyond branch instruction range 34 Addressing Modes e Offset Addressing Offset is added or subtracted from base register Result used as effective address for memory access lt Rn gt lt offset gt e Pre indexed Addressing Offset is applied to base register Result used as effective address for memory access Result written back into base register lt Rn gt lt offset gt e Post indexe
20. r GNU Assembler the directive for UAL is syntax unified For ARM assembler the directive for UAL is THUMB See comprehensive listing of Cortex M3 instruction set in Appendix A of book Joseph Jiu The Definitive guide to the ARM Cortex M3 2009 download from link provided here http dejazzer com coen4720 lectures html 11 Example 1 byte 0x12 20 0x20 1 mov r0 0 mov r4 0 movw rl lowerl6 data movt rl upperl6 data ldrb r2 r1 1 add r4 r2 add rO 1 cmp 4 bne MOV register Move register copies a value from a register to the destination register It can optionally update the condition flags based on the value Encoding T1 ARMv6 ML ARMv M If lt Rd gt and lt fm both from RO R7 otherwise all versions of the Thumb ISA Macs Rds Rm If lt Rd gt 1s the PC must be outside or last in IT block 15 14 13 12 11 10 9 8 765431310 oio ooaj op mm a From ARM d Wint D Rd m UInt Rm setflags FALSE Arch Itectu re if d 15 amp InllBlock amp amp LastInITBlock then UNPREDICTABLE Refe rence M anu al Encoding T2 All versions of the Thumb ISA MOWS lt Rd gt lt Rm Fermeri ape Not permitted inside IT block 15 14 13 12 11 10 9 8 7 64543 23 d UInt Rd m UInt Rm setflags TRUE if InITBlock then UNPREDICTABLE There are similar entries for move immediate move shifted which actually maps to different Encoding T3 ARMvi M instructions etc MO Speco W lt Rd gt
21. rtex M3 based microcontroller The Cortex M 3 is also the basis for microcontrollers from other manufacturers including Tl ST Toshiba Atmel etc LPC1768 operates at up to a 100 MHz CPU frequency Sophisticated clock system Peripherals include up to 512 kB of flash memory up to 64 kB of data memory Ethernet MAC a USB interface that can be configured as either Host Device or OTG 8 channel general purpose DMA controller 4 UARTs 2 CAN channels 2 SSP controllers SPI interface 3 12C interfaces 2 input plus 2 output 12S interface 8 channel 12 bit ADC 10 bit DAC motor control PWM Quadrature Encoder interface 4 general purpose timers 6 output general purpose PWM ultra low power RTC with separate battery supply up to 70 general purpose I O pins 16 LPC17638 Abstract Representation of a Development Board such as LandTiger 2 0 User I O Analog LCD Display Input Dual RS232 Configuration Dual CAN Jumpers LPC17xx Reset amp Interrupt Or variant Buttons Port LEDs USB SD Card Power amp COM Recall from lecture 1 ELECTROMECHANICAL PACKLUP amp SAFETY EXTERNAL ENVIRONMENT 17 LPC1 68 LPC1768 microcontrollers are based on the Cortex M3 processor with a set of peripherals distributed across three buses Advanced High performance Bus AHB and its two Advanced Peripheral Bus APB sub buses APB1 and APB2 These peripherals are controlled by the CM3 core with load and store instructions th
22. ss networking applications Improved code density code fits in even the smallest memory footprints Core pipeline has 3 stages Instruction Fetch Instruction Decode Instruction Execute Simplified Cortex M3 Architecture CM3 Core Interrupts Inst Data Code DCode System Cortex M3 Processor Core System Register Bank Memory Interface hoy pO Memory Instruction Bus Protection Data Bus Unit Bus Interconnect Debug Interface Memory System Private and Peripherals Peripherals Interrupts Instruction Fetch Unit Trace Interface Interrupt Controller Optional Cortex M3 Processor Architecture e Harvard architecture it uses separate interfaces to fetch instructions Inst and Data e Processor is not memory starved it permits accessing data and instruction memories simultaneously e From CM3 perspective everything looks like memory Only differentiates between instruction fetches and data accesses e Interface between CM3 and manufacturer specific hardware is through three memory buses Code DCode and System for peripherals which are defined to access different regions of memory Cortex M3 Processor e Cortex M3 is a load store architecture with three basic types of instructions 1 Register to register operations for processing data Memory operations which move data between memory and registers 3 Control flow operations enabling programming languag
23. struct __O uintl6_t FIOCLRL uint16 t FIOCLRH O struct __O __O __O __O LPC_GPIO_TypeDef uint8_t uint8_t uint8_t uint8_t FIOCLRO FIOCLR1 FIOCLR2 FIOCLR3 e The register addresses of the various ports are defined in the library see lpc17xx h define define define define define define LPC _APBO BASE LPC _UART1 BASE LPC SPI_BASE LPC GPIOINT BASE LPC ADC BASE LPC _GPIO1 0Ox40000000UL LPC_APBO BASE LPC _APBO BASE LPC _APBO BASE LPC _APBO BASE 0x10000 0x20000 0x28080 0x34000 LPC_GPIO TypeDef LPC _GPIO1_ BASE For example to turn on the LED marked as D11 on the LandTiger 2 0 board which is driven by the pin P2 1 of the MCU the following code can be used LPC _GPIO1 gt FIOSET 1 lt lt 1 20 Memory e On chip flash memory system Up to 512 kB of on chip flash memory Flash memory accelerator maximizes performance for use with the two fast AHB Lite buses Can be used for both code and data storage e On chip Static RAM Up to 64 kB of on chip static RAM memory Up to 32 kB of SRAM accessible by the CPU and all three DMA controllers are on a higher speed bus Devices with more than 32 kB SRAM have two additional 16 kB SRAM blocks LPC17xx system memory map l APB1 peripherals LPC1768 memory space EFREN or FFF 0x4008 C000 127 4 reserved z 0x4008 8000 14 motor
Download Pdf Manuals
Related Search