Chapter 3 Basic Simulation - Mentor Graphics SupportNet
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1. Figure 3 14 Parameter Name and Value in Source Examine Window Source Examine Xx test_counter dut ALWAYS 35 tpd reset to count 3 ox use the examine command at the VSIM gt prompt to output a variable value to the Transcript window 1 e examine count 5 Try out the step commands a Click the Step Into icon on the Step toolbar Ens Questa SIM Tutorial v10 3 35 Basic Simulation Set Breakpoints and Step through the Source This single steps the debugger Experiment on your own Set and clear breakpoints and use the Step Step Over and Continue Run commands until you feel comfortable with their operation Lesson Wrap Up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation 2 Click Yes when prompted to confirm that you wish to quit simulating 36 Questa SIM Tutorial v10 32. The simulation continues running until you execute a break command or it hits a statement in your code ie a Verilog stop statement that halts the simulation d Click the Break icon to stop the simulation 32 Questa SIM Tutorial v10 3 Basic Simulation Set Breakpoints and Step through the Source Set Breakpoints and Step through the Source Next you will take a brief look at one interactive debugging feature of the Questa SIM environment You will set a breakpoint in the Source window run the simulation and then step through the design under test Breakpoints can be set only on executable lines which are indicated with red line numbers 1 Open counter v in the Source window a Select View gt Files to open the Files window b Click the sign next to the sim filename to see the contents of vsim wlf dataset c Double click counter v or counter vhd if you are simulating the VHDL files to open the file in the Source window 2 Seta breakpoint on line 36 of counter v or line 39 of counter vhd for VHDL a Scroll to line 36 and click in the Ln line number column next to the line number A red dot appears in the line number column at line number 36 Figure 3 9 indicating that a breakpoint has been set Figure 3 9 Setting Breakpoint in Source Window 4 Tutorial examples tutorials verilog basicSimulation counter v test_counter dut Default Go Ln fe m Now fer 35 36 ee blways posedge clk or posedge re
3. Chapter 3 Basic Simulation Introduction In this lesson you will go step by step through the basic simulation flow 1 Create the Working Design Library 2 Compile the Design Units 3 Optimize the Design 4 Load the Design 5 Run the Simulation Design Files for this Lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated test bench The pathnames are as follows Verilog lt install_dir gt examples tutorials verilog basicSimulation counter v and tcounter v VHDL lt install_dir gt examples tutorials vhdl basicSimulation counter vhd and tcounter vhd This lesson uses the Verilog files counter v and tcounter v If you have a VHDL license use counter vhd and tcounter vhd instead Or if you have a mixed license feel free to use the Verilog test bench with the VHDL counter or vice versa Related Reading User s Manual Chapters Design Libraries Verilog and SystemVerilog Simulation and VHDL Simulation Reference Manual commands vlib vmap vlog vcom vopt view and run Create the Working Design Library Before you can simulate a design you must first create a library and compile the source code into that library 1 Create a new directory and copy the design files for this lesson into it Questa SIM Tutorial v10 3 25 Basic Simulation Create the Working Design Library 26 Start by creating a new directory for this exercise in case other users will be working
4. ECH pa_lib MODEL_TECH upf_lib Sms gp AP tanita tee oem te 1 Use the vopt command to optimize the design with full visibility into all design units a Enter the following command at the Questa SIM gt prompt in the Transcript window vopt acc test_counter o tesicounter_opt The acc switch provides visibility into the design for debugging purposes The o switch allows you designate the name of the optimized design file testcounter_opt Note You must provide a name for the optimized design file when you use the vopt command Load the Design 1 Load the test_counter module into the simulator a Use the optimized design name to load the design with the vsim command vsim testcounter_opt When the design is loaded a Structure window opens labeled sim This window displays the hierarchical structure of the design as shown in Figure 3 5 You can navigate within the design hierarchy in the Structure sim window by clicking on any line with a expand or Questa SIM Tutorial v10 3 contract icon 29 Basic Simulation Load the Design Figure 3 5 The Design Hierarchy sim Ee fen bes Plinstance Design unit Design unit type visibility I E ieee dut rt Jj increment g FALways 35 g INITIAL 17 g IMITIAL ZS wt IMITIAL 30 p ysim_capacity Library d sim Fest counter fas st l counker Fast counter Fast counter Fast best counter Fast best cou
5. Files dialog Figure 3 3 If the Compile menu option is not available you probably have a project open If so close the project by making the Library window active and selecting File gt Close from the menus b Select both counter v and tcounter v modules from the Compile Source Files dialog and click Compile The files are compiled into the work library c When compile is finished click Done Questa SIM Tutorial v10 3 27 Basic Simulation Compile the Design Units Figure 3 3 Compile Source Files Dialog Compile Source Files Library work 10 15 2013 6 56 7 31 2013 8 43 PM 7 31 2013 8 43 PM Compile selected files together Default Options Edit Source 2 View the compiled design units a In the Library window click the icon next to the work library and you will see two design units Figure 3 4 You can also see their types Modules Entities etc and the path to the underlying source files 28 Questa SIM Tutorial v10 3 Basic Simulation Optimize the Design Figure 3 4 Verilog Modules Compiled into work Library Library a work Library 1 counter Module 0 test_counter Module hh Floatrixlib Library H mcz ib Library hi mti wm Library i miticenn Library H mira Library TA a n Optimize the Design work C imodeltech C imodeltech MODEL_TECH lFloatFizxlib MODEL TECH fmc2 dib MODEL_TECH fayvm MODEL TECH foym 2 0 3 MODEL_T
6. ents from your operating system all changes should be made from within Questa SIM Questa SIM Tutorial v10 3 Basic Simulation Compile the Design Units Questa SIM also adds the library to the Library window Figure 3 2 and records the library mapping for future reference in the Questa SIM initialization file modelsim in1 Figure 3 2 work Library Added to the Library Window Library piName e Path H work Library work Hi floatfixlib ibrary SMODEL_TECH SHI mtiAvm Library MODEL_TECH fe HIJ mtiovm library SMODEL TECH om H mtivPr library MODEL_TECH qe i sv_std Library SMODEL_TECH 2 H vitalz000 Library MODEL_TECH H jeee ibrary MODEL_TECH g H modelsim_lib Library SMODEL_TECH 3 L ibrary SMODE gear std When you pressed OK in step 3c above the following was printed to the Transcript window vlib work vmap work work These two lines are the command line equivalents of the menu selections you made Many command line equivalents will echo their menu driven functions 1n this fashion Compile the Design Units With the working library created you are ready to compile your source files You can compile by using the menus and dialogs of the graphic interface as in the Verilog example below or by entering a command at the Questa SIM gt prompt 1 Compile counter v and tcounter v a Select Compile gt Compile This opens the Compile Source
7. nter Fast best counter Fast Module Module Function Process Process Process Process Foreign aCc 4cc 4Cc 4Cc 4 k elie T a i 2 Open the Objects and Processes windows a Select View gt Objects from the menu bar b Select View gt Process The Objects window shows the names and current values of data objects in the current region selected in the Structure sim window Figure 3 6 Data objects include signals nets registers constants and variables not declared in a process generics parameters and member data variables of a SystemC module The Processes window displays a list of HDL and SystemC processes in one of four viewing modes Active In Region Design and Hierarchical The Design view mode is intended for primary navigation of ESL Electronic System Level designs where processes are a foremost consideration By default this window displays the active processes in your simulation Active view mode 30 Questa SIM Tutorial v10 3 Basic Simulation Run the Simulation Figure 3 6 The Object Window and Processes Window Register Internal Register Internal ahxx Net Internal FINITIAL 418 Initial FINITIAL 24 Initial FINITIAL 31 Initial Run the Simulation We re ready to run the simulation But before we do we ll open the Wave window and add signals to it 1 Open the Wave window a Enter view wave at the command line The Wave window opens in the righ
8. set if reget count tpd reset to count 6 hoo else count lt tpd clk to count increment count 3 Disable enable and delete the breakpoint a Click the red dot to disable the breakpoint It will become a gray dot b Click the gray dot again to re enable the breakpoint It will become a red dot c Click the red dot with your right mouse button and select Remove Breakpoint 36 d Click in the line number column next to line number 36 again to re create the breakpoint 4 Restart the simulation Questa SIM Tutorial v10 3 33 Basic Simulation Set Breakpoints and Step through the Source a Click the Restart icon to reload the design elements and reset the simulation time to zero The Restart dialog that appears gives you options on what to retain during the restart Figure 3 10 Figure 3 10 Setting Restart Functions Restart Ed I List Format l Wave Format M Breakpoints W Logged Signals IW Assertions a Cover Directves lw ATV Format b Click the OK button in the Restart dialog c Click the Run All icon The simulation runs until the breakpoint is hit When the simulation hits the breakpoint it stops running highlights the line with a blue arrow in the Source view Figure 3 11 and issues a Break message in the Transcript window Figure 3 11 Blue Arrow Indicates Where Simulation Stopped Tutorial examples tutorials verilog basicSimulation counter v test_counter dut Defaul
9. t 22 2 Ea Es Ln 1 m Now r 35 36 ey blways posedge clk or posedge reset 37 if reset 36 count tpd reset to count 6 hoo 39 else 40 count lt tpd clk to count increment count 41 When a breakpoint is reached typically you want to know one or more signal values You have several options for checking values Look at the values shown in the Objects window Figure 3 12 34 Questa SIM Tutorial v10 3 Basic Simulation Set Breakpoints and Step through the Source Figure 3 12 Values Shown in Objects Window tpd_reset_to_count Parameter Internal tod dk to count 32 Parameter Internal count hie Packed Array Out thi Net In ho Net In Set your mouse pointer over a variable in the Source window and a yellow box will appear with the variable name and the value of that variable at the time of the selected cursor in the Wave window Figure 3 13 Figure 3 13 Hover Mouse Over Variable to Show Value es tutorials verilog basicSimulation counter y itest counter iduk Default Hir Lr 1H m Non A E iis J6 E always U iposedge clk or posedge reset 37 if reset 5 o teat counter dut resec a hoo 39 else l a 40 co oo ncerement count 41 H e Highlight a signal parameter or variable in the Source window right click it and select Examine from the pop up menu to display the variable and its current value in a Source Examine window Figure 3 14
10. t side of the Main window Resize it if necessary so it is visible You can also use the View gt Wave menu selection to open a Wave window The Wave window is just one of several debugging windows available on the View menu 2 Add signals to the Wave window a In the Structure sim window right click test_counter to open a popup context menu b Select Add Wave Figure 3 7 All signals in the design are added to the Wave window Questa SIM Tutorial v10 3 31 Basic Simulation Run the Simulation Figure 3 7 Using the Popup Menu to Add Signals to Wave Window amp sim Default ae Et ey ey Plinstance Design unit Design unit type t E test_counte lees Module View Declaration z dut Hogue Jj ince View Instantaton arii l IOC INTIA F O F g ANTA es T OCES vsim_capa Capacity Add Wave To b Add Dataflow Ctrl D Add to d aa teen EI T F 3 Run the simulation a Click the Run icon The simulation runs for 100 ns the default simulation length and waves are i drawn in the Wave window b Enter run 500 at the VSIM gt prompt in the Transcript window The simulation advances another 500 ns for a total of 600 ns Figure 3 8 Figure 3 8 Waves Drawn in Wave Window E wave Default Msgs itest counter telk 1 h thest_counter reset 1 hd ftest_counterfcount amp hle UCC UCOD COCO c Click the Run All icon on the Main or Wave window toolbar
11. with these lessons Verilog Copy counter v and tcounter v files from lt install_dir gt examples tutorials verilog basicSimulation to the new directory VHDL Copy counter vhd and tcounter vhd files from lt install_dir gt examples tutorials vhdl basicSimulation to the new directory 2 Start Questa SIM if necessary a b Type vsim at a UNIX shell prompt or use the Questa SIM icon in Windows Upon opening Questa SIM for the first time you will see the Welcome to Questa SIM dialog Click Close Select File gt Change Directory and change to the directory you created in step 1 3 Create the working library a b C Select File gt New gt Library This opens a dialog where you specify physical and logical names for the library Figure 3 1 You can create a new library or map to an existing library We ll be doing the former Figure 3 1 The Create a New Library Dialog Create a New Library f x _reate C anen library a map to an existing library f 3 new library and a logical mapping to it Library Marne hiro LE Library Physical Mame hina LE OK Cancel Type work in the Library Name field if it isn t already entered automatically Click OK Questa SIM creates a directory called work and writes a specially formatted file named _ info into that directory The _info file must remain in the directory to distinguish it as a Questa SIM library Do not edit the folder cont
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