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PowerPC 405GPr Embedded Processor Data Sheet

1. 00000 J 00000 H 00000 00000 F 00000 00000 0000000000000 0000000000000 D v B 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 h 120 409 0 20 B 0 55 0 15 SOLDERBALL x 456 A 24 0 REF v 5 0 15 0 35 C 1 00 0 45 2 21 4 13 Preliminary PowerPC 405GPr Embedded Processor Data Sheet 35mm 456 Ball E PBGA Package Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded Top View Gold Gate Release Corresponds to 1 Ball Location A 33 5 REF 17 5 TYP v v Note All dimensions mm 0 20 22 35 0 102510 0 35 C Bottom View AF 9000000000000000000000066 1 27 TYP 0600000000000000000000000006 AD 000000000000
2. 38 Recommended DC Operating 5 1 39 Input Capacitance ee ena eared eee Ge id 40 DC Electrical Characteristics 41 Clocking Specifications 42 Peripheral Interface Clock Timings 1 44 Specifications Group 1 46 2 49 PPC405GPr Legacy Mode Strapping Pin Assignments 51 PPC405GPr New Mode Strapping Pin Assignments 53 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Figures PPC405GPr Embedded Controller Functional Block Diagram 5 27mm 456 Ball E PBGA 1 13 35mm 456 Ball E PBGA 2 14 5V Tolerant Input 2 40 Input Setup and Hold Waveform
3. Function Option Ball Strapping pal Tunng TES Tx DTR for 6 lt lt 7 use choice 3 for 72M lt 12 wee choice 5 Choice 1 TUNE 9 0 1010111100 0 0 0 for 12 lt 32 use choice 6 Choice 2 TUNE 9 0 0100111000 0 0 1 Choice 3 TUNE 9 0 0100110110 0 1 0 Choice 4 TUNE 9 0 0100111100 0 1 1 Choice 5 TUNE 9 0 0100111000 1 0 0 Choice 6 TUNE 9 0 1000111100 1 0 1 Choice 7 TUNE 9 0 1000111110 1 1 0 Choice 8 TUNE 9 0 1011111110 1 1 1 PLL Forward Divider 2 016 15 DMAAck1 Bypass mode 0 0 Divide by 3 0 1 Divide by 4 1 0 Divide by 6 1 1 PLL Feedback Divider 2 B14 C12 DMAAck2 DMAAck3 Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 PLB Divider from CPU 2 P25 L24 EMCTxD3 EMCTxD2 Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 Preliminary PowerPC 405GPr Embedded Processor Data Sheet PPC405GPr Legacy Mode Strapping Pin Assignments Part 2 of 2 Function Option Ball Strapping OPB Divider from PLB 2 L25 J26 EMCTxD1 EMCTxDO Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 PCI Divider from PLB 23 D18 C20 GPIO1 TS1E GPIO2 TS2E Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 External Bus Divider from PLB K25 K23 EMCTxE
4. 45 Output Delay and Float Timing Waveform 2 4 45 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Ordering PVR and JTAG Information Product Order Part Number eae PVR Value JTAG ID PPCA05GPr IBM25PPC405GPr 3BA266C 266MHz 35mm 456E PBGA 0 50910950 0 14088049 PPC405GPr IBM25PPC405GPr 3BA266CZ 266MHz 35mm 456 0x50910950 0x14088049 PPC405GPr IBM25PPC405GPr 3DA266C 266MHz 27mm 456E PBGA 0x50910950 0x14088049 PPC405GPr IBM25PPC405GPr 3DA266CZ 266MHz 27mm 456E PBGA 0 50910950 0x14088049 PPC405GPr 25 050 333MHz 35mm 456 E PBGA 0 50910950 0 14088049 05 IBM25PPC4O5GPr 3BA333CZ 333MHz 35mm 456 E PBGA 0 50910950 0 14088049 PPC405GPr IBM25PPC405GPr 3DA333C 333MHz 27mm 456E PBGA 0 50910950 0x14088049 PPC405GPr IBM25PPC405GPr 3DA333CZ 333MHz 27 456 0 50910950 0x14088049 Note 1 2 at the end of the Order Part Number indicates a tape and reel shipping package Otherwise the chips are shipped in a tray This section provides the part number nomenclature For availability contact your local IBM sales office The part number contains a part modifier Included in the modifier is a revision code This refers to the die mask revision nu
5. O 3 3V LVTTL 6 PHYRxErr Receive Error This signal comes from the PHY and is 5V tolerant 1 synchronous to the 3 3V LVTTL T 5V tolerant PHYRxClk Receiver Medium clock This signal is generated by the PHY 3 3V LVTTL 1 Receive Data Valid Data on the Data Bus is valid when this 5V tolerant PHYRxDV signal is activated Deassertion of this signal indicates end of the 1 3 3V LVTTL frame reception PHYCrS Carrier Sense signal from the PHY This is an asynchronous 5V tolerant 1 signal 3 3V LVTTL Transmit Error This signal is generated by the Ethernet 5V tolerant EMCTxErr controller is connected to the PHY and is synchronous with the 3 3V LVTTL 6 It informs the PHY that an error was detected Transmit Enable This signal is driven by the to the PHY EMCTxEn Data is valid during the active state of this signal Deassertion of 5V tolerant 6 this signal indicates end of frame transmission This signal is 3 3V LVTTL synchronous to the This clock comes from the PHY and is the Medium Transmit 5V tolerant clock 3 3V LVTTL 1 A 5V tolerant PHYCol Collision signal from the PHY This is an asynchronous signal 3 3V LVTTL 1 Management Data Clock The is sourced to the PHY This EMCMDCIk clock has a period of 400ns adjustable via 5V tolerant EMACO STACR OPBC Management information is transferred 3 3V LVTTL synchronously with respect to this clo
6. 1 6 l Odd Trace execution status To access this function software O 3 3v LVTTL must toggle a DCR bit General Purpose I O or 5V tolerant GPIO4 TS20 1 6 Odd Trace execution status To access this function software O 3 3v LVTTL must toggle a DCR bit General Purpose I O GPIO5 8 TS3 6 19 vojoj tolerant 1 6 Trace status To access this function software must toggle 3 3V LVTTL DCR bit General Purpose or Trace interface clock A toggling signal that is always half of the 5V tolerant GPIO9 TrcCIk CPU core frequency To access this function software must VO O 1 6 3 3 LVTTL toggle DCR bit Note Initialization strapping must hold this pin low 0 during reset General Purpose 24 Note The pull up initialization strapping resistor must 1 UO 3 3V LVTTL 1 6 rather than in order to overcome the internal pull down w pull down i resistor Test Enable Used only for manufacturing tests Pull down for 1 8V CMOS TestEn n normal operation w pull down TmrClk An external clock input that can be used to clock the timers in the 5V tolerant 1 3 3V LVTTL Trace Interface Even Trace execution status To access this function software TS1E GPIO1 must toggle a DCR bit ovo tolerant 1 6 TS2E GPIO2 or VO 33v LVTTL General Purpose 36 PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 8 of 8
7. 266MHz 500 1000 MHz VCOFc VCO frequency 333MHz 500 1333 MHz PLB frequency 266 MHz 133 33 MHz OPB frequency 266MHz 66 66 MHz Clocking Waveform 42 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator SSCG with the PPC405GPr This controller uses a PLL for clock generation inside the chip The accuracy with which the PLL follows the SSCG is referred to as tracking skew The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency When using an SSCG with the PPC405GPr the following conditions must be met The frequency deviation must not violate the minimum clock cycle time Therefore when operating the PPC405GPr with one or more internal clocks at their maximum supported frequency the SSCG can only lower the frequency The maximum frequency deviation cannot exceed 3 and the modulation frequency cannot exceed 40kHz In some cases on board PPC405GPr peripherals impose more stringent requirements see Note 1 Use the peripheral bus clock PerCIk for logic that is synchronous to the peripheral bus since this clock tracks the modulation Use the SDRAM MemClkOut since it also tracks the modulation Notes 1 The serial port baud rates ar
8. 1 Ethernet Interface settable 2 10 3 7 1 2 EMCMDIO PHYMDIO 100 0 Mrd Po 10 3 74 EMCMDCk 2 EMCTxD3 0 na na 20 2 10 3 7 1 PHYTX 2 EMCTxEn na na 20 2 10 3 7 1 PHYTX 2 EMCTxErr na na 20 2 10 3 7 1 2 PHYCol 10 3 7 1 2 PHYCrS 10 3 7A 2 async 2 PHYRxD3 0 4 1 na na 10 3 7 1 2 PHYRxDV 4 1 na na 10 3 7 1 2 PHYRxErr 4 1 na na 10 3 7 1 PHYRX 2 2 46 PowerPC 405GPr Embedded Processor Data Sheet Specifications Group 1 Part 2 of 3 Notes Preliminary 1 PCI timings are for asynchronous operation up to 66 66 MHz PCI output hold time requirement is 1 for 66 66 MHz and 2ns for 33 33MHz 2 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 3 For PCI I O is specified at 0 9 and L is specified at 0 1OVpp For all other interfaces I O H is specified at 2 4 and I O L is specified at 0 4 V Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time 1 0 H VOL Clock Notes min Internal Peripheral Interface IICSCL na na na na 15 3 10 2 IICSDA na na na na 15 3 10 2 UARTO CTS na na 10 3 7 1 UARTO DCD na na 10 3 7 1 UARTO DSR na na
9. 10 or 7 bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters e Supports fixed Vpp interface Two independent 4 x 1 byte data buffers Fifteen memory mapped fully programmable configuration registers One programmable interrupt request signal Provides full management of all bus protocol Programmable error recovery Preliminary PowerPC 405GPr Embedded Processor Data Sheet General Purpose IO GPIO Controller Controller functions and GPIO registers are programmed and accessed via memory mapped OPB bus master accesses 23 of 24 GPIOs are pin shared with other functions DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose The 23 GPIOs are multiplexed with 7 of 8 chip selects All 13 external interrupts All nine instruction trace pins Each GPIO output is separately programmable to emulate an open drain driver i e drives to zero three stated if output bit is 1 Universal Interrupt Controller UIC The Universal Interrupt Controller UIC provides the control status and communications necessary between the various sources of interrupts and the local PowerPC processor Features include Supports 13 external and 19 internal interrupts Seven of the 13 interrupts are mapped to the same GPIOs as the PPC405GP The other six interrupts can be mapped to any of the GPIOs Edge trig
10. 11 14 GND V23 IRQ1 GPIO18 K4 PerData24 N2 PerData13 R15 GND V24 PHYRxDV K5 N3 PerData10 R16 GND V25 IRQO GPIO 17 K22 Vpp N4 PerData16 R22 Vpp V26 PCIAD31 K23 EMCTxEn N5 GND R23 PCIAD25 w1 MemData30 K24 PCIC2 BE2 N11 GND R24 PCIAD24 2 MemData27 K25 EMCTxErr N12 GND R25 PCIAD27 W3 MemData28 K26 PCIAD16 N13 GND R26 PCIC3 BE3 W4 MemData26 L1 GND N14 GND T1 GND w5 OVpp L2 PerData21 N15 GND T2 HoldPri W22 OVpp L3 PerData18 N16 GND T3 ExtReset W23 PHYCrS L4 PerData19 N22 GND T4 PerData3 W24 IRQ2 GPIO 19 L5 Vpp N23 PCIGnt4 5 Vpp W25 IRQ3 GPIO20 L11 GND N24 OVpp T11 GND W26 GND L12 GND N25 PCIAD20 T12 GND Y1 L13 GND N26 PCIAD22 T13 GND Y2 MemData25 L14 GND P1 PerData9 T14 GND Y3 ExtAck L15 GND P2 PerData7 115 GND Y4 ExtReq L16 GND P3 OVpp T16 GND Y5 OVpp L22 VDD P4 PerData5 T22 Vpp Y22 OVpp L23 PCIAD17 P5 GND T23 PCIGntt Y23 Reserved L24 EMCTxD2 P11 GND T24 PCIAD28 Y24 IRQ4 GP1021 L25 EMCTxD1 P12 GND T25 PCIAD30 Y25 IRQ5 GPIO22 L26 GND P13 GND T26 GND Y26 Reserved 26 PowerPC 405GPr Embedded Processor Data Sheet Signals Listed by Ball Assignment Part of 3 Preliminary Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name 1 GND AB26 Halt AD9 MemData8 AE18 UARTO DCD AA2 MemData23 AC1 UART1 Rx AD10 MembData6 AE19 7 DQM3 AC2 UART1_Tx AD11 MemD
11. Individually connect PCISErr PCIPErr PCITRDY and PCIStop through 3 3kQ resistors to 43 3 V Terminate PCIReq1 5 to 3 3V Terminate to GND For selected interfaces it is possible to turn off input receivers for some or all of the signals on that interface Control for this receiver gating is in register CR1 When this gating capability is applied to unused signals it is not necessary to strap them Refer to the PowerPC 405GPr Embedded Processor User s Manual for details External Bus Control Signals All peripheral bus control signals PerCS0 7 PerR W PerWBE0 3 PerOE PerWE PerBLast HoldAck ExtAck are set to the high impedance state when ExtReset 0 In addition as detailed in the PowerPC 405GPr Embedded Processor User s Manual the peripheral bus controller can be programmed via EBCO CFG to float some of these control signals between transactions and or when an external master owns the peripheral bus As a result a pull up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal The following table lists all of the signals provided by the PPC405GPr Please refer to Signals Listed Alphabetically on page 15 for the pin number to which each signal is assigned 29 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 1 of 8 Multiplexed signals are shown in
12. Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes Receiver input has hysteresis Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values If not used must pull down Strapping input during reset pull up or pull down as required 2 3 4 not used must pull up 5 6 7 Pull up may be required See External Bus Control Signals on page 29 Preliminary ground to these pins 4 must be tied to OVpp or GND Signal Name Description yo Type Notes Odd Trace execution status To access this function software must toggle a DCR bit 5V tolerant TS1O GPIOS BF 3 3V LVTTL 1 6 General Purpose Odd Trace execution status To access this function software must toggle a DCR bit 5V tolerant TS2OJaPlOs 7 33v LVTTL Ws General Purpose Trace status To access this function software must toggle a DCR bit 5V tolerant TS3 6 GPIO5 8 3 3v LVTTL General Purpose Trace interface clock A toggling signal that is always half of the CPU core frequency To access this function software must toggle a DCR bit TreClk GPIOg or 2y tolerant 1 6 3 3V LVTTL General Purpose Note Initialization strapping
13. Used as inputs when an external bus master owns the external interface 32 PowerPC 405GPr Embedded Processor Data Sheet Preliminary Signal Functional Description Part 4 of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values 4 not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description yo Type Notes Peripheral write enable Low when any of the four PerWBE0 3 eee write byte enables are low 5V tolerant PerWE PCIINT r 3 3V PCI PCI interrupt Open drain output two states 0 or open circuit PerCSO Peripheral chip select bank 0 d 11 7 Seven additional peripheral chip selects c 5V tolerant PerCS1 7 GPIO10 16 15 7 l General Purpose I O To access this function software must Ol 3 3v LVTTL toggle a DCR bit Used by either peripheral controller or DMA controller depending 5V tolerant PerOE upon the type of transfer involved When the PPC405GPr is the 3 3V
14. 266 2 Ipp 520 570 mA Active Operating Current Vpp 333MHz Ipp 620 740 mA Active Operating Current OVpp 266 MHz lopp 50 60 mA Active Operating Current OVpp 333MHz lopp 60 70 mA PLL Vpp Input current IPLL 16 23 mA Active Operating Power 266 MHz Pop 1 1 1 3 Ww Active Operating Power 333 MHz Ppp 1 3 1 7 1 Active operating currents and power values are design estimates 2 AVpp should be derived from Vpp using the following circuit Vpp 6000 AVpp L1 2 24 SMT inductor equivalent to MuRata LQH3C2R2M34 or SMT chip ferrite bead equivalent L1 to MuRata BLM31A700S T C1 C2 C3 C1 3 3 UF SMT tantalum AGND C2 0 41 SMT monolithic ceramic capacitor with X7R e dielectric or equivalent GND C3 0 01 SMT monolithic ceramic capacitor with X7R dielectric or equivalent Test Conditions Clock timing and switching characteristics are specified in Output accordance with operating conditions shown in the table Pin Recommended DC Operating Conditions For all signals other than S0pF l All signals other PCI signals AC specifications are characterized at OVpp and than PCI 85 C with the 50pF test load shown in the figure at right aL For PCI signals there are two different test load circuits one for the 5 rising edge and one the falling edge as shown in
15. 10 3 7 1 UARTO DTR 10 3 14 UARTO RI na na 10 3 7 1 UARTO RTS na na 10 3 7 1 UARTO Rx na na 10 3 7 1 UARTO Tx na na 10 3 7 1 MEME na na 10 3 7 1 VARTI DSR na na na na UART1_CTS UART1_Rx na na na na UART1_Tx na na 10 3 7 1 UARTSerClk na na na na Interrupts Interface IRQ0 6 GP1017 23 10 3 7 1 JTAG Interface TCK na na async TDI na na async TDO 10 3 7A async TMS na na async TRST na na async 47 Preliminary Notes PowerPC 405GPr Embedded Processor Data Sheet Specifications Group 1 Par of 3 1 PCI timings are for asynchronous operation up to 66 66 MHz PCI output hold time requirement is 1 for 66 66 MHz and 2ns for 33 33MHz 2 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 3 For PCI I O is specified at 0 9OVpp and L is specified at 0 1OVpp For all other interfaces H is specified at 2 4 V and I O L is specified at 0 4 V Signal Input ns Output ns Output Current mA System Interface Setup Time Tis min Hold Time min Valid Delay Tov max Hold Time min VOH min VOL min Clock Notes 1 2 GPIO1 GPIO2 GPIO3 4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 24 10 3 7 1 Halt dc SysClk na na na na SysE
16. Column Address Strobe 3 3V LVTTL DQM for byte lane 0 MemData0 7 1 MemData8 15 POMOS 2 MemData16 23 and SSV 3 MemData24 31 DQMCB for ECC check bits 3 3V LVTTL 0 7 check bits 0 7 y o 3 3V LVTTL BankSel0 3 Select up to four external SDRAM banks 3 3V LVTTL WE Write Enable 3 3V LVTTL ClkEn0 1 SDRAM Clock Enable 3 3V LVTTL Two copies of an SDRAM clock allows in some cases glueless MemClkOut0 1 SDRAM attach without requiring this signal to be repowered by a 3 3V LVTTL PLL or zero delay buffer External Slave Peripheral Interface Peripheral data bus used by PPC405GPr when not in external 5V tol PerData0 31 master mode otherwise used by external master VO a 1 Note PerData0 is the most significant msb on this bus Peripheral address bus used by PPC405GPr when not in external 5V tol t PerAddr0 31 master mode otherwise used by external master SUCI 1 Note is the most significant bit msb on this bus T 5V tolerant PerPar0 3 Peripheral byte parity signals 3 3V LVTTL 1 As outputs these pins can act as byte enables which are valid for an entire cycle or as write byte enables which are valid for each byte on each data transfer allowing partial word transactions As 5V tolerant PerWBE0 3 outputs pins are used by either the pripheral controller or the y o 3 3V LVTTL 1 7 DMA controller depending upon the type of transfer involved
17. On Chip Memory Controller Registers 0x018 0x01F 8w Reserved 0x020 0x07F 96W PLB Registers 0x080 0x08F 16W Reserved 0x090 0x09F 16W OPB Bridge Out Registers 0 0 0 0 7 8W Electronic Chip ID ECID 0x0A8 0x0A9 2W Reserved OxOAF ew Clock Control Interrupt Routing and Reset 0x0BO 0x0B7 8W Power Management 0 0 8 OxOBF 8W Interrupt Controller 0x0CO OxOCF 16W Reserved 0 000 OxOFF 48W DMA Controller Registers 0x100 0x13F 64W Reserved 0x140 0x17F 64W Ethernet MAL Registers 0x180 0x1 128W Reserved 0x200 Ox3FF 512W Notes 1 DCR address space is addressable with up to 10 bits 1024 or 1K unique addresses Each unique address represents a single 32 bit word register or 1 kiloword KW which equals 4 KB Preliminary PowerPC 405GPr Embedded Processor Data Sheet On Chip Memory OCM The OCM feature comprises a memory controller and a one port 4KB static RAM SRAM accessed by the processor core Features include e Low latency access to critical instructions and data Performance identical to cache hits without misses Contents change only under program control PLB to PCI Interface The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory This interface is compliant with version 2 2 of the PCI Specification Features include Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66 MHz Internal arbiter use
18. SDRAM command interface is configurable through SDRAMO TR LDF to provide 2 to 4 cycle delay before the command is used by SDRAM 2 SDRAM I O timings are specified relative to MemClkOut terminated into a lumped 10pF load 3 SDRAM interface hold times are guaranteed at the PPC405GPr package pin System designers must use the PPC405GPr IBIS model available from www chips ibm com to ensure their clock distribution topology minimizes loading and reflections and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring PerClk timing is specified with a 10pF load at the package pin Input timings are specified at 1 5V assuming transition times between 1 and 2ns when measured between the 10 and 90 points of the output voltage 6 I O H is specified at 2 4 V and I O L is specified at 0 4 V gt Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOH VOL Clock Notes min minimum minimum External Master Peripheral Interface BusReq na na 6 1 2 2 10 3 7 1 PerClk 5 ExtAck na na 5 9 2 1 10 3 7 1 PerClk 5 ExtReq 41 0 PerClk 5 ExtReset na na 6 1 15 3 10 2 PerClk 5 HoldAck na na 6 1 2 10 3 7 1 PerClk 5 HoldPri 2 1 0 na na na na PerClk 5 HoldReq 3 1 0 na na na na PerClk 5 PerClk na na 0 6 0 8 15 3 10 2 SysClk 4 5 PerErr 2 4 0 na na na
19. TMS AC22 JTAG 35 TRST AE26 JTAG 35 TS1E GPIO1 D18 TS2E GPIO2 C20 TS1O GPIOS A22 TS2O GPIO4 AF18 TSS GPIO5 AC9 System 35 TS4 GPIO6 AE8 TS5 GPIO7 AF5 TS6 GPIO8 7 TrcClk GPIO9 AB3 UARTO_CTS AB4 Internal Peripheral 34 UARTO DCD AE18 nternal Peripheral 34 UARTO DSR AE3 Internal Peripheral 34 UARTO DTR AF2 Internal Peripheral 34 UARTO RI AD15 Peripheral 34 UARTO RTS AD16 Peripheral 34 UARTO Rx AE16 nternal Peripheral 34 UARTO Tx AF3 Internal Peripheral 34 UART1 CTS UART1 DSR Internal Peripheral 34 UART1 DSR UART1 CTS Internal Peripheral 34 UART1 DTR UART1 RTS AD2 Internal Peripheral 34 UART1 RTS UART1 DTR AD2 Internal Peripheral 34 UART1 Rx AC1 Internal Peripheral 34 UART1 Tx AC2 Internal Peripheral 34 UARTSerCIk AE17 nternal Peripheral 34 23 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 10 of 10 Signal Name Ball Interface Group Page E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 Vpp pes Logic voltage 37 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 WE AC16 SDRAM 32 24 PowerPC 405GPr Embedded Processor Data Sheet Signals Listed by Ball Assignment Part 1 of 3 Preliminary Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name 1 GND B14
20. addressing modes are programmable Features include 11x8 to 13x11 addressing for SDRAM 2 and 4 bank 32 bit memory interface support Programmable address compare for each bank of memory Industry standard 168 pin DIMMS are supported some configurations Both 266 and 333 MHz PPC405GPrs support up to 133 MHz memory with PC 133 support 4MB to 256MB per bank Programmable address mapping and timing Auto refresh Page mode accesses with up to 4 open pages Power management self refresh Error checking and correction ECC support Standard single error correct double error detect coverage Aligned nibble error detect Address error logging External Peripheral Bus Controller EBC Supports eight banks of ROM EPROM SRAM Flash memory or slave peripherals Upto 66MHz operation Burst and non burst devices 8 16 32 bit byte addressable data bus width support Latch data on Reagy synchronous or asynchronous Preliminary PowerPC 405GPr Embedded Processor Data Sheet Programmable 2K clock time out counter with disable for Ready Programmable access timing per device 0 255 wait states for non bursting devices 0 31 burst wait states for first access and up to 7 wait states for subsequent accesses Programmable CSon CSoff relative to address Programmable OEon WEon WEoff 0 to 3 clock cycles relative to CS Programmable address mapping Peripheral Device pacing with external R
21. functi like th oe Legacy PPC405GP mode 0 If not strapped the PPC405GPr defaults to New PPC405GPr mode 1 Legacy mode Manufacturing Test Disable AB3 must be strapped low 0 GPIO9 TrcCIk during initilization Normal operation 0 Note 1 The tune bits adjust parameters that control PLL jitter The recommended values minimize jitter for the PLL implemented in the PPC405GPr These bits are shown for information only and do not require modification except in special clocking circumstances such as spread spectrum clocking For details on the use of Spread Spectrum Clock Generators SSCGs with the PPC405GPr visit the technical documents area of the IBM PowerPC web site 2 Not all combinations of dividers produce valid operating configurations Frequencies must be within the limits specified in Clocking Specifications on page 42 Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor User s Manual 3 Additional consideration must be given to pins that normally function as Trace signals Improved design margin can be gained by using tri state buffers instead of strapping resistors and minimizing trace lengths and stubs 4 The pull up initialization strapping resistor must be 1 rather than in order to overcome the internal pull down resistor 5 Preliminary 56 9 PowerPC 405GPr Embedded Processor Data Sheet c Copyright Inte
22. must hold this pin low 0 during reset Ground pins Ground GND Note L11 L16 M11 M16 N11 N16 P11 P16 R11 R16 and T11 T16 are also thermal balls OVpp pins OVpp Output driver voltage 3 3V pins Vpp Logic voltage 1 8V Other pins Reserved Reserved Except for AF4 do not connect signals voltage or 37 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only Operation at or beyond these maximum ratings can cause permanent damage to the device Characteristic Symbol Value Unit Supply Voltage Internal Logic Vpp 0 to 41 95 V Supply Voltage I O Interface OVpp 0 to 3 6 V PLL Supply Voltage AVpp 0 to 1 95 V Input Voltage 1 8 V CMOS receivers ViN 0 6 to Vpp 0 45 V Input Voltage 3 3V LVTTL receivers ViN 0 6 to OVpp 0 6 V Input Voltage 5 0 V LVTTL receivers ViN 0 6 to OVpp 2 4 V Storage Temperature Range Tera 55 to 4150 Case temperature under bias 40 10 120 Note All specified voltages are with respect to GND Package Thermal Specifications The PPC405GPr is designed to operate within a case temperature range of 40 C to 85 C Thermal resistance values for the E PBGA packages in a convection environment are as follows Airflow Package Thermal Resistance Symbol ft min m sec Unit 0 0 100 0 51 200 1 02 35mm
23. system 43 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Peripheral Interface Clock Timings Parameter Min Max Units input frequency asynchronous mode Note 1 66 66 MHz period asynchronous mode 15 Note 1 ns PCI Clock frequency synchronous mode 25 33 33 MHz PCI Clock period synchronous mode Note 2 30 40 ns input high time 40 of nominal period 60 of nominal period ns input low time 40 of nominal period 60 of nominal period ns output frequency 2 5 2 400 ns output high time 160 ns output low time 160 ns input frequency 2 5 25 MHz period 40 400 ns input high time 35 of nominal period ns input low time 35 of nominal period ns input frequency 2 5 25 MHz PHYRXxCIk period 40 400 ns input high time 35 of nominal period ns input low time 35 of nominal period ns PerClk output frequency 66 66 2 PerClk period 15 ns PerClk output high time 45 of nominal period 55 of nominal period ns PerClk output low time 45 of nominal period 55 of nominal period ns PerClk clock edge stability phase jitter cycle to cycle 0 3 ns UARTSerCIk input frequency Not
24. the figures at right Pin 10pF 250 PCI Rising edge a Output W o OVpp Pin 250 Falling edge 41 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Clocking Specifications Symbol Parameter Min Max Units CPU Processor clock frequency 266 66 or 333 33 MHz Processor clock period 3 75 or 3 00 ns SysClk Input SCFc Clock input frequency 25 66 66 MHz SCTc Clock period 15 40 ns SCTos Clock edge stability phase jitter cycle to cycle 0 15 ns 5 Clock input high time 40 of nominal period 60 of nominal period ns SCToL Clock input low time 40 of nominal period 60 of nominal period ns Note Input slew rate gt 2V ns MemClkOut Output MCOFgc Clock output frequency 266MHz 133 33 MHz MCOT Clock period 266MHz 75 ns Clock edge stability phase jitter cycle to cycle 0 2 ns Clock output high time 45 of nominal period 5596 of nominal period ns MCOTc Clock output low time 45 of nominal period 55 of nominal period ns TrcCIk Output Clock output frequency 2 MHz Clock period 2 ns 5 Clock edge stability phase jitter cycle to cycle 0 2 ns Clock output high time 45 of nominal period ns Clock output low time 45 of nominal period ns Other Clocks VCOFc VCO frequency
25. 0 PCISErr G24 PCI 30 PCIStop H23 PCI 30 PCITRDY G26 PCI 30 20 PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 7 of 10 Preliminary Signal Name Ball Interface Group Page 05 PerAddr1 A3 PerAddr2 B4 PerAddr3 5 PerAddr4 D6 PerAddr5 B6 PerAddr6 C6 PerAddr7 D7 PerAddr8 A5 PerAddr9 B7 PerAddr10 C7 PerAddr11 D8 PerAddr12 B8 PerAddr13 C8 PerAddr14 D9 ae External SLAVE Peripheral 32 PerAddr17 D10 PerAddr18 C10 PerAddr19 A10 PerAddr20 011 PerAddr21 B12 PerAddr22 D13 PerAddr23 12 PerAddr24 B13 PerAddr25 12 PerAddr26 A13 PerAddr27 C14 PerAddr28 14 PerAddr29 A15 PerAddr30 C15 PerAddr31 D15 PerBLast F2 External SLAVE Peripheral 32 PerClk E4 External MASTER Peripheral 34 50 B3 PerCS1 GPIO10 C4 PerCS2 GPIO11 C5 ec External SLAVE Peripheral 32 PerCS5 GPIO14 B10 PerCS6 GPIO15 AQ PerCS7 GPIO16 B11 21 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 8 of 10 Signal Name Ball Interface Group Page U4 PerData1 U3 PerData2 U1 PerData3 T4 PerData4 R2 5 4 PerData6 R4 PerData7 P2 PerData8 R1 PerData9 P1 PerData10 N3 PerData11 N1 PerData12 M1 PerData13 N2 PerData14 M3 PerData15 M4 PerData16 4 External SLAVE Peripheral 32 PerData1
26. 00 OxE800FFFF 64KB PCI I O 0 8800000 56 Configuration Registers 0 00007 8 Interrupt Acknowledge and Special Cycle 0 00000 OxEEDO00003 4B Local Configuration Registers OxEF400000 OxEF40003F 64B UARTO OxEF600300 OxEF600307 8B UART1 OxEF600400 OxEF600407 8B OxEF600500 OxEF60051F 32B Internal Peripherals Arbiter OxEF600600 OxEF60063F 64B GPIO Controller Registers OxEF600700 OxEF60077F 128B Ethernet Controller Registers OxEF600800 OxEF6008FF 256B Notes 1 When peripheral bus boot is selected peripheral bank 0 is automatically configured at reset to the address range listed above If PCI boot is selected a PLB to PCI mapping is automatically configured at reset to the address range listed above 2 3 After the boot process software may reassign the boot memory regions for other uses 4 All address ranges not listed above are reserved PowerPC 405GPr Embedded Processor Data Sheet DCR Address Map 4 Device Configuration Registers Preliminary Function Start Address End Address Size Total DCR Address Space 0x000 Ox3FF 1KW 4 By function Reserved 0x000 0 00 16W Memory Controller Registers 0x010 0x011 2W External Bus Controller Registers 0x012 0x013 2W Decompression Controller Registers 0x014 0x015 2W Reserved 0x016 0x017 2W
27. 00000000000000 00000 Mold 00000 00000 v u Thermal Balls 9o 399 Compound T 00000 000000 00000 R 00000 35 0 0 2 N 00000 M 00000 000000 60000 PCB 00000 r K 00000 Substrate J H 0000 00000000000000000000000000 00000000000000000000000000 B 1 3 5 7 9 11 13 15 17 19 21 23 25 0 6 0 1 2 4 6 8 10 12 14 16 18 20 22 24 26 2 49 0 65 0 05 SOLDERBALL x 456 2 65 h 20 309 B V 0 15S C 14 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Pin Lists The PPC405GPr embedded controller is available as a 456 ball E PBGA package The 456 ball package is available in two sizes 35 millimeters and 27 millimeters In this section there are two tables that correlate the external signals to the physical package pin ball on which they appear The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears M
28. 19 PCIReq0 Gnt E6 OVpp G25 PCIPErr B7 PerAddr9 C20 GPIO2 TS2E E7 OVpp G26 PCITRDY B8 PerAddr12 C21 PCIReqt E8 OVpp H1 GND B9 54 0 13 C22 PCIAD13 E9 GND H2 PerData30 B10 PerCS5 GPIO14 C23 PCIINT PerWE E10 Vpp H3 PerData28 B11 PerCS7 GPIO16 C24 GND E11 Vpp H4 PerData31 B12 PerAddr21 C25 Reserved E12 Vpp H5 OVpp B13 PerAddr24 C26 PCIAD14 E13 GND H22 OVpp 25 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed by Ball Assignment Part 2 of 3 Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name 23 PCIStop M1 PerData12 P14 GND U1 PerData2 H24 2 PerData17 P15 GND U2 HoldAck H25 PCIDevSel M3 PerData14 P16 GND U3 PerData1 H26 PCIGnt3 M4 PerData15 P22 GND U4 PerDataO J1 PerData23 M5 Vpp P23 PCIAD26 U5 Vpp J2 PerData26 M11 GND P24 PCIAD23 U22 Vpp J3 PerData25 M12 GND P25 EMCTxD3 U23 PCIGntO Req PerData27 M13 GND P26 PCIIDSel U24 PHYRxErr J5 GND M14 GND R1 PerData8 U25 OVpp J22 GND M15 GND R2 PerData4 U26 PCIAD29 J23 PCIIRDY M16 GND R3 BusReq V1 HoldReq J24 22 Vpp R4 PerData6 v2 EOT2 TC2 J25 PCIReq5 M23 PCIAD19 R5 Vpp MemData31 J26 EMCTxDO M24 PCIGnt5 R11 GND V4 MemData29 K1 PerData20 M25 PCIAD18 R12 GND V5 GND K2 26 PCIAD21 R13 GND V22 GND K3 PerData22 1
29. 456 balls Junction to Case 2 2 2 C W 35mm 456 balls Case to Ambient Oca 14 13 12 C W 27 456 balls Junction to Case 2 2 2 C W 27mm 456 balls Case to Ambient Oca 18 16 15 C W Note 1 Fora chip mounted on 282P card without a heat sink 2 For a chip mounted on a card with at least one signal and two power planes the following relationships exist a Case temperature is measured at top center of case surface with device soldered to circuit board b PXO ca where TA is ambient temperature and P is power consumption C Tomax where is maximum junction temperature and P is power consumption 38 E 7 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended Extended operation beyond the recommended conditions can affect device reliability Notes 1 PCI drivers meet PCI specifications Parameter Symbol Minimum Typical Maximum Unit Notes Logic Supply Voltage Vpp 1 65 1 8 1 95 V Supply Voltage OVpp 3 0 3 3 3 6 V PLL Supply Voltage AVpp 1 65 1 8 1 95 V Input Logic High 1 8V CMOS receivers 0 65 Voo Input Logic High 3 3V LVTTL receivers 0 OVDp y Input Logic High 5 0V LVTTL receivers 20 P y I
30. 5 EMCTxEn K23 Ethernet 31 EMCTxErr K25 Ethernet 31 EOTO TCO F3 EOT1 TC1 G2 EOT2 TC2 V2 EOT3 TC3 Y1 ExtAck External MASTER Peripheral 34 ExtReq Y4 External MASTER Peripheral 34 ExtReset T3 External MASTER Peripheral 34 Ethernet 31 External SLAVE Peripheral 32 F1 Ground F26 Notes GND H1 1 L11 L16 M11 M16 N11 N16 P11 P16 R11 R16 and T11 T16 are also 37 thermal balls L11 L16 L26 M11 M16 N5 N11 N16 N22 P5 P11 P16 P22 R11 R16 Ti T11 T16 T26 V5 v22 W26 1 26 5 16 PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 3 of 10 Preliminary Signal Name Ball Interface Group Page 9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 Ground AD24 Notes GND A 1 L11 L16 M11 M16 N11 N16 P11 P16 R11 R16 and T11 T16 are also 37 AE25 thermal balls AF1 AF6 AF8 AF11 AF16 AF21 AF25 AF26 Gnt PCIReqO C19 PCI 30 GPIO1 TS1E D18 GPIO2 TS2E C20 GPIO3 TS10 A22 GPIO4 TS20 AF18 GPIOS TSS AC9 System 35 GPIO6 TS4 AE8 GPIO7 TS5 AF5 GPIO8 TS6 AC7 GPIO9 TrcClk AB3 GPIO10 PerCS1 C4 GPIO11 PerCS2 C5 GPIO12 PerCS3 A4 GPIO13 PerCS4 B9 System 35 GPIO14 PerCS5 B10 GPIO15 PerCS6 A9 GPIO16 PerCS7 B11 GPIO17 IRQO V25 GPIO18 IRQ1 V23 GPIO19 IRQ2 W24 GPIO20 IRQS3 W25 GPIO21 IRQ4 24 System 35 GPIO22 IRQ5 Y25 GPIO23 IRQ6 AA24 GPIO24 D20
31. 7 M2 PerData18 L3 PerData19 L4 PerData20 K1 PerData21 L2 PerData22 K3 PerData23 J1 PerData24 4 PerData25 J3 PerData26 J2 PerData27 J4 PerData28 H3 PerData29 G1 PerData30 H2 PerData31 H4 PerErr B1 External MASTER Peripheral 34 PerOE C2 External SLAVE Peripheral 32 D3 PerPar1 G4 PerPar2 G3 External SLAVE Peripheral 32 PerPar3 E1 PerReady E3 External SLAVE Peripheral 32 PerR W C1 External SLAVE Peripheral 32 PerWBEO D2 PerWBE1 E2 PerWBE2 F4 External SLAVE Peripheral 32 PerWBE3 D1 PerWE PCIINT C23 External SLAVE Peripheral 32 PHYCol AA25 Ethernet 31 PHYCrS W23 Ethernet 31 PHYRxClk AF20 Ethernet 31 PHYMDIO EMCMDIO AD26 31 PHYRxDO AE23 PHYRxD1 AF23 PHYRxD2 20 Ethernet 3 PHYRxD3 AD20 PHYRxDV V24 Ethernet 31 PHYRxErr U24 Ethernet 31 E25 Ethernet 31 RAS AF24 SDRAM 32 22 E 7 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 9 of 10 Signal Name Ball Interface Group Page C25 E23 Other E24 Notes Reserved Y23 37 26 1 AF4 must be tied to OVpp or GND All other reserved pins should be left unconnected Req PCIGnt0 U23 30 SysClk A25 System 35 SysErr AD25 System 35 SysReset D22 System 35 TCK AD22 JTAG 35 TDI AE24 JTAG 35 TDO AD23 JTAG 35 TestEn D26 System 35 TmrClk D24 System 35
32. AE14 ECCO AF23 PHYRxD1 AB23 CAS AD6 IICSCL AE15 BankSel2 AF24 RAS AB24 BAO AD7 MemData13 AE16 UARTO_Rx AF25 GND AB25 0 AD8 MemData10 AE17 UARTSerClk AF26 GND 27 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal List The table following table provides a summary of the number of package pins associated with each functional interface group Pin Summary Group No of Pins PCI 60 Ethernet 18 SDRAM 71 External peripheral 96 External master 9 Internal peripheral 15 Interrupts 7 JTAG 5 System 18 Total Signal Pins 299 OVpp 32 Vpp 24 Gnd 59 Thermal and Gnd 36 Reserved 6 Total Pins 456 Multiplexed Pins In the table Signal Functional Description on page 30 each external signal is listed along with a short description of the signal function Some signals are multiplexed on the same package pin ball so that the pin can be used for different functions Multiplexed signals are shown as a default signal with a secondary signal in square brackets for example GPIO1 TS1E Active low signals for example RAS are marked with an overline It is expected that in any single application a particular pin will always be programmed to serve the same function The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible In addition to multiplexing many pins are al
33. DMAAck2 01 PerWBE3 E14 GND A2 GND B15 DMAAck1 D2 PerWBEO E15 Vpp A3 PerAddr1 B16 PCIAD1 D3 16 Vpp A4 PerCS3 GPIO12 B17 OVpp D4 GND E17 Vpp A5 PerAddr8 B18 PCIAD6 D5 E18 GND GND B19 PCIReq2 D6 PerAddr4 E19 OVpp A7 DMAReq3 B20 7 PerAddr7 E20 OVpp A8 PerAddr15 B21 PCIAD8 D8 PerAddr11 E21 OVpp A9 PerCS6 GPIO15 B22 PCIAD11 D9 PerAddr14 E22 AGND A10 PerAddr19 B23 PCIAD12 D10 PerAddr17 E23 Reserved 11 GND B24 PCIReset D11 PerAddr20 E24 Reserved A12 PerAddr25 B25 GND D12 PerAddr23 E25 PHYTxClk A13 PerAddr26 B26 GND 013 PerAddr22 E26 PCIParity A14 PerAddr28 C1 PerR W D14 DMAReq1 1 GND A15 PerAddr29 C2 PerOE D15 PerAddr31 F2 PerBLast A16 GND C3 GND D16 DMAAckO F3 EOTO TCO 17 PCIADO C4 PerCS1 GPIO10 D17 PCIAD4 F4 PerWBE2 A18 PCIAD3 C5 PerCS2 GPIO 1 1 D18 GPIO1 TS1E F5 OVpp A19 GND C6 019 PCICO BEO F22 OVpp A20 PCIAD7 C7 PerAddr10 D20 GPIO24 F23 PCIGnt2 21 GND C8 PerAddr13 D21 PCIAD10 F24 PCIC1 BE1 A22 GPIO3 TS10 C9 PerAddr16 D22 SysReset F25 PCIAD15 A23 PCIAD9 C10 PerAddr18 D23 GND F26 GND A24 PCIReq3 C11 DMAReq2 D24 TmrClk G1 PerData29 A25 SysClk C12 DMAAck3 D25 AVpp G2 1 1 26 GND C13 OVpp D26 TestEn G3 PerPar2 B1 PerErr C14 PerAddr27 E1 PerPar3 G4 PerPar1 B2 GND C15 PerAddr30 E2 PerWBE1 G5 OVpp B3 50 16 0 PerReady G22 OVpp B4 PerAddr2 C17 PCIAD2 E4 PerClk G23 PCIReq4 B5 PerAddr3 C18 5 5 G24 PCISErr B6 PerAddr5 C
34. Halt AB26 System 35 HoldAck U2 External MASTER Peripheral 34 HoldPri T2 External MASTER Peripheral 34 HoldReq V1 External MASTER Peripheral 34 IICSCL AD6 Internal Peripheral 34 IICSDA Peripheral 34 IRQO GPIO17 V25 IRQ1 GPIO18 V23 IRQ2 GPIO 19 W24 IRQS GPIO20 W25 Interrupts 35 IRQ4 GPIO21 Y24 IRQ5 GPIO22 Y25 IRQ6 GPIO23 AA24 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 4 of 10 Signal Name Ball Interface Group Page 22 1 21 2 21 021 4 22 MemAddr 19 SDRAM 32 ui AE19 Note During a CAS cycle MemAddr0 is the least significant bit Isb on this bus 019 9 18 10 AF19 MemAdar1 1 AD18 MemAdar12 AC17 MemClIkOutO AC26 MemClkOutt 23 SDRAM 35 MemDataO AC13 MemData1 AE12 MemData2 AD11 MemData3 AC11 MemData4 AF10 MembData5 AE11 MembData6 AD10 MemData7 AF9 MemData8 AD9 MembData9 AE9 MemData10 AD8 MembData1 1 AF7 MemData12 AC8 MemData13 AD7 MemData14 AE6 MemData15 AE5 SDRAM 32 MemData16 AE4 Note MemData0 is the most significant bit msb on this bus MemData17 AD5 MemData18 AD4 MemData19 AC5 MemData20 AD1 MemData21 AB2 MemData22 AA4 MemData23 AA2 MemData24 AB1 MemData25 Y2 MemData26 WA MemData27 2 MemData28 W3 MemData29 V4 MemData30 W1 MemData31 V3 18
35. LVTTL 7 bus master it enables the selected device to drive the bus Used by the PPC405GPr when not in external master mode as output by either the peripheral controller or DMA controller PerBAW depending upon the type of transfer involved High indicates a vo 5V tolerant 1 read from memory low indicates a write to memory 3 3V LVTTL Otherwise it used by the external master as an input to indicate the direction of transfer PerReady Used by a peripheral slave to indicate it is ready to transfer data AL 1 Used by the PPC405GPr when not in external master mode 5V tolerant PerBLast otherwise used by external master Indicates the last transfer ofa UA 3 3V LVTTL memory access DMAReq0 3 are used by slave peripherals to indicate they are 5V tolerant prepared to transfer data 3 3V LVTTL i DMAAckO 3 are used by the PPC405GPr to cause the DMA 5V tolerant MANUS peripheral to transfer data 9 3 3V LVTTL 8 0 3 0 3 End Of Transfer Terminal Count 2 21 1 33 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 5 of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull
36. Multipurpose signal used as PCIReq0 when internal arbiter is 5V tolerant uc used and as Gnt when external arbiter is used 3 3V PCI 30 PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 2 of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Preliminary Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values 4 not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description yo Type Notes PCIReq1 5 Used as PCIReq1 5 input when internal arbiter is used Gnt0 when internal arbiter is used PCIGntO Req 3 3V Req when external arbiter is used PCIGnt1 5 Used as PCIGnt1 5 output when internal arbiter is used phis Ethernet Interface PHYRxD3 0 Received data This is a nibble wide bus from the PHY The data 5V tolerant 1 9 is synchronous with the PHYRxClk 3 3V LVTTL Transmit data A nibble wide data bus towards the net The data 5V tolerant 0 is synchronous to the
37. Preliminary PowerPC 405GPr Embedded Processor Data Sheet Features IBM PowerPC 405 32 bit RISC processor core operating up to 333MHz with larger 16KB D cache PC 133 synchronous DRAM SDRAM interface 32 bit interface for non ECC applications 40 bit interface serves 32 bits of data plus 8 check bits for ECC applications 4KB on chip memory External peripheral bus Flash ROM Boot ROM interface Direct support for 8 16 or 32 bit SRAM and external peripherals Upto eight devices External Mastering supported DMA support for external peripherals internal UART and memory Scatter gather chaining supported Four channels PCI Revision 2 2 compliant interface 32 bit up to 66 2 Description Designed specifically to address embedded applications the PowerPC 405GPr PPC405GPr provides a high performance low power solution that interfaces to a wide range of peripherals by incorporating on chip power management features and lower power dissipation requirements This chip contains a high performance RISC processor core SDRAM controller PCI bus interface Ethernet interface control for external ROM and peripherals DMA with scatter gather Synchronous or asynchronous PCI Bus interface Use internal or external PCI Bus Arbiter Ethernet 10 100Mbps full duplex support with media independent interface MIl Programmable interrupt controller supports 13 exte
38. Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 5 of 10 Signal Name Ball Interface Group Page B17 C13 E6 E7 E8 E19 E20 E21 F5 F22 G5 G22 H5 H22 K2 OVpp E Output driver voltage 37 U25 W5 W22 Y5 Y22 AA5 AA22 AB6 AB7 AB8 AB19 AB20 21 AD14 AE10 PCIADO A17 PCIAD1 B16 PCIAD2 C17 PCIAD3 A18 PCIAD4 D17 PCIAD5 C18 PCIAD6 B18 PCIAD7 A20 PCIAD8 B21 PCIAD9 A23 PCIAD10 D21 PCIAD1 1 B22 PCIAD12 B23 PCIAD13 C22 PCIAD14 C26 PCIAD15 F25 PCI 30 PCIAD16 K26 Note PCIAD31 is the most significant bit msb on this bus PCIAD17 L23 PCIAD18 M25 PCIAD19 M23 PCIAD20 N25 PCIAD21 M26 PCIAD22 N26 PCIAD23 P24 PCIAD24 R24 PCIAD25 R23 PCIAD26 P23 PCIAD27 R25 PCIAD28 T24 PCIAD29 U26 PCIAD30 T25 PCIAD31 V26 19 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 6 of 10 Signal Name Ball Interface Group Page PCICO BEO D19 PCIC1 BE1 F24 PCIC2 BE2 PCI 30 PCIC3 BE3 R26 PCICIk B20 30 PCIDevSel H25 PCI 30 J24 30 PCIGntO Reg U23 PCIGnt1 T23 PCIGnt2 F23 PCIGnt3 H26 FC 39 PCIGnt4 N23 PCIGnt5 M24 PCIIDSel P26 PCI 30 PCIINT PerWE C23 PCI 30 PCIIRDY J23 30 PCIParity E26 PCI 30 PCIPErr G25 PCI 30 PCIReaO Gnt C19 PCIReg1 C21 PCIReg2 B19 PCIReq3 a24 20 PCIReq4 G23 PCIReq5 J25 PCIReset B24 PCI 3
39. Up and Pull Down Resistors on page 29 for recommended termination values 4 not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description 1 0 Type Notes External Master Peripheral Interface PerCik Peripheral clock to be used by an external master and by o 5V tolerant synchronous peripheral slaves 3 3V LVTTL ExtReset Peripheral reset to be used by an external master and by 5V tolerant synchronous peripheral slaves 3 3V LVTTL HoldRe Hold Request used by an external master to request ownership 5V tolerant 15 9 of the peripheral bus 3 3V LVTTL HoldAck Hold Acknowledge used by the PPC405GPr to transfer 5V tolerant 6 ownership of peripheral bus to an external master 3 3V LVTTL BxiRea ExtReq is used by an external master to indicate it is prepared to 5V tolerant 1 9 transfer data 3 3V LVTTL ExtAck is used by the 405 to indicate a data transfer 5V tolerant EXtACK cycle O 33V LVTTL 8 HoldPri Used by an external master to indicate the priority of a given 5V tolerant 1 external master tenure 3 3V LVTTL BusRe Used when the PPC405GPr needs to regain control of peripheral 5V tolerant q interface from an external Master 3 3V LVTTL PerErr An input used to indicate to the PPC405GPr that an external 5V tolerant 15 slave peripheral error occurred 3 3V LVTTL Intern
40. al Peripheral Interface Serial Clock used to provide an alternate clock to the internally UARTSerCIk generated serial clock Used in cases where the allowable 5V tolerant 1 internally generated baud rates are not satisfactory This input 3 3V LVTTL can be individually connected to either UART 2 5V tolerant UARTO_Rx UARTO Serial Data In 3 3V LVTTL 1 5V tolerant UARTO Tx UARTO Serial Data Out 3 3V LVTTL 6 UARTO DCD UARTO Data Carrier Detect V tol rant 1 3 3V LVTTL _ 5V tolerant UARTO_DSR UARTO Data Set Ready 3 3V LVTTL 1 c 5V tolerant UARTO CTS UARTO Clear To Send 3 3V LVTTL 1 UARTO DTR UARTO Data Terminal Read E 6 3 3V LVTTL UARTO_RTS UARTO Request To Send o tolerant 6 3 3V LVTTL 5V tolerant UARTO RI UARTO Ring Indicator 3 3V LVTTL 1 34 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 6 of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis Must pull up See Pull Up and Pull Down Resistors page 29 for recommended termination values Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values If not used must pull down Strapping input during reset pull up or pull down as required 2 3 4 not used must pull up 5 6 7 Pull up may be req
41. at 0 4 V Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time VOH VOL Clock Notes min min minimum minimum SDRAM Interface BA1 0 na na 4 5 1 6 15 3 10 2 MemClkOut 1 2 5 BankSel3 0 na na 4 5 1 5 15 3 10 2 MemClkOut 2 5 CAS na na 4 4 1 5 15 3 10 2 MemClkOut 1 2 5 ClkEn0 1 na na 3 9 1 4 23 19 3 MemClkOut 2 5 DQM0 3 na na 4 5 1 4 15 3 10 2 MemClkOut 2 5 DQMCB na na 4 3 1 4 15 3 10 2 2 5 0 7 1 4 0 4 5 1 5 15 3 10 2 MemClkOut 2 5 MemAdar1 2 0 na na 4 6 1 5 15 3 10 2 MemClkOut 1 2 5 MemData0 31 1 4 0 5 1 1 4 15 3 10 2 MemClkOut 2 5 4 4 1 5 15 3 10 2 1 2 5 WE na na 4 4 1 5 15 3 10 2 MemClkOut 1 2 5 External Slave Peripheral Interface DMAAckO 3 na na 6 1 2 2 10 3 7A PerClk 5 DMAReq0 3 3 2 0 na na na na PerClk 5 EOTO 3 TCO 3 dc dc 6 4 2 10 3 7 1 PerClk 5 PerAddr0 31 2 2 0 7 1 2 15 3 10 2 PerClk 5 PerBLast 3 3 0 6 5 2 3 10 3 7A PerClk 5 T na na 6 5 24 10 3 71 PerClk 5 PerData0 31 4 7 0 9 7 2 1 9 15 3 10 2 PerClk 5 PerOE na na 6 5 2 1 10 3 7 1 PerClk 5 PerPar0 3 2 3 0 7 2 2 1 15 3 10 2 PerClk 5 PerR W 3 3 0 6 6 2 1 10 3 7 1 PerClk 5 PerReady 5 5 0 na na na na PerClk 5 PerWBE0 3 2 3 0 6 1 2 2 10 3 7 1 PerClk 5 49 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Specifications Group 2 Part 2 of 2 Notes 1 The
42. ata2 AE20 5 4 MemData22 AC3 UABTLCTS AD12 ECC7 21 MemAddr2 AAS OVpp AC4 GND AD13 ECC3 AE22 22 OVpp AC5 MemData19 AD14 OVpp AE23 PHYRxDO AA23 MemClkOut1 AC6 DQM2 AD15 UARTO_RI AE24 TDI AA24 IRQ6 GPIO23 AC7 GPIO8 TS6 AD16 UARTO RTS AE25 GND AA25 PHYCol AC8 MemData12 AD17 BankSel0 AE26 TRST AA26 GND 9 GPIO5 TS3 AD18 MemAddr1 1 AF1 GND AB1 MemData24 AC10 DQM1 AD19 8 2 UARTO_DTR AB2 MemData21 AC11 MemData3 AD20 PHYRxD3 AF3 UARTO_Tx AB3 GPIO9 TrcClk AC12 DQMO AD21 MemAddr3 AF4 Reserved AB4 5 AC13 AD22 TCK AF5 GPIO7 TS5 5 GND AC14 BankSel3 AD23 TDO AF6 GND AB6 OVpp AC15 DQMCB AD24 GND AF7 MemData1 1 AB7 OVpp AC16 WE AD25 SysErr AF8 GND AB8 17 MemAddr12 AD26 9 MemData7 AB9 GND AC18 MemAdar9 AE1 GND AF10 MemData4 AB10 Vpp AC19 GND AF11 GND 11 Vpp AC20 PHYRxD2 UARTO DSR AF12 ECC5 AB12 Vpp 21 1 4 16 1 AB13 GND AC22 TMS 5 MemData15 AF14 ECC2 AB14 GND AC23 GND AE6 MemData14 AF15 15 Vpp AC24 BA1 AE7 IICSDA AF16 GND AB16 Vpp AC25 CIkEn1 AE8 GPIO6 TS4 AF17 BankSelt AB17 Vpp AC26 MemClkOutO AE9 MemData9 AF18 GPIO4 TS20 AB18 GND AD1 MemData20 AE10 19 MemAddr10 AB19 OVpp AD2 11 MemData5 AF20 20 OVpp AD3 GND AE12 MemDatat AF21 GND AB21 OVpp AD4 MemData18 AE13 ECC6 AF22 MemAddr4 AB22 GND AD5 MemData17
43. brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values 4 lf not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description yo Type Notes PCI Interface PCIAD31 0 PCI Address Data Bus Multiplexed address and data bus aca BEAR 5V tolerant PCIC3 0 BE3 0 PCI bus command and byte enables 3 3V PCI parity Parity is even across PCIADO 31 and PCICO 3 BEO 3 PCIParit PCIParity is valid one cycle after either an address or data phase UO 5V tolerant y The PCI device that drove PCIADO 31 is responsible for driving 3 3V PCI PCIParity on the next PCI bus clock PClIFrame is driven by the current PCI bus master to indicate the 5V tolerant beginning and duration of a PCI access vO 3 3V 2 PCIIRDY PCIIRDY is driven by the current PCI bus master Assertion of o 5V tolerant 2 PCIIRDY indicates that the PCI initiator is ready to transfer data 3 3V PCI The target of the current PCI transaction drives PCITRDY 5V tolerant PCITRDY As
44. ck Management Data Input Output is a bidirectional signal between 5V tolerant EMCMDIO PHYMDIO the Ethernet controller and the PHY It is used to transfer control y o 3 3V LVTTL 1 and status information 31 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values 4 not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description 1 0 Type Notes E E SDRAM Interface Memory data bus Notes MemD 31 3 3V LVTTL empatao 3 1 is the most significant bit 2 MemData31 is the least significant bit Isb Memory address bus Notes LVTTL 1 MemAddr12 is the most significant bit msb 9 a 2 MemAddrO is the least significant Isb BA1 0 Bank Address supporting up to 4 internal banks 3 3V LVTTL RAS Row Address Strobe 3 3V LVTTL CAS
45. d parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained in other operating environments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 1580 Route 52 Hopewell Junction NY 12533 6351 The IBM home page is www ibm com The IBM Microelectronics Division home is www chips ibm com SA14 2609 00
46. dr 32 bit data 32 bit addr 32 bit data PCI Bridge 66 MHz max async 33 MHz max sync The PPC405GPr is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an application specific ASIC product This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture Preliminary PowerPC 405GPr Embedded Processor Data Sheet Address Map Support The PPC405GPr incorporates two simple and separate address maps The first address map defines the possible use of address regions that the processor can access The second address map is for Device Configuration Registers DCRs The DCRs are accessed by software running on the PPC405GPr processor through the use of mtdcr and mfdcr instructions System Memory Address 4GB System Memory Function Subfunction Start Address End Address Size 0x00000000 OxE7FFFFFF 3712MB SDRAM External Peripherals and PCI OxE8010000 OxE87FFFFF 8MB 2 eee E 0 000000 44 Nate Any ofthe address ranges sted a 6MB functions OxEF500000 1MB OxEF900000 OxFFFFFFFF 263MB Peripheral Bus Boot 1 OxFFEO00000 OxFFFFFFFF 2MB PCI Boot 2 128 PCI 0 80000
47. e 3 1000 2 2 MHz UARTSerClk period 2 2 UARTSerClk input high time 1 UARTSerClk input low time 1 TmrClk input frequency 200 MHz 50 2 TmrClk period 200 MHz 20 ns TmrClk input frequency 266 MHz 66 66 2 TmrClk period 266 MHz 15 ns TmrClk input high time 40 of nominal period 60 of nominal period ns TmrCIk input low time 40 of nominal period 60 of nominal period ns Note 1 In asynchronous PCI mode the minimum PCICIk frequency is 1 8 the PLB Clock Refer to the PowerPC 405GPr Embedded Proces sor User s Manual for more information 2 In synchronous PCI mode the PCI clock is derived from SysClk and the input is unused 3 is the period in ns of the OPB clock The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66 66MHz for 266 2 parts 44 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Input Setup and Hold Waveform Tis Tia MIN MIN l 1 Output Delay and Float Timing Waveform SysCk 1 5V MIN 1 Valid Tor Outputs 1 5V 45 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Notes 1 In all of the following I O Specifications tables a timing values of na means not applicable and dc means don t care 2 See Test Conditions o
48. e synchronous to the modulated clock The serial port has a tolerance of approximately 1 596 on baud rate before framing errors begin to occur The 1 596 tolerance assumes that the connected device is running at precise baud rates If an external serial clock is used the baud rate is unaffected by the modulation 2 Operation of the PPC405GPr PCI Bridge is unaffected by the use of a SSCG For PCI frequencies of 33 33 MHz and below the PCI controller supports synchronous mode operation This is accomplished by strapping the PPC405GPr for synchronous mode PCI and connecting the PCI bus clock to the PPC405GPr SysClk input For 33 33 MHz signalling the PCI specification has no limitation on the amount of frequency deviation or modulation that may be applied to the PCI clock Therefore the PPC405GPr SSCG requirements stated above take precedence At PCI frequencies above 33 33 MHz the PCI controller must be operated in asynchronous mode When in asynchronous mode the PCI bus clock must be driven into the PPC405GPr input In this configuration the PCI controller supports the 66 66 MHz PCI clock specification which specifies a maximum frequency deviation of 1 at a modulation of between 30 kHz and 33 kHz 3 Ethernet operation is unaffected 4 operation is unaffected Caution It is up to the system designer to ensure that any SSCG used with the PPC405GPr meets the above requirements and does not adversely affect other aspects of the
49. eady External master interface Write posting from external master Read prefetching on PLB for external master reads Bursting capable from external master Allows external master access to all non EBC PLB slaves External master can control EBC slaves for own access and control DMA Controller 10 Supports the following transfers Memory to memory transfers Buffered peripheral to memory transfers Buffered memory to peripheral transfers Four channels Scatter gather capability for programming multiple DMA operations 8 16 32 bit peripheral support OPB and external 32 bit addressing Address increment or decrement Internal 32 byte data buffering capability Supports internal and external peripherals Support for memory mapped peripherals Support for peripherals running on slower frequency buses Preliminary PowerPC 405GPr Embedded Processor Data Sheet Serial Interface One 8 UART and one 4 pin UART interface provided Selectable internal or external serial clock to allow a wide range of baud rates Register compatibility with NS16550 register set Complete status reporting capability Transmitter and receiver are each buffered with 16 byte FIFOs when in FIFO mode Fully programmable serial interface characteristics Supports DMA using internal DMA engine Bus Interface Compliant with Phillips amp Semiconductors I C Specification dated 1995 Operation at 100kHz or 400kHz 8 bit data
50. gered or level sensitive Positive or negative active Non critical or critical interrupt to processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector for faster vector processing 10 100 Mbps Ethernet MAC Capable of handling full half duplex 100Mbps and 10Mbps operation Uses the medium independent interface MII to the physical layer PHY not included on chip JTAG EEE 1149 1 test access port IBM RISCWatch debugger support e JTAG Boundary Scan Description Language BSDL 12 Preliminary PowerPC 405GPr Embedded Processor Data Sheet 27mm 456 Ball E PBGA Package Ejector Mark 1 80 x 0 10 Top View 2 Small Radius Corner Corresponds to A1 Ball Location N Index Mark 1 10 Note All dimensions mm c 0 20 27 0 Bottom View A AF 2 00000 V U 20556 Thermal Balls 22226 27 0
51. is optional and can be disabled for systems which employ an external arbiter PCI bus frequency up to 66MHz Synchronous operation at 1 n fractions of PLB speed n 1 to 4 to S3MHz maximum Asynchronous operation from 1 8 PLB frequency to 66MHz maximum 32 bit PCI address data bus Power Management PCI Bus Power Management v1 1 compliant Supports 1 1 2 1 3 1 4 1 clock ratios from PLB to PCI Buffering between PLB and PCI PCI target 64 byte write post buffer PCI target 96 byte read prefetch buffer PLB slave 32 byte write post buffer PLB slave 64 byte read prefetch buffer Error tracking status Supports PCI target side configuration Supports processor access to all PCI address spaces Single byte PCI I O reads and writes PCI memory single beat and prefetch burst reads and single beat writes Single byte PCI configuration reads and writes type 0 and type 1 Preliminary PowerPC 405GPr Embedded Processor Data Sheet PCI interrupt acknowledge PCI special cycle Supports PCI target access to all PLB address spaces Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GPr Memory Controller core provides low latency access path to SDRAM memory A variety of system memory configurations are supported The memory controller supports up to four physical banks Up to 256 per bank are supported up to a maximum of 1 GB Memory timings address and bank sizes and memory
52. mber and is specified in the part numbering scheme for identification purposes only The PVR Processor Version Register is software accessible and contains additional information about the revision level of the part Refer to the PowerPC 405GPr Embedded Processor User s Manual for details on the register content Order Part Number Key IBM25PPC405GPr 3BA266Cx L Shipping Package Blank Tray Z Tape and reel IBM Part Number Operational Case Temperature Range 40 to 85 C Grade 3 Reliability Processor Speed 266 MHz 333 MHz Package Revision Level B 35mm 456 E PBGA D 27mm 456 E PBGA PowerPC 405GPr Embedded Processor Data Sheet PPC405GPr Embedded Controller Functional Block Diagram Universal Interrupt Controller Timers OCM SRAM DOCM MMU IOCM 405 Processor Core OCM Control DCR Bus 16KB D Cache JTAG Trace DCU ICU Code Decompression CodePack i 16KB Preliminary On chip Peripheral Bus OPB DMA Controller 4 Channel OPB Bridge Ethernet Processor Local Bus PLB v SDRAM Controller External Bus Controller External Bus Master Controller 13 bit ad
53. n page 41 for output capacitive loading Specifications Group 1 Part 1 of 3 Notes 1 PCI timings are for asynchronous operation up to 66 66 MHz PCI output hold time requirement is 1 for 66 66 MHz and 2ns for 33 33MHz 2 Ethernet interface meets timing requirements as defined by IEEE 802 3 standard 3 For PCI is specified at 0 9OVpp and I O L is specified at 0 1 OVpp For all other interfaces I O is specified at 2 4 V and I O L is specified at 0 4 V Input ns Output ns Output Current mA Signal Setup Time Hold Time Valid Delay Hold Time 1 0 H VOL Clock Notes Tis min PCI Interface PCIAD31 0 3 0 6 1 0 5 1 5 PCICIk 1 0 0 3 0 6 1 0 5 1 5 1 PCIDevSel 3 0 6 1 0 5 1 5 1 3 0 6 1 0 5 1 5 1 6 1 0 5 1 5 1 5 3 0 6 1 na na 1 PCIINT PerWE na na dc dc 0 5 1 5 PCICIK async PCIIRDY 3 0 6 1 0 5 1 5 PCICIK 1 PCIParity 3 0 6 1 0 5 1 5 PCICIk 1 PCIPErr 3 0 6 1 0 5 1 5 PCICIk 1 PCRs 5 0 na na na na PCICIK 1 PCIReset na na na na 0 5 1 5 PCISErr na na na na 0 5 1 5 PCIStop 3 0 6 1 0 5 1 5 1 PCITRDY 3 0 6 1 0 5 1 5
54. na PerClk 5 50 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Strapping When the SysReset input is driven low by an external device system reset the state of certain I O pins is read to enable default initial conditions prior to PPC405GPr start up The actual capture instant is the nearest SysClk edge before the deassertion of reset These pins must be strapped using external pull up logical 1 or pull down logical 0 resistors to select the desired default conditions The recommended pull up is 3kQ to 3 3V or 10kQ to 5V The recommended pull down is 1KQ to GND These pins are use for strap functions only during reset They are used for other signals during normal operation The following tables list the strapping pins along with their functions and strapping options The PPC405GPr can be used as a drop in replacement for the PPC405GP When the PPC405GPr is used for this purpose it should be strapped to operate in the PPC405GPr Legacy mode This option is selected by strapping 020 GPIO24 low 0 If Legacy mode is selected the PPC405GPr Legacy Mode Strapping Pin Assignments table should be used to determine the strapping options To operate the chip as a PPC405GPr strap D20 GPIO24 high 1 and use PPC405GPr New Mode Strapping Pin Assignments on page 53 to determine the strapping options PPC405GPr Legacy Mode Strapping Pin Assignments Part 1 of 2
55. nput Logic Low 1 8V CMOS receivers 0 0 65 Input Logic Low 3 3 5 0V LVTTL receivers 0 0 8 v Output Logic High VoH 2 4 OVpp V Output Logic Low VoL 0 0 4 3 3V Input Current no pull up or pull down hu zu pA Input Current with internal pull down lite 10 OV 200 Vpp 5V Tolerant I O Input Current lia 10 325 Input Max Allowable Overshoot 1 8V CMOS receivers VIMAO1 8 Vop 0 6 v Input Max Allowable Overshoot 3 3V LVTTL receivers Vimaos 0 6 Input Max Allowable Overshoot 5 0V LVTTL receivers VIMAOS 39 Input Max Allowable Undershoot Vimau 0 6 Output Max Allowable Overshoot Vomao OVpp 0 3 V Output Max Allowable Undershoot Vomau3 0 6 V Case Temperature Tc 40 485 Note 1 See 5V Tolerant Input Current on page 40 39 Preliminary PowerPC 405GPr Embedded Processor Data Sheet 5V Tolerant Input Current 50 50 100 150 Input Current 200 250 300 350 0 0 1 0 4 0 5 0 Input Voltage V Input Capacitance Parameter Symbol Maximum Unit Notes 3 3V LVTTL I O 8 8 pF 5V tolerant LVTTL Cine 8 pF PCI I O Cins 9 3 pF Rx only pins Cina 4 5 pF 40 PowerPC 405GPr Embedded Processor Data Sheet DC Electrical Characteristics Parameter Symbol Minimum Typical Maximum Unit Active Operating Current
56. ology permits input only signals can be connected together and terminated through either a common resistor or directly to 3 3V or GND When a resistor is used its value must ensure that the grouped I Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405GPr Unused I Os Strapping of some pins may be necessary when they are unused Although the PPC405GPr requires only the pull up and pull down terminations as specified in the Signal Functional Description on page 30 good design practice is to terminate all unused inputs or to configure I Os such that they always drive If unused the peripheral SDRAM and PCI buses should be configured and terminated as follows Peripheral interface PerAddr0 31 PerData0 31 and all of the control signals are driven by default Terminate PerReady high and PerError low SDRAM Program SDRAMO CFG EMDULR 1 and SDRAMO CFG DCE 1 This causes the PPC405GPr to actively drive all of the SDRAM address data and control signals PCI The PCI pull up requirements given in the Signal Functional Description apply only when the PCI interface is being used When the PCI bridge is unused configure the PCI controller to park on the bus and actively drive PCIAD31 0 PCIC3 0 BE3 0 and the remaining PCI control signals by doing the following Strap the PPC405GPr to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode
57. ow minimum of 16 cycles to initiate a system reset A system UO 5V tolerant 1 2 y reset can also be initiated by software Implemented as an open 3 3V LVTTL drain output two states 0 or open circuit AVpp Clean voltage input for the PLL 35 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signal Functional Description Part 7 of 8 Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball Notes 1 Receiver input has hysteresis 2 Must pull up See Pull Up and Pull Down Resistors on page 29 for recommended termination values 3 Must pull down See Pull Up and Pull Down Resistors on page 29 for recommended termination values 4 not used must pull up 5 If not used must pull down 6 Strapping input during reset pull up or pull down as required 7 Pull up may be required See External Bus Control Signals on page 29 Signal Name Description 5 Se ae Clean Ground input for the PLL 5V tolerant SysErr Set to 1 when a Machine Check is generated 3 3V LVTTL mens 5V tolerant Halt Halt from external debugger 3 3V LVTTL 1 2 General Purpose I O GPIO1 TS1E or vOJO 5V tolerant 16 GPIO2 TS2E Even Trace execution status To access this function software 3 3V LVTTL must toggle a DCR bit General Purpose I O or 5V tolerant GPIO3 TS10
58. rnal and 19 internal edge triggered or level sensitive interrupts Programmable timers Two serial ports 16550 compatible UART One interface General purpose GPIO available Supports JTAG for board level testing Internal processor local Bus PLB runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory Unique software accessible 64 bit chip ID number ECID support serial ports interface and general purpose I O Technology IBM CMOS SA 27E 0 18 um 0 11 um Leg Package 456 ball 35mm or 27mm enhanced plastic ball grid array E PBGA Power typical 1 1 W at 266MHz While the information contained herein is believed to be accurate such information is preliminary and should not be 1 relied upon for accuracy or completeness and no representations or warranties of accuracy or completeness are made Preliminary PowerPC 405GPr Embedded Processor Data Sheet Contents Ordering PVR and JTAG Information 41 4 Address Map Support ak ce ee Wale PEE Rao Rr RH ee E A E ae 6 On Chip Memory 1 7 8 PLB to Interface 8 SDRAM Memory Controller 9 External Peripheral Bus Cont
59. rnational Business Machines Corporation 1999 2002 All Rights Reserved Printed in the United States of America March 2002 The following are trademarks of International Business Machines Corporation in the United States or other countries or both Blue Logic CoreConnect IBM Logo CodePack IBM PowerPC Other company product and service names may be trademarks or service marks of others Preliminary Edition 3 8 02 This document contains information on a new product under development by IBM IBM reserves the right to change or discontinue this product without notice This document is a preliminary edition of the PowerPC 405GPr data sheet Make sure you are using the correct edition for the level of the product While the information contained herein is believed to be accurate such information is preliminary and should not be relied upon for accuracy or completeness and no representations or warranties of accuracy or completeness are made All information contained in this document is subject to change without notice The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons The information contained in this document does not affect or change IBM product specifications or warranties Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or thir
60. roller 0 1 9 Controller i e de eee ie peas KR be Pe eee ees 10 Serial Interface eee ee le ee we el jet mea ae rate 11 IC Bus Interface RRR Re eR E e de ae a A 11 General Purpose IO GPIO Controller 1 0 12 Universal Interrupt Controller UIC 12 10 100 Mbps Ethernet MAC 4 12 EE 12 SIDE P i eee Pee ee a rel Rhee a ee 28 Spread Spectrum Clocking 43 51 Tables System Memory Address Map 6 DCR Address Map ie edd 7 Signals Listed Alphabetically 4 15 Signals Listed by Ball Assignment 14 2 25 SUMMA RYE ES adu m e EE E ES 28 Signal Functional Description 1 1 30 Absolute Maximum Ratings ents 38 Package Thermal
61. rr na na 10 3 7 1 SysReset 10 10 3 7 1 TestEn dc dc na na na na async TmrClk dc dc na na na na async Trace TS1E TS2E 7510 7520 793 754 795 756 2 0 7 2 0 5 10 3 7 1 TrcCIk 10pF load on clk data 48 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Specifications Group 2 Par 1 of 2 Notes 1 2 3 The SDRAM command interface is configurable through SDRAMO TR LDF to provide a 2 to 4 cycle delay before the command is used by SDRAM SDRAM timings are specified relative to MemClkOut terminated into a lumped 10pF load SDRAM interface hold times are guaranteed at the PPC405GPr package pin System designers must use the PPC405GPr IBIS model available from www chips ibm com to ensure their clock distribution topology minimizes loading and reflections and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring PerClk timing is specified with a 10pF load at the package pin Input timings are specified at 1 5V assuming transition times between 1 and 2ns when measured between the 10 and 90 points of the output voltage 6 I O H is specified at 2 4 V and I O L is specified
62. rr EMCTxEn Divide by 2 0 0 Divide by 3 0 1 Divide by 4 1 0 Divide by 5 1 1 ROM Width AD2 8 bit ROM 0 0 16 bit ROM 0 1 32 bit ROM 1 0 Reserved 1 1 ROM Location U2 HoldAck PPC405GPr Peripheral Attach 0 PPC405GPr PCI Attach 1 PCI Asynchronous Mode Enable Y3 ExtAck Synchronous Mode 0 Asynchronous Mode 1 PCI Arbiter Enable 3 AF18 GPIO4 TS2O Internal Arbiter Disabled 0 Internal Arbiter Enabled 1 Note 1 The tune bits adjust parameters that control PLL jitter The recommended values minimize jitter for the PLL implemented in the PPC405GPr These bits are shown for information only and do not require modification except in special clocking circumstances such as spread spectrum clocking For details on the use of Spread Spectrum Clock Generators SSCGs with the PPC405GPr visit the technical documents area of the IBM PowerPC web site 2 Not all combinations of dividers produce valid operating configurations Frequencies must be within the limits specified in Clocking Specifications on page 42 Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor User s Manual 3 Additional consideration must be given to pins that normally function as Trace signals Improved design margin can be gained by using tri state buffers instead of strapping resistors and minimizing trace lengths and stubs PowerPC 405GPr Embedded Processor Data Sheet PPC405GPr New Mode Strapping Pin As
63. sertion of PCITRDY indicates that the PCI target is ready to 2 3 3V PCI transfer data The target of the current PCI transaction can assert PCIStop to 5V tolerant PCIStop indicate to the requesting PCI master that it wants to end the 3 3V PCI 2 current transaction i PCIDevSel is driven by the target of the current PCI transaction A 5V tolerant PCIDevSel PCI target asserts PCIDevSel when it has decoded an address y o 2 3 3V PCI and command encoding and claims the transaction PCIIDSel PCIIDSel is used during configuration cycles to select the PCI 5V tolerant slave interface for configuration 3 3V PCI POISER PCISErr is used for reporting address parity errors or catastrophic o 5V tolerant 2 failures detected by a PCI target 3 3V PCI PCIPErr is used for reporting data parity errors on PCI PCIPErr transactions PCIPErr is driven active by the device receiving UO 5V tolerant 2 PCIADO 31 PCICO 3 BE0 3 and PCIParity two PCI clocks 3 3V PCI following the data in which bad parity is detected is used as the asynchronous PCI clock when asynch 5V tolerant mode It is unused when the PCI interface is operated 3 3V PCI synchronously with the PLB bus LAS 5V tolerant PCIReset PCI specific reset 3 3V PCI PCI interrupt Open drain output two states 0 or open circuit PCIINT PerWE or 5V tolerant Peripheral write enable Low when any of the four PerWBE0 3 3 3V PCI write byte enables are low
64. signments Part 1 of 3 Preliminary Function Option Ball Strapping PLL Tuning AF3 AF2 AD16 See the PowerPC 405GPr UARTO Tx UARTO UARTO RTS Embedded Processor User s Choice 1 TUNE 9 0 1010111100 0 0 0 Manual for details Choice 2 TUNE 9 0 0100111000 0 0 1 Choice 3 TUNE 9 0 0100110110 0 1 0 Choice 4 TUNE 9 0 0100111100 0 1 1 Choice 5 TUNE 9 0 0100111000 1 0 0 Choice 6 TUNE 9 0 1000111100 1 0 1 Choice 7 TUNE 9 0 1000111110 1 1 0 Choice 8 TUNE 9 0 1011111110 1 1 1 PLL Forward Divider 2 016 15 9 DMAAck1 GPIOS5 TS3 Divide by 8 0 0 0 Divide by 7 0 0 1 Divide by 6 0 1 0 Divide by 5 0 1 1 Divide by 4 1 0 0 Divide by 3 1 0 1 Divide by 2 1 1 0 Divide by 1 1 1 1 PLL Forward Divider 2 P25 L24 AE8 EMCTxD3 EMCTxD2 GPIO6 TS4 Divide by 8 0 0 0 Divide by 7 0 0 1 Divide by 6 0 1 0 Divide by 5 0 1 1 Divide by 4 1 0 0 Divide by 3 1 0 1 Divide by 2 1 1 0 Divide by 1 1 1 1 53 Preliminary PowerPC 405GPr Embedded Processor Data Sheet PPC405GPr New Mode Strapping Pin Assignments Part 2 of 3 Function Option Ball Strapping PLL Feedback Divider 2 3 B14 C12 5 AC7 DMAAck2 DMAAck3 GPIO7 TS5 GPIOS TS6 Divide by 16 0 0 0 0 Di
65. so multi purpose For example the EBC peripheral controller address pins are used as outputs by the PPC405GPr to broadcast an address to external slave devices when the PPC405GPr has control of the external bus When during the course of normal chip operation an external master gains ownership of the external bus these same pins are used as inputs which are driven by the external master and received by the in the PPC405GPr In this example the pins are also bidirectional serving as both inputs and outputs Intialization Strapping One group of pins is used as strapped inputs during system reset These pins function as strapped inputs only during reset and are used for other functions during normal operation see Strapping on page 51 Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable 28 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Pull Up and Pull Down Resistors Pull up and pull down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state The recommended pull up value of 3kO to 3 3V 10kQ to 5V can be used on 5V tolerant I Os and pull down value of 1kQ to GND applies only to individually terminated signals To prevent possible damage to the device I Os capable of becoming outputs must never be tied together and terminated through a common resistor If your system level test method
66. uired See External Bus Control Signals on page 29 Signal Name Description yo Type Notes 5V tolerant UART1_Rx UART1 Serial Data In 3 3V LVTTL 1 5V tolerant UART1_Tx UART1 Serial Data Out 3 3V LVTTL 6 UART1 Data Set Ready UART1_DSR or 5V tolerant 1 CTS UART1 Clear To Send To access this function software must 3 3V LVTTL toggle a DCR bit UART1 Request To Send UART1_RTS or 5V tolerant 6 UART1_DTR UART1 Data Terminal Ready To access this function software 3 3V LVTTL must toggle a DCR bit 5V tolerant IICSCL Serial Clock y o 3 3V LVTTL 1 2 5V tolerant IICSDA Serial Data 3 3V LVTTL 1 2 Interrupts Interface Interrupt requests or 5V tolerant IRQO 6 GPIO17 23 1 l General Purpose I O To access this function software must VO 3 3V LVTTL toggle a DCR bit JTAG Interface 5V tolerant TDI Test data in 3 3V LVTTL 1 4 5V tolerant TMS JTAG test mode select 3 3V LVTTL 1 4 5V tolerant TDO Test data out 3 3V LVTTL TCK JTAG test clock The frequency of this input can range from DC to 5V tolerant 1 4 25MHz 3 3V LVTTL TRST JTAG reset TRST must be low at power on to initialize the JTAG 5V tolerant 5 controller and for normal operation of the PPC405GPr 3 3V LVTTL System Interface SysClk Main system clock input 29 toleran y y put 3 3V LVTTL Main system reset External logic can drive this bidirectional pin l
67. ultiplexed signals are shown with the default signal following reset not in brackets and the alternate signal in brackets Multiplexed signals appear alphabetically multiple times in the list once for each signal name on the ball The page number listed gives the page in Signal Functional Description on page 30 where the signals in the indicated interface group begin Signals Listed Alphabetically Part 1 of 10 Signal Name Ball Interface Group Page AGND E22 System 35 AVpp D25 System 35 BAO AB24 BAT 24 SDRAM ee BankSelO AD17 BankSel1 AF17 BankSel2 AE15 SDRAM e BankSel3 AC14 BEO PCICO D19 BE1 PCIC1 F24 BE2 PCIC2 BE3 PCIC3 R26 BusReq R3 External MASTER Peripheral 34 CAS AB23 SDRAM 32 0 25 1 25 SDRAM 38 DMAAckO D16 DMAAck1 B15 DMAAck2 B14 External SLAVE Peripheral 32 DMAAck3 C12 16 DMAReq1 D14 2 11 External SLAVE Peripheral 32 DMAReq3 A7 DQMO AC12 DQM1 AC10 2 6 SDRAM 32 DQM3 AA3 DQMCB AC15 SDRAM 32 ECCO AE14 ECC1 AF15 ECC2 AF14 ECC3 AD13 ECC4 AF13 SDRAM 2 5 12 ECC6 AE13 ECC7 AD12 H24 Ethernet 31 EMCMDIO PHYMDIO AD26 Ethernet 31 15 Preliminary PowerPC 405GPr Embedded Processor Data Sheet Signals Listed Alphabetically Part 2 of 10 Signal Name Ball Interface Group Page EMCTxDO J26 EMCTxD1 L25 EMCTxD2 L24 EMCTxD3 P2
68. vide by 1 0 0 0 1 Divide by 2 0 0 1 0 Divide by 3 0 0 1 1 Divide by 4 0 1 0 0 Divide by 5 0 1 0 1 Divide by 6 0 1 1 0 Divide by 7 0 1 1 1 Divide by 8 1 0 0 0 Divide by 9 1 0 0 1 Divide by 10 1 0 1 0 Divide by 11 1 0 1 1 Divide by 12 1 1 0 0 Divide by 13 1 1 0 1 Divide by 14 1 1 1 0 Divide by 15 1 1 1 1 2 125 26 EMCTxD1 EMCTxDO Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 PCI Divider from PLB 23 D18 C20 GPIO1 TS1E GPIO2 TS2E Divide by 1 0 0 Divide by 2 0 1 Divide by 3 1 0 Divide by 4 1 1 External Bus Divider from K25 K23 PLB EMCTxErr Divide by 2 0 0 Divide by 3 0 1 Divide 4 1 0 Divide by 5 1 1 ROM Width AD2 mom T9 DARTLDIS 8 bit ROM 0 0 16 bit ROM 0 1 32 bit ROM 1 0 Reserved 1 1 PowerPC 405GPr Embedded Processor Data Sheet PPC405GPr New Mode Strapping Pin Assignments Part 3 of 3 Function Option Ball Strapping ROM Location U2 HoldAck PPC405GPr Peripheral Attach 0 PPC405GPr Attach 1 PCI Asynchronous Mode Enable ExtAck Synchronous PCI Mode 0 Asynchronous Mode 1 External Bus Synchronous A22 Mode Enable 9 GPIO3 TS10 Synchronous Mode 0 Asynchronous Mode 1 PCI Arbiter Enable 3 AF18 GPIO4 TS2O Internal Arbiter Disabled 0 Internal Arbiter Enabled 1 New Mode Enable D20 In ed mode the GPIO24 4 Pr

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