SPC564Axx/SPC56ELxx devices Exception handling and single
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1. Machine check address register MCAR MCAR register contains target address reporting the fault condition It is updated only for Asynchronous Machine check group when MCSR MAV bit is cleared and it is valid only if MCSR MAV status flag is set Otherwise the MCAR register cannot be used in the fault analysis It is important to clear MCSR MAV bit after reading MCAR register value to enable capture of the address in case of new asynchronous machine check fault Machine check MCSRRO register This register is updated by the HW in the beginning of the machine check interrupt It stores the address of the instruction that causes the error condition DoclD025623 Rev 2 Ly AN4417 ZA Core exception overview It is used in the end of the machine check when mcrfi instruction is executed to fill the instruction pointer The result is that code restarts the same instruction that was cause of the error if additional modification of the MCSRRO register is not explicitly done Ly DoclD025623 Rev 2 7 22 Machine check handler AN4417 2 2 1 8 22 Machine check handler Machine check handler usually splits into two parts e Low level handler e User handler Low level handler Low level handler is responsible for first and last part of the exception execution It is usually written in assembly language as it needs to execute proper instruction sequence before it can pass the code execution to higher level routine and2. v AN4417 JJ ah Application note SPC564Axx SPC56ELxx devices Exception handling and single double bit error Introduction This document provides an overview of SPC564Axx SPC56ELxx exception handling with main focus on different kinds of exception that the application code may face during the runtime like single and double bit errors in memories MPU protection violation AIPS access protection violation and others It starts with the simple overview of Machine check interrupt highlighting important things from application perspective To get detailed view and to implement low level machine check interrupt handler it is necessary to use Z4 Core User Manual which describes all the details about the Core exception and interrupts The following part describes the reason of the exception how to find it and what possibilities exist to remove the fault December 2013 DoclD025623 Rev 2 1 22 www st com Contents AN4417 Contents 1 ZA Core exception overview ks RR RR RR RR RR RR RR RR RR Ri 5 1 1 Machine check interrupt IVOR1 EE EE ER ee ee ee 5 1 1 1 Machine check registers is EE EE EE Ge tenes 5 2 Machine check handler ses ss EER ER ER RR RR RR RR RR RR Re 8 2 1 Low level handler EE GE GE GE GE GE EE EE Es Es Es Ee ee se ei 8 2 1 1 Siri E 9 2 1 2 Final phase onda vm ede edu t s eke que aes 9 2 1 3 Modification of the MCSRRO register EE SS ES SE eee 9 2 2 User handler
3. o lt tE vals m AE 0x30007 Ox3000F i Ww iL w T ui i tu TE m Accessed o No of Nolo No fol No 0 No Jol No 0 No lolno o No Jo No by master change change change change change EE o No fol nolo No fol No 0 No Jol No lo No lo No o No Jo No by master change change change change change Accessed by master 1 0XS0000 0 YES 1 0x30000 0 NO 1 Ox30000 1 YES 1 ox300 0 NO f 1 Ox30000 1 YES Md 1 0x30000 1 YES 1 0x30000 1 YES 1 ox30000 1 YES 1 0x30000 1 YE 1 0x30000 1 YES by master E Accessed 4 ox30008 1 YES 1 0x30008 1 YES 1 ox30008 1 YES 1 ox30008 1 YE 1 0x30008 1 YES by master S boue 1 0x30008 0 YES 1 0x30008 0 NO 1 ox30008 1 YES 1 0x30008 o NO 1 0x30008 1 YES 10112 993 Puunp 1olAeUadg 49 04300204J91U1J Jo UOSIJEdUIO ZLVVNV c ASH Z96 0al20a cc 6l Table 8 Summary of reactions to single double bit error continued FLASH line 128bit e g ADDRESS 0x30000 SPC564A70 SPC564Axx SPC563M SPC56EL family SPC560P family means addr range 0x30000 0x3000F wor wor tc z tc z tc z tc rc a Es SE EES cess Ee EE el etek E E E e g addr e g addr E 5 S o amp S amp O ok l 5 o Noa 3 y MES o B Se S EI EE lt ex m d su ICE lt X lt range range 5 d O
4. Memory access must be within area belonging to the Flash memory User has to know which part belongs to the code flash and which part belongs to the data flash memory Error solving Flash 2b ECC error can be solved only with erase of the flash sector containing the cell with 2b ECC error It is usually not done in the exception handler itself because it takes significant amount of time The decision what to do in case of 2b ECC error is application specific Whether if to go to degraded mode or to continue the case of EEPROM emulation and to solve the issue later in the application If the decision is to continue user handler has to request modification of the MCSRRO register to continue the program flow with next instruction Otherwise program would be stuck in the reading of the fault flash address invoking machine checks DoclD025623 Rev 2 Ly AN4417 Comparison of microcontroller behavior during ECC error Appendix A Comparison of microcontroller behavior during ECC error Table 8 is a summary of the behavior of different 90nm microcontrollers in case of either single or double bit error in the flash To understand the table the user should keep in mind that flash is accessed in word line of 128 bit Each time a master would like to access read code fetch a location which belongs to a certain word line the whole word line is read out of the flash The word line consists of two double words A and B Each one double word
5. tna BR Ra a x RO n Rc 10 3 SPC564Axx SPC56ELxx exception cases 12 3 1 Flash 2b ECG eror iussa cos ao CR RC ned OR NOR DRR RR ES ands 12 3 1 1 Cause of the exception EE EE EE eee ee 12 3 1 2 Machine check exception status 0 0 eee eee 13 3 1 3 Flash 2b ECC error detection by ECSM 0 000 eee 13 3 1 4 ECSM_ESR FNCE implementation note for SPC564A70 device only 14 3 1 5 ECSM ESR implementation for SPC56ELx device only 14 3 1 6 Flash 2b ECC error detection by Flash controller 14 3 1 7 Flash x MCR ERR implementation note for SPC564A80 device only 15 3 1 8 User exception handler EE eee ee 16 3 1 9 Error solving ARE EE a EE A ee 16 Appendix A Comparison of microcontroller behavior during ECC error 17 Appendix B Reference documents 000c cece cece o 20 B 1 AGrOnymis saeua E SERE LS EER DER DR de Rc bue E ERR VASE 20 REVISION history anne RE c timed EE 28 29 B CR n n o Qe DG mh 21 2 22 DoclD025623 Rev 2 Ly AN4417 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Machine check interrupt causes 1 eee 5 Machine check register llle rn 6 Machine check causes EE EE EE ER ee ee eee 6 SPC564Axx SPC56ELxx exception cauSeS ie ee eee 12 Flash 2b ECC machine check exception status in core registerS 13 Flash 2b E
6. 6 Flash 2b ECC ECSM registers related to ECC error detection continued Register Description ECSM_ESR F1BC A reportable single bit platform flash correction has been detected ECSM ESR FNCE A reportable non correctable platform flash error 2b ECC has been detected Maintaining of ECSM ESR register to be performed properly For more details see Section Appendix B Heference documents ECSM ESR FNCE implementation note for SPC564A70 device only Flash controller always reads one complete prefetch buffer line 128 bit from flash array ECSM ESR FNCE bit detects ECC error separately for double word A bit 0 63 and double word B bit 64 127 in SPC564A70 device and it can cause an unexpected behavior Following is an example to demonstrate it Assuming that an ECC error is present in upper word and lower word is accessed by core Then the ECC error is detected during complete 128 bit line reading and core Machine check exception is invoked but ECSM ESR FNCE bit is not set in this case If Machine check exception handler tests the ECSM ESR FNCE bit only in our case then it may unexpectedly assume that no ECC issue occurred There is a possibility to check Flash A MCHR EER bit instead of the ECSM ESR FNCE The implementation depends on the application needs For more details see Section Appendix A Comparison of microcontroller behavior during ECC error ECSM ESR implementation for SPC56ELx device only S
7. ECC EDC hardware 1b ECC Single bit error its detected and correct by the ECC EDC hardware NMI Non maskable interrupt DoclD025623 Rev 2 Ly AN4417 Revision history Revision history Table 10 Revision history Date Revision Changes 12 Dec 2013 1 Initial release 19 Dec 2013 2 Modified Table 8 Ly DoclD025623 Rev 2 21 22 AN4417 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party pro
8. exception is invoked only if the accessed one double word contains ECC error in SPC564A80 device and it can cause an unexpected behavior Following is an example to demonstrate it Assuming that an ECC error is present in upper word and lower word is accessed by core The ECC error is detected during complete 128 bit line reading and core Machine check exception is NOT invoked but Flash x MCR EER bit is set in this case and it is not cleared automatically Let us assume that Machine check exception is invoked later on caused by another reason e g due to memory protection by MPU If the Machine check exception handler tests the Flash x MCR EER bit only then it may unexpectedly assume that flash ECC error has occurred instead However the Machine check exception handler routine may handle this situation by cross checking the data coming from FLASH AR and MCAR Note There is also a possibility to check ECSM_ESR FNCE bit instead of the Flash x MCH EER registers The implementation depends on the application needs For more details see Section Appendix A Comparison of microcontroller behavior during ECC error Ly DoclD025623 Rev 2 15 22 SPC564Axx SPC56ELxx exception cases AN4417 3 1 8 16 22 User exception handler Handler has to analyze the following e Type of access instruction fetch data read and data write Only instruction fetch or data read access are expected in case of 2b ECC Flash error e Memory range
9. level handler follows rules and recommendation described in the User Manual see Section Appendix B Reference documents Final phase Here the handler should restore the saved context of the interrupted process and return with the mcrfi instruction Before mcrfi instruction is executed which fills instruction pointer with MCSRRO content and MSR register with MCSRR1 content MCSRRO modification might be needed There are two cases which determine if the manipulation is needed or not This information is useful in the user handler to pass down to the low level driver 1 User handler finds the cause of the machine check exception and fix it in a way that the program can re execute the same instruction that caused the machine check exception 2 User is able to find the cause of the exception but the problem remains and re executing the same instruction lead to the machine check exception again gt Modification of the MCSRRO is needed Modification of the MCSRRO register In case that the cause of the exception cannot be removed MCSRRO register value is modified in a way that it takes the address of the following instruction This prevents re execution of the faulty instruction and retriggering the machine check exception Modification has to consider VLE instruction coding in case the interrupted process is implemented in VLE coding and increment the value accordingly of the length of the faulty instruction pointed by the curren
10. 0 er Olz Sj O5 m EO 5 E s or 0x30000 0x30008 4 9 BE 0 5 lt tl 9 lt u Sals i 92 0x30007 0x3000F i ui TE ui TE ui T hr T ui Accessed 4 030000 YES 1 0x30000 1 YES 1 ox30000 1 YES 1 0x30000 1 YE 1 0x30000 1 YES by master E ies 1 0x30000 1 YES 1 0x30000 1 YES 1 0x30000 1 YES 1 0x30000 1 YE 1 0x30000 1 YES by master 5 Note Marking in the first 2 columns of the table represents the address locations which are affected by an ECC error Accessed by the master means address location accessed read or write or core instruction fetch by crossbar XBAR master Microcontroller core is only one of the XBAR masters ZLVVNV 10112 993 BuuNP 1olAeUed 19 043100204J91U1I JO UOSMEduI09 Reference documents AN4417 Appendix B B 1 20 22 Reference documents e Z4d Core Reference Manual e SPC56EL60 32 bit MCU family built on the embedded Power Architecture RM0032 Doc ID 15265 e SPC56XL70xx 32 bit MCU family built on the embedded Power Architecture RMOO42 Doc ID 023986 e SPC564A74xx SPC564A80xx 32 bit MCU family built on the embedded Power Architecture RM0029 Doc ID 15177 e SPC564A70B4 SPC564A70L7 32 bit MCU family built on the embedded Power Architecture RM0068 Doc ID 18132 Acronyms Table 9 Acronyms Acronym Name ECC Error Correction Code EDC Error Detection Code 2b ECC double bit error it is only detected by the
11. CC ECSM registers related to ECC error detection 13 Flash 2b ECC flash controller registers related to ECC error detection 15 Summary of reactions to single double bit error llle 18 ate tos EES EEN EO eines tp EE EE EE pen Bondi qe dor Ee EN 20 Revisi hISLOEy RE N ON RE NE ER RE OE N 21 DoclD025623 Rev 2 3 22 List of figures AN4417 List of figures Figure 1 Machine check exception flow lisse III 8 Figure 2 Modification of MCSRRO register content liliis 10 Figure 3 Machine check exception user handler flow Li EE EE Ee EE Ee eee 11 Figure 4 Hlash2DbECOefOF ee de Se ee Ee Ge Ge ed ee hh nr 13 4 22 DoclD025623 Rev 2 Ly AN4417 ZA Core exception overview 1 1 1 1 1 Z4 Core exception overview Z4 Core used on SPC564Axx SPC56ELxx devices contains many exception sources and sixteen interrupts to service them Multiple exception sources can be mapped to one interrupt handler where few supportive status registers provide flags to find the cause of the exception in the handler Detailed list of the exception causes and their mapping to interrupt handlers is found in the ZA Core Reference Manual see Section Appendix B Reference documents This chapter gives an overview of machine check interrupt that is utilized for several important fault states of SPC564Axx SPC56ELxx devices Machine check interrupt IVOR1 Machine check inte
12. Lxx exception cases Figure 4 Flash 2b ECC error Crossbar Read access External bus Instruction fetch or Data error termination read PFLASHC Read data from Flash sid found FLASH Array Machine check exception status A 2b ECC error GAPG1203131159RI Table 5 Flash 2b ECC machine check exception status in core registers Register Description Address of the instruction that caused the exception In case of ECC error in the MCSRRO A a data flash area register modification is needed MCSR Type of operation is highlighted here instruction fetch data load or data write MCAR Target address that was accessed but finished with 2b ECC error This address can be used for further analysis Flash 2b ECC error detection by ECSM Flash controller provides detection ability of ECC errors detection Table 6 Flash 2b ECC ECSM registers related to ECC error detection Register Description The ECSM ESR signals the last properly enabled in ECSM ECR memory ECSM ESR event to be detected RAM and Flash single bit errors as well as dual bit errors are signaled by separated status bits ECSM ESR R1BC A reportable single bit platform RAM correction has been detected ECSM ESR RNCE A reportable non correctable platform RAM error 2b ECC has been detected DoclD025623 Rev 2 13 22 SPC564Axx SPC56ELxx exception cases AN4417 Note 14 22 Table
13. PC56ELx devices have been designed with functional safety in mind In case the reporting of dual bit errors is enabled in the ECSM the device reacts in one of the safest way i e a critical fault is triggered by the FCCU The outcome of this critical fault is a functional reset of the device without any exception triggered to the core Rational for this severe reaction is that since the dual bit error cannot be corrected software is not able to recover it Then safest reaction is assumed to be a reset Nevertheless this reset reaction prevents working correctly most of flash eeprom emulation drivers An ECC error is a standard error situation during read in flash area used for data eeprom emulation This situation is handled by the driver accordingly In case of the dual bit error reporting is disabled in the ECMS and then a core exception is invoked instead of reset Core exception handler gives possibility to the flash eeprom emulation driver to react accordingly Flash 2b ECC error detection by Flash controller Flash controller provides detection ability of ECC errors detection DoclD025623 Rev 2 Ly AN4417 SPC564Axx SPC56ELxx exception cases Table 7 Flash 2b ECC flash controller registers related to ECC error detection Register Description Flash x MCR EER Flash MCR ERR for SPC56ELxx devices EER provides information on previous reads If a double bit detection occurred the EER bit is set to a 1 This bit
14. accesses special purpose Core registers The middle of the interrupt service routine belongs to the user handler where analysis of the root cause of the exception and fault removal is done Once the user handler finishes code execution is given back to the low level driver to finish the interrupt and return back to the interrupt process Figure 1 Machine check exception flow Machine check exception HW updates MCSSRO MCSRR1 Standard exception processing Low level handler prepare info for user handler User handler prepare for finishing the interrupt Low level handler MCSRRO update if needed Interrupted process continues GAPG1203131132RI DoclD025623 Rev 2 ky AN4417 Machine check handler 2 1 1 Start phase In the first step the hardware Core carries out checks when the machine occurs exception The hardware stores content of the MSR register and address of the current instruction pointer if it is possible precise exception low level driver immediately starts processing The machine executes several steps like check status register saving context of the interrupted process saving and others This part stores some additional information as they are used by higher layer user handler to analyze the root cause of the exception later In the Z4 Core User Manual documentation is described a detailed description of the machine check resources their meaning and proper handling in case of interrupt Low
15. contains its own ECC Even there is always read complete word line behavior of microcontroller can differ regarding which double word is addressed and which one contains an ECC error One concrete word line starting at address 0x00030000 is chosen as an example The first 2 columns of the table represent the address location which can be accessed and can be affected by single double bit error Each row represents a combination of access and an ECC error e The marked cells in the first 2 columns are affected by an ECC error e Cells with the text Accessed by master are actually accessed by one of the crossbar master e In addition few cells are marked which highlights some differences in term of behavior The other columns contain reaction of selected registers separately for each microcontroller Ly DoclD025623 Rev 2 17 22 ala c 94 29S20d190d Table 8 Summary of reactions to single double bit error FLASH line 128bit e g ADDRESS 0x30000 SPC564A70 SPC564Axx SPC563M SPCSGEL family SPC560P family means addr range 0x30000 0x3000F LL sorda woas E s E GIE P oz 2 gif e sl Be Ww Ww tc tc tc rc tc EE EERS EES Ee SE ED ES Week e g addr e g addr Z amp gigal z amp ous amp Son 5 0 ggg I lt 2U gr lt q 2u ir lt q 2u ir lt q T lt range range 5 d O50 sos mr s 0 5 i EO 5 c s or 0x30000 0x30008 4 9 lgi o lt
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17. en MCSR MAV bit was 0 before the exception otherwise MCAR register is not updated Address of the instruction that caused the exception Once the exception is finished mcrfi instruction program starts execution with the same instruction that was the cause of the exception MCSRRO Save Restore register Machine check syndrome register MCSR This register is the first register to check additional information about the cause of the exception There are three groups of machine check causes Table 3 Machine check causes Machine check cause Brief description These exceptions are directly associated with the current instruction execution stream They are not masked with MSRye Error Report Machine check dd P bit It means that the exception is always taken whenever the IF LD ST G condition occurs They differentiate among Instruction fetch Data store and load Non maskable interrupt Not MSRyg gated exception occurs when NMI signaling is NMI enabled and NMI pin is driven low Exceptions reported by the subsystem usually as bus error termination back to the Core They are enabled by MSRyg bit and are cumulative This machine check whether the exception group triggers capture of the corresponding address to the MCAR register and if MCSRyay bit is cleared If MCSRyay was previously set then the MCAR register is not affected Asynchronous Machine check BUS IREER BUS DRERR BUS WRERR
18. must then be cleared or a reset must occur before this bit returns to a 0 state The ADDR field provides the first failing address in the event of ECC event error MCR EER set single bit correction MCR SBC set as well as providing the Flash x AR address of a failure that may have occurred in a state machine operation Flash ADR for MCR PEG cleared SPC56ELxx Note Flash controller always reads one complete prefetch buffer line 128 bit devices from flash array The first failing address stored in the AR register could be anywhere inside the flash prefetch line address range and can differ from the address originally accessed x A for SPC564A70 device X x A and or B for SPC564A74 SPC564A80 devices because flash address range is covered by two flash modules flash A and flash B For more details see Section Appendix B Reference documents 3 1 7 Flash x MCR ERR implementation note for SPC564A80 device only SPC564A80 contains two different flash modules Each of them contains its own Flash x MCR EER bit Addressing of particular flash modules depends on accessed address from flash address range For more details see Section Appendix B Reference documentsl Flash controller always reads one complete prefetch buffer line 128 bit from flash array Flash x MCR EER bit is always set if ECC error is detected in any of double word A bit 0 63 or double word B bit 64 127 In contrast core Machine check
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20. rogram will continue on next instruction following the failing one to avoid fault retrigger in case the fault remains Program will continue from the same instruction that caused the exception because fault was solved Update MCSRRO merfi Retum from machine GAPG1203131153RI DoclD025623 Rev 2 11 22 SPC564Axx SPC56ELxx exception cases AN4417 3 3 1 3 1 1 12 22 SPC564Axx SPC56ELxx exception cases This chapter lists most common exception cases that application software can experience while running code on SPC564Axx SPC56ELxx devices Table 4 SPC564Axx SPC56ELxx exception causes Exception Error Exception Description cause signaling Two or multiple bit error in the Flash memory leads to the machine check exception when faulty area is read instruction fetch or data read Flash 2b ECC External Machine error bus error check In general all protection access exceptions and 2b ECC exception lead to the same machine check exception because of external bus error termination In such cases further analysis relies on memory area check Flash 2b ECC error Cause of the exception Platform flash memory controller PFLASHC terminates bus transaction between CPU and PFLASHC controller in case the Flash memory array signals 2b ECC problem during read access This leads to machine check exception because of bus error termination DoclD025623 Rev 2 Ly AN4417 SPC564Axx SPC56E
21. rrupt is a handler that services multiple fault events that may occur during runtime code execution Table 1 Machine check interrupt causes Interrupt type Exception conditions NMI ISI ITLB Error on first instruction fetch for an exception handler Parity Error signaled on cache access External bus error Machine check This interrupt is used to handle various faults generated by peripherals in the SPC564Axx SPC56ELxx devices like MPU protection fault 2b ECC error in the Flash or RAM memory etc The reason is that most of the faults are signaled back as external bus error situation during the CPU Submodule bus transaction Machine check registers Z4 core implements few machine check status registers that are updated upon the exception event with some constraints stated in the Z4 Core Reference Manual see Section Appendix B Reference documents These registers are used to find the source of the exception and based on it is decided how to solve it DoclD025623 Rev 2 5 22 ZA Core exception overview AN4417 6 22 Table 2 Machine check register Register Content Register indicates the source of machine check this condition MCSR syndrome register gives the possibility to differentiate between them Register contains some sort of machine check conditions the address for which the asynchronous type of the machine MCAR address capture check exception was raised Address valid only wh
22. t MCSRRO register content see Figure 2 DoclD025623 Rev 2 9 22 Machine check handler AN4417 2 2 10 22 Figure 2 Modification of MCSRRO register content instruction Read content of address given by MCSRRO reg 0 instruction T Bit 3 instruction Bit 0 o 16 bit 32 bit instruction instruction MCSRRO MCSRRO MCSRRO 2 MCSRRO 4 GAPG1203131135RI User handler Here the root cause analysis is done Such analysis reguires supportive information from e Low level driver MCAR MCSR etc e Peripherals status registers for further elaboration Based on the results of analysis and the corrective actions done user handler should pass the information about the return type back to the low level driver indication if MCSRRO content is to be modified or not before mcrfi instruction DoclD025623 Rev 2 Ly AN4417 Machine check handler d Figure 3 Machine check exception user handler flow bus error termination Low level driver Low level driver provides information to the user handler Instruction fetch Data read write Access type check IF DR DW Memory range check MAV 1 Flash Code User Handler Flash Data Clear MCSR MAV RAM bit after reading Peripheral areas MCAR value Submodule check Fault processing and fix if possible User handler passes SSS BEE A SS SS eS qi information about the requested retum P
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