Lecture 5: Microwind/DCSH
Contents
1. MEER example E joj x Eile View Edt Simulate Compile Analysis Help BE 4F SA NL ek RBA EE else Microwind DSCH NOR Example Circuit After selecting the txt file a new window appears called Verilog file gt Yerlog File f DSCH 2 24 Flat Verilog i 8 23 01 5 34 07 Ph il example sch Sire Labels Routing Routing layers C Metal Metal Matalz Matal3 module example ini inz out input ind in output out wire Oy nmas amos foutyss in nmasnmaszioutvssinly 1 n EA pmas pros iout iid inz Vdd vss IE M Add Vertical bus Ie Limit row width to Doo lum Compiler Status Compiled cells r4 Routed wires 0 Pads Mo error amp Help a yf Backto editor on O Compile IH Show ia NI Click on Size on the right top menus This shows up the NMOS and PMOS sizes Set the sizes according to choice Yenlog File he E1 NW DSCH 2 24 Flat Verilog Jr 8 23 01 5 34 07 Pht Size Labels Routing Mos size rur Width P 1 600 Length P 10 200 il example sch module exampler ini inz out input ind inz output out wire Oy nmas nmastraut vss inzy nmas nmaszrut vss int pmas pros out iDw inzi Width N 0 400 Length IM 0 200 Compiler Status Compiled cells Of4 Routed wires2. Length MOS Mbr of Gates I Add metal ta drain Type Options v n Channel E low leakage C p Channel P C high speed With buried mwell high voltage Ho design rule error Congratulations 0 4 memory use UNIVERSITY OF NORTH TEX CSCE 5730 Digital CMOS VLSI Design N Discover the power of ideas Microwind DSCH NOR Example Layout e Create another NMOS and e The next step is to place place it in parallel to the first two PMOS transistors in NMOS device We share the series two devices drain diffusions A DRC check can be run by clicking on Analysis gt Design die aliii BLITZ BAIE ADA M5 B ir x 5 m ficrowind 2 C Amwu2tlablnor MSE jojk 500pm Fads J ST Contacts MOS Path Logo Bus Mas Parameters Width mos fie ambda Length MOS Mbr af Gates Add metal to drain Type Options C n Channel C low leakage f p Channel high speed iit buried nwel t high voltage Show palette menu UNIVERSITY OF NORTH TEX CSCE 5730 Digital CMOS VLSI Design ld il ete n Place the PMOs transistor ON The next step is to layout close to the Vdd rail on the top To construct two PMOS connect the in
3. Click on Add a Pulse Symbol in the palette 5th from the right in the 3rd row Then click on the metal2 of one of the inouts A window appears Change the name of the input signal Insert a 01 sequences and click on Insert he click on oimilarly assign the 2nd pun a pulse Tja x S Microwind 2 ES EEN id Mi ong Ele View Edi Sim TE Com Tm Analys N ER ELIE Te JURE E B lat Y amp amp 9 9 us plore SOBA TE HS S lambda m m J 7 amp x d Fi Label name mw DC Supply Clock Pulse sinus variable Ground Parameters Level D vy pon imeins Levelt ay 2 00 01 seq oot1oo11 mser P CMOS 0 18pm F Add text n2 visble at location 2281 Bd ad CSCE 5730 Digital CMOS VLSI Design UNIVERSI ry o NORTH T EXAS SF tne power OF ideas Now select the Visible Node symbol from the palette 7th in the third row Select it and click on the output The Add a Visible Property window appears Change the label name to out Select Visible in Simulation Click on Assign Now the output is also labeled Ee m 7 4 e Hls amp g amp 9 bug MA t E x l Label name out DC Supply Clock Pulse Sinus Variable Ground Parameters Add a tick in visible in simulation ta see the signal waveform atthe next simulation CMOS 0 18um 4 Add text ou
4. Microwind3 DSCH3 User Manual http intrage insa toulouse fr etienne microwind manual lite pdi e Installation and Use Unzip the files above to be able to work with Microwind Head the reference manual for the software Double click on Microwind3 exe to start the layout editor or on Dsch3 exe to start the schematic editor CSCE 5730 Digital CMOS VLSI Design UNIVERSITY C NORIH TEXAS Discover the power of ide Tools from Microwind http www microwind org e Microwind e DSCH e Microwind3 Editor e Microwind 2D viewer Microwind 3D viewer Microwind analog simulator Microwind tutorial on MOS devices e View of Silicon Atoms CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover th the power of ideas Microwind and DSCH NOR Example We will learn both the design flow and the CAD tools The specifications we are going to see may be different for different foundry and technology Design Example 3 Levels NOR Gate Logic Design Circuit Design Layout Design NT mU CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas of a Dsch2 example of x Open the Schematic Fie Edt inet Ven Smuate Heb Editor in Microwind DSCH3 Click on the transistor symbol in the Symbol Library on the MEM co right o S e Instantiate NMOS or MEE N PMOS transistors from the symbol l
5. txt file Ver SEE DSCH 2 2a Flat Verilog Vetilag Description ff 9 23 01 5 34 07 PM Hierarchy Verilog EE os f Flat Verilog for Mierowind2 modules examplei inl inz outi input inl ing output out Information nmos nmosii out vss inz Module name B char max nmos nmosz out vss inl ede pros pmosi rout ilwl inz pros pmoszi i lwl vdd ini endmodul M Append simulation infomations Simulation parameters The Verilog file has 17 lines inl CLE 10 in M in CLE 20 20 The design includes 9 symbols The circuit has 5 nodes Eve Running absolute time 6880 000ne CPU times 155s CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas e Open the layout editor window in Microwind Click File gt Select Foundry and select X rul This sets your layout designs in X technology Microwind 2 exam s E Pa eje X WU ek MW MA EE dd GI The current technology Is CMOS 0 1 um E Metal power supply 2 DUM Mo Error UNIVERSITY OF NORTH TEXAS Discover the power of ideas MEE File View Edt Simulate Lo Analysi lel CMOS 0 18um Load verlog file C Dsch 2 0 Export example t T CSCE 5730 Digital CMOS VLSI Design e Click on Compile gt Compile Verilog File An Open Window appears Select the txt verilog file saved before and open it
6. 0 Fads 0 Mo error BHISEEBHIE oft O Compile IH Show ia yf Back to etor ort CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas e Click Compile and then Back to editor in the Verilog File Window This creates a layout in layout editor window using automatic layout generation procedure ETE uU P MEET avs j File View Edit Simulate Compie Analysis Help e E f Pa amp amp O Wl oD 10 lambda e DR A EE ll i LT 1 000urm CINEERFEFEFEFEFN Compiling complete No error A21 um j CMOS D 18um UNT CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS DHscover the power of ideas e Add a capacitance to the output of the design The value of the capacitance depends on your choice E 1 lambda miei Fal x ut pmas2 iw eG oe AEE 2 1 000pm a XI E Parameters D Value 0 015 pF xl Xl xl Metal 3 TZ THE Enter a fixed value Le 3 in Metal 2 pF to load the line with a capacitance to ground XI Polysilicon 2 E Palysilicon NEN EAE TEE TEE REL AERE TT TE TT EC GGG GERERERERERERE FE P Diffuzion B N Diffusion Ill Iv M vel IF xl xXx xl In the layout fix the capacitance position l dir2 431 CMOS 0 1 Bum e Click on OK The e Click on the label marked In1
7. A capacitance is shown on window appears Click on the the left bottom corner Pulse option in the window Insert a 01 sequence for that specific with a value of 0 015fF input and click on nsert Then click on Assign Perform this assignment on the other inputs LISTS 2 Example msk 4 Microwind 2 Example msk File View Edt Simulate Compile Analysis Help File View Edit Simulate Compie Analysis Help e E rm ba 9 ss gt Sen RATE HI 2 E H FE be Sahe Ea Ala Ea x dtr 0 431 ICMDS 18um Pernod 4 000 ns frequency 0 250 GHz dis 036 EMOS 18um g CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS i ideas I COVEE LAE power OF ides Microwind DSCH NOR Example Circuit e Click Simulate gt Run simulation A simulation window appears with inputs and output shows the tphl tolh and tp of the circuit The power consumption is also shown on the right bottom portion of the window e If you are unable to meet the specifications of the circuit change the transistor sizes Generate the layout again and run the simulations till you achieve your target delays X Close VA on jas 7 007 ub a aie A CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas e Design the layout e Vdd and GND rails are of manually Metal1 he top rail is used as Vdd and the bottom
8. Bs 8 H LS pros nmds nmas Running absolute time 6060 000ne CPU time 135s JMIVERSITY OF NORTH TEXAS Lyiscover the power of ideas Eb o eal Wo SEEK Hee pros Pas Ine nas nmuas Running absolute tine 6880 000ne CPU time 155s CSCE 5730 Digital CMOS VLSI Design amp Em xy gs DE oo A aut TI Microwind DSCH NOR Example Logic e The simulation output can be observed as a waveform after the application of the inouts as above Click on the timing diagram icon in the icon menu to see the timing diagram of the input and output waveforms Timing diagrams of example sch Quit View All Help Ca DI BOD 100 150 0 2000 2500 300 0 S500 4000 4500 500 0 550 0 p000 650 0 nnn b b c P b m n b m n E nm n E n a E n E n b n b b n b LL a inl button ernest reverie HI M eo ee ee eee eee in2 button2 ik Mc RUE oe TUNER maa MENU NM I c E eee out light poems oa ee Ar N EN NN EEN DAN ET HEER A Bic ie m UE Ed ee OO MCN ME INTE is ETE ES DBU EER EE Oe 077 OBO Lesen EE EE EE EE NN VRAE CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas Simulate your system with Glick File gt Make Verilog File The Verilog koroista dha calculated Hierarchy and Netlist Bloscho reme seh ma amai Window appears his A ERES window shows the verilog representation of NOR gate Click OK to save the EON as a
9. Lecture 5 Microwind DCSH CSCI 5330 Digital CMOS VLSI Design Instructor Saraju P Mohanty Ph D NOTE The figures text etc included in slides are borrowed from various books websites authors pages and other sources for academic purpose only The instructor does not claim any originality UNT CSCE 5730 Digital CMOS VLSI Design 14 41 uai sis omer of ide a Lecture Outline e Microwind Tool e DCSH Tool e Silicon Tool Source 1 http www microwind org 2 Microwind Based Design http vsp2 ecs umass edu vspg 658 TA Tools microwind Microwind html CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS scover the power of ideas Microwind and DSCH Microwind is a tool for designing and simulating circuits at layout level The tool features full editing facilities copy cut past duplicate move various views MOS characteristics 2D cross section 3D process viewer and an analog simulator e DSCH is a software for logic design Based on primitives a hierarchical circuit can be built and simulated It also includes delay and power consumption evaluation e Silicon is for 3D display of the atomic structure of silicon with emphasis on the silicon lattice the dopants and the Silicon dioxide CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ide Microwind and DSCH e Download the followings from http www microwind org
10. RTH TEXAS Discover the power of ideas CSCE 5730 Digital CMOS VLSI Design Connect input button and output LED N ee HEI E Bu prins IN i l l pm advanced pros l nmus ME RES E Editing example sch e You now have NOR schematic ready Use your logic simulator to verify the functionality of your schematic The next step is to simulate the circuit and check for functionality e Click on Simulate gt Start Simulation e his brings up a Simulation EER EE N Control Window BEEN rr JAHE e Click on the input buttons to EE mm 4 Witte state Fin value DRegs Debug set them to 1 or 0 Red color in a switch indicates a 1 T CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas Microwind DSCH NOR Example Logic Inputs 00 E le s ME gt Em ly PP ot a oo a lal MAG S D ds simulatio z sx n p Fast Slow IY Wire state Pin value DRegs Debug Running absolute time 5660 000ne CPU times e Inputs O 1 Bl x 5 Bmw Pd of Rola L8 GLO Os BI s iz Running absolute timne 4560 000ne CPU time 1012 Inputs 10 m naeh el ero m sd Deche example sch TT EE EN N EET N feng Dech example sch File Edit Insert View Simulate Help ew aD
11. d antenna ratio matching supply rules ESD e Introducing CMOS 90nm technology A very simple four bit microprocessor designed and simulated at gate level with DSCHS3 CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover th the power of ideas
12. ibrary and place them in the editor window e E w PF foo AL WAG amp D d zs mo oH E mno o sl Dd el e EE di x SHES Bo g ale TL 4L TL Loaded C Dech 2 0E sport lEEE nmos SY CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas e Instantiate 2 NMOS and 2 PMOS transistors p Eu vEd x UI hb G OG 4 D m z ume Pr a e c TT Bal p m TITE Brus AYMDOI HDIaI X f IDEE i advanced draince ES H mos drairdraindrain nmuxs nmuaus SOUTE SOUILE oHG SNO Ep paste beginning UNI UNIVERSITY OF NORTH TEXAS Discover the power of ideas CSCE 5730 Digital CMOS VLSI Design e Connect the drains and Sources of transistors i Bl x X ce E np Ww FF Us Da nn A n BU QO 2 DI im SOUTCe qate BEE E i i f i l i LEE REM N H mrn i pamos 2ymbol library EF draince Brus drairdraindrain gate nmas nmas SOUTE SOUILE Sel Click at 55 25 e Connect Vdd and GND to the schematic e z Dech example ES Edit Insert View Simulate Help k P od Boo A E File E n SOUrce Gate x H MOS Basic advanced l drainze E pros draidrainlrain gos qate nmuius nmuas SOUrCe SOUrCe self se Le les Ed EG k B D amp JL zip Click at 35 4 UNI UNIVERSITY OF NO
13. one as GND Click on Metal 1 in the palette and then create the required rectangle in the layout window ELI _ e Open the layout editor window in Microwind Click File gt Select Founary and select X rul UESPPEEERICE DU eT Se NUT 2 example O x ele zx Im ic 7 Edit Simulate kfnpie Analysis Ip T A H Em vas Sar OPE EE m E BH n cmm T m En F i f 11 j x AA EO PELAAT ee 3 dA EE elds eB PE ta Qui S EER RATE HS 5 lambda 20 N 30 EH ap Bin ni N 100 du t 00 lambda ial 0 000 The current technology I CMOS 0 18um B Metal power supply 2 OO Ho Error CMOS 0 1 Bum j CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power c ideas Microwind DSCH NOR Example Layout e The next step is to build Then click on Generate the NMOS transistors device Ihe source of the Click on the transistor transistor is connected to symbol in the palette Set the GND rail the W L of the transistor BET owind 2 Mow Mabinor MSK pam nl x NT rowind 2 C mw2 lai i LEN iojx EERTITICUITA RR EES VOU Del le ule ra eaa BS le ER RATE bl ty TES 0 General inl xj 5 lambda MOS Path Logo Bus Mos Parame ters Width MOS
14. puts and the transistors in series diffusions are output of the WO shifted to a side and another poly transistors line is added as second transistor The diffusion is shared to save area and reduce capacitance EEN a EI b oo HE ER A Ela ioj x 5 dicrowind 2 C mw2 lab1 nor MSK 5 lambda D 5pm CMOS 0 18um Shaw palette menu CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas e he next step is to connect the poly to metal1 and then to metal2 he first symbol in the first row of the palette is the poly to metal1 contact lo xi EE 2 E mw2 labin Inor MSK o Pakre Poly inputs are connected output IS e Metal connected x Microwind 2 C mw2 labt 1nor HSK Fil View Edit Simulate mpile Analy ber lp 4 gt alette E EE ETE d WA i E kV Yt 5 lambda a 5 lambda MT D 5DDum des I D Sip Options Metal 5 E Metal 4 B Metal 3 e Xl I I XI XI XI XI xl Palvsilicon 2 Iv Polysilicon EN IF P Diffusion Bl IF N Diffusion II Iv M Vell v Shaw palette menu NT UNIVERSITY OF NORTH TEXAS Discover the power of ideas Polysilicon 2 Es IF Polysiicon MI P Diffusion B IF M Diffusion BLS Iv M Vell Li rd DAC Error
15. s CMOS 0 18pm Show palette menu CSCE 5730 Digital CMOS VLSI Design No Error CMOS 0 18pm e hen we connect the e he next step is to metall to metal2 contact connect the output to the previous contact Metal1 to Metal2 Once This is the 4th contact on again use the 4th the first row contact in the first row FEES gt Microwind 2 C mw lab1 no HSE le View Edt Simulate Compile Analysis He m Feta Microwind 2 C mw2 lab1 nor Pu File view Edit Simulate Compile Help EER nml xl 0O DOETE E TETELIIIT TEN WA I TEITE EE ES SODHM Show palette menu CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power of ideas Now we connect metal2 to the two inputs and one output and bring them to the top to go out of the cell Observe the two inputs left amp right and an output middle above the Vdd rail in dark blue color BLENDE MSK m nalysis Help he ile View Edit Simulate Compile A e pls ra teaa m gaba RATE H 2 Saved 55 boxes in C mw2Mlab1 nor MSK CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS Discover the power c ideas Now we label the inputs and output as In1 In2 and out
16. t visible at location 11 81 CMOS 0 18pm CSCE 5730 Digital CMOS VLSI Design UNIVERSITY CF NORTH TEXAS DN gn a D a ideas e Select Vdd Supply and GND from the To run the Simulation of your palette third row Also click on the circuit click on Simulate gt Start eng ow Aerei Simulation Depending on the input add it to the output Also extend the p well into the Vdd Rail The click on Edit 4 Sequences assigned at the Input gt Generate gt Contacts Select PATH he output Is observed in the and then in Metal choose Metal1 and simulation The power value is also N polarization given lt Microwind 2 AILE Ed a i Ele View Edt Simulate Compile Analysis Help oi ei Pra boe gt of RATE BOS TT iY Delay Gain between lint and out Evaluate MiniMax v Frequency out Time Scale E ns Step ps 0 00 o s00 ke More 30 Redraw C mwaMablnorMSK 2 boxes _ltr 2 017 CSCE 5730 Digital CMOS VLSI Design UNIVERSITY OF NORTH TEXAS iscover the power of 1 More Reading from Microwind Site http Intrage insa toulouse fr etienne microwind docs html e Introducing basic design rules MOS design rules interconnect design rules supply design rules e Technology influence on design rules resistance effect capacitance effect propagation e Specific design rules salicide Id
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