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SED1352 TECHNICAL MANUAL

1. 582 4 lt lt lt lt lt lt lt lt lt 5 SSESSSSE2282255ESSESESSS Dummy Pad 70 60 ip 50 Vpp WE Vss XSCL VD7 LCDENB VD6 VOE 80 VD5 IOCS TOW VD3 IOR MEMCS MEMW 4011 VAIO a SED1352D0B BHE VA8 OSCI VAT OSC2 90 VA6 THO VAS DBI VA4 DES VA3 DES VA2 DBA VAI 30 0 DBE RESET 19 Vss AB18 Vpp 100 10 T xu Dummy Pad I gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt tA O Q O Chip Size 4 400 mm x 4 400 mm Chip Thickness 0 400 mm Pad Size 0 090 mm x 0 090 mm Pad Pitch 0 140 mm Min X16B C 001 06 11 GRAPHICS NN EPSON 01352 PAD Coordinates
2. Figure 4 SDU1352B0C Rev 1 0 Schematic Diagram 4 of 7 SDU1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 20 Epson Research and Development Vancouver Design Center Figure 5 SDU1352B0C Rev 1 0 Schematic Diagram 5 of 7 SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 21 Vancouver Design Center REV gt S z v 2 d Gi 2 It IN 5 m E s 2 ae lt 4 x Ses L lt x lt amp z 5 Ji Ji E 5 lt I 4 E eoe p P z ea ZORA E eo
3. 558535 lt lt lt lt lt 555555 5 5 p Dummy Pad 70 60 LP 50 Vpp WF Vss XSCL VD7 LCDENB VD6 VOE 80 5 IOCS VD4 IOW VD3 IOR MEMCS MEMW 401 VAIO READY 9 BHE VA8 1 OSC2 90 VA6 DBO VA5 Dal VA4 DBZ VA3 a VA2 DB4 VAI DBS 30 VAO BS RESET Sn 19 Vss AB18 Vpp 100 1 10 20 7 Dummy Pad ig IIIJ PDPP PS MOM M See E E ee OUS ES ee ee ES oU tA Q Q Chip Size 4 00 mm x 4 00 mm Chip Thickness 0 400 mm Pad Size 0 090 mm x 90 mm Pad Patch 0 140 mm Min Figure 9 SED1352D0B Pad Diagram Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 20 Epson Research and Development Vancouver Design Center Table 4 1 SED1352D0A Pad Coordinates Pad Pin Pad Center Pad Pin Pad Center No Nama Coordinate No Name Coordinate X Y X Y 1 DB8 1 850 2 071 37 VAT 2 071 0 140 2 DB9 1 670 2 071 38 VA8 2 071 0 000 3 DB10 1 496 2 071 39 9 2 071 0 140 4 DB11 1 330 2 071 40 VA10 2 071 0 281 5 DB12 1 168 2 071 41 VDO 2 071 0 423 6 DB13 1 012 2 071 42 VDI 2 071 0 566 7 DB14 0
4. Pad Pin Pad Center Pad Pin Pad Center No Nama Coordinate No Name Coordinate x Y x Y 1 DB8 1 850 2 071 37 VAT 2 071 0 140 2 DB9 1 670 2 071 38 VA8 2 071 0 000 3 DB10 1 496 2 071 39 9 2 071 0 140 4 DB11 1 330 2 071 40 VA10 2 071 0 281 5 DB12 1 168 2 071 41 VDO 2 071 0 423 6 DB13 1 012 2 071 42 VDI 2 071 0 566 7 DB14 0 860 2 071 43 VD2 2 071 0 712 8 DB15 0 712 2 071 44 VD3 2 071 0 860 9 ABO 0 566 2 071 45 VD4 2 071 1 012 10 ABI 0 423 2 071 46 VD5 2 071 1 168 11 AB2 0 281 2 071 47 VD6 2 071 1 330 12 AB3 0 140 2 071 48 VD7 2 071 1 496 13 AB4 0 000 2 071 49 Vss 2 071 1 670 14 AB5 0 140 2 071 50 Vpp 2 071 1 850 15 AB6 0 281 2 071 51 VD8 1 850 2 071 16 AB7 0 423 2 071 52 VD9 1 670 2 071 17 8 0 566 2 071 53 VD10 1 496 2 071 18 9 0 712 2 071 54 VDI11 1 330 2 071 19 AB10 0 860 2 071 55 VD12 1 168 2 071 20 11 1 012 2 071 56 VD13 1 012 2 071 21 12 1 168 2 071 57 VD14 0 860 2 071 22 AB13 1 330 2 071 58 VD15 0 712 2 071 23 AB14 1 496 2 071 59 VAII 0 566 2 071 24 15 1 670 2 071 60 VA12 0 423 2 071 25 16 1 850 2 071 61 13 0 281 2 071 26 17 2 071 2 021 62 14 0 140 2 071 27 18 2 071 1 670 63 15 0 000 2 071 28 19 2 071 1 496 64 VWE 0 140 2 071 29 RESET 2 071 1 330 65 VCSO 0 281 2 071 30 VAO 2 071 1 168 66 VCS 1 0 423 2 0
5. 4 BIT SINGLE PANEL LP 240 PULSES M 4 UU YD pol n nn n n n n n n n n M WF X UD 3 0 LINE 1 LINE 2 LINE 3 X LINE 4 X LINE 239 LINE 240 LINE 1 LP WF la XSCL 80 CLOCK PERIODS gt XSCL ele UD3 0 0 X X UD2 m 12 X te X X X X 1 318 u X UD1 A X X Xe UDO va X18 XX X X XX 1 820 Example Timing for a 320x240 single panel X16B C 001 06 19 EN EPSON 01352 MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8 BIT SINGLE PANEL LP 480 PULSES LP 4 PULSES tp wF X UD 3 0 LD 3 0 A X LINE2 X LINES X LINE4 x LINE479 X LINE480 A une X umee LP XSCL 80 CLOCK PERIODS gt XSCL UD3 X X X X XX 1888 X UD2 12 X 110 X X Y X X Y 1 694 y UD1 13 X t X X Y X Y X X Y 1655 X UDO m 14 X 112 X X X X X X Y 1 636 LD3 15 Y 113 Y X X xX X X LD2 16 X 1 14 X X X X Y Y Y 1 638 Y LD1 uu 17 X 1 15 X x y Y Y X Y 1 639 Y L
6. MEMW Timing AB 19 0 BHE VALID tl lt P MEMCS t2 MEMW RE ih 6 d READY Hi Z Hi Z DB 15 0 Hi Z Hi Z 4 lt gt Figure 16 MEMW Timing Non 68000 Table 7 7 MEMW Timing Non 68000 3V 3 3V 5V Unit Symbol Parameter Min Typ Max Min Typ Max AB 19 0 BHE and MEMCS valid before MEMW 0 0 iis falling edge AB 19 0 BHE and MEMCS hold from MEMW 0 0 is rising edge t3 MEMW falling edge to READY falling edge 30 20 ns t4 MEMW falling edge to DB 15 0 valid 120 140 ns t5 DB 15 0 hold from MEMW rising edge 0 0 ns 3 5 3 5 t6 READY negated pulse width MCLK MCLK ns 20 10 Where MCLK period I fogc or 2 fosc or 4 fosc depending on which mode the chip is in see section 9 2 and 9 3 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 35 Vancouver Design Center MEMR Timing AB 19 0 VALID BHE tl t2 p 4 2 H MEMCS MEMR 4 t3 f t7 gt READY Hi Z Hi Z gt t5 DB 15 0 Hi Z STA Hi Z att Figure 17 MEMR Timing Non 68000 Table 7 8 MEMR Timing Non 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Max Units d AB 19 0 BHE and MEMCS valid before MEMR 0 0 n falling edge AB 19 0 BHE
7. 22 51 Summary of Configuration 25 D C CHARACTERISTICS ia a E eae eae ere 26 A C CHARACTERISTICS Re w n s x N RR W N 28 7 1 Bus Interface Timing 22 222 uoo g aras ee gos 1428 7 1 1 MC68000 Interface Timing 28 7 1 2 Non 68000 MPU Bus With READY or WAIT Signal 32 72 Clock Input Requirements 36 7 2 1 Recommended Clock Input 36 Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 4 Epson Research and Development Vancouver Design Center 73 Display Memory Interface Timing ll 027 7 3 1 Write Data to Display 37 7 3 2 Read Data From Display Memory 38 T4 LCD Interface Timings ve nk S Oe e gom 299 7 4 1 4 Bit Single LCD Interface 40 7 4 2 8 Bit LCD Interface Timing 41 8 HARDWARE REGISTER INTERFACE 46 8 1 RegisterDescriptions gt gt s pos s sz 46 8 2 Look Up Table Architecture sm n p 24 8 2 1 4 Level Gray Shade Mode 54 8 2 2 16 Level Gray
8. 55 8 3 Power Save Modes PSM1 95 8 3 1 Power Save 1 55 8 32 Power Save Mode 2 PSM2 22 52 6444 56 8 3 3 Power Save Mode Function Summary 56 8 3 4 Pin States in Power Save Modes 56 9 DISPLAY MEMORY 57 91 SRAM Configurations 57 9 1 1 8 BitMode 5 fava ah Eo oe ew E Buh 57 O12 16 Mode 2 m Z us Ung SS RAG Bea UR LEX Bae 59 9 2 SRAM Access Time ie eh m m GOR of ae ore ee ae aw 061 9 2 1 8 Bit Display Memory 61 9 2 2 16 Bit Display Memory Interface 61 93 Frame Rate Calculation 61 9 3 1 For Single Panel e pu pita me Me ale Sa RAP EE SP RE 61 9 3 2 For Dual Panel poce AE ee A eA ee 61 94 Memory Size Calculation o 1 9 5 Memory Size 62 10 MECHANICAL DATA 64 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 4 1 SED
9. Pad Pin Pad Center Pad Pin Pad Center No Nama Coordinate No Name Coordinate x Y x Y 73 LD1 1 496 2 071 88 BHE 2 071 0 000 74 LDO 1 670 2 071 89 OSCI 2 071 0 140 75 YD 2 021 2 071 90 OSC2 2 071 0 281 76 LP 2 071 1 850 91 DBO 2 071 0 423 77 WE 2 071 1 670 92 DBI 2 071 0 566 78 XSCL 2 071 1 496 93 DB2 2 071 0 712 719 LCDENB 2 071 1 330 94 DB3 2 071 0 860 80 VOE 2 071 1 168 95 DB4 2 071 1 012 81 IOCS 2 071 1 012 96 DB5 2 071 1 168 82 IOW 2 071 0 860 97 DB6 2 071 1 330 83 IOR 2 071 0 712 98 DB7 2 071 1 496 84 MEMCS 2 071 0 566 99 Vos 2 071 1 670 85 MEMW 2 071 0 423 100 VDD 2 071 1 850 86 MEMR 2 071 0 281 101 Dummy Pad 2 071 2 071 87 READY 2 071 0 140 102 Dummy Pad 2 071 2 071 Hardware Functional Specification Issue Date 99 07 28 Page 21 SED1352 X16 SP 001 16 Page 22 Epson Research and Development Vancouver Design Center 5 PINOUT DESCRIPTION Key I Input O Output Bidirectional Input Output Power pin COx CMOS level output driver x denotes driver type see Table 6 4 Output Specifications on page 27 TSx Tri state CMOS level output driver x denotes driver type see Table 6 4 Output Specifications on page 27 TSxD2 _ Tri state CMOS level output driver with pull down resistor typical values of 1OOKQ 200KQ at 5V 3 0V respectively x denotes driver type
10. WE UD 3 0 LD 3 0 LINE2 LINE3 LINE4 X X LINE479 LINE480 LINE2 LP WF XSCL 80 CLOCK PERIODS lt gt XSCL UD3 1 1 1 9 X X X X X 1 633 x 2 1 634 X UDI u 13 Y 111 X c X X 1 635 Y UDO m 14 Y 1 12 X A X X 1 686 X LD3 u 15 Y 143 Y Y X Y X X 1 637 X LD2 u 1 6 X 1 14 X X X X X X 1 638 1 1 17 Y 1 15 X X X 1 639 X LDO 1 8 X 1 16 X X Y 1 640 X Example timing for a 640x480 panel Figure 25 8 Bit Single Monochrome Panel Timing SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 45 Vancouver Design Center LP 240 PULSES LP 2 PULSES YD i qno E 2 gb 3 WF UD 3 0 LD 3 0 uve 1 241 y LINE 2 242 LINE 3 243 LINE 4 244 A ALINE 239 479XLINE 240 480 LINE 1 241 LINE meX LP WF la XSCL 160 CLOCK PERIODS gt M PEE UD3 X X X 1 637 X X UD2 uu 1 2 16 X X X X X X y 1 638 X UD X 12 X X X X Xe X upo MEME 21cm ET X LD3 gt 241 1 X 241 5 X X X Ya 1 63 y LD2 f 241 2 X
11. Symbol Parameter Min Typ Max Units tl LP period HT 24 ns hold from LP negated R1 bit 5 0 8tosc 24 ns t2b hold from LP negated bit 5 1 I3tosc 24 ns LP pulse width bit 5 0 24 ns t3b pulse width RI bit 1 5tosc 24 ns t4 WF delay from LP falling edge 0 20 ns t5 LP setup to XSCL falling edge R1 bit 5 0 2tosc 24 ns hold from XSCL falling edge R1 bit 5 0 2tosc 24 ns t b XSCL falling edge to LP falling edge R1 bit 5 1 only 13tosc 24 ns negated to XSCL falling edge bit 5 0 2tosc 24 ns t7b negated to XSCL falling edge bit 5 1 24 ns t8 XSCL period Atosc 24 ns 9 XSCL high width 2tosc 24 t0 XSCL low width 2tosc 24 ns 01 UD 3 0 setup to XSCL falling edge 2tosc 24 ns t12 UD 3 0 hold from XSCL falling edge 2tosc 24 ns t13a LP negated to XSCL rising edge R1 bit 5 0 0 ns t13b LP negated to XSCL rising edge bit 5 1 5tosc 24 ns Where number of horizontal panel pixels 16 tosc where tosc l fosc SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 41 Vancouver Design Center 7 4 2 8 Bit LCD Interface Timing Table 7 13 8 LCD Interface Tim
12. 16 001 06 6 001 06 9 5 1 SEN VCS1 O UB IOW gt IOW IOR gt IOR SBHE gt BHE yao 15 gt A0 15 RESET gt RESET 10 16 Decoder 4 VD0 7 amp ll 1 0 1 8 VD8 15 4 9 1 0 9 16 LA17 to LA23 MEMCS16 lt Decoder 4 Note Example implementation actual may vary SUPPORTED RESOLUTIONS Example Display Size Display 4 Gr 16 Gr SRAM CPU SRAM RAM ays ays Type Interface Interface X Y X Y 8 Kbytes 256 x 128 128 x 128 1 of 8Kx8 8 bit 8 bit 8 bit 8 bit 16 bit 16 Kbytes 320 x 200 200 x 160 2 of 8Kx8 16 bit 16 bit 32 Kbytes 512 x 256 256 x 256 1 of 32Kx8 8 bit 8 bit 1 of 8Kx8 and 40 Kbytes 512 320 320 256 1 of 32Kx8 8 bit 8 bit 8 bit 8 bit 16 bit 64 Kbytes 512x 512 512 x 256 2 of 32Kx8 16 bit 16 bit 128 Kbytes 1024 x 512 512 x 512 1 of 64Kx16 16 bit 16 bit BLOCK DIAGRAM Control Registers IOR IOW IOCS MEMCS MEMR BHE AB 19 0 Bus Port Signal Decoder Sequence gt LCDENB Translation Controller Memory e Look Up LCD UD 3 0 READY lt 4 Decoder Table Panel LDI3 0 Interface LP YD WF XSCL DB 15 0 5 Bus onversion enerator Display Data CPU CRT For
13. CS 8Kx8 WE F Ey n Figure 34 16 Bit Mode 16K bytes SRAM Hardware Functional Specification Issue Date 99 07 28 Page 59 SED1352 X16 SP 001 16 Page 60 Epson Research and Development Vancouver Design Center VDO 7 VWE SED1352 VCSO 0 14 VCS1 VD8 15 WE 32Kx8 CS CS 32Kx8 WE po Figure 35 16 Bit Mode 64K bytes SRAM VWE SED1352 VCSO VCS1 0 15 VDO0 7 VD8 15 gt O gt O WE 64Kx16 LB UB AO 15 1 8 9 16 SED1352 X16 SP 001 16 Figure 36 16 Bit Mode 128K bytes SRAM Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Page 61 Vancouver Design Center 9 2 SRAM Access Time 9 2 1 8 Bit Display Memory Interface Table 9 1 8 Bit Display Memory Interface SRAM Access Time Display Mode 3V 3 3V 5V 16 level gray shades Access time lt 1 fosc 5005 Access time lt 1 fosc 30ns 4 level gray shades Access time lt 2 fosc 5005 Access time lt 2 fosc 30ns 9 2 2 16 Bit Display Memory Interface Table 9 2 16 Bit Display Memory Interface SRAM Access Time Display Mode 3V 3 3V 5V 16 level gray shades Access time lt 2 fosc 50ns Access time lt 2 fosc 30ns 4 level gray shades Access time lt 4
14. Connector CPU BUS Comments Pin No Pin Name 1 SDO Connected to DBO of the SED1352 2 SD1 Connected to DB1 of the SED1352 3 SD2 Connected to DB2 of the SED1352 4 SD3 Connected to DB3 of the SED1352 5 GND Ground 6 GND Ground 7 SD4 Connected to DB4 of the SED1352 8 SD5 Connected to DB5 of the SED1352 9 SD6 Connected to DB6 of the SED1352 10 SD7 Connected to DB7 of the SED1352 11 GND Ground 12 GND Ground 13 SD8 Connected to DB8 of the SED1352 14 SD9 Connected to DB9 of the SED1352 15 SD10 Connected to DB10 of the SED1352 16 SD11 Connected to DB11 of the SED1352 17 GND Ground 18 GND Ground 19 SD12 Connected to DB12 of the SED1352 20 SD13 Connected to DB13 of the SED1352 21 SD14 Connected to DB14 of the SED1352 22 SD15 Connected to DB15 of the SED1352 23 RESET Connected to the RESET signal of the SED1352 24 GND Ground 25 GND Ground 26 GND Ground 27 12V 12 volt supply 28 12V 12 volt supply 29 SBHE Connected to the BHE signal of the SED1352 30 IOCHRDY Connected to the READY signal of the SED1352 31 IOSC Connected to the IOCS signal of the SED1352 32 MEMCS Connected to MEMCS signal of the SED1352 SED1352 X16 AN 002 09 SDU1352B0C Rev 1 0 Evaluation Board User Manual Issue Date 98 10 07 Epson Research and Development Vancouver Design Center Table 1 6 CPU BUS Connector H2 Pinout Connec
15. Monochrome LCD Support P wer Save Modes mss edges uum es geo DR tee pU Adjustable LCD Panel Negative Power Adjustable LCD Panel Positive Power Supply Crystal Support atio tere RE TRAE RAE P A W ls k u Q Sus eum Somers CPU Bus Interface Header Strips schematic Notes x venom DN LS REV VERE e vr uw Ee s PARTS LIST ase eo ERR IRA AT EO AUR RORIS e TRIER A ee SDU1352B0C REV 1 0 SCHEMATIC DIAGRAMS SDU1352B0C Rev 1 0 Evaluation Board User Manual Issue Date 98 10 07 Page 3 SED1352 X16 AN 002 09 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 1 1 Configuration DIP Switch Settings 8 Table 1 2 Mapping Example 8 Table 1 3 Decoding Jumper Setting 22e 8 Table 1 4 LCD Signal Connector J1 Pinout 9 Table 1 5 CPU BUS Connector H1 Pinout 10 Table 1 6 CPU BUS Connector H2 Pinout 11 List of Figures Figure 1 SDU1352B0C Rev 1 0 Schemat
16. number of pixels per scan line 1 2 pixels byte 2 bytes word val PanelX 4 1 For 16 gray shades only WriteRegister 2 val amp Oxff Line Byte Word Count Register WriteRegister 3 val gt gt 8 amp 0x01 Line Byte Word Count Power Save Reg BytesPerScanLine is a global variable BytesPerScanLine PanelX 2 For 16 gray shades only Total Display Line Count Register Screen 1 Display Line Count Register To show a full image on Screen 1 copy the Total Display Line Count into the Screen 1 Display Line Count Assume that all panels smaller than 400 lines are in 4 bit mode if 1 lt 400 val ReadRegister 1 val amp 0x04 WriteRegister 1 val Write to Mode Register LCD Data Width 4 bits val PanelY A dual panel LCD will of course have two panels Each panel will show either the top or bottom half of the image which is half of the vertical resolution if PanelType TYPE_DUAL val 2 Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 50 Epson Research and Development Vancouver Design Center WriteRegister 4 val amp Oxff Write to Total Display Line Count Reg WriteRegister 0x0a val amp Oxff Write to Screen 1 Display Line Count Reg WriteRegister 5 val 8 amp 0x03
17. Epson Research and Development Vancouver Design Center OxF8 Ox6C 0x66 0x66 0x66 Ox6C OxF8 0x00 D OxFE 0x62 0x68 0x78 0x68 0x62 OxFE 0x00 E OxFE 0x62 0x68 0x78 0x68 0x60 OxFO 0 00 0 3 0x66 0 0 OxCO OxCE 0x66 Ox3E 0x00 G OxCC OxCC OxCC OxFC OxCC OxCC OxCC 0x00 4 0x78 0x30 0x30 0x30 0x30 0x30 0x78 0x00 OxlE Ox0C Ox0C Ox0C OxCC OxCC 0x78 0x00 274 0 66 Ox6C 0 78 0 6 0x66 OxE6 0 00 OxFO 0x60 0x60 0x60 0x62 0x66 OxFE 0 00 Efe 0 6 OxEE OxFE OxFE OxD6 OxC6 OxC6 0x00 M 0xC6 OxE6 OxF6 OxDE OxCE 0xC6 OxC6 0x00 N 0x38 Ox6C OxC6 OxC6 OxC6 Ox6C 0x38 0x00 tf OxFC 0x66 0x66 Ox7C 0x60 0x60 OxFO 0 00 P 0x78 OxCC OxCC OxCC OxDC 0x78 Ox1C 0x00 OxFC 0x66 0x66 Ox7C 0x6C 0x66 OxE6 0 00 0x78 OxCC OxEO 0x70 Ox1C OxCC 0x78 0x00 5 OxFC OxB4 0x30 0x30 0x30 0x30 0x78 0 00 Z XE OxCC OxCC OxCC OxCC OxCC OxCC OxFC 0x00 ZU OxCC OxCC OxCC OxCC OxCC 0x78 0x30 0x00 V 0xC6 OxC6 OxC6 OxD6 OxFE OxEE 0 6 0x00 W 0 6 OxC6 Ox6C 0x38 0x38 0 6 OxC6 0x00 X OxCC OxCC OxCC 0x78 0x30 0x30 0x78 0x00 F LL OxFE 0xC6 Ox8C 0x18 0x32 0x66 OxFE 0 00 7 pdisplayFirstColumn pdisplayStart pDisplay pdisplayFirstCol
18. Intialize SED1352 registers INPUTS This function looks at the followingl global variables to determine the appropriate register settings 1 PanelY PanelType OUTPUTS The following Panel global variables are changed lGrayLevel BytesPerScanLine void Initialize void static unsigned int val static unsigned int x PanelGrayLevel 16 Mode Register Display ON Panel SINGLE Mask XSCL NOT MASKED LCDE NOT ENABLED Gray Scale 16 Gray Shades 4 bits pixel LCD Data Width 8 bit data transfer Memory Interface 16 bits RAMS Addressing for 8Kx8 SRAM val 0x8C if PanelType TYPE DUAL val 0x40 Set panel type to DUAL Wri val amp 0x04 teRegister 1 Set val LCD Data Width to 4 bit data transfer Write to Mode Register Line Byte Word Count Register SED1352 X16 BG 007 04 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Page 49 Vancouver Design Center Bits 0 7 are in AUX 2 Bit 8 is in AUX 3 Because the Memory Interface is set to 16 bits the Line Byte Word Count Register counts in words addition there are 2 pixels byte since there are 16 gray levels To calculate the number of words in a scan line use the following formula
19. Point to the beginning of the next scan line pVideoStart BytesPerScanLine pVideo pVideoStart howText ESCRIPTION Writes text to the LCD panel the letters A Z characters ar and the space NOTES background color mim black The character is translated to a Text must only contain character All other replaced by spaces It is assumed that a pixel set to a value of 0 represents the block character void ShowText unsigned char far pdisplayStart static const unsigned char pFont static unsigned char _far pdisplayFirstColumn static unsigned char _far pDisplay static unsigned char ch static unsigned int y val Display sta Each letter in the font is 8 x 8 bits tic const unsigned char font 28 8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 char str int color 0x00 blank OxFF OxFF OxFF OxFF OxFF OxFF OxFF 0x30 0x78 OxCC OxCC OxFC OxCC OxFC 0x66 0x66 Ox7C 0x66 0x66 0x3C 0x66 0 0 OxCO OxCO 0x66 Programming Notes and Examples Issue Date 98 10 08 OxCC OxFC 0 3 block B OXFE 0 00 0 00 0 00 char b SED1352 X16 BG 007 04 Page 56
20. 48411 E g S98 5 amp ge ga 2 8 4 508 a 8 i Sam is wee 3 55555095 ok 8 3 m g d 5 Ik E gt 5 5 2 lr j a E 5 i 5 8 a a 5 E 8 V4 5 E E x al E 8 T a 8 5 x 2 a 5 DE EN a a a E ES 8 8 E E E Be fanz Figure 2 SDU1352B0C Rev 1 0 Schematic Diagram 2 of 7 SDUI1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 18 Epson Research and Development Vancouver Design Center REV C VDC DU1352BOC YSTEMSINC VD S MOSSY e DocumentNumber SRM20100LTM 70 SRM20100LTM 70 Figure 3 SDU1352B0C Rev 1 0 Schematic Diagram 3 of 7 SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 19 Vancouver Design Center
21. DESCRIPTION Show split screen INPUTS None RETURN VALUE None void SplitScreen void SED1352 X16 BG 007 04 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Page 59 Vancouver Design Center static unsigned char _far pVideoImagel static unsigned char _far pVideoImage2 static unsigned long ImageSize static unsigned int OriginalLineCount static unsigned int val static unsigned int MinLineCount static unsigned int MaxVirtualScanLines Initialize ClearLCDScreen For 64k only FP SEG pVideolmagel 0xd000 FP OFF pVideolmagel 0x0000 Calculate starting video memory location for image 2 by finding the last location of image 1 ImageSize BytesPerScanLine PanelY Because the image size is limited to a maximum of 320 x 240 and there is 64k of video memory there is enough memory available FP SEG pVideoImage2 FP OFF pVideoImage2 0xd000 unsigned int ImageSize ShowVerticalBars pVideoImagel ShowHorizontalBars pVideoImage2 Show text The lightest gray shade is set to PanelGrayLevel 1 ShowText pVideoImagel SPLIT SCR ShowText pVideoImage2 SPLIT SCR I EN IMAGE ONE PanelGrayLevel 1 EN IMAGE TWO PanelGrayLevel 1 I Set Screen
22. R W gt IOW Note Example implementation actual may vary Interface with 8 Bit 780 MPU and 16Kbytes SRAM 2 of 8K x 8 Z80 po SED1352 MREQ p 10 to 15 VD0 7 ME Decoder hb IOCS amp VWE IORQ A0 to A15 ABO to 15 WE WE to D7 DBO to DB7 64 Kbit 64 Kbit WAIT 4 READY M WR gt MEMW RD 1 gt MEMR voco IOR VCS1 L jow VA0 12 RESET q gt RESET Note Example implementation actual may vary 16 001 06 6 001 06 Interface with 16 Bit 8086 MPU 64Kbytes SRAM 2 of 32K x 8 8086 Maximum mode 8288 SED1352 CLK MENR CLK VD0 7 AMWC amp L READY READY Sis gt sis VWE RESET p RESET 50 gt sos IORC IOR RDY DEN AIOWCAI IOW 8284A WE ALE 256 Kbit A16 to 19 AB16 to ABI9 CS Decoder Q gt M IO L 0 15 VOSO VAO 14 BHE P BHE BHE 16 ADO to AD15 AQ to Al6 D MEMCS Ly STB p IOCS WE 256 Kbit D0toDI5 6
23. x horizontal pixels 2 bytes per scan line This means that there x horizontal pixels 4 words per scan line Since the Memory Interface is set to 16 bits the Line Byte Word Count vefers to words val 1 4 1 BytesPerScanLine PanelX 2 WriteRegister 2 val amp Oxff Line Byte Count Register WriteRegister 3 val gt gt 8 amp 0x01 Line Byte Count Power Save Reg PanelGrayLevel 16 ShowVerticalBars pVideo Show text The lightest gray shade is set to PanelGrayLevel 1 ShowText pVideo VERTICAL BARS AT SIXT EN GRAY SHADES PanelGrayLevel 1 Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 54 Epson Research and Development Vancouver Design Center FUNCTION ShowVerticalBars DESCRIPTION Displays a series of vertical bars each with a different gray shade For 4 gray levels each vertical bar is 40 pixels wide For 16 gray levels each vertical bar is 20 pixels wide INPUTS Video address which points to beginning of vertical bars This address must be at the leftmost column of the display RETURN VALUE None void ShowVerticalBars unsigned char far pVideo static unsigned int y static unsigned int Bar BarWidth val static unsigned char _far pVideoStart
24. IOW Timing AB 9 0 BHE VALID 10 5 tl gt lt 5 lt t2 gt IOW t3 p t4 gt DB 15 0 Hz VALID Hz Figure 14 IOW Timing Non 68000 Table 7 5 IOW Timing Non 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units tl AB 9 0 BHE and IOCS valid before IOW falling 10 0 edge 2 AB 9 0 BHE IOCS hold from IOW rising edge 20 10 ns 3 DB 15 0 setup to IOW rising edge 20 10 ns t4 DB 15 0 hold from IOW rising edge 20 10 ns t5 Pulse width of IOW 30 20 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 33 Vancouver Design Center IOR Timing AB 9 0 VALID BHE IOCS tL PEN IOR 3 gt t4 DB 15 0 Hi Z SRI t Hi Z P t5 Figure 15 IOR Timing Non 68000 Table 7 6 IOR Timing Non 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units tl AB 9 0 BHE and IOCS valid before IOR falling 10 0 n edge 2 AB 9 0 BHE and IOCS hold from IOR rising edge 20 10 ns t3 IOR falling edge to DB 15 0 valid 80 60 ns 4 DB 15 0 hold from IOR rising edge 25 20 ns t5 IOR rising edge to DB 15 0 hi z delay 30 30 ns Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 34 Epson Research and Development Vancouver Design Center
25. 33 Table 7 7 MEMW Timing 68000 34 Table 7 8 MEMR Timing 68000 35 Table 7 9 Clock Input Requirements lle re 36 Table 7 10 Write Data to Display 37 Table 7 11 Read Data From Display 38 Table 7 12 4 Bit Single LCD Interface 2 40 Table 7 13 8 Bit LCD Interface 41 Table 8 1 Maximum Value of Line Byte Count Register 8 Bit Display Memory Interface 48 Table 8 2 Maximum Value of Line Byte Count Register 16 Bit Display Memory Interface 48 Table 8 3 Power Save Mode 49 Table 8 4 ID Bit Usage kuka ae ole Be ee d ae eR dp d 53 Table 8 5 Power Save Mode 2 2 2 2 55 Table 8 6 Power Save Mode Function Summary 56 Table 8 7 Pin States in Power Save 56 Table 9 1 8 Bit Display Memory Interface SRAM Access Time 61 Table 9 2 16 Bit Display Memory Interface SRAM Access 61 Table 9 3 Memory Size Requirement Number of Horizontal Pixels 640 62 Ta
26. 480 _ 1 239 OEFh Total Display Line Count 5 5 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 15 Vancouver Design Center 3 GRAY SHADES AND LOOK UP TABLES This section discusses memory formats and Look Up Table formats for the SED1352 3 1 Pixels A pixel is physically stored in display memory as a series of bits The more bits the more gray shades the pixel can show With only one bit the pixel can only show two different combinations of gray shades 0 or 1 With two bits the pixel can show four different combinations of gray shades 00b 01b 10b or 11b Similarly four bits allow 16 different combina tions of gray shades 0000b 0001b 0010b 1111b The SED1352 can be programmed to use either two bit or four bit pixels The following sections show how these pixels are stored in display memory 3 1 1 Two Bit Pixels To store two bit pixels four pixels are grouped into one byte of display memory as shown below Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 2 Pixel 2 Pixel 3 Pixel 3 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 When these pixels are shown Pixel 0 is seen to be left of Pixel 1 Pixel 1 is seen to be left of Pixel 2 and so on Figure 1 Pixel Storage for 2 Bits 4 Gray Shades In One Byte of Display Memory 3 1 2 Four Bit Pixels To store four bit pix
27. VLCD power supply used on the SDU1352 requires a logic 1 to disable it As the signal LCDENB is a logic 0 at power up it is inverted by ex ternal logic to disable VLCD and prevent damaging the panel connected to the SDU1352 Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel SDUI1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 14 Epson Research and Development Vancouver Design Center 1 3 7 Adjustable LCD Panel Positive Power Supply Most single Monochrome 640x480 STN LCD panels require a positive power supply to provide between 23V and 40V 45 For ease of implementation such a power supply has been provided as an integral part of this design The signal VDDH can be adjusted by R8 100K potentiometer to provide an output voltage from 23 V to 40 V and is enabled disabled by the control signal LCDENB Note LCDENB is directly controlled by register AUX 01 bit 4 of the SED1352 The VDDH power supply used on the SDU1352 requires a logic 1 to disable it As the signal LCDENB is a logic 0 at power up it is inverted by ex ternal logic to disable VLCD and prevent damaging the panel connected to 5001352 Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 1 3 8 Crystal Support The input crystal frequency may be up to 25
28. bits 3 0 palette data application specific 001 increment palette address 101 write monochrome LUT data 010 increment palette address 010 write monochrome LUT data ollel ojl oj o 011 increment palette address gt C i e a S OGI G O Till write monochrome LUT data SED1352 X16 BG 007 04 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Page 13 Vancouver Design Center Notes See Also AUX OEh 0000 0100 increment palette address AUX OFh 0000 0000 write monochrome LUT data AUX OEh 0000 0101 lincrement palette address AUX OFh 0000 0101 write monochrome LUT data AUX OEh 0000 0110 increment palette address AUX OFh 0000 1010 write monochrome LUT data AUX OEh 0000 0111 increment palette address AUX OFh 0000 1111 write monochrome LUT data AUX OEh 0000 1000 lincrement palette address AUX OFh 0000 0000 write monochrome LUT data AUX OEh 0000 1001 Jincrement palette address AUX OFh 0000 0101 write monochrome LUT data AUX OEh 0000 1010 lincrement palette address AUX OFh 0000 1010 write monochrome LUT data AUX OEh 0000 1011 lincrement palette address AUX OEh 0000 1111 Jincrement palette address AUX OFh
29. tl AB 9 1 and IOCS valid before AS falling edge 10 ns AB 9 1 hold from AS rising edge 20 ns t2b IOCS hold from AS rising edge ns t3 AS falling edge to DTACK falling edge 35 25 ns t4 AS rising edge to DTACK hi z delay 45 25 ns t5 AS falling edge to DB 15 0 valid 80 60 ns t6 DB 15 0 hold from AS rising edge 25 20 ns t7 AS rising edge to DB 15 0 hi z delay 35 30 ns Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 30 Epson Research and Development Vancouver Design Center Timing AB 19 1 MEMCS X X tl t2 AS UDS LDS INVALID R W 4 DTACK Hi Z Hiz t3 lt f 6 j t6 DB 15 0 Hi Z SAGE Hi Z Figure 12 MEMW Timing 68000 Table 7 3 MEMW Timing 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units AB 19 1 and MEMCS valid before AS falling edge 0 0 ns t2 AB 19 1 and MEMCS hold from AS rising edge 0 0 ns 35 355 3 AS falling edge to DTACK falling edge MCLK MCLK ns 20 10 t4 AS rising edge to DTACK hi z delay 45 22 ns t5 AS falling edge to DB 15 0 valid 120 140 ns t6 DB 15 0 hold from AS rising edge 0 0 ns Where MCLK period l fosc or 2 fosc or 4 f
30. 8 bit 350 ns 370 ns 150 ns 170 ns 750ns 770 32 350ns 370ns SHE 1 Memory more than 128KB cannot be supported by SED1352 2 Memory more than 64KB can only be supported through 16 bit display memory interface KB K byte 1024 bytes Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 64 Epson Research and Development Vancouver Design Center 10 MECHANICAL DATA 23 2 0 04 k i 20 0 0 1 lt 140504 17 2 0 04 0 15 0 05 200 0 1 0 35 rl 2 7 All dimensions in mm Figure 37 Mechanical Drawing QFP5 100pin S2 SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Page 65 Vancouver Design Center 16 0 04 0 1 P 14 0 75 51 76 50 14 0 04 16 0204 i Index v 0 168 0 1 5 gt lt A i k 0 5 0 2 NE 9519 All dimensions mm Figure 38 Mechanical Drawing QFP15 100pin Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 66 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 EPS
31. START ADDRESS LSB 00h START ADDRESS MSB 80h SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 25 Vancouver Design Center 4 2 2 Display Start Address Registers This section illustrates how to properly calculate the values for the Screen Start Address Registers for a given LCD panel resolution However this section is limited to single panel displays refer to Section 5 4 4 Dual Panel LCD on page 38 to program the Screen Start Address Registers for a dual panel display In the following example the Display Start Address Registers are programmed for a 16 gray shade 320 x 240 single monochrome display The technique shown however can also be used to calculate the memory map of other resolutions In addition reference is made to the SDU1352B0x evaluation board other hardware implementations of the SED1352 may assign different display and port addresses from those of the SDU1352B0x Refer to the DU1352B0x Evaluation Board User s Manual for more information on these hardware issues Example 7 Program the Display Start Address Registers for a 16 gray shade 320 x 240 single mono chrome LCD panel the display is attached to the 5001352 0 evaluation board with 64k of display memory 1 Calculate the number of bytes per scan line 16 gray shades gt 4 bits per pixel 4 bits per pixel 2 pixels per byte ixel li 2 number of bytes per scan line Pixels
32. Table 3 3 SED1352F0B Black To White Look Up Table for 4 Gray Shades Table 4 1 Memory Size Table 5 1 Smallest Number of Pixels for Table 5 2 Power Save Mode Table 5 3 Power Save Mode 5 Table 5 4 Power Save Mode Function List of Figures Figure 1 Pixel Storage for 2 Bits 4 Gray Shades In One Byte of Display Memory Figure 2 Pixel Storage for 4 Bits 16 gray shades in One Byte of Display Memory Figure 3 4 Level Gray Shade Mode Look Up Table Architecture Figure 4 16 Level Gray Shade Mode Look Up Table Architecture Figure 5 Memory Map for 320 x 240 LCD Panel with 16 Gray Shades Figure 6 Memory Map Example for 320 x 240 LCD Panel with 4 Gray Shades Figure 7 Memory Map Example for 640 x 200 LCD Panel with 16 Gray Shades Figure 8 640 480 1 Figure 9 Font for Message Figure 10 Display Memory Contents for Message Figure 11 Memory Map for Split Figure 12 320 x 240 Single Panel for Split Figure 13 640 x 480 Dual Panel for Split
33. 15 32 LookUpTable EU D ROO m s R qoe mU RUE S hom BoP gt mc LO 32 1 EUT Registers S suo x Bon ov T wee 16 3 2 2 Look Up Table Description 17 3 2 3 Four Gray Shades Two 1 19 3 2 4 Sixteen Gray Shades Four Bits Pixel 21 4 DISPLAY MEMORY MODELS 22 4l Registers 22252052 mehr 18 RR UM RE uy deor euer AA 22 Description eti ose tg het Dos ee eae a RN oe m es uad 4 2 1 SDU1352B0x Evaluation Board Display Memory 24 4 2 2 Display Start Address 1 25 4 3 Common Display Memory Requirements for LCD Panel 512585 27 5 5 28 51 Virtual Displays 28 S4 Registers IL Shes ae Dau p EUR Rer se ds 28 51 2 Description V tes Ge be ex ap eu du HE v AERE Sexe Webs eu 29 5 2 Bitmaps and Text 2 2 30 933 RegistetS lt u o Rom Geox uos Gn m WS Reve 2 5 32 5 3 1 Indexed Addressing 32 5 3 2 Direct Addressing s wa sm ne me URN PR BUR nues bu V qus 32 JA SphtScreens y uo m ae ege e Aog drew S94 DA Registefs
34. 2 5 Power Management 2 5 4 bl ek usu d 3 TYPICAL SYSTEM BLOCK DIAGRAMS 12 3 1 16 Bit MC68000 MPU 225255220554 eg eg hk gt 12 3 1 1 MPU with READY WAIT signal 13 3212 ISAC BUS uo o Po yo ee A AS w N ee ee ow ad veli AG 14 32 Internal Block Diagram 15 33 Functional Block Descriptions 1 3 31 Bus Signal Translation ss eR SO HORN Me wd 15 3 32 Control Registers sanki E Eb dow Geet iP S 15 3 3 3 Sequence Controller lt 7 s ene eee ew RES 15 3 34 LCD Panel Interface 2222 22 22 RR RR 15 2359 Look Up Table dew eRe ee Eb ba ws 16 3 3 6 Decoders Sa ea et mee um S wd 16 3 3 7 Memory Decoder sia eae Rot RE Seen el s 16 3 3 8 Data Bus Conversi n 222552225455 SPEAR ee E MES 16 3 3 9 Address Generator es Rd So ae a eee 16 3 3 10 CPU CRT Selector sg RR eee Roe eun 8 h S 16 3 3 11 Display Data Formatter 16 3 3 12 Glock Inputs Timings sero ex RU obere ee NR e RS 16 3 3 13 SRAM Interface uuo qu dde eee Nue eb v drea 16 4 PINOUT DIAGRAM 17 PINOUT 5
35. Display Data gt CPU CRT Formatter Timing Generator Selector Power Save Oscillator SRAM Interface s 20009 Sp L 9 E E a lt 42 Q Figure 6 Internal Block Diagram 3 3 Functional Block Descriptions 3 3 1 Bus Signal Translation According to configuration setting VD2 Bus Signal Translation translates MC68000 type CPU signals or READY type MPU signals to internal bus interface signals 3 3 2 Control Registers The fifteen internal Control and Configuration Registers are accessed by direct mapping or by using the built in internal index register 3 3 3 Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings 3 3 4 LCD Panel Interface The LCD Interface performs frame rate modulation for passive monochrome LCD panels Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 16 Epson Research and Development Vancouver Design Center 3 3 5 Look Up Table The Look Up Table contains sixteen 4 bit wide palettes that can be configured as one 16x4 palette or four 4x4 palettes used for the re mapping of gray scale outputs See Look Up Table Architecture on page 54 3 3 6 Port Decoder According to configuration settings VD1 VD12 VD4 IOCS and address lines AB9 1 the Port Decoder validates a given cycle 3 3 7 Memory Decoder According to configurat
36. the 16 position palette is arranged into four 4 position banks These two bits control which bank is currently selected These bits have no effect in 16 level gray mode 4 bits pixel ID Bits After power on or hardware reset these bits can be read to identify the current revision of the SED 1352 These same bits are used to identify the pin compatible SED1352F0x and would only be used in system implementations where common software is utilized As these bits are R W they must be read before being written in order to be used as ID bits Table 8 4 ID Bit Usage Aux 0Eh h Chip bit 5 bit 4 SED1353 0 0 Power On F352 0 1 RESET SED1352F0B F1B DOB 1 0 SEDI352F0A 1 1 Palette Address Bits 3 0 These 4 bits provide a pointer into the 16 position Look Up Table currently selected for CPU R W access The Look Up Table configuration e g 1 2 banks does not affect the R W access from the CPU as all 16 positions can be accessed sequentially Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 54 Epson Research and Development Vancouver Design Center AUX 0Fh Look Up Table Data Register I O address 1111b Read Write Palette Data Palette Data Palette Data Palette Data nia nia nia nia Bit 3 Bit 2 Bit 1 Bit 0 bits 3 0 Palette Data Bits 3 0 These 4 bits are the gray shade values used for display data output T
37. 68000 IOW Timing 68000 IOR Timing 68000 Timing 68000 MEMR Timing 68000 Clock Input Requirements Recommended Clock Interface Write Data to Display Memory Read Data From Display Memory LCD Interface LCD Interface Pixel Data Position 4 Bit Single Monochrome Panel Timing 8 Bit Single Monochrome Panel Timing 8 Bit Dual Monochrome Panel Timing 4 Level Gray Shade Mode Look Up Table Architecture 16 Level Gray Shade Mode Look Up Table Architecture 8 Mode 8K bytes 5 8 Bit Mode 16K bytes 8 Bit Mode 32K bytes 8 Bit Mode 40K bytes 8 Bit Mode 64K bytes 16 Bit Mode 16K bytes SRAM 16 Bit Mode 64K bytes SRAM 16 Bit Mode 128K bytes SRAM Mechanical Drawing QFPS 100pin S2 Mechanical Drawing QFP15 100pin Hardware Functional Specification Issue Date 99 07 28 Page 7 SED1352 X16 SP 001 16 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 9 Vancouve
38. DBO to DB15 CSH gt 9 OE 4 gt RESET VCS1 READY VD8 15 Note Example implementation actual may vary Interface with 8 Bit ISA Bus and 40Kbytes SRAM 1 of 8K x 8 and 1 of 32K x 8 8 Bit ISA Bus SED1352 REFRESH SA16 SA13 D gt MEMCS4 VD0 7 ecoder 4 SENE SMEMW MEMW SMEMR MEMR WE IOGHRDY Bd 64 Kbit 00 to SD7 DBO to DB7 TM SAO to SA19 ABO to ABI9 Q SA10 to SA15 Do 3 SA I or 4 to SA9 VCSO gt IOCS VA0 14 AEN IOW IOW M IOR gt IOR WE RESET 256 Kbit 1 CS OWS 4 Decoder 1 4 1 VCSI Note Example implementation actual may vary X16B C 001 06 3 GRAPHICS _ NE EPSON 01352 Interface with 16 Bit ISA Bus and 128Kbytes SRAM 1 of 128 x 8 16 bit ISA Bus REFRESH SED 1352 MEMCS MEMW MEMR READY SA16 5 14 Decoder SMEMW SMEMR IOCHRDY SDO to SD15 SAO to 5 19 DBO to DB15 ABO to AB19 VCSO LB 1 Mbit SA 1 or 4 to SA9 SA10 to 5 15 Decoder
39. Total Disp Line Cnt MSB WF Count Reg WriteRegister 0x0b val gt gt 8 amp 0x03 Scrn 1 Disp Line Count Reg MSB Set Screen 1 Display Start Address to beginning of video memory WriteRegister 6 0 Write to Screen 1 Display Start Address Register WriteRegister 7 0 Screen 2 Display Start Address Register If using a dual panel the Screen 2 Display Start Address must point to the second half of the image in video memory y if PanelType TYPE DUAL val unsigned int ReadRegister 3 amp 0x01 lt lt 8 ReadRegister 2 ttval val PanelY 2 WriteRegister 8 val amp Oxff WriteRegister 9 val gt gt 8 else On a single panel Screen 1 was programmed to show all of its lines Consequently Screen 2 will not be seen and so the Screen 2 Display Start Address will have no observable effect For convenience set the screen 2 address to 0 WriteRegister 8 0 WriteRegister 9 0 When the SDU1352B0x is set to 64k video memory exists from D000 0000 to D000 FFFF When the SDU1352B0x is set to 128k video memory exists from C000 0000 to D000 FFFF As far as the SED1352 is concerned video memory ALWAYS begins at 000 0000 even if there is no physical memory present SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Resea
40. Vertical scanning start pulse A logic 1 on this signal sampled by YD FPFRAME O 78 75 the LCD module on the falling edge of LP is used by the panel row driver Y driver to indicate the start of the vertical frame LCDENB 82 79 LCD enable signal output It can be used externally to turn off the panel supply voltage and backlight VESA Flat Panel Display Interface Standard FPDI 1 X16B C 001 06 GRAPHICS NN EPSON Clock Inputs F1B Pin Pin Name Pin D0B Pad Description This pin along with OSC2 is the 2 terminal crystal interface when using OSCI I 92 89 2 terminal crystal as the clock input If an external oscillator is used as a clock source then this pin is the clock input This pin along with is the 2 terminal crystal interface when using a OSC2 93 90 2 terminal crystal as the clock input If an external oscillator is used as a clock source then this pin should be left unconnected Power Supply F1B Pin n Pin Name Type Pin DOB Pad Description Vpp P 3 53 50 100 Voltage supply Vss P 2 52 49 99 Voltage ground SUMMARY OF CONFIGURATION OPTIONS Pin Name value on this pin at falling edge of RESET is used to configure 1 0 1 0 VDO 16 bit host bus interface 8 bit host bus interface VDI Use direct mapping for I O accesses Use inte
41. X16 AN 002 09 Page 16 Epson Research and Development Vancouver Design Center Appendix B SDU1352B0C REV 1 0 SCHEMATIC DIAGRAMS XSCL LCDENB RESET 32 SERE RESET Figure 1 SDU1352B0C Rev 1 0 Schematic Diagram 1 of 7 SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 17 Vancouver Design Center REV Sheet qs a 2 E 8 5 v 8 h 8 a 5 5 lov lov 5 v lo v 1 v 3 3 2 als 5 ME EN ge E 5 1 amp 3
42. bit4 bit 3 bit 2 bit 1 bit 0 DISP This bit selects display on or off When this bit 0 Display OFF is selected LDO 3 and UDO 3 are forced to 0 When this bit 1 Display ON is selected This bit goes low on RESET Panel This bit selects the LCD panel configuration single or dual When this bit 0 Single LCD panel drive is selected When this bit 1 Dual LCD panel drive is selected This bit goes low RESET Mask XSCL When this bit 0 XSCL is not masked off during the horizontal non display period When this bit 1 XSCL is masked off during the horizontal non display period This bit goes low on RESET LCDE The state of this pin determines the state of output pin 82 LCDENB and is intended for control of an external LCDBIAS power supply However this pin can be used as a General I O pin if desired When LCDE 0 LCDENB is forced low When LCDE 1 LCDENB is forced high This bit goes low on RESET Gray Scale Selects between 16 level or 4 level gray scale display When this bit 1 16 gray shades are displayed 4 bits pixel When this bit 0 4 gray shades are displayed 2 bits pixel This bit goes low on RESET LCD Data Width Selects between 4 bit and 8 bit display data widths for single LCD mode When this bit 1 8 bit data transfer width is enabled When this bit 0 4 bit data transfer width is enabled In dual panel mode the data transfer width is forced to 4 bits per panel This bit goes low on RE
43. fosc 50ns Access time lt 4 fosc 30ns 9 3 Frame Rate Calculation 9 3 1 For Single Panel f OSC FrameRate orizontalPixelst DHNDP x VerticalLines 4 9 3 2 For Dual Panel Jose FrameRate ticalLines HorizontalPixels DHNDP 2 2 2 Where DHNDP is Default Horizontal Non Display Period in term of pixels DHNDP 16 pixels per panel 9 4 Memory Size Calculation HorizontalPixels x VerticalLines x Bits PerPixel Memory Size bytes 8 Example For a 640x480 4 gray shades 2 bits per pixel system 4 4 2 Memory Size bytes 76800bytes 75Kbyte Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 62 Epson Research and Development Vancouver Design Center 9 5 Memory Size Requirement The following tables summarize the preceding information formulae Input clock fosc is limited by SRAM access time depending on the display mode and display memory interface that is being used As a result different resolutions will have different input clock and memory requirements for a particular frame rate Tables 9 3 through 9 5 summarize the minimum memory size and access time requirements for various resolutions at a particular input clock along with the corresponding frame rates Table 9 3 Memory Size Requirement Number of Horizontal Pixels 640 Numb
44. see Table 6 4 Output Specifications on page 27 TTL level input for VDD 5 0 see Table 6 3 Input Specifications on page 26 for VDD 3 0V and 3 3V 5 TTL level input with hysteresis Table 5 1 Bus Interface F1B DOB NT Pin Name Type FOB Pin Pin Pad Driver Description 94 100 1 91 98 These pins are connected to the system data bus In 8 bit bus 4 11 1 8 TRE mode DB8 DB15 must be tied to Vpp In MC68000 MPU interface this pin is connected to the Upper ABO I 12 9 TTL Data Strobe UDS pin of MC68000 In other bus interfaces this pin is connected to the system address bus 1 19 I 13 31 10 28 TTL These pins are connected to the system address bus In MC68000 MPU interface this pin is connected to the Lower Data Strobe LDS pin of MC68000 In other bus interfaces this a ids yore pin is the Bus High Enable input for use with 16 bit system In 8 bit bus mode tie BHE input to Vpp IOCS I 84 81 5 Active low input to select one of fifteen internal registers In MC68000 MPU interface this pin is connected to the R W pin of MC68000 This input pin defines whether the data transfer is a IOW I 85 82 TTLS read active high or write active low cycle In other bus interfaces this is the active low input to write data into an internal register In MC68000 MPU interface this pin is connected to the AS pin of MC68000 This input pin indicates a valid ad
45. 0 F 8 7 1 E 9 6 2 5 3 4 4 3 5 2 6 9 1 7 8 0 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 19 Vancouver Design Center 3 2 3 Four Gray Shades Two Bits Pixel When the SED1352 is configured for two bit pixels each pixel can index one of four LUT entries In this 4 gray shade mode the SED1352 treats the 16 entries in the LUT as four separate look up tables or banks each having four entries see Figure 3 The following examples show how to program and select these banks Example 5 4 gray shade mode program bank 2 LUT entries and select for use 1 Determine location of bank 2 in LUT The first four entries in the 16 entry LUT represent the first bank bank 0 The following four entries in the LUT rep resent the second bank bank 1 etc Consequently bank 2 starts at LUT index 8 as shown below start of bank index bank number x 4 start of bank 2 2x4 8 Bank 2 is shown in Figure 3 palette 2 Write LUT index to Look Up Table Address Register AUX OEh For bank 2 the index will one of the following values 08h 09h OAh or OBh Write LUT entry value to Look Up Table Data Register AUX OFh For a linear LUT use the look up table entries in Table 3 1 SED1352FOB Black To White Look Up Table for 16 Gray Shades on page 17 Repeat steps 2 and 3 until all 4 LUT entries have been written To display data using Bank
46. 0000 1100 write monochrome LUT data AUX OFh 0000 0000 write monochrome LUT data AUX OEh 0000 1101 Jincrement palette address AUX OFh 00 0101 write monochrome LUT data AUX OEh 0000 1110 increment palette address AUX OFh 0000 1010 write monochrome LUT data AUX OEh 0000 1111 select palette address AUX OFh 0000 1111 write monochrome LUT data Program Mode Register bit DISP to 1 and set LCDE to enable power supply 1001 00006 OR original value for 01 1 AUX OIh 1001 1000 e 7 display on application specific b4 LCDE LCDENB pin set to enable specific power supply design for SDU1353B0C set bit to 1 to enable power supply application specific Write one pixel to the top left corner of display memory If the SDU 1352B0x evaluation board is used the first panel s memory addresses begin at C000 0000h see Section 5 4 4 1 Displaying a Single Image on a Dual Panel on page 40 Consequently write to location C000 0000h for the 001352 0 Programming Notes and Examples Issue Date 98 10 08 SED1352 X16 BG 007 04 Page 14 Epson Research and Development Vancouver Design Center Note Panel Width in Pixels Memory Interface Width 8 or 16 bits 640 gt 2 79 4Fh Line Byte Count bits per pixel 2 or 4 bits 1 B Single Panel Total Display Line Count number of display lines 1 Dual Panel number of display lines
47. 0100 0000 1011 bits 7 0 bits 7 0 of Screen 2 Display Start Address application specific bits 15 8 of Screen 2 Display Start Address AUX 09h application specific Screen 2 Display Start Address points to C000 9600h bits 7 0 bits 15 8 of Screen 2 Display Start Address application specific see AUX 08h see Section 4 2 1 SDU1352B0x Evaluation Board Display Memory on page 24 and Section 4 1 Registers on page 22 AUXI OAR 1110 1111 bits 7 0 bits 7 0 of Screen 1 Display Line Count application specific bits 9 8 of Screen 1 Display Line Count in bits 1 0 of AUX OBh application specific Screen 1 Display Line Count is typically the same as Total Display Line Count AUX OAh AUX 04h bits 1 0 of AUX OBh bits 1 0 of AUX 05h see Section 5 4 Split Screen on page 34 AUX 0Bh 1111 1100 bits 7 2 not used bits 1 0 bits 9 8 of Screen 1 Display Line Count application specific see AUX OAh AUXI ODh 0000 0000 bits 7 0 no address pitch adjustment see Section 5 1 Virtual Displays on page 28 AUXI OEh 0000 0000 select palette address bits 7 6 bank 0 application specific bits 5 4 ID bits read only application specific bits 3 0 palette address application specific 00 0000 write monochrome LUT data bits 7 4 bits 5 4 bank 0 application specific
48. 15 0 AUX 09h bits 7 0 These 16 bits determine the Screen 2 Display Start Address In an 8 bit memory configuration these bits set the 16 bit start address i e byte access In a 16 bit memory configuration these are the 16 most sig nificant bits of a 17 bit start address 1 word access Page 51 In a dual panel configuration screen 2 refers to the lower half of the display The Screen 2 Display Start Address is the memory address corresponding to first displayed pixel in the first line of the lower half of the display If screen 2 is started right after screen 1 the Screen 2 Display Start Address is calculated with the following formula Screen2DisplayStartAddress hex ImageHorizontalResolution x ImageVerticalResolution x BytesPerPixel 2 ScreenlDisplayStartAddress In a single panel configuration screen 2 refers to the second screen of the Split Screen Display Feature where two different images screen and screen 2 can be displayed at the same time on one display The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory To display screen 2 refer to AUX OAh Screen 1 Display Line Count Register LSB below Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 52 Epson Research and Development Vancouver Design Center AUX 0Ah Screen 1 Display Li
49. 16 0 04 0 1 k 14 0 y 75 51 76 50 ae t o E Index 100 26 1 0 5 0 168 0 1 p gt 14501 0 1 gt ny os 0 5 02 Actual Size X16B C 001 06 23 GRAPHICS NE EPSON COMPREHENSIVE SUPPORT TOOLS Seiko Epson provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems Documentation Technical manuals e Evaluation Demonstration board manual Evaluation Demonstration Board Assembled and fully tested Graphics Evaluation Demonstration board Schematic of Evaluation Demonstration board Parts List Installation Guide CPU Independent Software Utilities Evaluation Software Application Engineering Support Seiko Epson offers the following services through their Sales and Marketing Network Sales Technical Support Customer Training Design Assistance CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS SED1352 Technical Manual 5001352 Evaluation Boards CPU Independent Software Utilities Japan 4 North America Taiwan R O C Epson Corporationi ee Epson Electronics America Inc Epson Taiwan Technology Electronic Devices Marketing Division 150 River Oaks Parkway amp Tradi
50. 175MHz depending on the specific panel size and frame rate desired Refer to Section 9 3 of the SED1352 Functional Specification Drawing Office No X16 SP 001 xx for further details 1 3 9 CPU Bus Interface Header Strips All of the CPU Bus interface pins of SED1352 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than the ISA bus Refer to Table 1 5 CPU BUS Connector Pinout on page 10 and Table 1 6 CPU BUS Connector H2 Pinout on page 11 for specific settings Note These headers only provide the CPU Bus interface signals from SED1352 when MC68K interface is selected SW1 3 closed external decoding logic MUST be used to access the SED1352 1 3 10 Schematic Notes The evaluation boards may have been modified and therefore the following schematics may not reflect the actual imple mentation Please request updated information before starting any hardware design SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Vancouver Design Center Appendix A PARTS LIST Page 15 Item Oy Designation Part Value Description Board 1 33 0 1uF 1206 pckg 2 1 C2 1 0uF 35V Tantalum 1 spacing radical 3 2 C3 C4 56uF 35V LXF35VB56RM6XIILL 4 4 C7 C11 C13 10uF 15V Tantalum D SIZE 5 2 H1 H3 Con32A 0 1
51. 2 Step 2 Enable LCDE turn on LCD power supply For the SDU1353B0C set LCDE bit to 1 val ReadRegister 1 val 0x10 WriteRegister 1 val Step 3 Turn on display val ReadRegister 1 val 0x80 WriteRegister 1 val ShowMenu SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center Page 65 7 GLOSSARY 1352 display memory The SED1352 LCD controller chip Memory in which an image is stored for display by the SED1352 gray shade A specific combination of white and black colors For example a lighter gray shade has more white than black LCD Liquid Crystal Display The display device used by the SED1352 LCD controller device used to control the LCD display The SED1352 is an LCD controller LUT Look Up Table or palette The LUT treats the value of a pixel as an index into an array of gray shades panel The circuitry and viewable area of an LCD display which supports a single image LCD displays may have one or two panels panning The right or left movement of the viewport in a virtual display pixel Picture Element A pixel is seen as a dot on the display and can be shown using one of power saving several different gray shades Combining pixels in a group creates an image A means of reducing the power consumption of the SED1352 register A memory storage
52. 241 6 X X X X Y X X 241 638 X LD1 u 241 3 X 241 7 X Y X X JQ41 639 X LDO K 2414Y 2418 X XX Y X 241 640 X Example timing for a 640x480 panel Figure 26 8 Bit Dual Monochrome Panel Timing Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 46 Epson Research and Development Vancouver Design Center 8 HARDWARE REGISTER INTERFACE SED1352 is configured and controlled via 15 internal 8 bit registers There are two ways to map these registers into the system 1 T O space Direct mapping Absolute I O address system address lines AB 3 0 base I O mapped address where base I O address is selected by VD7 VD12 see Table 5 6 This scheme requires 16 sequential I O addresses starting from the I O mapped base address selected by VD7 VD12 see Table 5 6 To perform an I O access write data IOW absolute I O address data read data IOR absolute I O address 2 Indexing I O address internal index register bits 3 0 This scheme requires 2 sequential I O addresses starting from the base address selected by VD4 VD12 see Table 5 6 To perform an 8 bit I O access write index I O mapped address index write the index of the register to be accessed then write data IOW I O mapped address 1 data write data to the indexed register or read data I O mapped address 1 read the indexed register To perform a 16 bit I O access write data IOW I O m
53. 3 Bit 2 Bit 1 Bit 0 AUX 07 Screen 1 Display Start Address Register MSB I O address 0111b Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 AUX 06 bits 7 0 Screen 1 Display Start Address Bits 15 0 AUX 07 bits 7 0 These 16 bits determine the Screen 1 Display Start Address In 8 bit memory configuration these bits Note set the 16 bit start address i e byte access In a 16 bit memory configuration these are the 16 most sig nificant bits of a 17 bit start address 1 word access The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel top left corner In a dual panel configuration screen 1 refers to the upper half of the display While in a single panel configuration screen 1 refers to the first screen of the Split Screen Display feature where two differ ent images screen and screen 2 can be displayed at the same time on one display The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 VD15 SED1352 X16 BG 007 04 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Vancouver Design Center AUX 08 Screen 2 Display Sta
54. 5 SED1352F0B Default Setup 1 5 1 Configuration Options 1 VD15 VD13 101 memory decoding for locations A segment 2 VD12 4 110000000 decoding for locations 1100000000b 1100000001b 3 VD3 0 No byte swap of high and low bytes 4 VD2 0 ISA Bus interface i e non MC68K interface 5 VD1 0 Indexing I O 6 VDO 0 8 bit bus interface Where pull up with a 10K resistor 0 no pull up resistor Note The states of these data pins are internally latched during RESET 1 5 2 Register Setting AUX 1 bit 1 0 for 16 bit memory interface or AUX 1 bit 1 1 for 8 bit memory interface ISA Bus Interface Considerations SED1352F0B Issue Date 98 10 08 X16 AN 003 05 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16 AN 003 05 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller MC68340 Interface Considerations Document Number X16 AN 004 06 Copyright 1996 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain ma
55. 67 70 CO4 Upper panel display data for dual panel mode For single panel mode these bits are the most significant 4 bits of the 8 bit output data to the panel PD 4 7 For 4 bit single panel mode these bits are the 4 bits of output data to the panel LD3 LDO LD3 LDO 74 77 71 74 CO4 Lower panel display data for dual panel mode For 8 bit single panel mode these bits are the least significant 4 bits of the 8 bit output data to the panel PD 0 3 For 4 bit single panels these bits are driven 0 low state XSCL FPSHIFT 81 78 CO4 Display data shift clock Data is shifted into the LCD X drivers on the falling edge of this signal LP FPLINE 79 76 CO4 Display data latch clock The falling edge of this signal is used to latch a row of display data in the LCD X drivers and to turn on the row driver Y driver WE MOD 80 77 CO4 LCD backplane BIAS signal This output toggles according to the value programmed in AUX 05h YD FPFRAME 78 75 CO4 Vertical scanning start pulse A logic 1 on this signal sampled by the LCD module on the falling edge of LP is used by the panel row driver Y driver to indicate the start of the vertical frame LCDENB 82 79 2 LCD enable signal output It can be used externally to turn off the panel supply voltage and backlight 4 VESA Flat Panel Display Interface
56. 800 0001 2 00 40x4 4 16 Offset Offset hex hex 0000 Scan Line 0 004 0050 Scan Line 1 009 4A60 Scan Line 238 4 4ABO Scan Line 239 4 Figure 6 Memory Map Example for 320 x 240 LCD Panel with 4 Gray Shades Offset Offset hex hex 0000 Scan Line 0 013 0140 Scan Line 1 027 F780 Scan Line 198 F8CO Scan Line 199 FOFF Figure 7 Memory Map Example for 640 x 200 LCD Panel with 16 Gray Shades Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 28 Epson Research and Development Vancouver Design Center 5 ADVANCED TECHNIQUES This section presents information on the following e virtual displays bitmaps and text displays reading and writing to the SED1352 registers Split screen displays panning and scrolling power saving 5 1 Virtual Displays This section presents a detailed description of the Address Pitch Adjustment Register followed by a description of a virtual display Afterwards an example is given showing how to create a virtual display 5 1 1 Registers Note Register bits discussed in this section are highlighted AUX 0D Address Pitch Adjustment Register I O address 1101b Read Write Addr Pitch Adjustment Bit 7 Addr Pitch Adjustment Bit 6 Addr Pitch Adjustment Bit 5 Addr Pitch Adjustment Bit 4 Addr Pitch Adjustment
57. 860 2 071 43 VD2 2 071 0 712 8 DB15 0 712 2 071 44 VD3 2 071 0 860 9 ABO 0 566 2 071 45 VD4 2 071 1 012 10 ABI 0 423 2 071 46 VD5 2 071 1 168 11 AB2 0 281 2 071 47 VD6 2 071 1 330 12 AB3 0 140 2 071 48 VD7 2 071 1 496 13 AB4 0 000 2 071 49 Vss 2 071 1 670 14 AB5 0 140 2 071 50 Vpp 2 071 1 850 15 AB6 0 281 2 071 51 VD8 1 850 2 071 16 AB7 0 423 2 071 52 VD9 1 670 2 071 17 AB8 0 566 2 071 53 VD10 1 496 2 071 18 AB9 0 712 2 071 54 1 1 330 2 071 19 10 0 860 2 071 55 12 1 168 2 071 20 11 1 012 2 071 56 VD13 1 012 2 071 21 AB12 1 168 2 071 57 VD14 0 860 2 071 22 AB13 1 330 2 071 58 VD15 0 712 2 071 23 14 1 496 2 071 59 VAII 0 566 2 071 24 15 1 670 2 071 60 12 0 423 2 071 25 16 1 850 2 071 61 VA13 0 281 2 071 26 AB17 2 071 2 021 62 VA14 0 140 2 071 27 AB18 2 071 1 670 63 VA15 0 000 2 071 28 AB19 2 071 1 496 64 VWE 0 140 2 071 29 RESET 2 071 1 330 65 VCS0 0 281 2 071 30 VA0 2 071 1 168 66 VCS1 0 423 2 071 31 VAI 2 071 1 012 67 UD3 0 566 2 071 32 VA2 2 071 0 860 68 UD2 0 712 2 071 33 VA3 2 071 0 712 69 UDI 0 860 2 071 34 VA4 2 071 0 566 70 UDO 1 012 2 071 35 VAS 2 071 0 423 71 LD3 1 168 2 071 36 VA6 2 071 0 281 72 LD2 1 330 2 071 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center Table 4 1 SED1352D0A Pad Coordinates Continued
58. 8KB WE Voc CS2 SRM2264 10 Figure 1 8 Bit Memory Configuration Example 3 1 1 Configuration Options VDO selects 16 8 bit Bus interface When using a 8 bit memory interface the 8 bit Bus interface must also be selected The state of VDO is internally latched during RESET In this example VDO has no external pull up resistor and is therefore latched as a 0 during RESET due to the internal pull down resistors thus selecting the 8 bit Bus interface Other option settings are not related to this implementation SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center AUX 00h 0000 0000 AUX 01h 1001 0011 AUX 02h 1001 1111 AUX 03h 0000 0000 AUX 04h 1110 1111 AUX 05h 0000 0000 AUX 06h 0000 0000 AUX 07h 0000 0000 AUX 08h xxxx xxxx AUX 09h xxxx xxxx AUX OAh 1110 1111 AUX OBh xxxx xx00 AUX 0Dh 0000 0000 Page 9 3 1 2 Register Settings not in test mode 4 bit single panel 4 gray shades 8 bit display memory interface with 32K bytes is the first chip horizontal resolution 640 4 gray shades 4 pixels per byte 4 pixels per fetch not in power save modes total 240 scan lines WE 0 default starting address at 0000h with AUX 06h don t care when not using split screen don t care when not using split screen together with AUX OBh bit1 0 should be the same as or larger than AUX 05h 11
59. AUX 04h bits 1 0 of AUX OBh bits 1 0 of AUX 05h see Section 5 4 Split Screen on page 34 AUX OBh 1111 1100 bits 7 2 not used bits 1 0 bits 9 8 of Screen 1 Display Line Count application specific see AUX OAh AUX ODh 0000 0000 bits 7 0 no address pitch adjustment see Section 5 1 Virtual Displays on page 28 AUX OEh 0000 0000 select palette address bits 7 6 bank 0 application specific bits 5 4 ID bits read only application specific bits 3 0 palette address application specific AUX 0Fh write monochrome LUT data bits 7 4 N A bits 3 0 palette data application specific 01 increment palette address 01 write monochrome LUT data 10 increment palette address 10 write monochrome LUT data 11 increment palette address S O ol ojl olj o 11 write monochrome LUT data Ol CO Or Oo 100 increment palette address Programming Notes and Examples Issue Date 98 10 08 SED1352 X16 BG 007 04 Page 10 Epson Research and Development Vancouver Design Center PCR Notes See Also AUX OFh 0000 0100 write monochrome LUT data AUX OEh 0000 0101 lincrement palette address AUX OFh 0000 0101 writ
60. Bit 3 Addr Pitch Adjustment Bit 2 Addr Pitch Adjustment Bit 1 Addr Pitch Adjustment Bit 0 bits 7 0 SED1352 X16 BG 007 04 Addr Pitch Adjustment Bits 7 0 These bits set the numerical difference between the last address of a display line and the first address in the following line If the Address Pitch Adjustment is not equal to zero then a virtual screen is formed The size of the virtual screen is only limited by the available display memory The actual display output is a window that is part of the whole image stored in the display memory For example with 128K of display memory a 640x400 16 gray image can be stored If the output display size is 320x240 then the whole image can be seen by changing display starting addresses through AUX 06 and 07 and AUX 08 and 09 Note that a virtual screen can be produced on either a single or dual panel In 8 bit memory interface if the Address Pitch Adjustment is not equal to zero then a virtual screen with a line length of Line Byte Count AUX 0D bytes is created with the display reflecting the contents of a window Line Byte Count 1 bytes wide The position of the window on the virtual screen is determined by AUX 06 and 07 and AUX 08 and 09 In 16 bit memory interface if the Address Pitch Adjustment is not equal to zero then a virtual screen with a line length of 2 Line Byte Count AUXT OD bytes is created with the display reflecting the con
61. Figure 14 Memory for a Dual Panel showing a Single Image Figure 15 Display for Programming Notes and Examples Issue Date 98 10 08 Page 5 SED1352 X16 BG 007 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center 1 INTRODUCTION Page 7 The purpose of this guide is to demonstrate how to program the SED1352 LCD controller with reference made to the SDU1352BO0x evaluation board The first half of this guide presents the basic concepts of LCD controllers which describe the following Initializing the SED1352 Gray Shades and Look Up Tables Display Memory Models e Virtual Displays Bitmaps and Text Displays Registers Split Screen Panning and Scrolling Power Saving The second half of this guide presents programming examples for the following e Initialization e Read Registers Gray Shades and Look Up Tables e Text Split Screen Panning and Scrolling Power Saving These programming examples are combined a simple menu driven program Most of the program is written in the programming language with some parts written in 8086 assembly Programming Notes and Examples Issue Date 98 10 08 SED1352 X16 BG 007 04 Page 8 Eps
62. K bytes Note For a detailed description of the memory size requirement see section 9 4 of the SED1352 Hardware Functional Specification drawing office number X16 SP 001 xx SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08 Epson Research and Development Page 7 Vancouver Design Center 2 2 2 SRAM Access Time For 8 bit display memory interface Access time lt 2 fosc 50 With 12MHz input clock Access time lt 116ns For 16 bit display memory interface Access time lt 4 fosc 50 With 12MHz input clock access time lt 283ns Note For detail description of the SRAM access time see section 9 2 of the SED1352 Hardware Functional Spec ification drawing office number X16 SP 001 xx LCD Panel Options Memory Requirements SED1352 Issue Date 98 10 08 X16 AN 005 07 Page 8 Epson Research and Development Vancouver Design Center 3 IMPLEMENTATION 3 1 8 Bit Display Memory Interface Since 35 7K bytes with at least 1 16ns access time SRAM is required one 8K bytes SRAM with 100ns access time and one 32K bytes SRAM with 100ns access time are used in this example 640x240 Panel co gt 9 58 x SRM20256 10 VDO 7 e gt 00 7 VAO 14 e gt 0 14 VCSO gt CS 12MHz gt OSC1 VCS1 32KB VOE gt VWE gt WE gt 00 7 SED1352 A0 12 5 CST
63. SP 001 16 Page 38 Epson Research and Development Vancouver Design Center 7 3 2 Read Data From Display Memory VA 15 0 VSCO VSC1 VALID X lt t1 t2 t3 VD 15 0 INPUT INPUT INPUT Figure 21 Read Data From Display Memory Table 7 11 Read Data From Display Memory 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Add leti MCLK MCLK ress cycle time 10 10 MCLK MCLK t2 VA 15 0 VCSO and VCS1 access time 50 30 t3 VD 15 0 hold time 0 0 Where MCLK period l fosc or 2 fosc or 4 fosc depending on which mode the chip is in See sections 9 2 and 9 3 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 39 Vancouver Design Center 7 4 LCD Interface Timing SED1352 outputs YD t3 tl LP SED1352 outputs AUX OLh bit 5 0 LP XSCL UD 3 0 LD 3 0 SED1352 outputs AUX OIh bit 5 1 LP t7b t8 t6b t13 t9 10 gt lt gt T UD 3 0 80 1 2 LD 3 0 Figure 22 LCD Interface Timing Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 40 Epson Research and Development Vancouver Design Center 7 4 1 4 Bit Single LCD Interface Timing Table 7 12 4 Bit Single LCD Interface Timing
64. Say pFont amp font 1 else if ch lt pFont amp font 0 else for pFont amp font ch y O y lt 8 4 Point to next character pdisplayStart Block character 0 ch gt Z 0 Tp 2 ty pDisplay pdisp ayFirstColumn val pFont Since there are 16 gray shades each bit in the font will be represented in display memory as four bit gray shade Programming Notes and Examples Issue Date 98 10 08 Page 57 SED1352 X16 BG 007 04 Page 58 if val amp 0x80 Display color lt lt 4 else Display 0 if val amp 0x40 Display color pDisplayt unsigned char Display if val amp 0x20 Display color 4 else Display 0 if val amp 0x10 Display color pDisplay unsigned char Display if val amp 0x08 Display color lt lt 4 else Display 0 if val amp 0x04 Display color pDisplay unsigned char Display if val amp 0x02 Display color lt lt 4 else Display 0 if val amp 0x01 Display color 1 unsigned char Display pdisplayFirstColumn BytesPerScanLine pdisplayStart 4 Point to next character pdisplayFirstColumn pdisplayStart Epson Research and Development Vancouver Design Center FUNCTION SplitScreen
65. This program requires BIOS1352 to be loaded The program BIOS1352 COM must be run before 1352PD Load BIOS1352 and re run 1352PD EXE SED1352 1352PD EXE Power Down Utility X16 UI 005 07 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller 1352READ EXE Diagnostic Utility Document Number X16 Ul 006 06 Copyright 1996 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352READ EXE Diagnostic Utility X16 UI 006 06 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center 1352READ EXE DIAGNOSTIC UTILITY 1352READ is an OEM utility program which enables the user to read the SED1352 register contents It is a useful utility for OEMs wishing to submit a problem report for the video controller If run with BIO
66. address 310h 8h 318h 2 Write the value 12h to port address 318h MOV DX 318h MOV AL 12h OUT DX AL Note The SDUI352B0x is normally configured for register indexing not direct mapping Refer to the SDU1352B0x Evaluation Board User s Manual for more information configuring the SDU1352BOx board for register indexing or register direct mapping Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 34 Epson Research and Development Vancouver Design Center 5 4 Split Screen This section describes how to create a split screen for both single and dual LCD panels For single panel displays the Screen 1 Display Line Count Registers are used For dual panel displays the Screen 2 Display Start Address Registers are used 5 4 1 Registers AUX 0A Screen 1 Display Line Count Register LSB I O address 10106 Read Write This register is used to enable the split screen display feature single panel only where two different images can be displayed at the same time on one display This register has no effect when using a dual panel configuration bits 7 0 Screen 1 Display Line Count Bits 7 0 These bits are the seven LSB of a 9 bit value used to determine the number of lines displayed for screen 1 The remaining lines will automatically display from the screen 2 display start address The 9 bit value pro grammed is the number of display lines 1 For example if AUX 0A 20h for a 320x240 display
67. amp Oxff Total Display Line Count WriteRegister 0x0b val gt gt 8 amp 0x03 Total Disp Line Cnt WF Count 1 0 1 val MinLineCount WriteRegister 0x0a val amp Oxff Total Display Line Count Reg WriteRegister 0x0b val gt gt 8 amp 0x03 Total Disp Line Cnt WF Count Delay 0 5 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 61 Vancouver Design Center void SetStartAddress int x int y int addr Assume 16 gray shades addr 0x8000 x 2 VIRTUAL_X 2 y 2 WriteRegister 6 addr amp Oxff WriteRegister 7 addr gt gt 8 void PanScroll void static unsigned int x y static unsigned int MaxX static unsigned int val pitch static unsigned char far pVideo printf Showing Panning and Scrolling n Initialize ClearLCDScreen This pitch is calculated for 16 gray shades pitch VIRTUAL X 2 BytesPerScanLine 2 WriteRegister 0x0d pitch BytesPerScanLine VIRTUAL X 2 For 64k only FP SEG pVideo 0xd000 FP OFF pVideo 0x0000 Display random blocks of data To do so a text character will be used This character sets all pixels in a character region so a block is shown at the specified gray shade Seed the random number generator with current time srand un
68. and MEMCS hold from rising 0 0 as edge t3 MEMR falling edge to READY falling edge 30 20 ns t4 READY rising edge to DB 15 0 valid 15 10 ns 5 DB 15 0 hold from MEMR rising edge 30 28 ns t6 MEMRE rising edge to DB 15 0 hi z delay 30 30 ns 3 5 3 5 t7 READY negated pulse width MCLK MCLK ns 30 10 Where MCLK period l fosc or 2 fosc or 4 fosc depending on which mode the chip is in see section 9 2 and 9 3 Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Epson Research and Development Page 36 Vancouver Design Center 7 2 Clock Input Requirements Clock Input Waveform Owe 7 E 10 fr TN t T lt i ra Tosc gt Figure 18 Clock Input Requirements Table 7 9 Clock Input Requirements Symbol Parameter Min Typ Max Units Input Clock Period 40 ns town Input Clock Pulse Width High CLKI 40 60 Tosc Input Clock Pulse Width Low CLKI 40 60 Tosc t Input Clock Fall Time 10 90 ns t Input Clock Rise Time 10 90 ns 7 2 1 Recommended Clock Input The nominal frequency must be calculated based on the formulas found in Frame Rate Calculation on page 61 The crystal oscillator must be fundamental mode and have the following recommended RC load values Ry 2MQ 5 CL 6 8 The figure be
69. bit display memory interface either 64K bytes or 128K bytes 128K bytes available at CO00h memory segment This board is also pre set to use indexing I O with address 0000 0011 0 000x where x is don t care and can be configured with dip switch SW 1 5 through SW1 7 The factory setting of 001 i e address 0310h and 03118 When using direct mapping I O the I O address is 0000 0011 0 xxxx where x is don t care and can be configured with dip switch SW1 5 through SW1 7 If 001 then the I O address for AUX 00h 0310h I O address for AUX 01h 031 1h I O address for AUX 02h 0312h and so Table 1 2 I O Mapping Example bit 6 bit 5 bit 4 Mapping Address Hex 0 0 1 Table 1 3 Decoding Jumper Setting Description 1 2 2 3 JP1 Set to the same polarity as SW1 1 VDO JP2 Set to the same polarity as SW1 5 VD7 JP3 Set to the same polarity as SW1 6 VD8 JP4 Set to the same polarity as SW1 7 VD9 O O Note These jumpers are necessary for the external ISA Bus decode logic SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 9 Vancouver Design Center LCD Signal Connector Pinout Table 1 4 LCD Signal Connector J1 Pinout LCD SED1352 Conne
70. c us gu q asema es Bil Oe ACE EDAM VET SEVERE 34 24 2 Description e ue h 35 24 3 Smgle Panel E CD zu use quee SS Se us qud Suis 35 JAA Dual Panel LCD a ee end dude ee a Oe 38 55 Panningvand Scrolling 2 200 loko ceo v b 4 o og 42 53 LImtalhzation Gem d ome co mS A SUE oe ee m 42 23 3 2 Panning Rishtand Left sos nonse we Wu ERU Bd aT Rue d DR UNIES 42 3 5 3 Scrolling Up and Down e 222474 be ee Xx Yel S up ee X RUE 5 uos 42 5 6 PowerSavimg e 44 2 0 gcd eg Sir Eua GRO Pues peu pt ate tn 44 5 6 2 PowerSave Modes PS 4k ESI E RM RU P rm 44 Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 4 Epson Research and Development Vancouver Design Center 6 PROGRAMMING THE 1352 46 61 MainLoopCode 2 0000 47 62 Initialization 48 6 3 Advanced Functions a a 955 PE 52 7 GLOSSARY 65 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center List of Tables Table 3 1 SED1352F0B Black To White Look Up Table for 16 Gray Shades Table 3 2 SED1352F0B Inverted Look Up Table White To Black
71. during Power Save implementation specific see Section 5 6 Power bit 4 no LUT bypass application specific Saving on page 44 bits 3 1 not used bit 0 bit 8 of Line Byte Count panel specific see AUX 02h AUX 04h 1110 1111 e bits 9 8 of Total Display Line Count in bits 1 0 of AUX 05h bits 7 0 bits 7 0 of Total Display Line Count panel specific see Note B and C at end of Table for calculation panel specific AUX 05h 0000 0000 e bits 1 0 bits 9 8 of Total Display Line Count panel specific bits 7 2 WF not required panel specific see AUX 04h Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 12 Epson Research and Development Vancouver Design Center AUX Register Data in Binary Notes See Also AUX 06h AUX 07h 0000 0000 0000 0000 bits 7 0 bits 7 0 of Screen 1 Display Start Address application specific bits 15 8 of Screen 1 Display Start Address in AUX 07h application specific Screen 1 Display Start Address points to C000 0000h when 0000h Screen 1 Display Start Address is located at D000 0000h bank 0 on the SDU1353B0C bits 7 0 bits 15 8 of Screen 1 Display Start Address application specific see AUX 06h see Section 4 2 1 SDU1352B0x Evaluation Board Display Memory on page 24 and Section 4 1 Registers on page 22 AUX 08h AUX 09h 0000
72. error message is generated 1352READ will accept any port address however the SDU1352 can only be configured to an address in the range of 300h through 370h Program Messages ERROR 1352 registers not responding at port address port 1352READ has not found an SED1352 at the port address specified Check the command line port setting for BIOS1352 and or 1352READ to ensure it is correct and re run the program ERROR 1352READ requires a port address 1352READ has not detected BIOS 1352 COM to obtain the port address and no port address was specified on the command line Either specify a port address the 1352READ command line or run BIOS1352 COM prior to running 1352READ ERROR BIOS1352 reports a port address of port which is different from the specified port address of port The poert address entered for 1352READ is different that the one entered for BIOS1352 COM Specify the same port address on the 1352READ command line as the one in BIOS1352 COM and the physical address of the SDU1352 evalu ation board and re run the program WARNING BIOS1352 state is out of sync with SED1352 registers One or more of the following command line items reported by BIOS1352 does not match the values found in the SED1352 registers horizontal panel size vertical panel size number of gray shades or panel type single or dual SED1352 1352READ EXE Diagnostic Utility X16 UI 006 06 Issue Date 98 10 08 EPSON SED1352 Dot Matri
73. into the SED1352 to accommodate the important need for power reduction in the hand held devices market These modes can be enabled by setting the 2 Power Save bits AUX 03h bits 7 6 The various settings are Table 6 5 Power Save Mode Selection Bit7 Bit 6 Mode Activated 0 0 Normal Operation 0 1 Power Save Mode 1 1 0 Power Save Mode 2 1 1 Reserved 8 3 1 Power Save Mode 1 PSM1 Power Save Mode has two states Initially when set the SED1352 enters State 1 If no valid memory cycle is detected within 1 2 or 4 clocks input clock frequency dependent the chip will enter State 2 The number of clocks of inactivity before entering State 2 is dependent on the display memory interface and the number of gray shades State 1 I O read write of all registers allowed Memory read write allowed LCD outputs are either forced low AUX 03h bit 5 0 or high impedance AUX 03h bit 5 1 State 2 The same as State 1 as well as e Master clock for display memory access is disabled Once a valid memory read write cycle is detected the SED1352 returns to State 1 where the MPU access is serviced The transition from going from State 2 to State 1 requires 1 2 or 4 clocks as described above Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 56 Epson Research and Development Vancouver Design Center 8 3 2 Power Save Mode 2 PSM2 I O read write of all registers
74. location to control a peripheral such as the SED1352 scrolling The up and down movement of the viewport in a virtual display SED1352 The 1352 chip SDU1352B0x The evaluation board for the SED1352 SDU1352BOx is an ISA board for a PC compatible computer viewport The visible portion of a virtual display virtual display Programming Notes and Examples Issue Date 98 10 08 An image stored in display memory that is larger than what the LCD display can show A virtual display supports panning and scrolling SED1352 X16 BG 007 04 Page 66 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller 1352SHOW EXE Display Utility Document Number X16 UI 001 08 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are t
75. mA Type 4 TS4 CO4 8 mA Low Level Output Voltage G 3V 2 TS2 CO2 TS2D2 1 mA Vpp 0 3 V Type 3 TS3 2 mA 4 TS4 CO4 4 mA High Level Output Voltage G 0V 2 TS2 CO2 TS2D2 1 mA 0 3 V Type 3 TS3 1 8 mA Type 4 TS4 CO4 3 5 mA Ioz Output Leakage Current 1 1 Output Pin Capacitance 6 pF Bidirectional Pin Capacitance 10 pF KEN 16 001 06 6 001 06 EPSON SED1352 PIN OUTS A CEEEEEEEEEEEEEEFEHTE VD7 ABIS Vss AB17 16 VD8 15 VD9 14 VD10 AB 13 VD13 ABIO 14 9 VD15 c AB8 VAI AB7 VA12 N AB6 VA13 ln ABS VAI4 4 15 AB3 VWE AB2 VCS0 ABI VCS1 ABO UD3 un DB15 UD2 DB14 DH DB13 UDO DB12 es DB11 ins DB10 LDI DB9 LDO DB8 YD Vpp LP Vss m s as ese RRR kas SEEEEEEEEEEBEEEEEEBE X16B C 001 06 GRAPHICS EPSON LP WF XSCL VOE IOCS IOW IOR MEMCS MEMW MEMR READY BHE SED1352F1B OSCI OSC2 DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS 76 19 LCDENB TI 80 81 82 84 86 83 85 87 88 78 IVpp 89 94 99 100 98 97 96 95 93 92 91 90 X16B C 001 06 10 5
76. or less either 4 or 16 shades are available In 4 gray shade mode it is possible to select 1 of 4 palettes Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS Seiko Epson BIOS1352 version 1 11 or later DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Installation Copy the file 1352gray exe to a directory that is in the DOS path on your hard drive Usage 1352GRAY is invoked from the DOS command line as follows 1352gray Where produces a usage message 1352GRAY displays a default gray shade pattern as a series of vertical or horizontal bars The pattern number of gray shades and current palette may be modified by the user when possible Instructions to modify these options will appear when available Pressing the ESC key terminates the program and restores the original BIOS 1352 settings 1352GRAY EXE Display Utility SED1352 Issue Date 98 10 08 X16 UI 004 08 Page 4 Epson Research and Development Vancouver Design Center Comments 1352GRAY requires BIOS1352 COM to be loaded prior to running Four gray shades is always possible Switching to 16 gray shades may not be possible if the panel size exceeds 640x400 Program Messages ERROR This program requires BIOS1352 to be loaded The program BIOS1352 COM must be run before 1352GRAY Load BIOS1352 COM and then re run 1352
77. page 40 Example 9 Determine if the SED1352 implementation can support a 640x480 LCD with 4 gray shades 1 Calculate the number of bytes per scan line pixels per scan line _ 640 _ wusndbyte 4 160 bytes per scan line 2 Calculate the total number of bytes required for display memory 160 bytes per scan line 480 scan lines 76800 bytes 3 Compare the required number of bytes with the amount of memory available to the SED1352 Ifthe SED1352 has 128k available there is 131 072 bytes available which is greater than the 76 800 bytes re quired for 640 x 480 with 4 gray shades e If the SED1352 has 64k available there is 65 536 bytes available which is less than the 76 800 bytes required for 640 x 480 with 4 gray shades SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center Page 27 4 3 Common Display Memory Requirements for LCD Panel Sizes The following is a list of memory requirements and memory maps for common LCD resolutions Note that the memory required for 640x480 with 16 gray shades exceeds 128k and is therefore not supported on the SED1352 Table 4 1 Memory Size Requirements Display Pixel Storage Memory Requirements Resolution Bits Pixel Gray Shades Bytes Hex 2 4 19 2 320x240 9 200 0000 4B00 4 16 38 400 0000 9600 2 4 32 000 0000 7000 640x200 4 16 64 000 0000 00 2 4 76
78. s m 160 bytes per scan line 00AO0h bytes per scan line 2 Calculate the total number of bytes required for display memory bytes per scan line X number of scan lines 160x240 38400 bytes 9600h bytes 3 Create the memory map Each scan line is 00A0h bytes long there are 240 scan lines and the last memory address is 9600h 1 Offset Offset hex hex 0000 Scan Line 0 009F 00A0 Scan Line 1 013F 94CO ScanLine238 955 9560 Scan Line 239 95FF Figure 5 Memory Map for 320 x 240 LCD Panel with 16 Gray Shades 4 Program the Screen 1 Display Start Address Registers Assume that the image starts at the beginning of display memory which for 64k is D000 0000h As shown in Example 6 the Screen 1 Display Start Address Registers must be programmed to 8000h words AUX 06h 00h AUX 07h 80h 5 Program the Screen 2 Display Start Address Registers Under normal programming conditions the Screen 2 Display Start Address should be set to the same value as the Screen 1 Display Start Address In the event that a split screen is required refer to Section 5 4 Split Screen on page 34 AUX 08h 00h AUX 09h 80h Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 26 Epson Research and Development Vancouver Design Center Example 8 Program the Display Start Address Registers for a dual panel LCD Refer to Section 5 4 4 1 Displaying a Single Image on a Dual Panel on
79. system The display will show 20h 1 33 lines on the upper part of the screen according to display starting address AUX 06 and AUX 07 and 240 33 207 lines on the lower part of the screen according to display starting address AUX 08 and AUX 09 Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis play start address However by using this method screen 2 is limited to the lower half of the display AUX 0B Screen 1 Display Line Count Register MSB I O address 1011b Read Write n a n a n a n a n a n a bits 1 0 Screen 1 Display Line Count Bits 9 8 These are the two MSB of the Screen Display Line Count Register SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 35 Vancouver Design Center 5 4 2 Description A split screen is generally considered as the presentation of two different images on the screen Image is shown on the top half and image 2 is shown on the bottom half of the screen Due to the design the SED1352 the system is always in split screen mode If only one image is to be shown either image 2 is hidden or image 2 appears as part of image 1 this depends on whether a single or dual panel LCD is in use 5 4 3 Single Panel LCD The following is the procedure to show a split screen image on a 16 gray shade 320 x 240 single panel LCD For this example the SDU1352BO0x is u
80. the SED1352 video memory will reside at DOOOh to DFFFh For 128K bytes of SED1352 video memory the memory will reside at CO00h to DFFFh Program Messages ERROR Panels greater than 640 pixels not supported More than 640 horizontal pixels has been specified for the panel in the command line ERROR Panels greater than 480 lines not supported More than 480 vertical lines has been specified for the panel in the command line ERROR Invalid port specified The port address p must be specified in the format 3x0 in the command line The range is 300h to 370h in 10h increments ERROR Only 4 or 16 gray shades allowed A number other than 4 or 16 has been specified for the variable g in the command line ERROR Not enough video memory for the panel The panel specified is too large to run in 16 gray shades mode Select 4 gray shades instead ERROR Video memory and VGA BIOS memory conflict Both the SED1352 video memory and the VGA BIOS are trying to use the memory at location C000h to CFFFh ERROR Only 8k 16k 32k 40k 64k or 128k memory allowed An invalid value has been specified for memory size m on the command line ERROR Only 8 or 16 bits allowed for width The SED1352 only supports 8 or 16 bit memory width ERROR Memory size cannot support memory width Choose one of the following combinations Memory Size m 8 16 32 40 64 128 Memory Width w 8 16 8 8 16 16 SED1352 BIOS1352 CO
81. the following formula Screen2DisplayStartAddress hex ImageHorizontalResolution x ImageVerticalResolution x BytesPerPixel 2 8 ScreenlDisplayStartAddress In a single panel configuration screen 2 refers to the second screen of the Split Screen Display Feature where two different images screen 1 and screen 2 can be displayed at the same time on one display The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory To display screen 2 refer to AUX 0A Screen 1 Display Line Count Register LSB below Programming Notes and Examples Issue Date 98 10 08 SED1352 X16 BG 007 04 Page 24 Epson Research and Development Vancouver Design Center 4 2 Description When displaying an image the SED1352 must read pixel data from display memory This memory is organized to match the display resolution of the given LCD panel To organize display memory the following registers must be programmed 1 Screen 1 Display Start Address Registers 2 Screen 2 Display Start Address Registers 3 Address Pitch Adjustment Register For the first example the Address Pitch Adjustment Register is programmed to zero This means that no virtual display is available for information on virtual displays see Section 5 1 Virtual Displays on page 28 4 2 1 SDU1352B0x Evaluation Board Display Memory There are several issues to consider when programming
82. the previous scan line number of bytes per scan line Screen 2 Display Start Address Screen 2 Display Start Address Z bytes per word AUX 08h LSB of Screen 2 Display Start Address AUX 09h MSB of Screen 2 Display Start Address To pan image 1 to the right by a group of pixels the Screen 1 Start Address Register must be increased by 1 Screen 1 Display Start Address Screen 1 Display Start Address 1 AUX 06h LSB of Screen 1 Display Start Address AUX 07h MSB of Screen 1 Display Start Address See Section 5 5 2 Panning Right and Left on page 42 for more information To pan image 2 to the left by a group of pixels the Screen 2 Start Address Register must be decreased by 1 Screen 2 Display Start Address Screen 2 Display Start Address 1 AUX 08h LSB of Screen 2 Display Start Address AUX 09h MSB of Screen 2 Display Start Address See Section 5 5 2 Panning Right and Left on page 42 for more information Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 40 Epson Research and Development Vancouver Design Center 5 4 4 1 Displaying a Single Image on a Dual Panel The following is the procedure to show a single image on a dual panel LCD In this procedure the single image is broken into two smaller images image 1 is placed on the top panel and image 2 is placed on the bottom panel For this example the SDU1352B0x is used with a 4 gray shade 640x480 dual panel LCD the Memor
83. the upper left corner of the screen When the program has completed writing the pixels for the word TEXT the display memory will have the data shown in Figure 10 In this figure the bytes are grouped within vertical lines SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 31 Vancouver Design Center Offset Offset hex hex 0000 0 0 0 0 0 0 000F 00A0 0 0 0 0 00 OOAF 0140 0 0 0 0 0 0 0 014 01 0 0 0 0 010 0 0 0 OIEF 0280 0 0 0 0 0 0 00 028F 0320 0 0 0 0 0 0 032F 03 0 0 0 Y 0 0 0 03 0460 0 0 0 0 0 0 0 0 046F Figure 10 Display Memory Contents for Message TEXT Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 32 Epson Research and Development Vancouver Design Center 5 3 Registers SED1352 has an internal set of sixteen 8 bit read write registers which configure it for various modes of operation The registers can be accessed in two ways Indexed Addressing and Direct Addressing Note Refer to the ED1352 Hardware Functional Specification and SDU1352B0x Evaluation Board User s Manual for more information on the SED1352 registers 5 3 1 Indexed Addressing This method requires only two sequential I O address locations starting from the base I O address The base I O address is determined by the power on state of the SRAM data lines VD 4 12 See Table 5 6 in the SED1352 Hardware F
84. to 0 on RESET Table 5 2 Power Save Mode Selection PS1 PSO Mode Activated 0 0 Normal Operation 0 1 Power Save Mode 1 1 0 Power Save Mode 2 1 1 Reserved Refer to Section 5 6 2 Power Save Modes on page 44 for a complete Power Save Mode description 5 6 2 Power Save Modes Two software controlled Power Save Modes have been incorporated into the SED 1352 to accommodate the important need for power reduction in hand held devices market These modes can be enabled by setting the 2 Power Save bits AUX 03h bits 7 6 The various settings are Table 5 3 Power Save Mode Selection Bit 7 Bit 6 Mode Activated 0 0 Normal Operation 0 1 Power Save Mode 1 1 0 Power Save Mode 2 1 1 Reserved 5 6 2 1 Power Save Mode 1 Power Save Mode 1 would typically be used when power savings are required and memory accesses may occur The disad vantage is that since the oscillator is running this mode consumes more power that Power Save Mode 2 5 6 2 2 Power Save Mode 2 Power Save Mode 2 is typically used when memory accesses would not occur SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center 5 6 2 3 Power Save Mode Function Summary Table 5 4 Power Save Mode Function Summary Power Save Mode PSM Function Normal PSM1 PSM2 Active State 1 State 2 Disp
85. 0 and AUX 04h when not using split screen no virtual screen Example setting of Look up Table when using bank 0 for display AUX OEh 00xx 0000 AUX OFh xxxx 0000 AUX OEb 00xx 0001 AUX OFh xxxx 0101 AUXI 0Eh 00xx 0010 AUX OFh xxxx 1010 AUX OEb 00xx 0011 AUX OFh xxxx 1111 x don t care LCD Panel Options Memory Requirements Issue Date 98 10 08 index 0 gray 0 index 1 gray 5 index 2 gray A index 3 gray F SED1352 X16 AN 005 07 Page 10 Epson Research and Development Vancouver Design Center 3 2 16 bit Display Memory Interface Since 35 7K bytes with at least 283ns access time SRAM is required two 32K bytes SRAM with 120ns access time are used for this example 640x240 Panel gt E z 58 x SRM20256 12 VD0 15 lt e D97 VA0 14 gt 0 14 VCS0 gt cS 12MHz gt OSC1 VCS1 32KB VOE gt OE VWE gt WE 08 15 07 SED1352 LL A0 14 5 CS 32KB WE SRM20256 12 Figure 2 16 Bit Memory Configuration Example 3 2 1 Configuration options VD0 no pull up resistor for 8 bit bus interface or VD0 pull up with a 10K resistor for 16 bit bus interface Other option settings are not related to this implementation SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08 Epson Res
86. 0 microcontroller 1 1 Reference Material Refer to the SED1352 Hardware Functional Specification X16 SP 001 xx for complete AC timing details This document makes no attempts to describe the operation of the MC68340 microcontroller please refer to the appropriate MC68340 documentation for this information MC68340 Interface Considerations SED1352 Issue Date 98 10 08 X16 AN 004 06 Page 6 Epson Research and Development Vancouver Design Center 2 MC68340 MPU INTERFACE The following sections provide the necessary settings and equations to complete the interface between the SED1352 and the MC68340 microcontroller MC68340 SED1352 Vcc 53 A gt MEMCS sizo gt PAL gt IOCS 10kQ BHER VD0 VD3 A0 VD13 A10 A17 A0 A19 gt ABO AB19 00 015 4 gt DBO DB15 Vcc Vcc MEMR 4 7kQ MEM DSACKi 4 READY AS gt OR R W gt IOW RESET d gt RESET Figure 1 MC68340 MPU Interface Block Diagram 2 1 MC68340 Setup For the purpose of this example the following conditions apply The internal chip select signal CS3 of the MC68340 along with external DSACKI response is employed to access the SED1352 Direct mapping of the I O with starting address at 00000000h and 128Kbytes of display memory with starting address 00020000h are also used 1 2 3 4 CS3 with 256kbyte block size starting address at 00000000h and ending addres
87. 07h 00h Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 36 9 Epson Research and Development Vancouver Design Center Calculate the total number of bytes required for image 1 bytes per scan line x number of scan lines for image 1 160 x 240 38400 bytes 9600h bytes 6 Determine the display memory location for image 2 Place image 2 immediately after image see Figure 11 Assign the starting address for image 2 as follows image 2 address base display memory address size of image 1 000 0000 0000 9600h C000 9600h 7 Program the Screen 2 Display Start Address Register to point to the beginning of image 2 Image 2 is placed right after image 1 as shown below J M size of image 1 in bytes Screen 2 Display Start Address Screen 1 Display Start Address Pbytesperwonl 0000h mE 4B00h AUX 08h 00h AUX 09h 4Bh 8 Program the Screen Display Line Count Register The Display Line Count Register indicates how many lines of the first screen should be shown minus 1 By changing the line count image 2 appears to move up or down the display e Ifthe line count is set to the maximum number of visible scan lines 1 only image 1 is shown visible scan lines 1 240 1 239 OOEFh AUX 0Ah LSB of visible scan lines 1 OEFh AUX OBh MSB of visible scan lines 1 00h fthe line count is set to 0 then the first scan line of image 1 is shown follo
88. 0B OSCI OSC2 82 84 86 87 89 85 90 83 88 91 81 92 93 Figure 7 SED1352F0B Pinout Diagram Package type surface mount 5 100 52 Note SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Vancouver Design Center Epson Research and Development Page 18 844549334444 8 BSR RB ABR BESS 2229222525355 RY ZZ ee 16 15 VD10 AB14 VD11 AB13 VD12 AB12 VD13 11 VD14 AB10 VD15 ie 9 VAI AB8 VA12 AB7 VA13 eq AB6 VA14 5 15 AB4 VWE AB3 VCS0 2 1 1 AB0 un DB15 DBl4 DB13 DB12 10 e 3E ak e DB9 d qun R DB8 4 584442245442554555585555 Figure 8 SED1352F IB Pinout Diagram Package type surface mount QFP15 100pin Note 99 07 28 Issue Date Hardware Functional Specification SED1352 X16 SP 001 16 Epson Research and Development Page 19 Vancouver Design Center
89. 1352DO0A Pad 20 5 17 Busdnterl ce scsi E RR Redes EI RAV RR DR 22 Table 5 2 Display Memory 22 2 23 Table 5 3 oabC D Interface 4 cen pO APP oS BA 4 24 Table 5 4 Clock Inputs x ect aoe oR RUBRA OR rr 24 Table 5 5 Powersupply 20 22 SS Ba gosse 24 Table 5 6 Summary of Power On Reset 25 Table 5 7 I O and Memory Addressing Example 25 Table 6 1 Absolute Maximum 26 Table 6 2 Recommended Operating 26 Table6 3 Input Specifications s cues 22542642 ee SE E 26 Table 6 4 Output Specifications 2222 2 2 27 Table 7 1 Timing 68000 see E due SR e UR POE S Ent 28 Table 7 2 JOR Timing 68000 4 y pope RUE UR BO o REUS 29 Table 7 3 Timing 68000 30 Table 7 4 68000 31 Table 7 5 IOW Timing 68000 32 Table 7 6 IOR Timing 68000
90. 2 Display Start Address register to point to Image 2 Adjust ImageSize to represent the size in words not bytes This is because the Memory Interface is set to 16 bits val unsigned int ImageSize 2 val 0x8000 Point to 0000 segment instead of C000 segment Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 60 Epson Research and Development Vancouver Design Center WriteRegister 8 unsigned int val amp Oxff WriteRegister 9 unsigned int val gt gt 8 Tf this is a dual panel then the split screen has just been shown Otherwise set up the Screen 1 Display Line Count register for single panels if PanelType TYPE_SINGLE OriginalLineCount unsigned int ReadRegister 0x0b amp 0x03 lt lt 8 ReadRegister 0x0a Only for 64k of memory axVirtualScanLines unsigned int unsigned long 0x10000 BytesPerScanLine MinLineCount OriginalLineCount MaxVirtualScanLines OriginalLineCount 1 Delay 0 5 Scroll image 2 down for val MinLineCount val lt OriginalLineCount val 1 WriteRegister 0x0a val amp Oxff Total Display Line Count WriteRegister 0x0b val gt gt 8 amp 0x03 Total Disp Line Cnt WF Count 1 0 1 Scroll image 2 up for val OriginalLineCount val gt MinLineCount val 1 WriteRegister 0x0a val
91. 2 write 10b to AUX OE bits 7 6 Table 3 3 SED1352F0B Black To White Look Up Table for 4 Gray Shades Look Up Table hex 0 0 Index hex 1 5 2 A 3 F Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 20 Epson Research and Development Vancouver Design Center 4 LUTs of 4 Entries x 4 Bits LUT b3 b2 bl bO Index 0 0 Llo 1 1 Palette 0 2 2 3 3 Bank Bits 0 4 Bo 110 1 Palette 1 5 Display Data m 2 6 2 Bits Pixel Doce 01 3 i Output Value to 10 i 0 8 Gray Scale Engine u Palette 2 9 2 3 0 1 Palette 3 D 2 E 3 F Figure 3 4 Level Gray Shade Mode Look Up Table Architecture SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 21 Vancouver Design Center 3 2 4 Sixteen Gray Shades Four Bits Pixel When the SED1352 has 4 bit pixels each pixel can index into one of 16 LUT entries The LUT bank bits are ignored in this mode LUT of 16 Entries x 4 Bits b3 b2 bl bO 0 1 2 3 4 5 Display Data x Output Value to Isblilo 7 gt Gray Scale Engine 8 9 A B D E F Figure 4 16 Level Gray Shade Mode Look Up Table Architecture Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 22 Epson Research and D
92. 2x16 Male Header PTH 6 1 H2 Con36A 0 1 2x18 Male Header PTH 7 19 JP1 JP19 Header 3 0 1 1x3 Male Header PTH 8 1 Con40A 40 pin strouded header dual row center key 9 2 J2 J3 M68340EVSP 64A Socket strip wire wray 64 pin 100 064 451 10 1 01 253905 PNP Signal Transistor TO 92 PTH 11 1 Q2 2N3903 NPN Signal Translator TO 92 PTH 12 7 R3 R8 1 ohm 1206 pckg 1 13 4 Dm p E IK 1206 pckg 5 9 resistors resistor network vi EU WE Bourne 4610 101 103 or equivalent 15 4 R11 R14 10K 1206 pckg 5 16 1 R16 100 ohm 1206 pckg 5 17 1 R17 500 ohm Trim Pot Bourns 3386W 1 501 or equivalent 18 1 R19 100K Trim Pot Bourns 3386W 1 104 or equivalent 19 2 R20 R22 100K 1206 pckg 5 20 1 R24 240 ohm 1206 pckg 5 21 2 S1 52 SW DIP 8 Dip Switch 8 position 22 1 53 SW DIP 4 Dip Switch 4 position 23 1 Ul SED1352F 5 100 100 pin SOCKET Supplied by SMOS 100ns 32K byte Static RAM SMOS part number 24 2 U4 US SRM20256LM10 sity P 25 2 U8 U9 741 5688 DW020 SMT 26 2 U10 911 TIBPAL22V10 15BCNT SOCKET Component programmed by SMOS 27 1 912 741 509 D014 SMT 28 2 013 014 SN74LVT16244 SN74LVT 16244 SSOP 29 2 015 016 SN74LVT16245 SN74LVT16244 SSOP 30 2 U17 918 7AHCT244 DW020 SMT 31 1 019 LM317T 3 pin TO 220 regulator 32 1 020 EPN001 XENTECK Negative Power Supply Supplied by SMOS 33 1 U21 OSC 14 SOCKET Only SDU1352B0C Rev 1 0 Evaluation Board User Manual Issue Date 98 10 07 SED1352
93. 6 LUT entries have been written Table 3 1 SED1352F0B Black To White Look Up Table for 16 Gray Shades Look Up Look Up pus Table ni Table hex hex 0 0 8 8 1 1 9 9 2 2 A A 3 3 B B 4 4 C C 5 5 D D 6 6 E E 7 7 F F Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 18 Epson Research and Development Vancouver Design Center Example 4 Initialize an Inverted Look Up Table This example shows how to invert an image by changing only the LUT Inverting means that pixels formally shown as light gray shades now shown as dark gray shades and vise versa It does not matter whether the SED 1352 is in 4 gray shade or 16 gray shade mode 1 Read LUT entry Write LUT index to Look Up Table Address Register AUX OEh Read Old LUT Entry from Look Up Table Data Register AUX OFh 2 Calculate New LUT Entry according to the following formula New LUT Entry 15 Old LUT Entry 3 Write LUT entry back Write LUT index to Look Up Table Address Register AUX OEh Write New LUT Entry to Look Up Table Data Register AUX OFh 4 Repeat steps 1 to 3 until all 16 LUT entries have been changed If Table 3 1 was previously programmed into the SED1352 the new inverted LUT would be the following Table 3 2 SED1352F0B Inverted Look Up Table White To Black Look Up Look Up pen Table Table hex hex
94. 71 31 VAI 2 071 1 012 67 UD3 0 566 2 071 32 VA2 2 071 0 860 68 UD2 0 712 2 071 33 VA3 2 071 0 712 69 UD1 0 860 2 071 34 VA4 2 071 0 566 70 UDO 1 012 2 071 35 5 2 071 0 423 71 LD3 1 168 2 071 36 VA6 2 071 0 281 72 LD2 1 330 2 071 12 X16B C 001 06 __ 5 Pin Pad Center Pad Pin Pad Center No Name Coordinate No Name Coordinate x Y x Y 73 LD1 1 496 2 071 88 BHE 2 071 0 000 74 LDO 1 670 2 071 89 OSCI 2 071 0 140 75 YD 2 021 2 071 90 OSC2 2 071 0 281 76 LP 2 071 1 850 91 DBO 2 071 0 423 77 WE 2 071 1 670 92 DBI 2 071 0 566 78 XSCL 2 071 1 496 93 DB2 2 071 0 712 719 LCDENB 2 071 1 330 94 DB3 2 071 0 860 80 VOE 2 071 1 168 95 DB4 2 071 1 012 81 IOCS 2 071 1 012 96 DB5 2 071 1 168 82 IOW 2 071 0 860 97 DB6 2 071 1 330 83 IOR 2 071 0 712 98 DB7 2 071 1 496 84 MEMCS 2 071 0 566 99 Vss 2 071 1 670 85 MEMW 2 071 0 423 100 Vpp 2 071 1 850 86 MEMR 2 071 0 281 101 Dummy Pad 2 071 2 071 87 READY 2 071 0 140 102 Dummy Pad 2 071 2 071 X16B C 001 06 13 GRAPHICS NE EPSON NEUEN PIN DESCRIPTION Key Analog Input Output Bidirectional Power Bus Interface F1B Pin Pin Name FOB Pin DOB Pad Description D
95. 8 10 08 Epson Research and Development Page 11 Vancouver Design Center Note A Line Byte Count qantas bits per pixel 2 or 4 bits 1 m 4 1 79 4Fh Single Panel Total Display Line Count number of display lines 1 240 1 239 OEFh Dual Panel number of display lines 5 1 Total Display Line Count Example 2 Initialize the registers for a 4 gray shade 640x480 dual panel LCD with 128k of display memory Afterwards write one pixel to the top left corner of the display Program SED1352 Registers 00h 0Dh AUX Register in Binary Data Notes See Also AUX 00h 0000 0000 e must be zero AUX 01h 1100 1000 07 display on normal b6 dual panel panel specific b5 XSCL not masked panel specific b4 LCDE LCDENB pin 0 implementation specific the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on b3 16 grays application specific b2 4 bit LCD data width panel specific bl 16 bit Memory Interface implementation specific 50 RAMS ignored implementation specific AUX 02h 0100 1111 bits 7 0 bits 7 0 of Line Byte Count panel specific see Note A at end of bit 8 of Line Byte Count in bit 0 of AUX 03h panel specific Table for calculation AUX 03h 0000 0110 bits 7 6 Power Save Mode 0 application specific bit 5 LCD interface signals forced to 0
96. A15 Decoder e gt IOCS4 AEN IOW e gt IOW IOR e gt IOR RESET gt RESET optional 4 neu la J pr Decoder lt q 2 SA or 4 through SA9 lt Figure 4 8 Bit Mode ISA example implementation only actual may vary 16 bit ISA Bu LOSDIUTSA Pus SED1352 REFRESH gt SA16 to 5 14 Decoder MEMCS SMEMW gt MEMW SMEMR gt MEMR IOCHRDY 4 READY SD0 to SD15 lt gt DBO to DBI5 SAO to SA19 e e gt ABO to 9 SA10 to SAIS Decoder o e gt IOCS AEN IOW IOW IOR gt IOR SBHE gt BHE RESET RESET 516 Decoder 4 LA17 to LA23 SA 1 or 4 through SA9 MEMCS 16 lt lt Decoder Figure 5 16 Bit Mode ISA example implementation only actual may vary SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center 3 2 Internal Block Diagram IOR IOW IOCS MEMCS Control Registers Page 15 gt Bus Port Signal Decoder Sequence gt LCDENB Translation Controller Memoy lt e J Look Up LCD UD 3 0 READY lt Decoder Table Panel LD 3 0 Interface LP YD WF XSCL COUR 7717
97. ABO0toAB15 D0 to D7 4 gt DBO to DB7 WAITH READY WR gt MEMW RD gt MEMR p IOR p IOW RESET O gt RESET Figure 2 8 Bit Mode Example Z80 example implementation only actual may vary 8086 Maximum mode 8288 SED1352 MS lt CLK S2 so MEN READY p READY S14 psi 5 RESET p RESET 50 gt sos IORC RDY gt low 8284A DT R ALE A16 to A19 e gt AB16 to 19 Al6 Decoder gt M IO c p to AB15 BHE gt BHEs c BHE ADO to ADI5 4 gt 0 16 0 0 MEMCS gt STB D IOCS D0toDI5 4 DBO to DB15 T D be Transceiver gt READY Figure 3 16 Bit Mode Example i8086 maximum mode example implementation only actual may vary Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 14 Epson Research and Development Vancouver Design Center 3 1 2 ISA Bus 8 Bit ISA Bus SED1352 REFRESH gt SA16 to SA13 Decoder MEMCS SMEMW gt MEMW SMEMR gt MEMR IOCHRDY 4 READY 00 to SD7 lt gt DBO to DB7 SAO to SA19 gt ABOto AB19 SA10 to S
98. B0 DB15 I O 94 100 1 91 98 These pins are connected to the system data bus In 8 bit bus mode DB8 DB15 4 11 1 8 must be tied to Vpp In MC68000 MPU interface this pin is connected to the Upper Data Strobe ABO I 12 9 UDS pin of MC68000 In other bus interfaces this pin is connected to the system address bus 1 19 I 13 31 10 28 These pins connected to the system address bus In MC68000 MPU interface this pin is connected to the Lower Data Strobe BHE I 91 88 LDS pin of MC68000 In other bus interfaces this pin is the Bus High Enable input for use with 16 bit system In 8 bit bus mode tie BHE input to Vpp IOCS I 84 81 Active low input to select one of fifteen internal registers In MC68000 MPU interface this pin is connected to the R W pin of MC68000 This input pin will define whether the data transfer is a read active high or write active low cycle In other bus interfaces this is the active low input to write data into an internal register In MC68000 MPU interface this pin is connected to the AS pin of MC68000 IOR I 86 83 This input pin will indicate a valid address is available on the address bus In other bus interfaces this is the active low input to read data from an internal register IOW I 85 82 MEMCS I 87 84 Active low input to indicate the attempt to access the display memory Active low input to write data to the display memory This pin should be tie
99. D0 uu 18 X 146 X X yY Xx X X X Y 16 0 Y Example timing for a 640x480 panel 20 X16B C 001 06 __ 5 MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8 BIT DUAL PANEL 4 LP 240 PULSES LP 2 PULSES YD tp X UD 3 0 LD 3 0 CERES LINE 21242 X LINE sua X LINE 4 244 X 239 479XLINE 240 480 LINE 1 241 LP WF M 4 XSCL 160 CLOCK PERIODS gt XSCL UD3 Aaa Xis X X ccc Y 7 637 7 Y UD2 Ac A X 1 638 X UD1 X 1 639 X UDO pS A ta X 1 8 X X X X X 1 640 LD3 u 241 1 241 5 Y Y X 241 637 X LD2 _ 241 2 241 6 X 241 638 X LD1 _ 241 3 X 241 7 X 241 639 X LDO 241 8 X X 241 640 X Example timing for a 640x480 panel X16B C 001 06 21 GRAPHICS NE EPSON 01352 PACKAGE DIMENSIONS QFP5 100PIN S2 Unit mm SED1352 23 2 0 04 le a 20 0 0 1 81 100 Actual Size 22 X16B C 001 06 AIDE 01352 QFP15 100PIN STD Unit mm SED1352F1B
100. DO 7 VWE 352 VCSO VCS1 0 12 WE 8Kx8 CS Figure 29 8 Bit Mode 8K bytes SRAM VDO 7 VWE SED1352 VCSO VCS1 0 12 WE 8Kx8 CS WE 8Kx8 CS Hardware Functional Specification Issue Date 99 07 28 Figure 30 8 Mode 16K bytes SRAM Requires AUX 01h bit 0 0 Page 57 SED1352 X16 SP 001 16 Page 58 Epson Research and Development Vancouver Design Center VDO 7 VWE 1 WEZ SED1352 ache CS VCSO Oo VCSI n c VA0 14 Figure 31 8 Bit Mode 32K bytes SRAM Requires AUX OIh bit 0 1 VD0 7 WE WE SED1352 8K 32Kx8 32K 8Kx8 CS CS VCSO VCS1 0 14 Figure 32 8 Bit Mode 40K bytes SRAM either 8Kx8 32Kx8 requiring AUX 01h bit 0 0 or 32Kx8 8 8 requiring AUX O1h bit 0 1 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center VDO 7 VWE SED 1352 VCSO VCS1 VAO 14 i al WE 32Kx8 CS WE 32Kx8 CS 9 1 2 16 Bit Mode Figure 33 8 Bit Mode 64K bytes SRAM Requires AUX 01h bit 0 1 VDO 7 VWE SED1352 VCSO 0 12 VCS1 VD8 15 Ed WES 8Kx8 CS
101. EPSON SED1352 Graphics LCD Controller SED1352 TECHNICAL MANUAL Document Number X16B Q 001 06 Copyright 1997 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page ii Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date 98 10 08 Epson Research and Development Page iii Vancouver Design Center CUSTOMER SUPPORT INFORMATION Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of imbedded graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and schematics borrow an evaluation board please contact your local Seiko Epson Corp sales representative Chip Documentation Technical manual includ
102. GRAY EXE SED1352 1352GRAY EXE Display Utility X16 UI 004 08 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller 1352PD EXE Power Down Utility Document Number X16 UI 005 07 Copyright 1996 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352PD EXE Power Down Utility X16 UI 005 07 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center 1352PD EXE POWER DOWN UTILITY 1352PD is an OEM utility program for setting power down modes in the SED1352 LCD Display Controller It provides a simple method for setting power modes during power consumption testing Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS Seiko Epson BIOS1352 version 1 11 or later DOS Progr
103. INGLE x 320 y 240 p 310 When DEMO is started output will be sent to the standard output device This output will present a menu of numbered options SDU1352B0x DEMO PROGRAM Press 1 to read registers Press 2 to show gray shade bar Press 3 to show split screen Press 4 to show panning and scrolling Press 5 to start power saving Press ESC to quit Figure 15 Display for DEMO EXE SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center 6 1 Main Loop Code if hf Page 47 D UNCTION main ESCRIPTION Start of demo program INPUTS Command line arguments R ETURN VALUE None void main char argc char argv while int ch CheckArguments argc argv printf Initializing n Initialize ClearLCDScreen ShowMenu ch getch I n Q switch ch case 1 ShowRegisters break case 2 GrayShadeBars break case 3 SplitScreen break case 4 PanScroll break case 5 PowerSaving break case ESC exit 0 Programming Notes and Examples Issue Date 98 10 08 SED1352 X16 BG 007 04 Page 48 6 2 Initialization Code Epson Research and Development Vancouver Design Center DESCRIPTION FUNCTION Initialize
104. Input Clock Memory Frame Rate KB 3V 3 3V 5V KB 3V 3 3V 5V fosc Interface 8 bit 60 ns 80 ns 2 2 2 170ns 190ns 19 60 ns 80 ns TREE vo 8 bit 90 ns 110 ns 2 2 a 230ns 250ns 90 ns 110 ns THE S 8 bit 115 ns 135 ns 2 2 280ns 300m 115 ns 135 ns Ta MH Hz gt lt 8 bit 150 ns 170 ns 50 ns 70 ns 5 350ns 370ns 150ns 170ns MER TRES o 2 8 bit 200 ns 220 ns 75 ns 95 ns E 240 2 450 ns 470mg Y 200 ns 220 ns PRI Z 8 bit 200 ns 220 ns 75 ns 95 ns 200 235 470ns 2008 220ns MHz TUE Table 9 5 Memory Size Requirement Number of Horizontal Pixels 320 Number of Horizontal Pixels 320 4 Grays 16 Grays 2 Example 2 bits per pixel 4 bits per pixel Displa Access Time Access Time isp ay Size Size Input Clock Memory sv KB 3V 33V sv Gao een Interface N 9s 8 bit 115 ns 135 ns 2 2 A 375 300ns 115 135ns eee vo 8 bit 150 ns 170 ns 50 ns 70 ns MA Seb 350 370ns 97 150ns 170ns MUR us S 9 8 bit 200 ns 220 ns 75 ns 95 ns 320 59 450ns 470ns 50 200ns 220ns S MHz s gt A 8 bit 280 ns 300 ns 115 ns 135 ns epe F 6155 630ns 0 280ns 300ns vine 2 8 bit 280 ns 300 ns 115 ns 135 ns g 20 44 6153 635ns 3 280ns 300ns PS E 2
105. M Utility X16 UI 003 08 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller 1352GRAY EXE Display Utility Document Number X16 UI 004 08 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352GRAY EXE Display Utility X16 UI 004 08 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center 1352GRAY EXE DISPLAY UTILITY 1352GRAY is a menu driven display utility for the SED1352 which demonstrates the gray shades and available palettes For 128K bytes of display memory and a panel size of 640x400 or less either 4 or 16 gray shades are available If the panel size is greater than 640x400 only 4 shades of gray are available For 64K bytes of display memory and a panel size of 640x200 320x240
106. Memory Interface is set to 16 bits the Address Pitch Adjustment Register refers to words 3 Determine the number of pixels per unit referred to by the Address Pitch Adjustment Register The Address Pitch Adjustment Register refers to units of words so find the number of pixels per word 16 gray shades 4 bits per pixel 4 bits per pixel gt 2 pixels per byte pixels per word pixels per byte x 2 2 2x2 4 pixels per word 4 Calculate the number of pixels on a horizontal scan line not visible virtual display width in pixels panel width in pixels 640 320 320 hidden pixels Consequently on a screen update the SED1352 will show the first 320 of 640 pixels and then ignore the remaining 320 pixels in order to reach the next scan line 5 Program the Address Pitch Adjustment Register number of hidden horizontal pixels _ B 80 words 50h words pixels per word Therefore AUX 0Dh 50h 6 view the rest of the image refer to Section 5 5 Panning and Scrolling on page 42 keeping in mind that the hor izontal width is 640 pixels not 320 Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 30 Epson Research and Development Vancouver Design Center 5 2 Bitmaps and Text Displays For the scope of this guide a bitmap is a data structure which represents the image shown on the LCD The bitmap includes the dimensions of the image and the gray shade palette used to program the look
107. Note The states of these data pins are internally latched during RESET Register Setting AUX O1h bit 1 0 for 16 bit memory interface must be 16 bit with a 16 bit bus MC68340 Interface Considerations SED1352 Issue Date 98 10 08 X16 AN 004 06 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16 AN 004 06 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller LCD Panel Options Memory Requirements Document Number X16 AN 005 07 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center 1 Figure 1 8 B
108. ON SED1352 Dot Matrix Graphics LCD Controller Programming Notes and Examples Document Number X16 BG 007 04 Copyright 1996 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTRODUCTION s te ee Rew Eee we WU w A eS ee 7 INITIALIZING THE SED1352 8 GRAY SHADES AND LOOK UP TABLES 15 eh rw e ae Be ae ab mem a S l Two Bit Pixels ane eb he ee CE AU be p eee S W 15 3 1 2 Four Bit Pixels ogc e se EAA A S EE EE
109. OS path or not on your system File is not GIF89a format The GIF file contains an invalid format 1352SHOW only supports GIF89a format Insufficient video memory for second image There is not enough video memory available to store both images Invalid format in the GIF file Use non interlaced GIF89a format SED1352 1352SHOW EXE Display Utility X16 UI 001 08 Issue Date 98 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller VIRTUAL EXE Display Utility Document Number X16 UI 002 08 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 VIRTUAL EXE Display Utility X16 UI 002 08 Issue Date 08 10 08 Epson Research and Development Page 3 Vancouver Design Center VIRTUAL EXE DISPLAY UTILITY VIRTUAL EXE demonstrates th
110. S 1352 loaded it will try to interpret the BIOS settings Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS Seiko Epson BIOS1352 COM optional DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Note 1352READ uses stdout calls and may be redirected to a file or piped to a DOS filter such as MORE COM Installation Copy the file 1352read exe to a directory that is in the DOS path on your hard drive Usage From DOS prompt type the following 1352read port Where 1352read without any argument will read the SED1352 registers including the gray shade lookup table port is the SED1352 port address in hex e g 310 produces a usage message Example to generate a report simply type 1352read port report txt and the information which 1352READ obtains will be stored in the file report txt 1352READ EXE Diagnostic Utility SED1352 Issue Date 98 10 08 X16 UI 006 06 Page 4 Epson Research and Development Vancouver Design Center Comments tis not necessary to specfy a port address if BIOS1352 has previously been loaded 1352READ will search for BIOS 1352 COM If this program is found the port address reported by BIOS1352 will be used If the port address is specified on the 1352READ command line the two port addresses are compared and if different an
111. SET Memory Interface This bit selects between the 8 bit or 16 bit memory interface When this bit 0 the 16 bit memory inter face is selected When this bit 1 the 8 bit memory interface is selected If 16 bit bus interface is selected VDO 1 on RESET the Memory Interface bit is forced to 0 internally 16 bit This bit goes low on RESET RAMS This bit configures the display memory address lines for an 8 bit memory interface system When this bit 0 addressing for 8Kx8 SRAM on an 8 bit display memory data bus interface is selected When this bit 1 addressing for 32Kx8 SRAM on an 8 bit display memory data bus interface is selected This bit goes low on RESET This bit is ignored for a 16 bit memory interface Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 48 Epson Research and Development Vancouver Design Center AUX 02h Line Byte Count Register LSB I O address 0010b Read Write Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Count Bit 7 Count Bit6 Count Bit5 Count Bit4 Count Count Bit 2 Count Bit 1 Count Bit 0 bits 7 0 Line Byte Count Bits 7 0 These are the 8 LSB of the 9 bit Total Display Line Count and represent the number of scan lines 1 to a maximum value of 3FFh 1024 scan lines Line Byte Count Bit 8 is located in register AUX 05h and is ignored in the 16 bit memory interface To c
112. Standard FPDI 1 Table 5 4 Clock Inputs F1B D0B Pin Name FOB Pin Pin it s 4 Driver Description This pin along with OSC2 is the 2 terminal crystal interface OSCI I 92 89 when using a 2 terminal crystal as the clock input If an external oscillator is used as a clock source then this pin is the clock input This pin along with OSCI is the 2 terminal crystal interface when using a 2 terminal crystal as the clock input If an external OSes 2 oscillator is used as a clock source this pin should be left unconnected Table 5 5 Power Supply F1B DOB Pin Name Type FOB Pin Pin Pad Driver Description VDD 3 53 50 100 P Voltage supply Vss 2 52 49 99 Voltage ground SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center 5 1 Summary of Configuration Options Page 25 The SED1352 requires some configuration information on power up This information is provided through the SRAM data lines VD 0 15 The state of these pins are read on the falling edge of RESET and used to configure the following options Table 5 6 Summary of Power On Reset Options Pin Name value on this pin at falling edge of RESET is used to configure 1 0 1 0 VDO 16 bit host bus interface 8 bit host bus interface VDI Use direct mapping for I O accesse
113. TS2 CO2 TS2D2 Io 6 mA Veg 04 V Type 3 TS3 IoL 12 mA Type 4 TS4 CO4 24 mA Low Level Output Voltage Voi 3 3 2 TS2 CO2 TS2D2 3mA 0 3 Type 3 TS3 IoL 6mA Type 4 TS4 CO4 IoL 12mA Low Level Output Voltage Vor 3 0 2 TS2 CO2 TS2D2 3mA 0 3 Type 3 TS3 5 mA 4 TS4 CO4 10mA High Level Output Voltage 5 0 2 TS2 CO2 TS2D2 2 mA Vpp 0 4 V Type 3 TS3 4 mA Type 4 TS4 CO4 8 mA Low Level Output Voltage 3 3 Type 2 TS2 CO2 TS2D2 1 mA Vpp 0 3 V Type 3 TS3 2 mA Type 4 TS4 CO4 4 mA High Level Output Voltage 3 0 Type 2 TS2 CO2 TS2D2 1 mA Vpp 0 3 V Type 3 TS3 1 8 mA Type 4 TS4 CO4 3 5 mA Ioz Output Leakage Current 1 1 uA Output Pin Capacitance 6 pF Bidirectional Pin Capacitance 10 pF Hardware Functional Specification SED1352 X16 SP 001 16 Page 28 7 A C CHARACTERISTICS Conditions Vpp 3 0V 10 3 3V 10 or 5 0V 10 40 C to 85 Tise and for all inputs must be lt 5 nsec 10 90 80pF Bus MPU Interface 100pF LCD Panel Interface 20pF Display Memory Interface 7 1 Bus Interface Timing 7 1 1 MC68000 Interface Timing Note All input timing parameters are based
114. Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Vpp Supply Voltage 0V 2 7 3 0 3 3 5 0 5 5 V Vin Input Voltage Vss Vpp V fosc 6 MHz lopp Operating Current 16 stays 3 0 3 5 7 0 mA Topr Operating Temperature 40 25 85 fosc 6 MHz Pryp Typical Active Power Consumption QSC z 9 0 11 55 35 0 mW 16 grays Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units Low Level Input Voltage Vpp 3 0V 0 6 V Vpp 5 5V 2 0 Vig High Level Input Voltage Vpp 3 6V 2 5 V Vpp 3 3V 2 3 VDD gt 5 0 2 4 Positive going Threshold Vpp 3 3 2 4 V Negative going Threshold Vpp 3 3 0 6 V VDD 5 0 0 1 Hysteresis Voltage Vpp 3 3 0 1 V VDD 3 0 0 1 Input Leakage Current 1 1 uA SED1352 Hardware Functional Specification Issue Date 99 07 28 Issue Date 99 07 28 Epson Research and Development Page 27 Vancouver Design Center Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units Cin Input Pin Capacitance 4 pF Vpp 5 0V Rpp Pull Down Resistance Ta V 50 200 kQ I DD Vpp 3 3V Rpp Pull Down Resistance Ta V 90 360 kQ I DD Vpp 3 0V Rpp Pull Down Resistance y 100 400 kQ DD Table 6 4 Output Specifications Symbol Parameter Condition Min Typ Max Units Low Level Output Voltage Vor 5 0V 2
115. To display vertical bars this routine assumes that pVideo points to the beginning of a scan line In addition this routine assumes that the Address Pitch Adjustment Register is 0 no virtual display To write one vertical line first write one pixel to the first byte pointed to by pVideo Write the next pixel to the byte on the next scan line pointed to by pVideotBytesPerScanLine this only works if the Address Pitch Adjustment Register is 0 Continue writing pixels by going down each scan line pVideoStart pVideo for 0 lt PanelY for Bar for BarWidth 0 BarWidth lt 10 BarWidth if PanelGrayLevel 4 In the 4 gray level mode each pixel is stored as two bits Since a byte holds 8 bits there are 4 pixels per byte 0 Bar lt PanelGrayLevel Bar The variable val represents the pixel value val Bar 4 pVideo unsigned char val lt lt 6 val lt lt 4 val lt lt 2 val else SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 55 Vancouver Design Center z val Bar pVideot In the 16 gray level mode each Since a byte holds 8 bits The variable val 16 unsigned char val lt lt 4 pixel is stored as four bits there are 2 pixels per byte represents the pixel value val
116. V 25MHz Pixel Clock 12MHz Pixel Clock 6MHz Pixel Clock SOQ NNS a2oIMI EUWU UBEoI IO I V0 IEL III9G I lt I I II I I I I Q QII II IKIII WU I I IWIIIIIIIIIIMIIUIIAQAII iii 40 35 30 N Mul a D gt 1 2 Pattern ACTIVE Pattern 00h Operating Mode Units mW mW mW PD2 0 2 0 3 0 0 PD1 3 3 2 2 0 2 lt gt lt 6 2 5 E 5 E 9 25 2 12 2 6MHz Power Consumption 98 10 08 Issue Date X16 AN 006 06 SED1352 EPSON SED1352F0B Dot Matrix Graphics LCD Controller ISA Bus Interface Considerations Document Number X16 AN 003 05 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain mate
117. a maximum 16MHz bus clock Epson Research and Development Vancouver Design Center IOW Timing AB 9 1 04 VALID X t2 IOCS AS t3 tl gt R W t4 UDS LDS INVALID DTACK Hiz lt Hi Z 5 E gt DB 15 0 Hiz VALID Hz Figure 10 IOW Timing 68000 Table 7 1 IOW Timing 68000 3V 3 3V 5V Symbol Parameter Min Typ Min Max Units tl AB 9 1 valid before AS falling edge 10 0 ns t2 AB 9 1 hold from AS rising edge 20 10 ns 3 IOCS hold from AS rising edge 0 0 ns t4 UDS LDS valid before AS rising edge 30 20 ns t5 UDS LDS falling edge to DTACK falling edge 40 25 ns t6 AS rising edge to DTACK hi z delay 45 25 ns t7 DB 15 0 setup to AS rising edge 20 10 ns t8 DB 15 0 hold from AS rising edge 20 10 ns SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Vancouver Design Center IOR Timing Page 29 AB 9 1 X VATIB IOCS t2b lt AS t2a UDS LDS INVALID R W DTACK Hi Z 15 lt 4 DB 15 0 Hi Z VALID Figure 11 IOR Timing 68000 Table 7 2 IOR Timing 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units
118. al panel configuration by changing the Screen 2 Display Start Address However by using this method screen 2 is limited to the lower half of the display This register is ignored in dual panel mode AUX 0Dh Address Pitch Adjustment Register I O address 1101b Read Write Addr Pitch Adjustment Bit 7 Addr Pitch Adjustment Bit 6 Addr Pitch Adjustment Bit 5 Addr Pitch Adjustment Bit4 Addr Pitch Adjustment Bit 3 Addr Pitch Adjustment Bit2 Addr Pitch Adjustment Bit 1 Addr Pitch Adjustment Bit 0 bits 7 0 SED1352 X16 SP 001 16 Addr Pitch Adjustment Bits 7 0 These bits set the numerical difference between the last address of a display line and the first address in the following line If the Address Pitch Adjustment is not equal to zero then a virtual screen is formed The size of the virtual screen is only limited by the available display memory The actual display output is a window that is part of the whole image stored in the display memory For example with 128K of display memory a 640x400 16 gray image can be stored If the output display size is 320x240 then the whole image can be seen by changing display starting addresses through AUX 06h and 07h and AUX 08h and 09h Note that a virtual screen can be produced on either a single or dual panel Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Page 53 Vancouver Des
119. alculate the Line Byte Count use the following formula BitsPerPixel LineByteCount SS Memorylnterface Wiqrh x HorizontalResolution 1 Example To calculate the Line Byte Count for 640 horizontal pixels with 16 gray shades 4 bits per pixel and 16 bit memory interface 4BitsPerPixel LineByteCount 640 1 159 The following two tables summarize the maximum value of the Line Byte Count Register for different dis play modes and display memory interface Table 8 1 Maximum Value of Line Byte Count Register 8 Bit Display Memory Interface Maximum Value of Corresponding Maximum Display M f Pixels 1 isplay Mode Line Byte Count Register Number of Pixels in One Display Line 4 level gray shades OFFh 256 x 4 1024 16 level gray shades 1FFh 512 x 2 1024 Table 8 2 Maximum Value of Line Byte Count Register 16 Bit Display Memory Interface Corresponding Maximum Maximum Value of P Display M f Pixels 1 isplay Mode Line Byte Count Register Number of Pixels in One Display Line 4 level gray shades OFFh 256 x 8 2048 16 level gray shades OFFh 256 x 4 1024 AUX 03h Line Byte Count Power Save Register MSB I O address 0011b Read Write PS PS LCD Signal LUT n a afa T Line Byte Bit 1 Bit 0 State Bypass Count Bit 8 bits 7 6 PS Bits 1 0 Selects the Power Save Modes as shown in the following table The PS bits 1 0 go
120. allowed Memory read write is disabled e Master clock for display memory access is disabled LCD outputs are either forced low AUX 03h bit 520 or high impedance AUX 03h bit 5 1 e Internal oscillator is disabled 8 3 8 Power Save Mode Function Summary Table 8 6 Power Save Mode Function Summary Power Save Mode PSM Functi PSMI unction Normal S PSM2 Active State 1 State 2 Display Active Yes No No No I O Access Possible Yes Yes Yes Yes Memory Access Possible Yes Yes No No Sequence Controller Running Yes No No No Internal Oscillator Disabled No No No Yes 8 3 4 Pin States in Power Save Modes Table 8 7 Pin States in Power Save Modes Pin State Pi PSM1 in Normal S PSM2 Active State 1 State 2 UD 3 0 LD 3 0 LP SC YD WE Active E eum Note 1 P P P UD 3 0 LD 3 0 LP XSCL YD WF Active Forced Low Forced Low Forced Low Note 2 AB 19 0 DB 15 0 Active Active Active Active IOR IOW Active Active Active Active MEMR MEMW Active Active Active Active RESET Active Active Active Active Note Internal Register AUX 03h bit 5 1 Internal Register AUX 03h bit 5 0 SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center 9 DISPLAY MEMORY INTERFACE 9 1 SRAM Configurations Supported 9 1 1 8 Bit Mode SED1 V
121. am Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Installation Copy the file 1352pd exe to a directory that is in the DOS path on your hard drive Usage 1352PD is run from the DOS command line as follows 1352pd ModeNumber Where ModeNumber isa decimal number 0 1 or 2 for the desired power down mode Example typing the following command line activates power down mode 2 1352pd 2 ENTER Output from the program can be redirected to an external DOS device such as a terminal attached to the serial port such as COMI as shown below 1352pd 2 gt coml ENTER Striking any key will set mode state 0 no power down 1352PD EXE Power Down Utility SED1352 Issue Date 98 10 08 X16 UI 005 07 Page 4 Epson Research and Development Vancouver Design Center Comments 1352PD EXE requires BIOS 1352 COM to be loaded prior to running The following power modes are supported Mode 0 Mode 0 operates at full power Mode 1 or 2 SED1352 will engage power down mode 1 or 2 SED1352 LUT will be disabled and all LCD signals are forced low Program Messages Power Down Mode xx is set The power down mode xx has been set This message may not be visible if the active display controller is the SED1352 ERROR Cannot set power mode xx 1352PD EXE cannot set the power down mode requested The power down mode must be 0 1 or 2 ERROR
122. apped address index data write the index data of the register to be accessed read data IOW I O mapped address index write to the indexed register mapped address 1 read the indexed register Note Bits marked n o should be set to 0 in the following registers 8 1 Register Descriptions AUX 00h Test Register I O address 0000b Read Write Test Mode peeved Test Input Test Input Test Input Test Output Test Output Test Output Enable Select Bit2 Select Bit Select BitO Select Bit2 Select Bit1 Select Bit 0 bit 7 Test Mode Enable When this bit 0 normal operation is enabled When this bit 1 the chip is placed in a special test mode The test input bits and test output bits bits 6 0 are used to select various internal test functions bit 6 Reserved During normal operation this bit must 0 bits 5 0 Test Mode Input Bits 2 0 and Output Bits 2 0 When bit 7 1 these are the Test Input Select Input and Output bits When bits 6 and 7 0 normal opera tion these bits may be used as read write scratch registers SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 47 Vancouver Design Center AUX 01h Mode Register address 0001b Read Write DISP Panel LCDE Gray Scale Mask LCD Data Memory Width Interface RAMS XSCL bit 7 bit 6 bit 5
123. b5 XSCL not masked panel specific b4 LCDE LCDENB pin 0 implementation specific the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on b3 16 grays application specific b2 4 bit LCD data width panel specific b1 16 bit Memory Interface implementation specific b0 RAMS ignored implementation specific AUX 02h 0100 1111 bits 7 0 bits 7 0 of Line Byte Count panel specific bit 8 of Line Byte Count in bit 0 of AUX 03h panel specific see Note A at end of Table for calculation AUX 03h 0000 0110 bits 7 6 Power Save Mode 0 application specific bit 5 LCD interface signals forced to 0 during Power Save implementation specific bit 4 no LUT bypass application specific bits 3 1 not used bit 0 bit 8 of Line Byte Count panel specific see AUX 02h see Section 5 6 Power Saving on page 44 AUX 04h 1110 1111 bits 7 0 bits 7 0 of Total Display Line Count panel specific bits 9 8 of Total Display Line Count in bits 1 0 of AUX 05h panel specific see Note B and C at end of Table for calculation AUX O5h 0000 0000 bits 7 2 WF not required panel specific bits 1 0 bits 9 8 of Total Display Line Count panel specific see AUX 04h SED1352 X16 BG 007 04 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Vancouv
124. ble 9 4 Memory Size Requirement Number of Horizontal Pixels 440 63 Table 9 5 Memory Size Requirement Number of Horizontal Pixels 320 63 Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 List of Figures 16 68000 Series 8 Bit Mode Example 780 16 Bit Mode Example 18086 maximum mode 8 Bit Mode 5 16 Bit Mode 5 Internal Block Diagram SED1352F0B Pinout Diagram SED1352F1B Pinout SED1352D0B Pad IOW Timing 68000 IOR Timing 68000 Timing 68000 MEMR Timing
125. ctor Mono STN LCD Comments Pin Name Pin No 8 bit 4 bit LDO 1 LDO Lower panel display data for dual panel dual drive LD1 3 LD1 mode In 8 bit single panel single drive mode these LD2 5 LD2 are the least significant 4 bits of the 8 bit output data to the panel data 3 0 In 4 bit single panel mode LD3 7 LD3 these outputs are low UDO 9 UDO UDO Upper panel display data for dual panel dual drive UDI 11 UDI UDI mode In 8 bit single panel single drive mode these UD2 B UD2 are the most significant 4 bits of the 8 bit output data to the panel data 7 4 In 4 bit single panel mode UD3 15 UD3 UD3 these are the 4 data bits output to the panel 17 31 N C odd pins XSCL 33 XSCL XSCL Shift Clock for LCD data NC 35 LP 37 LP LP Latch Pulse output YD 39 YD YD Vertical Scanning Start Pulse GRND 208 GRND GRND Logic Ground even pins N C 28 VLCD 30 VLCD VLCD Negative power supply output 18V to 23V VCC 32 5V 5V 12V 34 12V 12V VDDH 36 VDDH VDDH power supply output 23V to 40V WE 38 WE WF LCD backplane Bias signal LCDENB 40 LCDPWR LCDPWR LCD power control to external supply SDU1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 10 Epson Research and Development CPU BUS Interface Connector Pinouts Table 1 5 CPU BUS Connector Pinout Vancouver Design Center
126. d to MS B 88 M Vpp in an MC68000 MPU interface MEMR I 89 86 Active low input to read data from the display memory This pin should be tied to Vpp in an MC68000 MPU interface For MC68000 MPU interface this pin is connected to the DTACK pin of MC68000 and will be driven low when ever a data transfer is complete In other READY 90 87 bus interfaces this output is driven low to force the system to insert wait states when needed READY is placed in a high impedance Hi Z state after the transfer is completed RESET I 32 29 Active high input to force all signals to their inactive states 14 X16B C 001 06 NEUEN Display Memory Interface F1B Pin Pin Type Pin DOB Pad Description These pins are connected to the display memory data bus For 16 bit interface VDO VD7 are connected to the display memory data bus of even byte addresses and VD8 VD15 are connected to the display memory data bus of odd byte VDO VDI5 2 B addresses The output drivers of these pins are tri stated when RESET is high On the falling edge of RESET the values of VDO VD15 are latched into the chip to configure various hardware options VDO VD15 each have an internal pull down resistor 33 43 30 40 VAO VAI5 O 62 66 59 63 These pins are connected to the display memory address bus VCS 1l 69 66 Active low ch
127. dress is available 1987 I 86 83 TILS on the address bus In other bus interfaces this is the active low input to read data from an internal register MEMCS 1 87 84 TTLS Active low input to indicate the attempt to access the display memory Active low input to write data to the display memory This pin MIENNE m Bum should be tied to Vpp in an MC68000 MPU interface SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Vancouver Design Center Page 23 Table 5 1 Bus Interface Continued F1B D0B Pin FOB Pin Pin Pad Driver Description Active low input to read data from the display memory This pin 5 39 should be tied to Vpp in an 68000 MPU interface For MC68000 MPU interface this pin is connected to the DTACK pin of MC68000 and is driven low when ever a data transfer is complete In other bus interfaces this output is driven READY 90 87 TS3 low to force the system to insert wait states when needed READY is placed in a high impedance Hi Z state after the transfer is completed RESET I 32 29 5 Active high input to force all signals to their inactive states Table 5 2 Display Memory Interface F1B DOB Pin Name Type FOB Pin Pi is 4 Driver Description These pins are connected to the display memory data bus For 16 bit interface VDO VD7 are connected to the dis
128. e Screen 1 Display Start Address AUX 06h AOh AUX 07h 80h 4 FOR DUAL PANELS ONLY Add the number of words in a virtual scan line to the Screen 2 Display Start Address Register In this example the Screen 2 Display Start Address has previously been initialized as described in Section 5 4 4 1 Displaying a Single Image on a Dual Panel on page 40 ber of bytes i irtual li Screen 2 Display Start Address Screen 2 Display Start Address 2 bytes per word 5 FOR DUAL PANELS ONLY Program the Screen 2 Display Start Address AUX 08h least significant byte of Screen 2 Display Start Address AUX 09h most significant byte of Screen 2 Display Start Address Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 44 Epson Research and Development Vancouver Design Center 5 6 Power Saving The following section introduces the power saving capabilities of the SED1352 A detailed description of the Power Save Register is provided followed by a description of the power save modes 5 6 1 Registers Note Register bits discussed in this section are highlighted AUX 03 Line Byte Count MSB bit 8 for 16 level gray scale mode only Power Save Register address 0011b Read Write LCD Signal LUT Line Byte State Bypass us ki Count Bit 8 bits 7 6 PS Bits 1 0 Selects the Power Save Modes as shown in the following table The PS bits 1 0 go
129. e monochrome LUT data AUX OEh 0000 0110 lincrement palette address AUX OFh 0000 0110 write monochrome LUT data AUX OEh 0000 0111 Jincrement palette address AUX OFh 0000 0111 write monochrome LUT data AUX OEh 0000 1000 lincrement palette address AUX OFh 0000 1000 write monochrome LUT data AUX OEh 0000 1001 lincrement palette address AUX OFh 0000 1001 write monochrome LUT data AUX OEh 0000 1010 Jincrement palette address AUX OFh 0000 1010 write monochrome LUT data AUX OEh 0000 1100 lincrement palette address AUX OFh 0000 1100 write monochrome LUT data AUX OEh 0000 1101 lincrement palette address AUX OFh 0000 1101 write monochrome LUT data AUX OEh 0000 1110 Jincrement palette address AUX OFh 0000 1110 write monochrome LUT data AUX OEh 0000 1111 lincrement palette address AUX OFh 0000 1111 write monochrome LUT data Program Mode Register bit DISP to 1 and set LCDE to enable power supply 1001 0000b OR original value for 01 1 AUX OIh 1001 1000 p7 display on application specific b4 LCDE LCDENB pin set to enable specific power supply design for SDU1353B0C set bit to 1 to enable power supply application specific Write one pixel to the top left corner of display memory If the SDU1352B0Xx evaluation board is used video memory begins at D000 0000h in this case write OFOh to location D000 0000h SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 9
130. e up page down home and end keys 1352show picturel gif displays the named GIF image 1352show dog gif cat gif displays the two named GIF images in a split screen Screen two may be scrolled up and down using the arrow page up page down home and end keys Pressing the ESC key will terminate the program 1352SHOW EXE Display Utility SED1352 Issue Date 98 10 08 X16 UI 001 08 Page 4 Epson Research and Development Vancouver Design Center Comments 13525 requires BIOS 1352 COM to be loaded prior to running Split screen viewing is only allowed on single panels The size of screen two is determined by available memory and number of gray shades If there is insufficient memory for screen two 1352SHOW will not accept the two image files and will generate an error message When loading two GIF images it may take several seconds of apparent inactivity to load the second image into memory The GIF format must be 16 color non interlaced GIF89a format 13525 will clear the screen when the Esc key is pressed Program Messages ERROR Split screen available for single panel only Split screen viewing is only allowed on single panels ERROR This program requires BIOS1352 to be loaded The program BIOS1352 COM must be run before 1352SHOW Load BIOS1352 COM and re run 1352SHOW EXE File filename not found or cannot be opened for reading The GIF file you are trying to display is not in your D
131. e virtual panning capabilities of the SED1352 An image larger than the display resolution is loaded in display memory VIRTUAL EXE will then display a portion of the complete image while providing panning capabilities using the arrow keys for navigation Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS Seiko Epson BIOS1352 version 1 11 or later DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Installation Copy the file virtual exe to a directory that is in the DOS path on your hard drive Usage VIRTUAL is invoked from the DOS command line as follows virtual x n y n Where x is the horizontal resolution in multiples of 8 y is the vertical resolution produces a usage message If the user does not provide the virtual size the program will automatically select the size based on memory and panel size The user can then navigate throughout the image using the arrow keys to pan and scroll the screen Pressing the ESC key terminates the program Comments VIRTUAL requires BIOS1352 COM to be loaded prior to running VIRTUAL forces four gray shade mode regardless of original BIOS1352 settings The original BIOS1352 settings are restored on exiting VIRTUAL VIRTUAL EXE Display Utility SED1352 Issue Date 08 10 08 X16 UI 002 08 Page 4 Epson Research and Development Vancouve
132. earch and Development Vancouver Design Center Page 11 3 2 2 Register settings AUX 00h 0000 0000 not in test mode AUX 01h 1001 000 4 bit single panel 4 gray shades 16 bit display memory interface AUX 02h 0100 1111 horizontal resolution 640 4 gray shades 4 pixels per byte 8 pixels per fetch AUX 03h 0000 0000 notin power save modes AUX 04h 1110 1111 total 240 scan lines AUX 05h 200000000 WFz0 AUX 06h 0000 0000 AUX 07h 0000 0000 default starting address at 0000h with AUX 06h AUX 08h xxxx don t care when not using split screen AUX 09h xxxx don t care when not using split screen 1110 1111 together with AUX OBh bit1 0 should be the same as or larger than AUX 05h bit1 0 and AUX OBh xxxx xx00 AUX 04h when not using split screen AUX ODh 0000 0000 no virtual screen Example setting of Look up Table when using bank 2 for display AUX 0Eh 10xx 1000 index 8 AUX OFh 2 xxxx 0000 gray 0 AUX 0Eh 10xx 1001 index 9 AUX OFh xxxx 0101 5 AUX 0Eh 10xx 1010 index AUX OFh xxxx 1010 gray A AUX OEh 10 1011 index B AUX OFh 2 xxxx 1111 gray x don t care Note When LCDENB bit 4 of AUX 01h is used to control the LCD power the following sequence is recommeded to setup the AUX registers of the SED1352 1 Write to bit 4 of AUX OIh with value 0 2 Setup the AUX registers accordingly 3 Dela
133. earch and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16 AN 003 05 Issue Date 98 10 08 Epson Research and Development Page 5 Vancouver Design Center 1 INTRODUCTION The SED1352FOB is a general purpose LCD controller capable of interfacing to a variety of microprocessors This interface is accomplished through the use of minimal external circuitry This application note describes the interface between the SED1352FOB and the ISA Bus 1 1 Reference Material Refer to the SED1352F0B Hardware Functional Specification X16 SP 001 xx for complete AC timing details This document makes no attempts to describe the operation of the ISA Bus please refer to the appropriate ISA Bus documentation for complete information ISA Bus Interface Considerations SED1352F0B Issue Date 98 10 08 X16 AN 003 05 Page 6 Epson Research and Development Vancouver Design Center 2 16 BIT ISA BUS INTERFACE For the purpose of the example shown below the following conditions are set by default 1 Indexing I O with addresses 0310h and 031 1h see Configuration Options 2 128Kbytes of display memory occupying C D segments see Configuration Options Note This memory configuration will conflict with a VGA card installed on the same bus therefore either a serial terminal or monochrome display adapter is recommended as the primary console This section provides the necessary equations and setti
134. ed by a READY or one 1 Mbit SRAM 64Kx 16 WAIT signal one or two 32Kbyte SRAM s one or two 8Kbyte SRAM s one 8Kbyte and one 32Kbyte SRAM LCD panel configurations single panel single drive display dual panel dual drive display option to use built in index register or direct mapping to access one of fifteen internal registers 2 terminal crystal input for internal or external crystal oscillator 8 16 bit SRAM interface configurations maximum number of vertical lines two software power save modes 1 024 lines single panel single drive display low power consumption 2 048 lines dual panel dual drive display display modes split screen display support at single panel mode 2 bit pixel 4 level gray scale display package 4 bit pixel 16 level gray scale display QFP5 100 S2 package FOB virtual display support or QFP15 100 STD package F1B SYSTEM BLOCK DIAGRAM LCD PANEL X16B C 001 06 1 GRAPHICS _ NN EPSON NEUEN B INTERFACE OPTIONS Interface with 16 Bit MC68xxx MPU and 16Kbytes SRAM 2 of 8K x 8 MC68xxx SED1352 2s E im Decoder D gt MEMCS 16 14 VD8 15 Decoder IOCS 2 ecoder A10 to A19 VWE M M Alto 19 ABI to AB19 WE WE 0 1516 DBO to DB15 64 Kbit 64 Kbit DTACK 4 READY CS CS UDS gt ABO LDS gt BHE VCSO VCS 1 AS gt IOR
135. el power saving n getch val amp 0x38 WriteRegister 3 val Cancel power saving mode 2 FUNCTION PowerSaving DESCRIPTION Starts power saving mode 2 INPUTS None RETURN VALUE None This is an optional method of power saving void PowerSaving void static unsigned int val printf Starting Power Saving n The following are the steps to enter a power save mode Step 1 Turn off display val ReadRegister 1 val amp Ox7f WriteRegister 1 val Step 2 Disable LCDE turn off LCD power supply For the SDU1353B0C set LCDE bit to 0 val ReadRegister 1 val amp Oxef WriteRegister 1 val Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 64 Epson Research and Development Vancouver Design Center Step 2 Wait for LCD power supply to drop to zero volts For the SDU1353BO0C wait about a half second Delay 500 Step 3 Enter Power Save Mod val ReadRegister 3 val amp 0x3f val 0x80 WriteRegister 3 val Set power saving mode 2 printf Press any key to cancel power saving n getch The following are the steps to exit a power save mode Step 1 Exit Power Save Mode val ReadRegister 3 val amp 0x3f WriteRegister 3 val Cancel power saving mode
136. els two pixels are grouped into one byte of display memory as shown below Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 1 Pixel 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 When these pixels are shown Pixel 0 is seen to be left of Pixel 1 Programming Notes and Examples Figure 2 Pixel Storage for 4 Bits 16 gray shades in One Byte of Display Memory Issue Date 98 10 08 X16 BG 007 04 Page 16 Epson Research and Development Vancouver Design Center 3 2 Look Up Table LUT This section provides a concise description of the LUT registers followed by a description of a LUT Next is a series of examples which show how to initialize a LUT create an inverted LUT and how to select one of four banks in the 4 gray shade mode 3 2 1 LUT Registers Note Register bits discussed in this section are highlighted AUX 0E Look Up Table Address Register T O address 11106 Read Write Bank Bank ID Bit ID Bit Palette Palette Palette Palette Bit 1 Bit 0 Read Only Read Only Address Address Address Address y Bit 3 Bit 2 Bit 1 Bit 0 The SED1352 has one internal 16 position 4 bit wide Look Up Table palette The 4 bit value programmed into each table position determines the output gray shade of display data For example in 16 level gray shade mode a data value of 0001h 4 bits per pixel wi
137. er Design Center Page 9 AUX Register Data in Binary Notes See Also AUX 06h AUX 07h 0000 0000 1000 0000 bits 7 0 bits 7 0 of Screen 1 Display Start Address application specific bits 15 8 of Screen 1 Display Start Address in AUX 07h application specific Screen Display Start Address points to D000 0000h when 0000h Screen 1 Display Start Address is located at D000 0000h bank 0 on the SDU1353B0C bits 7 0 bits 15 8 of Screen 1 Display Start Address application specific see AUX 06h see Section 4 2 1 SDU1352B0x Evaluation Board Display Memory on page 24 and Section 4 1 Registers on page 22 AUX 08h AUX 09h 0000 0000 1000 0000 bits 7 0 bits 7 0 of Screen 2 Display Start Address application specific bits 15 8 of Screen 2 Display Start Address AUX 09h application specific Screen 2 Display Start Address points to D000 0000h bits 7 0 bits 15 8 of Screen 2 Display Start Address application specific see AUX 08h see Section 4 2 1 SDUI1352B0x Evaluation Board Display Memory on page 24 and Section 4 1 Registers on page 22 AUX OAh 1110 1111 bits 7 0 bits 7 0 of Screen 1 Display Line Count application specific bits 9 8 of Screen 1 Display Line Count in bits 1 0 of AUX OBh application specific Screen 1 Display Line Count is typically the same as Total Display Line Count AUX OAh
138. er of Horizontal Pixels 640 4 1 Grays I 6 frays 2 bits per pixel 4 bits per pixel Display Size Access Time Size Access Time Clock Memory KB sv KB 3V33V SV ee Interface OSC 8 bit 2 2 480 16 bit 75 115 ns 135 ns 150 1 1 24 MHz 76 Hz vo 8 bit 50 ns 70 ns 2 2 M0 623 150ns 170n 50 ns 70 ns MHZ DIE 5 8 bit 75 ns 95 ns 2 2 50 200ns 220ns 19 75 ns 95 ns TE gt 8 bit 115 ns 135 ns 2 2 29 280ns 300 80 115 135ns 12 MHz 70Hz Q 2 8 bit 115 ns 135 ns 2 2 240 AR 280 ns 300ns 7 115 ns 135 ns PME HS 2 8 bit 150 ns 170 ns 50 ns 70 ns 200 32 350ns 370ns 625 150ns 170ns 10 Miz DIM 1 Memory more than 128KB cannot be supported by SED1352 2 Memory more than 64KB can only be supported through 16 bit display memory interface KB K byte 1024 bytes SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 63 Vancouver Design Center Table 9 4 Memory Size Requirement Number of Horizontal Pixels 480 Number of Horizontal Pixels 480 4 Grays 16 Grays d Example 2 bits per pixel 4 bits per pixel Displa Access Time Access Time isp ay Size Size
139. ers An example resolution and desired frame rate will be selected and used to determine the remaining variables 1 1 Reference Material Refer to the SED1352 Hardware Functional Specification X16 SP 001 xx for complete AC timing details LCD Panel Options Memory Requirements SED1352 Issue Date 98 10 08 X16 AN 005 07 Page 6 Epson Research and Development Vancouver Design Center 2 CONFIGURATION EQUATIONS 2 1 Example LCD panel resolution 640x240 LCD panel configuration 4 bit Single drive panel LCD Gray Shades 4 Desired Frame rate 70Hz 2 1 1 Input Clock Requirement For a frame rate of 70Hz the input clock or pixel clock frequency can be calculated as following fosc input clock fosc Frame Rate of horizontal pixels 16 of vertical lines 4 Therefore fosc 70 640 16 240 4 fosc 11 2MHz Note 1 Due to oscillator frequency availability a 12MHz oscillator is selected thus producing a slightly higher frame rate 75Hz 2 For a detailed description of the frame rate formula see section 9 3 of the SED1352 Hardware Func tional Specification drawing office number X16 SP 001 xx 2 2 SRAM Size and Access Time Requirements 2 2 1 SRAM Size Manion Size of Horizontal pixels of Vertical pixels 8 4 of bits pixel i e 4 gray shades 2 bits pixel therefore 1 byte 8 bits 4 pixels Therefore Memory size bytes 640 240 4 Memory size bytes 37 5
140. es Data Sheet Application Notes and Programmer s Reference Software Utilities e User Utilities Evaluation Software Toobtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Issue Date 98 10 08 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www erd epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1352 Page iv Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date 98 10 08 Epson Research and Development Page v Vancouver Design Center TABLE OF CONTENTS INTRODUCTION SED1352 Graphics LCD Co
141. evelopment Vancouver Design Center 4 DISPLAY MEMORY MODELS This section introduces display memory models A concise description of the Display Start Address Registers is provided followed by a description of display memory Afterwards examples are provided illustrating how to calculate the display memory model for a given display resolution and gray level mode Once this model is calculated examples on programming the Display Start Address Registers are provided 4 1 Registers Register bits discussed in this section are highlighted AUX 01 Mode Register I O address 0001b Read Write Mask LCD Data Memory DISP Panel XSCL LCDE Gray Scale Width RAMS bit 1 Memory Interface This bit selects between the 8 bit or 16 bit memory interface When this bit 0 the 16 bit memory inter face is selected When this bit 1 the 8 bit memory interface is selected If 16 bit bus interface is selected VDO 1 on RESET the Memory Interface bit is forced to 0 internally 16 bit This bit goes low on RESET AUX 06 Screen 1 Display Start Address Register LSB I O address 0110b Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit
142. he DOS path on your hard drive Usage BIOS1352 COM is run from the DOS command line as follows bios1352 type x n y n g n p n m n Where type isthe panel type single for single panel or dual for dual panel is the horizontal panel size in pixels decimal is the vertical panel size in lines decimal is the number of gray shades 4 or 16 is the port address in hex 3001310 3601370 is the memory size in K bytes 64 or 128 produces a usage message gt B o a lt x The order and case of arguments is arbitrary Any invalid or missing argument will result in an error message Note that the port address must be the same as the physical address set on the SDU1352 evaluation board Example BIOS1352 SINGLE x 320 y 240 g 16 p 320 m 128 BIOS1352 COM Utility SED1352 Issue Date 98 10 08 X16 UI 003 08 Page 4 Epson Research and Development Vancouver Design Center Comments 51352 can be used in conjunction with a Monochrome Display Adapter mono card The standard DOS command MODE MONO will switch to the mono card and the DOS command MODE CO80 will switch to the LCD panel BIOS1352 emulates mode 3 but any program that attempts to write directly to video memory bypassing the video BIOS will not display correctly BIOSI1352 can be used in conjunction with a VGA BIOS In this case all TTY output will be displayed on the VGA monitor When the SED1352 video memory is specified as 64K bytes
143. he property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 1352SHOW EXE Display Utility X16 UI 001 08 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center 1352SHOW EXE DISPLAY UTILITY 1352SHOW is an OEM demonstration utility used to load and display GIF images It can also be used to demonstrate the split screen capabilities of the SED1352 by loading two images and vertically scrolling one image Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS Seiko Epson BIOS1352 version 1 11 or later DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Installation Copy the file 1352show exe to a directory that is in the DOS path on your hard drive Usage 1352SHOW is invoked from the DOS command line as follows 1352show imagel image2 i Where imagel is the first screen image to be displayed image2 is the second screen image to be displayed i will invert all displayed images show as negative produces the usage message Examples 1352show with no arguments will run the program in split screen mode This will display two predefined images with screen one displaying horizontal bars and screen two displaying vertical bars Screen two may be scrolled up and down using the arrow pag
144. hey are programmed into the 4 bit Look Up Table palettes positions pointed to by Palette Address bits 3 0 For example in a 16 level gray shade display mode a data value of 0001b 4 bits pixel will point to Look Up Table position one and display the 4 bit gray shade corresponding to the value programmed into that location 8 2 Look Up Table Architecture 8 2 1 4 Level Gray Shade Mode Look Up Table Bank 0 2 bit pixel data A 3 Bank 1 0 1 2 3 4 bit display data output Bank 2 0 1 2 3 3 0 1 2 3 Bank Select bits 1 0 Aux OEh bits 7 6 Note the above depiction is intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations Figure 27 4 Level Gray Shade Mode Look Up Table Architecture SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 55 Vancouver Design Center 8 2 2 16 Level Gray Shade Mode Look Up Table 16x4 WNK oO 4 bit pixel data 4 bit Look Up Table data outpu P3 P2 P1 PO msb Isb ugo Figure 26 16 Level Gray Shade Mode Look Up Table Architecture 8 3 Power Save Modes PSM 1 Two software controlled Power Save Modes have been incorporated
145. ic Diagram 1 7 16 Figure 2 SDU1352B0C Rev 1 0 Schematic Diagram 2 0f 7 17 Figure 3 SDU1352B0C Rev 1 0 Schematic Diagram 3 Of 7 18 Figure 4 SDU1352B0C Rev 1 0 Schematic Diagram 4 of 7 19 Figure 5 SDU1352B0C Rev 1 0 Schematic Diagram 5 of 7 20 Figure 6 SDU1352B0C Rev 1 0 Schematic Diagram 6 of 7 21 Figure 7 SDU1352B0C Rev 1 0 Schematic Diagram 70 7 22 SDU1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 7 Vancouver Design Center 1 SDU1352B0C REV 1 0 EVALUATION BOARD This manual reflects the use of SDU1352BO0C Rev 1 0 evaluation board in conjunction with the SED1352 LCD Controller All appropriate components are surface mount to reduce cost and minimize board space 1 1 Features 100 pin QFP5 package SMD technology for all appropriate devices Monochrome STN LCD support 8 bit and 16 bit ISA Bus support 5V operation e Two terminal crystal support up to 25 175MHz 16 bit wide 128K bytes SRAM support Configuration Options Support for S
146. ign Center In 8 bit memory interface if the Address Pitch Adjustment is not equal to zero then a virtual screen with a line length of Line Byte Count AUX 0Dh 1 bytes is created with the display reflecting the contents of a window Line Byte Count 1 bytes wide The position of the window on the virtual screen is determined by AUX 06h and 07h and AUX 08h and 09h In 16 bit memory interface if the Address Pitch Adjustment is not equal to zero then a virtual screen with a line length of 2 Line Byte Count AUX 0Dh 1 bytes is created with the display reflecting the con tents of a window 2 Line Byte Count 1 bytes wide The position of the window on the virtual screen is determined by AUX 06h and 07h and AUX 08h and 09h AUX 0Eh Look Up Table Address Register I O address 1110b Read Write Bank Bit 1 Bank ID Bit ID Bit ree e poss Bit 0 Read Only Read Only es Address Address Address i ead Only Big 3 Bit 2 Bit 1 Bit 0 The SED1352 has one internal 16 position 4 bit wide Look Up Table palette The 4 bit value programmed into each table position determines the output gray shade weighting of display data The Look Up Table can be arranged in two different configurations Refer to Table 27 4 Level Gray Shade Mode Look Up Table Architecture on page 54 for formats bits 7 6 bits 5 4 bits 3 0 Note Bank Bits 1 0 In 4 level gray mode 2 bits pixel
147. ing Symbol Parameter Min Typ Max Units tla period single panel mode HT 24 ns tlb LP period dual panel mode 2 HT 24 ns 2 YD hold from LP negated bit 5 0 8tosc 24 ns t2b YD hold from LP negated bit 5 1 13tosc 24 ns LP pulse width R1 bit 5 0 6tosc 24 ns t3b LP pulse width RI bit 1 24 ns t4 WF delay from LP falling edge 0 20 ns t5 LP setup to XSCL falling edge R1 bit 5 0 2tosc 24 ns hold from XSCL falling edge R1 bit 5 0 4tosc 24 ns t6b XSCL falling edge to LP falling edge single panel 15tosc 24 i8 mode R1 bit 5 1 only t c XSCL falling edge to LP falling edge dual panel mode 3ltosc 24 a bit 5 1 only LP negated to XSCL falling edge R1 bit 5 0 4tosc 24 ns t7b negated to XSCL falling edge bit 5 1 9tosc 24 ns 18 XSCL period 8tosc 24 ns 9 XSCL high width 4tosc 24 ns 00 XSCL low width 4tosc 24 ps t11 UD 3 0 LD 3 0 setup to XSCL falling edge 4tosc 24 ns t12 UD 3 0 LD 3 0 hold from XSCL falling edge 4tosc 24 ns t13a negated to XSCL rising edge bit 5 0 0 ns t13b LP negated to XSCL rising edge bit 5 1 5tosc 24 ns Where HT number of horizontal panel pixels 16 tosc where tosc Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 42 Epson Research and Development Vancouver Design Center LCD Interface Pixel Data Positi
148. ion All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Power Consumption X16 AN 006 06 Issue Date 98 10 08 Page 3 le panel le panel le panel ing ing 25MHz Pixel Clock 12MHz Pixel Clock 6MHz Pixel Clock ing SS RSQ RSQ RSQ RS 00h and on 640x480 s 00h and AAh on 480x320 s 00h and AAh on 320x240 s ESS SSSSSSSSSS SED1352 Power Consumption Vpp 5 0V screen pattern screen pattern screen pattern 25MHz 6MHz Pixel clock 12MHz No display connected Pixel clock Pixel clock 2 3 4 100 80 1 1 SED1352 POWER CONSUMPTION Epson Research and Development Vancouver Design Center 1 1 Conditions 40 20 Mul SED1352 X16 AN 006 06 PD2 Units mW mW mW PD2 0 1 0 1 0 0 PD1 14 3 4 7 11 8 PD1 Active Pattern AAh 105 5 66 1 36 1 Operating Mode Active 93 0 58 7 32 7 Pattern 00h ACTIVE Pattern AAh 25MHz 12MHz 6MHz ACTIVE Pattern 00h 98 10 08 Power Consumption Issue Date Vancouver Design Center Epson Research and Development Page 4 SED1352 Power Consumption Vpp 3 0
149. ion is called the viewport the user moves this viewport over different portions of the image by panning and scrolling Panning moves the viewport right or left Scrolling moves the viewport up or down 5 5 1 To pan and scroll over a large image the SED 1352 registers must first be initialized and the image written to display memory To do so initialize the registers as described in Section 2 INITIALIZING THE SED1352 on page 8 but with the following exception the Address Pitch Adjustment Register in the SED1352 must be set to create a virtual display see Section 5 1 Virtual Displays on page 28 for more information Initialization 5 5 2 Panning Right and Left To pan to the right increase the value in the Screen 1 Display Start Address Register To pan to the left decrease the value in the Screen 1 Display Start Address Register Note that the SED1352 can pan right or left by either 2 4 or 8 pixels This is because the Screen 1 Display Start Address Register refers to either bytes or words see Section 4 2 1 SDU1352BO0x Evaluation Board Display Memory on page 24 and a byte can represent either 2 or 4 pixels and so a word can represent 4 or 8 pixels see Table 5 1 below Table 5 1 Smallest Number of Pixels for Panning Memory Smallest Number of Pixels Gray Levels Pixels per Byte Interface for Panning 4 4 4 8 bits 16 2 2 4 4 8 16 bits 16 2 4 5 5 3 Scrolling Up a
150. ion settings VD15 VD13 MEMCS and address lines AB19 17 the Memory Decoder validates a given memory cycle 3 3 8 Data Bus Conversion According to configuration setting VDO the Data Bus Conversion maps the external data bus either 8 bit or 16 bit into the internal odd and even data bus 3 3 9 Address Generator The Address Generator generates display refresh addresses used to access display memory 3 3 10 CPU CRT Selector The CPU CRT Selector accesses the display memory from the CPU or the display refresh circuitry 3 3 11 Display Data Formatter The Display Data Formatter reads the display data from the display memory and outputs the correct format for all supported LCD panel types and gray scale selections 3 3 12 Clock Inputs Timing Clock Inputs Timing generates the internal master clock according to the gray level selected and display memory interface The master clock MCLK can be MCLK input clock MCLK 1 2 input clock MCLK 1 4 input clock Refer to section 9 2 SRAM Access Time for further details Pixel clock input clock 3 3 13 SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display memory SRAM SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Page 17 Epson Research and Development Vancouver Design Center 4 PINOUT DIAGRAM XSCL LCDENB VOE IOCS IOW IOR MEMCS MEMW MEMR READY BHE SED1352F
151. ip select output to the second odd byte address SRAM VCSO 68 65 Active low chip select output to the first or even byte address SRAM Active low output used for writing data to the display memory This pin is WEP 57 93 connected to the WE input of the SRAMs Active low output to enable reading of data from the display memory This pin is VOS 9 50 connected to the OE input of the SRAMs LCD Interface FPDI 1 F1B Pin Pin Nam T FOB Pin Description ame 5in Name FOB Pin 4 Descriptio Upper panel display data for dual panel mode For single panel mode these bits are the most significant 4 bits of the 8 bits output UD3 UD0 19 67 70 data to the panel PD 4 7 For 4 bit single panel mode these bits are the 4 bits of output data to the panel Lower panel display data for dual panel mode For 8 bit single panel mode these bits are the least significant 4 bits of the 8 bits output Per 10 oon data to the panel PD 0 3 For 4 bit single panels these bits are driven 0 low state XSCL FPSHIFT 0 81 78 Display data shift clock Data is shifted into the LCD X drivers on the falling edge of this signal Display data latch clock The falling edge of this signal is used to LP FPLINE O 79 76 latch a row of display data in the LCD X drivers and to turn on the row driver Y driver WF MOD 80 77 LCD backplane BIAS signal This output toggles once every n LP periods as programmed in AUX 5
152. it Memory Configuration Example Figure 2 16 Bit Memory Configuration Example Table of Contents INTRODUCTION 4 9 RIS 1 1 Reference Material CONFIGURATION EQUATIONS 21 Example 2 1 1 Input Clock Requirement 2 2 SRAM Size and Access Time Requirements 2 2 A SRAMESIZE dtt s ase woe esse ehe D E EUM S 2 2 2 SRAM Access IMPLEMENTATION 31 8 Bit Display Memory Interface 3 1 1 Configuration 3 1 2 Register Settings c3 olo goo n y Rede p RR S vmi 8 3 2 16 bit Display Memory Interface 3 2 1 Configuration options 322 Register Settings 2252 9552 UR ee FERIA AVES List of Figures LCD Panel Options Memory Requirements Issue Date 98 10 08 Page 3 SED1352 X16 AN 005 07 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08 Epson Research and Development Page 5 Vancouver Design Center 1 INTRODUCTION The SED1352 is a highly configurable general purpose LCD controller The LCD panel frame rate resolution and gray shades all determine the memory and input clock requirements This application note will describe the equations used to determine the various paramet
153. ity must now be provided externally and these two pins need to disconnected as there may be conflict problems associated with two different outputs driving the same input 1 3 3 SRAM Support The 00 1352 0 board supports 16 bit wide 64K byte 128K byte SRAM only DIP switch SW1 8 selects between the two options 1 3 4 Monochrome LCD Support The SED 1352 supports 4 and 8 bit Dual and Single monochrome STN LCD panels the necessary signals are provided on the 40 pin ribbon cable header The interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems Refer to Table 1 4 LCD Signal Connector J1 Pinout on page 9 for specific settings 1 3 5 Power Save Modes The SED 1352 supports 2 software Power Save Modes The utility program 1352PD EXE is supplied to control the software modes The software modes are controlled by directly writing the SED1352 associated internal registers 1 3 6 Adjustable LCD Panel Negative Power Supply The majority of Monochrome LCD panels require a negative power supply to provide between 18 V and 23 V ou 45mA For ease of implementation such a power supply has been provided as an integral part of this design The signal VLCD can be adjusted by R11 100K potentiometer to provide an output voltage from 14 V to 23 V and is enabled disabled by the control signal LCDENB Note LCDENB is directly controlled by register AUX 01 bit 4 of the SED1352
154. lay Active Yes No No No Access Possible Yes Yes Yes Yes Memory Access Possible Yes Yes No No Sequence Controller Running Yes No No No Internal Oscillator Disabled No No No Yes Note 1 When programming the PS bits do a read modify write operation so as not to destroy any other data in the register 2 Refer to the programming example in Advanced Functions on page 52 Programming Notes and Examples Issue Date 98 10 08 Page 45 SED1352 X16 BG 007 04 Page 46 Epson Research and Development Vancouver Design Center 6 PROGRAMMING THE SED1352 The purpose of this section is to show how to program the SED 1352 exercising the specific capabilities of this chip A series of functions written in will be presented each illustrating a basic feature of the SED1352 These functions are written for the SDU1352BO0x evaluation board and are combined under a menu driven program called DEMO EXE Note The sample code will not run on a display larger than 320x240 and will use 16 gray shades in most of the examples This program accepts the following command line options DEMO type x n y n p n where type SINGLE DUAL X horizontal panel size in pixels from 1 to 320 decimal y vertical panel size in pixels from 1 to 240 decimal 3001310 360 370 port address in hex I O indexed addressing selected by default For example if there is a 320x240 single panel LCD with a port address of 310h type DEMO S
155. lity See the BIOS1352 COM Utility manual X16 UI 003 xx for de tails 2 This board is pre set to use indexing I O with address 000 0011 0 000x where x is don t care and can be configured through dip switch SW1 7 to SW1 5 The factory setting of 222 001 i e I O address 0310h and 0311h 3 In indexing I O only two I O address spaces are needed For example if I O address 310h is used 310h will be the index register and 311h will be the data register Example I O write 310h 01 set index 1 I O read 311h read contents of AUX O01nh I O write 310h 05 set index 5 I O write 311h 07 write 07 to AUX 05h SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Page 13 Vancouver Design Center 1 3 2 Non ISA Bus Support This evaluation board was specifically designed to support the standard 8 16 bit ISA bus However as the SED1352 does support other bus interfaces header strips have been provided containing all necessary I O pins see section 1 3 9 on page 14 When using the header strips to provide the bus interface observe the following 1 All T O signals on the ISA bus card edge must be isolated from the ISA Bus do not plug the card into a computer Voltage lines are provided on the header strips 2 02 TIBPAL22V 10 is currently used to provide the SED1352 IOCS pin 23 and MEMCS pin 22 input signals for ISA bus use This functional
156. ll point to Look Up Table positions one and display the 4 bit gray shade that was previously programmed into that location bits 7 6 Bank Bits 1 0 In 4 level gray mode 2 bits pixel the 16 position palette is arranged into four 4 position banks These two bits control which bank is currently selected These bits have no effect in 16 level gray mode 4 bits pixel bits 3 0 Palette Address Bits 3 0 These 4 bits provide a pointer into the 16 position Look Up Table currently selected for CPU R W access Note The Look Up Table configuration e g 1 2 4 banks does not affect the R W access from the CPU as all 16 positions can be accessed sequentially AUX 0F Look Up Table Data Register I O address 1111b Read Write Palette Data Bit 1 Palette Data Bit 2 Palette Data Bit 3 Palette Data Bit 0 n a n a n a n a bits 3 0 Palette Data Bits 3 0 These 4 bits are the gray shade values used for display data output They are programmed into the 4 bit Look Up Table palettes positions pointed to by Palette Address bits 3 0 For example in a 16 level gray shade display mode a data value of 0001b 4 bits pixel will point to Look Up Table position one and display the 4 bit gray shade corresponding to the value programmed into that location SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 17 Vancouver Design Cen
157. low demonstrates both crystal interface and an oscillator interface to SED1352 Crystal Interface Oscillator Interface 92 92 OUT Vec Ci xi R uS SED1352 SED1352 enn NC 93 4 2 93 ACE Figure 19 Recommended Clock Interface Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Epson Research and Development Page 37 Vancouver Design Center 7 3 Display Memory Interface Timing 7 3 1 Write Data to Display Memory VA 15 0 VSCO VSC1 oe x H gt VWEst t2 3 t4 VOE 79 VD 15 0 dg INPUT Hz OUTPUT Hiz INPUT Hiz Figure 20 Write Data to Display Memory Table 7 10 Write Data to Display Memory 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units MCLK Address cycle time MCLK 10 10 ns 15 0 VCSO VCS1 valid before MCLK7 MCLK 2 VWE falling edge 20 10 VA 15 0 VCSO and VCS1 hold from t3 on 0 0 ns VWEH rising edge MCLK 2 t4 Pulse width of VWE MCLK 2 5 5 ns MCLK 2 MCLK 2 t5 VD 15 0 setup to VWE rising edge ns 20 20 t6 VD 15 0 hold from VWE rising edge 0 0 ns Where MCLK period or 2 fosc or 4 fosc depending on which mode the chip is in see section 9 2 and 9 3 Hardware Functional Specification Issue Date 99 07 28 SED1352 X16
158. low on RESET SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Page 49 Vancouver Design Center bit 5 bit 4 bit 0 Table 8 3 Power Save Mode Selection PS1 PSO Mode Activated 0 0 Normal Operation 0 1 Power Save Mode 1 1 0 Power Save Mode 2 1 1 Reserved Refer to Power Save Modes PSM 1 on page 55 for a complete Power Save Mode description LCD Signal State When this bit 0 all LCD interface signals are forced low during Power Save modes When this bit 1 all LCD interface signals are forced to a high impedance Hi Z state during Power Save modes This bit goes low on RESET LUT Bypass When the LUT Bypass bit 0 the Look Up Table is used for display data output When this bit 1 the Look Up Table is bypassed for display data output for power save purposes The LUT Bypass bit goes low on RESET Line Byte Count Bit 8 This is the MSB of the number of bytes to be fetched per display line minus 1 see AUX 02h This bit only has effect when in 16 gray shades with 8 bit memory interface This bit is ignored in the 16 bit mem ory interface AUX 04h Total Display Line Count Register LSB Vertical Total I O address 0100b Read Write Total Total Total Total Total Total Total Total Display Display Display Display Display Display Display Display Line Count Line Count Line C
159. low power consumption panel power control switch see AUX OIh bit 4 Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 12 Epson Research and Development Vancouver Design Center 3 TYPICAL SYSTEM BLOCK DIAGRAMS The following figures show typical system implementations of the SED1352 All of the following block diagrams are shown without SRAM or LCD display Refer to interface specific Application Notes for complete details X16 AN xxx xx 3 1 16 Bit MC68000 MPU M C68000 SED1352 P D Decoder gt MEMCS 16 14 4 Decoder O gt IOCS A10 to A19 Al to A19 gt AB to ABI9 to D15 4 gt DBOtoDBI5 DTACK 4 READY UDS gt ABO LDS BHE AS gt IOR R W IOW Figure 1 16 Bit 68000 Series example implementation only actual may vary SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 13 Vancouver Design Center 3 1 1 MPU with READY or WAIT signal Z80 pL 71 SED1352 MREQ V MEMCS A10 to A15 gt Decoder O 10 5 IORQ x AO to A15 gt
160. ly supports the 16 bit and 8 bit ISA Bus with indexing I O via a standard AT edge connector External logic has been added to provide signals which the SED 1352 does not support directly See Application Note X16 AN 003 xx Note 1 This board has been designed to operate in conjunction with either a VGA card or monochrome card or as a stand alone card If using the SDU1352BO0C in conjunction with VGA display adapter the following limitations apply a Only 64K bytes of memory is available residing at the D000h segment b Given the memory limitation certain panel size and gray shade capabilities are reduced c The VGA card video BIOS must be 8 bit only The SDU1352B0C must be configured as follows SW1 1 open 8 bit operation necessary to prevent MEMCS16 conflict when reading VGA BIOS SW1 2 to 7 set as desired SW1 8 closed 64K bytes available at DOOOh segment JP1 2 3 shorted to reflect SW1 8 polarity If using SDU1352BO0C in conjunction with a monochrome display adapter all 128K bytes of memory is available residing at segment 000 DOOOh The SDU1352B0C can be used as a stand alone video adapter with 128K bytes memory available If used as a stand alone video adapter the BIOS setup program for the computer must support and have No Video selected as the vid eo adapter The BIOS1352 COM utility program can be used with the evaluation board to simulate a standard video BIOS thus providing text and cursor functiona
161. m ne ale 88 Hz 30 5 Figure 6 SDU1352B0C Rev 1 0 Schematic Diagram 6 of 7 SDUI1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 22 Epson Research and Development Vancouver Design Center 25 175Mhz BYPASSCAPACITORS 1 POWERPIN 4 C ZA cis AS cu 05 2 g F Figure 7 SDU1352B0C Rev 1 0 Schematic Diagram 7 of 7 SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 EPSON SED1352 Dot Matrix Graphics LCD Controller Power Consumption Document Number X16 AN 006 06 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporat
162. matter Timing Generator Power Save SRAM Interface Oscillator lt lt lt lt lt 9 e 9 tr y eu aye N lt 2 Q 16 001 06 6 001 06 EH GRAPHICS Ml EPSON 01352 FUNCTIONAL BLOCK DESCRIPTIONS Bus Signal Translation According to configuration setting VD2 Bus Signal Trans lation translates MC68000 type CPU signals or READY type MPU signals to internal bus interface signals Control Registers The fifteen internal Control and Configuration Registers are accessed by direct mapping or by using the built in internal index register Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings LCD Panel Interface The LCD Interface performs frame rate modulation for passive monochrome LCD panels Look Up Table The Look Up Table contains sixteen 4 bit wide palettes that can be configured as one 16x4 palette or four 4x4 palettes used for the re mapping of gray scale outputs Port Decoder According to configuration settings VD1 VD12 VD4 IOCS and address lines AB9 1 the Port Decoder validates a given I O cycle Memory Decoder According to configuration settings VD15 VD13 MEMCS and address lines AB19 17 the Memory Decoder validates a given memory cycle Data Bus Conversion According to configuration setting VDO the Data Bu
163. ment Vancouver Design Center 3 8 ISA BUS INTERFACE For the purpose of the example shown below the following conditions are set by default 1 Indexing I O with partial decoding i e address lines A10 to A15 are not decoded for I O cycles Note Partial decoding is quite safe on most ISA Bus systems as I O addresses above 03FFh are rarely used 2 addresses are xxxxxx1100000000b and xxxxxx1100000001b 3 64Kbytes of display memory occupying A segment Note The 74LS00 is simply used to detect the B segment and invalidate the MEMCS input Note This memory configuration will conflict with a VGA card installed on the same bus therefore either a serial terminal or monochrome display adapter is recommended as the primary console This section provides the necessary settings to complete the interface between the SED1352FO0B and the 8 bit ISA Bus Since I O addresses are partially decoded there is no need to use a PAL for decoding 8 Bit ISA Bus SED1352F0B AEN gt IOCS REFRESH 1 BHE 4 3 MEMCS 10kQ saie D VD11 13 74LS00 5 0 19 gt ABO 19 VD15 00 7 gt DBO 7 SMEMW gt MEMW SMEMR gt MEMR IOW gt IOW IOR gt IOR IOCHRDY lt READY Figure 9 8 Bit ISA Bus Implementation SED1352F0B ISA Bus Interface Considerations X16 AN 003 05 Issue Date 98 10 08 Epson Research and Development Page 9 Vancouver Design Center 1
164. mp 10 2 As the SED1352 is capable of 16 bit IO access the IOCS 16 bus signal must be driven externally to indicate such a cycle As stated in the ISA specification the IOCS 1 6 is a straight address decode without qualification IOCS 16EN amp A9 6 8 amp A7 amp A6 amp A5 amp A4 amp amp A2 amp A1 3 With 128Kbytes of display memory and A17 to A19 decoded internally to SED1352FOB MEMCS REFRESH 1 3 Additional Discrete Logic Description 1 As shown in Figure 1 the 74LS688 is configured as a memory decoder with valid addresses between OCxxxxh and ODxxxxh 2 741 509 is used simply to provide the Open Collector outputs necessary for the IOCS16 and MEMCS 16 sig nals 1 4 SED1352F0B Default Setup 1 4 1 Configuration Options 1 VD15 VD13 110 memory decoding for locations C and D segments 2 VDI12 VD4 110001000 T O decoding for locations 1100010000b 1100010001b 3 VD3 0 no byte swap of high and low bytes 4 VD2 0 ISA Bus interface 1 non MC68K interface 5 VD1 0 indexing I O 6 VDO 1 16 bit bus interface Where pull up with a 10K resistor 0 no pull up resistor Note The states of these data pins are internally latched during RESET 1 4 2 Register Setting AUX 1 bit 1 0 for 16 bit memory interface must be 16 bit with a 16 bit bus ISA Bus Interface Considerations SED1352F0B Issue Date 98 10 08 X16 AN 003 05 Page 8 Epson Research and Develop
165. mum 25MHz input clock or pixel clock 2 terminal crystal input for internal oscillator or direct connection to external clock source maximum 16MHz 16 bit MC68000 MPU interface e 8 bit or 16 bit MPU Bus interface with memory accesses controlled by a READY or WAIT signal option to use built in index register or direct mapping to access one of fifteen internal registers e 8 bitor 16 bit SRAM data bus interface configurations display memory configurations 128K bytes using one 64Kx16 SRAM 128K bytes using two 64Kx8 SRAMs 64K bytes using two 32Kx8 SRAMs bytes using one 8Kx8 and 32Kx8 SRAM 32K bytes using one 32Kx8 SRAM bytes using two 8Kx8 SRAMs 8K bytes using one 8Kx8 SRAM 2 3 Display Modes 2 4 bits per pixel 4 16 level gray shade display modes 16x4 Look Up Table provided for gray shade display modes maximum 16 shades of gray split screen display mode see AUX OAh virtual display mode see AUX ODh SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 11 Vancouver Design Center 2 4 Display Support example resolutions 640x480 with 4 grays e 640x400 with 16 grays e passive monochrome LCD panels e 4 bit single 4 bit data transfer e 8 bit single 8 bit data transfer e 8 bit dual 4 bit data transfer for each half panel 2 5 Power Management two software power save modes
166. n lines vertical size of image 1 vertical size of panel 1 displ idth in pixel ne 640 size PAV ey number of scan lines in image 1 x 240 38400 bytes 9600h bytes pixels per byte 4 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 41 Vancouver Design Center 6 Determine the display memory location for image 2 Place image 2 immediately after image see Figure 14 Assign the starting address for image 2 as follows image 2 address base display memory address size of image 1 C000 0000h 0000 9600h C000 9600h 7 Program the Screen 2 Display Start Address Register to point to the beginning of image 2 Image 2 is placed right after image 1 as shown below 3 ize of i 1 in byt Screen 2 Display Start Address Register Screen 1 Display Start Address Register aca a eae 2 bytes per word 0000h oo 4B00h AUX 08h 00h AUX 09h 4Bh 8 Write both image 1 and image 2 to their respective locations in display memory Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 42 Epson Research and Development Vancouver Design Center 5 5 Panning and Scrolling Panning and scrolling are typically used to show an image which is too large to be shown completely on an LCD panel Although the image is stored entirely in display memory only a small portion is actually visible on the LCD panel This visible port
167. nd Down To scroll up increase the value in the Screen Display Start Address Register by the number of bytes in one virtual scan line To scroll down decrease the value in the Screen 1 Display Start Address Register by the number of bytes in one virtual scan line A virtual scan line is in reference to a virtual display in which an image larger than the physical size of the LCD is stored The number of bytes in a virtual scan line is the number of bytes required to store one horizontal line of pixels in the virtual image Example 14 Scroll down one line for a 16 gray shade 640x200 virtual image using a 320x240 single panel LCD The Memory Interface is 16 bits and 64k of display memory is available Also describe how to scroll in a dual panel LCD 1 Calculate the number of bytes in a virtual scan line _ 640 pixels scan line _ petbye gt 320 bytes scan line number of horizontal pixels in virtual image number of pixels per word SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 43 Vancouver Design Center 2 Add the number of words in a virtual scan line to the Screen 1 Display Start Address Register In this example the Screen 1 Display Start Address points to the beginning of the image Screen 1 Display Start Address Screen 1 Display Start Address bytes 1 a yirt alscan line 2 bytes per word 8000h 80A0h 3 Program th
168. ne Count Register LSB I O address 1010b Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display Display Display Display Display Display Display Line Count Line Count Line Count Line Count Line Count Line Count Line Count Line Count Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX 0Bh Screen 1 Display Line Count Register MSB I O address 1011b Read Write Screen 1 Screen 1 Display Display ne uo ue me ne ne Line Count Line Count Bit 9 Bit 8 AUX 0Ah bits 7 OScreen 1 Display Line Count Bits 9 0 AUXTOBh bits 1 0 These bits are the eight LSB of a 10 bit value used to determine the number of lines displayed for screen 1 The remaining lines will automatically display from the Screen 2 Display Start Address The 10 bit value programmed is the number of display lines 1 This register is used to enable the split screen display feature single panel only where two different images can be displayed at the same time on one display For example AUX OAh 20h for a 320x240 display system The display will display 20h 1 33 lines on the upper part of the screen as dictated by the Screen 1 Display Start Address Registers AUX 06h and AUX 07h and 240 33 207 lines will be displayed on the lower part of the screen as dictated by the Screen 2 Display Start Address Registers AUX 08h and AUX 09h Two different images can be displayed when using a du
169. ng Ltd 22178 Hino Lino shi San Jose CA 95134 USA 10F No 287 Tokyo 191 8501 Japan Tel 408 922 0200 Nanking East Road 408 922 0238 Sec 3 Taipei Taiwan R O C UE SUI http www eea epson com Tel 02 2717 7360 http www epson co jp Fax 02 2712 9164 Hong Kong Europe Singapore Epson Hong Kong Ltd Epson Europe Electronics GmbH Epson Singapore Pte Ltd 20 F Harbour Centre Riesstrasse 15 No 1 25 Harbour Road 80992 Munich Germany Temasek Avenue 36 00 Wanchai Hong Kong Tel 089 14005 0 Millenia Tower Tel 2585 4600 Fax 089 14005 110 Singapore 039192 Fax 2827 4346 Tel 337 7911 Fax 334 2716 Copyright 1997 1998 Epson Research and Development Inc All rights reserved VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Ep son EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation 24 X16B C 001 06 EPSON SED1352 Dot Matrix Graphics LCD Controller Hardware Functional Specification Document Number X16 SP 001 16 Co
170. ngs to complete the interface between the SED1352FO0B and the 16 bit ISA Bus Note A PAL was used instead of discrete logic to reduce external component count 16 Bit ISA Bus SED1352F0B AEN p gt gt IOCS Vcc REFRESH PAL MEME SA1 15 10kQ VD0 VD7 VD11 12 SA0 19 gt AB0 19 VD14 15 SBHE gt BHE 00 15 gt DBO 15 SMEMW gt MEMW SMEMR gt MEMR IOW gt IOW IOR IOR IOCHRDY 4 READY 1 06164 4 Jo gt 10 516 LA17 23 4 MEMCS16 sr a E LA23 17 p0 6 Q 741509 0000110 40 6 G 74LS688 Figure 8 16 Bit ISA Bus Implementation SED1352F0B ISA Bus Interface Considerations X16 AN 003 05 Issue Date 98 10 08 Epson Research and Development Page 7 Vancouver Design Center 1 2 PAL Equations The PAL is programmed with the following equations 1 As stated above the default I O address is from 0310h to 0311h The SED1352FOB provides internal decoding of ad dress bits AO to 9 therefore minimal external circuitry is necessary to provide signals IOCS and IOCS 16 IOCS is required by the SED 1352 to indicate a valid IO cycle In an ISA bus environment valid IO decoding must include addresses 15 0 Given this example addresses A10 15 must all be 0 AEN must also be 0 IOCS amp A15 amp A14 amp A13 amp A12 amp A11 a
171. nt may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 BIOS1352 COM Utility X16 UI 003 08 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center BIOS1352 COM UTILITY BIOS1352 is a DOS Terminate and Stay Resident TSR program which replaces and or supplements the PC video interrupt INT 10h This program provides text scroll and cursor functionality when no VGA BIOS is present Although the SED1352 is not a VGA or EGA compatible controller this program is supplied to give the user a familiar prompt Within limits BIOS1352 simulates a VGA BIOS and will allow standard output functions to work DOS programs such as Edlin Format Debug and internal commands such as Copy Ren Mkdir etc should work however complex programs such as Edit Qbasic and Scandisk will not work The standard output functions are handled by the VGA BIOS if present Program Requirements Video Controller SED1352 Display Type Up to 640x480 LCD BIOS None or any VGA DOS Program Yes DOS Version 3 0 or greater Windows Program No Windows DOS Box Yes Windows DOS Full Screen Yes OS 2 DOS Full Screen Yes Installation Copy the file bios1352 com to a directory that is in t
172. ntroller Data Sheet SPECIFICATION SED1352 Hardware Functional Specification PROGRAMMER S REFERENCE SED1352 Programming Notes and Examples UTILITIES 1352SHOW EXE Display Utility VIRTUAL EXE Display Utility BIOS1352 COM Utility 1352GRAY EXE Display Utility 1352PD EXE Power Down Utility 1352READ EXE Diagnostic Utility EVALUATION SDU1352B0C Rev 1 0 Evaluation Board User Manual APPLICATION NOTES Power Consumption ISA Bus Interface Considerations MC68340 Interface Considerations LCD Panel Options Memory Requirements Issue Date 98 10 08 SED1352 Page vi Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Issue Date 98 10 08 EPSON GRAPHICS October 1998 SED1352 GRAPHICS LCD CONTROLLER DESCRIPTION The SED1352 is a graphics display LCD controller capable of displaying a maximum of 16 levels of gray on single and dual scan Liquid Crystal Displays A 16x4 lookup table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel The SED 1352 can interface to the MC68000 microprocessor and 8 16 bit MPUs with READY WAIT signal with minimum external glue logic This chip can directly control up to 128 Kbytes of static SRAM Optimized for cost and power savings the SED1352 can operate from 2 7 volts to 5 5 volts and up to 25MHz FEATURES 16 bit 16 MHz MC68000 MPU interface display memory interface 8 16 bit MPU interface controll
173. oftware Power Save Modes On board adjustable LCD BIAS negative power supply On board adjustable LCD BIAS positive power supply CPU Bus Interface Header strips SDU1352B0C Rev 1 0 Evaluation Board User Manual SED1352 Issue Date 98 10 07 X16 AN 002 09 Page 8 Epson Research and Development Vancouver Design Center 1 2 Installation and Configuration The SED1352 has 16 configuration inputs VD 15 0 which are read on power up For the purpose of this design most of these configuration inputs have been factory set and therefore are not configurable A four position DIP switch block is provided for the selection of 8 or 16 bit bus interface and setting I O address bits 4 through 6 Table 1 1 Configuration DIP Switch Settings Switch Signal Closed Open 1 1 VDO 16 bit ISA Bus interface 8 bit ISA Bus interface SWI 2 VDI Direct mapping I O Indexing I O SWI 3 VD2 M68K CPU Interface ISA Bus other MPU other SWI 4 VD3 Byte swap high and low data bytes No byte swap SWI 5 7 mapping address bit 4 SWI 6 VD8 mapping address bit 5 See Table 1 2 I O Mapping Example SWI 7 9 mapping address bit 6 SWI 8 64K bytes of SRAM available at segment 128K bytes of SRAM available at segment C000h D000h D000h Note The polarity of the Configuration Dip Switches is Closed 1 or high Open 0 or low Factory set fixed options on this board are 16
174. on UD3UD2UDI uo UD3JUD2 uD LD2LDI 1 0 Dual Panel Top LBS 8 bit Single Panel Dual Panel Bottom ups up2 up1 000 4 bit Single Panel Figure 23 LCD Interface Pixel Data Position SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 43 Vancouver Design Center LP 240 PULSES LP 4 PULSES b i YD TENDS ee WF X X UD 3 0 LINE 1 LINE 2 LINE 3 LINE 4 LINE 239 LINE 240 LINE 1 LINE 2 LP WF 4 XSCL 80 CLOCK PERIODS gt XSCL RA UD3 EDGE X X an X UD2 12 SE MER Jem X UD1 p 13 X 17 X Y X x UD0 A 14 X 13 re Y 1 320 X Example Timing for a 320x240 single panel Figure 24 4 Bit Single Monochrome Panel Timing Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 44 Epson Research and Development Vancouver Design Center lt LP 480 PULSES LP 4 PULSES YD wl
175. on Research and Development 2 INITIALIZING THE SED1352 This section presents two examples to show how to initialize the SED1352 registers and write a pixel to the display Code to initialize the SED1352 is provided in Section 6 2 Initialization Code on page 48 The following examples describe values written to registers e normal value is one which must not change after initialization of all registers Vancouver Design Center panel specific value is one required for the given type of panel Such a value must never change after initializa tion of all registers An implementation specific value is one required for the hardware implementation of the SED1352 Such a value must never change after initialization of all registers Refer to the ED1352F0x Hardware Functional Specification and SDU1352B0x Evaluation Board User s Manual for more information on hardware implementation issues application specific value is one that can be changed by the program after initialization of all registers Example 1 Program SED1352 Registers 00h ODh Initialize the registers for a 16 gray shade 320x240 single panel LCD with 64k of display memory Afterwards write one pixel to the top left corner of the display AUX Register Data in Binary Notes See Also AUX 00h 0000 0000 must be zero AUX 01h 1000 1000 b7 display on normal b single panel panel specific
176. osc depending on which mode the chip is in see section 9 2 and 9 3 SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Page 31 Vancouver Design Center MEMR Timing AB 19 1 MEMCS X YALI X AS UDS LDS INVALID R W DTACK Hi Z lt P t5 t6 DB 15 0 Hi Z VALID HZ k t7 Figure 13 MEMR Timing 68000 Table 7 4 MEMR Timing 68000 3V 3 3V 5V Symbol Parameter Min Typ Max Min Typ Max Units tl AB 19 1 and MEMCS valid before AS falling edge 0 0 ns 2 AB 19 1 and MEMCS hold from AS rising edge 0 0 ns 3 5 3 35 t3 AS falling edge to DTACK falling edge MCLK MCLK ns 20 10 t4 AS rising edge to DTACK hi z delay 42 20 ns t5 DTACK falling edge to DB 15 0 valid 20 20 ns t6 DB 15 0 hold from AS rising edge 54 28 ns 7 AS rising edge to DB 15 0 hi z delay 60 30 ns Where MCLK period 1 or 2 fosc or 4 fosc depending on which mode the chip is in see section 9 2 and 9 3 Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 32 Epson Research and Development Vancouver Design Center 7 1 2 68000 MPU Bus With READY WAIT Signal
177. ount Line Count Line Count Count Line Count Line Count Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 bits 7 0 Total Display Line Count Bits 7 0 These are the 8 LSB of the 10 bit Total Display Line Count and represent the number of scan lines 1 to a maximum value of 3FFh or 1024 scan lines In single panel mode TotalDisplayLineCount NumberOfDisplayLines 1 In dual panel mode TotalDisplayLineCount Note Note that the value programmed partially determines the frame period and hence af fects display duty cycle Bits 8 and 9 are located in the following register AUX 05h Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 50 Epson Research and Development Vancouver Design Center AUX 05h Total Display Line Count Register MSB and WF Count Register I O address 0101b Read Write Total Total WE Count WE Count WE Count WE Count WE Count WE Count Display Display Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Line Count Line Count Bit 9 Bit 8 bits 7 2 WF Count Bits 5 0 These bits are used to adjust the WF output signal period The binary value stored in these bits represents the number of LP pulses 1 between toggles of the WF output The power up reset value of these bits is 0 which causes the WF output to toggle every frame When values of 01h to 3Fh are programmed into these bits the results are WF toggling every 1 LP pulses where i
178. owRegisters 4 DESCRIPTION Shows the contents of the SED1352 registers INPUTS None RETURN VALUE None void ShowRegisters void static unsigned char x printf SED1352 Registers for x 0 x lt 16 x printf 02 ReadRegister x printf nSED1352 Look Up Table for x 0 x lt 16 WriteRegister 0x0e x printf 02X ReadRegister 0x0f ShowMenu FUNCTION GrayShadeBars DESCRIPTION Displays one set of vertical bars each with a different gray shade INPUTS None RETURN VALUE None I void GrayShadeBars void static unsigned int val x static unsigned char _far pVideo SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 53 Vancouver Design Center Initialize ClearLCDScreen For 64k only FP SEG pVideo 0xd000 FP OFF pVideo 0x0000 Update Look Up Table for 16 gray shades for x 0 x 16 x WriteRegister 0x0e x WriteRegister 0x0f x Change Mode Register for 16 gray shades val ReadRegister 1 val 0x08 WriteRegister 1 val Update Line Byte Count register for 16 gray shades Since 16 gray shades corresponds to 2 pixels per byte ther
179. p Max Units Vpp Supply Voltage 0 2 7 3 0 3 3 5 0 5 5 VIN Input Voltage Vss VDD V fosc 6 MHz log Operating Current l anys 3 0 3 5 7 0 mA Topr Operating Temperature 40 25 85 o fosc 6 MHz 9 0 11 55 Pryp Typical Active Power Consumption 16 grays 35 0 mW Input Specifications Symbol Parameter Condition Min Typ Max Units Low Level Input Voltage Vpp 3 0V 0 6 27 0 5 Vpp 5 5 2 0 Vin High Level Input Voltage Vpp 3 6V 2 5 V Vpp 33V 2 3 VDD 5 0 2 4 Vr Positive going Threshold Vpp 3 3 2 4 V Vpp 5 0 0 6 Negative going Threshold Vpp 3 3 0 6 V 3 0 0 5 5 0 0 1 Hysteresis Voltage Vpp 3 3 0 1 V Vpp 3 0 0 1 Hz Input Leakage Current 1 1 16 001 06 6 001 06 GRAPHICS _ NN EPSON NEUEN Output Specifications Symbol Parameter Condition Min Typ Max Units Low Level Output Voltage VoL 5 0V 2 TS2 CO2 TS2D2 6 mA Vss 0 4 Type 3 TS3 12 mA Type 4 TS4 CO4 24 mA Low Level Output Voltage Vor 3 3V Type 2 TS2 CO2 TS2D2 3mA Vss 0 3 Type 3 TS3 4 TS4 CO4 12mA Low Level Output Voltage Type 3 TS3 Io 5 mA Type 4 TS4 CO4 10mA High Level Output Voltage 5 0 Type 2 TS2 2 TS2D2 2 mA Vpp 0 4 Type 3 TS3 4
180. pare logic 16 X16B C 001 06 01352 Example If an ISA bus no byte swap with memory segment A and location 300h are used the corresponding settings of VD15 VDO would be 8 Bit ISA Bus 16 Bit ISA Bus Pin Name i Direct Mapping i Direct Mapping VD0 0 0 1 1 VDI 0 1 0 1 VD2 0 0 0 0 VD3 0 0 0 0 VD12 VD4 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx VD15 VD13 101 101 101 101 Where x don t care 1 connected to pull up resistor 0 no pull up resistor X16B C 001 06 GRAPHICS _ NE EPSsON 01352 Illustrated below is the display data which is output from the UDO to UD3 signal pins and the corresponding display on various panels Ups upa up ubo ups upa up Dual Panel Top LD3 8 bit Single Panel Dual Panel Bottom ups una up upo 4 bit Single Panel LCD PANEL PIXELS 640 DOTS 1 1 1 2 1 639 1 640 2 1 2 2 2 639 2 640 CEES UPPER LCD PANEL I 240 1 240 2 240 639 240 640 241 1 241 2 241 639 241 640 240 LINES TOP VIEW LOWER LCD PANEL Y 480 1 480 2 480 639 480 640 18 X16B C 001 06 MONOCHROME PASSIVE STN LCD PANEL INTERFACE
181. play memory data bus of even byte addresses and VD8 VD15 are connected to the display memory data bus of odd byte addresses The output drivers 44 51 41 48 of these pins are placed a high impedance state when RESET is VDO VD15 I O 54 61 51 58 TS2D2 high On the falling edge of RESET the values of VD0 VD15 are latched into the chip to configure various hardware options VD0 VD15 each have an internal pull down resistor see section Table 5 6 on page 25 33 43 30 40 VAO VAI5 O 62 66 59 63 CO2 These pins are connected to the display memory address bus Active low chip select output to the second or odd byte address 2 92 29 SRAM See Display Memory Interface section for details Active low chip select output to the first or even byte address cal e o e Ber SRAM See Display Memory Interface section for details Active low output used for writing data to the display memory rd e j s This pin is connected to WE input of SRAMs VOE 83 80 CO2 Active low output to enable reading of data from the display memory This pin is connected to the OE input of the SRAMs Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 24 Table 5 3 Epson Research and Development Vancouver Design Center LCD Interface Pin Name FPDI 1 Pin Name Type FOB Pin F1B DOB Pin Pad Driver Description UD3 UDO UD3 UDO 70 73
182. pyright 1995 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 Hardware Functional Specification X16 SP 001 16 Issue Date 99 07 28 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTRODUCTION 2 000088 820 Se go as 9 12 05 5 o o ae Re um ek x ie 9 1 2 Overview 2 259 2 FEATURES s s E Ox 10 2 1 Technology xe ee fk ee wok 10 2 2 ee exse Ge ee env so 10 2 35 Display Modes gor ok oe x ey s d 24 Display Support
183. r Design Center 1 INTRODUCTION 1 1 Scope This is the Functional Specification for the SED1352 Dot Matrix Graphic Display LCD Controller Chip Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Graphics Subsystem Designers and Software Developers 1 2 Overview Description This device is designed for products where low cost low power consumption and low component count are the major design considerations This chip operates from 2 7 Volts to 5 5 Volts and up to 25MHz to suit different power consumption speed and cost requirements The SED1352 offers a flexible microprocessor interface SED1352 is capable of displaying a maximum of 16 levels of gray 16x4 Look Up Table is provided to allow remapping of the 16 possible gray shades displayed on the LCD panel The SED 1352 can interface to an MC68000 family microprocessor or an 8 16 bit MPU Bus with minimum external glue logic This device can directly control up to 128K bytes of static RAM with a 16 bit data path or up to 64K bytes with an 8 bit data path Hardware Functional Specification SED1352 Issue Date 99 07 28 X16 SP 001 16 Page 10 Epson Research and Development Vancouver Design Center 2 FEATURES 2 1 Technology low power CMOS e 2 7 to 5 5 volt operation 5 100 52 and QFP15 100 surface mount package 2 2 System maxi
184. r Design Center Program Messages ERROR This program requires BIOS1352 to be loaded The program BIOS1352 COM must be run before VIRTUAL EXE Load BIOS 1352 COM and then re run VIRTUAL EXE ERROR Insufficient memory for virtual display The virtual display is too large to fit in memory Choose a smaller x or y value ERROR Horizontal resolution must be a multiple of 8 Panning moves in multiples of pixels Choose a horizontal resolution which is gt a multiple of 8 so panning will not suffer from screen wrap around ERROR Specified horizontal resolution is smaller than panel resolution The virtual display must always be larger than the panel size ERROR Specified vertical resolution is smaller than panel resolution The virtual display must always be larger than the panel size SED1352 VIRTUAL EXE Display Utility X16 UI 002 08 Issue Date 08 10 08 EPSON SED1352 Dot Matrix Graphics LCD Controller 051352 Utility Document Number X16 UI 003 08 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this docume
185. rch and Development Vancouver Design Center Since note that thes since this demo program uses only 64k Registers must be adjusted to point to the D000 segment registers refer to words of data the Memory Interface is set to 16 bits Page 51 the Display Start Address To do so not bytes Consequently adding address registers will effectively the value 8000h words to th add 10000h bytes to the address point to D000 0000 WriteRegister 7 0x80 val ReadRegister 9 val 0x80 SB of Screen 1 Displ SB of Screen 2 Displ WriteRegister 9 val Set Address Pitch Adjustment to 0 WriteRegister 0x0d 0 Update Look Up Table for 16 gray shades for x 0 x 16 x WriteRegister 0x0e x WriteRegister 0x0f x Now that system is initialized val ReadRegister 1 val 0x10 LCDE enabled WriteRegister 1 val Programming Notes and Examples Issue Date 98 10 08 enable LCD Gl Adding 10000h to C000 0000 will which is why this address correction works lay Start Address lay Start Address Write to Address Pitch Adjustment Register SED1352 X16 BG 007 04 Page 52 Epson Research and Development Vancouver Design Center 6 3 Advanced Functions define VIRTUAL_X 360 define VIRTUAL_Y 360 FUNCTION Sh
186. rial protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352F0B ISA Bus Interface Considerations X16 AN 003 05 Issue Date 98 10 08 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 1 5 1 1 Reference Material 5 2 16 ISA BUS 6 12 PAL Equations i eR eot Be oe Reds 27 13 Additional Discrete Logic 2 7 14 SED1352F0B Default Setup 7 1 4 1 Configuration 7 1 4 2 Resister Setting v n ae pus S Bo RK AGS p SEC OR 7 3 8 BIT ISA BUS INTERFACE 8 1 5 SEDI352FO0B Default Setup 9 1 5 1 Configuration 9 1 5 2 Register Set ng y n ae SOP ea ee eoe be Se 9 List of Figures Figure 8 16 Bit ISA Bus Implementation 6 Figure 9 8 BitISA Bus Implementation 2 0 2 00000 00000000000 8 ISA Bus Interface Considerations SED1352F0B Issue Date 98 10 08 X16 AN 003 05 Page 4 Epson Res
187. rnal index register for I O accesses MPU Bus interface with memory accesses controlled by a READY WAIT signal Swap of high and low data bytes in 16 bit bus No byte swap of high and low data bytes in interface 16 bit bus interface VD2 MC68000 MPU interface VD3 Select I O mapping address bits 1 9 These nine bits are latched on power up and are compared to the MPU address bits 1 9 A valid I O cycle combined with a valid address will enable the internal I O decoder Therefore both types of I O mapping are limited to even address boundaries to determine either the absolute or indexed I O address of the first register Note that a valid I O cycle includes IOCS being toggled low VD4 VD 12 In direct mapping the base I O address is selected by VD7 VD12 In indexing the base I O address is selected by VD4 VD12 Select memory mapping address bits 1 3 These three bits are latched on power up and are compared to the MPU address bits 17 19 A valid memory cycle combined with a valid address will enable the internal memory decoder As only the three most significant bits of the address are compared the maximum amount of memory supported is 128K bytes Note that a valid memory cycle includes MEMCS being toggled low VD13 VD15 If 128K byte memory is used it must be mapped at an even address so all 128K bytes is available without a change in state on A17 as this would invalidate the internal com
188. rt Address Register LSB address 1000b Read Write Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX 09 Screen 2 Display Start Address Register MSB address 1001b Read Write Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 AUX 08 bits 7 0 Screen 2 Display Start Address Bits 15 0 AUX 09 bits 7 0 These 16 bits determine the Screen 2 Display Start Address In 8 bit memory configuration these bits set the 16 bit start address i e byte access In a 16 bit memory configuration these are the 16 most sig nificant bits of a 17 bit start address i e word access Page 23 In a dual panel configuration screen 2 refers to the lower half of the display The Screen 2 Display Start Address is the memory address corresponding to first displayed pixel in the first line of the lower half of the display If Screen 2 is started right after Screen 1 the Screen 2 Display Start Address is calculated with
189. s Conversion maps the external data bus either 8 bit or 16 bit into the internal odd and even data bus Address Generator The Address Generator generates display refresh addresses used to access display memory CPU CRT Selector The CPU CRT Selector accesses the display memory from the CPU or the display refresh circuitry Display Data Formatter The Display Data Formatter reads the display data from the display memory and outputs the correct format for all supported LCD panel types and gray scale selections Clock Inputs Timing Clock Inputs Timing generates the internal master clock according to the gray level selected and display memory interface The master clock MCLK can be MCLK input clock MCLK 1 2 input clock MCLK 1 4 input clock Pixel clock input clock SRAM Interface The SRAM Interface generates the necessary signals to interface to the Display memory SRAM 6 X16B C 001 06 6B C 001 06 AID DC SPECIFICATIONS Absolute Maximum Ratings Symbol Parameter Rating Units Supply Voltage Vss 0 3 to 6 5 VIN Input Voltage 0 3 to Vpp 0 3 V Vour Output Voltage Vss 0 3 to Vpp 0 3 V TsrG Storage Temperature 65 to 150 C Tso Solder Temperature Time 260 for 10 sec max at lead Recommended Operating Conditions Symbol Parameter Condition Min Ty
190. s Use internal index register for I O accesses Vp2 MPU Bus interface with memory accesses MEN mtertace controlled by a READY WAIT signal VD3 Swap of high and low data bytes in 16 bit bus No byte swap of high and low data bytes in interface 16 bit bus interface VD4 VD12 Select I O mapping address bits 1 9 These nine bits are latched on power up and are compared to the MPU address bits 1 9 A valid I O cycle combined with a valid address will enable the internal I O decoder Therefore both types of I O mapping are limited to even address boundaries to determine either the absolute or indexed I O address of the first register Note that a valid I O cycle includes IOCS being toggled low In direct mapping the base I O address is selected by VD7 VD12 In indexing the base I O address is selected by VD4 VD12 VD13 VD15 Select memory mapping address bits 1 3 These three bits are latched on power up and are compared to the MPU address bits 17 19 valid memory cycle combined with a valid address will enable the internal memory decoder As only the three most significant bits of the address are compared the maximum amount of memory supported is 128K bytes Note that a valid memory cycle includes MEMCS being toggled low If 128K byte memory is used it must be mapped at an even address so all 128K bytes is available without a change in state on A17 as this would invalida
191. s at 0003FFFFh External DSACKT response 16 bit port Don t care Function Codes and with CPU space access Both read and write accesses are allowed Settings for the Address Mask register and Base Address register for the above conditions are 058h 05Bh O003FFFFh Address Mask register 05 0526 000000F5h Base Address register SED1352 MC68340 Interface Considerations X16 AN 004 06 Issue Date 98 10 08 Epson Research and Development Page 7 Vancouver Design Center 2 2 PAL Equations The PAL is programmed with the following equations 1 With direct mapping I O occupying locations from 00000000h to 0000000Fh and A4 to A9 decoded internally to SED1352 IOCS CS3 amp A17 amp A16 amp 15 amp A14 amp AI3 amp A12 amp A11 amp A10 2 With memory locations from 00020000h to 003FFFFh and A17 to A19 decoded internally to SED1352 MEMCS CS3 3 BHE becomes valid for two conditions 1 16 bit or 32 bit cycle 1 SIZO 0 2 8 bit cycle with odd byte access i e SIZO 1 and AO 1 BHE 5170 amp AO 2 3 SED1352 Default Setup Configuration Options 1 VD15 VD13 001 memory decoding for locations 20000h 3FFFFh 2 VD12 VD4 000000xxx T O decoding for locations 00000000006 0000001111b 3 VD3 1 byte swap of high and low bytes 4 VD2 1 MC68K interface 5 VDI1 1 direct mapping I O 6 VDO 1 16 bit bus interface Where x don t care 1 pull up with a 10K resistor 0 no pull up resistor
192. s the value programmed bits 1 0 Total Display Line Count Bits 9 8 These are the two MSB of the Total Display Line Count Register AUX 04h AUX 06h Screen 1 Display Start Address Register LSB I O address 0110b Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX 07h Screen 1 Display Start Address Register MSB I O address 0111b Read Write Screen 1 Screen 1 Screen Screen Screen Screen 1 Screen 1 Screen 1 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 AUX 06h bits 7 0 Screen 1 Display Start Address Bits 15 0 AUX 07h bits 7 0 These 16 bits determine the Screen 1 Display Start Address In an 8 bit memory configuration these bits set the 16 bit start address i e byte access In a 16 bit memory configuration these are the 16 most sig Note nificant bits of a 17 bit start address 1 word access The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel top left corner In a dual panel configuration
193. screen refers to the upper half of the display While in a single panel configuration screen 1 refers to the first screen of the Split Screen Display feature where two differ ent images screen and screen 2 can be displayed at the same time on one display The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 VD15 see Table 5 6 Summary of Power On Re set Options on page 25 SED1352 X16 SP 001 16 Hardware Functional Specification Issue Date 99 07 28 Epson Research and Development Vancouver Design Center AUX 08h Screen 2 Display Start Address Register LSB address 1000b Read Write Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX 09h Screen 2 Display Start Address Register MSB I O address 1001b Read Write Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Screen 2 Display Display Display Display Display Display Display Display Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 AUX 08h bits 7 0 Screen 2 Display Start Address Bits
194. sed the Memory Interface is set to 16 bits and 128k of display memory is available In addition the two images shown on the split screen are each 320x240 only a portion of each image is shown 1 Determine whether the Display Start Address Registers refer to bytes or words Since the Memory Interface is set to 16 bits the Display Start Address Registers refer to words Note that when ad dresses refer to words the image must be aligned in memory such that the beginning is found on a word boundary the least significant bit of the memory address must be 0 2 Calculate the number of bytes per scan line 16 gray shades gt 4 bits per pixel 4 bits per pixel gt 2 pixels per byte ixel li 2 number of bytes per scan line Pxesperbyis m 160 bytes per scan line 00AO0h bytes per scan line 3 Determine the display memory location for image 1 For simplicity assign the beginning of display memory as the starting address of image 1 see Figure 11 For the SDU1352B0x this address is C000 0000h Display Memory Screen 1 Display Start Address C000 0000h Image 1 Screen 2 Display Start Address C000 9600h for this example Image 2 Figure 11 Memory Map for Split Screen 4 Program the Screen 1 Display Start Address Register to point to the beginning of image 1 Since image 1 is at the beginning of display memory for a 128k system program the Screen 1 Display Start Address Register to 0000h AUX 06h 00h AUX
195. set to 16 bits the Display Start Address Registers refer to words Note that when ad dresses refer to words the image must be aligned in memory such that the beginning is found on a word boundary the least significant bit of the memory address must be 0 2 Calculate the number of bytes per scan line 4 gray shades gt 2 bits per pixel 2 bits per pixel gt 4 pixels per byte ixel li 4 number of bytes per scan line Paire per bys 160 bytes per scan line 00 bytes per scan line 3 Determine the display memory location for image 1 For simplicity assign the beginning of display memory as the starting address of image 1 see Figure 11 For the SDU1352B0x this address is C000 0000h 4 Program the Screen 1 Display Start Address Register to point to the beginning of image 1 Since image 1 is at the beginning of display memory for a 128k system program the Screen 1 Display Start Address Register to 0000h AUX 06h 00h AUX 07h 00h 5 Calculate the total number of bytes required for image 1 bytes per scan line X number of scan lines for image 1 160 x 240 38400 bytes 9600h bytes 6 Determine the display memory location for image 2 Place image 2 immediately after image see Figure 11 Assign the starting address for image 2 as follows image 2 address base display memory address size of image 1 C000 0000h 0000 9600h C000 9600h 7 Program the Screen 2 Display Start Address Register
196. signed time NULL Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 62 for x 0 x lt 300 x FP OFF pVideo unsigned int rand OxffffL val rand 50 ShowText pVideo rand 16 ShowBorders Move virtual display from 0 0 to MaxX MaxX VIRTUAL X PanelX VIRTUAL Y PanelY for x 0 x lt MaxX x SetStartAddress x 0 1 0 1 for 0 lt MaxY SetStartAddress 1 0 1 for x x gt 0 SetStartAddress x MaxY Delay 0 1 for MaxY gt 0 SetStartAddress 0 y 1 0 1 SetStartAddress 0 0 0 RAND_MAX Epson Research and Development Vancouver Design Center FUNCTION PowerSaving DESCRIPTION INPUTS None RETURN VALUE SED1352 X16 BG 007 04 Starts power saving mode 2 None Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Page 63 Vancouver Design Center void PowerSaving void static unsigned int val printf Starting Power Saving n val ReadRegister 3 val amp 0x3f val 0x80 WriteRegister 3 val Set power saving mode 2 printf Press any key to canc
197. te the internal compare logic Note The SED1352 has internal pulldown resistors on these pins and therefore will be pulled down and read on a logic 0 after RESET If pullup resistors are required refer to Table 6 3 Input Specifications on page 26 for pulldown resistor values Example If an ISA bus no byte swap with memory segment A000h and location 300h are used the corresponding settings of VD15 VDO would be Table 5 7 I O and Memory Addressing Example 8 Bit ISA Bus 16 Bit ISA Bus Pin Name Roe Direct Mapping Direct Mapping VDO 0 0 1 1 VDI 0 1 0 1 VD2 0 0 0 0 VD3 0 0 0 0 VD12 VD4 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx VD15 VD13 101 101 101 101 Where x don t care 1 connected to pull up resistor 0 no pull up resistor Hardware Functional Specification Issue Date 99 07 28 SED1352 X16 SP 001 16 Page 26 6 D C CHARACTERISTICS Epson Research and Development Table 6 1 Absolute Maximum Ratings Vancouver Design Center X16 SP 001 16 Symbol Parameter Rating Units Vpp Supply Voltage Vss 0 3 to 6 5 V VIN Input Voltage 0 3 to 0 3 V Vour Output Voltage 0 3 to Vpp 0 3 V TsrG Storage Temperature 65 to 150 C Tso Solder Temperature Time 260 for 10 sec max at lead C
198. tents of a window 2 Line Byte Count 1 bytes wide The position of the window on the virtual screen is deter mined by AUX 06 and 07 and AUX 08 and 09 Programming Notes and Examples Issue Date 98 10 08 Epson Research and Development Page 29 Vancouver Design Center 5 1 2 Description The SED 1352 can be programmed to use memory offsets in such a way that the physical display behaves as a viewport into a much larger virtual memory space This viewport can be panned and or scrolled to display this larger memory space Referring to the figure below a virtual image of 640x480 can be viewed by navigating the 320x240 viewport around the image by panning and scrolling 320x240 Viewport Y 640x480 Virtual Display Figure 8 640 x 480 Virtual Display To create a virtual display the Address Pitch Adjustment Register must be programmed to indicate the horizontal size of the larger virtual image stored in display memory The Address Pitch Adjustment Register tells the SED1352 how many bytes or words of display memory are part of the nonvisible region of display memory see Example 10 Example 10 Program the Address Pitch Adjustment Register to support a 16 gray shade 640x480 virtual display on a 320x240 LCD panel the Memory Interface is 16 bits l Initialize the SED1352 registers for a 320x240 panel 2 Determine whether the Address Pitch Adjustment Register refers to bytes or words Since the
199. ter 3 2 2 Look Up Table Description The Look Up Table LUT or palette treats the value of a pixel as an index of an array of gray shades For example a pixel value of zero would point to the first LUT entry a pixel value of 7 would point to the eighth LUT entry Because LUT entries represent the actual gray shades shown on the LCD panel pixel values indirectly select which gray shade displays The SED1352 supports two different data formats 4 bits per pixel 16 gray shades and 2 bits per pixel 4 gray shades In 4 bits per pixel mode the SED1352 provides a 16 position 4 bit wide LUT In 2 bits per pixel mode the SED1352 provides 4 banks of 4 position 4 bit wide LUTs The value inside each LUT entry represents the gray shade This value ranges between 0 and 15 The SED1352FOB Look Up Table is linear increasing the LUT entry number results in a lighter gray shade For example a LUT entry of OFh into a look up entry will always result in a bright white output An entry of 00h into a look up entry will always result in a black output Example 3 Initialize the Look Up Table The following describes how to initialize the Look Up Table for 16 gray shades Table 3 1 shows a LUT with gray shades starting from black index 0 and finishing in white index 15 or OFh 1 Write LUT index to Look Up Table Address Register AUX OEh 2 Write LUT entry value to Look Up Table Data Register AUX OFh 3 Repeat steps 1 and 2 until all 1
200. terial protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16 AN 004 06 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center Table of Contents 1 1 1 Reference Material ll lees 2 MC68340MPUINTERFACE 2 1 MC68340 Setup c 2 4 RR e Yrs wo E S 22 PAL Equations eos Bh fe 2 3 SEDI352DefautSetup mo sov srogo a soroas List of Figures Figure 1 68340 MPU Interface Block Diagram MC68340 Interface Considerations Issue Date 98 10 08 Page 3 SED1352 X16 AN 004 06 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 MC68340 Interface Considerations X16 AN 004 06 Issue Date 98 10 08 Epson Research and Development Page 5 Vancouver Design Center 1 INTRODUCTION The SED1352 is a general purpose LCD controller capable of interfacing to a variety of microprocessors This interface is accomplished through the use of minimal external circuitry This application note describes the interface between the SED 1352 and the 16 bit MC6834
201. the Screen Display Start Address Registers for the SDU1352B0x evaluation board When the SDU1352B0x is set for 64k of display memory display memory exists from address D000 0000h to address D000 FFFFh When the SDU1352B0Xx is set for 128k of display memory display memory exists from address C000 0000h to address D000 FFFFh For the SDUI352B0x the Screen Display Start Address Registers are always in reference to the display memory address C000 0000h Writing 0 to a Display Start Address Register will always refer to C000 0000h even if display memory only exists from D000 0000h to D000 FFFFh Consequently if only 64k of display memory is present 64k must be added to the display address in order to point to D000 0000h This is a limitation of the evaluation board only Although the SED1352 can set the Memory Interface to 8 or 16 bits the SDU1352B0x evaluation board should be set up for 16 bits As a result the Display Start Address Registers are word pointers not byte pointers To illustrate how to use a word pointer refer to Example 6 In general any system which uses more than 64k of display memory must always have the Memory Interface set to 16 bits Example 6 For the SDU1352B0x calculate the required start address register value which refers location D000 0000h Since a value of 0 refers to location C000 0000h the start address register must be programmed with an offset address of 1000 0000h 10000h bytes or 8000h words
202. to point to the beginning of image 2 Image 2 is placed right after image 1 as shown below size of image 1 in bytes Screen 2 Display Start Address Screen 1 Display Start Address 7 bytes per word 9600h 0000h 5 4B00h AUX 08h 00h AUX 09h 4Bh 8 Write both image 1 and image 2 to their respective locations in display memory SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 39 Vancouver Design Center Notes When using a dual panel the Screen 1 Display Line Count Register is ignored by the SED1352 Once the two Display Start Address Registers are programmed the top panel will show the beginning of image 1 and the bottom panel will show the beginning of image 2 see Figure 13 Scan Line 0 n Image 1 Scan Line 239 Scan Line 240 ae Image 2 Scan Line 479 Figure 13 640 x 480 Dual Panel for Split Screen Each image can be scrolled or panned by appropriate programming of the respective Display Start Address Registers The following are some examples To scroll image 1 up the Screen 1 Start Address Register must point to the following scan line number of bytes per scan line Screen Display Start Address Screen 1 Display Start Address Z bytes per word AUX 06h LSB of Screen 1 Display Start Address AUX 07h MSB of Screen 1 Display Start Address To scroll image 2 down the Screen 2 Start Address Register must point to
203. tor CPU BUS Commenta Pin No Pin Name 1 SAO Connected to ABO of the SED1352 2 SAI Connected to ABI of the SED1352 3 SA2 Connected to AB2 of the SED1352 4 SA3 Connected to AB3 of the SED1352 5 SA4 Connected to AB4 of the SED 1352 6 5 5 Connected to 5 of the SED1352 7 SA6 Connected to AB6 of the SED 1352 8 SA7 Connected to AB7 of the SED 1352 9 GND Ground 10 GND Ground 11 SA8 Connected to AB8 of the SED1352 12 5 9 Connected to AB9 of the SED1352 13 5 10 Connected to AB10 of the SED1352 14 5 11 Connected to AB11 of the SED1352 15 5 12 Connected to AB12 of the SED1352 16 5 13 Connected to AB13 of the SED1352 17 GND Ground 18 GND Ground 19 14 Connected to 14 of the SED1352 20 SAI5 Connected to AB14 of the SED 1352 21 5 16 Connected to AB16 of the SED1352 22 5 17 Connected to AB17 of the SED1352 23 5 18 Connected to 18 of the SED1352 24 5 19 Connected to 19 of the SED1352 25 GND Ground 26 GND Ground 27 5V 5 volt supply 28 5V 5 volt supply 29 NOW Connected to the IOW signal of the SED1352 30 Connected to the IOR signal of the SED1352 31 SMEMW Connected to the MEMW signal of the SED 1352 32 SMEMR _ Connected to MEMR signal of the SED1352 SDUI1352B0C Rev 1 0 Evaluation Board User Manual Issue Date 98 10 07 Page 11 SED1352 X16 AN 002 09 Page 12 Epson Research and Development Vancouver Design Center 1 3 Technical Description 1 3 1 ISA Bus Support This board direct
204. umn If there are 4 gray levels there are 4 pixels byte if PanelGrayLevel 4 color amp 0x03 while str 0 ch if ch pFont amp font 1 0 Block character else if ch A ch gt Z pFont amp font 0 0 blank character else pFont amp font ch A 2 0 for 0 lt 8 pDisplay pdisplayFirstColumn val pFont iY Since there are 4 gray shades each bit in the font will be represented in display memory two bit gray shade SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Vancouver Design Center if val amp 0x80 Display color lt lt 6 else Display 0 if val amp 0x40 Display color lt lt 4 if val amp 0x20 Display color lt lt 2 if val amp 0x10 Display color 1 unsigned char Display if val amp 0x08 Display color lt lt 6 else Display 0 if val amp 0x04 if val amp 0x02 if val amp 0x01 Display color lt lt 4 Display color lt lt 2 Display color 1 unsigned char Display pdisplayFirstColumn BytesPerScanLine pdisplayStart 2 pdisplayFirstColumn else color while ch 16 Gray Shades amp OxOf str 0 strt t Gh
205. unctional Specification X16 SP 001 xx The two sequential I O addresses are defined as Index Address and Data To access registers using this method an Index Address must be written to the first I O address location allowing data to be written read to from the second I O address Example 12 Write 12h to register 08h on the SDU1352B0x evaluation board the base port address is 310h and indexed port mapping is used 1 Write O8h to the index register The index register is at base port address 0 310h MOV DX 310h MOV AL 08h OUT DX AL 2 Write 12h to the data register The data register is at base port address 1 311h MOV DX 311h MOV AL 12h OUT DX AL 5 3 2 Direct Addressing This method of addressing requires 16 sequential I O addresses starting from the base I O address The base I O address is determined by the power on state of the SRAM data lines VD 7 12 See Table 5 6 in the SED1352 Hardware Functional Specification X16 SP 001 xx To access the internal 16 registers of the SED1352 simply perform I O read write functions to the absolute address as defined in the previous paragraph SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 33 Vancouver Design Center Example 13 Write 12h to register 08h on the 5001352 0 evaluation board the base port address is 310h and direct port mapping is used 1 Calculate the port address for register O8h port
206. up table Text is shown by creating a font which in this example is a series of bitmaps one bitmap per alphanumeric character Example 11 Display the word TEXT ona 16 gray shade 320x240 LCD panel the Memory Interface is 16 bits 1 Define the font for the letters T and X Each character is 8x8 pixels with at least one horizontal and vertical side left blank for spacing Figure 9 Font for the Message TEXT 2 Program the Look up Table See Example 3 Initialize the Look Up Table on page 17 3 Calculate the display memory map See Figure 5 Memory Map for 320 x 240 LCD Panel with 16 Gray Shades on page 25 4 Write font to display memory In a general purpose program the entire bitmapped font would be placed in an array As characters are to be dis played the program would choose the appropriate bitmap select the proper position on the screen and write to dis play memory For this example assume that the program has already selected the proper bitmaps and the correct positions in display memory there is a detailed programming example later in this guide see Section 6 3 Advanced Functions on page 52 Each highlighted pixel in the text bitmap will be shown at maximum intensity which is pixel value 15 The text for simplicity will be shown in
207. wed by the first part of image 2 AUX 0Ah 00h AUX 0Bh 00h It is not possible to show only image 2 by changing the line count If only image 2 needs to be shown reprogram the Screen I Display Start Address Registers to point to the beginning of image 2 and set the line count to the maximum number of visible scan lines 1 SED1352 Programming Notes and Examples X16 BG 007 04 Issue Date 98 10 08 Epson Research and Development Page 37 Vancouver Design Center line count is set to 99 then the first 100 scan lines of image 1 are shown following by the first part of im age 2 see Figure 12 AUX 0Ah 63h 99 decimal AUX 0Bh 00h Scan Line 0 s Image 1 Scan Line 99 Scan Line 100 Image 2 Scan Line 239 Figure 12 320 x 240 Single Panel for Split Screen 9 Write both image and image 2 to their respective locations in display memory Programming Notes and Examples SED1352 Issue Date 98 10 08 X16 BG 007 04 Page 38 Epson Research and Development Vancouver Design Center 5 4 4 Dual Panel LCD The following is the procedure to show a split screen image on a 4 gray shade 640x480 dual panel LCD For this example the SDU1352B0x is used the Memory Interface is set to 16 bits and 128k of display memory is available In addition the two images shown on the split screen are each 640x240 1 Determine whether the Display Start Address Registers refer to bytes or words Since the Memory Interface is
208. x Graphics LCD Controller SDU1352BOC Rev 1 0 Evaluation Board User Manual Document Number X16 AN 002 09 Copyright 1995 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 SDU1352B0C Rev 1 0 Evaluation Board User Manual X16 AN 002 09 Issue Date 98 10 07 Epson Research and Development Vancouver Design Center Table of Contents 1 SDU1352BOC REV 1 0 EVALUATION BOARD 1 1 Features i 1 2 Installation and Configuration 1 3 Technical Description 1 3 1 1 3 2 1 3 3 1 3 4 1 3 5 1 3 6 1 3 7 1 3 8 1 3 9 1 3 10 Appendix A Appendix B ISA Bus Supporte c i Saha Pee he efe BORER eS IE e EA Non ISA Bus Support SRAM SUpport s Rr Rr
209. y Interface is set to 16 bits and 128k of display memory is available 1 Determine whether the Display Start Address Registers refer to bytes or words Since the Memory Interface is set to 16 bits the Display Start Address Registers refer to words Note that when ad dresses refer to words the image must be aligned in memory such that the beginning is found on a word boundary the least significant bit of the memory address must be 0 2 Calculate the number of bytes per scan line 4 gray shades gt 2 bits per pixel 2 bits per pixel gt 4 pixels per byte ixel li 4 number of bytes per scan line SOR perbyt 160 bytes per scan line 00 bytes per scan line 3 Determine the display memory location for image 1 For simplicity assign the beginning of display memory as the starting address of image 1 see Figure 14 For the SDU1352B0x this address is C000 0000h Display Memory Screen 1 Display Start Address First half of Image Screen 2 Display Start Address Second half of Image Figure 14 Memory Map for a Dual Panel showing a Single Image 4 Program the Screen Display Start Address Register to point to the beginning of image 1 Since image 1 is at the beginning of display memory for a 128k system program the Screen 1 Display Start Address Register to 0000h AUX 06h 00h AUX 07h 00h 5 Determine the size of image 1 number of scan lines in display _ 480 5 240 sca
210. y at least half a second depend on panel type it may be required more time delay 4 Write to bit 4 of AUX OIh with value 71 SED1352 X16 AN 005 07 LCD Panel Options Memory Requirements Issue Date 98 10 08 Page 12 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1352 LCD Panel Options Memory Requirements X16 AN 005 07 Issue Date 98 10 08

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