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MPC5510EVB User Manual

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4. 12 3 4 DEBUG CONFIGURATION 724 08 31 131 1 2 204 4 180 neret nennen rne 12 341 TELK Configuration iate te ee pase ee oes 12 3 42 ResetB fferihg uu tg dte oue ae 12 343 1 REUS ac t Tees eed eterne eene etos 13 2447 Vendor Configuration x enne e e e e De PO RE e iens 13 Debug Connector PIBOUIS 14 3 5 EXTERNAL MEMORY CONFIGURATION carens iinn E 15 3 5 1 Power Control J22 32 16 3 5 2 Port Size Select and Chip Select Control J35 sse 16 3 6 CAN CONFIGURATION J3 J4 JT tete t Grm ede n mean dete perve d eite t 17 3 7 RS232 CONFIGURATION J9 110 JIN os eee t eer tere herr E dese deca e de e een 18 3 8 LIN CONFIGURATION J1 J2 5 J6 e tete ee eiu reete d p EU be as 19 3 9 FLEXRAY CONFIGURATION 112 J13 J14 J15 J16 18 20 3 10 LED DOT MATRIX J23 gea me e aged arena tus e ok ee 22 3 11 TERMINATION RESISTOR CONTROL 726 23 4 SDAUGHTERCARDS NEEE E Ea 24 4 1 INSTALLATION AND REMOVAL INSTRUCTIONS
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8. 12 TABLE 3 13 PFO EVTI R W FUNCTION SELECTION ccccccsscccesssscecesscececsseeecesssececssseeceesseeeceessececssseeceeseeeceesseeecsteseesenes 13 TABLE 3 14 VENDOR I O2 DRIVE CONTROL ccccssccecssscececsececeessececesececeesseecceessececssseeceesseeeceessececssseceenaeeeceesseeeenteseesenas 13 TABLE 3 15 NEXUS DEBUG CONNECTOR PINOUT cccsessssesececeesssececececsesssececececeeseseceeececsesesaecececsesesaseseesceesensaaeeeeess 14 TABLE 3 16 MCU PINS REQUIRED FOR EIM SRAM OPERATION 2 00002 0 4 0 600000000000000000000000000000 0 15 TABLE 3 17 SRAM AND PLD POWER CONTROL JUMPERS 722 32 22222 2 2 00 0 0 000000000000 16 TABLE 3 18 CHIP SELECT AND PORT SIZE CONTROL JUMPER 735 16 TABLE 3 19 CAN CONTROL JUMPERS J3 4 J7 eese ener trennen ener nennen 17 TABLE 3 205 17 TABLE 3 21 5232 CONTROL JUMPERS ete ee vett ee etd eee eura eer eere e 18 TABLE 3 22 SCEPINCAVAIEABILITY teet ede ERA eeu ep ee ree eed rere 19 TABLE 3 23 LIN CONTROL JUMPERS oer Eee teo eo dee eee aeree ea dg eus 20 MPC5510EVBUM D iii Because of an order from the United States International Trade Commission BGA packaged
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11. sadi essetis 27 TABLE 5 1 EVB MCU PIN 0 27 TABLE 6 1 DEFAULT JUMPER POSITIONS cccsessscccececesssssececececeenssuececececsessauececececseneseceeececsensasseceeecsesesaaecececeesenaaeeeeess 28 TABLE 7 1 PORT A CONNECTOR PINOUT 16 2 2 021 4 1100000 ener enne enne nnne 30 TABLE 7 2 RV1 CONNECTION JUMPER J8 ccceccccscsscccccecsessssececccecsesssececececsessseaeceescseneeaecececeenessaseseescsesensaeeeecceceeneaeaeeees 30 TABLE 7 3 PORT B CONNECTOR PINOUT P30 reiii ee enne nnne nennen nennen enn entren nennen 30 TABLE 7 4 PORTC CONNECTOR PINOUT P24 sessi nenne entren trennen erret nns 31 TABLE 7 5 PORTD CONNECTOR PINOUT 15 etie edi teet e este He Rae edad never eade 31 TABLE 7 6 PORTE CONNECTOR PINOUT P31 sess eene nennen 31 TABLE 7 7 PORT PINOUT P17 seeded eee e esse e 32 TABLE 7 8 PORT CONNECTOR PINOUT P25 nnise iiis ai ai i e a aS eie E eei e eiia isan 32 TABLE 7 9 PORT H CONNECTOR PINOUT aN EEA E AE EE A 32 TABLE 7 10 PORTI CONNECTOR PINOUT EE E AE EE 33 TABLE 7 11 PORT K CONNECTOR PINOUT
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13. shee 500 ui sjonpoud X GGOdlW 0 LOZ sejejs payun ay ejes 4 ped pue 1 seyeis eu JopJO asneseg somosta 4952 751112222222 llooooooooo00 40000000000 010 00000000000 00000000000 llogoo00000000 USER LEOS 0 0 R boo0o000000000 000000000000 1100000000000 c 5 X 00000000000 2 o0o0000000000 221 oooooooooo od 63 Y P llooooooooooo 1293221255945 5 N omi nm 341101084 m z 4 _ D ET 1 s i 42 ofr n S 993 02 g 13524 5 o 377253384 10022 A 5 s 25 gt gt E 2 4 oe ix T 3 5 n u 5 E EIS e 3 2006 55 1 Z 5 2 a 4 3 3 gt 5 z N Os Te 25 5 E Y 5510 User Manual Rev 1 0 Sept 2007 Revision History March 2007 Initial Release RevA PCB s only Excludes BOM and daughter card
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15. By default the SRAM memory and latches are powered but the PLD is disabled This ensures that outputs on the buffers and SRAM s are tri stated so do not affect the corresponding GPIO signals To power down the memory and latches if desired remove jumper J22 In order to use the external SRAM the memory latches and GAL must all be powered by fitting jumpers J22 and J32 Note The SRAM and buffers are 5 0V devices so the corresponding MCU pins must be configured as 5 0V 3 5 2 Port Size Select and Chip Select Control J35 Jumper J35 serves 2 purposes with a single jumper Firstly it determines which MCU chip select CSO or CS1 is used to control the SRAM and secondly it determines whether the SRAM is configured for a 16 bit or 32 bit data port size Table 3 18 Chip select and Port Size Control Jumper J35 Jumper Position PCB Legend Description REMOVED No SRAM system is enabled Jas 2 4 D CS0 16 Bit MCU chip select 0 is used to control 16 bit SRAM 4 6 CSI 16 Bit MCU chip select 1 is used to control 16 bit SRAM 1 3 CS0 32 Bit MCU chip select 0 is used to control 32 bit SRAM 3 5 CSI 32 Bit MCU chip select 1 is used to control 32 bit SRAM Notes The jumper shunts should be placed horizontally Any jumper combination other than those shown in the table above is invalid and will cause mal function of the EVB or MCU This jumper header has no effect unless jumper J22 and J32 are fitted
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17. MPC5510EVBUM D Page 28 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 Default Jumper Positions Continued Jumper Default Posn Legend Description J35 2 4 50 16 Bit MCU chip select 0 is used to control 16 bit SRAM J36 VPP 1 2 5V S MCU VPP is powered from 5 0V switching regulator J37 VDDR 1 2 5V S MCU internal VREG 15 powered from 5 0V switching reg J38 VDDA 1 2 5V L MCU VDDA is powered from 5V linear regulator J39 Y1 PWR FITTED EVB oscillator module Y1 is powered J40 OSC SEL 1 2 1 Daughter is routed from Y1 J41 SBC PWR REMOVED SBC linear regulator output is Disabled J42 5 0V LINEAR FITTED ENABLE 5 0V linear regulator output is Enabled J43 Not Impelemted 444 1 5 REMOVED DISABLE 1 5V switching regulator output is Enabled 445 3 3V REMOVED DISABLE 3 3V switching regulator output is Enabled J46 5 0V REMOVED DISABLE 5 0V switching regulator output 15 Enabled MPC5510EVBUM D Page 29 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicat
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19. A AEN E EEE 33 TABLE 8 1 EXPANSION CONNECTOR PART NUMBERG cscssssssccecessssseceecceceesssececececsesseceeececsesessseeeeecsesesaaeeeesesesenssaeeeeees 35 TABLE 8 2 DAUGHTER CARD CONNECTOR a EE EE stone E AE I SEEE E N ae eon 35 TABLE 8 3 DAUGHTER CARD CONNECTOR 2 36 MPC5510EVBUM D iv Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 1 Introduction This user manual details the setup and configuration of the Freescale Semiconductor MPC5510 Evaluation Board hereafter referred to as the EVB The EVB is intended to provide a mechanism for easy customer evaluation of the 5510 family of microprocessors and to facilitate hardware and software development There are currently 3 package types supported within the MPC5510 family and by the EVB namely 208BGA 176QFP and 144QFP For the latest product information please speak to your freescale representative or consult the MPC5510 website at www freescale com The EVB is intended for bench laboratory use and has been designed using normal temperature specified components 70 11 Modular Concept For maximum flexibility and simplicity the EVB has
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22. 99085 05585 LED Matrix User LEDs and switches oF Su EIM and SRAM USER SWITCHES EKB JTAG and NEXUS gt HMPCB510EVB 2007 FREESCALE MCD APPLICATIONS z 625222520 46005009 91009000400 Clock led Circuitry and SMA In O User n Out Connectors 255222525 Power Connectors 000000 2990909 Daughter Card Connectors Voltage Power Routing with MCU Daughter Card Regulators Jumpers Superimposed Figure 3 1 EVB Functional Blocks MPC5510EVBUM D Page 3 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 The Power 3 1 Power Supply Configuration section is located in the bottom left area of the EVB The EVB requires an external power supply voltage of 12V DC minimum 1 This allows the EVB to be easily used in vehicle if required The 12v input is regulated on the EVB using 1 linear and 3 switching regulators to provide the necessary EVB and MCU operating voltages of
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28. 12 PF13 v 4 5 PH6 7 12 X M 14 15 X M LIN circuitry is located in the top edge of the EVB in an 3 8 LIN Configuration J2 J5 76 area titled LIN The EVB is fitted with two freescale MC33399 LIN transceivers The MCU SCI channels incorporate a hardware controlled LIN master and as such the LIN transceiver is connected to the same MCU pins as the RS232 transceiver Jumpers J10 and J11 are used as described in section 3 7 and in the table below to determine whether the relevant MCU pins are connected to the LIN transceiver or the SCI transceiver For flexibility the LIN transceivers are connected to a standard 0 1 connector P8 for LIN A and P7 for LIN B at the top edge of the PCB as shown in the figure below For ease of use the 12V EVB supply is fed to of the connectors and the LIN transceiver power input to pin 2 This allows the LIN transceiver to be powered directly from the EVB supply by simply linking pins and 2 of connector P7 P8 using a 0 1 jumper shunt VDD UNREG LIN VSUP LIN GND Figure 3 12 LIN Physical Interface Connector Along with the MCU signal routing jumpers J10 J11 there are jumpers J5 J6 to enable or disable the LIN transceiver and jumpers J1 and J2 which determine if the LIN transceiver is operating in master or slave mode as defined in the table below MPC5510EVBUM D Page 19 of 3
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33. ies 24 42 DAUGHTERCARD CONFIGURATION eene e en A E ESA 25 421 External VREG Configuration o te reet rede 25 4 2 2 Main Clock Configuration erre e aae 25 42 3 32Khz Clock Configuration dae eter re end epe eae 26 4 24 CLKOUT Impedance Matching Control ees 27 4 2 3 a egets ae eric aet 27 8 MCU PIN USAGE dois soncedestvscesdausicesessussacedstucesesvstsastassscedsoutssesbiesisestescasedsasuatsisesseedsssseisiies 27 6 DEFAULT JUMPER SUMMARY TABLE 28 7 USER CONNECTOR DESCRIPTIONS sscsssssssssscsssssessssescrssssscscssseserscssoesesssssscsssenerscssersesssesossssssosseeseseeees 30 7 1 1 Port A ADC Connector P16 and 28 30 TAD SCE P3 0 i cenae ende e vee nU e dee 30 71 32 Porte ADCAISCITP24 iei mad ipee eedem 3l 7 14 Port Dif CAN ZSCIASPI PIS ee eaue eai eene De Raids 31 7 1 5 PortE SPI eMIOS EIM Connector 31 31 MPCS5510EVBUM D i Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the Un
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38. 41 Installation and Removal Instructions The 5510 daughtercard connectors have a unique placement footprint meaning that only daughtercards from the MPC5510 family can be fitted To fit the daughtercard Ensure that the EVB is powered off With the white arrow on the daughtercard pointing towards the top of the EVB carefully line up the connectors on the underside of the daughtercard with those on the EVB and gently press down to fit the daughtercard Ensure the connectors are fully mated by pushing down on all corners of the daughtercard or the EVB may not function as expected To remove the daughtercard Ensure the EVB is powered off Gently rock the daughter card along the axis shown in the picture below Note that attempting to pull the daughtercard off the board in any other manner will probably cause damage to the connectors P Figure 4 2 Daughter Card Removal MPC5510EVBUM D Page 24 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package MPC5510EVB User Manual Rev 1 0 Sept 2007 4 2 Daughtercard Configuration 4 2 1 External VREG Configuration The default and recommended mode of operation of the MCU is to use the internal voltage regulators If you need to bypass the inter
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40. AUX 3 3V Switcher 1 5 Switcher o VDD 1 5 Figure 3 4 Power Supply Routing MPC5510EVBUM D Page 6 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 Table 3 3 MCU Power Supply Jumpers Power Jumper Position PCB Description Domain Legend 138 VDDA 1 2 D 5V L VDDA powered from 5V linear regulator 2 3 SBC MCU VDDA is powered from SBC VDD output 1 2 D 5V S MCU internal VREG is powered from 5 0V switching reg 5 0 J37 VDDR 2 3 SBC MCU internal VREG is powered from SBC VDD output REMOVED MCU regulator is not powered See note below J36 VPP 1 2 D 5V S MCU VPP is powered from 5 0V switching regulator 2 3 SBC MCU VPP is powered from SBC VCAN output J34 1 2 D 5V S VDDEx jumpers are supplied from 5V switching regulator VDDE SEL 2 3 SBC VDDEx jumpers are supplied from SBC VAUX Output J33 1 2 D FRM J34 MCU VDDE I is powered from output of J34 5 0V VDDE1 2 3 3 3V MCU VDDEI is powered from 3 3V switching regulator 3 3V J30 1 2 D FRM J34 MCU VDDE2 is powered from output of J34 VDDE2 2 3 3 3V MCU 2 is powered from 3 3V switching regulator J29
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46. 15 PEI4 eMIOS 30 v 16 PEI5 eMIOS 31 v 17 GND 18 GND impedance matching This can be disabled with a jumper if required See the daughter card user manual for details MPC5510EVBUM D Page 31 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 7 1 6 Port F EIM Connector P17 Table 7 7 Port F Connector Pinout P17 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PFO RD WR Y 2 1 v 3 PF2 8 v v 4 PF3 AD 9 Y Y Y 5 4 10 v v v 6 5 11 v v v 7 PF6 AD 12 v Y v 8 PF7 AD 13 v v v 9 14 v v v 10 PF9 AD 15 v v v 11 10 CS 1 Y Y 12 CS 0 Y Y 13 PF12 TS v v v 14 PF13 OE Y v 15 14 0 v v v 16 PF15 v 17 GND 18 GND Notes 0 15 are used to drive the EBI See section 3 5 PF 0 11 are used for the Nexus interface When using Nexus the must be disabled and nothing connected to these GPIO pins See section 3 4 7 1 7 Port G EIM Connector P25 Table 7 8 Port F Connector Pinout
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48. 3 10 LED Dot Matrix J23 he LED matrix is located beneath the prototype area The EVB includes a 5x7 LED dot matrix display connected via a 16244 buffer to MCU PortC eMIOS 0 11 pins The PWM ability on the pins allows strobing effects or the brightness of the matrix to be controlled if desired The LED matrix does not have any automatic character generation circuitry so to generate characters the 7 rows of the display must be written row at a time with sufficient scan speed to form the character without flicker This is potentially a good background task for the 70 core on the 5510 The diagram below shows how the matrix is connected Note that this is a common anode display so is illuminated by asserting the columns high and the rows low If desired the top two rows can be disabled for use with GPIO leaving 5 rows enabled which is still sufficient for most characters PC eMIOS11 Top 2 rows canbe isabled if i PC eMIOSI0 disabled if required PC eMIOS9 PC eMIOSS5 16244 Buffer Resistors to give approx 8mA PC eMIOS4 PC eMIOSO Figure 3 13 LED Matrix Control The 16244 buffers provide 4 separate output enable blocks These have been configured such that one block controls PortC outputs 10 and 11 and the remaining 3 blocks control PortC outputs 0 9 This allows the top two rows to be disabled if required A single jumper provides this functionality as described below Table 3 28 LED Matrix
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51. CS0 CSI Figure 3 9 CS and Port Size Control Jumper By default jumper header J35 is fitted to position 2 4 This enables the 16 bit SRAM system connected to MCU chip select CSO Moving the jumper horizontally determines which chip select is used whereas moving the jumper header vertically determines whether the 16 bit or 32 bit wide SRAM system is enabled Two LED s adjacent to the GAL 058 DS9 indicate the GAL operation and status DS9 shows GAL is powered and programmed and goes out when the EVB or MCU is in reset 058 illuminates when an external SRAM access is taking place MPC5510EVBUM D Page 16 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 CAN section is located in the top right corner of the EVB in an area marked CAN 3 6 CAN Configuration J3 J4 J7 The EVB has a Philips PCA82C250T high speed CAN transceiver on each of the MCU CAN A and CAN C channels The transceiver is pre configured for high speed operation by tying pin 8 of each PCA82C250T to ground via a zero ohm resistor If required these resistors can be exchanged to provide slope control mode of operation See the EVB schematics at the end of this manual for detail
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53. MCU 10 19 TDI MCU TDI 20 MDO 5 MCU PF9 21 TRST JCOMP 22 MDO 4 MCU PF8 23 Vendor I O 1 24 MDO 3 MCU PF7 25 Tool I O 3 RST OUT 26 MDO 2 MCU PF6 27 Tool I O 2 28 MCU PF5 29 Tool I O 1 30 MDO 0 MCU PF4 31 UBATT 12V Vin 32 EVTO MCU PFI 33 UBATT 12V Vin 34 MCKO MCU PF3 35 Tool I O 0 36 MSEI 37 VALTREF 5 38 MSEO MCU PF2 Note In order to preserve the ability to accurately measure power consumption on the MCU pins the JTAG and Nexus connector reference voltages are sourced directly from the 5V regulator or from the 12V unregulated input MPC5510EVBUM D Page 14 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 external memory block is located on the right had side of 3 5 External Memory Configuration EVB with some jumpers to right of the reset switch The 5510 external bus interface supports a multiplexed address data bus with a configurable data port size of either 16 bits or 32 bits The EVB uses 3 x 128Kbyte 16 bit asynchronous SRAM memories to provide either 128Kbytes of memory in 16 bit port width mode or 256Kbytes of memory in 32 bit port width A high speed PLD is used to control t
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56. 1 2 D FRM 134 MCU VDDE3 is powered from output of J34 VDDE3 2 3 3 3V MCU VDDE3 is powered from 3 3V switching regulator J27 FITTED MCU VDD33 pin is powered from switching regulator VDD33 REMOVED D MCU VDD33 pin is not powered externally add J25 FITTED MCU VDDSYN pin is powered from switching regulator VDDSYN REMOVED D MCU VDDSYN pin is not powered externally 15 321 VDD15 FITTED Meu VDD pin is powered from 1 5v switching regulator REMOVED D MCU VDD pin is not powered externally The jumper configuration shown in Table 3 3 details the default state of the EVB In this configuration the SBC is not used and all power is supplied from the Linear and Switching regulators VDDA is connected to the 5 0V Linear regulator VDDR is connected to the 5 0V switching regulator enabling the internal MCU 3 3V 1 5V regulators VPP and VDDE 1 3 are connected to the 5 0V switching regulator VDD33 VDDSYN and VDD are not powered externally IMPORTANT When jumper J37 VDDR is in position 1 2 5V S the MCU internal voltage regulators are enabled and supply power to the 3 3V and 1 5V MCU power domains In this case jumpers J27 VDD33 J25 VDDSYN and J21 VDD15 must not be fitted Similarly when jumper J37 is removed no power is supplied to the MCU internal voltage regulators and jumpers J27 VDD33 J25 VDDSYN and J21 VDD15 must be fitted to power the respective MCU pins The 3 3V and 1 5v switching regu
57. 4 5 MCU Pin Usage Map The table below provides a useful cross reference to see what MCU port pins are used by the various EVB peripherals and functions Note that there are some overlapping functions for example the Nexus and External bus as shown by the shaded boxes in the table below Table 5 1 EVB MCU Pin Usage Function PortA PortB PortC PortD PortE PortF PortG PortH PortJ Enabled By Default Nexus PE 6 PFO 11 CANA PD O 1 CANC PD 4 5 LINA PD 6 7 SCI LINB PD 8 9 Reset Config PD 2 Led Matrix PC 0 11 User RVAR 0 Disabled By Default SRAM PE 6 PF 0 15 PG 0 15 PH 14 15 PJ O 7 Flexray A 0 2 Flexray PC 7 9 MPC5510EVBUM D Page 27 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 6 Default Jumper Summary Table The following table details the DEFAULT jumper configuration of the EVB as explained in detail in section 3 Table 6 1 Default Jumper Positions Jumper Default
58. 7 89 14 91 93 95 PG8 97 PJ7 10 99 PF13 PH15 101 PG2 103 PGS PG7 105 107 PF6 109 PF9 PH14 111 113 PGI 115 PG4 PG6 117 119 TGT RST RST OUT Page 35 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Table 8 3 Daughter Card Connector 2 Pin Signal Signal Number Name Name Odd Even 1 PB6 10 3 15 5 7 GND 7 9 11 GND 10 13 7 15 17 PC8 GND _______ 21 11 12 23 GND PB8 25 14 1 27 5 PC9 29 PC13 GND 31 14 9 5 35 2 37 PC6 15 39 PDO PDI 41 PD2 GND 1 1 VDDE 45 PD4 47 GND PD 5 49 PD6 PD7 51 PD9 PD8 53 PD10 GND gt VDDEi 57 PD12 59 PE7 PD13 Pin Signal Signal Name Number Name 094 Even 61 9 63 PD14 65 10 67 12 PD15 69 71 GND PEO 73 PE13 1 19 2 14 77 79 15 PES 83 2 85 PJO PFO 87 89 4 91 CLK IN PJ6
59. 93 PJ4 95 GND 1 O 99 PE6 PF5 101 PJ3 GND 103 PF2 TDI 105 107 TCLK 109 111 PJ5 PF4 113 VDDE3 115 VDDE3 PF3 117 JCOMP TDO 119 TMS E Sept 2007 Power connections shown with red shading are from the outputs of the respective MCU power jumpers The power connections shown in orange shading 1 5V SR 3 3V SR 5 0V SR and P12V are direct outputs from the regulators main power input and are not jumpered These are designed to drive any non MCU daughter card The TGT RESET signal provides a mechanism of driving the MCU reset line from a non open drain source This can be used by a target system to control the system reset RST OUT is a driven reset signal which should be connected to Reset in of any custom devices on the daughter card The MCU Reset line provides a direct connection to the bidirectional MCU Reset pin Extreme caution should be exercised if this pin is used All of the MCU signals with the exception of VRH VRL EXTAL XTAL and REFBYPC are routed to the Notes circuitry connectors MPC5510EVBUM D Page 36 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 802 XLGGOdIN 0102 pa
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61. GND 22222222 MPC5510EVBUM D Page 30 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package Sept 2007 MPC5510EVB User Manual Rev 1 0 7 1 3 Port C ADC SCI P24 Table 7 4 PortC Connector Pinout P24 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PCO eMIOS 0 v v 2 PC eMIOS I Y Y 3 PC2 eMIOS 2 Y v 4 PC3 eMIOS3 Y Y 5 eMIOSI4 Y 6 5 eMIOS 5 Y Y 7 PC6 eMIOS 6 Y Y Y 8 Rey eMIOS 7 Y Y Y 9 8 Y v v 10 PC9 eMIOS 9 Y Y 11 10 eMIOS 10 Y Y 12 11 eMIOS 11 Y Y Y 13 12 eMIOS 12 Y Y 14 13 eMIOS 13 Y Y 15 14 eMIOS 14 Y Y Y 16 15 eMIOS 15 2 v Y 17 GND 18 GND Notes PC 0 11 is used to drive the LED dot matrix display if enabled See section 3 10 for details PC 0 2 and PC 7 9 are also used for the flexray interface See section 3 9 for details 7 1 4 Port D CAN SCI SPI P15 Table 7 5 PortD Connector Pinout P15 Pin Function Availability Pin Funct
62. MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 Configuration This section details the configuration of each of the EVB functional blocks Throughout this document all of the default jumper and switch settings are clearly marked with D and are shown in blue text This should allow a more rapid return to the default state of the EVB if required Note that the default configuration for 3 way jumpers is a header fitted between pins and 2 On the EVB 2 way and 3 way jumpers have been aligned such that is either to the top or to the left of the jumper On 2 way jumpers the source of the signal is connected to Pinl The EVB has been designed with ease of use in mind and has been segmented into functional blocks as shown below Detailed silkscreen legend has been used throughout the board to identify all switches jumpers and user connectors 1 SCI Ami 5 gt coco User Q Flexray drt 0 Potentiometer 10000001 my pn 2 a 01 B Bose i o00000000000000000000000000000 IST rat OOoO00000000000000000000000000000 SS 4 i fj wem ae cnr i 109 25199 REV EN abe 2 2 Prototype Area 000000000 Aroan amono
63. VDDA pin Linear LVI circuit monitor 5 0V Switcher MPC5510EVBUM D Page 8 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package MPCS5510EVB User Manual Rev 1 0 Sept 2007 3 2 MCU Clock Control J39 J40 MC U AEE control jumpers are located close to crystal 3 2 1 Clock Selection oscillator module Y1 The EVB supports three possible MCU clock sources 1 The local ALC pierce oscillator circuit on the MCU daughter card 2 An 8Mhz oscillator module on the EVB Y1 driving the MCU EXTAL signal 3 An external clock input to the EVB via the SMA connector P27 driving the MCU EXTAL signal The clock circuitry is shown in the diagram below Please refer to section 4 for specific daughter card configuration details EVB Clock Circuitry 3V_SR MCU Daughter Card Local Clock Circuitry Oscillator Module Y1 Local Crystal Circuit Y1 Figure 3 5 EVB Clock Selection Table 3 6 Clock Source Jumper Selection Jumper Position PCB Legend Description FITTED D EVB oscillator module Y1 is powered REMOVED EVB oscillator module 1 is not powered 140 OSC SEL 1 2 D Daughter card is routed from 1 2 3 S
64. been designed as a modular development platform The EVB main board does not contain an MCU Instead the MCU is fitted to an MCU daughter card sometimes referred to as an adapter board This approach means that the same EVB platform can be used for multiple package and MCU derivatives within the MPC5510 family High density connectors provide the interface between the EVB and MCU daughter cards as shown in the diagram below See section 4 for more information on the daughter card configuration Figure 1 1 Modular Concept EVB and MCU Daughter Cards MCU Daughter Card with specific MCU and local clock circuitry High Density Connectors EVB containing all circuitry except MCU MPC5510EVBUM D Page of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 2 EVB Features The EVB provides the following key features e Support provided for different MPC5510 MCU family members by utilising MCU daughter cards e Single 12 14V external power supply input with on board regulators to provide all of the necessary EVB and MCU voltages Power may be supplied to the EVB 2 1mm barrel style power jack or a 2 way lever connector 12V operation allows i
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69. 2 outputs from the MAX232 device is connected to a 9 way female D Type connector allowing a direct RS232 connection to PC or terminal Connector P5 provides the 5232 level interface for MCU SCI A and P6 for MCU SCI B The pinout of these connectors is detailed below Note that hardware flow control is not supported on this implementation Figure 3 11 5232 Physical Interface Connector The 5516 eSCI also provides hardware LIN master capability which is supported on the EVB via LIN transceivers see section 3 8 for details Jumpers J10 and J11 are provided to route the MCU SCI signals to either the RS232 or LIN physical interfaces as described below There is also a global power jumper J9 controlling the power to the RS232 transceivers Table 3 21 5232 Control Jumpers Jumper Position PCB Legend Description J9 FITTED D Power is applied to the MA X232 transceiver SCI PWR REMOVED No power is applied to the MAX232 transceiver J10 SCI A 2 4 D MCU is routed via MAX232 to P5 Top Row 4 6 TXD MCU TXD A is routed via LIN transceiver to P8 REMOVED MCU TXD A signal is disconnected from CAN LIN J10 SCI A 1 3 D MCU is routed via MAX232 to P5 Bottom Row 3 5 RXD MCU is routed via LIN transceiver to P8 REMOVED MCU signal is disconnected from CAN LIN J11 SCI B 2 4 D MCU TXD B is routed via MAX232 to P6 Top Row 4 6 TXD MCU is routed via LIN transceiver to
70. 2222222 To provide quick means of supplying input to the Analogue To Digital converter 2KQ variable resistor 1 will be connected between P5V and GND with the output centre tap connected to PAO ANO via jumper J8 By removing jumper J8 PAO is disconnected from the variable resistor and can function as a normal I O port J8 and RV1 are located in the top right hand corner of the EVB Table 7 2 Connection Jumper J8 Jumper Position PCB Legend Description J8 FITTED D Output from variable resistor RV1 is applied to MCU PAO RV1 REMOVED Output from is not connected to MCU disabled Note PAI4 and 15 can also be used for the EXTAL32 and XTAL32 32Khz reference clock If these pins are used for this purpose they will not be available for GPIO ADC input See section 4 2 3 for details 7 1 2 Port B ADC SCI P30 Table 7 3 Port B Connector Pinout P30 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 AIt 144 176 208 1 AN28 Y 2 AN29 Y Y 3 PB2 AN30 v Y 4 PB3 1 Y Y 5 PB4 AN32 Y 6 5 AN33 Y 7 AN34 8 7 AN35 Y 9 PB8 AN36 Y 10 PB9 AN37 Y Y Y 11 10 AN38 12 AN39 Y Y 13 12 TXD Y 14 PB13 RXD G Y Y 15 14 TXD H Y 16 15 RXD_H Y 17 GND 18
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74. 5 Flex B FITTED D WAKE Flexray B interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray B interface WAKE signal is unterminated Notes The default configuration has the flexray controller disabled Flexray A and B are a second alternate function of PortC as shown in the table below Before enabling Flexray you must ensure that none of the associated port pins are being used for any other function On the EVB PortC is shared with the LED Dot matrix display The flexray physical interfaces use molex 1 25mm shrouded 2 pin connectors to connect to the flexray bus as are standard fit on many Freescale development platforms using flexray Important A 40Mhz oscillator is required for the correct operation of the flexray controller Please ensure that an appropriate crystal is fitted to the MCU daughter card or use a 40Mhz external clock source MPC5510EVBUM D Table 3 27 Flexray Pin Availability Flexray 2 Alternate Pin Availability TXEN TX RX 144Pin 176Pin 208 Pin A PCO PCI PC2 v 9 PC8 21 36 Because of an order from the United States International Trade Commission BGA packaged product lines part numbers indicated here currently not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007
75. 5 0V 3 3V and 1 5V In addition the EVB supports the Freescale System Basis Chip SBC which is an integrated regulator for the MCU power supply lines For flexibility there are two different power supply input connectors on the EVB as detailed below 311 Power Supply Connectors 2 1mm Barrel Connector P28 This connector should be used to connect the supplied wall plug mains adapter Note if a replacement or alternative adapter is used care must be taken to ensure the 2 1mm plug uses the correct polarisation as shown below lt V 12V Figure 3 2 2 1mm Power Connector 2 Way Lever Connector P32 This can be used to connect a bare wire lead to the EVB typically from a laboratory power supply The polarisation of the connectors is clearly marked on the EVB Care must be taken to ensure correct connection V 12V Figure 3 3 2 Lever Power Connector 3 1 2 Power Switch SW6 Slide switch SW6 can be used to isolate the power supply input from the EVB voltage regulators if required Moving the slide switch to the right away from connector P32 will turn the EVB on Moving the slide switch to the left towards connector P32 will turn the EVB off MPC5510EVBUM D Page 4 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to Se
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79. 6 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Table 3 23 LIN Control Jumpers Sept 2007 Jumper Position PCB Legend Description J1 FITTED D LIN B transceiver is configured for LIN Master mode LINB M REMOVED LIN B transceiver is configured for LIN Slave mode J2 FITTED D LIN A transceiver is configured for LIN Master mode LINA M REMOVED LIN A transceiver is configured for LIN Slave mode J5 FITTED D The LIN B transceiver is enabled LINB EN REMOVED The LIN B transceiver is disabled J6 FITTED D The LIN A transceiver is enabled LINA EN REMOVED The LIN A transceiver is disabled Note Jumpers J5 J6 do NOT route power to LIN transceivers they only control an enable line on the LIN device Power to the LIN transceiver is supplied via connectors P7 P pin 2 The Default LIN configuration is with the module enabled in master mode By default the EVB SCI LIN signals are routed to the SCI transceivers To use the LIN interface the corresponding RX and TX pins must be routed to the LIN transceivers by re configuring jumpers J10 and J11 with the shunts positioned on pins 2 3 and 5 6 LIN slave mod
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82. 82 495 404 SSEZ HOS g uosueqoy Jequinn aus pe nouddy S9joN pue 4 uosyeqoy e uons 10 Aue seop 1 pue SAJOISSOdW 104 P120 104 940921 punea OS op 10 siseq e se soneuieuos 910 9 9 epuqpy 153 aJE2sooJJ P ped Aue 5 s10sseo20JdoJol A Ajlwe OL GGOdIN 5 14 eui 10 s y ui pesn Jo uonoejes jueuoduuoo Jo y se JO Ajueuem Aue zou seop yns sy sesodund pepi oud soneuieuos 95941 sjonpoug SNOILONULSNI LNOAVT 9 0N SHHONI Suorsueurd 14 401 Woy pue Nq god 40 AGISYAGNN 5 00 SOITv LI pejiejep ale sejou LNOAVT HOd ay uab XAdL sew 159 pejejndodun
83. AN controller The default configuration is with all jumpers fitted This fully enables both CAN A and CAN C with all MCU signals routed to the transceivers If the MCU is configured such that a CAN channel is used as GPIO then the respective jumpers must be removed from J3 or J4 or conflicts will occur Notes Both CAN channels are available on all current package derivatives see table below Care should be taken when fitting the jumper headers to the 2x2 jumper blocks J3 and J4 as they can easily be fitted in the incorrect orientation Jumpers J3 and 4 are fitted horizontally Table 3 20 CAN Pin Availability CAN 15 Alternate Pin Availability TX RX 144Pin 176Pin 208 Pin A PDO PDI PD3 PD2 PDA 5 MPC5510EVBUM D Page 17 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 RS232 circuitry is located at the top edge of the EVB in an area titled SCI 3 7 5232 Configuration J9 J10 J11 The EVB has a single MAX232CSE RS232 transceiver device providing RS232 signal translation for MCU SCI channels A and B Each of the two 523
84. C POWER tegens desse teet nasse eset nennen 5 TABLE 3 3 MCU POWER SUPPLY JUMPERS 1 2 00 120000000000000000000000000000 7 TABLE 3 4 VDDE 1 3 PAD GROUPINGS ccssscsssscessecsssevensecsseceensecsssccensesessesensecessevensecesseeensecssesensesnssesensecessesensecnsees 8 TABLE 3 5 POWER SUPPLY 1 1 12 224 00 0000001000000000000000000000000000 8 TABLE 3 6 CLOCK SOURCE JUMPER SELECTION 000 01200000000000000000000000000000 rena nnne en 9 TABLE 3 7 LVI MONITOR THRESHOLD 2 1 7 1 4 2 22 000000000000000000 10 TABLE 3 8 LVI CONTROL 8 000 01 10200000000000000000000000000000000000 10 TABLE 3 9 RESET OUT CONTROL 2 2 1 124204004 2 000410 7000000000000000000000000000 11 TABLE 3 10 CONTROL cccccccccecsssssseceeececsesscseceecceceeaueceecceceeseaaececececseneaaeceeececseseasaecececeeseaaaeeeesesesentaaeaeeees 12 TABLE 3 11 ONCE NEXUS TCLK TERMINATION 12 TABLE 3 12 JTAG NEXUS TARGET RESET
85. Control Jumper Position PCB Legend Description J23 FITTED D MCU PortC 10 11 signals are connected to LED Matrix LED Enable HIGH Posn 1 2 REMOVED MCU PortC 10 11 are not connected to LED Matrix J23 FITTED D MCU PortC 1 9 signals are connected to LED Matrix 8 LED Enable LOW Posn 3 4 REMOVED MCU 1 9 are not connected to LED Matrix MPC5510EVBUM D Page 22 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 By default the LED matrix is fully enabled with MCU PortC 0 11 signals being routed to the LED Matrix If you don t wish to use the matrix both jumpers should be removed from J23 Caution PortC is also used by the Flexray interface so the LED matrix and flexray interface cannot be used concurrently See section 5 for more details 3 11 Termination Resistor Control J26 When using the external bus there are some of the MCU control signals that must be pulled high In most normal circumstances these signals can also be left pulled high when the external bus is not used however a jumper J26 is provided to disconnect the power to these pulllup resistors if desired Table 3 29 EIM Pullup Resistor
86. Control J26 Jumper Position PCB Legend Description J26 FITTED D The external bus pullup resistors are powered enabled EIM Pullup REMOVED The external bus pullup resistors are not powered disabled MPC5510EVBUM D Page 23 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 4 Daughtercards This section of the user manual details how to configure install and remove the MCU daughtercards Failure to follow the installation and removal instructions could cause damage to the daughtercard connectors There are 3 daughtercards available as shown in the picture below The jumper naming has been standardised between the daughtercards so the configuration steps are identical making it extremely easy to migrate between cards 3 te ib 27 freescale BEE 92 freescale 5 t 1 2007 FRECSCACE 5 2007 FREESCALE A MCD APPLICATIONS EAST KILBRIDE UCO APPLICATIONS EAST KILBRIDE MCD APPLICATIONS EAST KILORIDE 5510 208664 DAUGHTER CARD 2007 5510 1160 DAUGHTER CARD 2007 EJ 5510 14407 DAUGHTER CARD 2007 144 208 176 Figure 4 1 Daughter Cards
87. Flexray PortC 0 2 7 9 VDDEI 5 0V or 3 3V 718 selects JTAG VDDE3 5 0V Nexus PF 0 11 VDDE2 3 5 0V 3 1 7 EVB Circuitry Power Domains Before disabling any of the EVB regulators it is worthwhile considering if any of the EVB components or peripherals you require will be affected Table 3 5 details a list of the various EVB components and peripherals powered by the regulators Note the SBC powers the MCU only and does not supply power to any of the EVB circuitry Table 3 5 Power Supply Distribution Regulator Used On MCU VDDI 5 pins ONLY use when on chip MCU regulator is disabled L5V Daughter Card Connectors 1 5V Switcher aughter Card Connectors 1 5V 1 5V Power section of Prototype area MCU VDD33 and VDDSYN pins ONLY use when on chip MCU regulator is disabled MCU VDDEXx pins when run in 3 3v mode Oscillator Module Y1 3 3V GAL22V10 Control Switcher Driver chip for LED Matrix I O supply for Flexray interface when VIO is 3 3V Daughter Card Connectors 3 3V 3 3V Power section of Prototype area MCU VDDEx 5v mode VPP and pins LVI circuit main power affecting Reset Switch Reset In Reset Out logic Reset configuration circuitry SRAM memory and address latches RS 232 Transceiver LIN transceiver CAN transceivers Flexray transceivers EIM signal pullup resistors Daughter Card Connectors 5 0V 5 0V Power section of Prototype area eICE and Nexus connectors 5 0V MCU
88. GNOOINAS TVNOLLVN 0 5 59 92 11 89797W 1 YOLONGNOOINAS TWNOILVN 89 92W1 Len S8dON fQav s929cW1 YOLONGNOOINAS IWNOILVN 59492 oen S8dON 0 S dWIZ 62W 1 YOLONGNOOINAS IWNOILVN 0 6 6 eim L SSO6ECOW YOLONGNOOINAS 3179593905 SSO6ECOW 8i NOIL VHOdHOO Of 18 AVOLAcC IVOdSI YOLONGNOOINAS 321111 Of 182 AVOLAZc 098 NOIL VHOdHOO ONN EC AVOLAcC IV9OdSI YOLONGNOOINAS NN1 Z AVOLAZZ1Vvods SLN L YOoOavrrc9lOAIVZNS SLNAWNYLSNI SYX3L H99QVrrc9VONTPZNS I 9917991951 ISSI 991799 1951 LLN VIN ZLN VSOS0ZXVIN INIXVIA VSOS0Z7XVIN LEN 005 1495 OT Ady enue 155 HAH9TSSOd N 005 3496 802 S JONPOJd x 0102 sejejs payun eu ejes Jo y oduui 4 pejeoipui ped pue seul 3onpoud peBexoed yog UOISSILWWOD jeuoneuJeju sejejs paun ue 10 jesus 2002 21 1equiejdeg AepseupaM eieg LELEZ 4dS dQd LELEZ HOS 8 yemas juawnoog aus Aouddy pue sjugjuo 11014 weweis on abed Aq mesg 913019694 20 yemas W 910 9 9 epuqpy 1523 1 53
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91. LX eoanog 20 50 ueym azedun TVIX TVIX TIVLXH sTeubrsenboTeue INOMTO NOW deex NASQdA pU NASSSA seubrs TWLX 3 OT Ady enuen SN HAH9TSSOd A 802 sjonpoud XLGGOdW 0LOZ sajejs payun y Jo 10 4 ejqejreAe eJeu pejeoipui ped pue seul 4 peBexoed yog UOISSILWWWOD jeuoneuJeju sejejs paun eui JepJo ue 30 S 19945 7002 z 1equieydes AepseupeMw SEG LELEZ 4dS 3 LELEZ HOS 8 2215 10 99UUOD SA30LSS2 dI 10 peg sajyBneg Buweig JOj2nipuoorues 2 1 2 se SYOLOANNOD 1 lt 005 3496 TVIX3 8A3 9 8 gt let 01 90134 NOILVOI4IOSdS HLIM NI GHOVId LSAW SHOLOSNNOO 2884 dwoor SNL pexedunp 2 gt gt aah 092 NOD
92. MA Daughter card EXT CLK is routed from P27 The default configuration provides power to the EVB oscillator module 1 and routes this clock signal to the MCU daughter card Note that the 3 3V regulator must be enabled when using oscillator module Y1 In order to use the SMA connector P27 to supply a clock signal jumper J40 must be moved to position 2 3 SMA The selection between local clock circuitry or external oscillator is achieved using jumpers on the daughter card See section 4 for details CAUTION The 5510 clock circuitry is all 3 3v based Any external clock signal driven into the SMA connector must have a maximum voltage of 3 3V MPC5510EVBUM D Page 9 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 RESET switch RED and 3 3 Reset Control Jumpers J17 J19 J20 SW1 LVI circuitry is located in the top left corner of the EVB in the area titled RESET The EVB incorporates an LVI Low Voltage Inhibit device to provide under voltage protection for the two main 5 0V regulators Linear and Switcher The SBC has its on monitoring circuit so does not require external monitoring When either of the 5 0V regulator volta
93. NG SCHEME i an Ro eR e Ve Ve eee e QNS 11 FIGURE 3 7 5510 JTAG ONCE 2 0 0020000 eene sedens enne esee 14 FIGURE 328 EXTERNAL MEMOR Y SUBSY STEM 15 FIGURE 3 9 CS AND PORT SIZE CONTROL JUMPER ccccsessscccececeesssececececsessuececcceceeseseeecececseseseseceeecsesesaaeeeeeesesensaaeeeeess 16 FIGURE 3 10 CAN PHYSICAL INTERFACE CONNECTOR cccccccscessesssececececeessssececececsensnsececececsesenssaeseeccseneaeaeseescsesensaaeeeeees 17 FIGURE 3 11 RS232 PHYSICAL INTERFACE CONNECTOR cccccccecessssssceeececsessaececececsensececececseseaaaeceeecsesessaeeeeccsenensaaeeeeees 18 FIGURE 3 12 LIN PHYSICAL INTERFACE CONNECTOR csccscscsccecsssssececececsessaeceeccecsesssececececsensaaeaecececseseaeaesececsesentaaeeeeees 19 FIGURE 3 13 MATRIX CONTRO 22 FIGURE 4 1 DAUGHTER CARDS etn seas esas eee 24 FIGURE 422 DAUGHTER CARD REMOYV AL iecit ire 24 FIGURE4 3 DAUGHTERCARD CLOCK SELECTION cccssssssscecececsessaececececsensaaececececsessaaeeecececseseaeaecececseseneaececeesesenaaeeecees 25 FIGURE4 4 DAUGHTERCARD 32KHZ CLOCK SELECTION sees eene enhn nennen entre nnne setenta nnns esee eite annees 26 TABLE 3 1 REGULATOR POWER JUMPERS tiene a HE E ERE Ye XXE Re ERE 5 TABLE 3 2 SB
94. O 046 0 001 ve 82 ON QNO 600 0 110919 ON e 85 1001 51 g 900 oe Ea 450 OL 238 pLHd 20 30 d 11 we yrav 4 200 155 9 7650 150 052 GNH AS WVHS 099 30 d uaav ODDA Toam isl old 297 i 26 Tam Glad ilre ot wiva 3104 319 91 101 LE XLNO ISY Jav 118 91 SH 3M 118 0 SH 3M 19 291193 2 40001 9zHaav GND 14047 Lev QNO gcHOQV 6 ian LO 6cuaav XLNO LSUY 21198 9 2 lt 5 114 2 3oz vo 30 121 1 91 792195 T 8 ON QNO yt i ON L dde ON d 242 m 1 91 e3eq 103 pexnbrjuoo st 6E Taa scc UT Aq It 91 VIVO Ov 054 vot GT 0 VIVd eq WIS lv 50 fac eui UT 39 Wad epou snq ezed 379 91 UI 21 tae ue3s g LIGH 9T
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97. P25 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PGO AD 16 2 PGI AD17 Y Y Y 3 PG2 AD 18 Y Y Y 4 PG3 AD 19 Y Y Y 5 PG4 AD 20 Y Y 6 5 AD 21 Y Y Y 7 PG6 AD 22 Y 8 PG7 AD 23 9 PG8 AD 24 10 PG9 AD 25 Y Y Y 11 PGIO AD 26 12 PGII AD 27 Y Y Y 13 PGI2 AD 28 Y Y Y 14 PG13 0 29 Y Y Y 15 14 AD 30 Y Y Y 16 15 AD 31 Y Y Y 17 GND 18 GND KAMA Note PG 0 15 are used to drive the See section 3 5 7 1 8 Port ADC EIM Connector P29 Table 7 9 Port H Connector Pinout Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PHO 27 Y 2 PHI AN 26 Y Y Y 3 PH2 25 Y Y 4 PH3 AN 24 Y Y Y 5 4 23 Y 6 5 22 Y 7 PH6 AN 21 Y Y Y 8 PH7 AN 20 Y Y Y 9 PH8 AN 19 Y Y Y 10 PH9 AN 18 Y Y Y 11 10 AN 17 Y Y Y 12 AN 16 Y Y Y 13 PHI2 PCS D 5 Y 14 PH13 Y 15 14 WE 2 Y Y 16 15 WE 3 Y Y 17 GND 18 GND Note PH 14 15 are used to drive the EBI 32 bit data port mode See section 3 5 MPC5510EVBUM D Page 32 of 36 Because of an order from the United States International Trade Commission BGA packaged product line
98. P7 REMOVED MCU TXD B signal is disconnected from CAN LIN 1 3 D MCU RXD B is routed via MAX232 to P6 oe 3 5 RXD MCU RXD B is routed via LIN transceiver to P7 Row REMOVED MCU signal is disconnected from CAN LIN The default configuration enables SCI A and SCI B channels RS232 compliant interfaces with no hardware flow control are available at DB9 connectors P5 and P6 If the MCU is configured such that the pins used on SCI A or SCI B are used for GPIO see Table 3 22 then the relevant jumpers must be removed to avoid any conflicts occurring If required jumper J9 can be used to completely disable the SCI transceiver Note Care should be taken when fitting the jumper headers to the 2x3 jumper blocks J10 and J11 as they can easily be fitted in the incorrect orientation Jumpers J10 and 11 are fitted horizontally MPC5510EVBUM D Page 18 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 Table 3 22 SCI Pin Availability SCI 1 Alternate Pin Availability TX RX 144 Pin 176 Pin 208 Pin A PD6 PD7 PD8 PD9 10 v
99. Posn PCB Legend Description J1 LINB M FITTED LIN B transceiver 1s configured for LIN Master mode J2 LINA M FITTED LIN A transceiver is configured for LIN Master mode J3 CAN A 1 2 TX MCU CNTX A is connected to CAN controller A 3 4 RX MCU CNRX A is connected to CAN controller A J4 CAN C 1 2 TX MCU CNTX C is connected to CAN controller C 3 4 RX MCU CNRX C is connected to CAN controller C J5 LINB EN FITTED The LIN B transceiver is enabled J6 LINA EN FITTED The LIN A transceiver is enabled J7 VDD CAN FITTED Power is applied to both CAN transceivers J8 RV1 FITTED Output from variable resistor RV1 is applied to MCU PAO J9 SCI PWR FITTED Power is applied to the MAX232 transceiver J10 SCI A 2 4 TXD MCU is routed via MAX232 to P5 1 3 RXD MCU is routed via MAX232 to P5 J11 SCI B 2 4 TXD MCU TXD B is routed via MAX232 to P6 1 3 RXD MCU RXD B is routed via 232 to P6 J12 Flex A REMOVED 3 shunts removed No MCU signals connected to Flexray 1 2 BGE Flexray A interface BGE signal is pulled to VIO J13 Flex A 3 4 EN Flexray A interface EN signal 15 pulled to VIO 5 6 STBEN Flexray A interface STBN signal is pulled to VIO 7 8 WAKE Flexray A interface WAKE signal is pulled to GND J14 Flex B REMOVED All 3 shunts removed No MCU signals connected to Flexray 1 2 BGE Flexray B interface BGE signal is pulled to VIO J15 Flex B 3 4 EN Flexray B interface EN signal is pulled to VIO 5 6 STBEN Flexray B interface STBN s
100. SSOdN 1224 7002 0 Jequieydag ad 8 01 552044 Og Lez HOS g JequnN jueunooq 2219 pueog OLSSOdW 1523 GoW eleoseaiy 8 0 5 G IE06LT1 ized AOJOSUuUOD NOILLVOI4IOSHdS HONVGHOOOUV on WHET S OTO6LT S 20 5 6006 1 5 dWV NI GHOVId LSAW SHYOLOANNOD 191701349 2 79 1910139 lt 61 lt 910199 2 7 lt 2 4 dwoor SNL T ipm nmi KKXLNO LSY 2299 SAL ae 300 gt A 2 I 021 29 ave gt EA gi yit SH ELL 4 zi am NGA ett or 80 40 801 201 90 901 HA 90 go SOL 70 zor 10 EOL H X oa car n Si en ea 1444 NASGGA 60 XOL Asad 801 204 XOL 90 SOL IL vol 20 8 18 0 08 64 62 tise e ue 92 SL vL L 9L y Fri nya
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104. ard crystal circuit EXTAL 2 3 EVB Clock is sourced from EVB clock oscillator or SMA The default configuration uses the local daughtercard clock If you wish to drive a clock into the MCU EXTAL line from the EVB either via the SMA connector or using the 8Mhz oscillator module move both the EXTAL and XTAL jumpers to position 2 3 4 2 3 32Khz Clock Configuration The 5510 supports an optional 32Khz oscillator circuit used to drive an RTC Real Time Counter The 32Khz clock circuitry is populated on the daughtercard with 2 jumpers to allow selection of the 32Khz oscillator if required User Connectors Local Crystal Circuit Y1 Figure4 4 Daughtercard 32Khz Clock Selection MCU EXTAL32 XTAL32 XTAL32 Table 4 3 Daughtercard 32KHz Clock Selection Jumper Position PCB Legend Description 1 2 D 4 MCU pin is routed to EVB user connectors XTAL32 2 3 MCU pin is connected to 32Khz crystal J2 1 2 D PF15 MCU pin is routed to EVB user connectors EXTAL32 2 3 MCU pin is connected to 32Khz crystal The default configuration has the MCU EXTAL32 XTAL32 pins connected to the MCU ports PortH or PortF depending on the package used If you wish to use the 32KHz crystal jumpers J1 and J2 must both be moved to position 2 3 MPC5510EVBUM D Page 26 of 36 Because of an order from the United States International Trade Commission BGA packaged product
105. d part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 7 2 Prototyping Area and User LED s Switches There is a rectangular prototype area on the EVB consisting of a 0 linch pitch array of through hole plated pads Power from all three voltage regulators is readily accessible along with GND This area is ideal for the addition of any custom circuitry Adapters are available to convert SMD devices to 0 linch pitch through hole Note the power supply lines to the prototype area are connected directly to the regulator outputs and not connected to the jumpered MCU supply There are 4 active low user LED s DS4 DS5 DS6 and DS7 These are driven by connecting a logic 0 signal to the corresponding pin on 0 1 header P10 user LED s There are 4 active high pushbutton switches SW2 SW3 SW4 and SW5 which will drive 5V onto the respective pins on 0 1 connector P11 when pressed The switch outputs are pulled to GND with a 10K resistor network MPCS5510EVBUM D Page 34 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 U
106. e 3 12 JTAG NEXUS Target Reset Routing Jumper Position PCB Legend Description JT AG reset signal is buffered to MCU RESET pin 5 connected to the MCU Reset In circuitry 2 3 DIRECT JTAG reset signal is connected direct to MCU RESET pin J31 JRST The default configuration connects the JTAG reset signal to the MCU reset via a buffer so the probe cannot monitor the reset If your debug probe has an open drain reset capable of monitoring the reset signal this can be enabled by moving jumper J31 to position 2 3 MPC5510EVBUM D Page 12 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 CAUTION If jumper J31 is positioned 2 3 and the debug probe actively drives the reset line high and low nothing else will be able to assert the MCU reset including the MCU itself 3 4 3 PFO Selection MCU pin PFO has alternate functions of EVTI debug control signal and R W To prevent conflicts between the external memory and debug interface jumper J31B is used to route PFO to either the debug connectors or the external memory as shown in the table below Table 3 13 PFO EVTI R W Function Selection J
107. e can be enabled by removing jumpers J1 J2 Flexray circuitry is located in the top edge of the 3 9 Flexray Configuration J12 J13 J14 J15 J1 6 J18 titled The EVB is fitted with 2 flexray physical interfaces connected to MCU flexray channels A and B Jumpers J12 and J14 are provided to route the respective MCU signals to the physical interfaces as described below Table 3 24 Flexray MCU Signal Routing Jumpers J12 J14 Jumper Position PCB Legend Description J12 Flex A FITTED TX MCU is connected to Flexray A transceiver TX Posn 1 2 REMOVED D MCU PC is not connected to Flexray A transceiver TX 12 Flex A FITTED TXEN MCU is connected to Flexray A transceiver TXEN Posn 3 4 REMOVED D MCU PC1 is not connected to Flexray A transceiver TXEN J12 Flex A FITTED RX MCU PC2 is connected to Flexray A transceiver Posn 5 6 REMOVED D MCU 2 is not connected to Flexray A transceiver J14 Flex A FITTED TX MCU is connected to Flexray B transceiver TX Posn 1 2 REMOVED D MCU 8 is not connected to Flexray B transceiver TX J14 Flex A FITTED TXEN MCU PC is connected to Flexray B transceiver TXEN Posn 3 4 REMOVED D MCU 9 is not connected to Flexray B transceiver TXEN J14 Flex A FITTED RX MCU PC7 is connected to Flexray B transceiver Posn 5 6 REMOVED D MCU 7 is not connected to Flexray transce
108. ed here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 7 User Connector Descriptions This section details the pinout of the EVB user connectors The connectors are 0 1 inch pitch turned pin headers and are located to the right hand side of the EVB Pins are grouped by port functionality and the PCB legend shows the respective port number adjacent to each pin Shaded GREEN areas represent pins that are shared with the Nexus port Shaded BLUE areas represent a GPIO pin that is also used on the EVB for another purpose Note that not all of the port functionality is available on all of the derivatives Please consult your particular MCU documentation for details on available ports 7 1 1 Port A ADC Connector P16 RV1 and J8 Table 7 1 Port A Connector Pinout P16 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PAO ANO 2 PAI ANI Y 3 2 AN2 Y 4 AN3 Y 5 4 Y Y Y 6 5 ANS Y Y 7 PA6 AN6 Y Y Y 8 7 7 Y Y 9 PA8 AN8 Y Y Y 10 PA9 AN9 Y Y Y 11 10 ANIO Y Y 12 Y 13 12 12 Y Y 14 PA13 AN13 Y 15 14 14 Y Y Y 16 15 15 Y Y Y 17 GND 18 GND 22
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111. eration of the code that is about to be loaded into RAM To prevent this occurring it is advised to either erase the internal flash or to prevent the MCU booting from flash by moving jumper J19 to position 2 3 ONCE and NEXUS 3 4 Debug Configuration connectors are located at the J24 J28 J31 J31B tefi hand edge of the EVB The EVB supports a standard ONCE cable with a 14 pin 0 1 walled header footprint There is also a 38 pin MICTOR connector for Nexus 2 debug Four generic jumpers are associated with both the ONCE and Nexus as detailed below 341 TCLK Configuration Some debug manufacturers specify whether the debug TCLK signal is pulled low or high Jumper J28 provides the ability to select whether TCLK is pulled to GND or 5V Table 3 11 ONCE NEXUS TCLK Termination Control PCB Legend 28 1 2 D 5V TCLK signal is pulled to 5 0V via 10K 2 TCLK PULL 2 3 GND TCLK signal is pulled to GND via 10K 2 Notes J28 is located to the right of the reset switch out with the ONCE Nexus connector area To achieve accurate low power current measurements TCLK should be pulled to GND 3 4 3 Reset Buffering Most debug probes only assert the MCU reset line but some also have the ability to also monitor the status of the reset line This is not possible when the reset signal is buffered so jumper J31 1s included to allow routing the debug reset signal direct to the MCU reset pin or via the EVB Reset In buffering Tabl
112. ges fall below a preset threshold level the LVI will assert the MCU reset line to prevent incorrect operation of the MCU or EVB circuitry The table below shows the approximate threshold voltages for each regulator Table 3 7 LVI Monitor Threshold Voltages Regulator Minimum Voltage Before MCU reset 5 0V Linear 4 45 5 0V Switcher 4 65V The LVI is powered from the 5 0V switching regulator and monitors the 5 0V linear using a 2 power fail monitor circuit LVI also provides a de bounced input for EVB reset switch SWI Jumpers are provided to disable either the main LVI reset out which affects the reset from the 5 0V switching regulator and from the reset switch or the power fail out circuit which only affects the reset from the 5 0V linear regulator If the switching regulator LVI is disabled the reset switch will not function Table 3 8 LVI Control Jumpers Jumper Position PCB Legend Description J20 FITTED D 5 0V switching regulator is monitored Reset switch active Posn 1 2 REMOVED MAIN 5 0V switching regulator is not monitored Reset switch Inactive J20 FITTED D 5 0V linear regulator is monitored Posn 3 4 REMOVED LINES 5 0V linear regulator 1s not monitored Notes Ifthe 5 0V switching regulator is disabled for any reason the LVI circuit will attempt to assert the MCU Reset signal Jumper shunts on jumper J20 position 1 2 and 3 4 must be removed in this situation Thi
113. h the Nexus debug port so the external memory cannot be used at the same time as Nexus Jumpers are provided as detailed in the following sections to enable the memory system and also to control the MCU chip select assignment and port size configuration Note that the 3 3V and 5 0V switching regulators must be enabled for the external memory system to function MPC5510EVBUM D Page 15 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 5 1 Memory Power Control J22 J32 The memory subsystem has components operating at 3 3V and 5 0V Each of these power domains has a separate power jumper as detailed below The SRAM devices and address latch buffers operate at 5 0V controlled by jumper J22 The PLD used to control the logic is powered from 3 3V with 5 0V tolerant I O This has a separate power jumper J32 Table 3 17 SRAM and PLD Power Control Jumpers J22 J32 Jumper Position PCB Legend Description J22 FITTED D The SRAM and address latches are powered enabled SRAM PWR REMOVED The SRAM and latches are not powered disabled J32 FITTED The control PLD is powered enabled GAL PWR REMOVED D The control PLD is not powered disabled
114. he routing of the relevant control signals depending on the selected port size Note that the SRAM does not supply a transfer acknowledge TA signal to the MCU at the end of a data cycle so the MCU external bus must be configured with auto TA acknowledge enabled Additional wait states may be required depending on the MCU bus speed See the relevant MCU reference manual for more details 5516 Mux d Address Demux d SRAM Address Data Latch Address A 3 29 G4Kx16 Upper Upper D 0 15 Address Latch Lower SRAM 13 29 64 16 Lower D 16 31 Naming Conventions Address A31 is LSB Data D31 is LSB SARAM A 15 30 64Kx16 Data Effectively D 16 31 Figure 3 8 External Memory Subsystem The MPC5510 family does not have an expanded mode of operation unlike other MCU families you may have encountered Instead the individual port pins must be switched to the correct mode of operation for the external bus The table below shows what MCU pins are required for correct bus operation in 16 bit and 32 bit port size modes Table 3 16 MCU pins required for EIM SRAM operation SRAM Port Size PortE Port F Port Port H Port J Configuraiton 16 Bit 6 0 1 9 10 11 12 13 14 15 0 15 32 Bit 6 0 15 0 15 14 15 0 7 Notes PE6 is the MCU CLKOUT pin which is required for the operation of the external memory PortF is shared wit
115. ignal is pulled to VIO 7 8 WAKE Flexray B interface WAKE signal is pulled to GND J16 Flex PWR REMOVED All 3 flexray power supply voltages are disconnected J17 RST IN FITTED External reset source can assert MCU reset J18 VIO 1 2 SY J19 BOOT CFG 1 2 FSH MCU boots from internal flash J20 1 2 MAIN 5 0V switching regulator is monitored Reset switch active 3 4 LINEAR 5 0V linear regulator is monitored J21 VDD15 REMOVED MCU VDD pin is not powered externally J22 SRAM PWR FITTED The SRAM and latches are powered 723 LED Enable 1 2 HIGH MCU PortC 10 11 signals are connected to LED Matrix 3 4 LOW MCU PortC 1 9 signals are connected to LED Matrix 724 VEND IO REMOVED Vendor I O2 pin can drive BOOTCFG at reset J25 VDDSYN REMOVED MCU VDDSYN pin is not powered externally J26 EIM Pullup FITTED The external bus pull up resistors are powered enabled J27 VDD33 REMOVED MCU VDD33 pin is not powered externally J28 TCLK PULL 1 2 5Y JTAG NEXUS TCLK signal is pulled to 5 0V via 10KQ J29 VDDE3 1 2 FRM J34 MCU VDDE3 is powered from output of J34 J30 VDDE2 1 2 FRM 134 MCU VDDE2 is powered from output of J34 J31 JRST 1 2 BUFFER JTAG reset signal is buffered to MCU RESET pin J31B PFO SEL 1 2 EVTI PFO is routed to Nexus for use as EVTI J32 GAL PWR REMOVED The control PLD is not powered disabled J33 VDDE1 1 2 FRM J34 MCU VDDE I is powered from output of J34 J34 VDDE SEL 1 2 5V S VDDEx jumpers are supplied from 5V switching regulator
116. instructions 1 0 September 2007 A Robertson Production EVB release Includes BOM and schematics for EVB 144QFP 176QFP and 208BGA daughter cards Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems
117. intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor other product or service names are the property of their respective owners Freescale Semiconductor 2007 Rights Reserved MPC5510EVBUM D i Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Ma
118. ion Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PDO A Y Y 2 PDI CNRX A Y Y 3 PD2 CNRX B Y Y 4 PD3 CNTX B v Y 5 Y v 6 PDS CNRXC Y Y 7 PD6 TXD A Y v Y 8 PD7 RXD A Y Y Y 9 PD8 TXD B Y Y 10 PD9 RXD B Y Y 11 PD10 PCS_B 2 Y Y Y 12 PDII PCS Y Y Y 13 PDI2 PCS B 0 Y v v 14 PDI3 SCK B Y Y Y 15 PD14 SOUT B Y Y Y 16 PD15 SIN B Y Y Y 17 GND 22222222 18 GND LMM Notes PD2 is used for BOOTCFG data See section 3 3 3 PDO PD4 and PDS are used for the EVB CAN interface See section 3 6 PD6 PD7 PD8 and PD9 are used on EVB SCI LIN Physical Interfaces See sections 3 7 and 3 8 PDI12 PD13 PD14 PD15 are used by the SBC SPI communication See section 3 1 5 7 1 5 PortE SPI eMIOS EIM Connector P31 Table 7 6 PortE Connector Pinout P31 Note Port has a series resistor close to the MCU on the MCU daughter card to provide some CLKOUT Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PEO PCS A 2 v v 2 PEI PCS Y v 3 2 PCS A 0 v Y v 4 PE3 SCK A v v 5 PE4 SOUT v v 6 PES SIN A 7 CLKOUT v v Y 8 PE7 9 eMIOS 24 v 10 PE9 eMIOS 25 Y 11 10 eMIOS 26 v v 12 eMIOS 27 v 13 PEI2 eMIOS 28 v 14 PEI3 eMIOS 29 v
119. ionality There is a lot of circuitry on the EVB that has access to the reset pin In order to reduce the loading on the MCU when driving the reset pin and also to allow connection of non open drain reset inputs a reset in and reset out buffering scheme is implemented as shown in Figure 3 6 Reset In There 3 possible external sources of reset JTAG Nexus connector reset User reset from user connectors reset circuitry including the reset switch Each of these reset sources is fed into the input of an AND gate and then converted to an open drain output which is directly connected to the MCU reset pin Reset Out The MCU reset pin is buffered to provide a reset out signal capable of driving the reset LED and also all other devices requiring a reset input The reset buffering scheme is detailed below note that the SBC also has an open drain reset in out that 1s connected directly to the MCU reset line Reset IN From JTAG Nexus Tri State Buffer From TGT From LVI Main From LVI Linear Reset OUT Reset OUT To RED Reset LED BDM Reset In external device reset Figure 3 6 EVB Reset Buffering Scheme Jumper J17 is used to completely disconnect the reset in buffering if desired This is for debug purposes only and should normally be left connected Disconnecting this jumper will mean no external MCU reset can be achieved Table 3 9 Reset Out Control Jumper Jumper Positi
120. ited States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 7126 EIM Connector PIT eee ie ee a oan heen 32 74 77 PortG EBIM Connector P25 3 nein ede petia ee th cane 32 7 1 8 Port H ADC API Connector 29 32 7 1 9 PortJ EIM SPI Connector 23 teens teens tette the teen sete ernst nennen 33 7 1 10 Port EXTAL32 XTAL32 Connector P33 sss 33 7 2 PROTOTYPING AREA AND USER LED S SWITCHES e enne ene n ene 34 8 DAUGHTER CARD CONNECTORS 9 22 4 1 4 1 110440 0 44 143 4 0 4 04 sesto seta tasse ness 02 0 35 APPENDIX Schematics and Bill of materials for EVB and Daughtercards Index of Figures and Tables FIGURE 1 1 MODULAR CONCEPT EVB AND MCU DAUGHTER CARDS 1 FIGURE 3 1 EVB FUNCTIONAL BLOCK te E ee Eee ere eae 3 FIGURE 3 2 2 IMM POWER CONNECTOR rette eec vetet ed tete 4 FIGURE 323 2 EEVER POWER CONNEGTOR reete ceti eee ee ee tese a res vet 4 FIGURE 324 POWER SUPPEY ROUTING 6 FIGURE 325 EV BiCrOCK SELECTION Tg ces ne gae NUOVO 9 FIGURE 3 6 EVB RESET BUFFERI
121. iver MPCS510EVBUM D Page 20 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 The power to the Flexray physical interface is controlled via jumper J16 to allow disconnection if required The Flexray physical interface is capable of interfacing with MCU I O voltages of 3 3V or 5 0V as defined by the voltage supplied to VIO via jumper J18 On the MPC5516 the MCU pad voltage is controlled by the voltage supplied to VDDE 1 3 The user must ensure that the voltage on the respective PortC pads is the same as VIO supplied to the flexray interface Table 3 25 Flexray Power Control Jumpers J16 J18 Jumper Position PCB Legend Description J16 Flex PWR FITTED 12V 12V Flexray circuitry is powered from main 12Vinput Posn 1 2 REMOVED D 12V Flexray circuitry is not powered J16 Flex PWR FITTED 5y 5V Flexray circuitry is powered from 5 0V switching reg Posn 3 4 REMOVED D 5V Flexray circuitry is not powered 16 Flex PWR FITTED VIO VIO Flexray circuitry is powered from J18 Posn 5 6 REMOVED D VIO Flexray circuitry is not powered J18 1 2 D 5V VIO is selected as 5 0V VIO 2 3 3 3V VIO is selected as 3 3V REMOVED No Power is app
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123. lators must also be enabled in this case When the internal voltage regulator is disabled and power is applied to VDDSYN VDD33 and VDD a ferrite bead on VSSSYN needs to be activated This is achieved by de soldering a zero ohm link on the bottom of the daughter card See section 4 2 1 for details Note that external regulator mode is not the intended mode of operation of the MCU and should be used for test purposes only MPC5510EVBUM D Page 7 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 1 6 1 VDDE 1 3 Voltage Groupings Before changing the VDDEx voltage from the default 5 0V setting you need to ensure that this will not impact any of the EVB peripherals that may be in use The table below details what EVB peripherals are tied to a particular VDDEx grouping and also the MCU pin operating voltage suitable for that peripheral Table 3 4 VDDE 1 3 Pad Groupings Item Port Pins VDDE Group Required Pad Voltage LED Dot Matrix Display PortC 0 11 VDDEI 5 0 3 3V PortG 0 15 VDDE2 External Memory deus i 5 0V PortJ 0 7 VDDE2 CANA and CANC PortD 0 5 VDDEI 5 0V SCI LIN A and B PortD 6 9 VDDEI 5 0V
124. lied to the VIO jumper J16 posn 5 6 The flexray interface has 4 pins which are used for configuration and are pulled high or low controlled by a jumper as described in the table below By default all of the jumper headers are fitted Please consult the Flexray physical interface specification before changing any of these jumpers Table 3 26 Flexray Control Jumpers J13 J15 Jumper Position PCB Legend Description J13 Flex A FITTED D BGE Flexray A interface BGE signal is pulled to VIO Posn 1 2 REMOVED Flexray A interface BGE signal is unterminated J13 Flex A FITTED D EN Flexray A interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray A interface EN signal is unterminated J13 Flex A FITTED D STBEN Flexray A interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray A interface STBN signal is unterminated J13 Flex A FITTED D WAKE Flexray A interface WAKE signal is pulled to GND Posn 7 8 REMOVED Flexray A interface WAKE signal is unterminated J15 Flex B FITTED D BGE Flexray B interface BGE signal is pulled to VIO Posn 1 2 REMOVED Flexray B interface BGE signal is unterminated J15 Flex B FITTED D EN Flexray B interface EN signal is pulled to VIO Posn 3 4 REMOVED Flexray B interface EN signal is unterminated J15 Flex B FITTED D STBEN Flexray B interface STBN signal is pulled to VIO Posn 5 6 REMOVED Flexray B interface STBN signal is unterminated J1
125. lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 4 2 4 CLKOUT Impedance Matching Control The MCU PE6 CLKOUT line has a series resistor close to the MCU in order to provide CLKOUT impedance matching If required this resistor can be shorted out bypassed by fitting a jumper header To minimise the effect of radiated emissions it is recommended this jumper is removed when is used for CLKOUT Table 4 4 Clkout Impedance Matchuing Jumper Position PCB Legend Description 5 FITTED MCU PE6 has no series termination CLKOUT DISABLE REMOVED D MCU has in line series resistor By default the jumper is removed to enable CLKOUT impedance matching To disable impedance matching fit the jumper CAUTION Fitting daughtercard jumper JS when CLKOUT is enabled on MCU PE6 will result in increased radiated emissions Ensure this jumper is removed when CLKOUT is active 4 2 5 Power LED There is a green power LED fitted to the top left corner of the daughtercard If the daughtercard is connected to the EVB and power is applied this LED should illuminate If the LED does not illuminate please check the daughtercard is installed correctly and follow the main EVB power fault finding tips detailed in section 3 1
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127. n car use if desired e Freescale System Basis Chip footprint to allow use of the SBC power supply if required available end 2007 Flexible on board power supply configuration with the option to bypass the internal MCU regulators for diagnostic purposes MCU power can also be sourced from either the EVB regulators or the SBC Master power switch and regulator status LED s User reset switch with status LED s User configurable LVI Low Voltage Inhibit device to monitor the status of the 5V regulators Control of the BOOTCFG status via a dedicated jumper Flexible MCU clocking options allow provision of an external clock via an SMA connector or 8Mhz EVB clock oscillator circuit Jumpers on the daughter card allow selection between these external clocks or the local daughter card ALC oscillator circuitry The MCU clkout signal is routed to an SMA connector for easy access e Standard 14 pin ONCE debug connector and 38 pin Nexus2 connectors e Twin 120 way polarised daughter card expansion connectors allowing connection of the MCU daughter card or a custom board for additional application specific circuitry of the MCU signals are readily accessible at a group of port ordered 0 1 pitch headers e Up to 256Kbytes of external SRAM memory which can be configured as either 32 bit or 16 bit data port width e SCI channels A and can be routed to either a standard DB9 female connector PC RS 232 compliant LIN inte
128. nal voltage regulators and supply 3 3V and 1 5V externally then a modification is required to the daughtercard to enable a ferrite bead on VSSSYN This is performed by de soldering a zero ohm link located on the underside of the board Table 4 1 VSSSYN Ferrite Control Daughtercard Zero Ohm link to remove 144QFP R6 176QFP R103 208BGA R6 CAUTION Please ensure that any solder modifications to the daughter cards are carried out in an anti static environment with the correct equipment and personnel for the job 4 2 2 Main Clock Configuration Each daughtercard contains a local crystal oscillator circuit and jumpers to allow the source of the clock to be selected from either the EVB or from the local crystal circuit Oscillator Module Y1 Figure 4 3 Daughtercard Clock Selection MPC5510EVBUM D Page 25 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Table 4 2 Daughtercard Clock Selection Sept 2007 Jumper Position PCB Legend Description J3 1 2 D 2 Clock is sourced from daughtercard crystal circuit XTAL 2 3 GND XTAL is grounded Use when J4 is in posn 2 3 J4 1 2 D Y2 Clock is sourced from daughterc
129. neoeg 2884 G INDOHAH9TSSOdIA 2002 Zi Jaquiaydes Aepseupew 9q 2612 3445 dQd ZELEZ HOS a 2215 2 2 NOW ran i GAAOLSSOdIN 10 98802 225994 2 E E E A EN angy 1 i o3e TWLXH LNOMTO NOW deey e L a pU NASSSA i sTeubts enbo eue 849 122 WIX pue NASQGA JAX TWIX lt NASSSA ILNSIOSPVLEWTS NASSSA oW 38000 tld d 6 43 our er 217 OLH 6H 8H ZH 019 69 89 49 va 9 38027 1459 802195 95504 tld SSA d SSA LN SSA VN SSA OLX SSA 6X SSA 84 SSA LASSA OLP SSA 6r SSA 8 55 4 55 OLH SSA 6H SSA 8H SSA LH SSA 0L9 SSA 69 SSA 89 SSA 4 55 La SSA 0 55 vLO SSA 0 55 Seo eaan AS SNId 38000 91 H 5 619 AG O I 390 7
130. nual Rev 1 0 Sept 2007 1 EET 1 1 1 MODULAR CONCEPT 1 2 FEATURES 0 2 3 CONFIGURATION S 3 3 1 POWER SUPPLY CONFIGURATION int rim ree mee meae D n rores 4 344 Power Supply Connectors iue eet ee ee e 4 3 L2 Power Swith eei e tee rdum ete ederent 4 3 1 3 Regulator Power Jumpers J42 J44 J45 and J46 sess 5 3 1 4 Power Status LED s and Fuse isses eerie nennen teet entretien een rennen enne nennen 5 SLX SBC Power Jumper ie e tta cedet b oe e n e ee 5 3 1 6 Supply Routing and Jumpers J21 J25 J27 J29 J30 733 734 736 737 738 6 3 1 7 EVB Circuitry Power Domains eig eed eene E EAE E EEA T eren en 8 3 2 MCU CLOCK CONTROL 139 4 iter ette tese E ee ceeds 9 3 24 ClockSelecti n su siii oo Re dee dae 9 3 3 RESET CONTROL JUMPERS J17 J19 J20 SW 1 nnne entere nennen nennen 10 IIL ReRe LEDS E Em 10 3 382 Reset B ffering Sehem d aeter acd satan tiet eee den EAS 11 3 3 3 Reset Boot Configuration 19 e
131. oddy OT Ady enuen SN HAH9TSSOd A 802 sjonpoud XLGGOdW 0LOZ oj sajejs y Jo 10 4 jou eJeu pejeoipur ped pue saul yonpoud peBexoed yog uoissiuuo jeuoneuJeju paun 94 JepJo ue esneoeg 2002 71 Jequiaydas AepseupeAw LELEZ AdS 4dd LELECHOS JequinN jueuno2og zi NOW SA30LSS2 dW 10 p129 nu Buweig JOj2npuoonues 1 5 1910139 NnoN OI NON OLSSDdIN 005 1dos 128 2884 SL NV 3 4 XHNO 8L NV 6 3 XLNO olv 0 4 4 zz Nv 3 vw ezNv 3 zl viw rz Nv ez so we zHd selNv zz lsowe 9z Nv v vas lozlso ie v 105 Lelay v NIS loelav v 1nos lezlav v 705 19 gzlav olv sod sod orod lezlav zlv Sod _ 69d szlav soa 0 sSod rzlav r lv Sod 29 lezlav ez so we 2 99 zzlav zz so we Sod zlavy Lzlsome vod lozlav ozlsoiwe 012 sod 9d 6
132. ollows LED DS10 Indicates that the 5 0V linear regulator is enabled and working correctly LED DS11 Indicates that the 1 5V switching regulator is enabled and working correctly LED DS12 Indicates that the 3 3V switching regulator is enabled and working correctly LED DS13 Indicates that the 5 0V switching regulator is enabled and working correctly Ifno LED s are illuminated when power is applied to the EVB and the regulators are correctly enabled using the appropriate jumpers it is possible that either power switch SW6 is in the OFF position or that the fuse F1 has blown The fuse will blow if power is applied to the EVB in reverse bias where a protection diode ensures that the main fuse blows rather than causing damage to the EVB circuitry If the fuse has blown check the polarity of your power supply connection then replace fuse 1 with a20mm 500mA fast blow fuse 3 1 5 SBC Power Jumper J41 The optional SBC System Basis Chip regulator has a single power supply input jumper as detailed in the table below By default the SBC is disabled For more details on the SBC regulator see Figure 3 4 below Table 3 2 SBC Power Jumpers Jumper Position PCB Legend Description FITTED SBC linear regulator output is Enabled J41 SBEC PWR ar MOVED D SBC linear regulator output is Disabled Note the SBC will not be available until the end of 2007 so it will not be fitted on an EVB manufactured prio
133. on PCB Legend Description External reset source LVI Debug or Target will be able J17 RST IN to assert MCU reset REMOVED External reset is disabled Not recommended MPC5510EVBUM D Page 11 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 3 3 Reset Boot Configuration J19 The 5510 has a single boot configuration pin BOOTCFG which determines the boot location of the MCU based on the state of the pin at POR Power On Reset This is shown in the table below Table 3 10 BOOTCFG Control Jumper Position PCB Legend Description 1 2 D FSH MCU boots from internal flash CES 2 3 SERIAL MCU boots from external serial source Note there have been some problems observed when application code is present in flash and an attempt is made to load and execute a different application from internal RAM Depending on the configuration and speed of the debugger used it is feasible that the application code in flash will already have started to execute by the time the debugger gains control This has implications if the flash code has already done some configuration of the device that is in conflict with the op
134. product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 TABLE 3 24 FLEXRAY MCU SIGNAL ROUTING JUMPERS 712 114 20 TABLE 3 25 FLEXRAY POWER CONTROL JUMPERS 716 118 21 TABLE 3 26 FLEXRAY CONTROL JUMPERS J13 J15 nennen rne enne 21 TABLE 3 27 FLEXRAY PIN AVAILABILITY ccccecsscccececsesssececececsesssuececececsesssaesecececsensssseeececseneaaesecececeesesaaeseeeesesentsaeeeeess 21 TABLE 3 28 LED MATRIX CONTROL cccccccccccssssssscecececsessssececececeeusuececececsessasececececsensasseeeececseseuaesececsceeseaaaeseeecsesenssaeaeeees 22 TABLE 3 29 EIM PULLUP RESISTOR CONTROL 726 nennen 23 TABLE 4 1 VSSSYN FERRITE CONTROL ccccsessssecececesssssececececeeseseceeececsesssuececececsenessseeececeeseassesecscsesensaeeeesesesennsaeaeeess 25 TABLE 4 2 DAUGHTERCARD CLOCK SELECTION ccecesssssececececeessaececccecsesesaececccecsesesesesececseseassececscseneaaeeeeecsesensaaeeeeees 26 TABLE 4 3 DAUGHTERCARD 32KHZ CLOCK SELECTION eese ense enhn enne ete nnn ness stent rn nasse eter trennen 26 TABLE 4 4 CLKOUT IMPEDANCE MATCHUING eene enne
135. ptember 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 1 3 Regulator Power Jumpers J42 J44 J45 and J46 The Power supply control jumpers are located adjacent to the respective regulators As mentioned above the EVB has four voltage regulators on board 1 5 switching regulator 1020 to supply the MCU Core voltage when the MCU on chip regulator is disabled 33V switching regulator U21 for EVB peripherals and MCU logic when the on chip regulator is disabled 5 0 switching regulator U22 for the MCU regulator and I O and EVB peripherals 5 0V linear regulator U19 for the MCU ADC power supply of the regulators have the option of being disabled if they are not required The table below details the jumper configurations for enabling and disabling the regulators By default all of the regulators are enabled Table3 1 Regulator Power Jumpers Jumper Position PCB Legend Description HIGOVLINEAR ENABLE 5 oy tinea regulator output is Disabled mo REMOVED DISABLE sy switching regulator output is Enabled REMOVED D PISABLE 3 3y switching regulator ouput is Enabled 16500 REMOVED m DISABLE Soy switching regulator output is Enabled 3 1 4 Power Status LED s and Fuse When power is applied to the EVB four green LED s adjacent to the voltage regulators show the presence of the supply voltages as f
136. r to the SBC release date MPC5510EVBUM D Page 5 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 MCU power supply jumpers are located in the 3 1 6 MCU Supply Routing and Jumpers ee EUR guns J21 J25 J27 J29 J30 J33 J34 J36 J37 J38 The MCU has internal regulators to generate the 3 3V and 1 5V supplies for VDDSYN VDD33 VDD Whilst this is the intended mode of operation for the MCU the EVB allows the internal MCU regulators to be disabled by disconnecting VDDR and applying external voltages to the VDDSYN VDD33 and VDD pins via jumpers J25 J27 and J21 respectively The VDDE 1 3 pins control the pad voltages over 3 groupings of pads see the MCU reference manual for details Jumpers J29 J30 733 and 134 allow the VDDEx pins to be connected to the 5 0v or 3 3V switching regulators or to the SBC auxiliary output which can is software selectable between 5 0V and 3 3V Each of the main supply pins VDDA VDDR VPP and VDDEx has the option of being routed from either the EVB regulators where VDDA has a dedicated linear regulator to ensure a accuracy or from the SBC MCU Power 5V Linear 1 VDDA EN SBC MAIN CAN Supply
137. rface header 0 1 both will full physical transceivers the SBC provides an additional 2 LIN interfaces e MCU FlexCAN channels A and C can be routed to 0 1 headers via a Philips high speed CAN transceiver The SBC provides an additional CAN physical interface 7x5 LED dot matrix display connected to the MCU eMIOS PWM channel 0 11 via 16244 buffer driver e User prototyping area consisting of a 0 1 grid of through hole pads with easy access to the EVB ground and power supply rails 4 active low LED s and 4 small pushbutton switches are adjacent to the prototype area e Jumper selectable variable resistor connected to ATD channel 0 driving between VRH and e Liberal scattering of GND test points surface mount loops placed throughout the EVB Note to alleviate confusion between jumpers and headers all EVB jumpers are implemented as 2mm pitch whereas headers are 0 linch 2 54mm This prevents inadvertently fitting a jumper to a header IMPORTANT Before the EVB is used or power is applied please fully read this user manual Failure to correctly configure the board may cause irreparable component MCU or EVB damage MPC5510EVBUM D Page 2 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208
138. s and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 7 1 9 Port J SPI Connector P23 Table 7 10 Port J Connector Pinout Sept 2007 Pin Function Availability Pin Function Availability GPIO 1 Alt 144 176 208 GPIO 1 Alt 144 176 208 1 PJO AD 0 Y 2 Y 3 2 2 4 PJ3 AD 3 Y 5 4 AD 4 Y Y 6 5 AD 5 Y Y 7 PJ6 AD 6 Y 8 7 Y Y 9 PJ8 PCS D 4 Y 10 9 PCS D 3 Y Y 11 PJ10 PCS D 2 Y Y 12 PCS 1 Y Y 13 PJ12 PCS D 0 Y Y 14 PJ13 SCK_D Y Y 15 4 SOUT_D Y 16 5 SIN_D 17 22222222 18 GND Note PJ 0 7 are used to drive the EBI 32 bit data port mode See section 3 5 7 1 10 Port EXTAL32 XTAL32 Connector P33 Table 7 11 Port K Connector Pinout Pin Function Availability Pin Function Availability GPIO 1 Alt 100 144 208 GPIO 1 Alt 100 144 208 1 PKO EXTAL32 2 EXTAL32 Y 17 GND 18 GND Note The EXTAL32 and XTAL32 function is available on pins 14 and 15 for all packages that do not provide PortK MPCS5510EVBUM D Page 33 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines an
139. s on the resistor to change For flexibility the CAN transceiver I O is connected to a standard 0 1 connector at the top edge of the PCB Connector P3 provides the CAN bus level signal interface for CAN A and connector P4 for CAN B The pinout for these connectors is shown below LOW GND Figure 3 10 CAN Physical Interface Connector Each of the MCU signals to the CAN transceivers is jumpered allowing the transceiver to be isolated if the respective MCU pin is not configured or used for CAN operation There is a 2x2 jumper for each CAN channel one for Rx one for Tx as shown in the table below The Global power jumper J7 physically removes power from both CAN transceivers Table 3 19 CAN Control Jumpers J3 J4 J7 Jumper Position PCB Legend Description J7 FITTED D Power is applied to both CAN transceivers VDD CAN REMOVED No power is applied to CAN transceivers J3 CAN A FITTED D TX MCU 15 connected to CAN controller A Posn 1 2 REMOVED MCU is NOT routed to CAN controller J3 CAN A FITTED D RX MCU is connected to CAN controller A Posn 3 4 REMOVED MCU CNRX A is NOT routed to CAN controller J4 CAN C FITTED D TX MCU CNTX C is connected to CAN controller C Posn 1 2 REMOVED MCU CNTX C is NOT routed to CAN controller 24 FITTED D RX MCU CNRX C is connected to CAN controller C Posn 3 4 REMOVED MCU CNRX C is NOT routed to C
140. s will also leave the reset switch SW1 inoperative Ifthe 5 0V linear regulator is disabled the shunt on jumper J20 position 3 4 must be removed to prevent the LVI asserting reset 3 3 1 Reset LEDs There are two reset LED s DS1 AMBER and DS2 RED placed adjacent to the EVB RESET switch to indicate the RESET status of the EVB and MCU LED 052 titled RST will illuminate if the MCU itself issues a reset In this condition LED DS1 will not illuminate LED DSI titled USR will illuminate when one of the following external hardware devices issues a reset to the MCU circuitry either an under voltage detection or the reset switch is pressed There is a reset being asserted from the user connectors or from the daughter card There is a reset being driven from the Nexus or JTAG debug probe Note that LED DS2 MCU Reset will also illuminate during an external user reset MPC5510EVBUM D Page 10 of 36 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 3 2 Reset Buffering Scheme The 5510 family has a single reset pin This single pin functions as a dual purpose input output signal providing Reset In and Reset Out funct
141. ser Manual Rev 1 0 8 Daughter Card Connectors P9 P22 As mentioned previously there are two 120 way expansion connectors fitted to the EVB allowing connection of an MCU daughter card or another board providing functionality enhancement The part numbers of possible connectors are detailed in Table 8 1 below Table 8 1 Expansion Connector Part Numbers Connector Location Height Pitch TYCO AMP Part Number EVB 8mm 0 8mm 179031 5 9mm 0 8mm 5 179009 5 13mm 0 8mm 5 179010 5 The pinout of the expansion connectors is detailed below for reference Table 8 2 Daughter Card Connector 1 Pin Signal Signal Number Name Name 0dd Even 1 2 12 3 13 5 7 9 11 13 PB13 PKI GND 19 PB4 PBO 21 15 PAII 23 GND PA9 25 PA6 7 27 5 29 14 GND 31 10 33 4 5 35 GND MCU RST 37 PAO 39 PAI PA2 41 PH10 GND 43 11 12 45 PH13 PJ13 47 GND PJ14 49 PH9 PJ15 __ wDDEZ 53 55 12 PH8 57 PJ10 5 59 GND PH6 MPC5510EVBUM D Pin Signal Signal Name Number 094 Even 61 PH7 PH3 63 PH4 8 65 9 69 PHI 7l GND PH2 73 PG12 PG13 75 PG14 15 77 PF8 GND 79 12 15 81 83 GND PG9 85 PG10 PG11 87
142. tional Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010 MPC551x products in 208 MAPBGA package 5510 User Manual Rev 1 0 Sept 2007 3 4 5 Debug Connector Pinouts The EVB is fitted with 14 pin JTAG ONCE and 38 pin Nexus 2 debug connectors The following diagram shows the 14 pin JTAG ONCE connector pinout 0 1 keyed header VSS VSS VSS 8 N C 10 TMS 12 VSS 14 JCOMP Figure 3 7 5510 JTAG ONCE Connector The Nexus module used on the MPC5510 family uses the JTAG pins for control of the Nexus block along with additional Nexus pins for trace messages Nexus mode is entered by a sequence whereby the Nexus EVTI pin is sampled on the rising edge of the TRST pin If the EVTI is asserted on TRST Nexus is enabled The table below shows the pinout of the 38 pin MICTOR Nexus connector for the 5510 Table 3 15 NEXUS Debug Connector Pinout Pin No Function Connection Pin No Function Connection 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Vendor I O 0 6 CLKOUT MCU PE6 7 Vendor I O 2 BOOTCFG 8 Vendor I O 3 9 Reset CCT 10 EVTI MCU PFO 11 TDO MCU TDO 12 VREF P5V 13 Vendor I O 4 14 15 TCLK MCU TCK 16 MDO 7 MCU 11 17 TMS MCU TMS 18 MDO 6
143. umper Position PCB Legend Description 1 2 D EVTI MCU PFO is routed to the ONCE Nexus debug connector TRATOR 2 3 RW MCU PFO is routed to the external memory system The default configuration connects PFO to the debug connectors to act as EVTI If the external bus is to be used then J31B must be moved to position 2 3 to route PFO to the memory subsystem as the R W signal Note EVTI is optional for ONCE debug and generally not required so with the jumper configured in position 2 3 to enable RW a ONCE debug session can still be established 3 4 4 Vendor I O Configuration Some Nexus debug probes can use the Vendor I O2 signal to drive BOOTCFG reset configuration data at reset The EVB 15 designed such that this will over ride any BOOTCFG data supplied by jumper J19 see section 3 3 3 A jumper is supplied to allow this feature to be enabled if desired Table3 14 Vendor I O2 Drive Control Jumper Position PCB Legend Description J24 FITTED Vendor I O2 pin disconnected VEND IO REMOVED D Vendor I O2 pin can drive BOOTCFG at reset By default the debug tool will not have the ability to over ride the EVB BOOTCFG settings and 124 will be removed To enable this feature fit Jumper J24 Note Be careful when fitting jumper J24 as this will override the EVB BOOTCFG setting when a nexus probe is fitted to the EVB MPC5510EVBUM D Page 13 of 36 Because of an order from the United States Interna
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