EDP-AM-AN16 Analog Input Applications Module User Manual
Contents
1. Jp301 2 Jp309 2 lt 1 312 1 2 lt 1 314 1 2 lt 1 308 2 lt 1 310 3 9 1 311 2 lt 1 313 2 lt O 1 201 2 Q 1 202 2 Q 1 203 2 JP205 2 lt Q Q 2 5 Q w13 5v 2 S s Q an 5V 12C Data lt 5 5 I2C CLK 3 3Vref 5 0Vref 126 bus can only read inputs ANO_5V to AN11_5 Block diagram of the Analog Module showing capability and basic link options Normally ANO_5V to AN15_5V are used for the raw analog inputs The processed analog signals are passed to the MCU via the backplane on ANO AN15 or redirected into the on board ADC for reading via an 12C chip With this implementation a total of 16 analog inputs are available the first 12 of which are readable via 12C You can also see that the analog ground VAGND and the digital signal ground SGND can be connected via a zero ohm link This link is normally left open as the same link is available on the CPU modules The CPU modules should normally use this option to connect the two grounds Most of the Electrocomponents plc Page 5 EDP AM AN16 Manual RS CPU modules should have this feature but check the circuit diagram and mapping aids on the respective CPU Modules The an2. E eg Q 100 lt LILI e BO R214 Lil R219 1 C206 1 R221 e e Cmm OO OF Hide C21 031 i 9315L 1 320L 11 P102 D
3. ASCO DTR SPI SSC CLK USB DEBUG D USB DEBUG D ASCI RX TTL ASCO DSR MOTOR POL USB DEBUG D USB DEBUG D SPI SSC CS NSS MOTOR POH CNTRL SPI CLK CNTRL SPI CLK ETH TX MOTOR PIL CNTRL SPI MRST CNTRL SPI MRST ETH TX MOTOR CNTRL SPI MTSR CNTRL SPI MTSR ETH RX MOTOR P2L CNTRL SPI CS NSS CNTRL SPI CS NSS ETH RX MOTOR P2H CNTRL I2C SDA CNTRL I2C SDA ETH LNK LED MOTOR PWM CNTRE I2C SCL CNTRL I2C SCL ETH RX LED EMG TRP USB HOST D USB HOST D ETH SPD LED MOTOR H0 ENCO USB HOST D USB HOST D 106 GENI SDA MOTOR H1 ENCI USB DEV D USB DEV D PC GENI SCL MOTOR H2 ENC2 USB DEV D USB DEV D CANI RX MOTOR TCO FB CANHO CANHO CANI TX gt 3V3BAT CANLO CANLO VCC CM lt gt VCC_CM VCC CM lt gt VCC_CM 3V3 lt gt 3V3 3V3 lt gt 3V3 5V lt gt 5V 5V lt gt 5V SGND SGND SGND 00 SGND gt T ic Tyco Amp 100 Way eld IEEE es 12VGND 139 140 12VGND Tyco Amp 140 Way Checked By Title Hitex UK Ltd EDP Connectors Sir William Lyons Road hite Size Number Revision University of Warwick Science Park i X Approved By A3 EDP AM AN16 Arl Arl Coventry MEVELOPMERN T TOD 5 Date 23 04 2008 c Hitex UK Ltd Sheet 1 of 3 File E PCB Designs DXP EDP AM AN16 EDP AM AN16 A Module Connectors 1 SchDoc Author A Davison 1 2 4 5 6 p 8 R201 R202 AN8 5V VAGND VAGND R204 R205 AN9 5V ANS 19201 3 way Jumper
4. C C R230 M S8 SI OCO go C QIO QIO R3OZLILIRSZZLIL Sg R306 R32 0O S S ck ele O N E CB301 z C302 Y Y mE R342 R357L1L1 9 118343 R314 1L amp 328 t IL R326 a Y aa PRG R354 LII RS340 O 40 00 Cmm imm 00 08 O O M MB 6023111 mit Tt 0122 VOEG PEE io Qos 90 SERS SEE LLL CL II e GE 9 E
5. EDP AM AN16 Manual RS Buffered Analog Channel Response 5V CPUs 1000 00 900 00 3 a SS 800 00 c 700 00 7 o 9 600 00 c amp 500 00 2 400 00 Decimal Value 300 00 E 20000 Q 100 00 0 00 0 1000 2000 3000 4000 5000 6000 milliVolts Applied To ANO AN7 1 5 2 Channels AN8 AN15 These are un buffered but still have over voltage protection The usable range is determined entirely by the characteristics of the ADC used Electrocomponents plc Page 8 EDP AM AN16 Manual RS 1 6 Analog Module Hints For best performance when using the CPU s own ADC i e least noise and greatest conversion accuracy ensure that the analog module is placed in the EDP baseboard position immediately adjacent to the CPU module Also solder bridge J301 can be closed to ensure that the analog ground is connected to the system ground SGND on the analog module rather than on the CPU module However to avoid ground loops though the link on the CPU module that connects these two grounds must be opened XC167 only Electrocomponents plc Page 9 1 2 3 4 5 6 y 8 Module Position 1 EDPCONI IO Connector P101 AN REF ANO ANI AN2 AN3 ANA ANS AN6 AN7 ANS ANIO ANII ANI2 ANI13 ANI4 5 VAGND GPIO0 GPIO VAGND GPIO2 MCIDATO GPIO3 GPIO4 MCIDATI GPIOS DSTX WS EDPCON2 Bus Cont
6. the on board ADC is available on a connector meaning a total of 16 plus 12 i e 28 channels are possible Two analog modules may be fitted simultaneously If this is the case the 16 analog channels which are fed directly down the backplane to the ADC on the MCU have to be allocated to each of the two modules respectively but the 12 additional ADC channels present on each of the AMs can be read independently giving a total of 16 plus 12 plus a second 12 i e a total of 40 channels If a second module is fitted the channels belonging to the CM remain the same although the user can specify which channel will be routed through which analog module The second analog module must use the second l2C channel I2C_GENO as the MAX1138 ADC has a fixed I2C address An alternative version of this device MAX1138KEEE has a different I2C address and can be fitted to the second module if required The on board ADC is by default the MAX1138 5V 10 bit ADC but the alternative MAX1139 3V3 device can be fitted The CM analog channels have a voltage range determined by the CPU fitted The analog module inputs are able to cope with a 0 5 range regardless of the CM type fitted It is therefore up to the user to ensure that the voltage applied to the inputs does not exceed that required by the CM A series protection resistor may optionally be fitted to reduce the chance of damaging a 3V3 ADC if 5V is applied The 5V and 3V3 precision references can be applied to t
7. 4 5V InF CB303 ju 5V 100nF J1X2 N R308 amp SGND Fit Zero Ohm Link OR U303A R309 R310 J308 C306 3 a UAE OPE Solderlink 12K 2 po P i i i 313 2 2 2n2F e I2C ANA 820R S S Z o lt z 5 2 VAGND R314 C308 1K6 100pF ANI 5V C309 U301B VAGND VAGND Fit Zero Ohm Link f 315 LPV324MT NOPB ANS 5V InF OR R316 R317 5 J 7 R318 U303B D303 e 6 d 1309 Fit Zero Ohm Link OR R320 R321 LPV324MT NOPB 1310 Iderlink i 6V2 A7nF P302 qo derli a gt 7 R323 2 Solderlink mr rene 12K gt EE way Jumper D304 C311 j 2 R326 VAGND VCC CM 6V2 2n2F F DC ANS ES C312 VAGND R328 C313 100pF 1K6 100pF C314 VAGND VAGND VAGND VAGND AN6 5V InF U303C C315 R330 LPV324MT NOPB Fit Zero Ohm Link OR ro R331 RU 13 z gt R333 olderli AN2 5V InF DK gt 8 T AN6 R U301C Pg C316 d E R336 LPV324MT NOPB 2n2F e I2C AN6 820R Fit Zero Ohm Link OR R337 R338 13 i 8 2 aa 2 VAGND li 340 C317 OI OR 1K6 100pF 6V2 C318 f 342 C319 2n2F e RC AN2 820R VAGND VAGND AN7 5V InF VAGND ll 343 C320 100pF C321 Dy R344 U303D Fit Zero Ohm Link OR LPV ZAM TADEN R345 R346 J313 VAGND VAGND aml 12 a R347 Solderlink AN3 5V InF DK M Sui mm 2 AN7 U301D Pod C322 OR R350 LPV324MT NOPB 2n2F e RC AN7 820R Fit Zero Ohm Link OR R351 R352 13 AN3 VAGND R354 C323 12K 13 1K6 100pF 6V2 2n2F DC AN3 VAGND VAGND Checked By Title Hitex UK Ltd VAGND li 3
8. 57 C325 Analog Module 2 Sir William Lyons Road hite 1K6 100pF Size Number Revision University of Warwick Science Park E X ES Approved By A3 EDP AM AN16 Arl Arl Coventry DFVFIOPMENT TODOIC Date 23 04 2008 c Hitex UK Ltd Sheet3 of 3 VAGND VAGND File E PCB Designs DXP EDP AM AN16 EDP AM AN16 A Analog2 SCHDOC Author A Davison 5 6 7 8 u202 LLLI e gt OO QU OU imm Sis exe OO Hr R213 6 is B R222 sels S9 im HB Loc ES E
9. CPU AN1 or MAX1138 AN1 enable 5V to 3V3 scaling for CPU AN1 J307 Create 4 pole active filter J312 Route AN2 5V to CPU AN2 or MAX1138 enable 5V to 3V3 scaling for CPU AN2 J303 Enable shutdown mode for AD5263 Default 2 3 J314 Route AN3_5V to CPU AN3 or MAX1138 AN3 enable 5V to 3V3 scaling for CPU AN3 RAL a CORE 326 aah D J310 Route AN5_5V to CPU AN5 or MAX1138 AN5 enable 5V to 3V3 scaling for CPU ANS C EH J308 Route AN4_5V to CPU AN4 or MAX1138 AN4 enable 5V to 3V3 scaling for CPU AN4 edit J311 Route AN6_5V to CPU or MAX1138 enable 5V to 3V3 scaling for CPU y EE P oO J313 Route AN7_5V to CPU AN7 or MAX1138 AN7 enable 5V to 3V3 scaling for CPU AN7 His 5 c amp em 9801 Connect local VAGND to SGND on module rather on CPU module NO P202 5V analog inputs to gt CPU ADC or MAX1138 ied P201 Power supply to ratiometric sensors P202 Analogue Input Connector
10. Embedded Development Platform EDP AM AN16 Analog Input Applications Module User Manual This document contains information on the AN16 analog input module for the RS EDP system Version v5 0 10 06 2010 EDP AM AN16 Manual Contents 1 Analog Input Module 1 1 Anti Aliasing Filters cccccecceeeeeeeeeeeeeeeceeeeeeaeeeeeeeseeeesaeeesnaeeneaes 1 2 Additional Items uiii d Ginnie Ro cat done 1 3 Setting Jumper Options ssssssssseeeeeenneen enn 1 3 Software Drivers For Analog 1 4 Mapping Of CPU Peripheral Pins To The Analog Module 1 5 Analog Module Input Characteristics ssssssssss 1 5 1 Channels ANO AN7 cccccccsscecececescecseseeaececeeeeeesssaeaeceeeeeeeenseaees 1 5 2 Channels AN8 AN15 1 6 Analog Module Hints Electrocomponents plc Page 2 EDP AM AN16 Manual RS 1 Analog Input Module The EDP AM AN16 A analog module allows up to 32 analog channels to be interfaced to the CM CPU Module or Command Module It has a mix of filtered and unfiltered inputs and two precision voltage sources for accurate absolute measurements The on board MAX1138 ADC is accessible via 20 CNTRL bus and gives up to 12 extra channels of 10 bit analog to digital conversion Each of the first 12 channels can be routed via jumpers to either the CM s own ADC or to the on board ADC In addition any unused channels on
11. V3 scaling for CPU AN7 1 2 J314 Solder Route ANS 5V to CPU AN3 or MAX1138 ANS enable 5V to 3V3 scaling for CPU AN3 1 2 J201 4W Link Select source for MAX1138 REF Open JP201 Link Select ADC for AN8 5V input 1 2 JP202 Link Select ADC for 5V input 1 2 JP203 Link Select ADC for AN10_5V input 1 2 JP204 Link Select voltage for VAREF 1 2 JP205 Link Select ADC for AN11_5V input 1 2 JP206 Link Select source for AN15 input 2 3 JP301 Link Select ANO_5V or pot as ANO input 1 2 JP302 Link Select 5V or LDR as AN1 input 1 2 P201 2 way Power supply to ratiometric sensors NC Electrocomponents plc Page 4 EDP AM AN16 Manual RS The locations of the most important user selectable items are shown below lt P203 Direct 5V analog input pu i to MAX1138 JP204 Select voltage for VAREF c TY 7 JP206 Select source for AN15 L35 JP202 Select ADC for AN9 5V 30202 Sas JP201 Select ADC for ANB 5V gt 186 6 EB JP205 Select ADC for AN11_5V rxe T JP203 Select ADC for ANTO 5V gt J202 Set voltage for MAX1138 ADC JP302 Select AN1_5V or LDR as AN1 input JP301 Select ANO 5V or pot as ANO input J205 Set 12C channel J204 Set 12C channel J305 Set AD5263 12C address ADO J306 Set AD5263 I2C address AD1 J302 Route ANO 5V to CPU ANO or MAX1138 ANO enable 5V to 3V3 scaling for CPU ANO J309 Route AN1 5V to
12. alogue board is capable of producing a very stable voltage reference signal This signal can be passed down the backplane as required to other modules The CPU modules for example can use this as a reference for their on board ADC s The AM is fitted with both a 3 3V and 5 0V voltage reference source The user selects between them as shown in the diagram Some CPU Modules can output their own reference on to the backplane also so the user must also check for contention on this signal line The on board ADC and the digital potentiometers present on the AM can be controlled via 12C Normally the user would use the CNTRL_I2C bus option rather than the 20 GENO bus option The 20 GENO bus is provided as a secondary 12C interface for the customers own I2C network Not all CPU Modules can support the second 12C bus The drawing is from a Mapping Aid document which is provided for each of the CPU Modules 1 3 Software Drivers For Analog Module The module has two 20 devices both of which require special software drivers to access The software drivers are provided for the CNTRL_I2C bus for each of the Command Modules currently in production The software drivers allow for the easy access to the resources available on this Application Modules As each piece of software is different for each of the CMs you will need to refer to the software pack for each of these CMs for more details 1 4 Mapping Of CPU Peripheral Pins To The Analog Module The analog m
13. derlink 2 PCA9306DP1 DC GENO SCL R237 VAGND VAGND en C213 100nF JP206 ZAREE 3 way Jumper SGND 2 5 O J206 5 5V J1X2 en C214 InF VAGND VAGND Checked By Title Hitex UK Ltd Analog Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park lt Approved By A3 Arl Arl Coventry DEVELOPMENT TOOIC Date 23 04 2008 c Hitex UK Ltd Sheet2 of 3 File E PCB Designs DXP EDP AM AN16 EDP AM AN16 A Analog1 SCHDOC Author A Davison 1 2 4 5 6 y 8 ll 9 4 3 6 n 8 C301 45V A U302 22nF 7 Bi z z Option to connect VAGND to SGND CB301 EM 3X Al o z on Analog AM rather than CM Normally Open C302 100nF EM 3 O WI dA z 2 gt E 5V 5V 10uF 10V 18 A NL i 24 es SGND ao 1 ANO 5V CB302 p EM W2 100nF VAGND SGND TOV S DC VDD 10 EM 4 Fit Zero Ohm Link il 301 SGND EN 5 OR T U301A J303 D SCL 5V 12 B EM c ww 3 LPV324MT NOPB Solderlink E SPEI gt DK 1 SDA 5V 1 z A 21 T is 1 20 6V2 C303 R358 RC VDD 9 a W4 47nF JP301 4 100K in 3 way Jumper UTERE p m E AD5263BRU50 VAGND en I2C ANO SGND RC VDD m RC VDD VCC_CM Solderpad 1304 C304 J305 2 2 1306 VR301 100pF Solderlink Solderlink 10K Place pad near edge of board en en VAGND VAGND SGND C305 5V SGND VAGND Allow a 4 pole filter AN
14. e DC ANS 19202 3 way Jumper VCC CM P201 Supply to ratiometric resistive sensors must VAGND Header 2 be set as per VCC_CM LM4120 3V3 V2 InF e PRC AN9 12V ANO 5V ANI 5V VAGND VAGND AN2 5V AN3 5V LM4040 5V AN4 5V AN5 5V AN10 i AN6 5V AN7 5V ANIO 5V EIUS 2 JP203 ANS 5V AN9 3 way Jumper ANIO 5V ANII 5V ANI2 5V ANI3 5V 6V2 e RC ANIO 4 5V 5 5V VAGND VAGND VAGND VAGND VAGND Leave Open to Disable External Reference LM4040 5V ANII 2 4 2 VAREF JP204 ANIL SV a Bae 2 9 205 C206 3 way Jumper P LM4120 3V3 Solderlink 3 way Jumper 100nF en R212 R213 A AE VAGND I2C VDD VAGND VAGND T R214 R215 Solderlink 47R 47R ANI2 5V ANI2 R219 P203 R220 I2C ANII DC AN2 ME DC AN3 RC ANIO 47R 47R R221 R222 DC ANA m mmm DC AN5 47R 47R R223 R224 VAGND VAGND DC AN6 J DC AN7 47R 15 16 47R R225 7 R226 DC ANS met 2 54mm Header pem DC 47R 47R AINC ANIS 5V R227 R228 AN13 R229 R230 MEA DC ANIO DC ANII MAX1138EEE 47R 47R 5V A R231 R232 E MES AONE Allow I2C Devices to be assigned to I2C General or CNTRL 47R 47R VAGND VAGND Access to I2C ADC Channels that are not being used elswhere no Filtering CNTRL I2C SDA 1203 1 2 1204 2 JIX2 Solderlink 3V3 U204 12c GENO spa MI A 4 5V AN14 e SDA 5V SCL 5V CNTRL PCO SCE J205 Sol
15. he CM s ADC and the on board ADC although the latter will sacrifice one channel if this is used They can also be fed back to the CM via the VAREF EDP signal Ratiometric conversions are possible using a special output pin on connector P201 pint for driving resistive sensors Quantity Type 2 2 pole filters with digitally controlled cut off 6 2 pole active filters with fixed cut off 8 1 pole passive filters with fixed cut off 12 Unfiltered channels 1 5V reference 1 3V3 reference 1 1 Anti Aliasing Filters Channels ANO to AN7 are equipped with 2 pole Sallen Key anti aliasing filters configured in a Butterworth mode The active filters are unity gain so they can be used for DC voltage measurements as well as for sampling rapidly changing signals Channels ANO and AN1 optionally have I2C controlled 256 step digital potentiometers which allow the filter characteristics to be altered under software control They can also be cascaded to yield a single 4 pole filter on channel ANO The remaining active filters have a cut off frequency of 12kHz By fitting the appropriate resistors to the potential dividers on the filter inputs R301 R304 etc the input voltage range can be extended to suit the user s application on a channel by channel basis Electrocomponents plc Page 3 EDP AM AN16 Manual RS AN8 AN15 have simple low pass filter inputs All inputs are protected against over voltage conditions 1 2 Additional Items A t
16. odule passes down the backplane the processed analog signals ANO to AN15 These may well have been processed by the on board filters on the AM for example The ANO AN15 signals can be directly read by the CPU module Not all of the CMs can read all of the ANO AN15 signals as the resources available on each MCU are all different To help with the matching up of CMs and Application Modules AMs a Mapping Aid document exists for each of the Command Modules This details the resources that are available on the MCU with the resources available on the AMs The page relating to the Analogue Module is shown below The analog inputs on connector P202 on the analog IO module are connected to the CPU module as shown below The mapping is shown for the STR9 and XC167 modules below XC167 Pin Allocation STR9 Pin Allocation EDP AM AN16 Allocation Vcc to BB Vcc 3V3 or 5V supplied by CM Vcc 3V3 or 5V supplied by CM 42 GUARD AN GND P3 5 AVSS Analog GND 5 7 VAGND IRQ GPIO18 I2C GENO INT P3 2 P5 6 GPIO16 CNTRL I2C INT Digital GND Digital GND Digital GND 37 AN8 NC AN8 39 AN6 P4 6 AN6 33 AN4 P4 4 AN4 31 AN2 P4 2 AN2 45 AN14 NC AN14 43 AN12 NC AN12 35 AN10 NC AN10 29 ANO P4 0 ANO 41 VAREF AVREF Analog AN_REF Vcc 5V from reg Electrocomponents plc 5V from baseboard regulator 5V from baseboard regulator Page 6 EDP AM AN16 Manual RS Vcc 3V3 from reg 3V3 from baseboard 3V3 from baseboard regulator regulat
17. or Pin XC167 Pin Allocation STR9PinAllocation EDP AM AN16 Allocation Vcc to BB Vcc 3V3 or 5V Vcc 3V3 or 5V supplied by CM supplied by CM GUARD AN GND AVSS Analog GND VAGND Digital GND Digital GND Digital GND 38 AN9 NC AN9 40 AN7 P4 7 AN7 34 AN5 P4 5 AN5 32 AN3 P4 3 AN3 46 AN15 NC AN15 44 AN13 NC AN13 36 AN11 NC AN11 30 AN1 P4 1 AN1 Vcc 5V from reg 5V from baseboard 5V from baseboard regulator regulator Vcc 3V3 from reg 3V3 from baseboard 3V3 from baseboard regulator regulator NC XC167 Pin Allocation STR9 Pin Allocation EDP AM AN16 Allocation Vcc 5V from reg Vcc 5V from reg Vcc 5V from reg Vcc 3V3 or 5V supplied by CPU Vcc 3V3 or 5V supplied by CPU Vcc 3V3 or 5V supplied by CPU Vcc 3V3 from reg Vcc 3V3 from reg Vcc 3V3 from reg 23 SDA1 2 3 I2C GENO SDA 24 SCL1 P2 2 I2C GENO SCL Digital GND Digital GND Digital GND 25 SDA2 P2 1 CNTRL I2C SDA 26 SCL2 P2 0 CNTRL I2C SCL Refer to the Mapping Aids to get an overview of what resources the module can connect to 1 5 Analog Module Input Characteristics 1 5 1 Channels ANO AN7 These are over voltage protected and buffered with unity gain 2 order filters The characteristics of the OP amps fitted mean that the usable voltage input range is 24mV to 4 49V with a linear and monotonic response With a 5V 10 bit ADC the decimal value range is from 9 to 804 bits With a 3V3 10 bit ADC the upper value is 1023 bits Electrocomponents plc Page 7
18. rimmer potentiometer and light dependent resistor and are fitted to channels ANO and AN1 respectively for educational purposes 1 3 Setting Jumper Options Some options are made using black 2mm links These are available from RS under part number 180 9353 The possible user settings are listed below along with their default configurations Jumper Type Purpose Default J202 Solder Set voltage for MAX1138 ADC 1 2 J204 Solder Set 12C channel 1 2 J205 Solder Set 12C channel 1 2 J301 Solder Connect local VAGND to SGND on module rather on CPU module NO 1 2 J302 Solder Route ANO 5V to CPU ANO or MAX1138 ANO enable 5V to 3V3 scaling for CPU ANO 1 2 J303 Solder Enable shutdown mode for AD5263 Default 2 3 2 8 J305 Solder Set AD5263 I2C address ADO 2 3 J306 Solder Set AD5263 I2C address AD1 2 3 J307 Solder Create 4 pole active filter from U301A and U301B Open J308 Solder Route AN4_5V to CPU AN4 or MAX1138 AN4 enable 5V to 3V3 scaling for CPU AN4 1 2 J309 Solder Route AN1 5V to CPU AN1 or MAX1138 AN1 enable 5V to 3V3 scaling for CPU AN1 1 2 J310 Solder Route AN5 5V to CPU or MAX1138 AN5 enable 5V to 3V3 scaling for CPU AN5 1 2 J311 Solder Route 5V to CPU or MAX1138 enable 5V to 3V3 scaling for CPU 1 2 J312 Solder Route AN2 5V to CPU AN2 or MAX1138 AN2 enable 5V to 3V3 scaling for CPU AN2 1 2 J313 Solder Route AN7 5V to CPU AN7 or MAX1138 AN7 enable 5V to 3
19. rol Connector GPIO6 MCIDAT2 GPIO7 DSRX CLK GPIO8 MCIDAT3 GPIO9 I2SRX WS GPIOI0 MCICLK GPIO11 DSRX SDA P102 GPIOI2 MCICMD GPIOI3 I2STX CLK ZRESIN ZRESIN GPIOI4 MCIPWR GPIOI5 I2STX SDA RESOUT RESOUT IRQ GPIOI16 CNTRL I2C INT CPU DACOO GPIOI17 I2C GENO SDA 126 GENO SDA IRQ GPIO18 I2C GENO INT CPU GPIO19 126 GENO SCL 126 GENO SCL IRQ GPIO20 I2C GENI INT EVMO GPIO21 IRQ GPIO22 I2C INT EVMI GPIO23 SOND A15 5 A15 ADI5 POND GPIO24 AD7 GPIO25 ADI5 A14 4 A14 ADI4 GPIO26 AD6 GPIO27 AD14 A13 AD13 A13 ADI3 GPIO28 AD5 GPIO29 AD13 A12 ADI2 A12 ADI2 GPIO30 AD4 GPIO31 AD12 All ADII All ADII GPIO32 AD3 GPIO33 ADII A10 ADIO A10 ADIO GPIO34 AD2 GPIO35 AD10 A9 AD9 A9 AD9 GPIO36 ADI GPIO37 AD9 A8 ADS A8 ADS GPIO38 ADO GPIO39 AD8 A7 AD7 A7 AD7 EVGO GPIO40 EVM2 GPIO41 CAPADC A6 AD6 A6 AD6 EVGI GPIO42 EVM3 GPIO43 A5 ADS A5 ADS EVG2 GPIO44 EVMA GPIO45 A4 AD4 A4 AD4 EVG3 GPIO46 EVMS GPIO47 A3 AD3 A3 AD3 EVG4 GPIO48 EVM6 GPIO49 A2 AD2 A2 AD2 EVGS GPIOSO EVM7 GPIOSI Al ADI Al ADI EVG6 GPIOS2 EVMS GPIOS3 A0 ADO A0 ADO EVG7 GPIOSA EVM9 GPIOSS ALE ALE EVG8 GPIOS6 EVG9 GPIOS7 ZRD ZRD EVGIO GPIOSS EVGII GPIOS9 ZWR ZWR EVGI2 GPIO60 EVGI3 GPIO61 ZWRH ZWRH EVG14 GPIO62 EVGIS GPIO63 ZPSEN ZPSEN EVGI6 GPIO64 EVGI7 GPIO65 CSO CSO EVGIS GPIO66 EVGI9 GPIO67 CS1 CS1 ASCO RX TTL EVMIO GPIO68 ASCO CTS CS2 CS2 ASCO TX TTL EVG20 GPIO69 ASCO RTS CS3 CS3 ASC1 RX TTL SPI SSC MRST MISO CANO RX CANO RX ASC1 TX TTL SPI SSC MTSR MOSI CANO TX CANO TX ASCI TX TTL
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