DS26303DK - Part Number Search
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1. RESET_MIC 1365 13C1 lt gt RLOS3 3_ lt 8 1 gt 283 7C5 lt 7CB 1104 1505 1508 1503 1506 1508 RLOSCON_1 7BS lt 1004 lt gt RNEG3 3_ lt 8 1 gt 11 1505 1508 15D3 1506 1508 1685 16B7 RNEG3 3_DUT lt 8 1 gt 381 3B4 gt 3Ci 3C4 gt 4B1 4B5 gt 4C1 gt 4 5 gt 1686 1688 RPOS3 3_ lt 8 1 gt 11 7 1505 1508 15D3 1506 1508 4661 1603 RPOSSOS DUT 8 1 3812 3B4 361 3C4 gt 4 1 4B5 gt 401 4 5 gt 16C3 1804 1 8 1 3B4 lt 8 lt 3C4 lt 3CB 4 4 lt 4BB lt 4C4 lt 4CB S l gt S85 5 1 gt 5 5 1 6BS gt 6C1 gt RTIP3 3_ lt 8 1 gt 4 lt 3B8 lt 3D4 lt 3DB lt 4B4 4BB lt 4C4 4CB lt SAS gt SB1 gt 5 1 gt SC5 gt BR1 685 6C1 gt 665 RUN_KIT_USR 13B3 lt gt 14 lt RW 10A4 lt gt 13D7 lt gt RXF USB 10B3 lt gt 12B5 R_PB_CFG BR2 BB2 gt SCANMODE33 2A3 lt 7DS lt SCI1_IN 12A6 gt 13B4 lt gt SCI1_OUT 12AB lt 13C4 lt gt sck 10B7 13C1 lt gt SCLK_ALE303 2B7 lt BC1 gt 1 B7 lt gt 1583 SDI_WR_LOCAL 2B7 lt 18A7 lt gt 15A3 lt gt SDO_RDY3 3 307 1 15B4 lt gt SIWU_USB 10D4 lt gt 12B5 ss 10B7 13B1 lt gt T1 CLK 1 lt 11 7 lt 10A3 lt gt 13D7 lt gt TCLK303 8 1 4 lt 3C4 lt 4 4 4RB 4 4 lt 4 8 lt 11B3 1505 1508 1503 1506 15D8 TCLKENABLE_BERT B 65 lt BBB 1085 lt 15AB lt g2. I 5 x End of Write Cycle 11 of 43 DS26303 Design Kit SOFTWARE CONFIGURATION Quick Start Software ChipView Perform steps in the Quick Start Hardware Configuration Load ChipView software Select COM port Select Register View From the Programs menu launch the host application named ChipView exe If the default installation options were used click the Start button on the Windows toolbar and select Programs gt ChipView gt ChipView e Load the DS26303DK def file e Make sure that all the register settings are correct for the proper function desired for the DS26303DK e Refer to the DS26303 data sheet for all questions pertaining to device functionality MEMORY MAP The on board microcontroller is configured to start the user address space at 0x81000000 All offsets given below are relative to the beginning of the user address space Table 6 DS26303DK Relative Address Map REF DES DEVICE OFFSET General Purpose FPGA U5 Tx Rx Clock Data 0x0000 Switch Mux U4 DS2174 BERT 0x1000 U6 I 8 Port T1 E1 J1 0x2000 All device registers can be easily modified using the ChipView exe host based user interface software Table 7 General Purpose FPGA Memory Map OFFSET REGISTER NAME TYPE DESCRIPTION 0x00 BRDID Read Only Board ID 0x02 DSIDH Read Only Dallas Extended ID Upper Nibble 0x03 DSIDM Read Only Dallas Extended
3. 1 SWITCH NA 11 USBDM 55722 QNN_THRU HOLE sua HDR TSW 107 14 T D DPDT JTMS MIC 1 cup a 9 IIMS GND JTDO XTIN nm Meine 5 245 ONCE_TDO_FLASHINA G gt 6 144 NA FT245BM Ul USBDP RSTOUT ALIGN KEY JTMS_MIC JDE_B JTRST B 16 XTOUT WR 45 5 RESET 14 TXE_USB rxr 12 RXF USB EECS EESK S PU SIWU USB EEDATA PWREN 10 PWREN_USB FEST 5232 NTERF AC 405 2 16 4 PRT1 IN SCI1 OUT 1 CAE i C 15 S i c 4 k 2 1 10 5 12 356011 9 14 PRT1 OUT 7 PRT1 OUT PRT1 IN TITLE SERIAL and USB DATE ENGINEER PAGE L CS2_ BOARD CSO _RAM 118 RESET MIC 128 CLKOUT_MM210 R59 10K R75 496 10K R24 83 85 cs3x 81 CS2x CSB RESET scr 23 RSTOUTx 120 SWIT ISHIT T TOIT TOWN DSO BI OSIN ISON 144PIN TQFP NA MMC2107PU I9 Ua 2107 CONTROL IIX NN IB H9T WIL NI INI 3STT cust asst USER _LED11 USER LEDA
4. 1788 CONN 4 P 1585 RES1 1208 RES1 5 6 1798 POWER_JACK 1808 RES1 16A7 RES1 1798 USB_BCON_U 1208 RES1 1688 RES1 575 1785 CONN_DBSP 1285 RES1 16BB RES1 sca 1207 CONN BNC SP 701 RES1 1686 RES1 575 17 7 CONN 14P 1263 RES1 16B5 RES1 sca 1785 5 7A2 RES1 1688 RES1 ses 179 CONN BNC SP 7 1 RES1 1687 RES1 1787 CONN 14P 1507 RES1 1698 RES1 ses 17 5 CONN 14P 1588 RES1 1688 RES1 1505 1784 CONN 14P 1507 RES1 15B5 RES1 17 4 CONN 14P 15 7 RES1 16BS RES1 sA2 17 4 CONN 14P 1505 RES1 1285 RES1 1 1798 CONN 14P 1586 51 702 RES1 1602 1794 CONN 14P 1505 RES1 7B2 RES1 1775 CONN 14P 1564 RES1 12 1 RES1 8525 1785 CONN 14P 1587 RES1 12 1 RES1 1504 1787 1898 RES1 1284 RES1 1505 1784 JMP3 1887 RES1 1285 RES1 1607 1795 1887 RES1 1307 RES1 1502 1787 5 5 RES1 1384 RES1 1607 1787 CONN BNC SP 503 RESI 1263 RES1 16D7 1796 5 51 1206 RES1 704 17C1 CONN_BNC_SP 593 RES1 1307 PUSHBUTTON 1388 17 2 1781 1785 17B2 1785 1785 17B2 1792 17B2 17 4 17B5 1 5ca 1796 5 5 1784 BAL sca
5. 3 lt 8 1 gt IRING303 8 1 5 I61 CONN_SMB 7S OHM VERT CONN_BNC_SP SMB UERT ITIP3O03 8 1 J32 L 9 3 RTIPSO3 8 1 CONN_BNC_SP 1 CONN 7S OHM 160 CONN SMB 75 OHM VERT TRING3 3_ lt 8 1 gt CONN BNC SP 4 RTIP303_ 8 1 gt NZ e 3 RRING303 8 1 gt lt TITLE RRING3 3_ lt 8 1 gt LIU INT ENGINEER E SMB 75 OHM VERT 5 41838 158 SMB 7S OHM VERT CONN J25 5 303 lt 8 15 e s TRING303 1 184 43223 8140 TH RI4S APORT J46 ror RTIP3 3_ lt 8 1 gt 6 163 CONN_SMB 7S OHM VERT CONN BNC_SP J36 49 168 20 159 CONN_SMB 7S OHM VERT CONN BNC_SP Ot 54 CONN_SMB 75 OHM VERT CONN BNC SP J28 8g TTIP3S03_ lt 8 1 gt TRING3 3_ lt 8 1 gt 9 38 8 1 RRING3 3_ lt 8 1 gt L q s TTIP303_ lt 8 1 gt TRING3 3_ lt 8 1 gt 6 RTIP3O03 8 1 5 166 CONN_SMB 7S OHM VERT CONN BNC SP eB e 50 e 8
6. 1 1785 BES COIL 2P 13D6 RES1 1 cs 1793 1792 RES1 RES1 8cs c6 1785 SAL RES1 RES1 805 1785 17C1 RES1 1866 RES1 7CB 17 4 17B2 RES1 1604 RES1 705 1763 17B1 RES1 16C6 RES1 506 1795 RES1 16C7 RES1 502 17B1 RES1 1602 RES1 705 586 1791 RES1 1604 RES1 14B2 582 1792 RES1 16C7 RES1 14B3 505 17B1 RES1 1705 RES1 17B1 RES1 1604 RES1 1492 1 6825 LED 18B7 RES1 16C6 RES1 7 6 502 LED 1497 1 7C4 RES1 705 17 4 LED RES1 17C5 RES1 7AS 1288 LED 707 RES1 705 RES1 1784 LED RES1 1687 RES1 128 LED 707 RES1 16B5 RES1 1505 1787 LED RES1 1685 RES1 16D7 1784 LED 707 RES1 16B7 RES1 BAS 1775 LED 1687 RES1 1794 LED 707 RES1 1685 1 1602 178 LED RES1 1685 RES1 1606 1208 LED 852 RES1 1687 RES1 15C7 1275 SCHOTTKYDIODE1 RES1 13A1 RES1 7C4 1268 SCHOTTKYDIODE1 RES1 13A1 RES1 16D7 i787 SCHOTTKYDIODEL RES1 7DS RES1 sc2 1288 4_40_HDWR 18 1 RES1 18B7 RES1 4 1384 4 40 HDWR 18B1 RES1 1688 RES1 1384 4 40 HDWR 1861 RES1 1208 RES1 6c2 1207 4_40_HDWR 1861 RES1 12D7 RES1 Sce
7. 3 MD EM DEM M MEM 6 BASIC OPERATION 7 HARDWARE CONFIGURATION 7 QUICK START HARDWARE SETTINGS SINGLE POWER SUPPLY eese teen 7 URS TION u uuu 7 Tabi T No T Dn 7 CEN o UE 8 ADDRESS DATA BUS CONNECTOR a anna 8 Table 2 Address uuu 8 TELECOM CLOCK AND DATA TEST 8 rk ERR ARR RR RR AAA 9 Tal Tolem Connie Clor FROU IM 9 ON BOARD BITERRORHSATE TESTER BERT u uuu ulus 9 Table 4 BERT 9 PROM SPUGONEJGIBATIQON Obra FC CD P E 10 Figure s SHIT THING Dagan ua PO p A 10 Figure 3 SFI Conhguratoh WIS PROM usuy unamasa estere 11 Tobie 5 CORT ONG c M 11 SOFTWARE CONFIGURATION u 12 12 MEMORE 77 ss asna 12 Table D395303DK Relative Address Map ARR SERA REN AR RAE 12 Table 7 General Purpose FPGA Memory Map u uuu ceariecdissssavecen
8. CONN_BNC_SP CONN BNC SP CONN BNC SP CONN_BNC_SP CONN_BNC_SP CONN_BNC_SP CONN_BNC_SP CONN_BNC_SP CONN_BNC_SP CONN_BNC_SP CONN BNC SP CONN BNC SP JMP OPEN 2P JMP OPEN 2P JMP OPEN 2P JMP OPEN 2P JMP OPEN 2P 603 507 503 SB7 5B3 507 587 583 503 507 503 586 5B3 507 RES1 12B2 RES1 12B1 RES1 1482 RES1 RES1 12 7 RES1 7C2 RES1 702 RES1 13D4 RES1 14B3 RES1 1486 RES1 1402 RES1 1495 RES1 1497 RES1 14B2 RES1 1361 RES1 RES1 14B2 SMWITCH DPDT SLIDE 6P SMHITCH DPDT SLIDE 5P SMHITCH DPDT SLIDE 5P PUSHBUTTON BB3 SMHITCH DPDT SLIDE 5P 1495 1264 1408 XFMR QURDPORT T1 U 582 SAG SB2 5B5 5C2 506 503 505 XFMR QUADPORT T1 U 6A2 682 2 606 505 FT24SBM_U 12 MMC2107 1 1305 1306 CY62128V_2 1407 52174 XC2S_FG256 8906 1 5 1165 XC18U02U044C ENGINEER 4 2 e _ 05232 128 NC7SZB5 U 702 MAX1793_U 1707 CY62128V_2 14C3 NC7SZ86_U 702 74 04 U 707 708 9A3 i366 1862 74 00 7B4 1386 18B2 74 04 7B 7C7 7C 7 7CB 1852 16_2 8B2 1792_1 1703 MAX1793_U 1705 XCFS_VO20 982 XTAL_U 12 7 XTRL 1384 osca 7B2 osca TITLE DATE ENGINEER C
9. 70SC MICRODATA_ lt 15 gt MICROADD_ lt 17 MASTER MODE BOOT INTERNAL PD1IS INTERNAL FLASH EN TITLE DATE SRAM ENGINEER PAGE Bui s gt ees 02 149 J11 TCLK303 8 TCLK3O03 8 DAT t 02 149 JS J43 TCLK3O03 8 RCLK3O03 8 RCLK3OS3 8 RCLK303_ lt 8 TPOS303 8 TPOS3O03 8 TPOS303 8 RPOS303_ lt 8 RPOS303_ lt 8 RPOS303_ lt 8 TNEG3 3_ lt 8 TNEG3 3_ lt 8 10 TNEG303_ 8 RNEG3 3_ lt 8 RNEG3 3_ lt 8 10 9 11 RNEG3 3_ lt 8 12 11 053503 8 053503 8 14 138 12 11 13 44 RLOS3 3_ lt 8 NN THRU HOLE R TSHW 107 14 T D TCLK303 8 18 138 14 6 14 14 13 CONN_14Pi TCLK303_ lt 8 CQNN_THRU HOLE HDR TSW 107 14 T D J16 RCLK303_ lt 8 11 TPOS303_ lt 8 11 12 10 RCLK303_ lt 8 5 0 lt 8 3 lt 8 3 8 TNEG303_ lt 8 TNEG303_ lt 8 RNEG303 8 RNEG3U03 8 RLOSS3O03 8 053035 lt 8 a IR TSW 107 14 T D INN THRU HOLE 61 a NI 63 INN_THRU HOLE TSW 107 14 T D CO NA HD II TL R
10. 16 1 USER_IN1 1 USER IN2 1 MICRO CONTROLLER s PAGE TEST TXDL RXD1 53 1 2 55_ rcocza 58 11 55 TXD2 58 RXD2 TEST 63 72 I2 SCI1 O0UT SCI1 IN 2 CLKOUT GND OSC_MCU USSSSYN lt ZT s m gt z o Y zl O TSSN essn eaqn ESSN gaan PSSA vadn 5550 saan 955 SS Bssn NASSSn Nasaan 1550 RESET_MIC VSSA 5 _ IC2107PV 300 2a IS 14 vaan MMC2107 dd HSU 14 Agisn 5 O3L1 9 2 x30 era 144 15 PD31 is 29 12 PD28 PD26 UST ULUGOHOIAW MICROADD_ lt 17 gt ENABLE MICRO 181 SWITCH Na SSA22 SWS U3 3 DPDT I 1 Ls og L9 ALO A9 AB 152 U3 IOS CY62128U IO3 SOIC 102 CY862128UL 70SC bony m QO cC d d C G G G RUN_KIT_USR FLASH_UPP gt MICRODATA_ lt 15 gt TIM_16H_8L 119 U11 CY62128U SOIC CY62128VL
11. 52 TCLKENABLE_BERT1 TCLKIN_BERT 3 TCLKOUT_BERT 5 RCLKIN BERT 7 RCLKENABLE_BERTS TDAT BERT RDAT_BERT 11 13 BERT Co TEST POINTS TSW 107 14 T D THRU HOLE THROUGH HOLE a TSW 120 07 T D 18 CLKF303 16 INT3 3 28 FPGA_EN USFR_IN2 32 15 16 118 19 22 28 Sno RDY303 21 55155 27 28 31 32 15 17 ig CSFPGA 21 CS_BERT 23 24 24 MOTEL 303 ADDRESS_LOCAL_ lt 8 MUX3a3 0538038 25 55 2628 27 SCLK_ALE3 3 29 og 39 32 USFR_IN1 BI SDI_WR_LOCAL 33 34 34 MODESEL 323 35 35 36 ESTPOINTS ENGINEER PAGE AINE eA ee _ _ _ T 8 OESOdH 77824 0 eaesods SERIAL TERMINATION So o lt T B gt T 8g ina eeesodasd lt T 782100 EBENON lt 1 B gt 8 gt OEwN oH T 8 1n0 lt T 8 lt T 8 gt 3 _ R38 R32 1 2 363 DATAS 3_ lt 7 gt 3 3 1 8 TEBEH TDH lt T EB EDSNY 8 3U REGULATOR 2 5U REGULATOR 8 9 REGULATOR DS26334 ONBORRD 3 3U REG CORE VOL FPGA S3EUE 33 11 I 13 jo
12. 4 0x04 RPOS Port 5 0x05 RPOS Port 6 0x06 RPOS Port 7 0x07 RPOS Port 8 0x08 HI Z 0x09 HI Z 0x0C HI Z 0x0D HI Z 0x0E HI Z 0x0F HI Z 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 TCLKBERT OUT 0x16 0xFF HI Z 17 of 43 DS26303 Design Kit Register Name TCLK Register Description PORT TCLK SOURCE Register Offset 0x10 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 D7 to D0 These bits control the source of the port TCLK for the DS26303 TCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 HI Z 0x09 HI Z OxOB HI Z OxOC HI Z OxOD HI Z OxOE HI Z OxOF HI Z 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 TCLKBERT OUT 0x16 0xFF HI Z 18 of 43 DS26303 Design Kit Register Name TPOS Register Description PORT TPOS SOURCE Register Offset 0x11 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D
13. 43 DS26303 Design Kit PROM SPI Configuration In software mode it is possible to configure the DS26303 using a parallel interface or a serial peripheral interface SPI Most advanced microcontrollers have both a parallel interface and SPI interface such as the microcontroller on the DS26303DK The command you send to the microcontroller through either the USB or serial port determines if that data is placed on the parallel or SPI bus Refer to the data sheet for Chipview on the particular commands required to switch data ports A unique feature with the SPI port is that a PROM can be used to provide the LIU with the specific data needed for configuration If the data in the PROM is formatted a certain way it can seem as the PROM is acting like controller with a SPI interface in master mode The most common 5 to use for this type of application are those with an internal address accumulator This feature for the PROM is important because the device must automatically jump to the next available address in the configuration memory The Xilinx 18 00 device family is a byte wide nonvolatile memory with an autoincrement address function The family of devices is available in 1Mb 2Mb and 4Mb densities The PROM is also useful because the device can perform in circuit programming with the JTAG port Refer the data sheet for the XC18V00 for the JTAG codes for programming the configuration memory Figure 2 shows a general relationshi
14. R123 Panasonic R30 R59 2 15 5 1 16W resistors 0603 ERJ 3GEYJ153V R51 4 Resistor 1206 __ POPULATE Panasonic R53 1 4700 5 1 16W resistor 0603 ERJ 3GEYJ471V Panasonic R92 1 510 5 1 16W resistor 0603 ERJ 3GEYJ510V R103 R105 R116 Panasonic R118 R119 R122 16 60 4 1 1 16W resistors 0603 ERJ 3EKF60R4V Panasonic SW2 SW6 2 4 pin single pole switch EVQPAE04M SW3 SW4 SW5 m Tyco Electronics SW7 4 6 pin slide switches DPDT through hole SSA22 Transformers 1 2 count transmitter 1 1 count Pulse Enai T1 T2 2 receiver ngineering 40 pin wide SO 40 C to 85 C U4 1 8 bit FIFO USB UART FTDI 32 pin LQFP FT245BM Motorola U2 1 MCORE Microcontroller 144 pin LQFP MMC2107PV 128k x 8 SRAM Cypress Haru 2 32 SO CY62128VL 70SC U4 1 DS2174 EBERT Dallas Semiconductor 44 pin PLCC 0 C to 70 C DS2174Q 05 1 Spartan ll 2 5V FPGA 200k gate Xilinx 256 pin BGA XC28200 5FG256C 6 1 3 3V E1 T1 J1 long haul octal LIU Dallas Semiconductor 144 pin eLQFP 0 C to 70 C DS26303L 4 of 43 DS26303 Design Kit SUPPLIER DESIGNATION QTY DESCRIPTION PART NUMBER U7 1 PROM for FPGA Xilinx 44 pin TQFP XC18V02VQ44C U8 1 Dual RS 232 transmitter receiver Dallas Semiconductor 150 mil 16 pin SO DS232AR Fairchild Semiconductor U9 U12 2 High speed buffers NC7SZ86 1 U18 2 1 9W 3 3V or adj 1A linear
15. regulators Maxim 16 TSSOP EP MAX1793EUE 33 Toshiba U13 U15 2 Hex inverters 14 pin SO TC74HCO4AFN U14 1 Quad 2 input NAND gate Toshiba 14 pin SO TC74HC00AFN U16 1 Switch debouncer Maxim 4 pin SOT143 MAX6816EUS T U17 1 2 5V or adj linear regulator Maxim 8 pin uMAX SO MAX1792EUA25 Platform flash in system programmable configuration MIS Fa 2Mb 20 TSSOP Pletronics X1 1 6 00MHz low profile crystal LP49 26 6 00M Ecliptek Corp X2 1 8 000MHz low profile crystal EC1 8 000M Y1 1 Oscillator crystal clock SaRonix 5V 2 048MHz NTH039A 2 0480 Y2 1 Oscillator crystal clock SaRonix 5V 1 544MHz NTH039A 1 5440 5 of 43 DS26303 Design Kit BOARD FLOORPLAN El LOS LED TCLK RCLK RLOS TPOS RPOS JUMPER TNEG RNEG JTAG PORTS 5 8 USER CON SWITCHES BERT FLASH DS2174 PROM BERT FPGA Tx Rx CLOCK TPOS RPOS DATA TNEG RNEG SWITCH MUX L 9 L3 9 L OS LED RLOS 08 20 0 8 0 08 2 0 8 8 9 6 of 43 DS26303 Design Kit BASIC OPERATION This design kit relies upon several supporting files which are available for downloading on our website at www maxim ic com DS26303DK The support files are used with an evaluation program called ChipView which is available for download at www maxim ic com telecom HARDWARE CONFIGURATION Quick Start Hardware Settings Single
16. 17_ 1019 2 FPGA_TECLK CS BERT 1018_ 1020 2 F12 303 RD_LOCAL DS 10190 10231 2 E15 MODESEL 303 SDI_WR_LOCAL CLKES3OS 1023_2 TEA 1024_2 TA IO1_3NINIT I02_3 D7 I03_3 IO4 3NUREF I06_3 I07_3 D6 108 5 T010_3 VREF IO11_3ND4 IO13_3NTRDY IO17 3 15 N14 M13 L14 L13 N16 M16 FRO Mis RD RCLI lt 15 TITLE FPGA PORT A ENGINEER PAGE dC s r Se RCLKENRI TCLKENABLI RLOS303 8 1 RLOS3 3_ lt 1 gt IS IO2 5NUREF 108 SwuREF 58 1010 5 5 GCKO T01_6 TRDY 101 4 I02 6 IO2 4 _6 IO3_4NUREF IO4_SSNUREF IO4_4 6 105 4 I05 6 IO6 4 I07_6 I07_4 _6 108 4 6 41 TOS_4 VREF IO10 5NUREF 201024 XC25 FG256 1011 6 11_4 1012 65 IO12 4 IC13 6 RNEG3 3_ lt 8 1 IO13 4 I014 6 v 1 m m 0 1014 4 5 6 1015 4 6 1016 4 017 6 IO17 4 IC18 6 15 IO18 4 10196 1019 4 1020 5 IO20 4 I021 6 TCLK303 8 1 IO21 4 1022 6 IO22 4 IO23_5 TPOS303_ lt 8 IOS TNUREF IO9_7 VREF IO12_7NIRDY RCLK303_ lt 8 DATAS 3_ lt 7 ADDRESS_BERT_ lt 3 gt FPGA PORT B ENGINEER PAGE E 3 8
17. 3 TCK RDAT_BERT 1 Ann 2TCLKOUT_BERT TMS 15 XC18V02 SPI DS26303 21 CEOX VQ44C SDI_WR_LOCAL 1 2TDAT BERT RESET CFGPRM 13 2 SCLK LES03 DS26303 22 PLCC E xj s CS303 A MCLK303 43 a 0521740 CSB 526303 UA VDD lt gt UDD lt 1 gt 0 052174 SERIAL FLASH ADDRESS_BERT_ lt 3 QUICK LIU CFG SPI CS_BERT RD_LOCAL SDI_WR_LOCAL gt 9 8T143 AX68 16EUS T SWITCH 23 3 NA U16 EUQPREDAM 6 MAX6816 1 GND UCC I S N M 7T TCLKIN BERT TCLK 25 TCLK_EN TCLKENABLE_BERT GND gt GND lt 1 gt GND lt 2 gt GND 3 22 29 3 N3 3 RCLKENABLE_BERT TCLKENABLE_BERT _SMT 6Q3_DNP e NA 258 JDS303OUT SPI PROM IN 1 2 JTDO TITLE DATE BERT and SPI PROM ENGINEER PAGE 8 _ UccINTs D4 UccINT4 D13 o 4 o UVCCINT1O N13 o UCCINT11 P3 P14 UCCINTL 5 ES uccINTs E12 UCCINT7 M12 Q UCCINT12 c3 UccINT2 14 o UCCO1 ucco2 JTMS ais JFLASHOUT_FPGAIN SERIAL CFG FLASH FOR FPGA ucco4 JTCLK JFPGROUT DSSOSIN uccos UCCOB5 XC2S FG256 PROGRAM P15 PROGRAM_FP
18. 4 D3 D2 D1 D0 Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 D7 to D0 These bits control the source of the port TPOS for the DS26303 TPOS DESCRIPTION 0x00 RPOS Port 1 0x01 RPOS Port 2 0x02 RPOS Port 3 0x03 RPOS Port 4 0x04 RPOS Port 5 0x05 RPOS Port 6 0x06 RPOS Port 7 0x07 RPOS Port 8 0x08 HI Z 0x09 HI Z OxOB HI Z OxOC HI Z OxOD HI Z OxOE HI Z OxOF HI Z 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 TDATBERT OUT 0x16 0xFF HI Z 19 of 43 DS26303 Design Kit Register Name TNEG Register Description PORT TNEG SOURCE Register Offset 0x12 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 D7 to D0 These bits control the source of the port TNEG for the DS26303 TNEG DESCRIPTION 0x00 RNEG Port 1 0x01 RNEG Port 2 0x02 RNEG Port 3 0x03 RNEG Port 4 0x04 RNEG Port 5 0x05 RNEG Port 6 0x06 RNEG Port 7 0x07 RNEG Port 8 0x08 HI Z 0x09 HI Z OxOB HI Z OxOC HI Z OxOD HI Z OxOE HI Z OxOF HI Z 0x10 1 544MHz On board o
19. 555 45 0 Maxi793 U IN1 OUT1 12 nf VDUT _ CON IN1 OUT1 mes otra 5 1 IN2 OUT2 ers ea INL OUTL vi INA ouT4 15 E RESET_B ds cn INA OUTA P I RST SET RESET_B RST SET 9 j SHDN GND SHDN GND 18 pum d opaz 4 MAX 1792 TITLE DATE DECOUPLING CAPS pu SU DC POWER SUPPLY REVERSE BI S PROTECTION amp 205 0 2 5 SMM J 02AH _ 26 295 0 BOARD PWR LED SPLIT BOARD POWER SUPPLY AND DUT POWER SUPPLY U DUT UDUT_CON e MMC2107 ON BOARD MICRO 9 JTAG CON REUERSE BIRS PROTECTION ON CE JTAG MUX XCF 0 2SVO20C FPGA CFG PROM XC2S2008 SFG XCFO2SUO2ZO0C CFG PROM FOR DS26334 SPI ONLY 9 JIAG NOIE 0526303 8 1 1 71 LIU TITLE 129 13 015 M DATE ENGINEER PAGE Eu E sw j x TITLE DATE NOTES ENGINEER amp 1
20. 6303 MCLK1 MCLKO DESCRIPTION OF MCLK 0 0 MCLK high impedance mode 0 1 MCLK on board T1 oscillator 1 0 MCLK on board E1 oscillator 1 1 MCLK user clock input 13 of 43 DS26303 Design Kit Register Name ABSP Register Description ADDRESS BANK SWAP POINTER Register Offset 0 0 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Bits 7 to 0 D7 to D0 These bits control the address bank for address 0x10 TCLK N 0x11 TPOS and 0x12 TNEG ABSP DESCRIPTION 0x00 Bank Address Value for Port 1 0x01 Bank Address Value for Port 2 0x02 Bank Address Value for Port 3 0x03 Bank Address Value for Port 4 0x04 Bank Address Value for Port 5 0x05 Bank Address Value for Port 6 0x06 Bank Address Value for Port 7 0x07 Bank Address Value for Port 8 14 of 43 DS26303 Design Kit Register Name BTCLK Register Description BERT TCLK SOURCE Register Offset 0x0B Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 DO Bits 7 to 0 D7 to DO These bits control the source of the TCLK for the BERT BTCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 HI Z 0x09 HI Z OxOB HI Z OxOC HI Z OxOD HI Z OxOE HI Z O
21. B3 7C4 BC3 lt MCLK_FPGA 18C3 lt gt MICRORDD 17 0 10 7 13B4 14B4 14B8 MICRODATA_ lt 15 gt 1085 1005 13B8 14C2 1465 MISO 1 B7 lt gt 1382 303 2C7 1 B3 lt gt 1583 16A7 lt MOSI 1 B7 lt gt 1382 MOTELSO3 2B7 10B3 lt gt 15B3 lt gt MUX383 2B7 10B3 15846 10646 13D7 14D3 1407 lt OE303 2C3 10B3 lt gt 15B3 lt gt ONCE_TDO_FLASHIN SB3 12C4 lt gt 13D2 lt gt OSC MCU 13B2 13B4 lt gt PD16 13BB 14B3 PD17 13BB 14B3 PD18 13B8 14R4 5519 13886 14A2 lt PD20 13B8 PD21 13CB 14B2 PD22 13CB lt gt 14 2 lt PD23 13CB 14B2 PD24 13CB lt gt PD25 1 8 PD26 13CB 14B3 PD27 13C8 PD28 13CB 14A2 lt PD29 13C8 PD3 13686 PD31 13C8 PROGRAM_FPGA_A 9B1 gt lt PRT1_IN 12A6 lt gt 12 8 PRT1 OUT 13686 1288 PHREN USB 1004 lt 1285 RCLK303_ lt 8 1 gt 1186 1505 1508 15D3 1506 1508 1668 1658 RCLK303_DUT lt 8 1 gt 3812 3B4 gt 3C1 gt 364 481 465 401 465 1865 16C7 RCLKENABLE_BERT 6 807 10AB lt gt 15AB lt gt RCLKIN_BERT BD7 lt 1076 gt 15AB lt gt RCON 10A4 lt gt 13D7 lt gt 14A2 lt RDAT_BERT BD8 1076 gt 15686 RD_LOCAL 2B7 lt 10 7 lt 15A3 lt gt RD_USB 10AB lt gt 1265 RESET 12B3 lt gt 13A7 lt RESET_B 9B1 lt gt 1388 17C6 gt 17 8 17D3 gt RESET_CFGPRM BR3
22. DS26303 The FPGA was designed to perform specific signal routing functions such as looping back RPOS to TPOS on a particular port or transferring data from the on board BERT If you are using user defined data and drive the signal on the connector be sure to tri state the input signal in the FPGA FAILURE TO DO SO COULD CAUSE DAMAGE TO THE FPGA On Board Bit Error Rate Tester BERT The DS26303DK has an on board bit error rate tester BERT to generate and detect errors in either pseudorandom or user defined patterns The BERT on the DS26303DK is the DS2174 A header for the relevant signals related to the BERT is located on the board J17 See Table 4 for the pinout of the BERT connector The BERT signals are routed into the FPGA and can be muxed into any of the 8 DS26303 LIU ports under software control For all questions concerning the operation of the on board BERT refer to the device data sheet available online at www maxim ic com telecom If you are using user defined data and driver the signal on the connector be sure to tri state the input signal in the FPGA FAILURE TO DO SO COULD CAUSE DAMAGE TO THE FPGA Table 4 BERT Connector Pinout PIN NAME FUNCTION 1 TCLK EN BERT TCLK Enable 2 4 6 8 10 12 1 GND Ground TCLKIN BERT TCLK Input RCLKIN BERT RCLK Input 3 5 TCLKO BERT TCLK Output 7 9 RCLKEN BERT RCLK Enable 11 TDAT BERT TDAT Output 13 RDAT BERT RDAT Input 9 of
23. DS26303DK 5 DALLAS 3 3V E1 T1 J1 Short Haul Octal LIU Design Kit GENERAL DESCRIPTION FEATURES The DS26303DK is a fully integrated design kit for Expedites New Designs by Eliminating First the DS26303 3 3V 8 port E1 T1 J1 line interface Pass Prototyping unit LIU This design kit contains all the necessary circuitry to evaluate the DS26303 in all modes of Demonstrates Key Functions of the 0526303 operation The design kit also includes an on board Includes DS26303 x 8 Port LIU Transformers microprocessor to run real time code for further part 750 BNC Connectors RJ 48 Connectors and evaluation Termination Passives Communicates Directly with any PC with a DESIGN KIT CONTENTS USB or RS 232 Serial Interface DS26303DK Board High Level Windows Based Software SV AC DC Adapter Provides Visual Access to All Registers 3ft USB Cable Download Software Controlled Register Mapped ChipView Software Configuration Switches Facilitate Real Time DS26303DK def Definition Files Clock and Signal Routing DS26303DK Data Sheet Precision Test Points for All Clocks and Signals ORDERING INFORMATION On Board and E1 Crystal Oscillators for PART DESCRIPTION Stable Clock Generation DS26303DK 0526303 Design Kit Board On Board BERT for Testing and Pattern Generation Windows is a registered trademark of Microsoft Corp 1 of 43 REV 101105 DS26303 Design Kit TABLE OF CONTENTS COMPONENT LS p e
24. ENRLOS1 CLKE SPI SWAP SPI MCLK1 MCLKO Bit 7 INT303 This bit indicates the status of the INT303 line If INT303 LOW there is no hardware interrupt on the DS26303 If INT303 HIGH there is a hardware interrupt on the DS26303 Bit 6 ENRLOS1 This bit enables the RLOS1 LED This should not be enabled when driving from the DS26303 If ENRLOS1 LOW the RLOS1 LED is not enabled If ENRLOS1 HIGH the RLOS1 LED is enabled and lights wnen RLOS1 is high Bit 5 CLKE This bit sets the CLKE pin on the DS26303 This is only active when SPI Bit 0 is HIGH If SPI Bit 0 is low CLKE is always low If CLKE LOW SDO is clocked out on the rising edge of SCLK If CLKE HIGH SDO is clocked out on the falling edge of SCLK Bit 4 SPI SWAP This bit sets the BSWP A5 pin on the DS26303 This is only active when SPI Bit 0 is HIGH If SPI SWAP LOW the SPI bus is LSB first If SPI SWAP HIGH the SPI bus is MSB first Bit 3 SPI This bit sets up the FPGA to use serial mode This bit also changes the mode pin on the DS26303 If SPI LOW the parallel bus is used for all read write access This also sets the MODE pin on the DS26303 to logic 1 If SPI HIGH the SPI bus is used for all read write access This also sets the MODE pin on the DS26303 to logic O Bit 2 OE This bit controls the OE pin to the DS26303 Bits 1 and 0 MCLK1 and MCLKO These bits control the MCLK pin to the DS2
25. ERFACE PORT TROL BLOCK 1 4 IU ERFACE PORT LOS I ERT an T and EDs d SPI P 5 8 COIN TEN FPGA CONTROL PGA PORT PGA PORT B ERIAL JTAG a MICRO CONTROLL RAM ESTPOINTS fin nd USB ER ERIRI ERMINA TION ECOUPLING POWER CON FS SIGNAL CROSS PART CROSS R APS REF EF P 1 COVER PAGE ENGINEER PAGE j ou 25 4 5 5 MODESEL 303 92 ADDRESS_LOCAL_ lt 8 0 SDO_RDY303 SDI_WR_LOCAL RD LOCRL SCLK_ALE3 3 CS303 8038 MUX303 JTRST_B JTCLK JTMS JDS3030UT_SPI_PROM_IN JFPGROUT DS3O0S3IN A47RIMPMS A3 GMC3 A2 GMC2 AL ZGMC1 AB GMCB SDO RDY ACK RIMPOF F SDI WR DS TSO RD RW TS1 SCLK ZALEZASB TS2 CS JRS MOTEL CODE MUX TIMPRM S26303_URLM CONTROL UDD IOA 17 UDD IOB D RD BSWP D676D6 7 DS ADS 7 D4 AD4 D3 AD37 D27 0D27 D41 6DB1 DO nDO RLOSL1 TECLK LOS2 RXPROBEAL LOS3 RXPROBEB1 LOS4 RXPROBEC1 RLOSS SCAN_DO RLOS6 SCAN_DI RLOST SCRN CLK RLOS8 SCRN EN SCAN_MODE YUSS_IOB 418 1955 108 91 15 V3_3 gt 114 OE303 DATAS 3_ lt 7 INT3 3 MCLK303 CLKA3 3 CLKE3 3 05303 lt 8 1 gt 94 SCANMODE3 3 TITLE DATE DS26303 CONTROL BLOCK ENGINEER PAGE RTIP303_ lt 8 R
26. GA_A en D15 CCLK_A E CONTROL Done R14 DONE_FPGA_A UCCO10 UCCO11 CFG_DIN_A COL ISO Ml 12 CEx 48 DONE_FPGA_A ONCE_TDQ_ELASHIN 4 13 Ucccia4 Re JIMS s OE RESETx 8 RESET_B ucco1s 54 JTCLK crx _2__PROGRAM_FPGA_A UCCC16 17 xCF S UO20 9 ET U13 DONE_FPGA_A 1 338 R123 TITLE DATE FPGA CONTROL ENGINEER PAGE 9 3 s j gt MEME DENEN ADDRESS_LOCAL_ lt 8 SB USB CLKOUT 010 200 1018 1 B10 101 1 5 IOA 1NUREF IOS 1NUREF IO12 1 IO13 1 IO15 1 IO19 1 IO20 1 2 H15 F PGA_CLKA USER_CLK 102 2xwuREF 5 MCLK_FPGA Io3 24D3 Gi6 INTGOS I02_1 WRITEX 108 IO4 2 IO3 0 I105_2 0 I06_2 D2 105 6 I Io7_2 D1 DATA_ lt 7 gt 06 0 2 IO7_ VREF 109_2 IO10 2NUREF XC2S FG6256 Ic9_ 1011_2 MICRORDD 17 0 MOSI 18 I012 2 DIN DO Di4 CFG DIN A MISO 66 roii p 1013 2 DoUT BUSY C15 RXF USB_ SS 8 1014_2 Hi4 TINTERLIPT 07 5 0 1015_2 313 MUXSOS EN tote Tole SDO_RDY323 SCLK_ALE323 101549 CSFPGA 10160 1018_2 S12 TXE USB_ CS303 84 10
27. ID Middle Nibble 0x04 DSIDL Read Only Dallas Extended ID Lower Nibble 0x05 BRDREV Read Only Board Rev 0x06 ASMREV Read Only Assembly Rev 0x07 FPGAREV Read Only FPGA Firmware Rev 0x08 CTRL1 Control Control Register 1 ABSP Control Address Bank Select Pointer 0x0B BTCLK Control BERT TCLK Input 0x0C BRCLK Control BERT RCLK Input 0x0D BRDAT Control BERT RDAT Input 0x10 TCLK Control Indirect Register for TCLK Source Control 0x11 TPOS Control Indirect Register for TPOS Source Control 0x12 TNEG Control Indirect Register for TPOS Source Control 12 of 43 DS26303 Design Kit ID REGISTERS BID BOARD ID Offset 0X0000 BID is read only with a value of 0xD XBIDH HIGH NIBBLE EXTENDED BOARD ID Offset 0X0002 XBIDH is read only with a value of 0x0 XBIDM MIDDLE NIBBLE EXTENDED BOARD ID Offset 0X0003 XBIDM is read only with a value of 0x1 XBIDL LOW NIBBLE EXTENDED BOARD ID Offset 0X0004 XBIDL is read only with a value of 0x6 BREV BOARD FAB REVISION Offset 0X0005 BREV is read only and displays the current fab revision AREV BOARD ASSEMBLY REVISION Offset 0X0006 AREV is read only and displays the current assembly revision PREV FPGA REVISION Offset 0X0007 PREV is read only and displays the current PLD firmware revision CONTROL REGISTERS Register Name CTRL 1 Register Description DS26303DK FPGA CONTROL REGISTER 1 Register Offset 0x08 Bit Name 7 6 5 4 3 INT303
28. Power Supply e For single power supply operation short jumpers J18 J19 J20 between the 3 3V pin and the VLIU pin This connects VDD of the DS26303 to the 3 3V supply on the design kit Ensure that the FLASH switch SW3 is in the RUN position Ensure that the FPGA switch SW5 is in the ON position Ensure that the SPI PROM switch SW7 is in the OFF position If using the serial port connect a RS 232 serial cable from DS26303DK J4 to the PC If using the USB port connect a USB cable from DS26303DK J3 to the PC Connect AC DC adapter with an AC power source and the DS26303DK 92 PWR LED should be on JTAG Configuration The JTAG chain is controlled by the connector JTAG CON J6 and two on board switches FLASH SW3 and ONCE JTAG SW4 Depending on the function such as programming the internal microcontroller flash or performing boundary scan operations the JTAG CON connector can be used and the switches can be configured to accomplish the desired task For information on programming the internal flash of the on board microcontroller refer to the MMC2107 microcontroller user manual and board schematic For most purposes having the complete JTAG chain is sufficient Figure 1 shows the complete chain as well as what order the devices appear during boundary scan Table 1 shows the pinout of the JTAG connector Connect any JTAG cable to the connector to perform all operations Note the JTAG chain changes depending on the swit
29. RING3 3_ lt 8 TPOS303_ lt 8 8 TCLK303_ lt 8 RTIP3O3 8 RRING303 8 TPOS303_ lt 8 TNEG303 8 TCLK303_ 8 1 1 Q a DS 26303T TTIP 1 45 RTIP RRING TNEG GNDT TPOS TDATA TTIP TRING RPOS RDATA RNEG CV U6 PORT DS26303 URLM RCLK 45 1g TIIP303_ lt 8 1 gt 46 1 TIRING303 8 1 40 14 RPOSSOS DUT 8 1 411 RNFG303_DUT lt 8 1 l 39 RCLK3 3 DUT lt 8 1 gt TTIP 2 52 RRING TNEG TCLK VDDT GNDT TPOS TDATA TTIP TRING RPOS RDATA RNEG CV 065 PORT DS26303_URLM RCLK 52 2 TTIP303_ lt 8 1 gt 51 3856 3 8 1 gt ERES RPOS303_DUT lt 8 1 33 2 g EM 34 2 RNEGSOS DUT 8 1 gt 32 2 RCLKSOS DUT 8 1 3 8 RRING3 3_ lt 8 TPOS303_ lt 8 TNEG3 3_ lt 8 TCLK3O03 8 RTIP3O3 8 RRING303 8 TPOS3 3_ lt 8 TNEG303 8 TCLK303_ lt 8 1121 IQFP DS26303T TTIPO3 57 RTIP RRING TPOS TDATA TNEG TCLK VDDT GNDT TTIP TRING RPOS RDATA RNEG CU i RCLK PORT DS26303 URLM 57 5 8 1 TRING3 3_ lt 8 1 7 3 4 RPOSSOS DUT 8 1 76 3 RNFG303_DUT lt 8 1 78 34 RCLK3O0S DUT 8 1 5 1122 TQF P DS 26303T TTIPOA 64 RTIP RRING TPOS TDATA TNEG TCLK VDD
30. T GNDT TTIP TRING RPOS RDATA RNEG CV He RCLK PORT DS26303_URLM 54 4 TITIP303 8 1 53 4 TRINGS 3_ lt 8 1 gt 70 RPOS303_DUT lt 8 1 gt 59 4 RNEG3OS DUT 8 1 gt 4 RCLK3OS DUT 8 1 gt TITLE DS26303 PORT 1 4 DATE ENGINEER PAGE 3 C AST ee RTIP303_ lt 8 RRING303 8 TPOS3 3_ lt 8 TNEG303 8 TCLK303 8 RTIP303_ lt 8 RRING3 3_ lt 8 TPOS303_ lt 8 TNEG3 3_ lt 8 TCLK303_ lt 8 TTIP S 17 53d 55 150 20b oS 181 nilo 5 108 02 oS 109 125 107 q 116 119 TTIP TRING RPOS RDATA RNEG CU RCLK TPOS TDATA TNEG TCLK VDDT GNDT U6 PORT DS26383_URLM 117 5 TTIP303_ lt 8 1 gt 118 s TRING3 3_ lt 8 1 gt 111 5 RPOS303_DUT lt 8 112 5 RNFG303_DUT lt 8 110 5 RCLK303_DUT lt 8 TTIPO6 124 1 gt 46 127 D es 126 r s 101 i 6 102 gt 26 100 4 125 122 TRING RPOS RDATA RNEG CVU RCLK TPOS TDATA TNEG TCLK VDDT GNDT U6 PORT DS26303_URLM 124 6 TTIP303_ lt 8 1 gt 123 TRING3 3_ lt 8 1 gt 104 RPOS303_DUT lt 8 105 RNFG303_DUT lt 8 103 6 RCIK303_DUT lt 8 1 1 1 RTIP303_ lt 8 RRING303 8 TPOS303 8 TNEG303 8 TCLK303 8 RTIP303_ lt 8 RRING303 8 TPOS303_ lt 8 TNEG3 3_ lt 8 TCLK303 8 129 TTIP TRING RPOS RDA
31. TA RNEG CU TPOS TDATA TNEG U6 TCLK RCLK UDDT PORT GNDT ps26303 URLM 129 0 8 1 130 7 TRINGSO3 8 1 gt 5 RPOSSO3 DUT 8 1 4 RNEG3O03 DUT 8 1 gt 6 RCL K303_DUT lt 8 1 gt 165 TQFP a 5 26303T 136 1 gt 139 iL 8 138 58 ed B 144 8 2 q 137 134 RTIP RRING TPOS TDATA TNEG TCLK UDDT GNDT TTIP TRING RPOS RDATA RNEG CU 5 RCLK PORT DS26303_URLM 136 _ 8 1 135 TRING3 3_ lt 8 1 gt 142 RP0S303_DUT lt 8 1 gt 141 RNFG303_DUT lt 8 1 143 RCLKS3OS DUT 8 1 TITLE DS26303 PORT 5 8 DATE ENGINEER PAGE 4 _ e ITIPSO3 8 1 14 ITIPSO3 1 154 CONN_SMB 78 OHM VERT 7593 9087 BS CONN_BNC_SP c 7380 CONN_BNC_SP 129 1 1 CN TRING3 3_ lt 8 1 gt gt RTIP303_ 8 1 6 5 1638 CONN SMB 75 OHM VERT CONN_BNC_SP 26 J22 RTIP303_ lt 8 1 gt TRING3 3_ lt 8 1 gt dg 1 RRING3 3_ lt 8 1 gt 162 CONN_SMB 7S OHM VERT CONN_BNC_SP TTIP303_ lt 8 1 gt J31 d L_
32. _ RRING303 8 1 gt TTIP303_ lt 8 1 gt 62 CONN_ SMB 7S OHM VERT CONN BNC SP J35 1 e st th I61 CONN_SMB 7S OHM VERT CONN BNC SP J27 e RTIP303_ lt 8 1 gt ING3 3_ lt 8 1 gt TITLE e RRING303 8 1 gt LIU INI DATE ERFACE PORT 5 8 ENGINEER PAGE 6 55 4 2 05303 8 1 D4 11 LED_RLOS1 2 1109 14 5 7484 AAA 2 SCAN MODE BIAS R15 R130 1 2SCANMODE3 3 1 INT303 5 115 156 I101 D3 5 5555 RED R101 MCLK3 3 1 2 MCLK_FPGA d R13 CLKAZZZ 1 A44 FPGA_CLKA 33 R104 RLOS3O03 8 1 1 2 FPGA_TECLK 175 014 05 1 a LED RLOS1 RLOSCON 1 2 205 0 7400 FPGA_CLKA CoNNLBNC_SP Y CLOCK A FPGA_TECLK v coNNL 8Nc_sP Js lc TECLK ON BOARD OSCILLATORS 5 An 211 Y1 155 2 2 5 OU NTH 39A 2 0480 YS osc UCC 5 AAA 2 1 33 CONN BNC 695 1 USER CLK TITLE RLOS INT and L EDs ENGINEER PAGE gt NEM DENEN JDS303O0UT SPI PRO RCLKENABLE_BERT RCLKIN_BERT pat TDO 3 2
33. al Data Bit 5 13 A2 Local Address Bit 2 14 D6 Local Data Bit 6 15 A1 Local Address Bit 1 16 D7 Local Data Bit 7 17 A0 Local Address Bit 0 18 CLKE SPI Clock Edge Select 19 MUX Mux 20 RDY Ready Handshake from LIU 21 CSFPGA Chip Select FPGA 22 OE Output Enable LIU 23 CSBERT Chip Select DS2174 24 MOTEL Motorola Intel Select 25 CSLIU Chip Select DS26303 26 INT Interrupt for DS26303 27 ALELIU Address Latch Enable 28 FPGAEN FPGA Enable Pin 29 RD Read Signal 30 UIN1 User Input 1 31 WR Write Signal 32 UIN2 User Input 2 33 MODESEL Mode Select 34 36 3 3V Board 3 3V 35 Not Used 37 40 GND Ground DS26303 Design Kit Telecom Clock and Data Test Points The DS26303DK has high impedance test points for all the telecom signals that are related to the LIU These signals are split up by port number and marked with easy to read silkscreen labels Table 3 shows the telecom connector for port 1 The pinout for this connector is repeated for all 8 ports Table 3 Telecom Connector Pinout PIN NAME FUNCTION 1 TCLK Transmit Clock Input 2 4 6 8 10 12 1 GND Ground 3 RCLK Receive Clock Output 5 TPOS Transmit Positive Data Input 7 9 RPOS Receive Positive Data Output TNEG Transmit Negative Data Input 11 RNEG Receive Positive Data Output 13 RLOS Receive Loss of Signal Output Note that the input signals in the telecom connector go from the connector to the on board FPGA then to the
34. ch SWA The ONCE location of SW4 is used for programming the on board microcontroller only Table 1 JTAG Connector J6 Pinout PIN NAME 1 JTDI 2 4 6 7 GND 3 JTDO 5 JTCLK 8 ALIGN KEY 9 BRD RST 10 JTMS 11 BRD V3 3 12 JDE 13 N C 14 JTRST 7 of 43 DS26303 Design Kit Figure 1 DS26303DK JTAG Chain SW4 U6 n ON BOARD FLASH MEM FLASH MEM uC FOR FPGA FOR SPI ONCE SW4 JTMS Address Data Bus Connector The DS26303DK has a connector J1 to monitor all local bus activity for the design kit All the signals can be captured with a high impedance probe and displayed on an oscilloscope or logic analyzer Note If the FPGA switch SW5 is in the OFF position the on board microcontroller will no longer drive any data onto the local bus Therefore the user can now connect the local bus of the DS26303 into another system without making any modifications to the hardware See Table 2 for specific pin information for connector J1 Table 2 Address Data Connector Pinout PIN NAME FUNCTION PIN NAME FUNCTION 1 A8 Local Address Bit 8 2 DO Local Data Bit 0 3 AT Local Address Bit 7 4 D1 Local Data Bit 1 5 A6 Local Address Bit 6 6 D2 Local Data Bit 2 7 5 Local Address Bit 5 8 D3 Local Data Bit 3 9 A4 Local Address Bit 4 10 D4 Local Data Bit 4 11 A3 Local Address Bit 3 12 D5 Loc
35. e 0 75 nylon standoff and 0 25 nylon screw 4 40KIT2 J1 1 40 pin terminal strip dual row vertical 2 1mm 5 5mm CUI Inc J2 1 Power jack right angle PC board mount closed PJ 002AH frame high current 24V DC at 5A J3 1 Black single right angle Type B N Spa J4 1 right angle connector short case 5 SMB connectors AMP LEM d 500 vertical gold 413990 1 J6 J9 J17 10 14 pin headers dual row vertical J18 J19 J20 3 100 mil 3 position jumpers NR J37 J44 8 2 headers 0 100in centers vertical J45 J46 2 8 pin 4 port RJ45 jacks right angle m L1 1 1 0uH 20 2 pin SMT inductor r 3 of 43 DS26303 Design Kit SUPPLIER DESIGNATION QTY DESCRIPTION PART NUMBER Resistors 0603 Pi 3 DO NOT POPULATE R2 R14 R26 R28 R32 R43 R46 R50 R52 54 R57 R63 R66 R68 R69 R71 Panasonic R72 R73 R76 57 10 5 1 16W resistors 0603 ERJ 3GEYJ103V R77 R82 R85 R86 R88 R91 R93 R96 R97 R130 R3 R9 R11 R12 R13 R29 R31 R44 R45 R60 R61 R62 R78 Panasonic R79 R94 R95 36 330 5 1 16W resistors 0603 ERJ 3GEYJ330V R98 R102 R104 R117 R120 R121 R124 R129 R10 1 22 5 1 16W resistor 0603 ERJ 3GEYJ223V R27 R67 R70 R74 R75 R80 Panasonic R81 R83 R84 12 3300 5 1 16W resistors 0603 ERJ 3GEYJ331V R89 R90
36. j 5 4 2 5 Signal Cross Reference for the entire design ADDRESS_BERT_ lt 3 gt 808 1164 ADDRESS_LOCAL_ lt 8 gt 267 1006 1595 CCLK_A 9B1 lt 9B3 lt gt CFG_DIN_A 981 gt 10B3 lt gt cLke3es 2B3 7 4 lt CLKE303 2B3 19A3 lt gt 15B4 lt gt CLKOUT 1007 13D3 CLKOUT_MM2107 13C1 lt gt 1304 0980 13C1 lt gt 14D3 1406 lt CS2_BOARD 19A4 lt gt 13C1 lt gt 2B7 1 10 7 lt 15 3 16AB lt CSFPGR 1 B7 lt gt 1583 CS BERT 1 B7 lt gt 15036 DATAS 3_ lt 7 gt 263 1185 15B4 16B8 DATA_ lt 7 gt 8B5 1 1205 DONE_FPGA_A SA3 lt 9B1 lt 9B3 lt gt E1 CLK 7B1 lt 11D6 lt EB 1 A4 lt gt 13D3 1403 EB1 10846 1303 14D7 lt FLASH UPP 13D7 1497 gt FPGA_CLKA 7D3 18C3 lt gt FPGA_EN 1 B7 lt gt 14AB lt gt 15B3 lt gt FPGA_TECLK 7BS lt 7C3 lt 7D3 lt gt 10B3 lt gt INT3O3 2B3 7 8 705 10 3 15 INTERUPT 1983 gt 1 2 JDE_B 12B2 138142 JDS3030UT SPI PROM IN 287 BA2 lt BD3 JFLASHOUT_FPGAIN SB1 SC3 JFPGROUT DS3031N 2A7 lt SC3 JTCLK 2B7 BD3 SB3 SC3 12B2 lt 12C3 lt gt 13B2 JTDI 12C3 lt gt 1302 JTDO 1 BD3 12 4 JTMS 2A7 lt BD3 9 3 9C3 lt 12 1 lt 12C3 lt gt JTMS MIC 12B2 12C4 13B2 lt gt JTRST B 2B7 12B2 lt gt 1 2 LED_RLOS1 4 707 gt MCLK303 2
37. p of the timing for a SPI bus For this case all data is clocked into the slave device on the rising edge of SCLK This feature can be configurable on the DS26303 Figure 2 SPI Timing Diagram bad Isb adrs Isb msb msb WRITE ACCESS ENABLED SDO Figure shows a simplified diagram of the XC18V00 device and the 0526303 in SPI serial mode Notice a few key points about this diagram First the CLK for the XC18V00 is the MCLK for the LIU but this is not the SCLK for the SPI interface The SCLK can be programmed as needed See Table 5 for an example of the memory map Second the programming for this device begins when OE on the XC18V00 goes high Therefore consideration must be taken if some delay is necessary Generally it is sufficient for the OE pin to be connected to some power up delay device The OE delay is not necessary on this DK 10 of 43 DS26303 Design Figure 3 SPI Configuration with PROM 18 00 SCLK PROM DS26303 OE CLK Table 5 Configuration Memory 0x00 1 0 0 Start of Write Cycle 0x01 0 0 0 Bit A0 0x02 0 1 0 Always a 0 for a write wes 14 19 11 T oor 0 Ss Y sas X 0 sat 1 2 Bit DO LSB gto T ane T T w T T eje
38. scillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 Drive Logic 0 0x16 0xFF 20 of 43 DS26303 Design Kit DS26303 INFORMATION For more information about the DS26303 refer to the DS26303 data sheet available on our website at www maxim ic com DS26303 DS26303DK INFORMATION For more information about the DS26303DK including software downloads go to www maxim ic com DS26303DK TECHNICAL SUPPORT For additional technical support e mail your questions to telecom support dalsemi com SCHEMATICS The DS26303DK schematics are featured in the following 22 pages 21 of 43 Maxim Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Dallas Semiconductor product No circuit patent licenses are implied Maxim Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corporation Da FA COUER DS26303 CONI 0526303 PORT DS26303 PORI IU INT
39. stiachinecibeneeninatacasbssectia Re kj vid kn 12 ID REGISTER uu ul ll T 13 CONTPOLRESISTERS 13 D52650 NRORMA TON uuu u k 21 DS26303DK INFORMATION 8 8 21 TECHNICAL SUPPORT u 21 SCHEMATIC t R 21 2 of 43 DS26303 Design Kit COMPONENT LIST DESIGNATION QTY DESCRIPTION C1 C4 C6 C7 C18 C24 C26 C34 C36 C37 C38 C41 C43 AVX C47 C49 C50 53 0 1uF 20 16V X7R ceramic capacitors 0603 0603YC104MAT C51 059 059 61 83 C85 C86 C90 C2 C3 C22 C30 C35 C40 C42 Panasonic C48 C52 C60 13 1 10 16V ceramic capacitors 1206 ECJ 3YB1C105K C84 C88 C89 C5 C9 C19 C21 Panasonic C27 C28 C87 7 10 20 10V ceramic capacitors 1206 ECJ 3YB1A106M C8 1 6 8uF 10 6 3V X5R ceramic capacitor 1206 E s EER C10 C17 8 470pF 10 100V ceramic capacitors 0603 4 for C20 C23 C25 Panasonic C91 C92 5 68uF 20 16V tantalum capacitors D case ECS T1CD686R C29 C31 C39 3 22pF 5 25V ceramic capacitors 0603 C32 C33 2 10pF 5 50V ceramic capacitors 1206 tall case 01 012 2 Green LEDs SMD D2 D11 10 Red LEDs SMD duris D43 D14 D15 3 1A 40V Schottky diodes H1 H4 4 KIT 4 40 hardware Not applicabl
40. t TCLKIN BERT BB8 1095 gt 1588 TCLKOUT BERT BDS lt 10 6 1588 TDAT_BERT 5 1076 gt 1588 TEA 10A3 lt gt 13D7 lt gt TEST 13636 1 13A3 lt 13D3 14B5 TNEG3U3 8 1 4 lt 3BB lt 3C4 3CB 4 4 lt 4BB lt 4 4 lt 4CB 1105 1565 1568 1503 gt 1506 1508 TPOS3US 8 1 3B4 3BB lt 3C4 lt 3CB 4 4 lt 4BB lt 4C4 lt 4CB 1187 1565 1568 1503 gt 1506 15D8 TRING303 8 1 3B1 gt 3B5 36012 3C5 gt 4B1 4B5 gt 4C1 gt 465 SB1 SB5 SD1 505 gt 6B1 gt 6B5 6D1 gt BD5 TTIP3US 8 1 381 3B5 gt 3D1 gt 305 gt 4B1 gt 4B5 gt 4 1 465 5 1 5 5 501 gt 505 gt BB1 685 gt 6D1 gt BD5 TXE_USB 10B3 12 5 lt USER_CLK 7R2 1 C7 lt USER_IN1 1382 1 15B3 lt gt USER_IN2 13A2 lt 13B3 lt gt 15B3 lt gt USER LED1 13A2 lt 13B3 lt gt USER_LED2 13A2 lt 13B3 lt gt UDDSYN 1306 UDUT_CON 17D4 lt gt 1B8A7 lt gt USSSSYN 13A4 lt WR_USB 10A4 lt gt 1285 XTAL 13A3 lt gt 13B2 lt gt TITLE DATE ENGINEER PAGE dp s o dr poe 2 Part Cross Reference for the entire design JMP_OPEN_2P 686 RES1 2 JMP_OPEN_2P RES1 1484 1785 575 JMP_OPEN 2P 603 RES1 17B7 sns RJ45_B 5 4 5B8 504 508 RES1 705 1785 1792 RJ45 B 4 688 504 508 RES1 1391
41. xOF HI Z 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 TCLKBERT OUT 0x16 OxFF HI Z 15 of 43 DS26303 Design Kit Register Name BRCLK Register Description BERT RCLK SOURCE Register Offset 0 0 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 DO Bits 7 to 0 D7 to DO These bits control the source of the RCLK for the BERT BTCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 HI Z 0x09 HI Z OxOB HI Z OxOC HI Z OxOD HI Z OxOE HI Z OxOF HI Z 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26303 0x14 TECLK DS26303 0x15 TCLKBERT OUT 0x16 OxFF HI Z 16 of 43 DS26303 Design Kit Register Name BRDAT Register Description BERT RDAT SOURCE Register Offset 0x0D Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Bits 7 to 0 D7 to D0 These bits control the source of the RDAT for the BERT Note that the DS26303 must be in single rail mode for BERT to function properly BRDAT DESCRIPTION 0x00 RPOS Port 1 0x01 RPOS Port 2 0x02 RPOS Port 3 0x03 RPOS Port
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