PCI Express 2.0 Mid-Bus Probe for Summit T24
Contents
1. 6 UL Arropen Oo toit ido de iota dou nde ein UA Uh MS e M UE 6 De MODUS T TODE RANON esas EUR URINE EI IU ME IINE RE DI I ea INE 11 3 9 Probe Comecon To ANa Or Eer dri thasd se turtur b dre ha ote qup A 11 3 4 PODS Keepout VOLU cuiaedodae nose e Enn Oxused hup idead ei RM n Dx pa e a E 11 33 Reference Clock Probe AUachmelttssuai ee tea adatta a op ied e and 12 4 ELECTRICAL DESIGN zen osse ligand tenet act elon eel aa MEM e UI E 13 Hed Probe TOGGING Beca ie e nexum odd edid A tne ect 13 4 2 Overview of Probe Pin Assignments esses senes 15 4 3 Pin Assignments for X1O Lane Widths iusso visus ei eer Pini ri UR 14 44 Pin Assignments for x8 Lane Widths ue vr el I ER AU 16 4 lt PIN ASSioninentS fOr x4 Lane Widihs aixsidseivt n ER ERRSEREC IRR HG Ye ES 17 40 Pin Assignments for x2 Lane Widths scien aie 16 qu PICAS NMEN S OP AT Tane WIGS uet dot dut ote diste 19 5 INSTALLATION OF THE UNIVERSAL 2 PIECE GEN2 MID BUS PROBE RETENTION MODULE 20 5 1 Attaching the Probe head to the Retention Module eese 22 AE GU Lr EE 24 5 2 1 iPass XA tO X8 Sifaignt Caple mac cR 24 5 2 2 Half size Gen2 Mid bus Probe Cable and Header Assembly sesseuuuuse 24 5 2 3 Reference Clock Cable iere aer bera Ur a aware riage Leute S du Needed o dirste o Los pd pa a tans 25 5 2 4 Daisy Chali Gale mace Ic tee eee 25 6 DUAL PROBE POD SETUP USING EXTERNAL CLOCKING ssscccecceccccceeene2. Cin Upstream Cis cin Downstream 11 GND BENE S 16 nc 155 no 18 nc 17 GND Signal Name 18 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 7 Pin Assignments for x1 Lane Widths For x1 lane widths a half size header can be used The diagram below shows the recommended pin assignments for x1 configurations x1 Bi directional Mid Bus Probe Pinout on a Full size Header Pin Signal Name Pin Signal Name 2 GND t Cop Upstream o Downstream Ss COn TUE 4 fco E a s p 7 GND 19 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 5 Installation of the Universal 2 piece Gen2 Mid bus Probe Retention Module The Teledyne LeCroy Universal Retention Module is designed for use in Gen2 or Gen1 mid bus probe applications The module comes in two sections which allows the same module for either full size or half size mid bus probe footprints In this example we will illustrate the steps to install the module using the full size footprint as an example Please note that in the illustrations a full size header is shown The Gen2 Mid bus Probe kit for the summit T24 uses a half size header but the steps for installation are the same 1 Ensure that the probe footprint on the target PCB is clean and free from obstructions 2 Align one of the pair of identical module ends into the pin hole at one en
3. port on the second pod The setup is shown below Probe Pod Ref Clock In Ref Clock Out Ref Clock In o cR Sh Probe Pod A A 3 Pin Header Target System Board 26 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 7 Recording Traffic Once you have set up the mid bus probe please note that the Break Connection button in the al analyzer software does not function This button is intended for use with the Teledyne LeCroy interposers that have link disconnect functionality Gen1 slot interposers For instructions on setting up and implementing a recording please refer to the analyzer user manual 2 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 8 Ordering Information Use the following table of part numbers and descriptions to order components of the Mid bus probes Gen2 Analyzer Mid bus Probes PEO82UIA X Mid bus Pod one 1 G2 Mid bus pod and one 1 power supply Gen2 Half size Mid Bus Probe Kit includes one 1 Gen2 Mid Bus Pod one 1 iPass x4 o x8 straight cable one 1 Ref Clock Cable one 1 Half size Mid Bus Probe cable power supply and one 1 Universal retention module Gen2 Half size Mid Bus Probe Cable one 1 Gen2 Half size Probe Cable connects to Mid bus box PEO76ACA X Universal retention module Gen1 or Gen2 1 piece 2 halves PEO13UCA X x4 to x8 Straight iPass Cable for Summit T24 T2 16 T28 T3 8 or T3 16 1 meter PEO14UCA
4. to avoid excessive loading conditions the Teledyne LeCroy mid bus probe employs high impedance tip resistors isolation resistors The probe isolation resistance is selected to both satisfy the probe sensitivity and system parasitic load requirements Extensive care has been taken to reduce the parasitic effect of the probed signals during each phase of the mid bus probe design An equivalent Spice model is available via the Teledyne LeCroy Protocol Systems Group support team psgsupport teledynelecroy com With this unique design the Teledyne LeCroy mid bus probes can capture bus traffic signals with amplitudes specified by the PCI Express standard while introducing only the loss and added jitter that are within the recommended specification in the PCI Express Mid Bus Probing Footprint and Pinout 4 2 Overview of Probe Pin Assignments Cross references from the PCI Express Mid Bus Probing Footprint and Pinout 8 05 03 Revision 1 0 are given in tables listed below In the pinout tables that follow the following variations may be applied e he designation of upstream and downstream may be reversed as long as it is reversed for every lane all upstream connections on the left and all downstream on the right may be swapped e Lane ordering may be reversed if done as a whole such that probe lanes 0 1 2 3 connect to physical lanes 3 2 LU e Each differential signal pair may have the D and D assignment reversed e f the Gen2 footpr
5. 0 03037 TYP pre 0 032 0 003 0 032 _ mete Pin G2 GND l Plated Thru Hole Non plated Thru Hole 0 073 Pad Both Sides Keepout Volume To allow access to r S thumb screws Not to scale f a 0 40 4 090 gt Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 A typical layout of a mid bus footprint might look something like the following two pictures Geni Mid Bus Layout Gen2 Mid Bus Layout PCB Layout 10 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 3 2 Mid bus Probe Retention To prepare a circuit board for PCI Express mid bus probing the mid bus footprint has to be laid out onto the target system board and a retention module has to be attached to the board Retention module attachment is simple and quick There are four through hole pins as part of the footprint design two on each end of the footprint The two holes of the Teledyne LeCroy universal retention module fit on each end of the footprint see installation section 5 The probe aligns to the retention module with four alignment pins two on each side and attaches securely with thumbscrews that fasten into the retention module holding the probe pins firmly in connection with the exposed pads of the footprint designed into the PCB The retention module should not be confused with a PCB connector because it is not part of the electrical circuits of either the target system or the probe With th
6. TELEDYNE LECROY Everywhereyoulook Protocol Solutions Group 3385 Scott Blvd Santa Clara CA 95054 Tel 1 408 727 6600 Fax 1 408 727 6622 U PCI Express 2 0 Mid Bus Probe for Summit Analyzers Installation and Usage Manual Manual Version 1 0 February 2014 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Document Disclaimer The information contained in this document has been carefully checked and is believed to be reliable However no responsibility can be assumed for inaccuracies that may not have been detected Teledyne LeCroy reserves the right to revise the information presented in this document without notice or penalty Trademarks and Servicemarks Teledyne LeCroy and Summit T2 16 Summit T3 16 Summit T3 8 Summit T28 and Summit T24 are trademarks of Teledyne LeCroy Microsoft and Windows are registered trademarks of Microsoft Inc PCI Express and PCle are registered trademarks of the PCI SIG All other trademarks are property of their respective companies Copyright 2014 TeledyneLeCroy All Rights Reserved This document may be printed and reproduced without additional permission but all copies should contain this copyright notice Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Table of Contents 1 INTRODUC ON S Iu GUINEA III MX III LM 4 2 PROBE COMPONENT pop M 5 3 n uize P M MILII
7. X Reference Clock Cable for use with x4 Multi lead Pod and Mid bus Pod 28 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Appendix A How to Contact Teledyne LeCroy Type of Service Call for technical Support PSG Support Hotline 1 408 653 1260 Worldwide 1 408 727 6622 Write a letter Teledyne LeCroy Customer Support 3385 Scott Blvd oanta Clara CA 95054 psgsupport teledynelecroy com Visit Teledyne LeCroy s web site teledynelecroy com 29
8. able Assembly D Mid Bus Probe Pod C Analyzer Cable E Power adapter for the Probe Pod F Clocking Cable Assembly not shown The Intel based mid bus footprint specification only supplies differential lane signaling and ground reference Should a reference clock RefClk be required a separate connection must be made Teledyne LeCroy PCI Express protocol analyzers can use a reference clock probe in conjunction with the mid bus analysis Each mid bus probe is equipped with one clock probe The mid bus reference clock probe is designed to facilitate capturing clock signals from the system board in the two configurations recommended by the Intel guideline i e a tap off of an existing clock or a dedicated clock 7 TELEDYNE SFINTE TZA m m PCI Express target board A with Mid Bus Probe B C and D Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 3 Mechanical Design This section describes footprint dimensions keepout volumes and probe pin assignments 3 1 Probe Footprints The Summit T24 Mid bus Probe is fully compatible with the standardized mid bus footprint recommended by the Intel guideline as shown in the following figures Gen1 Full size Mid bus Probe Footprint Pin 1 Pin 47 1 340 1 180 0 9055 UUUUUUUUUUUUUUUUUUUOUUUE Mey iN00000000000000000000g8 0 a ps 53 gt M 0 03937 TYP CI PS 20 032 i
9. d lane widths e g x1 and lane widths up to the maximum footprint size In the photo shown on page 6 the footprint occurs on the target board at B Note that this manual documents the mid bus footprint used for Gen1 and Gene applications the probe footprint for Gen3 is covered in the PCI Express 3 0 Mid Bus Probe User Manual Teledyne LeCroy makes two versions of mid bus probes one for Gen1 2 2 5 and 5 GT s data rates and one for Gen3 2 5 5 and 8 GT s data rates This manual covers only the Gen2 mid bus probe See other user manuals for the other mid bus probes The Gen2 mid bus probe is intended for use with the Summit Analyzers and is available with a half size probe or full size probe The half size probe is shown on page 6 It has a two strand ribbon cable and a connection header B Note that a half size footprint supports only up to x4 lane widths The part numbers and components of the Teledyne LeCroy Summit T24 Gen2 mid bus probe kit which is also compatible with Gen1 are as follows PEO081ACA X Gen2 Mid Bus Probe x4 Lane Width Half size Module which includes PEO13UCA X iPass x4 to x8 Straight Cable PEO71UIA X Mid Bus Pod for Summit T24 incl power supply PEO75ACA X Mid bus Probe Cable x4 PEO14UCA X Reference Clock Cable PEO76ACA X Universal Retention Module Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 2 Probe Components Universal Retention Module B Mid Bus Probe Header C
10. d of the probe footprint Note that the module end has two sets of pins the short pins should face out and the longer pins are inserted into the PCB 3 Insert the module end into the PCB 20 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 Turn the board over to ensure that the pins from the module end are visible and accessible on the bottom surface of the board Note the pins of the Universal Gen2 Retention Module are intended to accommodate PCB thicknesses up to 125 mils 3 175 mm 5 With the module held firmly against the front surface of the board solder the two pins into position allowing solder to wick down into the solder hole When the solder has set trim the excess length of the pin flush with the board surface 6 Turn the board right side up and align and inert the second module end into the opposite end of the footprint 7 Repeat steps 4 and 5 for soldering the second module end 21 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 5 1 Attaching the Probe head to the Retention Module The probe design is not keyed to allow probing of different mid bus signal assignments The probe head has labels indicating side A Upstream and side B Downstream Side B also has an LED indicator to show connection Side A must face odd numbered pins 1 3 5 and side B must face even numbered pins 2 4 6 1 Insert the probe head into the retention modu
11. ds l 0 001 0 029 0 003 Non plated Thru Hole Plated Thru Hole 0 053 Pad Both Sides Keepout Volume li 050 To allow access to thumb screws Not to scale LJ 0 023 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Gen2 Full size Mid bus Probe Footprint Pin 1 Pin 47 1 340 Pin G1 GND 1 180 0 98425 _ _ gt M ae D iw F 0000000000000000000000000 LAW TB soooooooooooooo0000000905 o Suse 0 107 0 032 0 003 Plated Thru Hole 0 073 Pad Both Sides i e Les 1221825222342 522 Ez LER ER TT Pin 48 000 lt 003937 TYP Pin G2 GND i 0 032 0 001 Non plated Thru Hole i 0 120 Pad Detail Keepout Volume To allow access to k i pos thumb screws Not to scale t Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 A typical layout of a mid bus footprint might look something like the following two pictures Geni Mid Bus Layout Gen2 Mid Bus Layout PCB Layout Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Gen2 Half size Mid bus Probe Footprint Pin 1 num Pin 423 Pin G1 GND i 0708 M 05118 gt 2 N Pad Detail 5 Tm 1 H H t T H i H Li 3 1 i esessose S Pin 24 0 002 Pi
12. e use of a retention module the requirement to have a keep out area on the backside of the board is eliminated Retention modules can be purchased through Teledyne LeCroy e Half size or full size P N PEO76ACA X Universal Retention Module 3 aye gl C 7 Connected PCI Express Midbus Probe ax2 SGT S 4x5 eme 7 4 e XM ER e a j n L r r 1 B21 774 00 A m F nr en al een ali J 3 3 Probe Connection to Analyzer The bus signals captured by the mid bus probe are connected to a mid bus probe pod for amplification This reduces the load imposed by the mid bus probe on the target system while allowing a longer cable to attach to the Teledyne LeCroy PCI Express protocol analyzer The Teledyne LeCroy PCI Express protocol analyzer can then interpret these signals for full decoding and protocol analysis 3 4 Probe Keepout Volume As with any connection to a PCB sufficient clearance must be allowed around the point where the probe will connect This is defined as the keep out volume which must be kept clear of other components mounted on the PCB The probe keepout volumes are shown in the diagrams in Section 3 1 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 3 5 Reference Clock Probe Attachment Should SSC clocking be used in the system under test or if the link varies the bit rate by more than 300ppm a reference clock tap may be required The connection from the reference cl
13. eenennnnneeeeesesenensesseenaeeeeenanaaseeneees 26 7 RECORDING TRAR IO rie cane sme dd t M M E LM eee LI US 27 8 ORDERING INFORMATION pet 28 APPENDIX A HOW TO CONTACT TELEDYNE LECROY sero p opera unu a ara aa uana aaa Ra RaR RR RE E RERER RES E RES ERERSR RE nna 29 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 1 Introduction Teledyne LeCroy offers a wide variety of ways to connect PCI Express protocol analyzers to products under test There are four common methods Interposers Specialty Probes Mid Bus Probes and Multi lead Probes If the product uses a standard PCI Express card connector an interposer is used which is inserted between the PCle Card and the card slot The interposer taps off the data traffic to allow the analyzer to monitor and record traffic with minimal perturbation of the electrical interface Specialty probes are used with specific card configurations and are used in the same manner as an interposer card in fact a specialty probe is an interposer card designed for a specific interface LeCroy supports a range of specialty probes including ExpressCard AMC XMC ExpressModule and HP Blade Server interfaces If the product has an embedded PCI Express bus e g a bus which runs between chips on the same circuit board then either a mid bus probe or a multi lead probe can be used The mid bus probe requires a connection footprint see below to be designed in
14. int is used an additional ground pin is present above Pin1 and below Pin 24 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 3 Pin Assignments for x16 Lane Widths For x16 lane widths two full size headers are required The diagrams below show the recommended pin assignments for x16 configurations keep in mind that any of modifications mentioned in Section 4 2 can be applied and in addition the lane swizzling feature of the Summit T3 16 and T2 16 systems noted in Section 4 2 x16 in Two Unidirectional Footprints Mid Bus Probe Pinout on two Full size Headers Summit only Signal Name Pin Signal Name i Signal Name Pin Signal Name 2 J OI DJ OJ CJ DU or T nar E B20 GND B22 x co LJ recen A unidirectional x16 configuration can be implemented using one full size header utilizing the pinout diagram on the right for upstream traffic or the diagram on the left for downstream traffic 14 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 x16 in Two Bi directional Footprints Mid Bus Probe Pinout on two Full size Headers Summit only Signal Name Pin 15 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 4 Pin Assignments for x8 Lane Widths For x8 lane widths one full size header is required The diagram below shows the recommended pin assignments for x8 configurations keep in mind that any
15. le and carefully tighten the two thumbscrews The thumbscrews should be screwed in only finger tight Caution The probe is delicate equipment Please tighten the thumbscrew carefully while watching the LEDs on the probe pod Over tightening the probe header might damage the miniature probing spring pins 2 Connect the other side of the probe cable to the mid bus probe pod ports marked A 0 3 and B 0 3 The mid bus probe pod amplifies the signal and sends it to the analyzer The PCle 2 0 Gen2 probe pod is shown on next page 22 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 Analyzer a ose PCI Express Midbus Pod CLK In 8x2 5GT s 8x5 0GT s Ex x1 an js E A 4 7 3 If you intend to use the analyzer s reference clock connect the three pin clock cable to the port marked CLK In Reference Clock In on the mid bus probe pod Connect the other end of the clock cable to the three pin reference clock header on the PCI Express board Orientation of the cable does not matter 4 Connect the wider end iPass x4 to x8 analyzer cable to the pod port marked Analyzer Connect the other side of the cable to the Summit T24 analyzer 23 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 5 2 Cables The following cables are used 5 2 1 iPass x4 to x8 Straight Cable 24 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 5 2 3 Refe
16. ock to the analyzer is a 3 pin header 1 by 3 0 050 center spacing which is placed on the clock signal transmission line of the DUT The PEO14UCA X Reference Clock Cable provides a three pin micro socket that connects from this header to the CLK IN port on the Mid Bus Pod If the reference clock is sampled by tapping off an existing clock the header shall be located on the existing clock transmission line where a high impedance clock probe from the mid bus probe is connected with no significant loading effects In the case of a dedicated clock the header shall be located at the end of a dedicated clock transmission line without termination where a 50 Ohm cable is connected and the termination for the clock signal is provided on the mid bus probe board The connectivity of the clock header pins follows the following table Signal PinNumber REFCLKp REFCLKn 3 or 1 Note that the analyzer is not sensitive to the polarity of the reference clock Therefore the probe can be plugged onto the pin header in either orientation The following 3 pin header can be used for the reference clock Samtec Part No TMS 103 Vertical Orientation Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 Electrical Design 4 1 Probe Loading Effect The logical probing of the PCI Express bus is achieved by tapping a small amount of energy from the probed signals and channeling this energy to the analyzer In order
17. of modifications mentioned in Section 4 2 can be applied and in addition the lane swizzling feature of the Summit T3 16 and T2 16 systems noted in Section 4 2 x8 Bi directional Mid Bus Probe Pinout on a Full size Header Pin Signal Name NM Pin Signal Name 1 6 COn Downstream 5 GND 8 GND 7 Cip Upstream 10 Cip Downstream 9 Cin Upstream Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 5 Pin Assignments for x4 Lane Widths For x4 lane widths a half size header can be used The diagram below shows the recommended pin assignments for x4 configurations keep in mind that any of modifications mentioned in Section 4 2 can be applied x4 Bi directional Mid Bus Probe Pinout on a Half size Header Pin Signal Name Pin Signal Name Fen COn Downstream GND 8 GND 7 Cip Upstream _ 10 C1p Downstream 9 Cin Upstream 1 REL c C2p Upstream ET GND C3p Upstream 24 Con Downsream 25 GND 17 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 4 6 Pin Assignments for x2 Lane Widths For x2 lane widths a half size header can be used The diagram below shows the recommended pin assignments for x2 configurations x2 Bi directional Mid Bus Probe Pinout on a Half size Header Pin Pin Signal Name GND Ls ono Om Uperemn 10 Cip Downstream 9
18. rence Clock Cable The Reference Clock Cable PEO14UCA X connects the Mid Bus Pod to the DUT so that the pod can use the clock from the DUT The cable has a 3 pin micro socket at one end that attaches to a 3 pin header 0 050 spacing designed into the DUT and the other end connects to the Clk In port on the Mid Bus Probe Pod 5 2 4 Daisy Chain Cable The Daisy Chain Cable PEO09UCA X connects multiple Mid Bus Pods together so they can share the same clock One end of the connector is attached to the Clk Out port of the Mid Bus Pod supplying the clock signal and the other end is connected to the Clk In port of the other Mid Bus Pod 25 Teledyne LeCroy PCI Express Mid Bus Probe for Summit Analyzers Version 1 0 6 Dual Probe Pod Setup Using External Clocking The steps outlined above describe a single Probe single analyzer configuration In a dual analyzer setup a second probe may need to be added depending on the type of link that is being recorded If the analyzer internal clock is to be used then cable the target device to the probe pod as follows however omit the 3 pin reference clock cable s shown in the illustration If external clocking is to be used using the PEO14UCA X Ref Clock cable connect the 3 pin reference clock cable from the 3 pin header on the system board to the CLK IN port on one probe pod Then using the PE009UCA X Daisy Chain Cable connect the CLK OUT port on that same pod and connect it to the CLK IN
19. to the board The multi lead probe allows individual connections to each bus trace on the board The Teledyne LeCroy mid bus probes are 16 channel differential signal probes that meet the demand for high density signal access accuracy and repeatability while providing connector less attachment to the device under test They are based upon the configuration that was initially recommended in the Intel PCI Express Mid Bus Probing Footprint and Pinout Revision 1 0 document dated 8 05 03 and the subsequent revisions A mid bus probe is one of the tools that can greatly help engineers debugging PCI Express buses A PCI Express mid bus probing solution provides direct probing capability of a PCI Express bus at a width of up to scccccccccccecccceccceess 16 lanes To accommodate a mid bus probe a special pad layout is required to expose the PCI Express differential pairs on the surface of the D target board e0006000000000000000000001 Although not part of the PCI Express specifications the industry has developed a common mid bus probe footprint for Geni and Gen2 applications as shown on the right This footprint is recommended for use with all types of test equipment including protocol analyzers logic analyzers and oscilloscopes The required pad layout can be in x4 half size x8 full size or x16 dual full size configurations depending on the maximum number of lanes that need to be probed All footprint sizes support probing at reduce
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