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Intel XScale Microarchitecture Users Manual.book

1. TDI gt Instruction Register 5 i Boundary Scan Register TMS ITCK TAP gt Controller Bypass Register 1 WIEST TDO Device ID Register 32 Data Specific Register s Control And Clock Signals Intel XScale Microarchitecture User s Manual 9 1 Test I ntel The Test Access Port interface is controlled via five dedicated pins These pins are described in Table 9 1 Table 9 1 TAP Controller Pin Definitions Signal Name Mnemonic Type Definition Clock input for the TAP controller instruction register and test Test Clock TCK Input gata registers Controls operation of the TAP controller The TMS input is Test Mode Select TMS Input pulled high when not being driven TMS is sampled on the rising edge of TCK Serial data input to the instruction and test data registers Data Test Data In TDI Input at TDI is sampled on the rising edge of TCK TDI is pulled high when not being driven Serial data output Data at TDO is clocked out on the falling edge of TCK It provides an inactive high Z state during non A Te SR shift operations to support parallel connection of TDO outputs at the board or module level Provides asynchronous initialization of the JTAG test logic Asynchronous Reset nTRST Input Assertion of this pin puts the TAP controller in the Test Logic Re
2. Data cache with write coalescing read write allocate and write back caching To support allocating variables to these various memory regions the tool chain compiler assembler linker and debugger must implement these named sections The performance of your application code depends on what cache policy you are using for data objects A description of when to use a particular policy is described below The Intel XScale core allows dynamic modification of the cache policies at run time however the operation does require considerable processing time and therefore should not be recommended for use by applications If the application is running under an OS then the OS may restrict you from using certain cache policies Non Cacheable Regions It is recommended that non cache memory X 0 C 0 and B 0 be used only if necessary as is often necessary for I O devices Accessing non cacheable memory is likely to cause the processor to stall frequently due to the long latency of memory reads Write through and Write back Cached Memory Regions Write through memory regions generate more data traffic on the bus Therefore use the write back policy in preference to the write through policy whenever possible In an external DMA environment it may be necessary to use a write through policy where data is shared with external companion devices In such a situation all shared memory regions should use write through policy to save regular c
3. 10 15 Software Debug NOt6eS 2 ee c Mab linie Lb P ER ges 10 46 11 Performance Considerations sss nennen nennen nene ernnrnnrn nennen 11 1 11 1 Branch Prediction ee Ree et ERI n E ERE RN NES 11 1 11 2 Instruction Eat ncles dt ere e ete bee Dente PUR osten edd 11 2 11 2 1 Performance Terms n sieri eaa aa aaae a a Taai 11 2 11 2 2 Branch Instruction Timings ei aAA AE EAR 11 3 11 2 3 Data Processing Instruction TIMINGS es m 11 4 11 2 4 Multiply Instruction Timings ennm mmn 11 5 11 25 Saturated Arithmetic Instructions eee 11 6 11 2 6 Status Register Access Instructions e 11 7 11 2 7 Load Store Insiruchons rennen nenne 11 7 11 2 8 Semaphore Inistructl rs i eere qe Pa et t e deu Eten 11 8 11 2 9 Coprocessor Instructions sssssssssssssesee emen mme nnne 11 8 11 2 10 Miscellaneous Instruction Timing se nenn 11 8 11 2 11 Thumb NSU OAS a re a r a a a a a aaa aeaa aa nennen 11 9 11 3 Interrupt Eatency iot eee ita 11 9 A Optimization Guides siaa a e ee ec tete t i te UL eat C eM eeu A 1 AT Introduction ss nee ae RE D OU UR ERU RIEN ers A 1 A44 About This Guild n tI Het Ete u ee bud A 1 A 2 Intel XScale Core Dipelme nenn A 1 A 2 1 General Pipeline Characteristics c ccccccecceeceeeeeeeeeceecaeeeeeeeeeeeeeeseessnsneeaeees A 2 A 2 1 1 Number of Pipeline Stages mee A 2 A 2 1 2 Intel XScale Core Pipeline Organization A 2 A
4. Select IR Scan State This is a temporary controller state The test data registers selected by the current instruction retain their previous state In this state if TMS is held low on the rising edge of TCK the controller moves into the Capture IR state and a scan sequence for the instruction register is initiated If TMS is held high on the rising edge of TCK the controller moves to the Test Logic Reset state The instruction does not change in this state Capture IR State When the controller is in the Capture IR state the shift register contained in the instruction register loads the fixed value 0001 on the rising edge of TCK Intel XScale Microarchitecture User s Manual 9 11 Test 9 5 12 9 5 13 9 5 14 9 5 15 9 5 16 9 12 intel The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state While in this state holding TMS high on the rising edge of TCK causes the controller to enter the Exit1 IR state If TMS is held low on the rising edge of TCK the controller enters the Shift IR state Shift IR State When the controller is in this state the shift register contained in the instruction register is connected between TDI and TDO and shifts data one bit position nearer to its serial output on each rising edge of TCK The test data register selected by the current instruction retains its previous value during this sta
5. 0 0 0 cece eeeeeeeeeeeeeeneeeeeeseteeeeeeennaeeeeeees A 31 Ap Optimizations for Glze ee enne n enne rrner ener nennen nen A 31 A 6 1 Multiple Word Load and Store ssseessessenennnnnennseeeeetrtnrrnnrnnnserettnnttrnnenrnnn nenene A 31 A 6 2 Use of Conditional Instructions nennen A 31 A 6 3 Use of PLD Instructions seccina eee ennn nennen nnn nnn nnn nnn A 32 A 6 4 Thumb Instructions ooooccccccnnnnnnnnnnnnoconcnnncnnnnnnnnnnnnnnnn non eene nennen nennen nns A 32 Figures 1 1 Intel XScale Microarchitecture Architecture Features ncna ronca 1 3 3 1 Example of Locked Entries in TR 3 8 4 1 Instruction Cache Organization seeeeeesseeeeeseesieeeeee sesenta nnns trn nnns nens 4 1 4 2 Locked Line Effect on Round Robin Replacement nnn 4 6 Intel XScale Microarchitecture User s Manual ix Contents ntel 551 BIB EN eee t e be Haie dant pea ae en 5 1 5 2 SN 5 2 0 1 Data Cache Organization teen nennen 6 2 6 2 Mini Data Cache Organization ssssssssseeeeneen n eene enne nennen nnns 6 3 6 3 Locked Line Effect on Round Robin Renlacement renn 6 13 9 1 Test Access Port TAP Block Diagram esere eseina nariai annn EAEn N NAE AEE AAEE 9 2 9 2 BSDL code for 256 MBGA package coooococncccccccccnoconcncnnnnnonnnnnnnnnnnn nn eene ennemi nennen 9 7 9 3 TAP Controller State Diagramm 9 9 10 4SEEDCSR Hardware ciae dae no aaa 10 17 10 2DBGTX e Elte sn ansehen 10 19 10 3DBGRX e Elte VE 10 20
6. Intel amp XScale Microarchitecture for the PXA255 Processor User s Manual March 2003 Order Number 278796 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel amp products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel XScale Microarchitecture Users Manual for the PXA255 processor may contain design defects or errors known as errata which may cause the product to deviate from published speci
7. The preload instruction PLD is only a hint it does not change the architectural state of the processor Using or not using them will not change the behavior of your code therefore you should avoid using these instructions when optimizing for space Thumb Instructions The best opportunity for code compaction is to utilize the ARM Thumb instructions These instructions are additions to the ARM architecture primarily for the purpose of code size reduction 16 bit Thumb instructions have less functionality than their 32 bit equivalents hence Thumb code is typically slower than 32 bit ARM code However in some unusual cases where Instruction Cache size is a significant influence being able to hold more Thumb instructions in cache may aid performance Whatever the performance outcome Thumb coding significantly reduces code size Intel XScale Microarchitecture User s Manual
8. XScale Microarchitecture User s Manual A 9 Optimization Guide ntel A 3 1 3 A 10 If we make the assumptions that both paths are equally likely to be taken and that branches are mis predicted 50 of the time the costs of using conditional execution Vs using branches can be computed as follows Cost of using conditional instructions 50 2 e up umm Fl 1 L x 10 100 x10 11 cycles Cost of using branches 50 2 2 E Al 4 9 1 5x7 joo X 6 ioo 4 9 5 cycles As can be seen we get better performance by using branch instructions in the above scenario Optimizing Complex Expressions Conditional instructions should also be used to improve the code generated for complex expressions such as the C shortcut evaluation feature Consider the following C code segment int foo int a int b if a 0 amp amp b 0 return 0 else return 1 The optimized code for the if condition is cmp ro 0 cmpne rl 0 Similarly the code generated for the following C segment int foo int a int b if a 0 b 0 return 0 else return 1 is cmp ro 0 cmpeq rl 0 The use of conditional instructions in the above fashion improves performance by minimizing the number of branches thereby minimizing the penalties caused by branch mispredictions This approach also reduces the utilization of branch prediction resources Intel XScale Microarchitecture User s Manual In
9. b write common exit 10 14 3 Ending a Debug Session Prior to ending a debug session the debugger must take the following actions 1 Clear the DCSR disable debug exit Halt Mode clear all vector traps disable the trace buffer 2 turn off all breakpoints 3 invalidate the mini instruction cache 4 invalidate the main instruction cache 5 invalidate the BTB These actions ensure that the application program executes correctly after the debugger has been disconnected Intel XScale Microarchitecture User s Manual 10 45 Software Debug I ntel i 10 15 10 46 Software Debug Notes 1 Trace buffer message count value on data aborts LDR to non PC that aborts gets counted in the exception message But an LDR to the PC that aborts does not get counted as an exception message 2 Software note on data abort generation in Special Debug State 1 Avoid code that could generate precise data aborts 2 If this cannot be done then handler needs to be written such that a memory access is followed by 1 NOP In this case certain memory operations must be avoided LDM STM STRD LDC SWP 3 Data abort on Special Debug State When write back is on for a memory access that causes a data abort the base register is updated with the write back value This is inconsistent with normal non SDS behavior where the base remains unchanged if write back is on and a data abort occurs 4 Trace Buffer wraps around and loses data i
10. 1 3 GPTA Registers uem Eoi n a lar ia 7 15 7 3 1 Registers 0 3 Performance Monitoring sss 7 16 7 3 2 Registers 6 7 Clock and Power Management 7 16 7 3 3 Registers 8 15 Software Debug emen 7 17 8 Performance Monitoring 2 r44000nmmnnnn0nonnnnnnnnonnnnnnnnonnnnnnnnonnnnnnnnnennnnnnnnnennnnnnnnennnnnnnennnnn 8 1 8r e EE 8 1 8 2 Clock Counter CCNT CP14 Register 1 esses emen 8 1 8 3 Performance Count Registers PMNO PMN1 CP14 Register 2 and 3 Respectively 8 2 8 3 1 Extending Count Duration Beyond 32 Bits sessssss 8 2 8 4 Performance Monitor Control Register PMNO mene 8 2 8 4 1 Managing the dt e 8 4 8 5 Performance Monitoring Events ssssssssssseeee eem nennen nennen nnns 8 4 8 5 1 Instruction Cache Efficiency Mode sessessssenesseseseeeersnerssnnnesrnnenersennnernennaeseennee 8 5 8 5 2 Data Cache Efficiency Mode sse 8 6 8 5 3 Instruction Fetch Latency Mode 8 6 8 5 4 Data Bus Request Buffer Full Mode sssssssssseenene es 8 6 8 5 5 Stall Writeback Statistics Mode 8 7 8 5 6 Instruction TLB Efficiency Mode eem 8 8 9 577 Data TL B Efficiency ModE ii it ps ada us P teat eee 8 8 8 6 Multiple Performance Monitoring Run Statistics eeeeeeeeeeeeeeeeeeeeeeerreseeerrrensrrnsssreerssne 8 8 9 Examples oen bled ee edes Is 8 8 9 ep aaa ceeectan tem T sedan tetas 9 1 9 1 Boundary Scan Architecture
11. int foo int a if a gt 10 return 0 else return 1 The code generated for the if else portion of this code segment using branches is cmp ro 10 ble L1 mov r0 0 b L2 L1 mov rO 1 L2 The code generated above takes three cycles to execute the else part and four cycles for the if part assuming best case conditions and no branch misprediction penalties In the case of the Intel XScale core a branch misprediction incurs a penalty of four cycles If the branch is mispredicted 50 of the time and if we assume that both the if part and the else part are equally likely to be taken on an average the code above takes 5 5 cycles to execute 50 Se a 4 x 5 5 cycles Intel XScale Microarchitecture User s Manual Optimization Guide If we were to use the Intel XScale core to execute instructions conditionally the code generated for the above if else statement is cmp r0 10 movgt r0 0 movle r0 1 The above code segment would not incur any branch misprediction penalties and would take three cycles to execute assuming best case conditions As can be seen using conditional instructions speeds up execution significantly However the use of conditional instructions should be carefully considered to ensure that it does improve performance To decide when to use conditional instructions over branches consider the following hypothetical code segment if cond if stmt else else stmt Ass
12. orr r0 rO 256 Set the value of r0 to Ox51f mov ro HOx1f orr rO rO 0x500 Set the value of r0 to Oxf100ffff mvn r0 HOxff 16 bic ro r0 0xe 8 Set the value of r0 to 0x12341234 mov r0 0x8d 30 orr r0 r0 0x1 20 add r0 r0 r0 LSL 16 shifter delay of 1 cycle Note that it is possible to load any 32 bit value into a register using a sequence of four instructions Optimizing Integer Multiply and Divide Multiplication by an integer constant should be optimized to make use of the shift operation whenever possible Multiplication of RO by 2 mov r0 rO LSL n Multiplication of RO by 2 1 add r0 rO r0 LSL n Intel XScale Microarchitecture User s Manual A 11 E Optimization Guide ntel A 3 5 A 4 A 12 m Multiplication by an integer constant that can be expressed as 2 1 2 can similarly be optimized as Multiplication of r0 by an integer constant that can be expressed as 2741 2 add r0 rO r0 LSL in mov r0 r0 LSL m Please note that the above optimization should only be used in cases where the multiply operation cannot be advanced far enough to prevent pipeline stalls Dividing an unsigned integer by an integer constant should be optimized to make use of the shift operation whenever possible Dividing r0 containing an unsigned value by an integer constant that can be represented as 22 mov r0 r0 LSR n Dividing a signed integer by an integer const
13. processor will be in Special Debug State so all of the special functionality applies The downloaded functions may also require some common routines from the static debug handler such as the polling routines for reading RX or writing TX To simplify the dynamic functions the debug handler should define a set of registers to contain the addresses of the most commonly used routines The dynamic functions can then access these routines using indirect branches BLX This helps reduce the amount of code in the dynamic function since common routines do not need to be replicated within each dynamic function High Speed Download Special debug hardware has been added to support a high speed download mode to increase the performance of downloads to system memory vs writing a block of memory using the standard handshaking The basic assumption is that the debug handler can read any data sent by the debugger and write it to memory before the debugger can send the next data Thus in the time it takes for the debugger to scan in the next data word and do an Update DR the handler is already in its polling loop waiting for it Using this assumption the debugger does not have to poll RR to see whether the handler has read the previous data it assumes the previous data has been consumed and immediately starts scanning in the next data word Intel XScale Microarchitecture User s Manual n Software Debug The pitfall is when the write to m
14. v5 RISC instruction and execution resumes as usual Pipeline Stalls The progress of an instruction can stall anywhere in the pipeline Several pipestages may stall for various reasons It is important to understand when and how hazards occur in the Intel amp XScaleTM core pipeline Performance degradation could be significant if care is not taken to minimize pipeline stalls Main Execution Pipeline F1 F2 Instruction Fetch Pipestages The job of the instruction fetch stages F1 and F2 is to present the next instruction to be executed to the ID stage Several important functional units reside within the F1 and F2 stages including Branch Target Buffer BTB Instruction Fetch Unit IFU An understanding of the BTB See Chapter 5 Branch Target Buffer and IFU are important for performance considerations A summary of operation is provided here so that the reader may understand its role in the F1 pipestage Branch Target Buffer BTB The BTB predicts the outcome of branch type instructions Once a branch type instruction reaches the X1 pipestage its target address is known If this address is different from the Intel XScale Microarchitecture User s Manual A 2 3 2 A 2 3 3 A 2 3 4 Optimization Guide address that the BTB predicted the pipeline is flushed execution starts at the new target address and the branch s history is updated in the BTB Instruction Fetch Unit IFU The IFU is responsible for de
15. 01011 private 00010 dbgrx 01100 private 00011 private 01101 private 00100 clamp 01110 01111 not used 00101 private 10000 dbgtx 00110 not used 10001 11001 private 00111 Idic 11010 11101 not used 01000 highz 11110 idcode 01001 deer 11111 bypass Intel XScale Microarchitecture User s Manual 9 3 Test Table 9 3 JTAG Instruction Descriptions Instruction Requisite Opcode Description extest IEEE 1149 1 Required 00000 The extest instruction initiates testing of external circuitry typically board level interconnects and off chip circuitry extest connects the Boundary Scan register between TDI and TDO in the Shift_DR state only When extest is selected all output signal pin values are driven by values shifted into the Boundary Scan register and may change only on the falling edge of TCK in the Update_DR state When extest is selected all system input pin states must be loaded into the Boundary Scan register on the rising edge of TCK in the Capture_DR state Values shifted into input latches in the Boundary Scan register are never used by the processor s internal logic sample IEEE 1149 1 Required 00001 The sample preload instruction performs two functions When the TAP controller is in the Capture DR state the sample instruction occurs on the rising edge of TCK and provides a snapshot of the component s normal operation without interfering with that nor
16. 2 2 Instruction Cache secci eee een ned cda 3 2 3 2 3 Data Cache and Write Buffer 3 2 Intel XScale Microarchitecture User s Manual iii Contents ntel 3 2 4 Details on Data Cache and Write Buffer Behavior 3 3 3 2 5 Memory Operation Ordering essen emen 3 3 3 2 0 IEXCEPUONS nione a om ette tete iet ted aid 3 4 3 3 Interaction of the MMU Instruction Cache and Data Cache 3 4 34 SCO A d ned ia o ep en a t D bant Bad ere reete a nen EUM 3 4 3 4 1 Invalidate Flush Operation 3 4 3 4 2 Enabling Disablirig ore eh oat 3 5 S43 Locking ENtriES Hr Rees exe aede pete ae iii 3 5 3 4 A Round Robin Replacement Algorithm senn en 3 7 4 instruction CACHO rai E EE roi e tute set loce ist edat eet etude 4 1 4 1 OVerVIeW cetero e d ate pa adt iu vv tr aae ded 4 1 SCHEER 4 2 4 2 1 Instruction CGacheisEnabled 4 2 4 2 2 The Instruction Cache Is Disabled 4 2 4 2 3 Fetch POLICY za ehe rea e RE TS ERR tS een Ee 4 2 4 2 4 Round Robin Replacement Algorithm essen 4 3 4 2 5 Parity Protectlon ule ee tente eG LO ORE See 4 3 4 2 6 Instruction Fetch Latency eem enne 4 4 4 2 7 Instruction Cache Coherency ccccoccooccccconocncccnonannnnnnnnanonnnncnnnnn eene emere nenne 4 4 4 3 Instruction Cache Control tad ri nalen Decio edo dd 4 5 4 3 1 Instruction Cache State at RESET ooooncccnccccnonccncncnccononnnoncnnononnnnnnnoncrnnnancnnrnnnnnnn 4 5 4 3 2 Enabling Disabling eee qe
17. BRK DBG BRK DBGBRK allows the debugger to generate an external debug break and asynchronously re direct execution to a debug handling routine A debugger sets an external debug break by scanning data into the DBG SR with DBG_SR 2 set and the desired value to set the DCSR JTAG writable bits in DBG_SR 34 3 Once an external debug break is set it remains set internally until a debug exception occurs In Monitor mode external debug breaks detected during abort mode are postponed until the processor exits abort mode In Halt mode breaks detected during SDS are postponed until the processor exits SDS When an external debug break is detected outside of these two cases the processor ceases executing instructions as quickly as the current pipeline contents can be completed This improves breakpoint accuracy by reducing the number of instructions that can execute after the external debug break is requested However the processor will continue to process any instructions which have already begun execution Debug mode will not be entered until all processor activity has ceased in an orderly fashion DBG DCSR The DCSR is updated with the value loaded into DBG DCSR following an Update DR Only bits specified as writable by JTAG in Table 10 3 are updated Intel XScale Microarchitecture User s Manual Intel 10 10 3 10 10 4 Software Debug DBGTX JTAG Command The DBGTX JTAG instruction selects the DBGTX JTAG data register T
18. Considerations Intel Table 11 4 Branch Instruction Timings Those not predicted by the BTB Minimum Issue Latency when Minimum Issue Latency when Mnemonic the branch is not taken the branch is taken BLX 1 N A 5 BLX 2 1 5 BX 1 3 Data Processing Instruction with PC as the destination Same as Table 11 5 4 numbers in Table 11 5 LDR PC lt gt 2 8 LDM with PC in register list 3 numreg 10 max 0 numreg 3 a numreg is the number of registers in the register list including the PC 11 2 3 Data Processing Instruction Timings Table 11 5 Data Processing Instruction Timings 11 4 shifter operand is NOT a Shift Rotate Shifter ae n by By Register lt shifter operand gt is RRX Minimum Issue Minimum Result Minimum Issue Minimum Result Latency Latency Latency Latency ADC 1 1 2 2 ADD 1 1 2 2 AND 1 1 2 2 BIC 1 1 2 2 CMN 1 1 2 2 CMP 1 1 2 2 EOR 1 1 2 2 MOV 1 1 2 2 MVN 1 1 2 2 ORR 1 1 2 2 RSB 1 1 2 2 RSC 1 1 2 2 SBC 1 1 2 2 SUB 1 1 2 2 TEQ 1 1 2 2 TST 1 1 2 2 a If the next instruction needs to use the result of the data processing for a shift by immediate or as Rn in a QDADD or QDSUB one extra cycle of result latency is added to the number listed Intel XScale Microarchitecture User s Manual intel 11 2 4 Multiply Instruction Timings Table 11 6 Multi
19. Data Breakpoint 0 DBRO 0b000 0b0000 MRC p15 0 Rd c14 c0 0 Intel XScale Microarchitecture User s Manual 7 13 Configuration n Table 7 19 Accessing the Debug Registers Sheet 2 of 2 Function opcode 2 CRm Instruction Write DBRO 0b000 0b0000 MCR p15 0 Rd c14 c0 O Read Data Mask Address Register 0b000 060011 MRC p15 0 Rd c14 c3 0 DBR1 Write DBR1 0b000 0b0011 MCR p15 0 Rd c14 c3 0 Read Data Breakpoint Control Register DBCON 0b000 0b0100 MRC p15 0 Rd c14 c4 0 Write DBCON 0b000 0b0100 MCR p15 0 Rd c14 c4 0 7 2 13 Register 15 Coprocessor Access Register Register 15 Coprocessor Access Register is selected when opcode 2 0 and CRm 1 This register controls access rights to all the coprocessors in the system except for CP15 and CP14 Both CP15 and CP14 can only be accessed in privilege mode This register is accessed with an MCR or MRC with the CRm field set to 1 This register controls access to CPO on the application processors Example 7 1 Disallowing access to CPO The following code clears bit 0 of the CPAR This will cause the processor to fault if software attempts to access CPO bit 0 is clear move to CPAR wait for effect See Section 2 3 3 LDR RO 0x3FFE MCR P15 O RO C15 Cl O CPWAIT Table 7 20 Coprocessor Access Register Sheet 1 of 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6
20. M3 MS it is considered committed because it will modify architectural state regardless of subsequent events Basic Optimizations This chapter outlines optimizations specific to the ARM architecture These optimizations have been modified to suit the Intel XScale core where needed Conditional Instructions The Intel XScale core architecture provides the ability to execute instructions conditionally This feature combined with the ability of the Intel amp XScaleTM core instructions to modify the condition codes makes possible a wide array of optimizations Optimizing Condition Checks The Intel XScale core instructions can selectively modify the state of the condition codes When generating code for if else and loop conditions it is often beneficial to make use of this feature to set condition codes thereby eliminating the need for a subsequent compare instruction Consider the C code segment if a b Code generated for the if condition without using an add instruction to set condition codes is Assume r0 contains the value a and r1 contains the value b add LO 150 SL cmp ro 0 However code can be optimized as follows making use of an ADD instruction to set condition codes Assume r0 contains the value a and rl contains the value b adds r0 r0 r1 The instructions that increment or decrement the loop counter can also be used to modify the condition codes This eliminates the need for a subsequent compare
21. Management Lock unlock operations on a TLB when the MMU is disabled have an undefined effect This register is write only Reads from this register as with an MRC have an undefined effect Table 7 16 shows the commands for locking down entries in the instruction TLB and data TLB The entry to lock is specified by the virtual address in Rd Table 7 16 TLB Lockdown Functions 72 11 Function opcode_2 CRm Data Instruction Translate and Lock TLB entry 0b000 0b0100 MVA MCR p15 0 Rd c10 c4 0 Translate and Lock D TLB entry 0b000 0b1000 MVA MCR p15 0 Rd c10 c8 0 Unlock TLB 0b001 0b0100 Ignored MCR p15 0 Rd c10 c4 1 Unlock D TLB 0b001 0b1000 Ignored MCR p15 0 Rd c10 c8 1 Register 13 Process ID The Intel XScale core supports the remapping of virtual addresses through a Process ID PID register This remapping occurs before the instruction cache instruction TLB data cache and data TLB are accessed The PID register controls when virtual addresses are remapped and to what value The PID register is a 7 bit value that is ORed with bits 31 25 of the virtual address when they are zero This effectively remaps the address to one of 128 slots in the 4 Gbytes of address space If bits 31 25 are not zero no remapping occurs This feature is useful for operating system management of processes that may map to the same virtual address space In those cases the virtually m
22. NMAX 1 Unfortunately prefetch loop unrolling does not work on loops with indeterminate iterations Pointer Prefetch Not all looping constructs contain induction variables However prefetching techniques can still be applied Consider the following linked list traversal example while p do something p data p p gt next The pointer variable p becomes a pseudo induction variable and the data pointed to by p gt next can be prefetched to reduce data transfer latency for the next iteration of the loop Linked lists should be converted to arrays as much as possible while p prefetch p gt next do something p gt data p p gt next Recursive data structure traversal is another construct where prefetching can be applied This is similar to linked list traversal Consider the following pre order traversal of a binary tree preorder treeNode t if t process t gt data preorder t gt left preorder t gt right The pointer variable t becomes the pseudo induction variable in a recursive loop The data structures pointed to by the values t gt eft and t gt right can be prefetched for the next iteration of the loop preorder treeNode t if t prefetch t gt right prefetch t gt left process t gt data preorder t gt left preorder t gt right Note the order reversal of the prefetches in relationship to the usage If there is a cache conflict and
23. Read undefined Write As Zero Reserved undefined undefined Software Read Write 0 unchanged 5 JTAG Read Only Sticky Abort SA Method Of Entry MOE 0b000 unchanged 000 Processor Reset 001 Instruction Breakpoint Hit Software Read Write 010 Data Breakpoint Hit 4 2 JTAG Read Only 011 BKPT Instruction Executed 100 External Debug Event Asserted 101 Vector Trap Occurred 110 Trace Buffer Full Break 111 Reserved Software Read Write Trace Buffer Mode M 0 unchanged 1 JTAG Read Only 0 Wrap around mode 1 fill once mode Trace Buffer Enable E 0 unchanged 0 Software Read Write D Disabled JTAG Read Onl SOR 1 Enabled 10 3 1 10 3 2 10 3 3 10 4 Global Enable Bit GE The Global Enable bit disables and enables all debug functionality except the reset vector trap Following a processor reset this bit is clear so all debug functionality is disabled When debug functionality is disabled the BKPT instruction becomes a NOP and external debug breaks hardware breakpoints and non reset vector traps are ignored Halt Mode Bit H The Halt Mode bit configures the debug unit for either halt mode or monitor mode Vector Trap Bits TF TI TD TA TS TU TR The Vector Trap bits allow instruction breakpoints to be set on exception vectors without using up any of the breakpoint registers When a bit is set it acts as if an instruction breakpoint was set up on the corresponding exception vector A debu
24. The events that are monitored provide performance information for compiler writers system application developers and software programmers Overview The Intel XScale core hardware provides two 32 bit performance counters that allow two unique events to be monitored simultaneously In addition the Intel amp XScaleTM core implements a 32 bit clock counter that can be used in conjunction with the performance counters its sole purpose is to count the number of core clock cycles which is useful in measuring total execution time The Intel amp XScaleTM core can monitor either occurrence events or duration events When counting occurrence events a counter is incremented each time a specified event takes place and when measuring duration a counter counts the number of processor clocks that occur while a specified condition is true If any of the 3 counters overflow an IRQ or FIQ will be generated if it s enabled Each counter has its own interrupt enable The counters continue to monitor events even after an overflow occurs until disabled by software Each of these counters can be programmed to monitor any one of various events To further augment performance monitoring the Intel amp XScaleTM core clock counter can be used to measure the executing time of an application This information combined with a duration event can feedback a percentage of time the event occurred with respect to overall execution time Each of the three counters a
25. User s Manual 10 19 Software Debug I ntel 10 10 5 10 10 6 DBGRX JTAG Command The DBGRX JTAG instruction selects the DBGRX JTAG data register The JTAG opcode for this instruction is 0600010 Once the DBGRX data register is selected the debugger can send data to the debug handler through the RX register DBGRX JTAG Register The DBGRX JTAG instruction selects the DBGRX JTAG Data register The debugger uses the DBGRX data register to send data or commands to the debug handler Figure 10 3 DBGRX Hardware 10 20 software read write undefined I i delay l 0 0 1 Capture DR TXRXCTRL l NEN 31 30 29 ITD gt TDO A I 3534 32 10 DBG SR I pol ey DBG_REG 1 I Update DR clear byla read from RX gt t by Deb Writ pu set by Debugger Write TCK 34133 2 110 DBG REG k ME NEED Wm Wen mE DEE mmm um o mum mum m um clear DBG REG 34 j Flush RR BEUTE En to TXRXCTRL 29 RX set TXRXCTRL 31 4 Write enable RX Logic 31 0 TXRXCTRL 31 D Core CLK software read A Capture DR loads TXRXCTRL 31 into DBG_SR 0 The other bits in DBG SR are loaded as shown in Figure 10 3 The captured data is scanned out during the Shift DR state While polling TXRXCTRL 31 incorrec
26. a debug exception and re directs execution to the debug handler before the next instruction executes The processor reports the data breakpoint by setting the DCSR moe to 0b010 The link register of a data breakpoint is always PC of the next instruction to execute 4 regardless of whether the processor is configured for monitor mode or halt mode Software Breakpoints Mnemonics BKPT See ARM Architecture Reference Manual ARMvST Operation If DCSR 31 0 BKPT is a NOP If DCSR 31 1 BKPT causes a debug exception The processor handles the software breakpoint as described in Section 10 4 Debug Exceptions on page 10 5 Transmit Receive Control Register TXRXCTRL Communications between the debug handler and debugger are controlled through handshaking bits that ensure the debugger and debug handler make synchronized accesses to TX and RX The debugger side of the handshaking is accessed through the DBGTX Section 10 DBGTX JTAG Register and DBGRX Section 10 DBGRX JTAG Register JTAG Data Registers depending on the direction of the data transfer The debug handler uses separate handshaking bits in TXRXCTRL register for accessing TX and RX The TXRXCTRL register also contains two other bits that support high speed download One bit indicates an overflow condition that occurs when the debugger attempts to write the RX register before the debug handler has read the previous data written to RX The other bit is used by
27. a resource dependency stall the next instruction is immediately available from the cache or memory interface the current instruction does not incur resource dependency stalls during execution that can not be detected at issue time and 1f the instruction uses dynamic branch prediction correct prediction is assumed Minimum Result Latency The required minimum cycle distance from the issue clock of the current instruction fo the issue clock of the first instruction that can use the result without incurring a resource dependency stall assuming best case conditions i e that the issuing of the next instruction is not stalled due to a resource dependency stall the next instruction is immediately available from the cache or memory interface and the current instruction does not incur resource dependency stalls during execution that can not be detected at issue time Minimum Issue Latency with Branch Misprediction The minimum cycle distance from the issue clock of the current branching instruction fo the first possible issue clock of the next instruction This definition is identical to Minimum Issue Latency except that the branching instruction has been mispredicted It is calculated by adding Intel XScale Microarchitecture User s Manual 11 2 2 Performance Considerations Minimum Issue Latency without Branch Misprediction to the minimum branch latency penalty number from Table 11 1 Minimum Resource Latency The minim
28. allowing the debugger to access the DCSR generate an external debug break set the hold rst signal which is used when loading code into the instruction cache during reset Figure 10 1 SELDCSR Hardware Capture DR i m ee TDI gt TDO 35 34 32 110 DBG SR LL 3 ignored Update DR T TCK 3433 2 1 0 DBG REG LLL Core CLK y hold_rst y external debug break D DCSR 31 0 o software read write A Capture_DR loads the current DCSR value into DBG_SR 34 3 The other bits in DBG_SR are loaded as shown in Figure 10 1 A new DCSR value can be scanned into DBG_SR and the previous value out during the Shift DR state When scanning in a new DCSR value into the DBG SR care must be taken to also set up DBG SR 2 1 to prevent undesirable behavior Update DR parallel loads the new DCSR value into DBG_REG 33 2 This value is then loaded into the actual DCSR register All bits defined as JTAG writable in Table 10 3 Debug Control and Status Register DCSR on page 10 3 are updated An external host and the debug handler running on the Intel XScale core must synchronize access to the DCSR If one side writes the DCSR at the same time the other side reads the DCSR the results are unpredictable Intel XScale Microarchitecture User s Manual 10 17 Softw
29. and Buffer Behavior when X A 3 3 3 3 Memory Operations that Impose a tence mener 3 4 3 4 Valid MMU amp Data mini data Cache Combinations see 3 4 7 1 MRC MCR Format 7 2 7 2 LDC STC Format when Accessing CIA 7 2 7 3 CP15 Registers AAA 7 3 74 D Regista DE a da een dad de 7 4 7 5 Cache Type Register 7 5 7 6 ARM Control Register 2 nee anna 7 6 7 7 Auxiliary Control Register 7 7 X Intel XScale Microarchitecture User s Manual j ntel 5 Contents 7 8 Translation Table Base Register esesseseseeseeeseeeene eee E Aea EEE RNa 7 7 7 9 Domain Access Control Regteter ocn nnrnnn nennen nennen nenne 7 8 7 10 Fault Status Register ees 2 ed qe pesi dn det repeti quee d ede ense deret 7 8 7 11 Fault Address Register ee ee En hen eben dex evi 7 9 7 12Gache Fu nctions ierit Ian le ie 7 9 719 EB EUDCUONRS era rae E in NEED ME On me IR dom 7 11 7 14 Cache Lockdown FUNCIONS ocn rcnnnnn eene AEE ener nnne 7 11 7 15 Data Cache Lock Register oooonncccccnnnnnccccnnnonccccnnnnnnnccnnnnnnnencnnnnnnec cnc REENEN 7 11 7 16 TEB Eockdowrr EUROS neen dianas 7 12 7 17 Accessirig Process ID ie iiem ee en 7 12 7 18 Process ID Register ENEE dudit dede de add ride Lt ddnde aded lia 7 13 7 19 Accessing the Debug Register 7 13 7 20 Coprocessor Access Register ccccccsscccceeeseececeeseseececeeeseaaaeneessenaceeeeseaaceceestecececenseanaeeeeeess 7 14 7 21 e et Ee E CN 7 16 7 22 Accessing the Perf
30. and Store Instruction Timings o ooocccnnnnoncccnnnnoccccccnononrnccnnnnn cc cnn nano cr nana ennemis 11 7 11 12Load and Store Multiple Instruction TiMINgS 44444 nnennnnennnnnnnnnennnnnnnnnnnn nenn 11 8 11 13Semaphore Instruction TIMINGS sssssseeeeeenenme nenne eee nennen ann 11 8 11 14CP15 Register Access Instruction TIMINgS seen 11 8 11 15CP14 Register Access Instruction TIMINgS seem 11 8 11 16SWI Instruction TIMINGS serrera e A rca rra rr 11 8 11 17Count Leading Zeros Instruction Timings seem 11 9 Pipelines and Pipe stages ooocoococccococccccccccnnccononncnnnnnnnnnnncnnnnnnnnnnnnn nn n nn nnnnnnn A 3 Intel XScale Microarchitecture User s Manual intel Introduction 1 1 1 1 1 1 Note 1 1 2 About This Document This document describes the Intel XScale core as implemented in the PXA255 processor Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Intel retains the right to make changes to these specifications at any time without notice In particular descriptions of features timings and pin outs does not imply a commitment to implement them How to Read This Document It is necessary to be familiar with the ARM Version 5TE Architecture in order to understand some aspects of this document Each chapter in this document focuses on a specific architectura
31. are evaluated to be true Once in the branch target buffer the Intel XScale core dynamically predicts the outcome of these instructions based on previous outcomes Table 11 1 shows the branch latency penalty when these instructions are correctly predicted and when they are not A penalty of zero for correct prediction means that the Intel XScale core can execute the next instruction in the program flow in the cycle following the branch Table 11 1 Branch Latency Penalty Core Clock Cycles Description ARM Thumb Predicted Correctly The instruction matches in the branch target buffer and is ii 0 correctly predicted Mispredicted There are three occurrences of branch misprediction all of which incur a 4 cycle branch delay penalty 1 The instruction is in the branch target buffer and is predicted not taken but 4 5 is actually taken 2 The instruction is not in the branch target buffer and is a taken branch 3 The instruction is in the branch target buffer and is predicted taken but is actually not taken Intel XScale Microarchitecture User s Manual 11 1 Performance Considerations n 11 2 11 2 1 Instruction Latencies The latencies for all the instructions are shown in the following sections with respect to their functional groups branch data processing multiply status register access load store semaphore and coprocessor The load and store addressing modes implement
32. as opposed to LDM STM which issues in four clock cycles Avoid LDRDs targeting R12 this incurs an extra cycle of issue latency The LDRD instruction has a result latency of 3 or 4 cycles depending on the destination register being accessed assuming the data being loaded is in the data cache add r6 r7 r8 sub r5 r6 r9 The following ldrd instruction would load values into registers r0 and r1 Lara r0 r3 orr r8 rl 0xf mul 175 0 x7 Intel XScale Microarchitecture User s Manual A 5 1 2 Optimization Guide In the code example above the ORR instruction would stall for 3 cycles because of the 4 cycle result latency for the second destination register of an LDRD instruction The code shown above can be rearranged to remove the pipeline stalls The following ldrd instruction would load values into registers r0 and r1 ldrd r0 r3 add r6 r7 r8 sub r5 r6 r9 mul r7 rO r7 orr r8 rl Host Any memory operation following a LDRD instruction LDR LDRD STR and so on would stall for 1 cycle This stall time could be used to execute a data processing instruction The str instruction below would stall for 1 cycle ldrd ro r3 str r4 r5 Scheduling Load and Store Multiple LDM STM LDM and STM instructions have an issue latency of 2 20 cycles depending on the number of registers being loaded or stored The issue latency is typically 2 cycles plus an additional cycle for each of the registers be
33. buffer is allocated for each cache read miss A fill buffer is also allocated for each cache write miss if the memory space is write allocate along with a pending buffer A subsequent read to the same cache line does not require a new fill buffer but does require a pending buffer and a subsequent write will also require a new pending buffer A fill buffer is also allocated for each read to a non cached memory page and a write buffer is needed for each memory write to non cached memory that is non coalescing Consequently a STM instruction listing eight registers and referencing non cached memory will use eight write buffers assuming they don t coalesce and two write buffers if they do coalesce A cache eviction requires a write buffer for each dirty bit set in the cache line The prefetch instruction requires a fill buffer for each cache line and 0 1 or 2 write buffers for an eviction When adding prefetch instructions caution must be asserted to insure that the combination of prefetch and instruction bus requests do not exceed the system resource capacity described above or performance will be degraded instead of improved The important points are to spread prefetch operations over calculations so as to allow bus traffic to free flow and to minimize the number of necessary prefetches Intel XScale Microarchitecture User s Manual A 19 Optimization Guide n A 4 4 6 A 20 Cache Memory Considerations Stride the way data structur
34. codes in this register select the specific test operation performed and the test data register accessed These instructions can be either mandatory or optional as set forth in the IEEE Std 1149 1a 1993 user defined or private The instruction register is a 5 bit wide serial shift register Data is loaded into the IR serially through the TDI pin clocked by the rising edge of TCK when the TAP controller is in the Shift IR state The most significant bit of the IR is connected to TDI and the least significant bit is connected to TDO TDI is shifted into IR on the rising edge of TCK as long as TMS remains asserted Upon activation of the nTRST pin the latched instruction asynchronously changes to the idcode instruction Boundary Scan Instruction Set The application processor supports three mandatory public boundary scan instructions extest sample preload bypass It also supports three optional public instructions idcode clamp highz four user defined instructions dbgrx Idic desr dbgtx and fourteen private instructions The application processor does not support the optional public instructions runbist intest or usercode Table 9 2 summarizes these boundary scan instruction codes Table 9 3 describes each of these instructions in detail Table 9 2 JTAG Instruction Codes Instruction Code Instruction Name Instruction Code Instruction Name 00000 extest 01010 private 00001 sample preload
35. counter in the debug handler code This avoids the problem were the debugger s loop counter is out of synchronization with the debug handler s counter because of overflow conditions that may have occurred DBG FLUSH DBG FLUSH allows the debugger to flush any previous data written to RX Setting DBG FLUSH clears TXRXCTRL 31 Debug JTAG Data Register Reset Values Upon asserting TRST the DEBUG data register is reset Assertion of the reset pin does not affect the DEBUG data register Table 10 15 shows the reset and TRST values for the data register Note these values apply for DBG REG for SELDCSR DBGTX and DBGRX Table 10 15 DEBUG Data Register Reset Values 10 11 1011 1 Intel XScale Microarchitecture User s Manual Bit TRST RESET DBG REG 0 0 unchanged DBG REG 1 0 unchanged DBG REG 33 2 unpredictable unpredictable DBG REG 34 0 unchanged Trace Buffer The 256 entry trace buffer provides the ability to capture control flow information to be used for debugging an application Two modes are supported 1 The buffer fills up completely and generates a debug exception Then software empties the buffer 2 The buffer fills up and wraps around until it is disabled Then software empties the buffer Trace Buffer CP Registers CP14 defines three registers see Table 10 16 for use with the trace buffer These CP14 registers are accessible using MRC MCR LDC and STC CDP to any CP14 regist
36. disabled to allow normal operation of the application processor Test logic is disabled by loading the idcode register No matter what the state of the controller it enters Test Logic Reset state when the TMS input is held high 1 for at least five rising edges of TCK The controller remains in this state while TMS is high The TAP controller is also forced to enter this state by enabling nTRST If the controller exits the Test Logic Reset controller states as a result of an erroneous low signal on the TMS line at the time of a rising edge on TCK for example a glitch due to external interference it returns to the test logic reset state following three rising edges of TCK with the TMS line at the intended high logic level Test logic operation is such that no disturbance is caused to on chip system logic operation as the result of such an error Run Test Idle State The TAP controller enters the Run Test Idle state between scan operations The controller remains in this state as long as TMS is held low In the Run Test Idle state the runbist instruction is performed the result is reported in the RUNBIST register Instructions that do not call functions Intel XScale Microarchitecture User s Manual 9 9 Test 9 5 3 9 5 4 9 5 5 9 5 6 intel generate no activity in the test logic while the controller is in this state The instruction register and all test data registers retain their current state When TMS is high on the ris
37. downloaded into the mini IC is valid in the mini IC so it is not necessary to download the same code again If it is necessary to download code into the instruction cache then 2 Assert TRST halting the device awaiting activity on the JTAG interface 3 Clear the Halt Mode bit through JTAG This allows the instruction cache to be invalidated by reset 4 Place the LDIC JTAG instruction in the JTAG IR then proceed with the normal code download using the Invalidate IC Line function before loading each line This requires 10 packets to be downloaded per cache line instead of the 9 packets as described in Section 10 13 3 Intel XScale Microarchitecture User s Manual 10 37 Software Debug I ntel a 10 13 5 Dynamically Loading IC After Reset An external host can load code into the instruction cache on the fly or dynamically This occurs when the host downloads code while the processor is not being reset However this requires strict synchronization between the code running on the Intel XScale core and the external host The guidelines for downloading code during program execution must be followed to ensure proper operation of the processor The description in this section focuses on using a debug handler running on the Intel XScale core to synchronize with the external host but the details apply for any application that is running while code is dynamically downloaded To dynamically download code during softwar
38. handler read returns the newly written data and the previous data is lost However in this specific case the overflow flag does not get set so the debugger is unaware that the download was not successful Intel XScale Microarchitecture User s Manual intel Performance Considerations 11 11 1 This chapter describes performance considerations that compiler writers application programmers and system designers need to be aware of to efficiently use the Intel XScale core Performance numbers discussed here include branch prediction and instruction latencies The timings in this section are specific to the PXA255 processor and how it implements the ARM vSTE architecture This is not a summary of all possible optimizations nor is it an explanation of the ARM vSTE instruction set For information on instruction definitions and behavior consult the ARM Architecture Reference Manual Branch Prediction The Intel XScale core implements dynamic branch prediction for the ARM instructions B and BL and for the Thumb instruction B Any instruction that specifies the PC as the destination is predicted as not taken and is not entered into the BTB For example an LDR or a MOV that loads or moves directly to the PC will be predicted not taken and incur a branch latency penalty The instructions B and BL including Thumb enter into the branch target buffer when they are taken for the first time A taken branch refers to when they
39. incurred by the code shown above can be prevented by rearranging the code mra r6 r7 acco add r2 r2 1 mov rO r6 mov ri r7 The MAR MCRR instruction has an issue latency a result latency and a resource latency of 2 cycles Due to the 2 cycle issue latency the pipeline would always stall for 1 cycle following a MAR instruction The use of the MAR instruction should therefore be used only where absolutely necessary A 5 6 Scheduling the MIA and MIAPH Instructions The MIA instruction has an issue latency of 1 cycle The result and resource latency can vary from 1 to 3 cycles depending on the values in the source register Consider the following code sample mia accO r2 r3 mia accO r4 r5 The second MIA instruction above can stall from 0 to 2 cycles depending on the values in the registers r2 and r3 due to the 1 to 3 cycle resource latency Similarly consider the following code sample mia accO r2 r3 mra r4 r5 accO The MRA instruction above can stall from 0 to 2 cycles depending on the values in the registers r2 and r3 due to the 1 to 3 cycle result latency The MIAPH instruction has an issue latency of 1 cycle result latency of 2 cycles and a resource latency of 2 cycles Consider the code sample shown below add rl x2 3 miaph accO r3 r4 miaph accO r5 r6 mra r6 r7 acco sub r8 r3 r4 The second MIAPH instruction would stall for 1 cycle due to a 2 cycle resource latency The MRA instructio
40. instruction A conditional branch instruction can then be used to exit or continue with the next loop iteration Consider the following C code segment for i 10 i 0 i do something Intel XScale Microarchitecture User s Manual A 7 Optimization Guide n A 3 1 2 A 8 The optimized code generated for the above code segment would look like L6 subs r3 r3 1 bne L6 It is also beneficial to rewrite loops whenever possible so as to make the loop exit conditions check against the value 0 For example the code generated for the code segment below will need a compare instruction to check for the loop exit condition for i 0 i lt 10 i do something If the loop were rewritten as follows the code generated avoids using the compare instruction to check for the loop exit condition for i 9 i gt 0 i do something Optimizing Branches Branches decrease application performance by indirectly causing pipeline stalls Branch prediction improves the performance by lessening the delay inherent in fetching a new instruction stream The number of branches that can accurately be predicted is limited by the size of the branch target buffer Since the total number of branches executed in a program is relatively large compared to the size of the branch target buffer it is often beneficial to minimize the number of branches in a program Consider the following C code segment
41. into different memory banks or by paralleling the data structures such that the data resides within the same memory page It is also extremely important to insure that instruction and data sections are in different memory banks or they will continually trash the memory page selection Prefetch Considerations The Intel XScale core has a true prefetch load instruction PLD The purpose of this instruction is to preload data into the data and mini data caches Data prefetching allows hiding of memory transfer latency while the processor continues to execute instructions The prefetch is important to compiler and assembly code because judicious use of the prefetch instruction can enormously improve throughput performance of the Intel XScale core Data prefetch can be applied not only to loops but also to any data references within a block of code Prefetch also applies to data writing when the memory type is enabled as write allocate The Intel XScale core prefetch load instruction is a true prefetch instruction because the load destination is the data or mini data cache and not a register Compilers for processors which have data caches but do not support prefetch sometimes use a load instruction to preload the data cache This technique has the disadvantages of using a register to load data and requiring additional registers for subsequent preloads and thus increasing register pressure By contrast the prefetch can be used to reduce re
42. p ee eate 4 5 4 3 3 Invalidating the Instruction Cache 4 5 4 3 4 Locking Instructions in the Instruction Cache 4 6 4 3 5 Unlocking Instructions in the Instruction Cache 4 7 5 Branch Target Buffer 2 5 n oci edi a pee o EE de d eee ee cue LO ee bu Luce a aep Is 5 1 5 1 Branch Target Buffer BTB Operation 5 1 DEN D CI DEEP 5 2 Ste Update Policy toe hee ma eens 5 2 5 2 BTB Gontroll sacco Seele EE a n e ER frr dee 5 2 5 21 Disabling Enablitig ipee nde ee decies uela 5 2 5 2 2 gt InValidation ice ter ee eec co e cemere ect eda toca ced da 5 3 6 Data Cache ui se daret eit t Ne ed etes it a dete dad edad 6 1 6 1 OVerVIeWS instituta titt iuveni eege bett v de egi e e 6 1 6 1 1 Data Cache OVerVvi6Wx eoe re N ade ote a tae eaa 6 1 6 1 2 Mini Data Cache Overview cccccccccessecceeccecesseeeeeeceaeesceceeeceasnseeeeeeaneeeeseteneasnes 6 2 6 1 3 Write Buffer and Fill Buffer Ovenlew menn 6 3 6 2 Data Cache and Mini Data Cache Operation 6 4 6 2 1 Operation When Caching is Cnabiled nenn 6 4 6 2 2 Operation When Data Caching is Disabled se 6 4 6 2 3 Cache Policies nir d Leve eter aaa 6 4 6 2 3 1 Cacheability u ect es I iR ka 6 4 6 2 3 2 Read Miss ole iii ieh 6 4 6 2 3 3 Write Miss Policy 6 5 6 2 3 4 Write Back Versus Write Through ns nnnnnnnnnnnnnnnn nn 6 6 6 2 4 Round Robin Replacement Algorithm nen 6 6 6 2 5 Parity Protection iiic de el ae it 6 6 6 2 6 AtomiC ACCOSSOS ei dee o
43. pipelined as the processing of a single instruction may require use of the same datapath resources for several cycles before a new instruction can be accepted The type of instruction and source arguments determines the number of cycles required No more than two instructions can occupy the MAC pipeline concurrently When the MAC is processing an instruction another instruction may not enter M1 unless the original instruction completes in the next cycle The MAC unit can operate on 16 bit packed signed data This reduces register pressure and memory traffic size Two 16 bit data items can be loaded into a register with one LDR The MAC can achieve throughput of one multiply per cycle when performing a 16 by 32 bit multiply Intel XScale Microarchitecture User s Manual Intel A 2 5 1 A 3 A 3 1 A 3 1 1 Optimization Guide Behavioral Description The execution of the MAC unit starts at the beginning of the M1 pipestage where it receives two 32 bit source operands Results are completed N cycles later where N is dependent on the operand size and returned to the register file For more information on MAC instruction latencies refer to Section 11 2 Instruction Latencies An instruction that occupies the M1 or M2 pipestages will also occupy the X1 and X2 pipestage respectively Each cycle a MAC operation progresses for M1 to M5 A MAC operation may complete anywhere from M2 M5 If a MAC operation enters
44. policies which can be configured differently for each application Cache locking All these features improve the efficiency of the memory bus external to the core The Intel XScale core efficiently handles audio processing through the support of 16 bit data types and enhanced 16 bit operations These audio coding enhancements center around multiply and accumulate operations which accelerate many of the audio filtering and multimedia CODEC algorithms ARM Compatibility ARM Version 5 V5 Architecture added new features to ARM Version 4 including among other inclusions floating point instructions The Intel XScale core implements the integer instruction set of ARM V5 but does not provide hardware support for any of the floating point instructions Intel XScale Microarchitecture User s Manual 1 2 2 Introduction The Intel XScale core provides the ARM V5T Thumb instruction set and the ARM V5E DSP extensions To further enhance multimedia applications the Intel XScale core includes additional Multiply Accumulate functionality as the first instantiation of Intel amp Media Processing Technology These new operations from Intel are mapped into ARM coprocessor space Backward compatibility with StrongARM products is maintained for user mode applications p y g p pp Operating systems may require modifications to match the specific hardware features of the Intel XScale core and to take advantage of the
45. reads to be outstanding Another key function of the Fill Intel XScale Microarchitecture User s Manual i ntel Introduction Buffer along with the Instruction Fetch Buffers is to allow the application processor external SDRAM to be read as 4 word bursts rather than single word accesses improving overall memory bandwidth Both the Fill Pend and Write buffers help to decouple core speed from any limitations to accessing external memory Further details on these buffers can be found in Section 6 5 Write Buffer Fill Buffer Operation and Control on page 6 13 1 2 2 7 Performance Monitoring Two performance monitoring counters have been added to the Intel amp XScaleTM core that can be configured to monitor various events in the Intel XScaleTM core These events allow a software developer to measure cache efficiency detect system bottlenecks and reduce the overall latency of programs Refer to Chapter 8 Performance Monitoring for more information 1 2 2 8 Power Management The Intel XScale core incorporates a power and clock management unit that can assist ASSPs in controlling their clocking and managing their power These features are described in Section 7 3 CP14 Registers on page 7 15 1 2 2 9 Debug Intel XScale core supports software debugging through two instruction address breakpoint registers one data address breakpoint register one data address mask breakpoint register a mini instruction
46. reset vector and do any necessary setup before the application code executes Any code downloaded into the instruction cache through JTAG must be downloaded to addresses that are not already valid in the instruction cache Failure to meet this requirement will result in unpredictable behavior by the processor During a processor reset the instruction cache is typically invalidated with the exception of the following modes LDIC mode active when LDIC JTAG instruction is loaded in the JTAG IR prevents the mini instruction cache and the main instruction cache from being invalidated during reset Intel XScale Microarchitecture User s Manual 10 33 Software Debug I ntel ii Note 10 13 4 1 10 34 HALT mode active when the Halt Mode bit is set in the DCSR prevents only the mini instruction cache from being invalidated main instruction cache is invalidated by reset During a cold reset in which both a processor reset and a JTAG reset occurs it can be guaranteed that the instruction cache will be invalidated since the JTAG reset takes the processor out of any of the modes listed above During a warm reset if a JTAG reset does not occur the instruction cache is not invalidated by reset when any of the above modes are active This situation requires special attention if code is downloaded during the warm reset While Halt Mode is active reset can invalidate the main instruction cache Thus debug handler code downloaded dur
47. the Intel XScale core as Implemented in the Application Processors The Intel XScale core is an ARM VSTE compliant microprocessor It is a high performance and low power device that leads the industry in MIPS mW The core is not intended to be delivered as a stand alone product but as a building block for an ASSP Application Specific Standard Product with embedded markets such as handheld devices networking storage remote access servers etc The PXA255 processor is an example of an ASSP designed primarily for handheld devices This document limits itself to describing the implementation of the Intel XScale core as it is implemented in the PXA255 processor In almost every attribute the Intel amp XScaleTM core used in the application processor is identical to the Intel XScale core implemented in the Intel amp 80200 The Intel XScale core incorporates an extensive list of microarchitecture features that allow it to achieve high performance This rich feature set lets you select the appropriate features that obtain the best performance for your application Many of the micro architectural features added to the Intel XScale core help hide memory latency which often is a serious impediment to high performance processors This includes The ability to continue instruction execution even while the data cache is retrieving data from external memory A write buffer Write back caching Various data cache allocation
48. the RX register Table 10 9 Normal RX Handshaking 10 12 Debugger Actions Debugger wants to send data to debug handler Before writing new data to the RX register the debugger polls RR through JTAG until the bit is cleared After the debugger reads a 0 from the RR bit it scans data into JTAG to write to the RX register and sets the valid bit The write to the RX register automatically sets the RR bit Debug Handler Actions Debug handler is expecting data from the debugger The debug handler polls the RR bit until it is set indicating data in the RX register is valid Once the RR bit is set the debug handler reads the new data from the RX register The read operation automatically clears the RR bit When data is being downloaded by the debugger part of the normal handshaking can be bypassed to allow the download rate to be increased Table 10 10 shows the handshaking used when the debugger is doing a high speed download Before the high speed download can start both the debugger and debug handler must be synchronized such that the debug handler is executing a routine that supports the high speed download Intel XScale Microarchitecture User s Manual Software Debug Although it is similar to the normal handshaking the debugger polling of RR is bypassed with the assumption that the debug handler can read the previous data from RX before the debugger can scan in the new data Table 10 10
49. values usually about half the trace buffer length apart Intel XScale Microarchitecture User s Manual intel 10 11 1 2 Software Debug This is always the case as the messages in the trace buffer vary in length With two entries the first oldest entry that set a checkpoint in the trace buffer corresponds to CHKPT1 the second entry that set a checkpoint corresponds to CHKPTO Although the checkpoint registers are provided for wrap around mode they are still valid in fill once mode Trace Buffer Register TBREG The trace buffer is read through TBREG using MRC and MCR Software can only read the trace buffer when it is disabled Reading the trace buffer while it is enabled will cause unpredictable behavior of the trace buffer Writes to the trace buffer have unpredictable results Reading the trace buffer returns the oldest byte in the trace buffer in the least significant byte of TBREG The byte is either a message byte or one byte of the 32 bit address associated with an indirect branch message Table 10 18 shows the format of the trace buffer register Table 10 18 TBREG Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 reset value unpredictable Bits Access Description 31 8 Read as Zero Write ignored Reserved 7 0 Read Write unpredictable Message Byte or Address Byte 10 11 2 Trace Buffer Usage The Intel XScale core trace buffer is 256 b
50. write RO to PMNC Counting begins Counter overflow can be dealt with in the IRQ interrupt service routine as shown below Example 8 2 Interrupt Handling IRO INTERRUPT SERVICE ROUTINE Assume that performance counting interrupts are the only IRQ in the system MRC P14 0 R1 C0 c0 0 read the PMNC register BIC R2 R1 1 Clear the enable bit MCR P14 0 R2 C0 c0 0 clear interrupt flag and disable counting MRC P14 0 R3 C1 c0 0 read CCNT register MRC P14 0 R4 C2 c0 0 read PMNO register MRC P14 0 R5 C3 c0 0 read PMN1 register process the results SUBS PC R14 4 return from interrupt As an example assume the following values in CCNT PMNO PMNI and PMNC Example 8 3 Computing the Results Assume CCNT overflowed CCNT 0x0000 0020 Overflowed and continued counting Number of instructions executed PMNO 0x6AAA AAAA Number of instruction cache miss requests PMN1 0x0555 5555 Instruction Cache miss rate 100 PMN1 PMNO 5 CPI CCNT 2 32 Number of instructions executed 2 4 cycles instruction In the contrived example above the instruction cache had a miss rate of 5 and CPI was 2 4 Intel XScale Microarchitecture User s Manual 8 9 Performance Monitoring 8 10 Intel XScale Microarchitecture User s Manual INTal Test 9 The application processor Test Access Port TAP conforms to the IEEE Std 1149 1 1990 IEEE Std 1149 1a 1993 Standard
51. 0 sub X pr r2 Scheduling Multiply Instructions Multiply instructions can cause pipeline stalls due to either resource conflicts or result latencies The following code segment would incur a stall of 0 3 cycles depending on the values in registers r1 r2 r4 and r5 due to resource conflicts mul O TL x2 mul r3 r4 r5 The following code segment would incur a stall of 1 3 cycles depending on the values in registers rl and r2 due to result latency mul T0 EL x2 mov r4 rO Note that a multiply instruction that sets the condition codes blocks the whole pipeline A 4 cycle multiply operation that sets the condition codes behaves the same as a 4 cycle issue operation Consider the following code segment muls r0 rl r2 add r3 r3 1 sub r4 r4 1 sub r5 rb 1 Intel XScale Microarchitecture User s Manual A 5 4 A 5 5 Optimization Guide The add operation above would stall for 3 cycles if the multiply takes 4 cycles to complete It is better to replace the code segment above with the following sequence mul r0 ri r2 add r3 r3 1 sub r4 r4 1 sub r5 r5 1 cmp ro 0 Please refer to Section 11 2 Instruction Latencies to get the instruction latencies for the multiply instructions The multiply instructions should be scheduled taking into consideration these instruction latencies Scheduling SWP and SWPB Instructions The SWP and SWPB instructions have a 5 cycle issue latency As a result of thi
52. 10 4 RX Write e 10 21 10 5 DBGRX Data Register hai naar EVA Md 10 22 10 6High Level View of Trace Buffer enne nennen nnns 10 26 10 7Message Byte Fomati erosin a lei 10 27 10 8Indirect Branch Entry Address Byte Organization namen 10 30 10 9LDIC JTAG Data Register Hardware 10 31 10 10Format of LDIC Cache Functions ssssessssseneeeeee eene ennemi nne nnns 10 33 10 11Code Download During a Cold Reset For Debug em 10 35 10 12Code Download During a Warm Reset For Debug em 10 37 10 13Downloading Code in IC During Program Execution seem 10 38 A 1 Intel XScale Core RISC Superpipeline nennen A 2 Tables 2 1 Multiply with Internal Accumulate Fomat eee eene 2 4 2 2 MIA lt cond gt acc0 Rm RS see eee 2 4 2 3 MIAPH lt cond gt acc0 Rm Re 2 5 2 4 MIAxy cornid accO RM RS een hin 2 6 2 5 Internal Accumulator Access Fomat eene 2 7 2 6 MAR lt cond gt accO RdLo Hd 2 8 2 7 MRA lt cond gt RdLo RdHi ac 2 8 2 8 First level Descriptors einlassen aan in kenne 2 9 2 9 Second level Descriptors for Coarse Page Table nn 2 9 2 10Second level Descriptors for Fine Page Table sss 2 10 2 11 Exception Summary 2 11 2 12 Event Priority m eek nenne 2 11 2 13Intel amp XScale Core Encoding of Fault Status for Prefetch Aborts 4m 2 12 2 14Intel amp XScale Core Encoding of Fault Status for Data Aborts sssssssss 2 13 3 1 Data Cache and Buffer Behavior when X 0 eem eee 3 2 3 2 Data Cache
53. 10 through 13 support a 256 entry trace buffer Register 14 and 15 are the debug link register and debug SPSR saved program status register These registers are explained in more detail in Chapter 10 Software Debug Opcode 2 and CRm must be zero Intel XScale Microarchitecture User s Manual 7 17 Configuration l n e Table 7 26 Accessing the Debug Registers Function CRn Register Instruction Read Transmit Debug Register TX 0b1000 MRC p14 0 Rd c8 c0 0 Write TX 0b1000 MCR p14 0 Rd c8 c0 0 Read Receive Debug Register RX 0b1001 MRC p14 0 Rd c9 c0 0 Write RX 0b1001 MCR p14 0 Rd c9 c0 0 Read Debug Control and Status Register DCSR 0b1010 MRC p14 0 Rd c10 c0 0 Write DCSR 0b1010 MCR p14 0 Rd c10 c0 0 Read Trace Buffer Register TBREG 0b1011 MRC p14 0 Rd c11 c0 0 Write TBREG 0b1011 MCR p14 0 Rd c11 c0 0 Read Checkpoint 0 Register CHKPTO 0b1100 MRC p14 0 Rd c12 c0 0 Write CHKPTO 0b1100 MCR p14 0 Rd c12 c0 0 Read Checkpoint 1 Register CHKPT1 0b1101 MRC p14 0 Rd c13 c0 0 Write CHKPT1 0b1101 MCR p14 0 Rd c13 c0 0 E n cea Debug Control 0b1110 MRC p14 0 Rd c14 c0 0 Write TXRXCTRL 0b1110 MCR p14 0 Rd c14 c0 0 7 18 Intel XScale Microarchitecture User s Manual intel Performance Monitoring 8 8 1 8 2 This chapter describes the performance monitoring facility of the Intel XScale core
54. 19 18 17 16 15 14 13 12 11109 8 7 6 54 3 21 0 CHKPTx reset value Unpredictable Bits Access Description CHKPTx 31 0 Read Write target address for corresponding entry in trace buffer The two checkpoint registers CHKPTO CHKPT1 on the Intel XScale core provide the debugger with two reference addresses to use for re constructing the trace history When the trace buffer is enabled reading and writing to either checkpoint register has unpredictable results When the trace buffer is disabled writing to a checkpoint register sets the register to the value written Reading the checkpoint registers returns the value of the register In normal usage the checkpoint registers are used to hold the target addresses of specific entries in the trace buffer Direct and indirect entries written into the trace buffer are marked as checkpoints with the corresponding target address being automatically written into the checkpoint registers Exception and roll over messages never use the checkpoint registers When a checkpoint register value is updated the processor sets bit 6 of the message byte in the trace buffer to indicate that the update occurred refer to Table 10 19 Message Byte Formats When the trace buffer contains only one entry relating to a checkpoint the corresponding checkpoint register is CHKPTO When the trace buffer wraps around two entries will typically be marked as relating to checkpoint register
55. 2 1 3 Out Of Order Completion ent A 3 A 2 1 4 Register Dependencies seeessssssseeeeeneen nennen nnn nnns A 3 A 2 1 5 Use of ByPaSSing ccccecccccceeeeccceeceeeeecceeeeseeeeeceneneeeaeeeeesteaaeeneeneaaes A 3 A 2 2 Instruction Flow Through the Pipeline see A 4 A 2 2 1 ARM v5 Instruction Execution eseseeeseessenerennsensserrerrnrrrnrrnnsensseent A 4 A222 Pipeline Stalls eite etr tera iEn eee Cere d De Er eet de eae A 4 A 2 3 Main Execution Pipeline sess emen A 4 A 2 3 1 F1 F2 Instruction Fetch Pipestages A 4 A 2 3 2 ID Instruction Decode Pipestage eeeeeeeeeeeeeseeerreserrrrrseerrressreees A 5 A 2 3 3 RF Register File Shifter Pipestage nn A 5 A 2 3 4 X1 Execute Pipestages meme A 5 A 2 3 5 X2 Execute 2 Pipestage eee A 6 A 2 3 6 XWB write Dack 1n nk xe tette ederet teer eet ii eer ee d e A 6 A 2 4 Memory Pipelne eraai nte nnne nnne then nen tette nnne A 6 AX2 4 1 Di and D2 Pipestage eec teedetetetelutsdteete te A 6 A 2 5 Multiply Multiply Accumulate MAC Pipeline ssoseesseeeeneeeserresseerrsssrerrrsreerrrsssee A 6 A 2 5 1 Behavioral Description A 7 AS Basic Optimizations eei eoe RUNE MR tune hens aan A 7 A 3 1 Conditional Instruchons nennen A 7 A 3 1 1 Optimizing Condition Checks nn A 7 A 3 1 2 Optimizing Branches emen A 8 A 3 1 3 Optimizing Complex Expressions ssssesnennrtnesseeseeesrt rn rrn rr
56. 2 2 2 A 2 3 A 2 3 1 A 4 Instruction Flow Through the Pipeline The Intel XScale core pipeline issues a single instruction per clock cycle Instruction execution begins at the Fl pipestage and completes at the XWB pipestage Although a single instruction may be issued per clock cycle all three pipelines MAC memory and main execution may be processing instructions simultaneously If there are no data hazards then each instruction may complete independently of the others Each pipestage takes a single clock cycle or machine cycle to perform its subtask with the exception of the MAC unit ARM v5 Instruction Execution Figure A 1 uses arrows to show the possible flow of instructions in the pipeline Instruction execution flows from the F1 pipestage to the RF pipestage The RF pipestage may issue a single instruction to either the X1 pipestage or the MAC unit multiply instructions go to the MAC while all others continue to X1 This means that at any instant either M1 or X1 will be idle All load store instructions are routed to the memory pipeline after the effective addresses have been calculated in X1 The ARM v5 BLX branch and exchange instruction which is used to branch between ARM and THUMB code causes the entire pipeline to be flushed The BLX instruction is not dynamically predicted by the BTB If the processor is in Thumb mode then the ID pipestage dynamically expands each Thumb instruction into a normal ARM
57. 2 DR state Exit2 DR State This is a temporary state If TMS is held high on the rising edge of TCK the controller enters the Update DR state which terminates the scanning process If TMS is held low on the rising edge of TCK the controller enters the Shift DR state The instruction does not change while the TAP controller is in this state All test data registers selected by the current instruction retain their previous value during this state Update DR State The Boundary Scan register is provided with a latched parallel output This output prevents changes at the parallel output while data is shifted in response to the extest sample preload instructions When the Boundary Scan register is selected while the TAP controller is in the Update DR state data is latched onto the Boundary Scan register s parallel output from the shift register path on the falling edge of TCK The data held at the latched parallel output does not change unless the controller is in this state While the TAP controller is in this state all of the test data register s shift register bit positions selected by the current instruction retain their previous values The instruction does not change while the TAP controller is in this state When the TAP controller is in this state and TMS is held high on the rising edge of TCK the controller enters the Select DR Scan state If TMS is held low on the rising edge of TCK the controller enters the Run Test Idle state
58. 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 MA reset value writable bits set to 0 Bits Access Description 31 2 Read unpredictable Write as Zero Reserved Mode M 0 ACTIVE 1 0 Read Write 1 Idle Mode 2 Reserved 3 Sleep Mode Software can change core clock frequency by writing to CP 14 register 6 CCLKCFG Table 7 24 CCLKCFG Register 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 0 CCLKCFG reset value unpredictable Bits Access Description 31 4 Read unpredictable Write as Zero Reserved Core Clock Configuration CCLKCFG 0b0001 Enter Turbo Mode 3 0 Read Write 0b001x Enter Frequency Change Sequence Turbo Mode bit may be set or cleared in the same write Other values are reserved Table 7 25 Clock and Power Management valid operations Function Data Instruction Enter Idle Mode 1 MCR p14 0 Rd c7 c0 0 Reserved 2 MCR p14 0 Rd c7 c0 0 Enter Sleep Mode 3 MCR p14 0 Rd c7 c0 0 Read CCLKCFG ignored MRC p14 0 Rd c6 c0 0 Write CCLKCFG CCLKCFG value MCR p14 0 Rd c6 c0 0 7 3 3 Registers 8 15 Software Debug Software debug is supported by address breakpoint registers Coprocessor 15 register 14 serial communication over the JTAG interface and a trace buffer Registers 8 and 9 are used for the serial interface and registers
59. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 reset value unpredictable Bits Access Description 31 11 Read unpredictable Write as Zero Reserved Status Field Extension X This bit is used to extend the encoding of the Status field 10 Read Write when there is a prefetch abort See Table 2 13 on page 2 12 and when there is a data abort See Table 2 14 on page 2 13 Debug Event D 9 Read Write This flag indicates a debug event has occurred and that the cause of the debug event is found in the MOE field of the debug control register CP14 register 10 8 Read as zero Write as Zero 0 Domain Specifies which of the 16 domains was being Read Write accessed when a data abort occurred Status Used along with the X bit above to determine the 3 0 Read Write type of cycle type that generated the exception See Event Architecture on page 2 11 7 8 Intel XScale Microarchitecture User s Manual intel T 2 6 Configuration Register 6 Fault Address Register Table 7 11 Fault Address Register 7 2 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 0 Fault Virtual Address reset value unpredictable Bits Access Description Fault Virtual Address Contains the MVA of the data 31 0 Read Write access that caused the memory abort Register 7 Cache Functions Al
60. 5 4 3 2 1 0 reset value 0x0000 0000 Bits Access Description Reserved Should be programmed to zero for future 31 16 Read unpredictable Write as Zero compatibility 7 14 Intel XScale Microarchitecture User s Manual n Configuration Table 7 20 Coprocessor Access Register Sheet 2 of 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 0 reset value 0x0000 0000 Bits Access Description Reserved Should be programmed to zero for future 15 14 Read as Zero Write as Zero end compatibility Coprocessor Access Rights Each bit in this field corresponds to the access rights for 13 1 Read Write each coprocessor Only CPO has any effect on the application processors CP1 CP 13 must always be written as zero Coprocessor Access Rights This bit corresponds to the access rights for CPO 0 Read Write 0 7 Access denied Any attempt to access the corresponding coprocessor will generate an Undefined exception even in privileged modes 17 Access allowed Includes read and write accesses A typical use for this register is for an operating system to control resource sharing among applications All applications can be denied access to CPO by clearing the appropriate coprocessor bit in the Coprocessor Access Register An application may request the use of the accumulator in CPO by issuing an access to the resource which will result in an
61. Ali 1 D i Ali clil The second loop reuses the data elements A i and c i Fusing the loops together produces for i 0 i lt NMAX i prefetch D i 1 A i 1 c i 1 bli 1 ai bli clil A i ai D il ai clil Prefetch to Reduce Register Pressure Prefetch can be used to reduce register pressure When data is needed for an operation then the load is scheduled far enough in advance to hide the load latency However the load ties up the receiving register until the data can be used For example ldr r2 r0 Process code not yet cached latency gt 30 core clocks add EE E X2 Intel XScale Microarchitecture User s Manual A 23 E Optimization Guide ntel A 5 A 5 1 A 24 In the above case r2 is unavailable for processing until the add statement Prefetching the data load frees the register for use The example code becomes pid r0 prefetch the data keeping r2 available for use Process code ldr r2 ro Process code ldr result latency is 3 core clocks add rb rd YA With the added prefetch register r2 can be used for other operations until just before it is needed Instruction Scheduling This chapter discusses instruction scheduling optimizations Instruction scheduling refers to the rearrangement of a sequence of instructions for the purpose of minimizing pipeline stalls Reducing the number of pipeline stalls improves application performance While making thi
62. Branch Target of any previously running process A breakpoint address see Section 7 2 12 Register 14 Breakpoint Registers on page 7 13 must be expressed as an MVA when written to the breakpoint register This means the value of the PID must be combined appropriately with the address before it is written to the breakpoint register All virtual addresses in translation descriptors see Chapter 3 Memory Management are MVAs Register 14 Breakpoint Registers The Intel XScale core contains two instruction breakpoint address registers IBCRO and IBCR1 one data breakpoint address register DBRO one configurable data mask address register DBRI and one data breakpoint control register DBCON The Intel XScaleTM core also supports a 2K byte mini instruction cache for debugging and a 256 entry trace buffer that records program execution information The registers to control the trace buffer are located in CP14 Refer to Chapter 10 Software Debug for more information on these features of the Intel XScale core Table 7 19 Accessing the Debug Registers Sheet 1 of 2 Function opcode 2 CRm Instruction Read Instruction Breakpoint Register 0 IBCRO 0b000 0b1000 MRC p15 0 Rd c14 c8 0 Write IBCRO 0b000 0b1000 MCR p15 0 Rd c14 c8 0 Read Instruction Breakpoint Register 1 IBCR1 0b000 0b1001 MRC p15 0 Rd c14 c9 0 Write IBCR1 0b000 0b1001 MCR p15 0 Rd c14 c9 0 Read
63. CO O if RX is valid read it bpl loop if RX is not valid loop 10 8 Transmit Register TX The TX register is the debug handler transmit buffer The debug handler sends data to the debugger through this register Table 10 13 TX Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 TX reset value unpredictable Bits Access Description Software Read Write 31 0 Debug handler writes data to send to debugger JTAG Read only Since the TX register is accessed by the debug handler using MCR MRC and the debugger through JTAG handshaking is required to prevent the debug handler from writing new data before the debugger reads the previous data The TX register handshaking is described in Table 10 11 TX Handshaking on page 10 14 10 9 Receive Register RX The RX register is the receive buffer used by the debug handler to get data sent by the debugger through the JTAG interface Table 10 14 RX Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 RX reset value unpredictable Bits Access Description 31 0 Software Read only Software reads to receives data commands from JTAG Write only debugger Since the RX register is accessed by the debug handler using MRC and the debugger through JTAG handshaking is required to prevent the debugger from writing new data to the register before the debug han
64. CRx E reset value unpredictable address disabled Bits Access Description Instruction Breakpoint MVA in ARM mode IBCRx 1 is ignored IBCRx Enable E 0 Read Write 0 Breakpoint disabled 17 Breakpoint enabled 31 1 Read Write An instruction breakpoint will generate a debug exception before the instruction at the address specified in the IBCR executes When an instruction breakpoint occurs the processor sets the DBCR MOE bits to 0b001 Software must disable the breakpoint before exiting the handler This allows the breakpointed instruction to execute after the exception is handled Single step execution is accomplished using the instruction breakpoint registers and must be completely handled in software either on the host or by the debug handler 10 5 2 Data Breakpoints The Intel XScale core debug architecture defines two data breakpoint registers DBRO DBR1 The format of the registers is shown in Table 10 6 Table 10 6 Data Breakpoint Register DBRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 0 DBRx reset value unpredictable Bits Access Description DBRO Data Breakpoint MVA 31 0 Read Write DBR1 Data Address Mask OR Data Breakpoint MVA DBRO is a dedicated data address breakpoint register DBR1 can be programmed for 1 of 2 operations Intel XScale Microarchitecture User s Manual 10 9 Softwa
65. Event Priority Reset Vector Trap Data Abort precise Data Breakpoint Data Abort imprecise External debug break Trace buffer full FIQ IRQ Instruction Breakpoint Prefetch Abort Undefined SWI BKPT O 0 di Ou a Ei Goal m o a See Vector Trap Bits TF TI TD TA TS TU TR on page 10 4 for vector trap options Halt Mode The debugger turns on Halt mode through the JTAG interface by scanning in a value that sets the bit in DCSR The debugger turns off Halt mode through JTAG either by scanning in a new DCSR value or by a TRST Processor reset does not effect the value of the Halt mode bit When halt mode is active the processor uses the reset vector as the debug vector The debug handler and exception vectors can be downloaded directly into the instruction cache to intercept the default vectors and reset handler or they can be resident in external memory Downloading into the instruction cache allows a system with memory problems or no external memory to be debugged Refer top Section 10 13 Downloading Code into the Instruction Cache on page 10 30 for details about downloading code into the instruction cache During Halt mode software running on the Intel XScale core cannot access DCSR or any of hardware breakpoint registers unless the processor is in Special Debug State SDS described below When a debug exception occurs during Halt m
66. Halt Mode Software Protocol This section describes the overall debug process in Halt Mode It describes how to start and end a debug session and provides details for implementing a debug handler Intel may provide a standard Debug Handler that implements some of the techniques in this chapter This code and other documentation describing additional handler implementation techniques and requirements is intended for manufacturers of debugging tools Starting a Debug Session Prior to starting a debug session in Halt Mode the debugger must download code into the instruction cache during reset via JTAG Section 10 Downloading Code into the Instruction Cache This downloaded code should consist of adebug handler an override default vector table an override relocated vector table if necessary Intel XScale Microarchitecture User s Manual intel 10 14 1 1 10 14 1 2 Software Debug While the processor is still in reset the debugger sets up the DCSR to trap the reset vector This causes a debug exception to occur immediately when the processor comes out of reset Execution is redirected to the debug handler allowing the debugger to perform any necessary initialization The reset vector trap is the only debug exception that can occur with debug globally disabled DCSR 31 0 Therefore the debugger must also enable debug prior to exiting the handler to ensure all subsequent debug exceptions correctly break to the deb
67. High Speed Download Handshaking States 10 7 2 10 7 3 Debugger Actions Debugger wants to transfer code into the Intel amp XScale core system memory Prior to starting download the debugger must poll the RR bit until it is clear Once the RR bit is clear indicating the debug handler is ready the debugger starts the download The debugger scans data into JTAG to write to the RX register with the download bit and the valid bit set Following the write to RX the RR bit and D bit are automatically set in TXRXCTRL Without polling of RR to see whether the debug handler has read the data just scanned in the debugger continues scanning in new data into JTAG for RX with the download bit and the valid bit set An overflow condition occurs if the debug handler does not read the previous data before the debugger completes scanning in the new data see Section 10 Overflow Flag OV for more details on the overflow condition After completing the download the debugger clears the D bit allowing the debug handler to exit the download loop Debug Handler Actions Debug handler is in a routine waiting to write data out to memory The routine loops based on the D bit in TXRXCTRL The debug handler polls the RR bit until it is set It then reads the Rx register and writes it out to memory The handler loops repeating these operations until the debugger clears the D bit Overflow Flag OV The Overflow flag is a st
68. If the first non zero entry is any other type of message byte then these 0 s indicate that the trace buffer has not wrapped around and that first non zero entry is the start of the trace Intel XScale Microarchitecture User s Manual 10 12 10 12 1 Software Debug If the oldest entry from the trace buffer is non zero then the trace buffer has either wrapped around or just filled up Once the trace buffer has been read and parsed the host software must re create the trace history from oldest trace buffer entry to latest Trying to re create the trace going backwards from the latest trace buffer entry will not work in most cases because once a branch message is encountered it may not be possible to determine the source of the branch In fill once mode the return from the debug handler to the application should generate an indirect branch message The address placed in the trace buffer will be that of the target application instruction Using this as a starting point re creating a trace going forward in time is straightforward In wrap around mode the host software uses the checkpoint registers and address bytes from indirect branch entries to re create the trace going forward The drawback is that some of the oldest entries in the trace buffer may be untraceable depending on where the earliest checkpoint or indirect branch entry is located The best case is when the oldest entry in the trace buffer set a checkpoint so the ent
69. Invalidate IC Line VA 31 5 ololofofo1o 5 0 Invalidate Mini IC vele indicates first 5 2 bit shifted in 32 31 e Data Word 7 indicates last bit shifted in Load Main IC CMD 0b010 Data Word 0 and Load Mini IC CMD 0b011 VA 31 5 efe 1 All packets are 33 bits in length Bits 2 0 of the first packet specify the function to execute For functions that require an address bits 32 6 of the first packet specify an 8 word aligned address Packet1 32 6 VA 31 5 For Load Main IC and Load Mini IC 8 additional data packets are used to specify 8 ARM instructions to be loaded into the target instruction cache Bits 31 0 of the data packets contain the data to download Bit 32 of each data packet is the value of the parity for the data in that packet BE HI N HI a N As shown in Figure 10 10 the first bit shifted in TDI is bit 0 of the first packet After each 33 bit packet the host must take the JTAG state machine into the Update DR state After the host does an Update DR and returns the JTAG state machine back to the Shift DR state the host can immediately begin shifting in the next 33 bit packet 10 13 4 Loading IC During Reset Code can be downloaded into the instruction cache through JTAG during a processor reset This feature is used during software debug to download the debug handler prior to starting an application program The downloaded handler can then intercept the
70. Mode In this last scenario the mini instruction cache does not get invalidated by reset since the processor is in Halt Mode This scenario is described in more detail in this section The last scenario described above is shown in Figure 10 12 Intel XScale Microarchitecture User s Manual n Software Debug Figure 10 12 Code Download During a Warm Reset For Debug RESET pin asserted until hold_rst signal is set Reset pin TRST RESET does not affect Mini IC Halt Mode Bit set Internal RESET hold rst keeps internal reset asserted held st clock 15 tcks after wait 2030 tcks after last update dr Reset deasserted in LDIC mode JTAG IR JTAG INSTR Y SELDCSR X LDIC SELDCSR l set hold rst signal enter LDIC mode clear hold rst signal keep Halt Mode bit set Load code into IC keep Halt Mode bit set Halt Mode As shown in Figure 10 12 reset does not invalidate the instruction cache because the processor is in Halt Mode Since the instruction cache was not invalidated it may contain valid lines The host must avoid downloading code to virtual addresses that are already valid in the instruction cache mini IC or main IC otherwise the processor will behave unpredictably There are several possible solutions that ensure code is not downloaded to a VA that already exists in the instruction cache 1 Since the mini instruction cache was not invalidated any code previously
71. Performance Monitoring 1 5 1 2 2 8 Power Management 1 5 1 2 2 9 Debug EE 1 5 1 3 Terminology and Conventions nn 1 6 1 3 1 Number Representaton ener nennen 1 6 1 3 2 Terminology and Acronvms ener nenne 1 6 2 Programming MOG ELS 2 1 2 4 ARM Architecture Compatibility nennen 2 1 2 2 ARM Architecture Implementation Options ssseessesseeeenennrtnrrenssesesrrtttntrtnnnnnsnnnnnrenre nnn 2 1 2 2 1 Big Endian versus Little Endian mem 2 1 2 222 OA 2 1 2 2 3 ARM DSP Enhanced Instruction Get 2 2 2 2 4 Ee LE EE 2 2 2 3 Extensions to ARMY Architecture 2 2 2 3 4 DSP Coprocessor 0 HE EE 2 3 2 3 1 1 Multiply With Internal Accumulate Format en ennneen 2 3 2 3 1 2 Internal Accumulator Access Format 2 6 2 9 2 New Page Attributes geesde ere ir etie aa 2 9 2 3 3 Additions to CP15 Functional 2 10 2 3 4 Event Architecture ernennen 2 11 2 3 4 1 Exception Summary seserian anaia aA EEANN 2 11 2 9 4 2 Event PO Vcc ree cette ihn 2 11 2 9 4 3 Prefetch ADOFtS cei eite tta lehnen 2 12 2 9 44 Data ADOS SEEHPERRLHERLDEHERFERERFEREEEFEFEERLOFERENFERBBERPEFDLETRFERECTEEFLOERSEREERERREHEFEFRGE 2 12 2 3 4 5 Events from Preload Instructions s nssseeeneeeeeeeeeeeerenrrnnnen rererere 2 14 2 39 46 Debug Events comisaria 2 15 3 Memory Management nike nike 3 1 3 1 ey m 3 1 3 2 Architecture Model eie I eene rael nern A MERE Vaud 3 1 3 2 1 Version 4 vs Version be 3 2 3
72. Performance Monitoring The performance monitoring unit contains a control register PMNC a clock counter CCNT and two event counters PMNO and PMN1 The format of these registers can be found in Chapter 8 Performance Monitoring along with a description on how to use the performance monitoring facility Opcode_2 and CRm must be zero Table 7 22 Accessing the Performance Monitoring Registers 7 3 2 7 16 Function CRn Register Instruction Read PMNC 0b0000 MRC p14 0 Rd cO c0 0 Write PMNC 0b0000 MCR p14 0 Rd cO c0 0 Read CCNT 0b0001 MRC p14 0 Rd c1 c0 0 Write CCNT 0b0001 MCR p14 0 Rd c1 c0 0 Read PMNO 0b0010 MRC p14 0 Rd c2 c0 0 Write PMNO 0b0010 MCR p14 0 Rd c2 c0 0 Read PMN1 0b0011 MRC p14 0 Rd c3 c0 0 Write PMN1 0b0011 MCR p14 0 Rd c3 c0 0 Registers 6 7 Clock and Power Management These registers contain functions for managing the core clock and power Power management modes are supported through register 7 Two low power modes are supported that are entered upon executing the functions listed in Table 7 25 To enter any of these modes write the appropriate data to CP14 register 7 PWRMODE Software may read this register but since software only runs during ACTIVE mode it will always read zeroes from the M field Intel XScale Microarchitecture User s Manual n Configuration Table 7 23 PWRMODE Register 7 31 30 29 28
73. Resource Early Termination Value Issue Latency Latency Latency Throughput 0 2 RdLo 2 RdHi 3 2 Rs 31 15 0x00000 1 3 3 3 0 2 RdLo 3 RdHi 4 3 UMLAL Rs 31 27 0x00 1 4 4 4 0 2 RdLo 4 RdHi 5 4 all others 1 5 5 5 0 1 RdLo 2 RdHi 3 2 Rs 31 15 0x00000 1 3 3 3 0 1 RdLo 3 RdHi 4 3 UMULL Rs 31 27 0x00 1 4 4 4 0 1 RdLo 4 RdHi 5 4 all others 1 5 5 5 a If the next instruction needs to use the result of the multiply for a shift by immediate or as Rn in a QDADD or QDSUB one extra cycle of result latency is added to the number listed Table 11 7 Multiply Implicit Accumulate Instruction Timings Rs Value Early Minimum Issue Minimum Resuit Minimum Resource Mnemame Termination Latency Latency Latency Throughput Rs 31 16 0x0000 or 1 1 1 Rs 31 16 OxFFFF MIA Rs 31 28 0x0 or 1 2 2 Rs 31 28 OxF all others 1 3 3 MIAxy N A 1 1 1 MIAPH N A 1 2 2 Table 11 8 Implicit Accumulator Access Instruction Timings Mnemonic Minimum Issue Latency Minimum Result Latency Minimum PRISE Lae Throughput MAR 2 2 2 MRA 1 RdLo 2 RdHi 3 2 a If the next instruction needs to use the result of the MRA for a shift by immediate or as Rn in a QDADD or QDSUB one extra cycle of result latency is added to the number listed 11 2 5 Saturated Arithmetic Instructions 11 6 Intel XScale Microarchitecture User s Manual Table 11 9 Saturated Data Processing Instruction Timings Performance Consideration
74. Speed Download Handshaking States oonoccoconnnncccnnnonacccccccnncannccncnnannncnnnn nana nccncnannnns 10 13 10 11TX FHandshaking etel pee eicit via euch as inedit 10 14 10 12TXRXCTRL Mnemonic Extensions nn 10 14 TOTI TEA Cid 10 15 10 14RX d cruce 10 15 10 15DEBUG Data Register Reset Values esse ene 10 23 10 16CP 14 Trace Buffer Register Summary 10 24 10 17Checkpoint Register CHKPTX ssssssssseene eene nnne enne nennen nennen nenne 10 24 10 18 TBREG Format 5 tte dile 10 25 10 19Message Byte Formats ssssssssssesseeeeeneee nennen nennen seen nenne nennen nnne nnns 10 28 10 20LDIC Cache FUNCOMS eene nen nennen enne e A 10 32 11 1 Branch Latency Penalty 2 50 ar tice ia 11 1 11 2Latency Example A sich eevee e epe dea Eee 11 3 11 3Branch Instruction Timings Those predicted by the BIER 11 3 Intel XScale Microarchitecture User s Manual xi Contents i ntel A 1 xii 11 4Branch Instruction Timings Those not predicted by the BTB 11 4 11 5Data Processing Instruction TIMINGS essen nnnm renes 11 4 11 6Multiply Instruction TIMINGS rini aeiee E EE AA A TEATE nennen nre nennen enn 11 5 11 7 Multiply Implicit Accumulate Instruction TiMINngS em 11 6 11 8Implicit Accumulator Access Instruction Timings em 11 6 11 9Saturated Data Processing Instruction TIMINGS essee mem 11 7 11 10Status Register Access Instruction Timimgs mem 11 7 11 11Load
75. Test Access Port and Boundary Scan Architecture Refer to this standard for any explanations not covered in this section This standard is more commonly referred to as JTAG an acronym for the Joint Test Action Group The JTAG interface on the application processor can be used as a hardware interface for software debugging of PXA255 systems This interface is described in Chapter 10 Software Debug The JTAG hardware and test features of the application processor are discussed in the following sections 9 1 Boundary Scan Architecture and Overview The JTAG interface on the application processor provides a means of driving and sampling the external pins of the device irrespective of the core state This feature is known as boundary scan Boundary scan permits testing of both the device s electrical connections to the circuit board and integrity of the circuit board connections between devices via linked JTAG interfaces The interface intercepts external connections within the device via a boundary scan cell and each such cell is then connected together to form a serial shift register called the boundary scan register The boundary scan test logic elements include the TAP pins TAP Controller instruction register and a set of test data registers including boundary scan register bypass register device identification register and data specific registers This is shown in Figure 9 1 Figure 9 1 Test Access Port TAP Block Diagram
76. a programmable logic device that interfaces to the Test Access Port TAP The TAP controller changes state only in response to a rising edge of TCK or power up The value of the test mode state TMS input signal at a rising edge of TCK controls the sequence of state changes The TAP controller is automatically initialized on power up In addition the TAP controller can be initialized by applying a high signal level on the TMS input for five TCK periods Behavior of the TAP controller and other test logic in each controller state is described in the following sub sections Figure 9 3 shows the state transitions that occur in the TAP controller Note that all application processor digital signals participate in the boundary scan except the PVR EN pin This prevents a scan operation from turning off power to the application processor For greater detail on the state machine and the public instructions refer to IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Document Intel XScale Microarchitecture User s Manual intel Test Figure 9 3 TAP Controller State Diagram 9 5 1 9 5 2 1 nTRST 0 TEST LOGIC RESET 0 SELECT IR SCAN CAPTURE IR p SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR 1 0 PAUSE DR EXIT2 DR UPDATE DR NOTE ALL STATE TRANSITIONS ARE BASED ON THE VALUE OF TMS Test Logic Reset State In this state test logic is
77. aces the highest priority exception based on the priorities in Table 10 4 in the MOE field Trace Buffer Mode Bit M The Trace Buffer Mode bit selects one of two trace buffer modes Wrap around mode Trace buffer fills up and wraps around until a debug exception occurs Fill once mode The trace buffer automatically generates a debug exception trace buffer full break when it becomes full Trace Buffer Enable Bit E The Trace Buffer Enable bit enables and disables the trace buffer Both DCSR e and DCSR ge must be set to enable the trace buffer The processor automatically clears this bit to disable the trace buffer when a debug exception occurs For more details on the trace buffer refer to Section 10 Trace Buffer Debug Exceptions A debug exception causes the processor to re direct execution to a debug event handling routine The Intel XScale core debug architecture defines the following debug exceptions 1 instruction breakpoint data breakpoint software breakpoint 2 3 4 external debug break 5 exception vector trap 6 trace buffer full break Intel XScale Microarchitecture User s Manual 10 5 Software Debug I ntel i When a debug exception occurs the processor s actions depend on whether the debug unit is configured for Halt mode or Monitor mode Table 10 4 shows the priority of debug exceptions relative to other processor exceptions Table 10 4 Event Priority 10 4 1 10 6
78. ache cleaning Memory regions that are private to a particular processor should use the write back policy Intel XScale Microarchitecture User s Manual Intel A 4 2 3 A 4 2 4 A 4 2 5 Optimization Guide Read Allocate and Read write Allocate Memory Regions Most of the regular data and the stack for your application should be allocated to a read write allocate region It is expected that you will be writing and reading from them often Data that is write only or data that is written to and subsequently not used for a long time should be placed in a read allocate region Under the read allocate policy if a cache write miss occurs a new cache line will not be allocated and hence will not evict critical data from the Data cache Creating On chip RAM Part of the Data cache can be converted into fast on chip RAM Access to objects in the on chip RAM will not incur cache miss penalties thereby reducing the number of processor stalls Application performance can be improved by converting a part of the cache into on chip RAM and allocating frequently used variables to it Due to the Intel XScale core round robin replacement policy all data will eventually be evicted Therefore to prevent critical or frequently used data from being evicted it should be allocated to on chip RAM The following variables are good candidates for allocating to the on chip RAM Frequently used global data used for storing context for context swi
79. address to specify which dynamic function to execute Since the dynamic function is being downloaded into the main instruction cache the downloaded code may overwrite valid application code and conversely application code may overwrite the dynamic function The dynamic function is only guaranteed to be in the cache from the time it is downloaded to the time the debug handler returns to the application or the debugger overwrites it 3 External memory Dynamic functions can also we downloaded to external memory or they may already exist there The debugger can download to external memory using the write memory commands Then the debugger executes the dynamic command using the address of the function to identify which function to execute This method has many of the same advantages as downloading into the main instruction cache Depending on the memory system this method could be much slower than downloading directly into the instruction cache Another problem is the application may write to the memory where the function 1s downloaded If it can be guaranteed by software design that the application does not modify the downloaded dynamic function the debug handler can save the time it takes to re download the code Otherwise to ensure the application does not corrupt the dynamic functions the debugger should re download any dynamic functions it uses For all three methods the downloaded code executes in the context of the debug handler The
80. affected by the El field of DBCON The mask is used only when DBRO is enabled When DBRI is programmed as a second data address breakpoint it functions independently of DBRO In this case the DBCON E1 controls DBR1 A data breakpoint is triggered if the memory access matches the access type and the address of any byte within the memory access matches the address in DBRx For example LDR triggers a breakpoint if DBCON E0 is 0b10 or 0b11 and the address of any of the 4 bytes accessed by the load matches the address in DBRO The processor does not trigger data breakpoints for the PLD instruction or any CP15 register 7 8 9 or 10 functions Any other type of memory access can trigger a data breakpoint For data breakpoint purposes the SWP and SWPB instructions are treated as stores they will not cause a data breakpoint if the breakpoint is set up to break on loads only and an address match occurs On unaligned memory accesses breakpoint address comparison is done on a word aligned address aligned down to word boundary 10 10 Intel XScale Microarchitecture User s Manual 10 6 10 7 Software Debug When a memory access triggers a data breakpoint the breakpoint is reported after the access is issued The memory access will not be aborted by the processor The actual timing of when the access completes with respect to the start of the debug handler depends on the memory configuration On a data breakpoint the processor generates
81. ale Microarchitecture User s Manual 10 1 Software Debug I ntel a 10 1 2 10 2 The debug handler can be downloaded and locked directly into the instruction cache through the JTAG interface so external memory is not required to contain debug handler code Monitor Mode In monitor mode debug exceptions are handled like ARM prefetch aborts or ARM data aborts depending on the cause of the exception When a debug exception occurs the processor switches to abort mode and branches to a debug handler using the pre fetch abort vector or data abort vector The debugger then communicates with the debug handler to access processor state or memory contents Debug Registers CP15 registers are accessible using MRC and MCR CRn and CRm specify the register to access The opcode 1 and opcode 2 fields are not used and must be set to 0 Software access to all debug registers must be done in privileged mode User mode access will generate an undefined instruction exception Specifying registers which do not exist has unpredictable results Table 10 1 Coprocessor 15 Debug Registers Register name CRn CRm Instruction breakpoint register 0 IBCRO 14 8 Instruction breakpoint register 1 IBCR1 14 9 Data breakpoint register 0 DBRO 14 0 Data breakpoint register 1 DBR1 14 3 Data breakpoint control register DBCON 14 4 CP14 registers are accessible using MRC MCR LDC and STC CDP to any CP14 registers will cau
82. and Overview ssssssssseeenene eene 9 1 9 24 dal 9 3 Intel XScale Microarchitecture User s Manual V a Contents ntel 9 3 Instruction Register crisol iaa 9 3 9 3 1 Boundary Scan Instruction Gei 9 3 9 4 TestData Registro oe ee edt ee preteriti Eeer Ee 9 5 9 4 4 Bypass E LEE 9 5 9 4 2 Boundary Scan Register 9 6 9 4 3 Device Identification ID Code Register see nenn 9 8 9 4 4 Data Specific Registers orses ninnaa inae aan AA EEEa AEN ETEA AERE 9 8 9 5 ITAP Controller anreisen meinen Deel en Ee aenea du 9 8 9 571 Test bodie Reset States oe tete et tee teet et eter et be Aue Gs 9 9 9 5 2 Run Test Idle Giate eene rne nnn 9 10 9 5 3 Select DR Scan Giate nn 9 10 9 5 4 Capture DR State e ae R r ae a aaea e aeaaaee 9 10 950 Shift DR Stato idee lt 9 10 9 5 6 ExitT DR State n eee enin ete iios 9 11 9 5 7 Pause DRistate zac eee ended echa due melted 9 11 9 5 8 EXI DR States eire een LEE ds ORE 9 11 9 5 9 Update DR State etr a anal re ds 9 11 9 5 10 SelectlR Scan State esine eet ien ADU SENI RR davis E LINE DER ECL LERRA 9 12 9 541 Capture IR State rote dee t metre 9 12 9 5712 Shife IR State e eese a cies Macaca sot iti men to age ct dee 9 12 9 5 13 Exit Rate een llei drid 9 12 9 5 14 Pause IR Mate iii Eh 9 12 9 5 15 TEE 9 13 90 16 UpdatelR ate in a e ee 9 13 10 Software Deb g ierit ii dd pd d edad ea dd d 10 1 10517 Introductionis a
83. ant should be optimized to make use of the shift operation whenever possible Dividing r0 containing a signed value by an integer constant that can be represented as 2n mov rl r0 ASR 31 add rO rO rl LSR 32 n mov r0 r0 ASR in The add instruction would stall for 1 cycle The stall can be prevented by filling in another instruction before add Effective Use of Addressing Modes The Intel XScale core provides a variety of addressing modes that make indexing an array of objects highly efficient For a detailed description of these addressing modes please refer to the ARM Architecture Reference Manual The following code samples illustrate how various kinds of array operations can be optimized to make use of these addressing modes Set the contents of the word pointed to by r0 to the value contained in rl and make r0 point to the next word str r1 r01 4 Increment the contents of r0 to make it point to the next word and set the contents of the word pointed to the value contained In el str rl rO 4 Set the contents of the word pointed to by r0 to the value contained in r1 and make r0 point to the previous word str rl rO 4 Decrement the contents of r0 to make it point to the previous word and set the contents of the word pointed to the value contained in r1 str rl rO 4 Cache and Prefetch Optimizations This chapter considers how to use the various cache memories in all their modes an
84. apped caches on the Intel XScale core would not require invalidating on a process switch Table 7 17 Accessing Process ID 7 12 Function opcode_2 CRm Instruction Read Process ID Register 0b000 0b0000 MRC p15 0 Rd c13 c0 0 Write Process ID Register 0b000 0b0000 MCR p15 0 Rd c13 c0 0 Intel XScale Microarchitecture User s Manual intel Configuration Table 7 18 Process ID Register 7 2 11 1 7 2 12 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 0 RRE reset value 0x0000 0000 Bits Access Description Process ID This field is used for remapping the virtual 3125 Read Write address when bits 31 25 of the virtual address are zero Reserved Must be programmed to zero for future 24 0 Read as Zero Write as Zero b compatibility The PID Register Affect On Addresses All addresses generated and used by User Mode code are eligible for being translated using the PID register Privileged code however must be aware of certain special cases in which address generation does not follow the usual flow The PID register is not used to remap the virtual address when accessing the Branch Target Buffer BTB Debug software reading the BTB needs to recognize addresses as MVAs Any write to the PID register invalidates the BTB This prevents any virtual addresses after the PID has changed from matching the incorrect
85. are Debug I ntel a 10 10 2 1 10 10 2 2 10 10 2 3 10 18 DBG HLD_RST The debugger uses DBG HLD_RST when loading code into the instruction cache during a processor reset Details about loading code into the instruction cache are in Section 10 Downloading Code into the Instruction Cache The debugger must set DBG HLD_RST before or during assertion of the reset pin Once DBGHLD RST is set the reset pin can be de asserted and the processor will internally remain in reset The debugger can then load debug handler code into the instruction cache before the processor begins executing any code Once the code download is complete the debugger must clear DBG HLD RST This takes the processor out of reset and execution begins at the reset vector A debugger sets DBG HLD RST in one of 2 ways Either by taking the JTAG state machine into the Capture DR state which automatically loads DBG SR I with 1 then the Exit2 state followed by the Update Dr state This sets the DBG HLD RST clear DBG BRK and leave the DCSR unchanged the DCSR bits captured in DBG SR 34 3 are written back to the DCSR on the Update DR Refer to Figure 9 3 TAP Controller State Diagram on page 9 9 Alternatively a 1 can be scanned into DBG_SR 1 with the appropriate value scanned in for the DCSR and DBG BRK DBG HLD RST can only be cleared by scanning in a 0 to DBG_SR 1 and scanning in the appropriate values for the DCSR and DBG
86. ata registers that the current instruction selects but does not place in the serial path retain their previous value during this state The instruction does not change while the TAP controller is in this state If TMS is high on the rising edge of TCK the controller enters the Exit1 DR state If TMS is low on the rising edge of TCK the controller remains in the Shift DR state Exit1 DR State This is a temporary controller state When the TAP controller is in the Exit1 DR state and TMS is held high on the rising edge of TCK the controller enters the Update DR state which terminates the scanning process If TMS is held low on the rising edge of TCK the controller enters the Pause DR state The instruction does not change while the TAP controller is in this state All test data registers selected by the current instruction retain their previous value during this state Intel XScale Microarchitecture User s Manual Intel 9 5 7 9 5 8 9 5 9 9 5 10 9 5 11 Test Pause DR State The Pause DR state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state The controller remains in this state as long as TMS is low When TMS goes high on the rising edge of TCK the controller moves to the Exit
87. ath between TDI and TDO to allow the device to be bypassed during boundary scan testing This allows for more rapid movement of test data to and from other components on a board that are required to perform JTAG test operations When the bypass highz or clamp instruction is the current instruction in the instruction register serial data is transferred from TDI to TDO in the Shift DR state with a delay of one TCK cycle There is no parallel output from the bypass register A logic 0 is loaded from the parallel input of the bypass register in the Capture DR state Boundary Scan Register The boundary scan register consists of a serially connected set of cells around the periphery of the device at the interface between the core logic and the system input output pads This register can be used to isolate the pins from the core logic and then drive or monitor the system pins The connected boundary scan cells make up a shift register The boundary scan register is selected as the register to be connected between TDI and TDO only during the sample preload and extest instructions Values in the boundary scan register are used but are not changed during the clamp instruction In the normal system mode of operation straight through connections between the core logic and pins are maintained and normal system operation is unaffected Such is the case when the sample preload instruction is selected In test mode when extest is the currently sele
88. cache and a trace buffer Testability amp hardwar 8 3 r 8 le a028 3 10 e r 10 e 7 0 11 9 27 5 2ma 0 000007 Tc 1 Tf9 2 3 2me 6 4 2 21 Intel XScale Microarchitecture User s Manual 1 5 Configuration n 7 2 4 Register 3 Domain Access Control Register Table 7 9 Domain Access Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 for Jona oo re om foro ow or oe Too Tow v on Tor To reset value unpredictable Bits Access Description Access permissions for all 16 domains The meaning 31 0 Read Write of each field can be found in the ARM Architecture Reference Manual 7 2 5 Register 5 Fault Status Register The Fault Status Register FSR indicates which fault has occurred which could be either a prefetch abort or a data abort Bit 10 extends the encoding of the status field for prefetch aborts and data aborts The definition of the extended status field is found in Section 2 3 4 Event Architecture on page 2 11 Bit 9 indicates that a debug event occurred and the exact source of the event is found in the debug control and status register CP14 register 10 When bit 9 is set the domain and extended status field are undefined Upon entry into the prefetch abort or data abort handler hardware will update this register with the source of the exception Software is not required to clear these fields Table 7 10 Fault Status Register 31
89. cation processor and what the memory access latency is for Data Cache miss requests to external memory If the Intel amp XScaleTM core memory access latency Intel XScale Microarchitecture User s Manual 8 5 5 Performance Monitoring is high possibly due to starvation these Data Cache buffers will become full This performance monitoring mode is provided to see if the Intel XScale core is being starved of the bus external to the Intel XScale core PMNO accumulates the number of clock cycles the processor is being stalled due to this condition and PMNI monitors the number of times this condition occurs Statistics derived from these two events The average number of cycles the processor stalled on a data cache access that may overflow the data cache buffers This is calculated by dividing PMNO by PMNI This statistic lets you know if the duration event cycles are due to many requests or are attributed to just a few requests If the average is high then the Intel XScale core may be starved from accessing the application processor internal bus due to other bus activity e g companion chip bus cycles The percentage of total execution cycles the processor stalled because a Data Cache request buffer was not available This 1s calculated by dividing PMNO by CCNT which was used to measure total execution time Stall Writeback Statistics Mode When an instruction requires the result of a previous instruction and that r
90. ceeeeeeneneeeenentnes A 18 A 4 4 1 Prefetch Distances een A 18 A 4 4 2 Prefetch Loop Gchedulmg A 18 A 4 4 3 Compute vs Data Bus Bound rnnr nn A 19 A 4 4 4 Low Number of Iterations e A 19 A 4 4 5 Bandwidth Limitations eee eeeeeeeeeeeaecaeeeeeeeeeteeeeeees A 19 A 4 4 6 Cache Memory Consideratons A 20 ASAT Cache Blocking eb nip ca cease eua eum bres A 21 A 4 4 8 Prefetch Unrolling esiseinas arniarna nn A 21 A449 Pointer Prefetch sid eee tie aan A 22 A 4 4 10 Loop Interchange mmm enn A 23 A 4 4 11 Loop FUSION iiir net nn deat a renda A 23 A 4 4 12 Prefetch to Reduce Register Pressure eeessseeereeerrerrerrerseeen A 23 AS Instruction Scheduling i isi did dedicado reads oda A 24 A 5 1 Scheduling Loads 0oooocconncoccccnnicocccononaconcncnnnno nn nan cnnno nennen nennen nenne A 24 A 5 1 1 Scheduling Load and Store Double LDRD STRD A 26 A 5 1 2 Scheduling Load and Store Multiple LDM STM A 27 A 5 2 Scheduling Data Processing Instructions eeeeeeeeeeeeeeeeeeeeeerreseeerrresrerrrssseee ns A 28 A 5 3 Scheduling Multiply Instructions men A 28 A 5 4 Scheduling SWP and SWPB Instructions n A 29 A 5 5 Scheduling the MRA and MAR Instructions MRRCMCHR sess A 29 A 5 6 Scheduling the MIA and MIAPH Instructions eeeeeeeeeeeeeeeeeeeeeneeeerrrnnneeen A 30 A 5 7 Scheduling MRS and MSR Instruchons nn A 30 A 5 8 Scheduling Coprocessor Instructions
91. ch of these requests loads 32 bytes at a time due to the instruction fetch buffers even when the memory page is marked as uncached Intel XScale Microarchitecture User s Manual a Performance Monitoring ntel A 8 5 2 8 5 3 8 5 4 Statistics derived from these two events Instruction cache miss rate This is derived by dividing PMN1 by PMNO The average number of cycles it took to execute an instruction or commonly referred to as cycles per instruction CPI CPI can be derived by dividing CCNT by PMNO where CCNT was used to measure total execution time Data Cache Efficiency Mode PMNO totals the number of data cache accesses which includes cacheable and non cacheable accesses mini data cache access and accesses made to locations configured as data RAM Note that STM and LDM will each count as several accesses to the data cache depending on the number of registers specified in the register list LDRD will register two accesses PMNI counts the number of data cache and mini data cache misses Cache operations do not contribute to this count See Section 7 2 7 for a description of these operations The common statistic derived from these two events is Data cache miss rate This is derived by dividing PMN1 by PMNO Instruction Fetch Latency Mode PMNO accumulates the number of cycles when the instruction cache is not able to deliver an instruction to the Intel XScale core due to an instruction cache miss
92. ciative cache There are 32 sets each containing two ways each way contains 8 words The cache uses the round robin replacement policy for lines overloaded from the debugger Normal application code is never cached in the mini instruction cache on an instruction fetch The only way to get code into the mini instruction cache is through the JTAG LDIC function Code downloaded into the mini instruction cache is essentially locked it cannot be overwritten by application code running on the Intel amp XScaleTM core It is not locked against code downloaded through the JTAG LDIC functions Application code can invalidate a line in the mini instruction cache using a CP15 Invalidate IC line function to an address that hits in the mini instruction cache However a CP15 global invalidate IC function does not affect the mini instruction cache The mini instruction cache can be globally invalidated through JTAG by the LDIC Invalidate IC function or by a processor reset when the processor is not in HALT or LDIC mode A single line in the mini instruction cache can be invalidated through JTAG by the LDIC Invalidate IC line function The mini instruction cache is virtually addressed and addresses may be remapped by the PID However since the debug handler executes in Special Debug State address translation and PID remapping are turned off For application code accesses to the mini instruction cache use the normal address translation and PID mechanisms
93. cludes instructions that were executed and conditional instructions that were not executed due to the condition of the instruction not matching the CC flags In the case of back to back branches the word count would be 0 indicating that no instructions executed after the last branch and before the current one A rollover message is used to keep track of long traces of code that do not have control flow changes The rollover message means that 16 instructions have executed since the last message byte was written to the trace buffer If the incremental counter reaches its maximum value of 15 a rollover message is written to the trace buffer following the next instruction which will be the 16th instruction to execute This is shown in Example 10 1 The count in the rollover message is 0b1111 indicating that 15 instructions have executed after the last branch and before the current non branch instruction that caused the rollover message Example 10 1 Rollover Messages Examples 10 12 1 3 count 5 BL label1 branch message placed in trace buffer after branch executes count 0 7 count 060101 MOV count 1 MOV count 2 MOV count 14 MOV count 15 MOV rollover message placed in trace buffer after 16th instruction executes count 0 count 0b1111 If the 16th instruction is a branch direct or indirect the appropriate branch message is placed in the trace buffer instead of the roll over message The incremen
94. ct the outcome of branch type instructions It provides storage for the target address of branch type instructions and predicts the next address to present to the instruction cache when the current instruction address is that of a branch The BTB holds 128 entries Refer to Chapter 5 Branch Target Buffer for more information Data Cache The Intel XScale core implements a 32 Kbyte 32 way set associative data cache and a 2 Kbyte 2 way set associative mini data cache Each cache has a line size of 32 bytes supporting write through or write back caching The data mini data cache is controlled by page attributes defined in the MMU Architecture and by coprocessor 15 Refer to Chapter 6 Data Cache for more information The Intel XScale core allows applications to re configure a portion of the data cache as data RAM Software may place special tables or frequently used variables in this RAM Refer to Section 6 4 Re configuring the Data Cache as Data RAM on page 6 10 for more information Fill Buffer amp Write Buffer The Fill Buffer and Write Buffer enable the loading and storing of data to memory beyond the Intel XScale core The Write Buffer carries all write traffic beyond the core allowing data coalescing when both globally enabled and when associated with the appropriate memory page types The Fill buffer assists the loading of data from memory which along with an associated Pend Buffer allows multiple memory
95. cted instruction values can be applied to the output pins independently of the actual values on the input pins and core logic outputs On the application processor all of the boundary scan cells include update registers with the exception of the nRESET OUT and PWR EN pins In the case of the nRESET OUT and PWR EN pins the contents of the scan latches are not placed on the pins This is to prevent a scan operation from disabling power to the device and or resetting external components The following pins are not part of the boundary scan shift register PEXTAL PXTAL TEXTAL Intel XScale Microarchitecture User s Manual 9 5 Test TXTAL XM XP YM e YP REF The five TAP Controller pins Also JTAG operations cannot be performed in sleep i e the nBATT FAULT and nVDD FAULT pins must always be driven high during JTAG operation The extest guard values should be clocked into the boundary scan register using the sample preload instruction before the extest instruction is selected to ensure that known data is applied to the core logic during the test These guard values should also be used when new EXTEST vectors are clocked into the boundary scan register The values stored in the boundary scan register after power up are not defined Similarly the values previously clocked into the boundary scan register are not guaranteed to be maintained across a JTAG reset from forcing nTRST low or entering the Test Logic Re
96. d or cover vast amounts of data space Addressing these types of data spaces from the Data cache would corrupt much if not all of the Data cache by evicting valuable data Eviction of valuable data will reduce performance Placing this data instead in a Mini data cache memory region would prevent Data cache corruption while providing the benefits of cached accesses A prime example of using the mini data cache would be for caching the procedure call stack The stack can be allocated to the mini data cache so that it s use does not trash the main data cache This would separate local variables from global data Intel XScale Microarchitecture User s Manual A 15 Optimization Guide ntel A 4 2 6 A 16 Following are examples of data that could be assigned to the mini data cache The stack space of a frequently occurring interrupt the stack is used only during the duration of the interrupt which is usually very small Video buffers these are usual large and would otherwise more than occupy the main cache allowing for little or no reuse of cached data Streaming data such as Music or Video files that will be read sequentially with little data reuse Over use of the Mini Data cache will thrash the cache This is easy to do because the Mini Data cache only has two ways per set For example a loop which uses a simple statement such as for i20 i IMAX i Afi Bli Clil Where A B and C reside in a min
97. d then examines when and how to use prefetch to improve execution efficiencies Intel XScale Microarchitecture User s Manual Intel A 4 1 A 4 1 1 A 4 1 2 A 4 1 3 A 4 1 4 Optimization Guide Instruction Cache The Intel XScale core has separate instruction and data caches Only fetched instructions are held in the instruction cache even though both data and instructions may reside within the same memory space with each other Functionally the instruction cache is either enabled or disabled There is no performance benefit in not using the instruction cache The exception is that code which locks code into the instruction cache must itself execute from non cached memory Cache Miss Cost The Intel XScale core performance is highly dependent on reducing the cache miss rate Note that this cache miss penalty becomes significant when the core is running much faster than external memory Executing non cached instructions severely curtails the processor s performance in this case and it is very important to do everything possible to minimize cache misses Round Robin Replacement Cache Policy Both the data and the instruction caches use a round robin replacement policy to evict a cache line The simple consequence of this is that at sometime every line will be evicted assuming a non trivial program The less obvious consequence is that predicting when and over which cache lines evictions take place is very diff
98. data address breakpoint registers are 32 bit registers The instruction breakpoint causes a break before execution of the target instruction The data breakpoint causes a break after the memory access has been issued In this section Modified Virtual Address MVA refers to the virtual address ORed with the PID Refer to Section 7 2 11 Register 13 Process ID on page 7 12 for more details on the PID The processor does not OR the PID with the specified breakpoint address prior to doing address comparison This must be done by the programmer and written to the breakpoint register as the MVA This applies to data and instruction breakpoints Intel XScale Microarchitecture User s Manual n Software Debug 10 5 1 Instruction Breakpoints The Debug architecture defines two instruction breakpoint registers IBCRO and IBCR1 The format of these registers is shown in Table 10 5 Instruction Breakpoint Address and Control Register IBCRx In ARM mode the upper 30 bits contain a word aligned MVA to break on In Thumb mode the upper 31 bits contain a half word aligned MVA to break on In both modes bit 0 enables and disables that instruction breakpoint register Enabling instruction breakpoints while debug is globally disabled DCSR GE 0 will result in unpredictable behavior Table 10 5 Instruction Breakpoint Address and Control Register IBCRx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 21 0 IB
99. data is evicted from the cache then only the data from the first prefetch is lost Intel XScale Microarchitecture User s Manual In A 4 4 10 A 4 4 11 A 4 4 12 Optimization Guide Loop Interchange As mentioned earlier the sequence in which data is accessed affects cache thrashing Usually it is best to access data in a contiguous spatially address range However arrays of data may have been laid out such that indexed elements are not physically next to each other Consider the following C code which places array elements in row major order for j 0 j NMAX j for i 0 i lt NMAX i prefetch Ali 1 j sum Ali j In the above example A i j and A i 1 j are not sequentially next to each other This situation causes an increase in bus traffic when prefetching loop data In some cases where the loop mathematics are unaffected the problem can be resolved by induction variable interchange The above example becomes for i 0 i NMAX i for j 0 j NMAX j prefetch A i j 1 sum Alil j Loop Fusion Loop fusion is a process of combining multiple loops which reuse the same data into one loop The advantage of this is that the reused data is immediately accessible from the data cache Consider the following example for i 0 i lt NMAX i prefetch A i 1 b i 1 eli 1 Afi bli clil for i 0 i lt NMAX i prefetch D i 1 c i 1
100. de intel ii A 2 1 A 2 1 1 A 2 1 2 General Pipeline Characteristics While the Intel XScale core pipeline is scalar and single issue instructions may occupy all three pipelines at once Out of order completion is possible The following sections discuss general pipeline characteristics Number of Pipeline Stages The Intel XScale core has a longer pipeline 7 stages versus 5 stages for StrongARM which operates at a much higher frequency than its predecessors do This allows for greater overall performance The longer Intel XScale core pipeline has several negative consequences however Larger branch misprediction penalty 4 cycles in the Intel XScale core instead of 1 in StrongA RM Architecture This is mitigated by dynamic branch prediction Larger load use delay LUD LUDs arise from load use dependencies A load use dependency gives rise to a LUD if the result of the load instruction cannot be made available by the pipeline in due time for the subsequent instruction An optimizing compiler should find independent instructions to fill the slot following the load Certain instructions incur a few extra cycles of delay on the Intel XScale core as compared to StrongARM processors LDM STM Decode and register file lookups are spread out over 2 cycles in the Intel XScale core instead of 1 cycle in predecessors Intel amp XScale Core Pipeline Organization The Intel XScale cor
101. dictable behavior Dynamic Debug Handler On the Intel XScale core the debug handler and override vector tables may reside in the 2 KB mini instruction cache separate from the main instruction cache A static Debug Handler is downloaded during reset This is the base handler code necessary to do common operations such as handler entry exit parse commands from the debugger read write ARM registers read write memory etc Some functions may require large amounts of code or may not be used very often As long as there is space in the mini instruction cache these functions can be downloaded as part of the static Debug Handler However if space is limited the debug handler also has a dynamic capability that allows a function to be downloaded when it is needed There are three methods for implementing a dynamic debug handler using the mini instruction cache main instruction cache or external memory Each method has limitations and advantages Section 10 Dynamically Loading IC After Reset describes how to dynamically load the mini or main instruction cache 1 using the Mini IC The static debug handler can support a command which can have functionality dynamically mapped to it This dynamic command does not have any specific functionality associated with it until the debugger downloads a function into the mini instruction cache When the debugger sends the dynamic command to the handler new functionality can be downloaded or
102. dler reads the previous data out The handshaking is described in Section 10 RX Register Ready Bit RR Intel XScale Microarchitecture User s Manual 10 15 Software Debug I ntel ii 10 10 10 10 1 10 16 Debug JTAG Access There are four JTAG instructions used by the debugger during software debug LDIC SELDCSR DBGTX and DBGRX LDIC is described in Section 10 Downloading Code into the Instruction Cache The other three JTAG instructions are described in this section SELDCSR DBGTX and DBGRX use a common 36 bit shift register DBG SR New data is shifted in and captured data out through the DBG SR In the UPDATE DR state the new data is shifted into the appropriate data register Details of the JTAG state machine can be found in Section 9 Test SELDCSR JTAG Command The SELDCSR JTAG instruction selects the DCSR JTAG data register The JTAG opcode is 01001 When the SELDCSR JTAG instruction is in the JTAG instruction register the debugger can directly access the Debug Control and Status Register DCSR The debugger can only modify certain bits through JTAG but can read the entire register The SELDCSR instruction also allows the debugger to generate an external debug break Intel XScale Microarchitecture User s Manual ntel Software Debug 10 10 2 SELDCSR JTAG Register Placing the SELDCSR JTAG instruction in the JTAG IR selects the DCSR JTAG Data register Figure 10 1
103. dynamic function or the lines where it is downloaded are invalidated 2 Using the Main IC The steps for downloading dynamic functions into the main instruction cache is similar to downloading into the mini instruction cache However using the main instruction cache has its advantages Using the main instruction cache eliminates the problem of inadvertently overwriting static Debug Handler code by writing to the wrong way of a set since the main and mini instruction caches are separate The debug handler code does not need to be specially mapped out to avoid Intel XScale Microarchitecture User s Manual 10 43 Software Debug j ntel e 10 14 2 4 10 44 this problem Also space for dynamic functions does not need to be allocated in the mini instruction cache and dynamic functions are not limited to the size allocated The dynamic function can actually be downloaded anywhere in the address space The debugger specifies the location of the dynamic function by writing the address to RX when it signals to the handler to continue The debug handler then does a branch and link to that address If the dynamic function is already downloaded in the main instruction cache the debugger immediately downloads the address signalling the handler to continue The static Debug Handler only needs to support one dynamic function command Multiple dynamic functions can be downloaded to different addresses and the debugger uses the function s
104. e available for processing on subsequent loops thus minimizing cache misses and reducing bus traffic As an example of cache blocking consider the following code for i 0 i lt 10000 i for j 0 j 10000 j for k 0 k lt 10000 k C j k A i k B j i The variable A 1 k is completely reused However accessing C j k in the j and k loops can displace A i k from the cache Using blocking the code becomes for i 0 i lt 10000 i for j1 0 j 100 j for k1 0 k lt 100 k for j2 0 j lt 100 j for k2 0 k lt 100 k ji 100 j2 kl 100 k2 j k A i k B j i Prefetch Unrolling When iterating through a loop data transfer latency can be hidden by prefetching ahead one or more iterations The solution incurs an unwanted side affect that the final interactions of a loop loads useless data into the cache polluting the cache increasing bus traffic and possibly evicting valuable temporal data This problem can be resolved by prefetch unrolling For example consider for i 0 i NMAX i prefetch datali 2 sum data i Intel XScale Microarchitecture User s Manual A 21 Optimization Guide ntel A 4 4 9 A 22 The last two iterations will prefetch superfluous data The problem can be avoid by unrolling the end of the loop for i 0 i lt NMAX 2 i prefetch data i 2 sum datalil sum data NMAX 2 sum data
105. e interrupt occurs will enable longer durations of performance monitoring This intrudes upon program execution but is typically negligible comparing the ISR execution time in the order of tens of cycles to the 2 cycles it takes to generate an overflow interrupt 8 4 Performance Monitor Control Register PMNC The performance monitor control register PMNC is a coprocessor register that controls which events PMNO and PMNI will monitor 8 2 Intel XScale Microarchitecture User s Manual n Performance Monitoring detects which counter overflowed enables disables interrupt reporting resets all counters to zero and enables the entire mechanism Table 8 3 shows the format of the PMNC register Table 8 3 Performance Monitor Control Register CP14 register 0 Sheet 1 of 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 54 3 2 1 LLLI seem onen 71 ma D mm ler reset value E and inten are 0 others unpredictable Bits Access Description 31 28 Read unpredictable Write as 0 Reserved Event Count1 identifies the source of events that 27 20 Read Write PMN1 counts See Table 8 4 for a description of the values this field may contain Event Count identifies the source of events that 19 12 Read Write PMNO counts See Table 8 4 for a description of the values this field may contain 11 Read unpredictable Write as 0 Reserved Overflow Interrupt Flag identifi
106. e IMMU is disabled In halt mode since the debug handler would typically be downloaded directly into the instruction cache it would not be appropriate to do TLB accesses or translation walks since there may not be any external memory or if there is the translation table or TLB may not contain a valid mapping for the debug handler code To avoid these problems the processor internally disables the IMMU during SDS The PID is disabled for instruction fetches This prevents fetches of the debug handler code from being remapped to a different address than where the code was downloaded The SDS remains in effect regardless of the processor mode This allows the debug handler to switch to other modes maintaining SDS functionality Entering user mode will cause unpredictable behavior The processor exits SDS following a CPSR restore operation When exiting the debug handler should use subs pc Ir 4 This restores CPSR turns off all of SDS functionality and branches to the target instruction Monitor Mode In monitor mode the processor handles debug exceptions like normal ARM exceptions If debug functionality is enabled DCSR 31 1 and the processor is in Monitor mode debug exceptions cause either a data abort or a pre fetch abort The following debug exceptions cause data aborts data breakpoint external debug break trace buffer full break 1 When the vector table is relocated CP15 Control Register 13 1 the deb
107. e User s Manual j ntel 5 Contents 10 7 5 Conditional Execution Using TSRSCTRL emen 10 14 10 8 Transmit Register A EAR 10 15 10 9 Receive Register RX uri Taaa AE EE eene et ntn a inn nen nannten nas 10 15 10 10 Debug JTAG ACCESS ea or ia de IRE IRR s 10 16 10 10 1 SELDCSR JTAG Commande 10 16 10 10 2 SELDCSR JTAG Register AAA 10 17 10 10 2 1 DBO HED ROT aa 2 2 2 2 e nic 10 18 10 10 22 DRG BRR 2 2 2 UR ir ri 10 18 10 10 2 3 DBG DGSR 2 2 2 0 et ei eek ragen 10 18 10 10 3 DBGTX JTAG Commande 10 19 10 10 4 DBGTX JTAG Register 10 19 10 10 5 DBGRX JTAG Commande 10 20 10 10 6 DBGRX JTAG Register z rrise inania EE E E nnne nnne snnt nnns 10 20 10 10 6 1 RX Write Loge iiit eee Po i ea ee 10 21 10 10 6 2 DBGRX Data Register 10 21 10 10 6 3 DBGi RR ac a Het ara 10 22 10 10 6 4 DB Mini doeet eene din e et petes 10 22 10 10 6 5 DBG RX iii as ann dd nd 10 22 19 106 RER RTE 10 23 10 10 6 7 DBG ELUSH iii ere aa ie 10 23 10 10 7 Debug JTAG Data Register Reset Values 10 23 10 11 Trace Buffer eei retenti eee 10 23 10 11 1 Trace Buffer CP Registers sse 10 23 10 11 1 1 Checkpoint Regisiers nn 10 24 10 11 1 2 Trace Buffer Register TBREOG nos 10 25 10 11 2 Trace Buffer UsagE soseen i a a aada seats nnns a asas nn 10 25 10 12 Trace Buffer EMOS oiite 22 tddi Ee re tate ene iret 10 27 10 12 1 Message Byte nun nn ee nido dde ndn dd daa ade ea dd nd 10 27 10 12 1 1 Exception Message Byte ssssssse e
108. e a te b uta 10 1 10 1 1 Halt Mode reed ee ex qu em ER 10 1 10 1 2 Monitor M Ode n multi dee lad ettet te te ERE tienes 10 2 10 27 Debug Registers nerea Pe A rs 10 2 10 3 Debug Control and Status Register DCSR sse 10 3 10 3 1 Global Enable Bit GE esses nennen etre nennen nnns 10 4 10 3 2 Halt Mode Bit FH au e nte dee einen Niet 10 4 10 3 3 Vector Trap Bits TE TLITDIATSGSTUTRI meme 10 4 10 34 Sticky Abort Bit SA ari de 10 5 10 3 5 Method of Entry Bits MOE nemen nnns 10 5 10 3 6 Trace Buffer Mode Bit MI 10 5 10 3 7 Trace Buffer Enable DIE 10 5 10 4 DEBUG EXCEPTIONS S aii etre re tct rte eene er e deer dd Eats 10 5 10 4 Halt Mode ne han RR ERE Ore 10 6 10 4 2 Monitor Mode 1 2 nalen stellte 10 7 10 5 HW Breakpoint Resources s ssssesseeesnnertnnsrnsstessttntttnnttnsttestttttnntnn nnan nntertenrtnn nennen 10 8 10 5 1 Instruction Breakpoints soie a a a a a a a 10 9 10 5 2 Data Breakpoints a ae aa aa a a a aAa a rtr renes a Enara 10 9 10 6 Software Breakp lnts 4 2 4 pei date ies Ee cesis Here Cds iei ica 10 11 10 7 Transmit Receive Control Register TXRXCTRL sssssseeeenee eene 10 11 10 7 1 RX Register Ready Bit RRJ aeree een enn 10 12 10 7 2 Overflow Flag OV Han sun ee 10 13 10 7 3 Download Flag D tenter e nre tr Hebe ANEN 10 13 10 7 4 TX Register Ready Bit TR enne 10 14 vi Intel XScale Microarchitectur
109. e debug there must be a minimal debug handler stub responsible for doing the handshaking with the host resident in the instruction cache This debug handler stub can be downloaded into the instruction cache during processor reset using the method described in Section 10 13 4 Section 10 Dynamic Code Download Synchronization describes the details for implementing the handshaking in the debug handler Figure 10 13 shows a high level view of the actions taken by the host and debug handler during dynamic code download Figure 10 13 Downloading Code in IC During Program Execution 10 38 Debugger Actions signal handler wait for handler to signal poca is complete ready to start download download code AR TCKS T JTAG IR DBGTX X LDIC Y DBGRX continue execution Handler begins execution signal host ready for download wait for host to signal download complete Debug Handler Actions The following steps describe the details for downloading code 1 Since the debug handler is responsible for synchronization during the code download the handler must be executing before the host can begin the download The debug handler execution starts when the application running on the Intel amp XScaleTM core generates a debug exception or when the host generates an external debug break 2 While the DBGTX JTAG instruction is in the JTAG IR see Section 10 DBGTX JTAG Command the host polls DBG SR 0 wa
110. e single issue superpipeline consists of a main execution pipeline MAC pipeline and a memory access pipeline These are shown in Figure A 1 with the main execution pipeline shaded Figure A 1 Intel amp XScale Core RISC Superpipeline A 2 Memory pipeline gt Main execution pipeline Table A 1 gives a brief description of each pipe stage Intel XScale Microarchitecture User s Manual In Optimization Guide Table A 1 Pipelines and Pipe stages A 2 1 3 A 2 1 4 A 2 1 5 Pipe Pipestage Description Covered In Main Execution Pipeline Handles data processing instructions Section A 2 3 F1 F2 Instruction Fetch Section A 2 3 ID Instruction Decode Section A 2 3 RF Register File Operand Shifter Section A 2 3 X1 ALU Execute Section A 2 3 X2 State Execute Section A 2 3 XWB Write back Section A 2 3 Memory Pipeline Handles load store instructions Section A 2 4 D1 D2 Data Cache Access Section A 2 4 DWB Data cache writeback Section A 2 4 MAC Pipeline Handles all multiply instructions Section A 2 5 M1 M5 Multiplier stages Section A 2 5 MWB not shown MAC write back may occur during M2 M5 Section A 2 5 Out Of Order Completion Sequential consistency of instruction execution relates to two aspects first to the order in which the instructions are completed and second to the order in which memory is accessed due to load and store instructions The Intel amp XScaleTM core preserves a wea
111. e that no more than 4 loads are outstanding at the same time For example the number of loads issued sequentially should not exceed 4 Also note that a preload instruction may cause a fill buffer to be used As a result the number of preload instructions outstanding should also be considered to derive how many loads are simultaneously outstanding Similarly the number of write buffers also limits the number of successive writes that can be issued before the processor stalls No more than eight stores can be issued Also note that 1f the data caches are using the write allocate with writeback policy then a load operation may cause stores to the external memory if the read operation evicts a cache line that is dirty modified The number of sequential stores may be further limited by these other writes Scheduling Load and Store Double LDRD STRD The Intel XScale core introduces two new double word instructions LDRD and STRD LDRD loads 64 bits of data from an effective address into two consecutive registers conversely STRD stores 64 bits from two consecutive registers to an effective address There are two important restrictions on how these instructions may be used the effective address must be aligned on an 8 byte boundary e the specified register must be even 10 12 etc If this situation occurs using LDRD STRD instead of LDM STM to do the same thing is more efficient because LDRD STRD issues in only one two clock cycle s
112. e unpredictable results Table 7 12 Cache Functions Sheet 1 of 2 Function opcode 2 CRm Data Instruction Invalidate I amp D cache amp BTB 0b000 0b0111 Ignored MCR p15 0 Rd c7 c7 0 Invalidate cache amp BTB 0b000 0b0101 Ignored MCR p15 0 Rd c7 c5 0 Invalidate cache line 0b001 0b0101 MVA MCR p15 0 Rd c7 c5 1 Invalidate D cache 0b000 0b0110 Ignored MCR p15 0 Rd c7 c6 0 Invalidate D cache line 0b001 0b0110 MVA MCR p15 0 Rd c7 c6 1 Clean D cache line 0b001 0b1010 MVA MCR p15 0 Rd c7 c10 1 Intel XScale Microarchitecture User s Manual 7 9 Configuration n Table 7 12 Cache Functions Sheet 2 of 2 7 2 8 7 10 Function opcode_2 CRm Data Instruction Drain Write amp Fill Buffer 0b100 0b1010 Ignored MCR p15 0 Rd c7 c10 4 Invalidate Branch Target Buffer 0b110 0b0101 Ignored MCR p15 0 Rd c7 c5 6 Allocate Line in the Data Cache 0b101 0b0010 MVA MCR p15 0 Rd c7 c2 5 The line allocate command allocates a tag into the data cache specified by bits 31 5 of Rd Ifa valid dirty line with a different MVA already exists at this location it will be evicted The 32 bytes of data associated with the newly allocated line are not initialized and therefore will generate unpredictable results if read This command may be used for cleaning the entire data cache on a context switch and also when re config
113. ed in the Intel XScale core do not add to the instruction latencies numbers The following section explains how to read these tables Performance Terms Issue Clock cycle 0 The first cycle when an instruction is decoded and allowed to proceed to further stages in the execution pipeline i e when the instruction is actually issued Cycle Distance from A to B The cycle distance from cycle A to cycle B is B A that is the number of cycles from the start of cycle A to the start of cycle B Example the cycle distance from cycle 3 to cycle 4 is one cycle Issue Latency The cycle distance from the first issue clock of the current instruction fo the issue clock of the next instruction The actual number of cycles can be influenced by cache misses resource dependency stalls and resource availability conflicts Result Latency The cycle distance from the first issue clock of the current instruction fo the issue clock of the first instruction that can use the result without incurring a resource dependency stall The actual number of cycles can be influenced by cache misses resource dependency stalls and resource availability conflicts Minimum Issue Latency without Branch Misprediction The minimum cycle distance from the issue clock of the current instruction 10 the first possible issue clock of the next instruction assuming best case conditions e that the issuing of the next instruction is not stalled due to
114. emory stalls long enough that the assumption fails In this case the download with normal handshaking can be used or high speed download can still be used but a few extra TCKs in the Pause_DR state may be necessary to allow a little more time for the store to complete The hardware support for high speed download includes the Download bit DCSR 29 and the Overflow Flag DCSR 30 The download bit acts as a branch flag signalling to the handler to continue with the download This removes the need for a counter in the debug handler The overflow flag indicates that the debugger attempted to download the next word before the debug handler read the previous word More details on the Download bit Overflow flag and high speed download in general can be found in Section 10 Transmit Receive Control Register TXRXCTRL Following is example code showing how the Download bit and Overflow flag are used in the debug handler hs write word loop hs write overflow bl read RX read data word from host read TXRXCTRL into the CCs mrc pl4 0 r15 c14 cO O bcc hs write done if D bit clear download complete exit loop beq hs write overflow if overflow detected loop until host clears D bit str rO r6 4 store only if there is no overflow b hs write word loop get next data word hs write done after the loop if the overflow flag was set return error message to host moveq ro HOVERFLOW RESPONSE beq send response
115. en rereere ene A 10 A 3 2 Bit Field Manipulation r a e a a a E a a aai A 11 A 3 3 Optimizing the Use of Immediate Values A 11 A 3 4 Optimizing Integer Multiply and Divide ss m A 11 A 3 5 Effective Use of Addressing Modes ee A 12 viii Intel XScale Microarchitecture User s Manual i ntel Contents AA Cache and Prefetch Optimizations rennen A 12 A 4 1 Instruction Cache A 13 A444 Cache Miss COS diiniita edes ence e odd eel d ue RR Ee n ah A 13 A 4 1 2 Round Robin Replacement Cache Policy sess A 13 A 4 1 3 Code Placement to Reduce Cache Misses ecnneeereeenee A 13 A 4 1 4 Locking Code into the Instruction Cache eeeeeeeeeeeseeeereeeeenesen A 13 A42 Data and Mini Cache 4 toe t tete Re hee e EAR E A 14 A 4 2 1 Non Cacheable Regions eene A 14 A 4 2 2 Write through and Write back Cached Memory Regions A 14 A 4 2 3 Read Allocate and Read write Allocate Memory Regions A 15 A 4 2 4 Creating ODp chipRAM emen enn A 15 AA 25 Mini data Cache aan ann A 15 A 4 2 6 Data Alignment emen A 16 AA Literal Pools iniret ete rd n teer dd o di A 17 A 4 3 Cache Considerations ooocococccinnnocccccnnoconcccnnnnnncncnnnnnnnncncnnnn eene A 17 A 4 3 1 Cache Conflicts Pollution and Pressure A 17 A 4 3 2 Memory Page Thrasbmg ee A 18 AAA Prefetch Considerations 00 ccccccecccccceeeeccceceeseeceeeeeeseecceeeeesne
116. eq r0 r5 4 addne r4 r5 4 subeq r4 r5 4 cmp r0 10 The optimized code takes six cycles to execute compared to the seven cycles taken by the unoptimized version The result latency for an LDR instruction is significantly higher 1f the data being loaded is not in the data cache To minimize the number of pipeline stalls in such a situation the LDR instruction should be moved as far away as possible from the instruction that uses result of the load Note that this may at times cause certain register values to be spilled to memory due to the increase in register pressure In such cases use a prefetch load instruction as a preload hint to ensure that the data access in the LDR instruction hits the cache when it executes A PLD instruction should be used in cases where we can be sure that the load instruction would be executed Consider the following code sample all other registers are in use sub rl 6 rJ mul E3526 2 mov r2 r2 LSL 2 orr r9 r9 Host add r0 r4 rb ldr r6 r0 add r8 r6 r8 add r8 r8 4 orr r8 r8 Host The value in register r6 is not used after this In the code sample above the ADD and the LDR instruction can be moved before the MOV instruction Note that this would prevent pipeline stalls if the load hits the data cache However if the load is likely to miss the data cache move the LDR instruction so that it executes as early as possible before the SUB instruction However moving the LDR in
117. er Restrictions The Debug Handler executes in Debug Mode which is similar to other privileged processor modes however there are some differences Following are restrictions on Debug Handler code and differences between Debug Mode and other privileged modes The processor is in Special Debug State following a debug exception and thus has special functionality as described in Section 10 Halt Mode Although address translation and PID remapping are disabled for instruction accesses as defined in Special Debug State data accesses use the normal address translation and PID remapping mechanisms Debug Mode does not have a dedicated stack pointer DBG_r13 Although DBG r13 exists it is not a general purpose register Its contents are unpredictable and cannot be relied upon across any instructions or exceptions However DBG r13 can be used by data processing non RRX and MCR MRC instructions as a temporary scratch register The following instructions must not be executed in Debug Mode as they will result in unpredictable behavior LDM LDR w Rd PC LDR w RRX addressing mode SWP LDC STC Intel XScale Microarchitecture User s Manual intel 10 14 2 3 Software Debug The handler executes in Debug Mode and can be switched to other modes to access banked registers The handler must not enter User Mode any User Mode registers that need to be accessed can be accessed in System Mode Entering User Mode will cause unpre
118. ermine when the TX register is empty any previous data has been read out by the debugger The handler polls the TR bit until it is clear Once the TR bit is clear the debug handler writes new data to the TX register The write operation automatically sets the TR bit Conditional Execution Using TXRXCTRL All ofthe bits in TXRXCTRL are placed such that they can be read directly into the CC flags using an MCR instruction To simplify the debug handler the TXRXCTRL register should be read using the following instruction mro p14 0 r15 C14 CO O This instruction will directly update the condition codes in the CPSR The debug handler can then conditionally execute based on each CC bit Table 10 12 shows the mnemonic extension to conditionally execute based on whether the TXRXCTRL bit is set or clear Table 10 12 TXRXCTRL Mnemonic Extensions 10 14 TXRXCTRL bit mnemonic extension to execute if bit set all EE ta motera IT BIE 31 to N flag MI PL 30 to Z flag EQ NE 29 to C flag CS CC 28 to V flag VS VC The following example is a code sequence in which the debug handler polls the TXRXCTRL handshaking bit to determine when the debugger has completed its write to RX and the data is ready for the debug handler to read loop mcr pl4 0 r15 c14 cO O read the handshaking bit in TXRXCTRL Intel XScale Microarchitecture User s Manual i ntel Software Debug mcrmi pl4 0 r0 c9
119. ers will cause an undefined instruction trap The CRn field specifies the number of the register to access The CRm opcode_1 and opcode_2 fields are not used and must be set to 0 10 23 Software Debug n Table 10 16 CP 14 Trace Buffer Register Summary 10 11 1 1 CP14 Register Number Register Name 11 Trace Buffer Register TBREG 12 Checkpoint 0 Register CHKPTO 13 Checkpoint 1 Register CHKPT1 Any access to the trace buffer registers in User mode will cause an undefined instruction exception Specifying registers which do not exist has unpredictable results Checkpoint Registers When the debugger reconstructs a trace history it is required to start at the oldest trace buffer entry and construct a trace going forward In fill once mode and wrap around mode when the buffer does not wrap around the trace can be reconstructed by starting from the point in the code where the trace buffer was first enabled The difficulty occurs in wrap around mode when the trace buffer wraps around at least once In this case the debugger gets a snapshot of the last N control flow changes in the program where N is less than of equal to the size of the buffer The debugger does not know the starting address of the oldest entry read from the trace buffer The checkpoint registers provide reference addresses to help reduce this problem Table 10 17 Checkpoint Register CHKPTx 10 24 31 30 29 28 27 26 25 24 23 22 21 20
120. es are walked through can affect the temporal quality of the data and reduce or increase cache conflicts The Intel XScale core data cache and mini data caches each have 32 sets of 32 bytes This means that each cache line in a set is on a modular 1K address boundary The caution is to choose data structure sizes and stride requirements that do not overwhelm a given set causing conflicts and increased register pressure Register pressure can be increased because additional registers are required to track prefetch addresses The effects can be affected by rearranging data structure components to use more parallel accesses to search and compare elements Similarly rearranging sections of data structures so that sections often written fit in the same half cache line 16 bytes for the Intel XScale core can reduce cache eviction write backs On a global scale techniques such as array merging can enhance the spatial locality of the data As an example of array merging consider the following code int a NMAX int b NMAX int ix for i20 i lt NMAX i ix b il if a i 0 ix a i do_other calculations In the above code data is read from both arrays a and b but a and b are not spatially close Array merging can place a and b spatially close struct int a int b c arrays int ix for i20 i lt NMAX i ix c il b if c il a 0 ix c il a do_other_calculations A
121. es which counter overflowed Bit 10 7 clock counter overflow flag Bit 9 performance counter 1 overflow flag Bit 8 performance counter 0 overflow flag 10 8 Read Write Read Values 0 no overflow 1 overflow has occurred Write Values 0 nochange 1 clear this bit 7 Read unpredictable Write as 0 Reserved Interrupt Enable used to enable disable interrupt reporting for each counter Bit 6 clock counter interrupt enable 0 disable interrupt 17 enable interrupt 6 4 Read Write Bit 5 performance counter 1 interrupt enable 0 disable interrupt 17 enable interrupt Bit 4 performance counter 0 interrupt enable 0 disable interrupt 17 enable interrupt Clock Counter Divider D 3 Read Write 0 CCNT counts every processor clock cycle 1 CONT counts every 64th processor clock cycle Intel XScale Microarchitecture User s Manual 8 3 Performance Monitoring n Table 8 3 Performance Monitor Control Register CP14 register 0 Sheet 2 of 2 8 4 1 8 5 Note 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 54 3 2 1 L eee O eoe O e O e PETE reset value E and inten are 0 others unpredictable Bits Access Description Clock Counter Reset C 2 Read unpredictable Write 0 no action 1 reset the clock counter to 0x0 Performance Counter Reset P 1 Read unpredictable Write 0 no action 1 reset both perfo
122. esult is not yet available the Intel amp XScale M core stalls in order to preserve the correct data dependencies PMNO counts the number of stall cycles due to data dependencies Not all data dependencies cause a stall only the following dependencies cause such a stall penalty Load use penalty attempting to use the result ofa load before the load completes To avoid the penalty software should delay using the result of a load until it s available This penalty shows the latency effect of data cache access Multiply Accumulate use penalty attempting to use the result of a multiply or multiply accumulate operation before the operation completes Again to avoid the penalty software should delay using the result until it s available ALU use penalty there are a few isolated cases where back to back ALU operations may result in one cycle delay in the execution These cases are defined in Chapter 11 Performance Considerations PMNI counts the number of writeback operations emitted by the data cache These writebacks occur when the data cache evicts a dirty line of data to make room for a newly requested line or as the result of clean operation CP15 register 7 Statistics derived from these two events The percentage of total execution cycles the processor stalled because of a data dependency This is calculated by dividing PMNO by CCNT which was used to measure total execution time Often a compiler can reschedule code to a
123. fication register is used to read the 32 bit device identification code No programmable supplementary identification code is provided When the idcode instruction is current the ID register is selected as the serial path between TDI and TDO The format of the ID register is as follows 31 28 27 12 11 0 Version Part Number JEDEC Code The high order 4 bits ofthe ID register contains the version number of the silicon and changes with each new revision There is no parallel output from the ID register The 32 bit device identification code is loaded into the ID register from its parallel inputs during the CAPTURE DR state Intel XScale Microarchitecture User s Manual 9 7 Test 9 4 4 9 5 9 8 intel Data Specific Registers are used for the application processor instruction cache initialization and software debugging For further information see Section 10 3 Debug Control and Status Register DCSR on page 10 3 Section 10 10 2 SELDCSR JTAG Register on page 10 17 Section 10 13 2 LDIC JTAG Data Register on page 10 31 Section 10 10 4 DBGTX JTAG Register on page 10 19 and Section 10 10 6 DBGRX JTAG Register on page 10 20 Data Specific Registers TAP Controller The TAP controller is a 16 state synchronous finite state machine that controls the sequence of test logic operations The TAP can be controlled via a bus master The bus master can be either automatic test equipment or
124. fications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright O Intel Corporation 2003 Other names and brands may be claimed as the property of others ARM and StrongARM are registered trademarks of ARM Ltd ii Intel XScale Microarchitecture User s Manual i ntel Contents Contents 1 A 1 1 13 About This DOCUmohlt titre tet rente ata 1 1 1 1 1 How to Read This Document 1 1 1 1 2 Other Relevant Documents ssssssseneseneeenrtnrtrrtrnsstrrsrttttttnrnnsrnnratrt ttnn tnn nennen ent 1 1 1 2 High Level Overview of the Intel XScale core as Implemented in the elei ele ein Med ee 1 2 1 2 1 ARM Compatibility au a naeh 1 3 JF UM WE 1 3 1 2 2 1 Multiply Accumulate MAC 1 3 1 2 2 2 Memory Management 1 4 1 2 2 3 Instruction Cache eter rta Eee betta ten prd Mae chua 1 4 1 2 2 4 Branch Target Buffer cete eadein nae 1 4 1 2 2 5 Data Cache A 1 4 1 2 2 6 Fill Buffer amp Write Buffer ooooococooononnconccnccccccccnooonnononccnnnonnnnnnnnnnnnnnnnnos 1 5 1 2 2 7
125. following a cold reset 1 ON Ai Assert the Reset and TRST pins This resets the JTAG IR to IDCODE and invalidates the instruction cache main and mini Load the SELDCSR JTAG instruction into JTAG IR and scan in a value to set the Halt Mode bit in DCSR and to set the hold_rst signal For details ofthe SELDCSR refer to Section 10 10 2 After hold_rst is set de assert the Reset pin Internally the processor remains held in reset After Reset is de asserted wait 2030 TCKs Load the LDIC JTAG instruction into JTAG IR Download code into instruction cache in 33 bit packets as described in Section 10 LDIC Cache Functions After code download is complete clock a minimum of 15 TCKs following the last update_dr in LDIC mode Place the SELDCSR JTAG instruction into the JTAG IR and scan in a value to clear the hold_rst signal The Halt Mode bit must remain set to prevent the instruction cache from being invalidated When hold_rst is cleared internal reset is de asserted and the processor executes the reset vector at address 0 Intel XScale Microarchitecture User s Manual 10 35 Software Debug I ntel ii 10 13 4 2 10 36 An additional issue for debug is setting up the reset vector trap This must be done before the internal reset signal is de asserted As described in Section 10 3 3 the Halt Mode and the Trap Reset bits in the DCSR must be set prior to de asserting reset in order to trap the reset vector There are
126. g exception is generated before the instruction in the exception vector executes Software running on the Intel amp XScaleTM core must set the Global Enable bit and the debugger must set the Halt Mode bit and the appropriate vector trap bit through JTAG to set up a non reset vector trap Intel XScale Microarchitecture User s Manual 10 3 4 10 3 5 10 3 6 10 3 7 10 4 Software Debug To set up a reset vector trap the debugger sets the Halt Mode bit and reset vector trap bit through JTAG The Global Enable bit does not effect the reset vector trap A reset vector trap can be set up before or during a processor reset When processor reset is de asserted a debug exception occurs before the instruction in the reset vector executes Sticky Abort Bit SA The Sticky Abort bit is only valid in Halt mode It indicates a data abort occurred within the Special Debug State see Section 10 Halt Mode Since Special Debug State disables all exceptions a data abort exception does not occur However the processor sets the Sticky Abort bit to indicate a data abort was detected The debugger can use this bit to determine if a data abort was detected during the Special Debug State The sticky abort bit must be cleared by the debug handler before exiting the debug handler Method of Entry Bits MOE The Method of Entry bits specify the cause of the most recent debug exception When multiple exceptions occur in parallel the processor pl
127. g them down into the cache removing or reducing the occurrences of hardware page table walks This also can be accomplished by locking down the application s page table entries into the TLBs along with the page table entry for the interrupt service routine Intel XScale Microarchitecture User s Manual 11 9 Performance Considerations 11 10 Intel XScale Microarchitecture User s Manual intel Optimization Guide A 1 A 1 1 A 2 Introduction This document contains optimization techniques for achieving the highest performance from the Intel XScale core architecture It is written for developers who are optimizing compilers or performance analysis tools for the Intel XScale core based processors It can also be used by application developers to obtain the best performance from their assembly language code The optimizations presented in this chapter are based on the Intel XScale core and hence can be applied to all products that are based on it including the PX A255 processor The Intel XScale core architecture includes a superpipelined RISC architecture with an enhanced memory pipeline The Intel XScale core instruction set is based on ARM v5 architecture however the Intel XScale core includes new instructions Code generated for the SA 110 SA 1100 and SA 1110 executes on Intel XScale core based processors however to obtain the maximum performance of your application code it shou
128. gger this event Executing a swi from User mode will not trigger this event because it will incur a mode change all others Reserved unpredictable results Some typical combination of counted events are listed in this section and summarized in Table 8 5 In this section we call such an event combination a mode Table 8 5 Some Common Uses of the PMU 8 5 1 Mode PMNC evtCount0 PMNC evtCount1 Instruction Cache Efficiency 0x7 instruction count 0x0 I Cache miss Data Cache Efficiency OxA D Cache access OxB D Cache miss Instruction Fetch Latency Ox1 I Cache cannot deliver 0x0 I Cache miss Data Bus Request Buffer Full 0x8 D Buffer stall duration 0x9 D Buffer stall Stall Writeback Statistics 0x2 data stall OxC D Cache writeback Instruction TLB Efficiency 0x7 instruction count 0x3 ITLB miss Data TLB Efficiency OxA D cache access 0x4 DTLB miss Instruction Cache Efficiency Mode PMNO totals the number of instructions that were executed which does not include instructions fetched from the instruction cache that were never executed This can happen if a branch instruction changes the program flow the instruction cache may retrieve the next sequential instructions after the branch before it receives the target address of the branch PMNI counts the number of instruction fetch requests to external memory Ea
129. gister pressure instead of increasing it The prefetch load is a hint instruction and does not guarantee that the data will be loaded Whenever the load would cause a fault or a table walk then the processor will ignore the prefetch instruction the fault or table walk and continue processing the next instruction This is particularly advantageous in the case where a linked list or recursive data structure is terminated by a NULL pointer Prefetching the NULL pointer will not fault program flow Prefetch Distances Scheduling the prefetch instruction requires some understanding of the system latency times and system resources which affect when to use the prefetch instruction For the PXA255 processor a cache line fill of 8 words from external memory will take more than 10 memory clocks depending on external RAM speed and system timing configuration With the core running faster than memory data from external memory may take many tens of core clocks to load especially when the data is the last in the cacheline Thus there can be considerable savings from prefetch loads being used many instructions before the data is referenced Prefetch Loop Scheduling When adding prefetch to a loop which operates on arrays it may be advantageous to prefetch ahead one two or more iterations The data for future iterations is located in memory by a fixed offset from the data for the current iteration This makes it easy to predict where to fetch the data The
130. gram execution Loading the instruction cache during normal program execution requires a strict handshaking protocol between software running on the Intel XScaleTM core and the external host In the remainder of this section the term instruction cache applies to either main or mini instruction cache LDIC JTAG Command The LDIC JTAG instruction selects the JTAG data register for loading code into the instruction cache The JTAG opcode for this instruction is 00111 The LDIC instruction must be in the JTAG instruction register in order to load code directly into the instruction cache through JTAG 1 A cache line fill from external memory will never be written into the mini instruction cache The only way to load a line into the mini instruction cache is through JTAG 10 30 Intel XScale Microarchitecture User s Manual ntel Software Debug 10 13 2 LDIC JTAG Data Register The LDIC JTAG Data Register is selected when the LDIC JTAG instruction is in the JTAG IR An external host can load and invalidate lines in the instruction cache through this data register Figure 10 9 LDIC JTAG Data Register Hardware unpredictable Y TDI gt TDO LDIC_SR1 Gi SSES Capture DR Update DR LDIC REG os 2 1 0 TCK Y Core CLK LDIC SR2 s2 2 1 0 To Instructi
131. he JTAG opcode for this instruction is 0b10000 Once the DBGTX data register is selected the debugger can receive data from the debug handler DBGTX JTAG Register The DBGTX JTAG instruction selects the Debug JTAG Data register Figure 10 2 The debugger uses the DBGTX data register to poll for breaks internal and external both to cause an entry into Debug mode and once in Debug mode to read data from the debug handler Figure 10 2 DBGTX Hardware software write set by write to TX software read only TX T a 2 TXRXCTRL 28 0x0000 0000 Core CLK Jp m mm mmm mm mm mm ee mm mm mm mm mm mmm mm mm mm mm mm Om Rm mm m m m I Capture DR Y TELS d M NO 174 elay I 0 0 1 I clear by Debugger read o TDO I 35 34 3 2 1 0 DBG SR 1 z 1 Update_DR Ignored A Capture DR loads the TX register value into DBG_SR 34 3 and TXRXCTRL 28 into DBG SR 0 The other bits in DBG_SR are loaded as shown in Figure 10 3 The captured TX value is scanned out during the Shift DR state Data scanned in is ignored on an Update DR A 1 captured in DBG SR 0 indicates the captured TX data is valid After doing a Capture DR the debugger must place the JTAG state machine in the Shift DR state to guarantee that a debugger read clears TXRXCTRL 28 Intel XScale Microarchitecture
132. i data cache memory region and each is array is aligned on a 1K boundary will quickly thrash the cache Data Alignment Cache lines begin on 32 byte address boundaries To maximize cache line use and minimize cache pollution data structures should be aligned on 32 byte boundaries and sized to multiple cache line sizes Aligning data structures on cache address boundaries simplifies later addition of prefetch instructions to optimize performance Not aligning data on cache lines has the disadvantage of moving the prefetch address correspondingly to the misalignment Consider the following example struct long ia long ib long ic long id tdata IMAX for i 0 i lt IMAX i PREFETCH tdata i 1 tdata i ia tdata i ib tdata i ic tdatalil id tdata i id 0 In this case if tdata is not aligned to a cache line then the prefetch using the address of tdata i 1 1a may not include element id If the array was aligned on a cache line 12 bytes then the prefetch would have to be placed on amp tdata i 1 id Intel XScale Microarchitecture User s Manual A 4 2 7 A 4 3 A 4 3 1 Optimization Guide If the structure is not sized to a multiple of the cache line size then the prefetch address must be advanced appropriately and will require extra prefetch instructions Consider the following example struct long ia long ib long ic long id long ie tdata IMAX ADDRESS
133. icky flag that is set when the debugger writes to the RX register while the RR bit is set The flag is used during high speed download to indicate that some data was lost The assumption during high speed download is that the time it takes for the debugger to shift in the next data word is greater than the time necessary for the debug handler to process the previous data word So before the debugger shifts in the next data word the handler will be polling for that data However if the handler incurs stalls that are long enough such that the handler is still processing the previous data when the debugger completes shifting in the next data word an overflow condition occurs and the OV bit is set Once set the overflow flag will remain set until cleared by a write to TXRXCTRL with an MCR After the debugger completes the download it can examine the OV bit to determine if an overflow occurred The debug handler software is responsible for saving the address of the last valid store before the overflow occurred Download Flag D The value of the download flag is set by the debugger through JTAG This flag is asserted during high speed download to replace a loop counter Using the download flag the debug handler loops until the debugger clears the flag Therefore when doing a high speed download for each data word downloaded the debugger should set the D bit On completing the download the debugger clears the D bit releasing the debug handle
134. icult to predict This information must be gained by experimentation using performance profiling Code Placement to Reduce Cache Misses Code placement can greatly affect cache misses One way to view the cache is to think of it as 32 sets of 32 bytes which span an address range of 1024 bytes When running the code maps into 32 modular blocks of 1024 bytes of cache space See Figure 6 1 on page 6 2 Any sets which are overused will thrash the cache The ideal situation is for the software tools to distribute the code on a temporal evenness over this space This is very difficult if not impossible for a compiler to do Most of the input needed to best estimate how to distribute the code will come from profiling followed by compiler based two pass optimizations Locking Code into the Instruction Cache One very important instruction cache feature is the ability to lock code into the instruction cache Once locked into the instruction cache the code is always available for fast execution Another reason for locking critical code into cache is that with the round robin replacement policy eventually the code will be evicted even if it is a very frequently executed function Key code components to consider for locking are Interrupt handlers Real time clock handlers OS critical code Time critical application code The disadvantage to locking code into the cache is that it reduces the cache size for the rest of the program How much c
135. in which the condition is present Stall due to a data dependency This event will occur every cycle in which the condition is 0x2 present 0x3 Instruction TLB miss 0x4 Data TLB miss Intel XScale Microarchitecture User s Manual Performance Monitoring Table 8 4 Performance Monitoring Events Sheet 2 of 2 Event Number evtCount0 or evtCount1 Event Definition 0x5 Branch instruction executed branch may or may not have changed program flow 0x6 Branch mispredicted B and BL instructions only 0x7 Instruction executed 0x8 Stall because the data cache buffers are full This event will occur every cycle in which the condition is present 0x9 Stall because the data cache buffers are full This event will occur once for each contiguous sequence of this type of stall regardless the length of the stall OxA Data cache accesses including misses and uncached accesses but not including Cache Operations defined in Section 7 2 7 OxB Data cache misses including uncached accesses but not including Cache Operations defined in Section 7 2 7 OxC Data cache write back This event occurs once for each 1 2 line four words that are written back from the cache OxD Software changed the PC This event occurs any time the PC is changed by software and there is not a mode change For example a mov instruction with PC as the destination will tri
136. ing edge of TCK the controller moves to the Select DR Scan state Select DR Scan State The Select DR Scan state is a temporary controller state The test data registers selected by the current instruction retain their previous state If TMS is held low on the rising edge of TCK when the controller is in this state the controller moves into the Capture DR state and a scan sequence for the selected test data register is initiated If TMS is held high on the rising edge of TCK the controller moves into the Select IR Scan state The instruction does not change while the TAP controller is in this state Capture DR State When the controller is in this state and the current instruction is sample preload the Boundary Scan register captures input pin data on the rising edge of TCK Test data registers that do not have parallel input are not changed Also if the sample preload instruction is not selected while in this state the Boundary Scan registers retain their previous state The instruction does not change while the TAP controller is in this state If TMS is high on the rising edge of TCK the controller enters the Exit1 DR If TMS is low on the rising edge of TCK the controller enters the Shift DR state Shift DR State In this controller state the test data register which is connected between TDI and TDO as a result of the current instruction shifts data one bit position nearer to its serial output on each rising edge of TCK Test d
137. ing loaded or stored assuming a data cache hit The instruction following an LDM would stall whether or not this instruction depends on the results of the load A LDRD or STRD instruction does not suffer from this drawback except when followed by a memory operation and should be used where possible Consider the task of adding two 64 bit integer values Assume that the addresses of these values are aligned on an 8 byte boundary This can be achieved using the LDM instructions as shown below r0 contains the address of the value being copied rl contains the address of the destination location ldm r0 r2 r3 ldm rl r4 r5 adds r0 r2 r4 adc El 23425 If the code were written as shown above assuming all the accesses hit the cache the code would take 11 cycles to complete Rewriting the code as shown below using LDRD instruction would take only 7 cycles to complete The performance would increase further if we can fill in other instructions after LDRD to reduce the stalls due to the result latencies of the LDRD instructions r0 contains the address of the value being copied rl contains the address of the destination location ldrd r2 r0 ldrd r4 r1 adds r0 r2 r4 adc rl r3 r5 Similarly the code sequence shown below takes 5 cycles to complete stm TO r2 r3 add Pri rl 1 The alternative version which 1s shown below would only take 3 cycles to complete strd r2 r0 add El El HI Intel XScale Microarch
138. ing reset can only be loaded into the mini instruction cache However code can be dynamically downloaded into the main instruction cache refer to Section 10 Dynamically Loading IC After Reset The following sections describe the steps necessary to ensure code is correctly downloaded into the instruction cache Loading IC During Cold Reset for Debug The Figure 10 11 shows the actions necessary to download code into the instruction cache during a cold reset for debug NOTE In the Figure 10 11 hold rst is a signal that gets set and cleared through JTAG When the JTAG IR contains the SELDCSR instruction the hold rst signal is set to the value scanned into DBG SR I Intel XScale Microarchitecture User s Manual intel Software Debug Figure 10 11 Code Download During a Cold Reset For Debug Reset Pin RESET pin asserted until hold rst signal is set TRST resets JTAG IR to IDCODE TRST a S Ic RESET does not affect IC Internal RESET hold_rst keeps internal reset asserted ER branches i to address 0 hold rst clock 15 tcks after wait 2030 tcks after last update dr Reset deasserted in LDIC mode L JTAG IR E IDCODE SELDCSR V LDIC X SELDCSR set hold rst signal Enter LDIC mode clear hold rst signal set Halt Mode bit Download code keep Halt Mode bit set An external host should take the following steps to load code into the instruction cache
139. ions to create the debug handler start address and branch to it This would require another line in the mini instruction cache since the intermediate code must also be downloaded This method also requires that the layout of the debug handler be well thought out to avoid the intermediate code overwriting a line of debug handler code or vice versa For the indirect branch cases a temporary scratch register may be necessary to hold intermediate values while computing the final target address DBG_r13 can be used for this purpose see Section 10 Debug Handler Restrictions for restrictions on DBG r13 usage Implementing a Debug Handler The debugger uses the debug handler to examine or modify processor state by sending commands and reading data through JTAG The software interface between the debugger and debug handler is specific to a debugger implementation Debug Handler Entry When the debugger requests an external debug break or is waiting for an internal break it then polls the TR bit through JTAG to determine when the processor has entered Debug Mode The debug handler entry code must do a write to TX to signal the debugger that the processor has entered Debug Mode The write to TX sets the TR bit signalling the host that a debug exception has occurred and the processor has entered Debug Mode The value of the data written to TX is implementation defined debug break message contents of register to save on host etc Debug Handl
140. ious pipestages and sends the branch target address to the BTB which will restart the pipeline X2 Execute 2 Pipestage The X2 pipestage contains the program status registers PSRs This pipestage selects what is going to be written to the RFU in the XWB cycle PSRs MRS instruction ALU output or other items XWB write back When an instruction has reached the write back stage it is considered complete Changes are written to the RFU Memory Pipeline The memory pipeline consists of two stages D1 and D2 The data cache unit or DCU consists of the data cache array mini data cache fill buffers and writebuffers The memory pipeline solely handles load and store instructions D1 and D2 Pipestage Operation begins in D1 after the X1 pipestage has calculated the effective address for load stores The data cache and mini data cache returns the destination data in the D2 pipestage Before data is returned in the D2 pipestage sign extension and byte alignment occurs for byte and half word loads Multiply Multiply Accumulate MAC Pipeline The Multiply Accumulate MAC unit executes all multiply and multiply accumulate instructions supported by the Intel XScale core The MAC implements the 40 bit Intel XScale core accumulator register accO and handles the instructions which transfer its value to and from general purpose ARM registers The following are important characteristics about the MAC The MAC is not truly
141. ire trace buffer can be used to re create the trace The worst case is when the first checkpoint is in the middle of the trace buffer and no indirect branch messages exist before this checkpoint In this case the host software would have to start at its known address the first checkpoint which is half way through the buffer and work forward from there Trace Buffer Entries Trace buffer entries consist of either one or five bytes Most entries are one byte messages indicating the type of control flow change The target address of the control flow change represented by the message byte is either encoded in the message byte as for exceptions or can be determined by looking at the instruction word like for direct branches Indirect branches require five bytes per entry One byte is the message byte identifying it as an indirect branch The other four bytes make up the target address of the indirect branch The following sections describe the trace buffer entries in detail Message Byte There are two message formats exception and non exception as shown in Figure 10 7 Figure 10 7 Message Byte Formats 0 0 7 7 M Message Type Bit MMMM Message Type Bits VVV exception vector 4 2 CCCC Incremental Word Count CCCC Incremental Word Count Exception Format Non exception Format Table 10 19 shows all of the possible trace messages Intel XScale Microarchitecture User s Manual 10 27 Soft
142. itecture User s Manual A 27 Optimization Guide n A 5 2 A 5 3 A 28 Scheduling Data Processing Instructions Most Intel XScale core data processing instructions have a result latency of 1 cycle This means that the current instruction is able to use the result from the previous data processing instruction However the result latency is 2 cycles if the current instruction needs to use the result of the previous data processing instruction for a shift by immediate As a result the following code segment would incur a 1 cycle stall for the MOV instruction sub r6 r7 r8 add Yl r2 r3 mov r4 rl LSL 2 The code above can be rearranged as follows to remove the 1 cycle stall add rb 92 023 sub rE x7 x8 mov r4 rl LSL 2 All data processing instructions incur a 2 cycle issue penalty and a 2 cycle result penalty when the shifter operand is a shift rotate by a register or shifter operand is RRX Since the next instruction would always incur a 2 cycle issue penalty there is no way to avoid such a stall except by re writing the assembler instruction Consider the following segment of code mov r3 ELO mul r4 r2 r3 add r5 r6 r2 LSL r3 sub r7 X8 x2 The subtract instruction would incur a 1 cycle stall due to the issue latency of the add instruction as the shifter operand is shift by a register The issue latency can be avoided by changing the code as follows mov r3 10 mul r4 r2 r3 add r5 r6 r2 LSL 1
143. iting for the debug handler to set it 3 When the debug handler gets to the point where it is ready to begin the code download it writes to TX which automatically sets DBG SR 0 This signals the host that it can begin the download The debug handler then begins polling TXRXCTRL 31 waiting for the host to clear it through the DBGRX JTAG register to indicate the download is complete 4 The host writes LDIC to the JTAG IR and downloads the code For each line downloaded the host must invalidate the target line before downloading code to that line Failure to invalidate a line prior to writing it will cause unpredictable operation by the processor Intel XScale Microarchitecture User s Manual I n Software Debug 5 When the host completes its download the host must wait a minimum of 15 TCKs then switch the JTAG IR to DBGRX and complete the handshaking by scanning in a value that sets DBG_SR 35 This clears TXRXCTL 31 and allows the debug handler code to exit the polling loop 6 After the handler exits the polling loop it branches to the downloaded code Note The debug handler stub must reside in the instruction cache and execute out of the cache while doing the synchronization The processor must not be doing any code fetches to external memory while code is being downloaded 10 13 5 1 Dynamic Code Download Synchronization The following pieces of code are necessary in the debug handler to implement the synchronizatio
144. ize each pool to a multiple of 32 bytes the size of a cache line One additional optimization would be to group highly used literal pool references into the same cache line The advantage is that once one of the literals has been loaded the other seven will be available immediately from the data cache Cache Considerations Cache Conflicts Pollution and Pressure Cache pollution occurs when unused data is loaded in the cache and cache pressure occurs when data that is not temporal to the current process is loaded into the cache For an example see Section A 4 4 2 Prefetch Loop Scheduling below Intel XScale Microarchitecture User s Manual A 17 E Optimization Guide ntel A 4 3 2 A 4 4 A 4 4 1 A 4 4 2 A 18 Memory Page Thrashing Memory page thrashing occurs because of the nature of SDRAM SDRAMs are typically divided into multiple banks Each bank can have one selected page where a page address size for current memory components is often defined as 4k Memory lookup time or latency time for a selected page address is currently 2 to 3 bus clocks Thrashing occurs when subsequent memory accesses within the same memory bank access different pages The memory page change adds 3 to 4 bus clock cycles to memory latency This added delay extends the prefetch distance correspondingly making it more difficult to hide memory access latencies This type of thrashing can be resolved by placing the conflicting data structures
145. k processor consistency because instructions may complete out of order provided that no data dependencies exist While instructions are issued in order the main execution pipeline memory and MAC pipelines are not lock stepped and therefore have different execution times This means that instructions may finish out of program order Short younger instructions may be finished earlier than long older ones The term to finish is used here to indicate that the operation has been completed and the result has been written back to the register file Register Dependencies In certain situations the pipeline may need to be stalled because of register dependencies between instructions A register dependency occurs when a previous MAC or load instruction is about to modify a register value that has not been returned to the register file and the current instruction needs access to the same register If no register dependencies exist the pipeline will not be stalled For example if a load operation has missed the data cache subsequent instructions that do not depend on the load may complete independently Use of Bypassing The Intel XScale core pipeline makes extensive use of bypassing to minimize data hazards Bypassing allows results forwarding from multiple sources eliminating the need to stall the pipeline Intel XScale Microarchitecture User s Manual A 3 E Optimization Guide ntel A 2 2 A 2 2 1 A
146. l feature of the Intel XScale core Chapter 2 Programming Model Chapter 3 Memory Management Chapter 4 Instruction Cache Chapter 5 Branch Target Buffer Chapter 6 Data Cache e Chapter 7 Configuration Chapter 8 Performance Monitoring Chapter 10 Software Debug Chapter 11 Performance Considerations Appendix A Optimization Guide covers instruction scheduling techniques Most of the buzz words and acronyms found throughout this document are captured in Section 1 3 2 Terminology and Acronyms on page 1 6 located at the end of this chapter Other Relevant Documents ARM Architecture Reference Manual Document Number ARM DDI 0100E This document describes the ARM Architecture and is publicly available See http www arm com ARMARM for details Sold as ARM Architecture Reference Manual Second Edition edited by David Seal Addison Wesley ISBN 0 201 73719 1 Intel PXA255 Processor Developer s Manual Intel Order 278693 Intel XScale Microarchitecture User s Manual 1 1 Introduction 1 2 1 2 1 1 2 intel Intel PXA255 Processor Design Guide Intel Order 278694 Intel 80200 Processor Development Manual Intel Order 273411 This document describes the first implementation of the Intel amp XScaleTM Microarchitecture in a microprocessor targeted at IO applications Available from http developer intel com High Level Overview of
147. l the cache functions defined in existing StrongARM products appear here The Intel XScale core adds other functions as well This register is write only Reads from this register as with an MRC have an undefined effect Disabling enabling a cache has no effect on contents of the cache valid data stays valid locked items remain locked and accesses that hit in the cache will hit To prevent cache hits after disabling the cache it is necessary to invalidate it The way to prevent hits on the fill buffer is to drain it All operations defined in Table 7 12 work regardless of whether the cache is enabled or disabled The Drain Write Buffer function not only drains the write buffer but also drains the fill buffer The Intel XScale core does not check permissions on addresses supplied for cache or TLB functions Because only privileged software may execute these functions full accessibility is assumed Cache functions will not generate any of the following translation faults domain faults permission faults Since the Clean D Cache Line function reads from the data cache it is capable of generating a parity fault The other operations will not generate parity faults The invalidate instruction cache line command does not invalidate the BTB If software invalidates a line from the instruction cache and modifies the same location in external memory it needs to invalidate the BTB also Not invalidating the BTB in this case will caus
148. ld be optimized for the Intel XScale core using the techniques presented here About This Guide This guide assumes that you are familiar with the ARM instruction set and the C language It consists of the following sections Section A 1 Introduction Outlines the contents of this guide Section A 2 Intel XScale Core Pipeline This chapter provides an overview of the Intel XScale core pipeline behavior Section A 3 Basic Optimizations This chapter outlines basic optimizations that can be applied to the Intel XScale core Section A 4 Cache and Prefetch Optimizations This chapter contains optimizations for efficient use of caches Also included are optimizations that take advantage of the prefetch instruction of the Intel XScale core Section A 5 Instruction Scheduling This chapter shows how to optimally schedule code for the Intel XScale core pipeline Section A 6 Optimizations for Size This chapter contains optimizations that reduce the size of the generated code Intel XScale Core Pipeline One of the biggest differences between the Intel XScale core and StrongARM processors is the pipeline Many of the differences are summarized in Figure A 1 This section provides a brief description of the structure and behavior of the Intel XScale core pipeline Intel XScale Microarchitecture User s Manual A 1 a Optimization Guid ptimization Gui
149. livering instructions to the instruction decode ID pipestage One instruction word is delivered each cycle 1f possible to the ID The instruction could come from one of two sources instruction cache or fill buffers ID Instruction Decode Pipestage The ID pipestage accepts an instruction word from the IFU and sends register decode information to the RF pipestage The ID is able to accept a new instruction word from the IFU on every clock cycle in which there is no stall The ID pipestage 1s responsible for General instruction decoding extracting the opcode operand addresses destination addresses and the offset Detecting undefined instructions and generating an exception Dynamic expansion of complex instructions into a sequence of simple instructions Complex instructions are defined as ones that take more than one clock cycle to issue such as LDM STM and SWP RF Register File Shifter Pipestage The main function of the RF pipestage is to read and write to the register file unit or RFU It provides source data to EX for ALU operations MAC for multiply operations Data Cache for memory writes Coprocessor interface The ID unit decodes the instruction and specifies which registers are accessed in the RFU Based upon this information the RFU determines if it needs to stall the pipeline due to a register dependency A register dependency occurs when a previous instruction is about to modify a register val
150. mal operation The instruction causes Boundary Scan register cells associated with outputs to sample the value being driven by the application processor When the TAP controller is in the Update DR state the preload instruction occurs on the falling edge of TCK This instruction causes the transfer of data held in the Boundary Scan cells to the slave register cells Typically the slave latched data is then applied to the system outputs by means of the extest instruction dbgrx 00010 For Software Debug see Section 10 10 5 DBGRX JTAG Command on page 10 20 clamp 00100 The clamp instruction allows the state of the signals driven from the application processor pins to be determined from the boundary scan register while the Bypass register is selected as the serial path between TDI and TDO Signals driven from the application processor pins will not change while the clamp instruction is selected Idic 00111 For Software Debug see Section 10 13 1 LDIC JTAG Command on page 10 30 highz 01000 The highz instruction floats all three stateable output and in out pins Also when this instruction is active the Bypass register is connected between TDI and TDO This register can be accessed via the JTAG Test Access Port throughout the device operation Access to the Bypass register can also be obtained with the bypass instruction dcsr 01001 For Software Debug see Section 10 3 Debug Co
151. me 10 28 10 12 1 2 Non exception Message Byte nenn 10 28 10 12 1 3 Address Bytes eee cet rd nin enean bns 10 29 10 13 Downloading Code into the Instruction Cache 10 30 10 13 1 LDIC JTAG Commande 10 30 10 13 2 LDIC JTAG Data Register racinun a eai a eai aai eaaa uee 10 31 10 13 3 LDIC Cache FUNCIONS eersel AAS eR AAN aer Ia iA nnn 10 32 10 13 4 Loading IC During HReset sse 10 33 10 13 4 1 Loading IC During Cold Reset for Debug ns nseneeeennneen 10 34 10 13 4 2 Loading IC During a Warm Reset for Debug nn 10 36 10 13 5 Dynamically Loading IC After Reset usseeeeeeeeeeensseerrsserirrresrerrrsssrerrsssrrrenn 10 38 10 13 5 1 Dynamic Code Download Synchronization ssusss 10 39 10 13 6 Mini Instruction Cache Overview emm 10 40 10 14 Halt Mode Software Protocol ener nee nn 10 40 10 14 1 Starting a Debug Session ssseeesssseeeeerseeeeerrneessnnnesetstnessetenanettnnnesstnnneeennnnnne 10 40 10 14 1 1 Setting up Override Vector Tables 10 41 10 14 1 2 Placing the Handler in Memory seemm nenn 10 41 10 14 2 Implementing a Debug Handler 10 42 10 14 2 1 Debug Handler Ent 10 42 10 14 2 2 Debug Handler Restrictions seesssseeeesssersesrerrrstterrrsssrerrnssrrenna 10 42 10 14 2 3 Dynamic Debug Handler 10 43 10 14 2 4 High Speed Download 10 44 10 14 3 Ending a Debug Session nennen nn 10 45 Intel XScale Microarchitecture User s Manual vii a Contents intel
152. mum Result Latency LDM 3 23 1 3 for load data 1 for writeback of base STM 3 18 1 for writeback of base a LDM issue latency is 7 N if R15 is in the register list and 2 N if it is not STM issue latency is calculated as 2 N N is the number of registers to load or store Semaphore Instructions Table 11 13 Semaphore Instruction Timings 11 2 9 Table 11 14 CP15 Register Access Instruction Timings Table 11 15 CP14 Register Access Instruction Timings 11 2 10 Miscellaneous Instruction Timing Mnemonic Minimum Issue Latency Minimum Result Latency SWP 5 5 SWPB 5 5 Coprocessor Instructions Mnemonic Minimum Issue Latency Minimum Result Latency MRC 4 4 MCR 2 N A Mnemonic Minimum Issue Latency Minimum Result Latency MRC 7 7 MCR 7 N A LDC 10 N A STC 7 N A Table 11 16 SWI Instruction Timings Mnemonic Minimum latency to first instruction of SWI exception handler SWI Intel XScale Microarchitecture User s Manual Performance Considerations Table 11 17 Count Leading Zeros Instruction Timings 11 2 11 11 3 Mnemonic Minimum Issue Latency Minimum Result Latency CLZ 1 1 Thumb Instructions The timing of Thumb instructions are the same as their equivalent ARM instructions This mapping can be found in the ARM Architecture Reference Manual The only exception is the Thumb BL inst
153. n used during dynamic code download The pieces must be ordered in the handler as shown below Before the download can start all outstanding instruction fetches must complete The MCR invalidate IC by line function serves as a barrier instruction in the core All outstanding instruction fetches are guaranteed to complete before the next instruction executes NOTE1 the actual address specified to invalidate is implementation defined but must not have any harmful effects NOTE2 The placement of the invalidate code is implementation defined the only requirement is that it must be placed such that by the time the debugger starts loading the instruction cache all outstanding instruction fetches have completed HHH db db HHH H mov r5 address mcr p15 0 r5 c7 c5 1 The host waits for the debug handler to signal that it is ready for the code download This can be done using the TX register access handshaking protocol The host polls the TR bit through JTAG until it is set then begins the code download The following MCR does a write to TX automatically setting the TR bit NOTE The value written to TX is implementation defined dk dk db db dbod mcr p14 0 r6 c8 CO O The debug handler waits until the download is complete before continuing The debugger uses the RX handshaking to signal the debug handler when the download is complete The debug handler polls the RR bit until it is set A debugger write to RX au
154. n Halt Mode when configured for fill once mode It is possible to overflow and lose data from the trace buffer in fill once mode in Halt Mode When the trace buffer fills up it has space for 1 indirect branch message 5 bytes and 1 exception message 1 byte If the trace buffer fills up with an indirect branch message and generates a trace buffer full break at the same time as a data abort occurs the data abort has higher priority so the processor first goes to the data abort handler This data abort is placed into the trace buffer without losing any data However if another imprecise data abort is detected at the start of the data abort handler it will have higher priority than the trace buffer full break so the processor will go back to the data abort handler This 2nd data abort also gets written into the trace buffer This causes the trace buffer to wrap around and one trace buffer entry is lost oldest entry is lost Additional trace buffer entries can be lost if imprecise data aborts continue to be detected before the processor can handle the trace buffer full break which will turn off the trace buffer This trace buffer overflow problem can be avoided by enabling vector traps on data aborts 5 The TXRXCTRL OV bit overflow flag does not get set during high speed download when the handler reads the RX register at the same time the debugger writes to it If the debugger writes to RX at the same time the handler reads from RX the
155. n would stall for 1 cycle due to a 2 cycle result latency These stalls can be avoided by rearranging the code as follows miaph accO r3 r4 add rb BD Ya miaph accO r5 r6 sub r8 r3 r4 mra r6 r7 accO A 5 7 Scheduling MRS and MSR Instructions The MRS instruction has an issue latency of 1 cycle and a result latency of 2 cycles The MSR instruction has an issue latency of 2 cycles 6 if updating the mode bits and a result latency of 1 cycle A 30 Intel XScale Microarchitecture User s Manual intel A 5 8 A 6 A 6 1 A 6 2 Intel XScale Microarchitecture User s Manual Optimization Guide Consider the code sample mrs CU cpsr orr r0 ro 1 add rl r2 r3 The ORR instruction above would incur a 1 cycle stall due to the 2 cycle result latency of the MRS instruction In the code example above the ADD instruction can be moved before the ORR instruction to prevent this stall Scheduling Coprocessor Instructions The MRC instruction has an issue latency of 1 cycle and a result latency of 3 cycles The MCR instruction has an issue latency of 1 cycle Consider the code sample add rl r2 r3 mrc pis 0 r7 Cl CO 0 mov r0 x7 add fi rl SI The MOV instruction above would incur a 2 cycle latency due to the 3 cycle result latency of the MRC instruction The code shown above can be rearranged as follows to avoid these stalls mrc pis 0 r7 C1 CO 0 add rl r2 r3 add ri x1 1 mov T0 r
156. nd the performance monitoring control register are accessible through Coprocessor 14 CP14 registers 0 3 Refer to Section 7 3 1 Registers 0 3 Performance Monitoring on page 7 16 for more details on accessing these registers with MRC MCR LDC and STC coprocessor instructions Access is allowed in privileged mode only Clock Counter CCNT CP14 Register 1 The format of CCNT is shown in Table 8 1 The clock counter is reset to 0 by Performance Monitor Control Register PMNC or can be set to a predetermined value by directly writing to it It counts core clock cycles When CCNT reaches its maximum value OxFFFF_FFFF the next clock cycle will cause it to roll over to zero and set the overflow flag bit 10 in PMNC An IRQ or FIQ will be reported if it is enabled via bit 6 in the PMNC register The CCNT register continues running in DEBUG mode yet will become unpredictable if the Power Mode register see Section 7 3 2 Registers 6 7 Clock and Power Management on page 7 16 1s written as non ACTIVE Intel XScale Microarchitecture User s Manual 8 1 Performance Monitoring n ii Table 8 1 Clock Count Register CCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Clock Counter reset value unpredictable Bits Access Description 32 bit clock counter Reset to 0 by PMNC register 31 0 Read Write When the clock counter reaches its maximum value OxFFFF FFFF the nex
157. ndler code to within 32 MB of the reset vector or an indirect branch with a data processing instruction The data processing instruction creates an address using immediate operands and then branches to the target An LDR to the PC does not work because the debugger cannot set up data in memory before starting the debug handler The 2 way set associative limitation 1s due to the fact that when the override default and relocated vector tables are downloaded they take up both ways of Set 0 w addresses 0x0 and OxFFFF 0000 Therefore debug handler code cannot be downloaded to an address that maps into Set 0 otherwise it will overwrite one of the vector tables avoid addresses w lower 12 bits 0 The instruction cache 2 way set limitation is not a problem when the reset vector uses a direct branch since the branch offset can be adjusted accordingly However it makes using indirect branches more complicated Now the reset vector actually needs multiple data processing instructions to create the target address and branch to it One possibility is to set up vector traps on the non reset exception vectors These vector locations can then be used to extend the reset vector Intel XScale Microarchitecture User s Manual 10 41 Software Debug I ntel i 10 14 2 10 14 2 1 10 14 2 2 10 42 Another solution is to have the reset vector do a direct branch to some intermediate code This intermediate code can then use several instruct
158. ng a write to RX The debugger polls DBG RR to determine when the handler has read the previous data from RX The debugger sets TXRXCTRL 31 by setting the DBG V bit DBG V The debugger sets this bit to indicate the data scanned into DBG_SR 34 3 is valid data to write to RX DBG V is an input to the RX Write Logic and is also cleared by the RX Write Logic When this bit is set the data scanned into the DBG_SR will be written to RX following an Update DR If DBG V is not set and the debugger does an Update DR RX will be unchanged This bit does not affect the actions of DBG FLUSH or DBGD DBG RX DBGRX is written into the RX register based on the output of the RX Write Logic Any data that needs to be sent from the debugger to the processor must be loaded into DBG RX with DBG V set to 1 DBG RX is loaded from DBG_SR 34 3 when the JTAG enters the Update DR state Intel XScale Microarchitecture User s Manual intel 10 10 6 6 10 10 6 7 10 10 7 Software Debug DBGRX is written to RX following an Update DR when the RX Write Logic enables the RX register DBG D DBG D is provided for use during high speed download This bit is written directly to TXRXCTRL 29 The debugger sets DBG D when downloading a block of code or data to the Intel XScale core system memory The debug handler then uses TXRXCTRL 29 as a branch flag to determine the end of the loop Using DBG D as a branch flags eliminates the need for a loop
159. ng enabling the MMU has no effect on the contents of either TLB valid entries stay valid locked items remain locked To invalidate the TLBs the commands below are required All operations defined in Table 7 13 work regardless of whether the cache is enabled or disabled This register is write only Reads from this register as with an MRC have an undefined effect Intel XScale Microarchitecture User s Manual n Configuration Table 7 13 TLB Functions Function opcode 2 CRm Data Instruction Invalidate I amp D TLB 0b000 0b0111 Ignored MCR p15 0 Rd c8 c7 0 Invalidate TLB 0b000 0b0101 Ignored MCR p15 0 Rd c8 c5 0 Invalidate TLB entry 0b001 0b0101 MVA MCR p15 0 Rd c8 c5 1 Invalidate D TLB 0b000 0b0110 Ignored MCR p15 0 Rd c8 c6 0 Invalidate D TLB entry 0b001 0b0110 MVA MCR p15 0 Rd c8 c6 1 7 2 9 Register 9 Cache Lock Down Register 9 is used for locking down entries into the instruction cache and data cache The protocol for locking down entries can be found in Chapter 6 Data Cache Data can not be locked into the mini data cache Table 7 14 shows the command for locking down entries in the instruction cache instruction TLB and data TLB The cache entry to lock is specified by the virtual address in Rd The data cache locking mechanism follows a different procedure than the instruction cache The data cache is placed in lock down mode such that all sub
160. nough the debugger may overwrite the previous data before the handler can read it The logic sets the overflow flag when the previous data has not been read yet and the debugger has just written new data to RX Figure 10 4 RX Write Logic DBG REG 34 Latch gt Clear DBG REG 34 Y ie RX write enable Latch Set TXRXCTRL 31 Set overflow flag TXRXCTRL 31 TXRXCTRL 30 10 10 6 2 DBGRX Data Register Core CLK The bits in the DBGRX data register Figure 10 5 are used by the debugger to send data to the processor The data register also contains a bit to flush previously written data and a high speed download flag Intel XScale Microarchitecture User s Manual 10 21 Software Debug I ntel i Figure 10 5 DBGRX Data Register 10 10 6 3 10 10 6 4 10 10 6 5 10 22 RX TXRXCTRL 31 0 0 1 Capture_DR 1 1 DBG_SR TDI 1 35 34 3 1 3 1 1 0 gt TDO L DBGRR cleared by RX Write Logic Update DR Lo DBG_REG 34133 2 10 TCK DBG FLUSH DBGD DBGRX DBGV DBG RR The debugger uses DBG RR as part of the synchronization that occurs between the debugger and debug handler for accessing RX This bit contains the value of TXRXCTRL 31 after a Capture DR The debug handler automatically sets TXRXCTRL 31 by doi
161. ntrol and Status Register DCSR on page 10 3 dbgtx 10000 For Software Debug see Section 10 10 3 DBGTX JTAG Command on page 10 19 idcode IEEE 1149 1 Optional 11110 The idcode instruction is used in conjunction with the device identification register It connects the identification register between TDI and TDO in the Shift_DR state When selected idcode parallel loads the hard wired identification code 32 bits on TDO into the identification register on the rising edge of TCK in the Capture_DR state Note The device identification register is not altered by data being shifted in on TDI bypass IEEE 1149 1 Required 111115 The bypass instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR state effectively bypassing the processor s test logic 0 is captured in the CAPTURE DR state While this instruction is in effect all other test data registers have no effect on the operation of the system Test data registers with both test and system functionality perform their system functions when this instruction is selected Intel XScale Microarchitecture User s Manual intel 9 4 9 4 1 9 4 2 Test Test Data Registers The Test Data Registers are Bypass Register Boundary Scan Register Device Identification ID Code Register Data Specific Registers Bypass Register The Bypass register is a single bit register that 1s selected as the p
162. nts the number of data TLB table walks which occur when there is a TLB miss If the data TLB is disabled PMNI will not increment The statistic derived from these two events is Data TLB miss rate This is derived by dividing PMN1 by PMNO Multiple Performance Monitoring Run Statistics Even though only two events can be monitored at any given time multiple performance monitoring runs can be done capturing different events from different modes For example the first run could monitor the number of writeback operations PMN1 of mode Stall Writeback and the second run could monitor the total number of data cache accesses PMNO of mode Data Cache Efficiency From the results a percentage of writeback operations to the total number of data accesses can be derived Examples In this example the events selected with the Instruction Cache Efficiency mode are monitored and CCNT is used to measure total execution time Sampling time ends when PMNO overflows which will generate an IRQ interrupt Intel XScale Microarchitecture User s Manual n Performance Monitoring Example 8 1 Configuring the Performance Monitor Configure PMNC for instruction cache efficiency evtCount0 7 evtCountl 0 flag 0x7 to clear outstanding overflows inten 0x7set all counters to trigger an interrupt on overflow C 1 reset CCNT register H P 1 reset PMNO and PMN1 registers E 1 enable counting MOV RO 0x7777 MCR P14 0 R0 C0 c0 0
163. number of iterations to prefetch ahead is referred to as the prefetch scheduling distance Intel XScale Microarchitecture User s Manual A 4 4 3 A 4 4 4 A 4 4 5 Optimization Guide It is not always advantageous to add prefetch to a loop Loop characteristics that limit the use value of prefetch are discussed below Compute vs Data Bus Bound At the extreme a loop which is data bus bound will not benefit from prefetch because all the system resources to transfer data are quickly allocated and there are no instructions that can profitably be executed On the other end of the scale compute bound loops allow complete hiding of all data transfer latencies Low Number of Iterations Loops with very low iteration counts may have the advantages of prefetch completely mitigated A loop with a small fixed number of iterations may be faster if the loop is completely unrolled rather than trying to schedule prefetch instructions Bandwidth Limitations Overuse of prefetches can usurp resources and degrade performance This happens because once the bus traffic requests exceed the system resource capacity the processor stalls The Intel XScale core data transfer resources are 4 fill buffers 4 pending buffers 8 half cache line write buffer SDRAM resources are typically 1 4 memory banks 1 page buffer per bank referencing a 4K address range 4 transfer request buffers Consider how these resources work together A fill
164. ode the processor takes the following actions disables the trace buffer sets DCSR moe encoding processor enters a Special Debug State SDS for data breakpoints trace buffer full break and external debug break R14 dbg PC of the next instruction to execute 4 for instruction breakpoints and software breakpoints and vector traps R14 dbg PC of the aborted instruction 4 e SPSR dbg CPSR Intel XScale Microarchitecture User s Manual intel 10 4 2 Software Debug CPSR 4 0 0610101 DEBUG mode e CPSR S 0 e CPSR 6 1 e CPSR 7 1 e PC 0x0 Following a debug exception the processor switches to debug mode and enters SDS which allows the following special functionality All events are disabled SWI or undefined instructions have unpredictable results The processor ignores pre fetch aborts FIQ and IRQ SDS disables FIQ and IRQ regardless of the enable values in the CPSR The processor reports data aborts detected during SDS by setting the Sticky Abort bit in the DCSR but does not generate an exception processor also sets up FSR and FAR as it normally would for a data abort Normally during halt mode software cannot write the hardware breakpoint registers or the DCSR However during the SDS software has write access to the breakpoint registers see Section 10 HW Breakpoint Resources and the DCSR see Table 10 3 Debug Control and Status Register DCSR on page 10 3 Th
165. ode to lock is very application dependent and requires experimentation to optimize Intel XScale Microarchitecture User s Manual A 13 E Optimization Guide ntel A 4 2 A 4 2 1 A 4 2 2 A 14 Code placed into the instruction cache should be aligned on a 1024 byte boundary and placed sequentially together as tightly as possible so as not to waste precious memory space Making the code sequential also insures even distribution across all cache ways Though it is possible to choose randomly located functions for cache locking this approach runs the risk of landing multiple cache ways in one set and few or none in another set This distribution unevenness can lead to excessive thrashing of the Data and Mini Caches Data and Mini Cache The Intel XScale core allows the user to define memory regions whose cache policies can be set by the user see Section 6 2 3 Cache Policies Supported policies and configurations are Non Cacheable with no coalescing of memory writes Non Cacheable with coalescing of memory writes Mini Data cache with write coalescing read allocate and write back caching Mini Data cache with write coalescing read allocate and write through caching Mini Data cache with write coalescing read write allocate and write back caching Data cache with write coalescing read allocate and write back caching Data cache with write coalescing read allocate and write through caching
166. ollowing table shows the cache functions supported through JTAG Table 10 20 LDIC Cache Functions 10 32 Arguments Function Encoding Address Data Words Invalidate IC Line 0b000 VA of line to invalidate 0 Invalidate Mini IC 0b001 0 Load Main IC 0b010 VA of line to load 8 Load Mini IC 0b011 VA of line to load 8 RESERVED 0b100 0b111 Invalidate IC line invalidates the line in the instruction cache containing specified virtual address If the line is not in the cache the operation has no effect It does not take any data arguments Invalidate Mini IC will invalidate the entire mini instruction cache It does not effect the main instruction cache It does not require a virtual address or any data arguments Load Main IC and Load Mini IC write one line of data 8 ARM instructions into the specified instruction cache at the specified virtual address The LDIC Invalidate Mini I Cache function does not invalidate the BTB like the CP15 Invalidate IC function so software must do this manually where appropriate Intel XScale Microarchitecture User s Manual i ntel Software Debug Each cache function is downloaded through JTAG in 33 bit packets Figure 10 10 shows the packet formats for each of the JTAG cache functions Invalidate IC Line and Invalidate Mini IC each require 1 packet Load Main IC and Load Mini IC each require 9 packets Figure 10 10 Format of LDIC Cache Functions
167. on Cache LDIC State Machine The data loaded into LDIC_SR1 during a Capture DR is unpredictable All LDIC functions and data consists of 33 bit packets which are scanned into LDIC SRI during the Shift DR state Update DR parallel loads LDIC SR1 into LDIC REG which is then synchronized with the Intel XScale core clock and loaded into the LDIC_SR2 Once data is loaded into LDIC SR2 the LDIC State Machine turns on and serially shifts the contents if LDIC_SR2 to the instruction cache Note There is a delay from the time ofthe Update DR to the time the entire contents of LDIC_SR2 have been shifted to the instruction cache Removing the LDIC JTAG instruction from the JTAG IR before the entire contents of LDIC_SR2 are sent to the instruction cache will cause unpredictable behavior Therefore following the Update DR for the last LDIC packet the LDIC instruction must Intel XScale Microarchitecture User s Manual 10 31 Software Debug I ntel ii 10 13 3 remain in the JTAG IR for a minimum of 15 TCKs This ensures the last packet is correctly sent to the instruction cache LDIC Cache Functions The Intel XScale core supports four cache functions that can be executed through JTAG Two functions allow an external host to download code into the main instruction cache or the mini instruction cache through JTAG Two additional functions are supported to allow lines to be invalidated in the instruction cache The f
168. on retains its previous value during this state The instruction does not change and the instruction register retains its state Update IR State The instruction shifted into the instruction register is latched onto the parallel output from the shift register path on the falling edge of TCK Once latched the new instruction becomes the current instruction Test data registers selected by the current instruction retain their previous values Intel XScale Microarchitecture User s Manual j ntel Test If TMS is held high on the rising edge of TCK the controller enters the Select DR Scan state If TMS is held low on the rising edge of TCK the controller enters the Run Test Idle state Intel XScale Microarchitecture User s Manual 9 13 Test 9 14 Intel XScale Microarchitecture User s Manual intel Software Debug 10 10 1 10 1 1 This chapter describes the software debug and related features implemented in the Intel XScale core namely debug modes registers and exceptions aserial debug communication link via the JTAG interface atrace buffer amini Instruction Cache amechanism to load the instruction cache through JTAG Debug Handler software issues Introduction Two key terms that require clear definition in debugging are the differences between the host and target ends of a debugging scenario The following text in this chapter refers to a debugger and a debug handler The debugge
169. or instruction TLB miss This event means that the processor core is stalled PMNI counts the number of instruction fetch requests to external memory Each of these requests loads 32 bytes at a time This is the same event as measured in instruction cache efficiency mode and is included in this mode for convenience so that only one performance monitoring run is need Statistics derived from these two events The average number of cycles the processor stalled waiting for an instruction fetch from external memory to return This is calculated by dividing PMNO by PMNI If the average is high then the Intel amp XScaleTM core may be starved of memory access due to other bus traffic The percentage of total execution cycles the processor stalled waiting on an instruction fetch from external memory to return This is calculated by dividing PMNO by CCNT which was used to measure total execution time Data Bus Request Buffer Full Mode The Data Cache has buffers available to service cache misses or uncacheable accesses For every memory request that the Data Cache receives from the processor core a buffer is speculatively allocated in case an external memory request is required or temporary storage is needed for an unaligned access If no buffers are available the Data Cache will stall the processor core How often the Data Cache stalls depends on the performance of the bus external to the Intel amp XScaleTM core the internal bus inside the appli
170. ore information Memory Management The Intel XScale core implements the Memory Management Unit MMU Architecture specified in the ARM Architecture Reference Manual The MMU provides access protection and virtual to physical address translation The MMU Architecture also specifies the caching policies for the instruction cache and data cache These policies are specified as page attributes and include 1 3 Introduction 1 2 2 3 1 2 2 4 1 2 2 5 1 2 2 6 identifying code as cacheable or non cacheable selecting between the mini data cache or data cache write back or write through data caching enabling data write allocation policy enabling the write buffer to coalesce stores to external memory Refer to Chapter 3 Memory Management for more information Instruction Cache The Intel XScale core implements a 32 Kbyte 32 way set associative instruction cache with a line size of 32 bytes All requests that miss the instruction cache generate a 32 byte read request to external memory A mechanism to lock critical code within the cache is also provided Refer to Chapter 4 Instruction Cache for more information In addition to the main instruction cache there is a 2 Kbyte mini instruction cache dedicated to advanced debugging features Refer to Chapter 10 Software Debug for more information Branch Target Buffer The Intel XScale core provides a Branch Target Buffer BTB to predi
171. ormance Monitoring HReoieterg AAA 7 16 1223PWRMODE Register ae 7 17 7 24 CCEKCFG Register 6 nicotina s 7 17 7 25 Clock and Power Management valid operations ooooooccconnnnoccccccnnncanccncnononnnncncnnnnncncnnnanannnncnnnns 7 17 7 26 Accessing the Debug Register 7 18 8 1 Clock Count Register CONT sesser suinka sandarai arean ia nennen Eee nennen nennen nnne enne nennen 8 2 8 2 Performance Monitor Count Register PMNO and DMNT een 8 2 8 3 Performance Monitor Control Register CP14 register UO 8 3 8 4 Performance Monitoring Events ooccccccnnoccccnnnacocccccananoncccnannnnnnnn nano nennen nennen enne enne 8 4 8 5 Some Common Uses of the PM 8 5 9 1 TAP Controller Pin Definitions esseen enne ne nennen tnn nnn nth nnns th nnns 9 2 9 2 JTAG Instruction Code 9 4 9 3 JTAG Instruction Descripiions enmt nnn nens aaae ea senis 9 4 10 1 Coprocessor 15 Debug HRegisiers eee arranco nn nn enne nnns 10 2 10 2 Coprocessor 14 Debug HRegisiers nennen meer 10 2 10 3 Debug Control and Status Register DCH 10 3 10 4 Event Priority aset aic a zu Hee ei Eu Lee eU a i aii 10 6 10 5 Instruction Breakpoint Address and Control Register BCHST 10 9 10 6 Data Breakpoint Register ODDBRx enne nennen nennen nnne nnns 10 9 10 7 Data Breakpoint Controls Register DBCON emen 10 10 10 8 TX RX Control Register TXRXCTRL essen nennen nennen nennen 10 12 10 9 Normal RX Handebhaking essen nennen nennen nennen nennen rnnt 10 12 10 10High
172. performance enhancements added Features Figure 1 1 shows the major functional blocks of the Intel amp XScaleTM core The following sections give a brief high level overview of these blocks Figure 1 1 Intel amp XScale Microarchitecture Architecture Features 1 2 2 1 1 2 2 2 Intel XScale Microarchitecture User s Manual Instruction Micro Data Cache Mini Data Cache Processor e 32 Kbytes Cache 32 Kbytes 7 Stage ays 2 Kbytes 32 Ways pipeline WR Back or Data Ram 2 Ways Lockable by line WR Through Max 28 Kbytes Hit under miss Re Map of data cache Branch Target IMMU DMMU Fill Buffer Buffer 32 entry TLB 32 entry TLB 4 8 entries Fully associative Fully associative 12B Entries Lockable by entry Lockable by entry Performance Monitoring Power MAC Write Buffer Mgnt Single cycle through E piden D B Ctrl put 16 32 ull coalescing wei TOT 16 bit SIMD ardware breakpoints 40 bit lat Branch History Table ER JTAG Multiply Accumulate MAC The MAC unit supports early termination of multiplies accumulates in two cycles and can sustain a throughput of a MAC operation every cycle Several architectural enhancements were made to the MAC to support audio coding algorithms which include a 40 bit accumulator and support for 16 bit packed data Refer to Section 2 3 Extensions to ARM Architecture on page 2 2 for m
173. ply Instruction Timings Sheet 1 of 2 Performance Considerations Mnemonic Rs Value S Bit Minimum Minimum Result Minimum Resource Early Termination Value Issue Latency Latency Latency Throughput Rs 31 15 0x00000 0 1 2 1 or Rs 31 15 OX1FFFF 1 2 2 2 Rs 31 27 0x00 0 1 3 2 MLA or Rs 31 27 0x1F 1 3 3 3 0 1 4 3 all others 1 4 4 4 Rs 31 15 0x00000 0 1 2 1 or Rs 31 15 0Ox1FFFF 1 2 2 2 Rs 31 27 0x00 0 1 3 2 MUL or Rs 31 27 Ox1F 1 3 3 3 0 1 4 3 all others 1 4 4 4 Rs 31 15 0x00000 0 2 RdLo 2 RdHi 3 2 or Rs 31 15 Ox1FFFF 1 3 3 3 Rs 31 27 0x00 0 2 RdLo 3 RdHi 4 3 SMLAL or Rs 31 27 Ox1F 1 4 4 4 0 2 RdLo 4 RdHi 5 4 all others 1 5 5 5 SMLALxy N A N A 2 RdLo 2 RdHi 3 2 SMLAWy N A N A 1 3 2 SMLAxy N A N A 1 2 1 Rs 31 15 0x00000 0 1 RdLo 2 RdHi 3 2 or Rs 31 15 OX1FFFF 1 3 3 3 Rs 31 27 0x00 0 1 RdLo 3 RdHi 4 3 SMULL or Rs 31 27 Ox1F 1 4 4 4 0 1 RdLo 4 RdHi 5 4 all others 1 5 5 5 SMULWy N A N A 1 3 2 SMULxy N A N A 1 2 1 Intel XScale Microarchitecture User s Manual Performance Considerations n ii Table 11 6 Multiply Instruction Timings Sheet 2 of 2 kenane Rs Value S Bit Minimum Minimum Result Minimum
174. preadd tdata for i 0 i lt IMAX i PREFETCH predata 16 tdata i ia tdata i ib tdata i ic tdata i id tdata il ie tdata i ie 0 In this case the prefetch address was advanced by size of half a cache line and every other prefetch instruction is ignored Further an additional register is required to track the next prefetch address Generally not aligning and sizing data will add extra computational overhead Literal Pools The Intel XScale core does not have a single instruction that can move all literals a constant or address to a register One technique to load registers with literals in the Intel amp XScaleTM core is by loading the literal from a memory location that has been initialized with the constant or address These blocks of constants are referred to as literal pools See Section A 3 Basic Optimizations for more information on how to do this It is advantageous to place all the literals together in a pool of memory known as a literal pool These data blocks are located in the text or code address space so that they can be loaded using PC relative addressing However references to the literal pool area load the data into the data cache instead of the instruction cache Therefore it is possible that the literal may be present in both the data and instruction caches resulting in waste of space For maximum efficiency the compiler should align all literal pools on cache boundaries and s
175. r is software that runs on a host system outside of the Intel XScale core The debug handler is an event handler that runs on the Intel amp XScaleTM core when a debug event occurs The Intel XScale core debug unit when used with a debugger application allows software running on an Intel XScale core target to be debugged The debug unit allows the debugger to stop program execution and re direct execution to a debug handling routine Once program execution has stopped the debugger can examine or modify processor state co processor state or memory The debugger can then restart execution of the application The external debug interface to the PXA255 processor is via the JTAG port Further details on the JTAG interface can be found in Section 9 Test On the Intel XScale core one of two debug modes can be entered Halt mode Monitor mode Halt Mode When the debug unit is configured for halt mode the reset vector is overloaded to serve as the debug vector A new processor mode DEBUG mode CPSR 4 0 0x15 is added to allow debug exceptions to be handled similarly to other types of ARM exceptions When a debug exception occurs the processor switches to debug mode and redirects execution to a debug handler via the reset vector After the debug handler begins execution the debugger can communicate with the debug handler to examine or alter processor state or memory through the JTAG interface Intel XSc
176. r to take the data Intel XScale Microarchitecture User s Manual 10 13 Software Debug I ntel i 10 7 4 The download flag becomes especially useful when an overflow occurs If a loop counter is used and an overflow occurs the debug handler cannot determine how many data words overflowed Therefore the debug handler counter may get out of sync with the debugger the debugger may finish downloading the data but the debug handler counter may indicate there is more data to be downloaded this results in unpredictable behavior of the debug handler TX Register Ready Bit TR The debugger and debug handler use the TR bit to synchronize accesses to the TX register The debugger and debug handler must poll the TR bit before accessing the TX register Table 10 11 shows the handshaking used to access the TX register Table 10 11 TX Handshaking 10 7 5 Debugger Actions Debugger is expecting data from the debug handler Before reading data from the TX register the debugger polls the TR bit through JTAG until the bit is set NOTE while polling TR the debugger must scan out the TR bit and the TX register data Reading a 1 from the TR bit indicates that the TX data scanned out is valid The action of scanning out data when the TR bit is set automatically clears TR Debug Handler Actions Debug handler wants to send data to the debugger in response to a previous request The debug handler polls the TR bit to det
177. rap bits in Table 10 3 writing a one enables the trap behavior while writing a zero will disable the trap 7 6 5 43 2 1 0 r Reset TRST Bits Access Description Value Value Global Enable GE 0 h d 31 Software Read Write ie al Fnable GE HORAM JTAG Read Only 0 disables all debug functionality 1 enables all debug functionality Halt Mode H unchanged 0 30 Software Read Only JTAG Read Write Ooi Mode 1 Halt Mode 29 24 Read undefined Write As Zero Reserved undefined undefined Software Read Only unchanged 0 23 JTAG Read Write Trap FIQ TF Software Read Only unchanged 0 22 STAG Read Write TS 21 Read undefined Write As Zero Reserved undefined undefined Software Read Only unchanged 0 20 JTAG Read Write Trap Data Abort TD Software Read Only unchanged 0 19 JTAG Read Write Trap Prefetch Abort TA Software Read Only unchanged 0 18 JTAG Read Write Trap Software Interrupt TS Software Read Onl unchanged 0 17 JTAG Read wo Trap Undefined Instruction TU 9 Software Read Only unchanged 0 16 STAG Read Write Trap Reset TR Intel XScale Microarchitecture User s Manual 10 3 Software Debug n Table 10 3 Debug Control and Status Register DCSR Sheet 2 of 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O Reset TRST Bits Access Description Value Value 15 6
178. re Debug n data address mask second data address breakpoint The DBCON register controls the functionality of DBRI as well as the enables for both DBRs DBCON also controls what type of memory access to break on Table 10 7 Data Breakpoint Controls Register DBCON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 54 3 21 0 ACEEEO I BI Te reset value 0x0000_0000 Bits Access Description 31 9 Read as Zero Write ignored Reserved DBR1 Mode M 8 Read Write 0 DBR1 Data Address Breakpoint 1 DBR1 Data Address Mask 7 4 Read as Zero Write ignored Reserved DBR1 Enable E1 When DBR1 Data Address Breakpoint 0b00 DBR1 disabled 3 2 Read Write 0b01 DBR1 enabled Store only 0b10 DBR1 enabled Any data access load or store 0b11 DBR1 enabled Load only When DBR1 Data Address Mask this field has no effect DBRO Enable E0 0b00 DBRO disabled 1 0 Read Write 0b01 DBRO enabled Store only 0b10 DBRO enabled Any data access load or store 0b11 DBRO enabled Load only When DBRI is programmed as a data address mask it is used in conjunction with the address in DBRO The bits set in DBRI are ignored by the processor when comparing the address of a memory access with the address in DBRO Using DBRI as a data address mask allows a range of addresses to generate a data breakpoint When DBR1 is selected as a data address mask it is un
179. rmance counters to 0x0 Enable E 0 Read Write 0 all 3 counters are disabled 1 all 3 counters are enabled Managing the PMNC An interrupt will be reported when a counter s overflow flag is set and its associated interrupt enable bit is set in the PMNC register The interrupt will remain asserted until software clears the overflow flag by writing a one to the flag that is set Note that the PX A255 processor Interrupt Controller and the CPSR interrupt bit must be enabled in order for software to receive the interrupt The PMCR registers continue running in DEBUG mode yet will become unpredictable if the Power Mode register see Section 7 3 2 Registers 6 7 Clock and Power Management on page 7 16 is written as non ACTIVE The counters continue to record events even after they overflow Performance Monitoring Events Table 8 4 lists events that may be monitored by the PMU Each of the Performance Monitor Count Registers PMNO and PMN1 can count any listed event Software selects which event is counted by each PMNx register by programming the evtCountx fields of the PMNC register Table 8 4 Performance Monitoring Events Sheet 1 of 2 Event Number evtCount0 or Event Definition evtCount1 0x0 Instruction cache miss requires fetch from external memory 0x1 Instruction cache cannot deliver an instruction This could indicate an Cache miss or an ITLB miss This event will occur every cycle
180. ruction when H 0 the timing in this case would be the same as an ARM data processing instruction Interrupt Latency Minimum Interrupt Latency is defined as the minimum number of cycles from the assertion of any interrupt signal IRQ or FIQ to the execution of the instruction at the vector for that interrupt An active system responding to an interrupt will typically depend predominantly on the PXA255 processor s internal amp external bus activity Assuming best case conditions exist when the interrupt is asserted e g the system isn t waiting on the completion of some other operation the core will recognize an interrupt approximately 6 core clock cycles after the application processors interrupt controller detects an interrupt A sometimes more useful concept to work with is the Maximum Interrupt Latency This is typically a complex calculation that depends on what else is going on in the system at the time the interrupt is asserted Some examples that can adversely affect interrupt latency are the instruction currently executing could be a 16 register LDM the processor could fault just when the interrupt arrives the processor could be waiting for data from a load doing a page table walk etc and high core to system bus clock ratios Maximum Interrupt Latency can be reduced by ensuring that the interrupt vector and interrupt service routine are resident in the instruction cache This can be accomplished by lockin
181. s Mnemonic Minimum Issue Latency Minimum Result Latency QADD 1 2 QSUB 1 2 QDADD 1 2 QDSUB 1 2 11 2 6 Status Register Access Instructions Table 11 10 Status Register Access Instruction Timings Mnemonic Minimum Issue Latency Minimum Result Latency MRS 1 MSR 2 6 if updating mode bits 11 2 7 Load Store Instructions Table 11 11 Load and Store Instruction Timings Mnemonic Minimum Issue Latency Minimum Result Latency LDR 1 3 for load data 1 for writeback of base LDRB 1 3 for load data 1 for writeback of base LDRBT 1 3 for load data 1 for writeback of base LDRD 1 1 if Rd is R12 3 for Rd 4 for Rd 1 2 for writeback of base LDRH 1 3 for load data 1 for writeback of base LDRSB 1 3 for load data 1 for writeback of base LDRSH 1 3 for load data 1 for writeback of base LDRT 3 for load data 1 for writeback of base PLD N A STR 1 for writeback of base STRB 1 for writeback of base STRBT 1 for writeback of base STRD 1 for writeback of base STRH 1 for writeback of base STRT 1 for writeback of base Intel XScale Microarchitecture User s Manual Performance Considerations Table 11 12 Load and Store Multiple Instruction Timings 11 2 8 In Mnemonic Minimum Issue Latency Mini
182. s an example of rearranging often written arrays to sections in a structure consider the code sample struct employee struct employee prev struct employee next float Year2DatePay float Year2DateTax int ssno int empid float Year2Date401KDed float Year2DateOtherDed In the data structure shown above the fields Year2DatePay Year2DateTax Year2Date401K Ded and Year2DateOtherDed are likely to change with each pay check The remaining fields however change very rarely If the fields are laid out as shown above assuming that the structure is aligned Intel XScale Microarchitecture User s Manual A 4 4 7 A 4 4 8 Optimization Guide on a 32 byte boundary modifications to the Year2Date fields is likely to use two write buffers when the data is written out to memory However we can restrict the number of write buffers that are commonly used to 1 by rearranging the fields in the above data structure as shown below struct employee struct employee prev struct employee next int ssno int empid float Year2DatePay float Year2DateTax float Year2Date401KDed float Year2DateOtherDed Cache Blocking Cache blocking techniques such as strip mining are used to improve temporal locality of the data Given a large data set that can be reused across multiple passes of a loop data blocking divides the data into smaller chunks which can be loaded into the cache during the first loop and then b
183. s latency the instruction following the SWP SWPB instruction would stall for 4 cycles SWP and SWPB instructions should therefore be used only where absolutely needed For example the following code may be used to swap the contents of 2 memory locations Swap the contents of memory locations pointed to by r0 and r1 ldr r2 r0 swp r2 ri str r2 rt The code above takes 9 cycles to complete The rewritten code below takes 6 cycles to execute assuming the availability of r3 Swap the contents of memory locations pointed to by r0 and r1 ldr r2 0 ldr r3 1 str r2 el str r3 r0 Scheduling the MRA and MAR Instructions MRRC MCRR The MRA MRRC instruction has an issue latency of 1 cycle a result latency of 2 or 3 cycles depending on the destination register value being accessed and a resource latency of 2 cycles Consider the code sample mra r6 r7 accO mra r8 r9 acco add rl rl 1 The code shown above would incur a 1 cycle stall due to the 2 cycle resource latency of an MRA instruction The code can be rearranged as shown below to prevent this stall mra r6 r7 accO add rl rl 1 mra r8 r9 accO Similarly the code shown below would incur a 2 cycle penalty due to the 3 cycle result latency for the second destination register mra r6 r7 accO mov rl x7 mov rO r6 add r2 r2 1 Intel XScale Microarchitecture User s Manual A 29 E Optimization Guide ntel The stalls
184. s rearrangement care should be taken to ensure that the rearranged sequence of instructions has the same effect as the original sequence of instructions Scheduling Loads On the Intel XScale core an LDR instruction has a result latency of 3 cycles assuming the data being loaded is in the data cache If the instruction after the LDR needs to use the result ofthe load then it would stall for 2 cycles If possible the instructions surrounding the LDR instruction should be rearranged to avoid this stall Consider the following example add EX x3 ldr r0 r5 add r6 rO rl sub r8 r2 r3 mul r9 r2 ES In the code shown above the ADD instruction following the LDR would stall for 2 cycles because it uses the result of the load The code can be rearranged as follows to prevent the stalls ldr ro r5 add ri x25 X3 sub r8 r2 r3 add r6 YO ri mul r9 r2 r3 Note that this rearrangement may not be always possible Consider the following example cmp rl 0 addne r4 r5 4 subeq r4 r5 4 ldr ro r4 cmp ro 10 Intel XScale Microarchitecture User s Manual Optimization Guide In the example above the LDR instruction cannot be moved before the ADDNE or the SUBEQ instructions because the LDR instruction depends on the result of these instructions Noting the conditional behavior one could rewrite the above code to make it run faster at the expense of increasing code size cmp rl 0 ldrne r0 r5 4 ldr
185. s that 0 instructions executed since the last control flow change and the current exception For example if a branch is immediate followed by a SWI a direct branch exception message for the branch is followed by an exception message for the SWI in the trace buffer The count value in the exception message will be 0 meaning that 0 instructions executed after the last control flow change the branch and before the current control flow change the SWI Instead of the SWI if an IRQ was handled immediately after the branch before any other instructions executed the count would still be 0 since no instructions executed after the branch and before the interrupt was handled A count of 0b1111 indicates that 15 instructions executed between the last branch and the exception In this case an exception was either caused by the 16th instruction if it is an undefined instruction exception pre fetch abort or SWI or handled before the 16th instruction executed for FIQ IRQ or data abort Non exception Message Byte Non exception message bytes are used for direct branches indirect branches and rollovers In a non exception message byte the 4 bit message type field MMMM specifies the type of message refer to Table 10 19 Intel XScale Microarchitecture User s Manual Software Debug The incremental word count CCCC is the instruction count since the last control flow change excluding the current branch The instruction count in
186. se an undefined instruction trap The CRn field specifies the number of the register to access The CRm opcode 1 and opcode 2 fields are not used and must be set to 0 Table 10 2 Coprocessor 14 Debug Registers 10 2 Register name CRn CRm TX Register TX 8 0 RX Register RX 9 0 Debug Control and Status Register DCSR 10 0 Trace Buffer Register TBREG 11 0 Checkpoint Register 0 CHKPTO 12 0 Checkpoint Register 1 CHKPT1 13 0 TXRX Control Register TXRXCTRL 14 0 The TX and RX registers certain bits in the TXRXCTRL register and certain bits in the DCSR can be accessed by a debugger through the JTAG interface This is to allow an external debugger to have access to the internal state of the processor For the details of which bits can be accessed see Table 10 8 Table 10 12 and Table 10 3 Intel XScale Microarchitecture User s Manual Intel 10 3 Table 10 3 Debug Control and Status Register DCSR Sheet 1 of 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Software Debug Debug Control and Status Register DCSR The DCSR register is the main control register for the debug unit Table 10 3 shows the format of the register The DCSR register can be accessed in privileged modes by software running on the core or by a debugger through the JTAG interface Refer to Section 10 SELDCSR JTAG Register for details about accessing DCSR through JTAG For the T
187. sequent fills to the data cache result in that line being locked in as controlled by Table 7 15 Lock unlock operations on a disabled cache have an undefined effect This register is write only Reads from this register as with an MRC have an undefined effect Table 7 14 Cache Lockdown Functions Function opcode 2 CRm Data Instruction Fetch and Lock cache line 0b000 0b0001 MVA MCR p15 0 Rd c9 c1 0 Unlock Instruction cache 0b001 0b0001 Ignored MCR p15 0 Rd c9 c1 1 Read data cache lock register 06000 oboo10 Readlockmode MRC p15 0 Rd co c2 0 Write data cache lock register ob000 oboo10 SeWClearlock MCR p15 0 Rd c9 c2 0 Unlock Data Cache 0b001 0b0010 Ignored MCR p15 0 Rd c9 c2 1 Table 7 15 Data Cache Lock Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 43 2 1 0 LR reset value writable bits set to 0 Bits Access Description 31 1 Read unpredictable Write as Zero Reserved Data Cache Lock Mode L 0 Read unpredictable Write 0 No locking occurs ns 1 Any fill into the data cache while this bit is set gets locked in Intel XScale Microarchitecture User s Manual 7 11 Configuration 7 2 10 Register 10 TLB Lock Down intel Register 10 is used for locking down entries into the instruction TLB and data TLB The protocol for locking down entries can be found in Chapter 3 Memory
188. set state The PXA255 256 pin PBGA package boundary scan pin order is shown in Figure 9 2 on page 9 6 Figure 9 2 BSDL code for 256 MBGA package A full BSDL file for this part is available from Intel entity processor jtag is generic PHYSICAL PIN MAP port gpio scl sda usb n usb p mmdat mmcmd md pwr_en nreset_out ac reset n rdnwr sdclk_0 Sdclk 1 sdclk 2 sdcke nsdcs_0 nsdcs 1 nsdcs 2 nsdcs 3 dom 0 dom 1 dom 2 dom 3 nsdcas out out out out out out 3 out out out out out out out 3 out out out out String MBGA 256 inout bit vector 80 DOWNTO 0 inout bit inout bit inout bit inout bit inout bit inout bit inout bit vector 31 DOWNTO 0 bit bit bit bit bit bit bit bit vector 1 DOWNTO 0 bit bit bit bit bit bit bit bit bit Intel XScale Microarchitecture User s Manual 9 4 3 Test nsdras out bit nwe out bit noe out bit ncs O0 out bit ma out bit vector 25 DOWNTO 0 test in bit testclk in bit nvdd fault in bit nbatt fault in bit boot sel in bit vector 2 DOWNTO 0 nreset in bit pextal out bit textal out bit yp in bit ym in bit xp in bit xm in bit ref in bit pxtal in bit txtal in bit tms in bit tck in bit tdi in bit tdo out bit ntrst in bit Device Identification ID Code Register The Device Identi
189. set state An external source must drive this signal from low to high for TAP controller operation 9 2 Reset The boundary scan interface includes a synchronous finite state machine the TAP controller in Figure 9 1 In order to force the TAP controller into the correct state a reset pulse must be applied to the nTRST pin Note A clock on TCK is not necessary to reset the application processor To use the boundary scan interface these points apply During power up only drive nTRST from low to high either before or at the same time as nRESET During power up only wait 10 us after deassertion of nTRST before proceeding with any JTAG operation Always drive the nBATT FAULT and nVDD FAULT pins high An active low signal on either pin puts the device into sleep which powers down all JTAG circuitry The action of reset either a pulse or a dc level is System mode is selected the boundary scan chain does NOT intercept any of the signals passing between the pads and the core dcode instruction is selected If TCK is pulsed the contents of the ID register are clocked out of TDO If the boundary scan interface is not to be used then the nTRST pin may be tied permanently low or to the nRESET pin 9 2 Intel XScale Microarchitecture User s Manual 9 3 1 Test Instruction Register The instruction register IR holds instruction codes shifted through the Test Data Input TDI pin Instruction
190. struction before the SUB instruction would change the program semantics It is possible to move the ADD and the LDR instructions before the SUB instruction if we allow the contents of the register r6 to be spilled and restored from the stack as shown below all other registers are in use str r6 sp 4 add ro r4 rb ldr r6 r0 mov r2 r2 LSL 2 orr r9 r9 Host add r8 r6 r8 ldr r6 sp 4 add r8 r8 4 orr r8 r8 Host sub rl r6 r7 mul r3 Y6 X2 The value in register r6 is not used after this Intel XScale Microarchitecture User s Manual A 25 Optimization Guide ntel A 5 1 1 A 26 As can be seen above the contents of the register r6 have been spilled to the stack and subsequently loaded back to the register r6 to retain the program semantics Another way to optimize the code above is with the use of the preload instruction as shown below all other registers are in use add r0 X4 rb5 pld r0 sub rl PE r7 mul r3 r6 r2 mov r2 r2 LSL 2 orr r9 r9 0xf ldr r6 r0 add r8 r6 r8 add r8 r8 4 orr r8 r8 0xf The value in register r6 is not used after this The Intel XScale core has 4 fill buffers that are used to fetch data from external memory when a data cache miss occurs The Intel XScale core stalls when all fill buffers are in use This happens when more than 4 loads are outstanding and are being fetched from memory As a result the code written should ensur
191. t cycle will cause it to roll over to zero and generate an IRQ or FIQ if enabled 8 3 Performance Count Registers PMNO PMN1 CP14 Register 2 and 3 Respectively There are two 32 bit event counters their format is shown in Table 8 2 The event counters are reset to 0 by the PMNC register or can be set to a predetermined value by directly writing to them When an event counter reaches its maximum value OXFFFF FFFF the next event it needs to count will cause it to roll over to zero and set the overflow flag bit 8 or 9 in PMNC An IRQ or FIQ interrupt will be reported if it is enabled via bit 4 or 5 in the PMNC register Table 8 2 Performance Monitor Count Register PMNO and PMN1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 54 3 2 1 0 Event Counter reset value unpredictable Bits Access Description 32 bit event counter Reset to 0 by PMNC register When an event counter reaches its maximum value 31 0 Read Write OxFFFF_FFFF the next event it needs to count will cause it to roll over to zero and generate an IRQ interrupt if enabled 8 3 1 Extending Count Duration Beyond 32 Bits To increase the monitoring duration software can extend the count duration beyond 32 bits by counting the number of overflow interrupts each 32 bit counter generates This can be done in the interrupt service routine ISR where an increment to some memory location every time th
192. tal counter is still set to 0b1111 meaning 15 instructions executed between the last branch and the current branch Address Bytes Only indirect branch entries contain address bytes in addition to the message byte Indirect branch entries always have four address bytes indicating the target of that indirect branch When reading the trace buffer the MSB of the target address is read out first the LSB is the fourth byte read out and the indirect branch message byte is the fifth byte read out The byte organization of the indirect branch message is shown in Figure 10 8 Intel XScale Microarchitecture User s Manual 10 29 Software Debug n Figure 10 8 Indirect Branch Entry Address Byte Organization 10 13 10 13 1 target 31 24 Trace buffer is read by software in this target 23 16 direction The message byte is always the last of target 15 8 the 5 bytes in the entry target 7 0 to be read Y indirect branch message Downloading Code into the Instruction Cache On the Intel XScale core a 2K mini instruction cache physically separate from the 32K main instruction cache can be used as an on chip instruction RAM An external host can download code directly into either the mini or main instruction cache through JTAG In addition to downloading code several cache functions are supported The Intel XScale core supports loading either instruction cache during reset and during pro
193. tching Global variables that are accessed in time critical functions such as interrupt service routines The on chip RAM is created by locking a memory region into the Data cache see Section 6 4 Re configuring the Data Cache as Data RAM for more details If the data in the on chip RAM is to be initialized to zero then the locking process can be made quicker by using the CP15 prefetch zero function This function does not generate external memory references When creating the on chip RAM care must be taken to ensure that all sets in the on chip RAM area of the Data cache have approximately the same number of ways locked An uneven allocation may increase the level of thrashing in some sets while leaving other sets under utilized For example consider three arrays arrl arr2 and arr3 of size 64 bytes each that are being allocated to the on chip RAM and assume that the address of arrl is 0 address of arr2 is 1024 and the address of arr3 is 2048 All three arrays will be within the same sets i e scil and setl as a result three ways in both sets set and setl will be locked leaving 29 ways for use by other variables This can be improved by allocating on chip RAM data in sequential order In the above example allocating arr2 to address 64 and arr3 to address 128 allows the three arrays to use only 1 way in sets 0 through 5 Mini data Cache The mini data cache is best used for data structures which have short temporal lives an
194. te The instruction does not change If TMS is held high on the rising edge of TCK the controller enters the Exitl IR state If TMS is held low on the rising edge of TCK the controller remains in the Shift IR state Exit1 IR State This is a temporary state If TMS is held high on the rising edge of TCK the controller enters the Update IR state which terminates the scanning process If TMS is held low on the rising edge of TCK the controller enters the Pause IR state The test data register selected by the current instruction retains its previous value during this state The instruction does not change and the instruction register retains its state Pause IR State The Pause IR state allows the test controller to temporarily halt the shifting of data through the instruction register The test data registers selected by the current instruction retain their previous values during this state The instruction does not change and the instruction register retains its state The controller remains in this state as long as TMS is held low When TMS goes high on the rising edges of TCK the controller moves to the Exit2 IR state Exit2 IR State This is a temporary state If TMS is held high on the rising edge of TCK the controller enters the Update IR state which terminates the scanning process If TMS is held low on the rising edge of TCK the controller enters the Shift IR state This test data register selected by the current instructi
195. tel A 3 2 A 3 3 A 3 4 Optimization Guide Bit Field Manipulation The Intel XScaleTM core shift and logical operations provide a useful way of manipulating bit fields Bit field operations can be optimized as follows Set the bit number specified by r1 in register r0 mov r2 1 Orr LO r0 r2 asl ri Clear the bit number specified by r1 in register r0 mov r2 1 bic rO rO r2 asl r1 Extract the bit value of the bit number specified by r1 of the value in r0 storing the value in ro mov rl r0 asr rl and r0 ri 1 Extract the higher order 8 bits of the value in r0 storing the result in r1 mov rl rO 1sr 24 Optimizing the Use of Immediate Values The Intel amp XScaleTM core MOV or MVN instruction should be used when loading an immediate constant value into a register Please refer to the ARM Architecture Reference Manual for the set of immediate values that can be used in a MOV or MVN instruction It is also possible to generate a whole set of constant values using a combination of MOV MVN ORR BIC and ADD instructions The LDR instruction has the potential of incurring a cache miss in addition to polluting the data and instruction caches The code samples below illustrate cases when a combination of the above instructions can be used to set a register to a constant value Set the value of r0 to 127 mov rO 127 Set the value of r0 to Oxfffffefb mvn r0 260 Set the value of r0 to 257 mov rO 1
196. the debug handler as a branch flag during high speed download All of the bits in the TXRXCTRL register are placed such that they can be read directly into the CC flags in the CPSR with an MRC with Rd PC The subsequent instruction can then conditionally execute based on the updated CC value Intel XScale Microarchitecture User s Manual 10 11 Software Debug n Table 10 8 TX RX Control Register TXRXCTRL 10 7 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 reset value 0x0000 0000 Bits Access Description 31 Software Read only Write ignored RR JTAG Write only 1 RX Register Ready 2 OV 30 Software Read Write i 1 RX overflow sticky flag 29 Software Read only Write ignored D JTAG Write only High speed download flag 28 Software Read only Write ignored TR JTAG Write only 1 TX Register Ready 27 0 Read as Zero Write ignored Reserved RX Register Ready Bit RR The debugger and debug handler use the RR bit to synchronize accesses to RX Normally the debugger and debug handler use a handshaking scheme that requires both sides to poll the RR bit To support higher download performance for large amounts of data a high speed download handshaking scheme can be used in which only the debug handler polls the RR bit before accessing the RX register while the debugger continuously downloads data Table 10 9 shows the normal handshaking used to access
197. the previously downloaded functionality can be used There are also variations in which the debug handler supports multiple dynamic commands each mapped to a different dynamic function or a single dynamic command that can branch to one of several downloaded dynamic functions based on a parameter passed by the debugger Debug Handlers that allow code to be dynamically downloaded into the mini instruction cache must be carefully written to avoid inadvertently overwriting a critical piece of debug handler code Dynamic code is downloaded to the way pointed to by the round robin pointer Thus it is possible for critical debug handler code to be overwritten if the pointer does not select the expected way To avoid this problem the debug handler should be written to avoid placing critical code in either way of a set that is intended for dynamic code download This allows code to be downloaded into either way and the only code that is overwritten is the previously downloaded dynamic function This method requires that space within the mini instruction cache be allocated for dynamic download limiting the space available for the static Debug Handler Also the space available may not be suitable for a larger dynamic function Once downloaded a dynamic function essentially becomes part of the Debug Handler If written in the mini instruction cache it does not get overwritten by application code It remains in the cache until it is replaced by another
198. tly setting DBG_SR 35 or DBG_SR 1 will cause unpredictable behavior following an Update DR Intel XScale Microarchitecture User s Manual i ntel Software Debug Update DR parallel loads DBG_SR 35 1 into DBG REG 34 0 Whether the new data gets written to the RX register or an overflow condition is detected depends on the inputs to the RX write logic 10 10 6 1 RX Write Logic The RX write logic Figure 10 4 serves 4 functions 1 Enable the debugger write to RX the logic ensures only new valid data from the debugger is written to RX In particular when the debugger polls TXRXCTRLJ 3 1 to see whether the debug handler has read the previous data from RX The JTAG state machine must go through Update_DR which should not modify RX 2 Clear DBG_REG 34 mainly to support high speed download During high speed download the debugger continuously scans in data to send to the debug handler and sets DBG REG 34 to signal the data is valid Since DBG_REG 34 is never cleared by the debugger in this case the 0 to 1 transition used to enable the debugger write to RX would not occur 3 Set TXRXCTRL 31 When the debugger writes new data to RX the logic automatically sets TXRXCTRL 3 1 signalling to the debug handler that the data is valid 4 Set the overflow flag TXRXCTRL 30 During high speed download the debugger does not poll to see if the handler has read the previous data If the debug handler stalls long e
199. to capture a trace the process of reading the captured trace data also re initializes the trace buffer for its next usage The trace buffer can be used to capture a trace up to a processor reset A processor reset disables the trace buffer but does not affect the contents The trace buffer does not capture reset events or debug exceptions Since the trace buffer is cleared out before it is used all entries are initially 0500000000 In fill once mode these 0 s can be used to identify the first valid entry in the trace buffer In wrap around mode in addition to identifying the first valid entry these 0 entries can be used to determine whether a wrap around occurred As the trace buffer is read the oldest entries are read first Reading a series of 5 or more consecutive 0b00000000 entries in the oldest entries indicates that the trace buffer has not wrapped around and the first valid entry will be the first non zero entry read out Reading 4 or less consecutive 0500000000 entries requires a bit more intelligence in the host software The host software must determine whether these 0 s are part of the address of an indirect branch message or whether they are part of the 0b00000000 that the trace buffer was initialized with If the first non zero message byte is an indirect branch message then these 0 s are part of the address since the address is always read before the indirect branch message see Section 10 Address Bytes
200. tomatically sets the RR bit allowing the handler to proceed NOTE The value written to RX by the debugger is implementation defined it can be a bogus value signalling the handler to continue or it can be a target address for the handler to branch to loop mrc pis 0 r15 c14 cO O handler waits for signal from debugger bpl loop mrc p14 0 r0 c8 cO O debugger writes target address to RX bx ro In a very simple debug handler stub the above parts may form the complete handler downloaded during reset with some handler entry and exit code When a debug exception occurs routines can be downloaded as necessary This allows the entire handler to be dynamic Intel XScale Microarchitecture User s Manual 10 39 Software Debug I ntel ii 10 13 6 10 14 10 14 1 10 40 Another possibility is for a more complete debug handler to be downloaded during reset The debug handler may support some operations such as read memory write memory etc However other operations such as reading or writing a group of CP registers can be downloaded dynamically This method could be used to dynamically download infrequently used debug handler functions while the more common operations remain static in the mini instruction cache Mini Instruction Cache Overview The mini instruction cache is a smaller version of the main instruction cache Refer to Chapter 4 for more details on the main instruction cache It is a 2KB 2 way set asso
201. tro rel ee ater PRAE TIE I ROS SE TE C e rud PSP RR TR ee ava 6 7 iv Intel XScale Microarchitecture User s Manual j ntel 5 Contents 6 3 Data Cache and Mini Data Cache Control 6 7 6 3 1 Data Memory State After Reset 6 7 6 3 2 Enabling Disablirig nacre ie TERR eed dg 6 7 6 3 3 Invalidate A Clean Operations eene 6 8 6 3 3 1 Global Clean and Invalidate Operation 6 8 6 4 Re configuring the Data Cache as Data RAM ssssse eene 6 10 6 5 Write Buffer Fill Buffer Operation and Control 6 13 7 GOnHTIgUuration eec oot as aaa uae ta eto d ee da 7 1 f Re EE 7 1 1 2 CPIS Registers De aient etnia See et 7 3 7 2 1 Register 0 ID amp Cache fvpoebeoisters 7 4 7 2 2 Register 1 Control amp Auxiliary Control Registers AAA 7 5 7 2 3 Register 2 Translation Table Base Register 7 7 7 2 4 Register 3 Domain Access Control Register 7 8 7 2 5 Register 5 Fault Status Register eee 7 8 7 2 6 Register 6 Fault Address Register 7 9 7 2 7 Register 7 Cache Functions oooonnnccccnnnnnnccccccnnnoncccnnnnnnncc cnn nano e anar mene 7 9 7 2 8 Register 8 TLB Operations emm emen 7 10 7 2 0 Register 9 Cache Lock Down emnes 7 11 7 2 10 Register 10 TEB Lock Down 7 12 24 Register 13 Process ID zs ie tenerse nn ei 7 12 7 2 11 1 The PID Register Affect On Addresses eeeeeeeeeeseeerreeeeerrrsenes 7 13 7 2 12 Register 14 Breakpoint Register 7 13 7 2 13 Register 15 Coprocessor Access Register 7 14
202. two possibilities for setting up the reset vector trap The reset vector trap can be set up before the instruction cache is loaded by scanning in a DCSR value that sets the Trap Reset bit in addition to the Halt Mode bit and the hold rst signal The reset vector trap can be set up after the instruction cache is loaded In this case the DCSR should be set up to do a reset vector trap with the Halt Mode bit and the hold rst signal remaining set In either case when the debugger clears the hold rst bit to de assert internal reset the debugger must have already set the Halt Mode and Trap Reset bits in the DCSR Loading IC During a Warm Reset for Debug Loading the instruction cache during a warm reset is a slightly different situation than during a cold reset For a warm reset the main issue is whether the instruction cache gets invalidated by the processor reset or not There are several possible scenarios While reset is asserted TRST is also asserted In this case the instruction cache is invalidated so the actions taken to download code are identical to those described in Section 10 13 4 1 When reset is asserted TRST is not asserted but the processor is not in Halt Mode In this case the instruction cache is also invalidated so the actions are the same as described in Section 10 13 4 1 after the LDIC instruction is loaded into the JTAG IR When reset is asserted TRST is not asserted and the processor is in Halt
203. ue that has not been returned to the RFU and the current instruction needs to access that same register If no dependencies exist the RFU will select the appropriate data from the register file and pass it to the next pipestage When a register dependency does exist the RFU will keep track of which register is unavailable and when the result is returned the RFU will stop stalling the pipe The ARM architecture specifies that one of the operands for data processing instructions is the shifter operand where a 32 bit shift can be performed before it is used as an input to the ALU This shifter is located in the second half of the RF pipestage X1 Execute Pipestages The X1 pipestage performs the following functions ALU calculation the ALU performs arithmetic and logic operations as required for data processing instructions and load store index calculations Determine conditional instruction execution The instruction s condition is compared to the CPSR prior to execution of each instruction Any instruction with a false condition is Intel XScale Microarchitecture User s Manual A 5 E Optimization Guide ntel A 2 3 5 A 2 3 6 A 2 4 A 2 4 1 A 2 5 A 6 cancelled and will not cause any architectural state changes including modifications of registers memory and PSR Branch target determination If a branch was mispredicted by the BTB the X1 pipestage flushes all of the instructions in the prev
204. ug handler Setting up Override Vector Tables The override default vector table intercepts the reset vector and branches to the debug handler when a debug exception occurs If the vector table is relocated the debug vector is relocated to address OxFFFF 0000 Thus an override relocated vector table is required to intercept vector OxFFFF 0000 and branch to the debug handler Both override vector tables also intercept the other debug exceptions so they must be set up to either branch to a debugger specific handler or go to the application s handlers It is possible that the application modifies its vector table in memory so the debugger may not be able to set up the override vector table to branch to the application s handlers The Debug Handler may be used to work around this problem by reading memory and branching to the appropriate address Vector traps can be used to get to the debug handler or the override vector tables can redirect execution to a debug handler routine that examines memory and branches to the application s handler Placing the Handler in Memory The debug handler is not required to be placed at a specific pre defined address However there are some limitations on where the handler can be placed due to the override vector tables and the 2 way set associative mini instruction cache In the override vector table the reset vector must branch to the debug handler using adirect branch which limits the start of the ha
205. ug vector is relocated to OXFFFF 0000 Intel XScale Microarchitecture User s Manual 10 7 Software Debug I ntel i 10 5 The following debug exceptions cause pre fetch aborts instruction breakpoint BKPT instruction The processor ignores vector traps during monitor mode When an exception occurs in monitor mode the processor takes the following actions 1 disables the trace buffer 2 sets DCSR moe encoding 3 sets FSR 9 4 R14 abt PC of the next instruction to execute 4 for Data Aborts R14 abt PC of the faulting instruction 4 for Prefetch Aborts 5 SPSR abt CPSR 6 CPSR 4 0 05610111 ABORT mode 7 CPSR 5 0 8 CPSR 6 unchanged 9 CPSR 7 1 10 PC Oxc for Prefetch Aborts PC 0x10 for Data Aborts During Abort mode external Debug breaks and trace buffer full breaks are internally postponed When the processor exits Abort mode either through a CPSR restore or a write directly to the CPSR the postponed Debug breaks will immediately generate a Debug exception Any of these postponed Debug breaks are cleared once any one Debug exception occurs When exiting the debug handler should do a CPSR restore operation that branches to the next instruction to be executed in the program under debug HW Breakpoint Resources The Intel XScale core debug architecture defines two instruction and two data breakpoint registers denoted IBCRO IBCR1 DBRO and DBRI The instruction and
206. um cycle distance from the issue clock of the current multiply instruction to the issue clock of the next multiply instruction assuming the second multiply does not incur a data dependency and is immediately available from the instruction cache or memory interface For the following code fragment here is an example of computing latencies Example 11 1 Computing Latencies UMLAL r6 r8 r0 r1 ADD r9 r10 r11 SUB r2 r8 r9 MOV r0 r1 Table 11 2 shows how to calculate Issue Latency and Result Latency for each instruction Looking at the issue column the UMLAL instruction starts to issue on cycle 0 and the next instruction ADD issues on cycle 2 so the Issue Latency for UMLAL is two From the code fragment there is a result dependency between the UMLAL instruction and the SUB instruction In Table 11 2 UMLAL starts to issue at cycle 0 and the SUB issues at cycle 5 thus the Result Latency is five Table 11 2 Latency Example Cycle Issue Executing 1 umlal 2nd cycle 3 sub stalled sub stalled 5 sub 6 mov sub 7 mov Branch Instruction Timings Table 11 3 Branch Instruction Timings Those predicted by the BTB Maia Minimum Issue Latency when Correctly Minimum Issue Latency with Branch Predicted by the BTB Misprediction B 1 5 BL 1 5 Intel XScale Microarchitecture User s Manual Performance
207. ume that we have the following data Nlg Number of cycles to execute the if stmt assuming the use of branch instructions N2p Number of cycles to execute the else stmt assuming the use of branch instructions Pl Percentage of times the if_stmt is likely to be executed P2 Percentage of times we are likely to incur a branch misprediction penalty Nic Number of cycles to execute the if else portion using conditional instructions assuming the if condition to be true N2c Number of cycles to execute the if else portion using conditional instructions assuming the if condition to be false Once we have the above data use conditional instructions when PL 100 PI Pl 100 21 22 Wiad xm s OPI S AR x EL N2 x POEN CES d c Too c 100 BX TO B 700 100 The following example illustrates a situation in which we are better off using branches over conditional instructions Consider the code sample shown below cmp r0 0 bne L1 add ro ro 1 add rl ri 1 add qu t2 1 add r3 Y3 2 add r4 r4 1 b L2 Rb sub rO rO 1 sub Cl pli dB sub r2 r2 1 sub 13 X3 4l sub r4 r4 1 L2 In the above code sample the cmp instruction takes 1 cycle to execute the if part takes 7 cycles to execute and the else part takes 6 cycles to execute If we were to change the code above so as to eliminate the branch instructions by making use of conditional instructions the if else part would always take 10 cycles to complete Intel
208. undefined exception The operating system may grant access to this coprocessor by setting the appropriate bit in the Coprocessor Access Register and return to the application where the access is retried Sharing resources among different applications requires a state saving mechanism Two possibilities are The operating system during a context switch could save the state of the coprocessor if the last executing process had access rights to the coprocessor The operating system during a request for access saves off the old coprocessor state with the last process to have access to it Under both scenarios the OS needs to restore state when a request for access is made This means the OS has to maintain a list of what processes are modifying CPO and their associated state A system programmer making this OS change should include code for coprocessors CPO through CP13 Although the PXA255 processor only supports CPO future products may implement additional coprocessor functionality from CP1 CP13 7 3 CP14 Registers Table 7 21 lists the CP14 registers implemented in the Intel XScale core Intel XScale Microarchitecture User s Manual 7 15 Configuration l n Table 7 21 CP14 Registers Register CRn Access Description 0 3 Read Write Performance Monitoring Registers 4 5 Unpredictable Reserved 6 7 Read Write Clock and Power Management 8 15 Read Write Software Debug 7 3 1 Registers 0 3
209. uring portions of the data cache as data RAM In both cases Rd is a virtual address that maps to some non existent physical memory When creating data RAM software must initialize the data RAM before read accesses can occur Specific uses of these commands can be found in Chapter 6 Data Cache Other items to note about the line allocate command are It forces all pending memory operations to complete Ifthe targeted cache line is already resident this command has no effect This command cannot be used to allocate a line in the mini Data Cache The newly allocated line is not marked as dirty However if a valid store is made to that line it will be marked as dirty and will get written back to external memory if another line is allocated to the same cache location This eviction will produce unpredictable results if the line allocate command used a virtual address that mapped to non existent memory To avoid this situation the line allocate operation should only be used if one of the following can be guaranteed The virtual address associated with this command is not one that will be generated during normal program execution This is the case when line allocate is used to clean invalidate the entire cache The line allocate operation is used only on a cache region destined to be locked When the region is unlocked it must be invalidated before making another data access Register 8 TLB Operations Disabli
210. void these penalties when given the right optimization switches Total number of data writeback requests to external memory can be derived solely with PMNI Intel XScale Microarchitecture User s Manual 8 7 a Performance Monitoring ntel A 8 5 6 8 5 7 8 6 8 7 8 8 Instruction TLB Efficiency Mode PMNO totals the number of instructions that were executed which does not include instructions that were translated by the instruction TLB and never executed This can happen if a branch instruction changes the program flow the instruction TLB may translate the next sequential instructions after the branch before it receives the target address of the branch PMNI counts the number of instruction TLB table walks which occur when there is a TLB miss If the instruction TLB is disabled PMNI will not increment Statistics derived from these two events Instruction TLB miss rate This is derived by dividing PMN1 by PMNO CPI See Section 8 5 1 can be derived by dividing CCNT by PMNO where CCNT was used to measure total execution time Data TLB Efficiency Mode PMNO totals the number of data cache accesses which includes cacheable and non cacheable accesses mini data cache access and accesses made to locations configured as data RAM Note that STM and LDM will each count as several accesses to the data TLB depending on the number of registers specified in the register list LDRD will register two accesses PMNI cou
211. ware Debug l n e Table 10 19 Message Byte Formats Message Name Message Byte Type Message Byte format address bytes Exception exception ObOVVV CCCC 0 Direct Branch non exception 0b1000 CCCC 0 Direct Branch with checkpoint b non exception 0b1100 CCCC 0 Indirect Branch non exception 0b1001 CCCC 4 Indirect Branch with checkpoint non exception 0b1101 CCCC 4 Roll over non exception 0b1111 1111 0 10 12 1 1 10 12 1 2 10 28 a Direct branches include ARM and THUMB bl b b These message types correspond to trace buffer updates to the checkpoint registers 63 Indirect branches include ARM Idm Idr and dproc to PC ARM and THUMB bx blx and THUMB pop Exception Message Byte When any kind of exception occurs an exception message is placed in the trace buffer In an exception message byte the message type bit M is always 0 The vector exception VV V field is used to specify bits 4 2 of the vector address offset from the base of default or relocated vector table The vector allows the host software to identify which exception occurred The incremental word count CCCC is the instruction count since the last control flow change not including the current instruction for undef SWI and pre fetch abort The instruction count includes instructions that were executed and conditional instructions that were not executed due to the condition of the instruction not matching the CC flags A count value of 0 indicate
212. y Optimizations for Size For applications such as cell phone software it is necessary to optimize the code for improved performance while minimizing code size Optimizing for smaller code size will in general lower the performance of your application These are some techniques for optimizing for code size using the Intel XScale core instruction set Many optimizations mentioned in the previous chapters improve the performance of ARM code However using these instructions will result in increased code size Use the following optimizations to reduce the space requirements of the application code Multiple Word Load and Store The LDM STM instructions are one word long and let you load or store multiple registers at once Use the LDM STM instructions instead of a sequence of loads stores to consecutive addresses in memory whenever possible Use of Conditional Instructions Using conditional instructions to expand if then else statements as described in Section A 3 1 Conditional Instructions may result in increasing or decreasing the size of the generated code Compare the savings made by any removal of branch instructions to determine whether conditional execution reduces code size If the conditional components of both the if and else are more than two instructions it would be more compact code to use branch instructions instead A 31 E Optimization Guide ntel A 6 3 A 6 4 A 32 Use of PLD Instructions
213. ytes in length The first byte read from the buffer represents the oldest trace history information in the buffer The last 256th byte read represents the most recent entry in the buffer The last byte read from the buffer will always be a message byte This provides the debugger with a starting point for parsing the entries out of the buffer Because the debugger needs the last byte as a starting point when parsing the buffer the entire trace buffer must be read 256 bytes on the Intel XScale core before the buffer can be parsed Figure 10 6 is a high level view of the trace buffer Intel XScale Microarchitecture User s Manual 10 25 Software Debug I ntel i Figure 10 6 High Level View of Trace Buffer 10 26 first byte read target 7 0 oldest entry 1001 CCCC indirect 1000 CCCC direct 1100 CCCC direct CHKPT1 ee CHKPTO 1111 1111 roll over target 31 24 target 23 16 target 15 8 target 7 0 1101 CCCC indirect 1000 CCCC direct 1111 1111 roll over last byte read most recent entry 1000 CCCC direct The trace buffer must be initialized prior to its initial usage then again prior to each subsequent usage Initialization is done be reading the entire trace buffer The process of reading the trace buffer also clears it out all entries are set to 0500000000 so when the trace buffer has been used

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