USING THE DSM2180F3 WITH THE ANALOG DEVICES ADSP-2185
Contents
1. x8 seg y9t ema eoeds Aiowayy dsa Kiowa yse 4 seg X94 05 Kiowa use J seg x91 LS Asoway use J sea X94 cs Kowa yse 4 sea y9L 25 Kiowa yse 4 x91 vs Asoway use J seg 191 98 Kiowa yse seg 91 95 1 yse 4 sama x91 25 6na e eds Asowayy Ving eig dsa s934 962 0152 599 8 yen 55 padde 25531 SWOl eoeds Kuouiayy 9 17 AN1386 APPLICATION NOTE Figure 6 shows a typical memory map with the following attributes m Address Space The 256 byte locations for DSM control registers csiop reside in DSP I O address space selected by the DSP IOMS signal Since DSP I O accesses are 16 bits not 8 bits the upper byte of a 16 bit DSP I O access must be ignored m Byte DMA Address Space The DSP may boot load or fetch overlay bytes from 128 KBytes of Flash memory using the DSP BDMA channel The DSP may also write to Flash memory using the Byte DMA channel DSM Flash memory is accessed in 128 KB continuous byte address locations through the BDMA channel and is selected whenever the DSP BMS signal is active Flash memory in the DSM device must be un locked and written by the DSP one byte at a time checking status after each write typical Flash memory programming algorithm m Data Overlay Memory Address Space All 128 KBytes of Flash memory also reside in DSP External Data over2. orviva Qd uM viva ja Luvn G91 L 8Sviva 8viva dn 19599 MOvaMd 61d Za 91d Elv gely LLV OLY 6v 8v lv 9v SV ev IV 0v SWO SdL Sna 1VIH3S 19095 11935 019095 11395 4Jd cOul O VHINI 9dd L1OHl O VHINI 93 010 _ 30 dd O390W edd g83Q00W L4d V3GOW 04d WLX 10 1011050 NI NMOG HMd lt enng INvuS 98 nyao snai 2 5 17 AN1386 APPLICATION NOTE ADSP 218X to DSM2180F3 Schematic Figure shows an example schematic diagram for an ADSP 218x to DSM2180F3 design While Table 1 shows the required connections for every design the schematic shows additional signals and functions that would be typical of many designs Specifically the following signals have been added Table 2 ADSP 2185 DSM2180F3 Optional Signals Used Gus pap O o S PC7 Address bit 17 PWDACK PD2 CSI Power down chip select signal N A PB2 Chip Select for external device such as LCD UART etc Note The schematic also shows basic ADSP 218x connections such as the system reset input and the DSM2180F3 shows additional op tional connections such as I O and JTAG DEFINE THE ADSP 2185 INTERFACE IN PSDSOFT EXPRESS Highlights of design entry will be given here Please refer to the PSDsoft Express User Manual for a thor ough coverage of all the featur
3. csi ow adio3 pa Las Pin Function adiod CPLD Input adio5 pbl f Logic or address adio6 pb2 7 C adio c CPLD Output C adio8 pb4 7 Combinatorial adio3 External chip select Active Hi adiol pbb 7 C External chip select Active Lo adioll pb adiol2 Other C adol3 pcc tk C MCU 1 0 mode sse LI MCU 1 0 mode with pin enable adiolS ped 7 PSD chip select input CSI C ped C cnitl2 ped i C cni pe Update Delete reset pc Step 3 Final Step C pall Click Next gt gt after all pins are defined C pal pd Click View at any time to check progress Click Done to save the update and close LIN View Nest Cancel Done Note There are detailed instructions on how to use this screen and other screens in the PSDsoft Express User Manual ADSP 2185 BOOT LOADER The ADSP 2185 has two mechanisms to allow automatic loading of the internal program memory after reset which are BDMA boot or IDMA boot Either mode can be used with the DSM2180F3 however this application note uses BDMA booting The method for booting is controlled by the Mode A B and C con figuration bits See the ADSP 2185 data sheet for details on the boot methods and Mode pins ADSP 2185 MEMORY MA
4. Conte Snel aim mp wdme Step 3 MCU DSP Parameters Select a particular configuration for the device interconnection Bus Width esi z Bus Mode Non Mutiplexed Bus Description for any selection above Specify the PSD part number for your design Now you have your project established based on a DSM2180F3 and an ADSP 2185 When the Design Parameters screen appears choose Use example template selection and click OK to be taken to the MCU Template Selection screen Now choose Application Note 076 DSP loader and click Generate This will automatically setup the extra pins described in Table 2 and the memory map described in the next section Pin Definitions Your pin definitions should match Figure 5 and are defined according to the schematic shown in Figure 3 On this screen you can add or update pin functionality as desired When you are finished clicking Next gt gt will take you to the Design Assistant screen which will be covered in the next section 7 17 AN1386 APPLICATION NOTE Figure 5 DSM2180F3 Pin Definitions Definitions Define each pin by repeating the following steps Step 2 Pin Function standard pins already defined Define the pin function then click the Step 1 Select a pin on the chip diagram below Add Update button Return to step 1 repeat for next pin adol p5c di Mame
5. each PSD memory segment below Scroll to see all segments You may need to edit add the start and stop addresses if paging or other memory More Info manipulation is used Memory File File Select Memory Select Equations Address Address File Name Name Start Stop hex amp bms 51215 amp 14 FSO amp lal amp lalG amp csik rrr Prosrom hes Browse amp _ioms Ipdn amp bms amp 1a15 amp 14 k lal amp lalB amp _osi amp 4000 rre Progrem hex Browse dms amp tt amp amp bms amp 15 amp lal4 amp lal 51816 61 csi 8000 prr Program hed Browse dms amp _ioms Ipdn amp 1 bms amp 15 amp a14 amp lal amp lalB amp csi amp B dms amp _ioms tt Ipdn amp Browse zi Record Type Mapping Mode Concatenate Files Intel Hex Record Motorola 5 Record Direct Relative File Setting Step 2 Merge PSD configuration and MCU DSP firmware Click OK to create a programming data file Cancel PROGRAMMING THE DSM2180F3 IN CIRCUIT USING THE JTAG INTERFACE The ability to initially program a new system board with a blank Flash memory soldered directly to it has solved many manufacturing logistics problems no sockets or individual labels are reguired inventory of non volatile program memory chips is
6. Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2001 STMicroelectronics All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A www st com 1574 17 17
7. address gt h14000 amp address lt hl7FFF amp _ioms amp dms _bms 14 17 amp _bms amp _bms amp _bms amp _bms amp _bms AN1386 APPLICATION NOTE page 5 amp address gt h0000 amp address lt h3FFF amp ioms amp dms amp _bms fs6 address gt h18000 amp address lt hlBFFF amp ioms amp dms bms page 6 amp address gt h0000 amp address lt h3FFF amp ioms amp dms amp _bms 57 address gt h1C000 amp address lt hlFFFF amp ioms amp dms bms page 7 amp address gt h0000 amp address lt h3FFF amp ioms amp dms amp _bms external cs address gt h0200 amp address lt h0207 amp ioms amp dms amp _bms 15 17 AN1386 APPLICATION NOTE Table 3 Document Revision History Description of Revision 21 Jun 2001 1 0 Document written 16 17 AN1386 APPLICATION NOTE For current information on PSD products please consult our pages on the world wide web www st com psd If you have any questions or suggestions concerning the matters raised in this document please send them to the following electronic mail addresses apps psd st com for application support ask memory st com for general enquiries Please remember to include your name company location telephone number and fax number
8. reduced to one package the PLD is programmed at the same time as the memory chip one system board can be built and inventoried and options can be programmed into the Flash memory at board level testing Port C I O lines are used to interface to the standard JTAG signals TMS TCK TDI and TDO TSTAT and TERR are optional JTAG ISP extensions that can be monitored to decrease the programming time of the DSM2180F3 The DSM configuration PLD logic and Flash memory can all be programmed through the JTAG port Port C JTAG pins can also be multiplexed with other signals such that the signals are used to program the DSM while the DSP is held in reset and as general I O during normal DSP operation The cost of JTAG muxing is a single pin on the DSM to control the state of this mux This option frees up the JTAG pins for I O functions after JTAG programming is complete For more information on how the JTAG port can be multiplexed see Application Note AN1153 and the PSDsoft Express User Manual at http Avww ps dst com html psdsoft exp htm Also note that the DK 2180 development board multiplexes the JTAG sig nals and has a slightly different pin configuration 12 17 AN1386 APPLICATION NOTE SUMMARY As DSPs continue to proliferate into markets such as communications industrial medical signal condi tioning and hand held test equipment the DSM2180F3 and DSP form an ideal 2 chip solution with on chip PLD and I O lines that are indivi
9. P The ADSP 2185 uses a modified Harvard architecture with up to four independent memory spaces I O Data Program and Combined It contains 16 KWords x16 of on chip Data Memory DM Ram and 16 KWords x24 of on chip Program Memory PM RAM See the ADSP 2185 data sheet from Analog De vices for details on the memory architecture Figure 6 shows one possible memory map The nomenclature 150 157 are individual 16 KByte Flash mem ory segment designators within the DSM and csiop designates the DSM control register block For this memory map the DSP should be set to run in Full Memory Mode Memory contents of the DSM device may lie in one or more of three different DSP address spaces I O space with limited address lines byte DMA space and or External Data overlay Memory Space DMS Since the DSM device is a byte wide memory awareness of the natural x16 and x24 nature of DM and PM respectively is important The de signer may easily specify memory mapping in a point and click software environment using PSDsoft Ex press Since the memory mapping is implemented with the DPLD and the Page Register many possibilities exist 8 17 ki AN1386 APPLICATION NOTE The memory map is organized to work within the restrictions of the ADSP 2185 Boot Loader discussed and to utilize the entire Flash memory and show the paging features of the in the previous section DSM2180F3 2185 DSM2180F3 Memory Map Figure 6 ADSP 9S6r0IV
10. RR pc5 tdi Dedicated JTAG TDI tdo Dedicated JTAG TDO pc al7 Logic or address _ioms Logic or address dms Logic or address pa2 _csi PSD chip select input CSI User defined nodes None defined Page Register settings pgr0 is used for paging is used for paging pgr2 is used for paging pgr3 is not used pgr4 is not used pgr5 is not used pgr6 is not used pgr7 is not used Equations csiop address gt h0000 amp address lt hOOFF amp _ioms amp dms amp _bms fs0 address gt h0000 amp address lt h3FFF amp _ioms amp dms amp bms page 0 amp address gt h0000 amp address lt h3FFF ioms amp dms fsl address gt h4000 amp address lt h7FFF amp ioms amp dms amp bms page 1 amp address gt h0000 amp address lt h3FFF _ioms amp _dms fs2 address gt h8000 amp address lt hBFFF amp _ioms amp dms amp bms page 2 amp address gt h0000 amp address lt h3FFF _ioms amp _dms fs3 address gt hC000 amp address lt hFFFF 6 _ioms amp dms amp bms page 3 amp address gt h0000 amp address lt h3FFF _ioms amp _dms fs4 address gt h10000 amp address lt hl3FFF amp ioms amp dms _bms page 4 amp address gt h0000 amp address lt h3FFF _ioms amp _dms fs5
11. SZA CONTENTS PURPOSE DSM2180F3 ARCHITECTURE DEVELOPMENT SYSTEMS INTERFACING THE DSM2180F3 WITH THE ADSP 2185 DSM2180F3 Bus Inter face ADSP 218X to DSM2180F3 Schematic DEFINE THE ADSP 2185 INTERFACE IN PSDSOFT EXPRESS ADSP 2185 BOOT LOADER ADSP 2185 MEMORY MAP PROGRAMMING THE DSM2180F3 IN CIRCUIT USING THE JTAG INTERFACE m SUMMARY m APPENDIX June 2001 AN1386 APPLICATION NOTE Using the DSM2180F3 with the Analog Devices ADSP 2185 The DSM2180F3 is a system memory device for use with Dig ital Signal Processors from the popular Analog Devices ADSP 218X family DSM means Digital signal processor System Memory A DSM device brings In System Programmable ISP Flash memory programmable logic and additional I O to DSP systems The result is a simple and flexible two chip solution for DSP designs DSM devices provide the flexibility of Flash memory and smart JTAG programming techniques for both manufacturing and the field On chip integrated memory de code logic and memory paging logic make it easy to add large amounts of external Flash memory to the ADSP 218X family for bootloading and or overlay memory The DSP accesses this Flash memory using either its Byte DMA BDMA interface or as external data overlay memory DMA setup overhead JTAG In System Programming ISP reduces development time simplifies manufacturing flow and lowers the cost of field upgrades The JTAG ISP inter
12. dually configured to perform any function required by the system de sign Using the DSM2180F3 as an 8 bit boot loader in both high speed and low speed systems is an ideal and rapid design alternative to a discrete solution Inexpensive slower memory and PLDs integrated in the DSM2180F3 now become both cost and performance effective Several features of the DSM2180F3 were used to expand the functionality of the ADSP 2185 including m In System Programmable Flash memory m JTAG ISP to simplify manufacturing m Expanded I O m Interfacing to external devices was easily accomplished by generating the required control signals in the internal programmable PLD m A quick and easy design prototype using PSDsoft Express These changes have added to both the versatility and performance of the ADSP 2185 APPENDIX The Appendix contains the PSDsoft Express Design Assistant Summary listing all logic equations to show how the DSM2180F3 is configured for the ADSP 2185 interface in order to implement the example in this Application Note Application Note AN1356 presents a step by step illustration of how to configure the Flash DSM Family Although AN1356 uses the 16 bit Flash PSD4235G2 in the example the software and procedure is the same for the 8 bit DSM2180F3 KCkCkCkCkckckckckckckckck ck ckckckckckckckckckckckckckckckckckckckckckckckckck ck ck kckckckckckckckckckckckckckckckckckckckckckckckck ck kk kk PSDsoft Express Version 7 10 Summary of De
13. e DSM2180F3 device is designed to interface directly with the popular Analog Devices ADSP 218X se ries of DSPs The DSM2180F3 device provides bootloading capability and enables the core DSP design to be done with two chips The DSM JTAG port allows In System Programming ISP of a completely blank DSM2180F3 device sol dered to the board with no involvement of the DSP which is ideal for first time programming during man ufacturing Subsequent field updates can also be done via this interface This application note addresses the ease of interfacing the DSM2180F3 with the ADSP 2185 DSP Famil iarity with the DSM2180F3 is assumed Please see the DSM2180F3 data sheet for a detailed description of the device DSM2180F3 ARCHITECTURE Figure 1 is a block diagram of the DSM2180F3 Figure 1 DSM2180F3 Block Diagram SECURITY DSM2180F3 LOCK DSP SYSTEM FLASH MEMORY MEMORY DECODE PLD DPLD fs0 8 SEGMENTS 16 KB 128 KBytes TOTAL RUNTIME CONTROL CSIOP REGISTER POWER MANAGEMENT 16 INPUT MICRO lt gt CELLS HD Sz al JTAG ISP TO ALL AREAS OF CHIP PIN FEEDBACK NODE FEEDBACK A104951 On chip features supply the key elements to implement a two chip DSP System Flash DSM features in clude m Glueless connection to DSP easily add memory logic and I O to DSP 27 174 AN1386 APPLICATION NOTE 128 KBy
14. e this is a template the design should fit without errors if you have not modified the design If you do get an error you will need to fix it before moving on m Take note of the Generate C Code button It is used to generate flash routines that can be pasted into your C Code before compiling and linking This is not required for the presented design m Click the Merge MCU DSP firmware with PSD button This step is where the DSM configuration mem map are merged with the output of the compiler linker tools chain Upon invocation you will get a warning that basically says since paging was used in the design the software is not sure how to fill in the file start and stop addresses and you will have to do it manually Figure 9 shows an example of how this might be filled in and assumes that a file called Program hex has been previously generated taking up the first three DSM flash segments Note the scroll bar on the right to access memory beyond fs3 Click OK to generate the programming data file obj that will be used to program the device That s it you are now ready to program the device For more information on how to program the DSM through the JTAG port or a conventional programmer consult the PSDsoft Express User Manual http www psdst com html psdsoft exp htm 174 11 17 AN1386 APPLICATION NOTE Figure 9 Merging of DSP Firmware with DSM Memory Map Step 1 MCU DSP firmware placement Specify name of MCLI DSP firmware file
15. es of PSDsoft Express This section is meant to show you just the essentials to get you going Here are the steps when using a template Invoke PSDsoft Express and Open a New Project m Start PSDsoft Express m Create a new project m Select your project folder and name the project in this example name the project DSM2180 in the folder PSDsoftmy project The associated dialog box is shown graphically in Figure 4 MCU DSP and PSD Selection When you click OK in the New Project window the MCU and PSD Selection screen appears When you see this screen make the following selections m Select Analog Devices for the manufacturer and ADSP 218x for the type m The control signals are selected for you m Select the DSM2180 for the Family the DSM2180F3 for the part and the package m The MCU DSP parameters are set for you Click OK 6 17 AN1386 APPLICATION NOTE Figure 4 PSDsoft Express Define DSM and MCU DSP MCU DSP and PSD Selection x Step 1 Select Microcontroller MCU DSP Step 2 Specify the PSD device Select an MCLI DSP and its control signal options IF pour Use product selection wizard Wizard MCU DSP does not appear on the list select Other then specify its contral signal configuration Check latest MCU DSP and PSD data sheets to confirm AC timing compatibility PSD Fami psu2180 Z E E Janaba Devices m Part Number AEA l Package KmePmPLCC
16. face eliminates the need for Sockets and pre programmed memory and logic devices For manufacturing end products may be assembled with a blank DSM device soldered to the circuit board and programmed quickly In addition to ISP Flash memory DSM devices add program mable logic PLD and up to 16 configurable I O pins to the DSP system The state of each I O pin can be driven by DSP software or PLD logic PLD and I O configuration are program mable by JTAG ISP just like the Flash memory The PLD con sists of more than 3000 gates and has 16 macro cell registers Common uses for the PLD include chip selects for external de vices state machines simple shifters and counters keypad and control panel interfaces clock dividers handshake delay and muxes This eliminates the need for small external PLDs and logic devices Configuration of PLD I O and Flash memo ry mapping are easily entered in a point and click environment using the software development tool PSDsoft Express This software is available at no charge from http www psdst com html softcenter2 html The two chip combination of a DSP and a DSM device is ideal for systems that have limitations on physical size and power consumption concerns DSM memory and logic are zero pow er meaning they automatically go to standby between memo ry accesses or logic input changes producing low active and standby current consumption 1 17 AN1386 APPLICATION NOTE PURPOSE Th
17. ing logic pari paging logic paging logic r Description Select this bit for memory paging Use one bit to define two memory pages use two bits to define four pages three bits for eight pages and so on Select enough bits to cover the number required pages Always start with par and add more bits going upward as these l lt lt Back Reset Al View Done Cancel The memory map is organized to work within the restrictions of the ADSP 2185 Boot Loader andto utilize the entire Flash memory and show the paging features of the DSM2180F3 The three paging bits will provide 2 8 pages Click Next to see the Chip Selection Equations screen shown in Figure 8 10 17 LLL AN1386 APPLICATION NOTE Figure 8 DSM2180F3 Chip Select Equations Assistant Page Register Definition Chip Select Equations 1 0 Logic Equations User defined Node Equations For each chip select select a page number if memory paging is used the active address range and any Double click any of the signal names additional signal qualifiers Ensure PSD page register bits have been defined if used here below to append the signal name to the Logical AND of Signal Qualifiers Signal qualifiers are listed in box on right Logically AND qualifiers within same line using amp symbol Create eaten logic OR by using nest line below Use I symbol for logical NOT List of chip select
18. lay Memory Space selected by DMS allowing more efficient byte writes to Flash memory The DSP uses its external data overlay window of 8 KB locations to access external memory as data The DSP doubles the size of this window to 16 KB locations by manipulating its A13 address line using its DMOVLAY register See the ADSP 2185 data sheet for details Since all 128 KBytes of Flash memory must be accessed through a window of only 16 KB locations the DSP uses the Page Register inside the DSM device to page through 8 pages of 16 KBytes as shown in Figure 6 Since DSP Data accesses are by 16 bits not 8 bits the upper byte of a 16 bit DSP Data access must be ignored Define the Memory Map in PSDsoft Express The template s memory map is setup according to Figure 6 First note how the Page Register is setup shown in Figure 7 Figure 7 DSM2180F3 Page Register Setup EDesign Assistant _ m x Page Register Definition Chip Select Equations 1 0 Logic Equations User defined Node Equations Define how individual PSD page register bits will be used Each bit added for paging can extend the MCU DSP address range Start with par Each bit added for logic can used as logic input to the PLDs Start with pgr r Define use of page register bits Page Reg Bit Type of Use Name of Logic Signal par paging loge paging logic pars paging logic pard paging logic par pagng logic pare pag
19. rface signals from the ADSP 2185 used to access the Flash memory PLD logic and I O inside the DSM2180F3 These signals are automatically configured when the ADSP 218X is selected Table 1 ADSP 2185 DSM2180F3 Bus Interface Pin Functions ADSP 2185 Pin A 15 0 ADIO 15 0 External Address Bus addresses all external memory Program Data and 1 0 D 7 0 8 high byte bi directional external Data bus lines D 15 8 Port A PA 7 0 8 low byte bi directional external Data bus lines Port A is used as the 8 bit Data bus into the DSM2180F3 ANR CNTLO Write signal is used to access external memory during memory write cycles RD Read signal is used to access external memory CNTL1 during memory read cycles BMS CNTL2 Byte Memory Select signal is used for external 8 bit data memory accesses RESET _RESET System reset input 4 17 AN1386 APPLICATION NOTE Figure 3 ADSP 218x to DSM2180F3 Bus Interface Schematic S6v0IV Z 0 ad JopeaH vir jeuondo MA SOA lt or or lt or O I 1909135 109198 jeuondo ss3uaav 08LcINSG 19599 ISO 20 29 9 SIO vlOl 0150 LLO 010 60 80 ZO 90 SO vO O LO 00 av av av av av av av av av av av JosiMedns 19939 NMOG H3MOd 211 9 V
20. s Enter system memory information r Eligible signals Page Hex Start Hex End Logical AND of Signal Qualifiers E Number Address Address more than one E i y FFF g oms tams Logical DA with next statement p Sp 4 FFF bm Logical OF with next statement L EB Resultant equation bme 2 Intemal PSD chip select for one 16K byte segment of main flash P 3FFF hex locations max 4 b 1 ri lt lt Prev Next gt gt Reset ll View Done Cancel Show Eq If you click on each of the chip select signals in the list on the list you will see that they have all been defined according to the memory map in Figure 6 Note that all the chip select equations are listed in the Appendix The Logic Equations and User defined Equations tabs are used to implement general purpose com binatorial and sequential logic These topics are covered in more detail in the PSDsoft Express User Man ual http www psdst com html psdsoft_exp htm When you are ready to see how the DSP firmware can be loaded into the DSM via the programming data file obj click Done Loading the ADSP Firmware into the DSM Now that you have completed the definitions of the DSM s internal and external signals it is time to load the ADSP firmware into the DSM To accomplish this take the following steps m Click the Fit Design to Silicon button in the PSDsoft Express design flow Sinc
21. sign Assistant KKEKKKKKKKKKKK KKK ckckckckckckckckckck KKK KK KKK KKK KKK KK KKK KKK ckckckckckckckckckckckckckckckckck ck ckck ck kk PROJECT ANO76 DATE 05 21 2001 DEVICE DSM2180F3 TIME 13 05 59 MCU DSP ADSP 218x KCKCkCkCk kckckckckckckckckckckck ck kckckckckckckckckckckckckckckckckckckckck ck kckckckckckckckck ckckckckckckckckckckckckckckckckck ck kk kk Pin Definitions Pin Signal Pin Name Name Type adio0 a0 Address line adiol al Address line adio2 a2 Address line adio3 a3 Address line adio4 a4 Address line adio5 a5 Address line adio6 a6 Address line adio7 a7 Address line adio8 a8 Address line adio9 a9 Address line adiol0 alo Address line adioll all Address line adiol2 al2 Address line 1574 13 17 AN1386 APPLICATION NOTE adiol3 a13 Address line adiol4 al4 Address line adiol5 al5 Address line cnt 10 _wr DSP bus control signal Gnt T2 ms DSP bus control signal cnt11 _rd DSP bus control signal reset _reset RESET input pad d8 Data line pal d9 Data line pa2 10 Data line pa3 dii Data line pa4 d12 Data line pa5 813 Data line pa6 14 Data line 15 Data line _cs_uart External chip select Active Lo pco tms Dedicated JTAG TMS pci tck Dedicated JTAG TCK pc2 al6 Logic or address pc3 tstat Dedicated JTAG TSTAT pc4 _terr Dedicated JTAG TE
22. tes of main Flash memory divided into eight equal individually protected sectors Flash based PLD with 16 Output Macrocells and 16 Input Macrocells General Purpose PLD that is configurable for external chip selects or combinatorial logic 19 individually configurable I O Port pins Each may be defined as DSP I Os PLD I Os latched DSP address outputs or special function I Os 8 bit Page Register to expand the external address space and implement memory swapping m JTAG compliant serial port for true In System Programming ISP of blank devices and reprogramming of devices in the factory or field DEVELOPMENT SYSTEMS This application note provides general guidelines for connecting the DSM2180F3 to the ADSP 218X DSP In addition ST provides a specific development kit implementation called the DK 2180 that highlights many of the features of the DSM and ADSP For more information see our development kit section of our website http www psdst com html tools html PSDsoft Express is a software development tool that runs on Windows platforms for DSM family develop ment This tool allows you to configure the DSM using a simple point and click interface DSP bootloader firmware is imported and merged to create a single programming data file obj to program into the DSM The generated programming data file is then used to program the DSM using one of ST s programmers PSDpro or FlashLINK or a 3rd party programmer For more information on PSDsoft E
23. xpress visit http www psdst com html softcenter2 html To see list of compatible 3rd party programmers visit http www psdst com html psdprog html INTERFACING THE DSM2180F3 WITH THE ADSP 2185 The ADSP 2185 contains the following m An on chip 8 bit Automatic Boot Loader through DMA interface or memory port m 80 KBytes RAM configures as m 16 KWords Program Memory RAM 24 bit m 16 KWords Data Memory RAM 16 bit m Dual purpose Program Memory for both instructions and data storage The low cost DSM2180F3 is selected for this design to take advantage of the ADSP 2185 resident boot loader using its Flash memory to store the downloadable ADSP 2185 program code Figure 2 is a basic block diagram that shows the implementation of a basic system using the 05 2180 3 ADSP 2185 two chip combination All glue logic Flash memory bus interface logic I O chip selects and PLDs are contained in the DSM chip 3 17 AN1386 APPLICATION NOTE Figure 2 Minimized DSP System Block Diagram Optional Device D8 D15 Data A0 A15 AD0 AD15 Address Control LCD UART etc Control CNTL 2 0 Lines JTAG Header ADSP 2185 DMS2180 Al04952 DSM2180F3 Bus Interface When an ADSP218x is selected in PSDsoft Express see Section 6 the bus interface is pre configured so there is no chance to make a configuration mistake Table 2 lists the bus inte
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