PMX-P, PME-P Manual
Contents
1. 6 MN MS Fe R 2 58 8 Specifications 2 1 Rastergraf 2 1 Specifications Common to the PMX P and PME P Form Factor PCI Interface Indicators Test Points Printed Circuit Board Standards Compatibility PCI Bus Loading Power Requirements Weight Environmental Specifications 2 2 Short PCI standard height 167 7 mm x 104 1 mm Bridged connection uses 7 9 130 PCI PCI X to PCIe x1 x2 x4 PCI is 32 64 bit 33 66 MHz PCI X is 32 64 bit 33 66 100 133 MHz Full PCI and PCI X functionality was verified on a Supermicro C2SBX motherboard Green LEDs for 3 3VAUX 12V PCIe 3 3V_PCle 12V 12V 5V 3 3V 1 8V_VAUXS 1 8V_VDS 1 8V_VAS VIO PCI LOO VPWR 12V Amber LED for GPIO3 high VPWR 5V Red for Hi Temp GPIO3 Low 3 3VAUX 12V PCIe 3 3V PCIe 12V 12V SV 3 3V 1 8V VAUXS 1 8V VDS 1 8V VAS VIO PCI LOO VPWR Hi Temp GPIO3 GND 8 layer stackup Signal Ground Signal 3 3V VDDC PI7C9X130 Core Signal Ground Signal PCI PCI X trace lengths connector to 7 9 130 by necessity exceed standard trace length specifications because the pinout for the PI7C9X130 is backwards from that which would yield the optimum trace layout There is no other chip that would work better Each PCIe CLK and nets pair is matched to 125 mm PCIe net pairs don t have to be matched pair to pair Signal traces are i2. 1 4 Additional References You can find Rastergraf documentation and other technical literature on the Rastergraf web page http www rastergraf com The PCI Local Bus 2 3 Specification and the PCI X1 0 Specification are maintained by the PCI Special Interest Group PCISIG Web Page _ http www pcisig com home Some specifications are available from Rastergraf s technical library Web Page _http www rastergraf com Library standards_library htm VITA Documentation Store Order any official VITA standard https www vita com online store html 1156 2 1996 IEEE Standard for Environmental Specifications for Computer Systems 1996 includes IEEE 1101 1156 2 1996 IEEE Standard for Environmental Specifications for Computer Systems 1386 2001 and 1386 1 2001 IEEE Standard for Common Mezzanine Card Family CMC and IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards 1386 2001 amp 1386 1 Standard fora Common Mezzanine Card Family General Information 1 5 Rastergraf Chapter 2 Specifications Rastergraf Inc 1804 SE First St Redmond OR 97756 Phone 541 923 5530 Fax 541 923 6475 ee 45 degree CHAMFER 2X 59 9948 581152 0 320 104 1146 is eee un 7 6 88 591 e e 12491 8 26 483 0 020 45
3. 32 33 Honda HDRA E68W1LFDT 8 F19 66 67 VHDCI Connector 34 68 GND Connector Pinouts 3 4 Rastergraf 3 4 PME P PCI Express Target Connector Fi Signal Name 86 sMpaT B10 BI B B PRN I lt wW 17 PRSNT2 wW 2 lt Signal Name 12V 1 TDO TMS gt I 3 3V PERST Q e gt 2 REFCLK A13 REFCLK 14 15 0 16 PERnO A17 GND A18 End of x1 Connector B PETn1 PETp2 GND GND B PETn2 ND SV GND w NTR 21 N B B B B2 i w w w w t2 gt oO t w U RESV A19 GND A20 PERp1 A21 PERn1 A22 GND A23 GND 24 PERp2 A25 PERn2 A26 GND A27 N 28 PERp3 A29 PERn3 A30 N 31 RESV A32 Q Q J End of x4 Connector Connector Pinouts 3 5 Rastergraf 3 4 PME P PCI Express Target Connector continued Pin SignalName SignalName Pin GND A34 A35 GND 8 PRSNT2 Connector Pinouts 3 6 Rastergraf 3 4 PME P PCI Express Target Connector continued Pin SignalName SignalName Pin GND 65 8 ox __ A66 GND GND n c n c GND GND n c n c GND Q 5 8 6 69 70 7 72 73 74 7 76 77 7 A80 PRSNT2 81 End of x16 Connec
4. OT al EXE 10149 ej ae EM 2 ls n 00100 Hip a zm BE EX 5 5 bo om m 5 411568 2 g SE 2 e ee H LN ES I Eur D tS e o D 125 E zi lt NISL oe mu o OA eje erem cw JE Wei 7 T yoo g 2 5 yo 2 8 E z 5 i pe Rastergraf Inc Product designed in USA Redmond OR USA Copyright 2009 Installing Your PMX P PME P Board 4 5 Rastergraf 4 6 Installing Your PMX P or PME P Board Rastergraf Chapter 5 Troubleshooting Introduction This chapter contains information which should assist you in tracking down installation and functional problems with your board 5 1 General procedures 5 2 Dealing with the PCI bus 5 3 Maintenance Warranty and Service Troubleshooting 5 1 Rastergraf 5 1 General Procedures The PM Series boards were designed with reliability and durability in mind Nevertheless it may happen that problem will occur This section is devoted to aiding the user in tracking down the problem efficiently and quickly You may be able to locate minor problems without technical assistance If the problem can not be remedied Rastergraf
5. connection See Section 3 4 for more information VO area of PCIe target board Note that in some cases it may be necessary to remove the PCIe sheet metal panel in order to get things to fit PCIe Specification 1 1 Board 12V 20 mA each SV 20 mA 3 3V 90 4A Additional power is consumed by the PCIe module 12V and 3 3V Presently no current limiting is enforced but this is subject to change in a later revision Chapter 3 Connector Pinouts Rastergraf 3 1 Pn4 Connector PMX P P46 The PMC Pn4 Breakout Connector pinout is derived from the VITA 46 9 P64s pinout Since the V46 connector is not appropriate for this product the 64 pins are mapped as 32 differential pairs wired to Honda HDRA EC68LFDT S SL VHDCI 8 connector The pair grouping on PMC Pn4 connector are adjacent pins on the same side of the connector 1 3 2 4 The pairs are length matched both by pair and over the signal set at 28 425 mm 125 mm via Connections are routed as 100 ohm differential pairs If used as single ended one line in each pair MUST be grounded When used as differential pairs 100 Ohm round cable discrete twisted pair cable MUST BE USED Ribbon IDC cable CANNOT be used because routing limitations prevented matching circuit pairs with ribbon cable pairs to via PMC Pn4 7 BUM 42 al ul al co amp Molex PMC Connectors Connecto
6. 56 57 58 59 60 Bol B62 Signal Name CBE 2 GND IRDY DEVSEL PCIXCAP LOCK PERR SERR CBEI1 AD 14 GND AD 12 AD 10 M66EN w w w AD 08 gt J w AD 05 AD 03 ND AD 01 VIO ACK64 5 lt lt Signal Name Signal Name GND A37 PAR A43 AD 13 A46 09 49 5 0 52 AD 04 A55 GND A56 AD 00 A58 VIO A59 lt Connector Pinouts 3 9 Rastergraf 3 5 2 PCI PCI X Bus 64 Bit Connector Extension Connector Pinouts 3 10 Signal Name ND CBE 7 CBE 5 VIO PAR64 AD 62 GND AD 60 AD 58 GND AD 56 AD 54 VIO AD 52 AD 50 GND AD 48 AD 46 GND AD 44 AD 42 VIO AD 40 AD 38 GND AD 36 AD 34 GND AD 32 RESV ND RESV ON gt gt gt Lu I a ON 7 gt gt gt lt 3 664 Olle 53 B gt Chapter 4 Installing Your or Board Your or P P Board 4 1 Rastergraf 4 1 Introduction Using the PMX P or involves resolving some system integration issues The is carrier for card and the PME P 15 adapter for PCIe card In either case of course you have to know what you are doing and how you plan to use the board The allows you to install the XMC card and actually close up the system box The PME P is l
7. The PMX P does NOT support Rapid I O XMC boards Damage to the PMX P and or a Rapid I O or other non PCIe will likely result if you try to use such a board with the PMX P 4 2 Installing Your PMX P or PME P Board Rastergraf There are other potential problems with the a The XMC uses a BGA based 7x19 connector from Samtec At the time of writing this connector system has not been documented to be viable for more about 75 100 insertion removal cycles This is because of stress failures in the BGA solder joints All of the mechanical stress of the connector system goes through the BGA solder joints and they are not strong enough to withstand many cycles Please contact Rastergraf if you have questions or concerns about this b The VITA 42 0 XMC master specification defines 14 power pins The power pin is rated at I A Given the various supply voltages you could theoretically draw in excess of 130W There is nothing in the VITA 42 0 specification that controls power consumption Note that the practical limit of the XMC card with 10 mm spacing is around 15W to 20W Please exercise caution See Section 2 2 for more information 4 3 Comments Concerning PCIe boards PCIe cards are pretty straightforward There is only one connector definition and it covers board implementations from x1 to x16 data links It allows some optional features such as Hot Swap and JTAG PME P will accept a board with anything from x1 to
8. a set of on board registers which control the characteristics of the board as required by the PCI Specification The information used to program these registers is supplied to Operating System OS specific functions by Rastergraf s software Ordinarily several address map translations occur including the CPU physical and virtual address maps and the CPU to PCI bridge address map While x86 systems generally follow the standards required to meet PC compatibility and mask these details PowerPC systems do not Among PowerPC vendors there are no standards which ensure interoperability among CPU boards even when they use the same CPU and PCI bridge Therefore if you plan to use an PM Series board in a PowerPC based system it is vital to ensure that Rastergraf can vouch for the board s operation before you order the board Otherwise you may go crazy trying to figure out why it doesn t work Please contact us at support rastergraf com or 541 923 5530 if you have problems 5 3 Maintenance Warranty and Service Maintenance The PM Series requires no regular service but if used in a particularly dirty environment periodic cleaning with dry compressed air is recommended Because of the heat generated by normal operation of the board and other boards in the system forced crossflow ventilation is required If forced ventilation is not used IC temperatures can rise to 60 degrees C or higher Such high temperature operation cause
9. can then issue Return Material Authorization RMA so that the board can be returned to the factory for quick repair It can happen that installing new board will overload computer s power supply if the power supply margins are exceeded The first step in ascertaining if this is the problem is to calculate power supply budget This involves adding up the power requirements of each board in the system to see if you are within specification Consult your computer s technical manual for information on how to correctly determine this typical PM Series will draw a total of less than I Amp at 5 and 3 3 Volts When attempting to verify that the power supply is working properly it is not unusual to unplug everything and measure the supply without load While this practice is acceptable for linear supplies switching supplies which are very commonly used in computers require certain load before proper regulation is achieved Typically at least 5 Amps must be drawn from the 5 Volt supply before the 12 volt supplies will give the proper readings 5 2 Troubleshooting Rastergraf 5 2 Dealing with the PCI Bus Because of the nature of the PCI protocol and the way support has been implemented in the Operating Systems for PCI bus devices such as the PM Series it is not possible to follow the same debugging strategies In fact there are no address jumpers for these boards Everything is configured in software through
10. within 125 mm Also see Section 3 1 The breakout follows VITA 46 9 x8 12d38s pinout but the I O connector is two 68 pin VHDCIs Signals are routed as 39 matched length pairs The set of 39 pairs match length to within 125 mm Also see Section 3 3 VITA 42 0 XMC VITA 42 3 PCIe on and parts of VITA 46 9 1 PCIe Specification 1 1 for PCIe signal rules and connections Board 12V 20 mA each est 5V 20 mA est 3 3V 00 4 est Additional power will be consumed by the XMC module The current pin rating for the is 1A The has 14 power pins If VPWR 12 you have a theoretical power of 133W The practical power limit for an XMC is actually in the range of 15W to 20W The PMX P does not have current limiting on the 12V and 3 3V pins but this is subject to change in a later revision However VPWR is current limited by a Polyswitch resettable fuse for VPWR 5V fuse is 2 6A Hold 5A Trip 5s trip time 12V fuse is 1 25A Hold 2 5A Trip 45 trip time Specifications 2 3 Rastergraf 2 3 Specifications Unique to the PME P Target Interface PCIe Access I O Access Standards Compatibility Power Requirements Specifications 2 4 One PCIe Specification 1 1 Gen 1 compliant PCIe module Uses top mounted socket see Figure 1 2 without card latch Accepts 1 to x16 PCIe card but bridge only goes up to x4 Supports a single x1 x2 or x4 PCIe
11. 0000000000000000000000000000000000 00000000000 37 3 1 PMX P PN4 I O CONNECTOR 46 3 2 3 2 PMX P PN5 TARGET VITA 42 3 PCIE CONNECTOR 3 3 3 3 PMX P PN6 I O CONNECTOR 202 0 2 000010000000000000000000 3 4 3 4 PME P PCI EXPRESS TARGET e n n nen nnn nnn nnn n nnn e e n n a 3 5 3 5 PMX P AND PME P PCI PCI X HOST CONNECTOR 00 n n n n n nnn nnne nnn nnn annua 3 8 3 5 1 PCI PCI X Bus 32 Bit 3 8 3 5 2 PCI PCI X Bus 64 Bit Connector Extension 020 000 000000 06 nennen nene tren e 3 10 CHAPTER 4 INSTALLING YOUR PMX P OR PME P BOARD 4 1 4 1 INTRODUCTION 4 2 4 2 COMMENTS CONCERNING BOARDS 2 4 2 4 3 COMMENTS CONCERNING PCIE 5 2 4 3 44 UNPACKING YOUR eeu ner ae 4 4 45 CH NGING JUMPERS 28H a Udo tee Pe E ee 4 4 CHAPTER 5 TROUBLESHOOTING eere ee ee eren nane ae esee eese enssssseeeeeeeseesesesee 9 1 INTRODUCTION sr bee ea e seeders 5 1 5 1 GENERAL PROCEDURES rei 5 2 5 2 DEALING WITH THE PCI BUS Lee 5 3 5 3 MAINTENANCE WARRANTY AND SERVICE ccccsessssecececeesesecescceceesensesecececeesensaaeceeececeenssaeeeeececeeneas 5 3 Rastergraf Figures F
12. 3 3 PMX P Pn6 Connector PMX P P46 The Breakout Connector pinout is is derived from the Connections are routed as 100 ohm differential pairs If used as sin VITA 46 9 X8 12d38s pinout Since the V46 connector is not gle ended one line in each pair MUST be grounded appropriate the 78 signal pins are mapped as 39 differential pairs When used as differential pairs 100 Ohm round cable discrete wired to a Honda HDRA E68WILFDTIEC SL CEMM twisted pair cable MUST BE USED Ribbon IDC cable CAN dual connector NOT be used because routing limitations prevented matching circuit The pairs are length matched both by pair and over the signal set at pairs with ribbon cable pairs 146 025 mm 125 mm via to via Pn6 Upper VHDCI 68 D7 E7 U23 U22 051 050 El U17 UL A10 B10 D10 E10 A12 B12 D12 E12 GND U49 U48 U15 U14 GND A13 B13 U47 U46 D13 E13 U13 012 14 14 D14 14 GND U45 U44 U11 U10 GND A15 BIS Pn6 Lower VHDCI 68 T 35 GND CI FI 2 3 36 37 C2 C3 4 5 F2 F3 38 39 6 7 40 41 GND C4 C5 8 9 F5 22 43 10 11 44 45 GND C6 12 13 F6 F7 46 47 14 15 48 49 GND C8 C9 16 17 F8 F9 50 51 C10 18 19 52 53 20 21 54 55 GND m PT S FI2 F13 24 25 58 F14 215 60 61 Samtec XMC Connectors 28 29 62 63 GND 16 C17 30 31 FIG FI7 64 65 C18
13. CI or PCI X slot Because the PCIe board plugs into socket at the top edge of the the height of the combination of the two boards stands at about twice the standard height of a PCI card By necessity therefore the PME P is most practically used in a lab environment for testing or other non production applications Rastergraf produces several other PMC carriers for PCI or CompactPCI computers For more information about them and the rest of Rastergraf s products please contact Rastergraf Worldwide Sales at 541 923 5530 or consult Rastergraf s web page at http www rastergraf com General Information 1 2 Rastergraf 1 2 Feature Summary Short PCI form factor board holds one VITA 42 3 PMX P P46 version provides optional breakout connectors with matched length pairs for PMC Pn4 and XMC Pn6 32 64 bit 33 66 100 133 MHz PCI PCI X operation e PCI 2 3 and PCI X 1 0 compliant with Universal PCI signaling VITA 42 3 compliant supports PCIe x1 x2 or x4 on the Uses PI7C9X130 PCI Express to PCI PCI X Bridge Test Point pins and LED indicators for most on board power supplies User selectable VPWR 5 or 12 with current limiting Requires host supplied 3 3V 5V 12V and 12V Universal PCI signaling e LM75 thermal sensor Figure 1 1 PMX P Functional Outline LEDs amp Test Points XMC Pn6 to Dual 68 pin VHDCI connectors w
14. PMX P User s Manual XMC or PCIe to PCI PCI X Adapters Rastergraf Rastergraf Inc 1810 J SE First St Redmond 97756 541 923 5530 web http www rastergraf com Release 2 1 April 29 2014 Table of Contents GETTING HEMP vinkel 0 2 ILO DNA ONS 0 2 MANUAEREVISIONS RN 0 2 NOTIGES MR LM PN 0 3 CONVENTIONS USED IN THIS MANUAL 0 4 CHAPTER 1 GENERAL INFORMATION 1 1 1 1 INTRODUCTION eee 1 1 1 1 INTRODUCTION 1 2 1 2 PMX P FEATURE SUMMARY eerrrvrevevererererererererererevererererererereverevererererevevevevevevevevevevevevevevevenenevevevenevener 1 3 1 3 PME P FEATURE SUMMARY errrvrevevererereverererererevevererererererereveverevereverereveveveverevevevevevevevevevenenevevevenevener 1 4 1 4 ADDITIONAL REPFERENGES eet 1 5 CHAPTER 2 SPECIFICATIONS e eeeeeee esee eese eese ensassssee esee eese snssssseeeeseeseeseseeee 2 1 2 1 SPECIFICATIONS COMMON TO THE PMX P AND 2 2 2 2 SPECIFICATIONS UNIQUE TO THE 2 3 2 3 SPECIFICATIONS UNIQUE TO THE PME P rrrorronnnnnrvrnvnrsernennrnrnvnssrsnennnnrnrnserssennnnnnnnenssnensnnnnnnenssnnnsnnnnns 2 4 CHAPTER 3 CONNECTOR PINOUTS 2222000000000000
15. ation contained in this document The electronic equipment described herein generates uses and may radiate radio frequency energy which can cause radio interference Rastergraf assumes no liability for any damages caused by such interference Rastergraf products are not authorized for any use as critical components in flight safety or life support equipment without the written consent of the president of Rastergraf Inc These products have been designed to operate in user provided PCI compatible computers Connection of incompatible hardware is likely to cause serious damage Rastergraf assumes no liability for any damages caused by such incompatibility Rastergraf assumes no responsibility for the use or reliability of software or hardware that is not supplied by Rastergraf or which has not been installed in accordance with this manual Rastergraf is a trademark of Rastergraf Inc other trademarks and copyrights are the property of their respective owners Copyright O 2014 by Rastergraf Inc Introduction 3 Rastergraf Conventions Used In This Manual Introduction 4 The following list summarizes the conventions used throughout this manual Code fragments Commands program names System prompts and commands Keyboard usage Caution Warning Code fragments file directory or path names and user computer dialogs in the manual are presented in courier typeface Commands or the nam
16. epair A flat fee will be charged for normal repairs and must be covered by valid purchase order If extensive repairs are required Rastergraf will request authorization for an estimated time and materials charge If replacement is required additional authorization will be requested All repair work will be done at the Rastergraf factory in Redmond Oregon unless otherwise designated by Rastergraf 5 4 Troubleshooting Rastergraf Index Additional References 1 5 conventions used in manual 0 4 Maintenance 5 3 PCI 5 1 5 3 PMB C 5 3 Return Policy 5 4 RMA 5 2 5 4 Service 5 4 technical support 0 2 unpacking your board 4 4 Warranty 5 4
17. er locations 4 5 1 VPWR Select The XMC specification provides for the eight VPWR pins on Pn5 to be set to 5V or 12V This means that you need to be VERY SURE of what your target XMC board expects on VPWR To be on the safe side the is shipped with NO JUMPER INSTALLED Thus there is 0 volts on the pins Rastergraf cannot be responsible for damage caused to your board if you select the wrong voltage If you have any questions about what to do please contact Rastergraf for assistance 4 5 2 EEPROM Write Enable The has an EEPROM that be loaded with variety of start up parameters as well as manufacturing related information However due to problems with Pericom s EEPROM program it is best not to use it A jumper must be installed to allow the EEPROM to be reprogrammed 4 4 Installing Your PMX P or PME P Board Rastergraf Figure 4 1 Jumper Locations 27 021 bo NG gt mm D SEE G e arc 57 ec 2 gt mo een 2 2 5 90109 A EGRE o ie x ms mum 2 a
18. es of executable programs except those in code fragments are in bold Commands in code fragments are preceded by the system prompt percentage sign the standard prompt in UNIX s C shell or hash mark the standard UNIX prompt for the Super User lt CR gt stands for the key on your keyboard labeled RETURN or ENTER Note boxes contain information either specific to one or more platforms or interesting background information that is not essential to the installation Caution boxes warn you about actions that can cause damage to your computer or its software Warning boxes warn you about actions that can cause bodily or emotional harm Rastergraf Chapter I General Information PMX P General Information 1 1 Rastergraf 1 1 Introduction The Rastergraf PMX P and part of Rastergraf s line of active and passive interface adapters and carriers for PCI and CompactPCI computers The carrier board enables an module to be used in PCI slot Its design enables the PMX P with XMC card installed to fit in one standard 32 bit or 64 bit PCI or PCI X slot and allows adjacent slots in the computer to be occupied and for the computer to be completely closed up Optional breakout connectors provide access to the Pn4 PMC and Pn6 XMC I O connectors The carrier board enables standard PCI Express PCIe board to be used in P
19. igure 1 1 PMX P Functional Outline it a 1 3 Figure 1 2 PMEP Functional 1 4 Figure 4 1 Jumper Locations iei tee edi dar 4 5 Rastergraf PE MESE ETE ELDER MET i Introduction This manual provides information about how to configure install and program the Rastergraf PMX P and PME P PCI Express to PCI PCI X Adapters for 32 bit and 64 bit computers with PCI or PCI X slots For the sake of brevity the term PMX PME will be used when referring to the two boards collectively PCI X 15 plug compatible high performance superset of PCI and allows the bus speed to operate at up to 133 MHz This manual is broken down into five chapters Chapter 1 General Information Chapter 2 Specifications Chapter 3 Connector Pinouts and Cable Information Chapter 4 Installing Your PMX P or PME P Adapter Board Chapter 5 Troubleshooting Chapter I provides background material about the PMX PME boards and it is not essential for the hardware or software installation If you want to perform the installation as quickly as possible start with Chapter 4 If you have problems installing the hardware refer to Chapter 5 for help Introduction 1 Rastergraf Getting Help This installation manual gives specific steps to take to install your Rastergraf board There may well be variables specific to your computer configu
20. ike an extender card and in most cases there is no way to close up the box To see the difference please see Figures 1 1 and 1 2 Please note that it is beyond the scope of this manual to deal with the selection and use of actual or PCIe cards solving their I O problems or software We can only advise on the connection between them and the CPU host 4 2 Comments Concerning XMC boards XMC board specifications are bit mess VITA 42 0 defines the card form factor differential pair locations on the connector and some common signals However 42 0 doesn t require a particular use of the differential pairs Several dot or subspecifications do that and even then things are not nailed down very well VITA 42 3 is used for implementing PCI Express Gen1 on the XMC card It envisions the possibilities of a single x1 to x16 link or even two to x8 links This makes it IMPERATIVE that you know what your XMC board is designed to do BEFORE you plug it into the PMX P The PMX P is designed for use with XMC boards that have a single x1 to x4 PCle port located on Pn5 It will work with an x8 but only x4 wide link will be active The second connector in location Pn6 is used only for I O It should not cause any harm to plug an x16 XMC board which would use lines on Pn6 into the PMX P but you still will have only an x4 PCle connection Please contact Rastergraf support if you have questions WARNING
21. ith 39 matched length pairs I XMC Board 9 OOF HT are siz ES UU8 aas ui 1 Pn4 to 68 pin E 2E ESE Lava att EP PES VHDCI connector with ANNAN 32 matched length pairs 32 64 bit PCI PCI X Host Connector General Information 1 3 Rastergraf 1 3 Feature Summary Short PCI board form factor e 32 64 bit 33 66 100 133 MHz PCI PCI X operation e PCI 2 3 and PCI X 1 0 compliant with Universal PCI signaling e PCIe 1 1 specification compliant supports PCIe x1 x2 or x4 Uses Pericom PI7C9X130 PCI Express to PCI PCI X Bridge e PCIe socket accepts up to x16 only up to x4 is actually connected Test Point pins and LED indicators for most on board power supplies Requires host supplied 3 3V 5V 12V and 12V e PCIe hot swap is not supported LM75 thermal sensor Figure 1 2 PME P Functional Outline Target PCI Express Board LEDs amp Test Points 32 64 bit PCI PCI X Host Connector General Information 1 4 Rastergraf
22. mpedance controlled verified with SPECCTRA advanced noise rules and simulated with less than 25 mV trace to trace parallel or layer to layer PCI Revision 2 2 and PCI X Revision 1 0 One PCI 2 2 compatible load See Sections 2 2 and 2 3 Note that the PCI Host MUST supply 3 3V Board PRSNT1 2 pins advertise as requiring up to 25W 0 26 kg 0 56 Ib Operating temperature 0 to 70 C Storage 40 to 85 C Humidity 5 to 95 non condensing Rastergraf 2 2 Specifications Unique to the PMX P Target Interface PCIe Access I O Access Standards Compatibility Power Requirements One VITA 42 0 compliant XMC module The uses the Samtec ASP 103612 04 which is the Low Insertion Force lead free preinstalled solder balls version see Samtec Listing It is designed to mate with the ASP 103614 04 See Section 4 3 for more information Due to features of the Samtec connector there is a limit of approximately 75 100 insertion removal cycles Uses XMC Pn5 Follows VITA 42 3 Specification for PCI Express on XMC Supports a single x1 x2 or x4 PCIe connection See Section 3 2 for more information XMC Front Panel and or PMX P breakout connectors which support PMC Pn4 to 68 pin VHDCI and Pn6 to dual 68 pin VHDCI connectors The Pn4 breakout follows VITA 46 9 P64s pinout but the connector is 68 pin VHDCI Signals are routed as 32 matched length pairs The set of 32 pairs match length to
23. r Pinouts 3 2 a Pn4 VHDCI 68 135GND 35 GND c 3 E 3 5 5 Hm VHDCI 68 ae 58 60 4 802 fam Honda HDRA EC68LFDT VHCDCI Connector Rastergraf 3 2 PMX P Pn5 Target VITA 42 3 PCIe Connector Pan n c n n c 10 GND GND TDO GND GND GAO Pi ee ee om won re ovans moon m Notes The table above follows PCIe Electromechanical Specification PCIeES naming conventions Note that for some reason VITA 42 3 Section 4 2 3 swaps the R and T part of the data pair naming relative to the definition provided in PCIeES 1 1 Section 5 1 default PETpx PETnx pins the Transmitter differential pair of the connector shall be connected to the PCI Express Transmitter differential pair on the system board and to the PCI Express Receiver differential pair on the add in card n c not connected RFU Reserved for Future Use VPWR can be connected to 5 or 12 See Section 4 5 for more information about power GAO GA2 MPRES and MVMRO not used Pulled up to 3 3V thru 5 1K MRSTI connected PCI PCI X RESET MRSTO MBIST WAKE and ROOTO not connected MSDA connected to PCI PCI X SDA MSCL connected to PCI PCI X SCL JTAG signals connected to PCI PCI X signals JTAG I O looped thru XMC board 3 3Vaux connected to PCI PCI X 3 3Vaux Connector Pinouts 3 3 Rastergraf
24. ration that this manual does address Normally the default values given in this manual will work If you have trouble installing or configuring your system first read Chapter 6 Troubleshooting If this information does not enable you to solve your problems do one of the following 1 call Rastergraf technical support at 541 923 5530 2 send E mail to support rastergraf com Board Revisions This manual applies to the following board revision levels Fab Rev 0 Manual Revisions Revision 1 0 November 10 2009 First released version Revision 2 0 September 7 2010 Some revisions Revision 2 1 April 29 2014 Minor corrections Introduction 2 Rastergraf Notices Information contained in this manual is disclosed in confidence and may not be duplicated in full or in part by any person without prior approval of Rastergraf Its sole purpose is to provide the user with adequately detailed documentation to effectively install and operate the equipment supplied The use of this document for any other purpose is specifically prohibited The information in this document is subject to change without notice The specifications of the PMX P and PME P Adapter boards and other components described in this manual are subject to change without notice Although it regrets them Rastergraf assumes no responsibility for any errors or omissions that may occur in this manual Customers are advised to verify all inform
25. s IC failures and reduced MTBF With proper forced air cooling IC temperatures will be less than 35 degrees C Troubleshooting 5 3 Rastergraf Warranty The PM Series boards are warranted to be free from defects in material or manufacture for period of 12 months from date of shipment from the factory Rastergraf s obligation under this warranty is limited to replacing or repairing at its option any board which is returned to the factory within this warranty period and is found by Rastergraf to be defective in proper usage This warranty does not apply to modules which have been subjected to mechanical abuse electrical abuse overheating or other improper usage This warranty is made in lieu of all other warranties expressed or implied All warranty repair work will be done at the Rastergraf factory Return Policy Before returning module the customer must first request Return Material Authorization RMA number from the factory The RMA number must be enclosed with the module when it is packed for shipment A written description of the trouble should also be included Customer should prepay shipping charges to the factory Rastergraf will prepay return shipping charges to the customer Repair work is normally done within ten working days from receipt of module Out of Warranty Service Factory service is available for modules which are out of warranty or which have sustained damage making them ineligible for warranty r
26. tor 0 Q 5 gt gt Q 5 69 7 B71 B72 B7 B74 B75 2 e 3 Q 5 gt Q gt 76 Q 5 gt gt M SI SI 867 Bos B69 B70 B71 B72 B73 B74 875 876 577 ae me Notes table above follows PCIe Electromechanical Specification 1 1 n c not connected RESV Reserved for Future Use 3 3 and 12 are current limited on Rev 1 not Rev 0 See Section 4 5 for more information about power PERST connected to PCI PCI X RESET H WAKE connected to a pullup to 3 3 Vaux 3 3Vaux connected to PCI PCI X 3 3Vaux Hot Swap function not supported SMDAT connected to PCI PCI X SDA SMCLK connected to PCI PCI X SCL JTAG signals connected to PCI PCI X signals JTAG I O looped thru PCIe board Connector Pinouts 3 7 Rastergraf 3 5 PMX P and PME P PCI PCI X Host Connector 3 5 1 PCI PCI X Bus 32 Bit Connector Pin Signal Name Pin B3 5 B7 B13 B15 B17 GND A17 B19 B20 ADI30 A20 B23 ADI27 AD 26 A23 B26 CBEI3 A26 B29 ADI21 AD 20 A29 B30 B31 B32 AD I7 AD 16 A32 Connector Pinouts 3 8 Rastergraf 3 5 1 PCI PCI X Bus 32 Bit Connector continued Pin B33 B34 B35 B36 B37 B38 B39 B40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
27. x16 PCIe However the intrinsic capability of the PI7C9X130 bridge is limited to a maximum of x4 so anything beyond that is ignored Also you can use either PCIe 2 5Mb s links or Gen2 5 Mb s links But the bridge is Genl so the data links will operate at 2 5Mbs At the time of this writing no standalone Gen2 PCI PCle bridge is commercially available It is unlikely that you will run into trouble trying to use any sort of PCIe card EXCEPT high power graphics boards The PME P advertises to the PCI PCI X host on the PCI PRSNT1 and PRSNT2 pins that it is a 25 watt board which means the host should supply that much However it is not clear than most systems actually limit power to the slots Therefore please exercise caution and don t try to run a board that needs more than 25 watts Installing Your PMX P or PME P Board 4 3 Rastergraf 4 4 Unpacking Your Board When you unpack your board inspect the contents to see if any damage occurred in shipping If there has been physical damage claim with the carrier at once and contact Rastergraf for information regarding repair or replacement Do not attempt to use damaged equipment Caution Be careful not to remove the board from its antistatic bag or container until you are ready to install it It is preferable to wear grounded wrist strap whenever handling computer boards 4 5 Changing Jumpers In the following subsections please refer Figure 4 1 for jump
Download Pdf Manuals
Related Search