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SH7729R CPU Board HS7729RSTC01H User`s Manual

1. Menu Bar Pull Down Menu User s Manual This Manual View Menu Breakpoints O 3 10 3 15 4 2 2 Command Line O Disassembly O I O Area O Labels O Locals O 3 14 Memory O 3 11 Performance Analysis O Profile List O Profile Tree O Registers O 3 8 Source O 3 6 2 Status O 3 9 4 2 4 Trace O Watch O Cache Control 4 2 6 Run Time 3 16 4 2 5 Simulated I O Window 4 2 7 Run Menu Reset CPU O Go O 3 9 Reset Go O Go To Cursor O Set PC To Cursor O Run O Step In O 3 13 1 Step Over O 3 13 3 Step Out O 3 13 2 Step O Halt O 64 RENESAS Table 4 1 Menu Bar Memory Menu Pull Down Menu Refresh Hitachi Debugging Interface User s Manual HDI Window Menus and Related Manual Entries cont This Manual Load Save Verify Test Fill Copy Compare Configure Map Configure Overlay Setup Menu Status bar Options Radix Customize Configure Platform 3 5 4 2 1 Window Menu Cascade Tile Arrange Icons Close All Help Menu Notes QI BG Wo Index Using Help Search for Help on About HDI Function not supported Only CPU board ROM and RAM information display is supported User program is executed after setting PC to H ACO00000 Function
2. e e eeee oe aaa aan 135 7 2 User Program Using SCE ZA dz A Ad wi tie ee 137 1 2 1 Cieation of SCI Drivers z oi o O O a i 137 7 2 2 _ SCl Related Register SettingS uuee eee aaa aaa 138 1 3 Sample Program esi i o O eere A BA AA R GREW EA O 140 iv RENESAS Section 1 Overview 1 1 Features The SH7729R CPU board hereafter referred to as the CPU board supports the evaluation of the functions and performance of the Hitachi SH7729R microcomputer and the development and evaluation of systems that incorporate the SH7729R The features of this CPU board are as follows e Supports user expansion boards Has an expansion bus connector for I O of signals conforming to the SH7729R external bus specifications to which expansion boards developed by the user to increase memory and I O can be connected and evaluated e Supports the maximum operating frequency Allows evaluation at 200 MHz internal operating frequency which is the maximum frequency of the SH7729R e Interface For interfacing with IBM PC compatible as the host computer a serial interface that conforms to RS 232C one channel is provided The Hitachi Debugging Interface HDI is also provided as host interface software e Enables user program evaluation Up to 15 5 Mbytes of a user program can be loaded by serial interface into the user memory and be evaluated e Support for PCMCIA PCMCIA interface hardware is provided as standard equipment so th
3. 89 RENESAS Table 5 5 Pin Assignment of Expansion Connector CN6 cont Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function 58 GND 73 TXD1 SCPT 2 88 GND 59 MCST O J PINTT O 74 GND 89 IRQO 1 PTC 0 60 GND 75 SCK1 SCPT 3 90 GND 61 MCST 1 PINTT1 76 GND 91 IRQ1 1 PTC 1 62 GND 77 RXD2 SCPT 4 92 GND 63 MCS 2 PINT 2 78 GND 93 IRQ2 1 PTC 2 64 GND 79 TXD2 SCPT 4 94 GND 65 MCST 3 PINT 3 80 GND 95 IRQ3 1 PTC 3 66 GND 81 SCK2 SCPT 5 96 GND 67 _Wakeup 82 GND 97 IRQ4 1 PTD 3 68 GND 83 RTS2 SCPT 6 98 GND 69 RESETOUT 84 GND 99 Reserve PTD 2 70 GND 85 CTS2 SCPT 7 100 GND 71 RXD1 SCPT 2 86 GND 72 GND 87 PTH 6 Notes 1 Do not connect the Reserve pin 2 Some signals are converted and input to the CPU or output to the expansion connector 90 as follows 1 IRQ 4 0 Invalid and not reserved during monitor program execution RENESAS Table 5 6 Pin Assignment of Expansion Connector CN7 Pin No Pin Name Pin Function Pin No Pin Name Pin Function 1 Reserve 11 AN 4 PTL 4 2 AVss 12 AVss 3 AN 0 PTL 0 13 AN 5 PTL 5 4 AVss 14 AVss 5 AN 1 PTL 1 15 AN 6 DA 1 PTL 6 6 AVss 16 AVss 7 ANI2 PTLI 2 17 AN 7 DAT 0 PTL 7 8 AVss 18 AVss 9 AN 3 PTL 3 19 Reserve 10 AVss 20 AVss Note Do not connect the Reserve pins 91 RENESAS CKIO expansion connector BREQ tBREQH
4. 115200 bit s 66 7 MHz Figure 4 4 System Status Window RENESAS 71 Description The items listed in the following table are displayed in the System Status window Table 4 6 System Status Window Display Items Page Item Description Session Target system Indicates whether the CPU board is connected or not Session Name Displays the session file name Program Name Displays the load module file name Platform Connected to Displays the name of the connected CPU board monitor program CPU Displays the target CPU and endian setting Mode Displays the CPU processor mode privileged mode or user mode Cache Status Shows whether the cache is enabled or disabled MMU Status Shows whether the MMU is enabled or disabled I O definition Displays the selected I O register definition file Clock Displays the clock frequency CPU operating frequency and external bus frequency being used Target DLL Version Indicates the version of the target DLL for connection to the CPU board Monitor Version Displays the monitor program version Run Status Displays the user program execution status Run Being executed Break Stopped Break Cause Displays the cause of the program stopping at break Run Time Count Shows the time from the start of the user program to the break When the run time count function is disabled Oh Omin Os Oms 0 0us is displayed Comm port baudrate Indicates the dat
5. IRQOUT STATUS1 0 STATUS1 0 vices cke a CKE BREQ NMI WAIT U2 FPGA BREQ NMI u19 WAIT BACK RSTout Control VHC244 BACK circuit RESETP IRQL 4 0 U27 RESETP LS279 sw12 H 5V es Ni Clock Divider or GW Driver selector Mi CKIN Se RR OSC2 Divider x1 8 14 7456MHz TCLK 10 ka RD CS0 CS2 CS3 CS4 RD o SG con u16 GS5 CE1A CS5ICETA dra CS6 CE1B CS6 CE1B 33N RD WR RD WR 10 kg RAS2L BS onsl Saat i GA EGAN CASHLCASHH MASTA RASSL Figure 5 11 Configuration of User Expansion Board Interface Circuit CN3 94 RENESAS SH7729R IRL 3 0 IRQ 3 0 IRQ4 RESETM CTS2 RTS2 RXD1 2 TXD1 2 SCK1 2 CE2A 2B DACKO 1 DRAKO 1 WAKEUP BACK CAS2L 2H RAS2U 3U DREGO 1 10IS16 GA ADTRG PTC 7 0 PTD 2 PTE 7 0 PTF 7 0 PTG 6 0 PTH 6 AN 7 0 PTL 7 0 Expansion connector U2 FPGA 33V 3 3V U19 4 7 ko 4 7 kd VHC244 IRQ 3 0 Control circuit 3 3 V 3 3 V RXD1 2 TXD1 2 SCK1 2 CE2A 2B DACKO 1 DRAKO 1 WAKEUP BACK CAS2L 2H RAS2U 3U DREQO 1 IOIS16 CA ADTRG PTC 7 0 PTD 2 PTE 7 0 PTF 7 0 PTGI 6 0 PTH 6 AN 7 0 PTL 7 0 Figure 5 12 Configuration of User Expansion Board Interface Circuits CN6 CN7 RENESAS CPU board User expansion board o 6 g 1011 08 L 2088 loy z0 c a Adjust the height using spacers Uni
6. i g a Kine EE ac000038 ac000040 ac000044 ac000045 ac00004c ac000058 ac00005c ac000060 Break Step Figure 3 32 Program Window Before Step Over Execution 48 RENESAS ra Hitachi Debugging interface Sort SH 729R CPU board E File Edit view Run Memory Window Help eae s Seay FANHL AP PHD Fa sO M5 555 io Wi Bl ME 0 8 2 BA W Value A BP Source a ac000000 _main void main void ASTI long a 10 ECA long j j int i min max gt 16882 ac000004 for i 0 1 lt 10 i Of D 13023 ac00000c j ran ac000014 1f j lt OF ac000018 ac00001c fa a fa N e i g 3 Kine E ac000038 ac000040 ac000044 ac000045 ac00004c ac000050 ac00005c ac000060 For Help press F1 Figure 3 33 Program Window Step Over When the last statement of the change function is executed the data of variable a which is displayed in the Watch Window window is sorted in descending order 49 RENESAS 3 14 Displaying Local Variables The user can display local variables in a function using the Locals window For example we will examine the local variables in the main function which declares five local variables a j i min and max e Select Locals from the View menu The Locals window is displayed If no local variable exists none is displayed on the Locals window e Select Step In from the Run
7. menu to execute another step The local variables and the corresponding values are displayed on the Locals window Locals LOl ol x Y alue Oxacf ffd4 1166 Figure 3 34 Locals Window e Double click the symbol in front of array a in the Locals window to display the elements of array a e When the elements of the array a are referenced before and after executing the sort function in the program the random data should be sorted in descending order This confirms that the program is operating normally 50 RENESAS 3 15 Software Break Function The CPU board has software break function With the HDI a software breakpoint can be set using the Breakpoints window The CPU board can set up to 255 software breakpoints Setting a software breakpoint is described below e Select Breakpoints from the View menu The Breakpoints window is displayed e Right click in the Breakpoints window to open a pop up menu and select the Delete All button to cancel all the breakpoints that have been set A dialog box will prompt you to confirm the deletion of breakpoints Click Yes to delete the breakpoints Breakpoints ol Ol x Figure 3 35 Breakpoints Window Before setting software break 51 RENESAS Right click in the Breakpoints window to open a pop up menu and select Add The Add Edit Breakpoint dialog box is displayed Either an address or a symbol can be entered e Enter change and che
8. tBREQS tBACKD expansion connector BACK ig CPU tCBACKD BACK expansion connector tCOFF1 A RD CSn RD WR CAS RAS WEn tCOFF2 expansion connector D expansion connector Figure 5 8 Bus Release Timing 1 CKIO expansion connector BREQ a tBREQS tBACKD expansion connector BREQ BACK CPU BACK expansion connector A RD CSn RD WR CAS RAS WEn P expansion connector D Sons expansion connector Figure 5 9 Bus Release Timing 2 92 RENESAS Table5 7 AC Specifications Parameter Minimum Maximum tBREQH tBREQH tBREQH tBREQS tBREQS tBREQS tBACKD tBACKD tBACKD tCBACKD 25 5 ns tCOFF1 29 7 ns tCOFF2 30 1 ns tCON1 29 7 ns tCON2 30 1 ns Note Equivalent to CPU AC specifications CPU board User expansion board 3 3 V Characteristic impedance 0 54Q 100Q Make the line between the expansion bus connector and receiver as short as possible LVT series VHC series etc IDT49FCT3805 loh 8 mA loh 16 mA Expansion bus connector When the characteristic impedance of the user expansion board is the same as that of the CPU board terminal resister R1 100 Q and R2 160 Q Figure 5 10 Example of CKIO Terminal Resistor Connection 93 RENESAS 3 3 V SH7729R ow Expansion 4 7kQ U123 15 connector BEM A 25 0 WE 3 0 WEJB 0 U4 7 D 31 0 QS3384 A DI31 0 3 3V U18 4 7 KQ IRQOUT
9. 0 No STSCHG interrupt request 1 STSCHG interrupt request by the slot 0 I O card Bit 3 POCDC card detection interrupt This indicates that either PCCOCD2 or PCCOCD1 has changed a card has been inserted or removed The condition for setting the bit is a change in signal level it is cleared by writing 0 to it The interrupt can be masked by PCCOCSCIER bit 3 0 No change in PCCOCD2 PCCOCD1 1 Either PCCOCD2 or PCCOCD1 has changed Bit 2 PORC ready change interrupt In cases where the card of slot 0 is a memory card this bit is set to 1 when the PCCORDY signal changes in cases where the card is an I O card this bit is always 0 The condition for setting the bit is when the RDY BSY pin changes from low to high there is a transition from a busy state to a ready state the bit is cleared by writing 0 to it The interrupt can be masked by PCCOCSCIER bit 2 0 No change in RDY BSY 1 RDY BSY changed from low to high level 103 RENESAS Bit 1 POBW battery voltage low interrupt data is preserved but the battery must be replaced In cases where the card of slot 0 is a memory card this bit is set to 1 when the PCCOBVD2 BVD1 signal indicates a drop in battery voltage in the case of an I O card this bit is always 0 The condition for setting this bit is when PCCOBVD2 Low and in addition PCCOBVD1 High the bit is cleared by writing O to it The interrupt can be masked by PCCOCSCIER bit 1 0 Memory card of slot 0 does not indica
10. RENESAS 3 4 Setting up the CPU Board The following conditions can be set up on the CPU board before downloading the program e Connection method e I O definition file e Options on program load The following describes how to set up the CPU board for the tutorial programs 3 5 Setting the Monitor Setup Dialog Box e Select Configure Platform from the Setup menu to set configuration The Monitor Setup dialog box is displayed Monitor Setup Target Monitor Comms Settings COO Comms Port COM1 i Cancel Baud Rate 115200 Help 1 0 definition file SH7729R Browse Jo Download with veny I Delete breakpoints when program is reloaded I Reset CPU when program has been downloaded Figure 3 5 Monitor Setup Dialog Box 27 RENESAS Set options as follows Table 3 3 Setting the Monitor Setup Dialog Box Option Default Value Comms Port COM1 Select from among COM1 COM2 COM3 or COM4 as the host computer serial port Baud Rate 115200 Sets the serial baud rate Select either 57600 bit s or 115200 bit s to match the setting of jumper J7 Connection is not possible at any other setting I O definition file SH7729R Sets the I O register definition file The SH7729R definition file is set as default On selecting a file the I O Registers window accessed from the View menu can be used to display register information Download with verify The CPU
11. RENESAS Table 5 1 Specifications cont Item Expansion board interface Specifications Three expansion connectors CN3 CPU board 8817 180 170L manufactured by KEL CORPORATION User side 8807 180 170L manufactured by KEL CORPORATION Note Gold plated thickness No mark Flush D 0 25 um or more CN6 CPU board 8931E 100 178S manufactured by KEL CORPORATION User side 8925 100 179 manufactured by KEL CORPORATION Note Strain relief E Yes R No CN7 CPU board 7620 6002SC manufactured by 3M Company User side 7920 7500SC manufactured by 3M Company PCMCIA Memory card or I O card x 2 slots E10A emulator interface CN8 CPU board type number 10236 5202JL manufactured by 3M Company Switches SW1 Manual reset switch SW2 Abort switch SW3 Power supply switch External Board Width 210 mm Length 150 mm dimensions Product Width 227 mm Length 167 mm Height 50 mm 79 RENESAS 5 3 Memory Map Memory map of the CPU board is shown in figure 5 2 Each area of the CPU is allocated as follows Area 0 Monitor program area Allocated to flash memory on board registers and monitor input output Bus width is 16 bits fixed Area 1 CPU reserved area Area 2 Expansion bus area Area 3 16 Mbytes of SDRAM is allocated The first 15 5 Mbyte area is assigned to the user area and the remaining 0 5 Mbyte area is assigned to the monitor program work area Bus width is 32 bits fixed Area 4 Ex
12. Simulated I O Window window line by line by using the SCIO The sample program files including source and object files are automatically copied to the Sample directory under the HDI installation directory Load the compiled load module Simio abs set the program counter and stack pointer values PC H AC000000 R15 H ACF80000 and click the Go button to execute the program W Simulated I O Window Ee x Test Start gt ABCDEFGHIJKLMN ABCDEFGHIJKLHN gt 12345 12345 gt xx Figure 7 1 Executing the Sample Program Note The HEW work space supplied by this sample program was created by HEW Version 1 1 Release 4 The program cannot be opened by a HEW version earlier than 1 1 For details refer to the Hitachi Embedded Workshop User s Manual 140 RENESAS File Configuration Table 7 3 shows the files that compose the sample program Table 7 3 Sample Program Files File Name install directory Sample Simio hws Description HEW work space file install directory Sample Simio hww HEW HWW file install directory Sample Simio Brkaddr inc Branch address definition install directory Sample Simio Env inc EXPEVT INTEVT register definition install directory Sample Simio Intprg src Interrupt processing program install directory Sample Simio lodefine h SH7729R register definition install directory Sample Simio lolevel c SCI driver program install directo
13. at a specified rate Use the Go described in section 3 9 Executing the Program to confirm that the program is executed up to the sort function statement at address H AC000038 ac000040 min ac000044 max ac000048 min ac00004c max ac000050 change 3 ac000058 min al ac00005c max a 0 ac000060 ac00006c _sort pu sort long a long t int i j k gap ac000070 ac000074 vitleC ap gt 0 Jf ac000078 Cs 0 k lt gap k ac000080 for i k gap 1 lt 10 J i gap JI 3000098 r Falitsalieep t gt M Figure 3 25 Program Window Step Execution 44 RENESAS 3 13 1 Executing Step In Command The Step In steps into the called function and stops at the first statement of the called function e To step through the sort function select Step In from the Run menu or click the Step In button in the toolbar Figure 3 26 Step In Button Source ac000038 Break sort a ac000040 min alo ac000044 max al 9 ac000048 min i ac00004c max ac000050 chan ac000058 min ac00005c max ac000060 ASY a NNQNNN stoi long t int i j k gap acO00070 ac000074 diec te gt 0 Jf ac000078 ste sa TAT k ac000080 i k gap i lt 10 i i gap ac000098 for Gat pan tanki Js xt Pt Figure 3 27 Program Window Step In e The highlighted line moves to the first statement of the sort function in the Program window 45 RENESAS 3 13 2 Executing Step Out Comma
14. been used initiate this HDI with Run as follows without using the session files lt Directory path name in which HDI is installed gt hdi n n initiates the HDI without loading the recently used session files RI ET If there is another session file of a different debug platform the following error message is displayed RENESAS 131 invalid target system lt recently used debug platform name gt 6 When another HDI is uninstalled after installation of this HDI some functions may not work correctly In this case re install this HDI 7 For operations such as Fill Memory and Test Memory it may take a few minutes to complete operation This depends on the size of data specified Since only 5 seconds is specified for the timeout time in the HDI of the CPU board the Command not ready error may occur In such cases the results of the operation will not be guaranteed therefore specify a smaller size and execute the operation again 8 The access size and target start and end addresses can be specified in the Fill Memory dialog box If the access size does not match the specified start address the HDI will treat them as follows e Fill size end address start address e The fill size is decreased to the nearest integer multiple of the access size e The start address is decreased to the nearest integer multiple of the access size e If the fill size is smaller than the access size the fill siz
15. download program to RAM areas Otherwise the operation cannot be guaranteed 6 When a Motorola S type file is downloaded two menus Load Program and Load Memory can be used but the Load Program is recommended because it can transfer data faster 23 HDI 1 In this HDI the Command Line menu can be selected but operation of the command entered from the command line cannot be guaranteed Do not use the command line 2 This HDI does not support software breakpoint setting in the Select Function dialog box described in section 10 Selecting Functions in the Hitachi Debugging Interface User s Manual 3 If the following memory contents are displayed in the Memory window they will be incorrect e Word access from address 2n 1 e Longword access from address 4n 1 4n 2 or 4n 3 The font size used in the memory window must be 4 or larger In one window up to 32768bytes can be displayed 4 For each Watchdog Timer register there are two registers to be separately used for write and read Table 6 2 Watchdog Timer Register Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter 5 Since different versions of HDI cannot be used at the same time re install this HDI whenever another previously installed HDI is used If another HDI has
16. function information Note No symbol or memory information is saved in the session files If changes are to be used again in future they must be saved separately For details refer to the Hitachi Debugging Interface User s Manual 60 RENESAS 3 18 What Next In this tutorial we have introduced as examples program debugging using the CPU board and the HDI Further details on the use of the HDI can be found in the Hitachi Debugging Interface User s Manual available in the supplied CD R RENESAS 61 62 RENESAS Section 4 Descriptions of Windows 4 1 HDI Windows HDI window menu bars and the corresponding pull down menus are listed in table 4 1 A O mark and or the relevant section number is shown in the table when menu description is included in the Hitachi Debugging Interface User s Manual or in this manual Menu items shown in gray on the screen are not available Table 4 1 Menu Bar File Menu Pull Down Menu New Session HDI Window Menus and Related Manual Entries Hitachi Debugging Interface User s Manual This Manual Load Session Save Session Save Session AS 3 17 Load Program 3 6 1 Initialize Exit Edit Menu Cut Copy Paste Find Evaluate OOO OOOOO OO O O RENESAS 63 Table 4 1 HDI Window Menus and Related Manual Entries cont Hitachi Debugging Interface
17. in slot 1 is a memory card this bit enables and disables battery replacement interrupts An interrupt request is generated when PCCICSCR bit O is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 Battery replacement interrupt disabled 1 Battery replacement interrupt enabled 9 PCC voltage control register PCCVCR BE Apr W AJ Name VCCO VGCO VPPO VPPO VCC1 VCC1 VPP1 VPP1 SEL1 SELO SEL1 SELO SEL1 SELO SEL1 SELO aw je r Initial 1 1 1 1 value This register is used to control the power supply for slots 0 and 1 Four control signals for each slot are directly driven either high or low Bits 7 0 0 Corresponding signal driven low 1 Corresponding signal driven high 111 RENESAS PCC Power Supply Correspondence VCCXSEL1 VCCXSELO VCC Output VPPXSEL1 VPPXSELO VPP Output Settings 0 0 OFF 0 0 OV 0 1 5V 0 1 VPP 1 0 3 3V 1 0 VCC 1 1 OFF 1 1 Hi Z 5 4 4 E10A Emulator Interface The CPU board is equipped with a Hitachi UDI port connector CN8 to which an SH7729R E10A emulator can be connected SH7729R H UDI and AUD signals are connected directly to this connector When connecting an E10A emulator always be sure to turn on the jumper J11 on the CPU board Figure 5 16 shows the pin arrangement of the Hitachi UDI port connector CN8 Table 5 11 shows the pin assignment for the Hitachi UDI port connector CN8 Pin 36 Hitachi UDI Port connector Figure 5 16 H
18. is displayed in this window e Data input from the keyboard of the host computer is displayed in this window in addition to being sent to the CPU board This window is displayed on selecting the Simulated I O Window item from the View menu Right clicking the mouse on this window displays the following pop up menu Copy Copies the text appearing in highlighted to the Windows clipboard Paste Pastes the contents of the Windows clipboard to the Simulated I O Window and sends the same contents to the CPU board Clear Window Clears the contents of the Simulated I O Window window 75 RENESAS Window W Simulated I O Window Test Start gt ABCDEFGHIJKLMN ABCDEFGHIJKLHN gt 12345 12345 gt xxl Figure 4 7 Simulated I O Window Window The above is the window displayed when the sample program supplied with this CPU board is used For details on the sample program refer to section 7 3 Sample Program Note When using the Simulated I O Window window an interrupt handler must be prepared in the user program For details on the interrupt handler refer to section 7 Creation of User Interrupt Handler 4 2 8 Command Line Window The SH7729R CPU board does not guarantee the Command Line window operation do not use the Command Line window 76 RENESAS Section 5 CPU Board Specifications 5 1 Block Diagram A block diagram of the CPU board is shown in figure 5 1 Abort switch
19. license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein SH7729R CPU Board HS7729RSTCOIH User s Manual QENESAS ADE 702 263 Rev 1 0 08 20 01 Hitachi Ltd HS7729RSTCO1HE B Cautions 1 Hitachi neither warrants nor grants licenses of any rights of Hitachi s or any third party s patent copyright trademark or other intellectual property rights for information contained in this document Hitachi bears no responsibility for problems that may arise with third party s rights including intellectual property rights in connection with use of the information contained in this document 2 Products and product specifications may be subject to change without notice Confirm that you have received the latest product standards or specifications before final design purchase or use 3 Hitachi makes every attempt to ensure that its products are of high quality and reliability However contact Hitachi s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury such as
20. menu through which breakpoints can be set changed deleted enabled or disabled RENESAS 3 11 Viewing Memory The user can view the contents of a memory block in the Memory window For example to view the memory contents corresponding to the main in word size Select Memory from the View menu enter main in the Address edit box and set Word in the Format combo box Open Memory Window X Address main Format word IE Figure 3 18 Open Memory Window Dialog Box e Click the OK button The Memory window showing the specified area of memory is displayed Word Memory _mainn O X Figure 3 19 Word Memory Window 39 RENESAS 3 12 Watching Variables As the user steps through a program it is possible to watch that the values of variables used in the user program are changed For example set a watch on the long type array a declared at the beginning of the program by using the following procedure e Click the left of displayed array a in the Program window to position the cursor e Click the Program window with the right mouse button and select Instant Watch from a pop up menu The following dialog box will be displayed Instant Watch x Add watch Figure 3 20 Instant Watch Dialog Box 40 RENESAS e Click Add Watch button to add a variable to the Watch Window window Watch Window OMEA Value Oxacf ffd4 Figure 3 21 Watch Window
21. not connect the Reserve pins 2 Some signals are converted and input to the CPU or output to the expansion connector as follows 2 3 A 25 0 See figure 5 11 RSTOUT A low level pulse is output when the CPU is reset at power on when the manual reset switch is pressed or when the reset signal is input from the expansion connector 4 BACK See figures 5 8 5 9 5 11 and 5 12 RENESAS 87 Table 5 4 Pin Assignment of Expansion Connector CN3 cont Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function 151 GND 161 GND 171 GND 152 STATUSO 162 _WAIT 8 172 Reserve 153 GND 163 GND 173 GND 154 PTJ 1 10 164 Reserve 174 Reserve 155 GND 165 GND 175 GND 156 _BREQ 5 166 Reserve 176 Reserve 157 GND 167 GND 177 CKIO 9 158 TCLK 6 168 Reserve 178 GND 159 GND 169 GND 179 GND 160 _NMI 7 170 Reserve 180 GND Notes 1 Do not connect the Reserve pins 2 Some signals are converted and input to the CPU or output to the expansion connector as follows 5 BREQ See figures 5 8 5 9 5 11 and 5 12 6 TCLK Clock input for the timer Jumper J3 selects either the CPU board clock or clock input from the expansion connector 7 NMI Invalid and not reserved during monitor program execution 8 WAIT The result of ORing the WAIT signals from the CPU board resource area 0 and area 6 PCMCIA space on access is input to the CPU 9 CKIO Out
22. other reason the modified contents will be discarded and returned to original value set before program execution 21 Watch 1 Local variables at optimization Depending on the generated object code local variables in a C source file that is compiled with the optimization option enabled will not be displayed correctly Check the generated object code in the mixed display of the Program window If the allocation area of the specified local variable does not exist displays as follows 129 RENESAS Example The variable name is asc asc target error 2010 xxxx 2 Variable name specification When a name other than a variable name such as a symbol name or function name is specified no data is displayed Example The function name is main main 3 Array display When the number of array elements exceeds 1000 the number exceeding 1001 will not be displayed 22 Serial Interface 1 When the bus frequency is set to 33 3 MHz by jumpers J9 and J10 the serial interface baud rate must not be set to 115 200 bit s set the baud rate to 57 600 bit s 2 The CPU board does not control data flow Therefore when transferring a large amount of data from the CPU board to the host computer an overrun error may occur If an error occurs after performing one of the following corrective actions repeat the action In the control panel of the host computer set the serial port to 115 200 bit s and FIFO to the initial state Table 6 1
23. recommended as the swap area CD ROM drive Required to install the HDI Pointing device such as mouse Connectable to the host computer compatible with Windows 95 Windows 98 and Windows NT Power supply for AC power supply adapter Input 100 to 240 VAC 50 60 Hz 0 9 A max Output 5 0 VDC 6 0 A max RENESAS Section 2 Preparation before Use 2 1 CPU Board Preparation A WARNING READ the reference sections shaded in figure 2 1 before using the CPU board product Incorrect operation will damage the user system and the CPU board The USER PROGRAM will be LOST Unpack the CPU board and prepare it for use as shown in figure 2 1 Reference Unpack the CPU board Check the components against the component list Turn on the host computer Procedure s when the CPU Install the HDI Section 2 2 board is used first Component list Turn off the host computer Connect the CPU board to the host computer and AC power supply adapter and when necessary to a PCMCIA card or user expansion board Also be sure to set the jumper on the CPU board Turn on the host computer Procedure when the CPU Turn on the CPU board Section 3 board is used for second time or later Sections 2 4 to 2 9 Start the HDI Figure 2 1 CPU Board Preparation Flow Chart RENESAS 2 2 HDI Installation An example of installing the HDI on an IBM PC compatible machine i
24. right to change wholly or partially the specifications design user s manual and other documentation at any time without notice Target User of the CPU Board This CPU board should only be used by those who have carefully read and thoroughly understood the information and restrictions contained in the user s manual Do not attempt to use the CPU board until you fully understand its mechanism It is highly recommended that first time users be instructed by users that are well versed in the operation of the CPU board RENESAS LIMITED WARRANTY Hitachi warrants its CPU boards to be manufactured in accordance with published specifications and free from defects in material and or workmanship Hitachi at its option will repair or replace any CPU boards returned intact to the factory transportation charges prepaid which Hitachi upon inspection determine to be defective in material and or workmanship The foregoing shall constitute the sole remedy for any breach of Hitachi s warranty See the Hitachi warranty booklet for details on the warranty period This warranty extends only to you the original Purchaser It is not transferable to anyone who subsequently purchases the CPU board from you Hitachi is not liable for any claim made by a third party or made by you for a third party DISCLAIMER HITACHI MAKES NO WARRANTIES EITHER EXPRESS OR IMPLIED ORAL OR WRITTEN EXCEPT AS PROVIDED HEREIN INCLUDING WITHOUT LIMITATION THEREOF WAR
25. sleep instruction will be executed Table 7 5 Interrupt Source UBC trap Code EXPEVT 1E0 Interrupt Processing in the Sample Program Processing Branches to the CPU board This processing is used by step execution Unconditional trap FF EXPEVT 160 Branches to the CPU board This processing is used by breakpoint function Reserved instruction code exception EXPEVT 180 Branches to the CPU board and informs the occurrence of a reserved instruction code exception Slot illegal instruction exception EXPEVT 1A0 Branches to the CPU board and informs the occurrence of a slot illegal instruction exception CPU address error load EXPEVT 0E0 Branches to the CPU board and informs the occurrence of a CPU address error exception CPU address error store EXPEVT 100 Branches to the CPU board and informs the occurrence of a CPU address error exception DMA address error EXPEVT 5C0 Branches to the CPU board and informs the occurrence of a DMA address error exception NMI EXPEVT 1C0 Branches to the CPU board This processing is used when execution is stopped by using the abort switch SCI RXI 142 EXPEVT 500 Buffers the characters received through the SCI When the HALT code H 12 is received execution branches to the CPU board This processing is used when execution is stopped by the HALT button RENESAS
26. to the CPU as IRQ1 e PCMCIA control Two PCMCIA slots are supported I O cards or memory cards can be used in both slots e Card voltage Both 3 3 V and 5 V are supported e PCMCIA area Both slots use area 6 Because area 6 is further subdivided into eight areas each area is allocated 8 Mbytes PCMCIA supports up to 64 Mbytes in each area and so the CPU board is provided with a bank switching register corresponding to upper addresses A25 to A23 Access procedure is as follows 1 Upper addresses A25 to A23 are written to GCR General Control Register bits 2 to 0 of the slot to be accessed 0 1 2 An area 6 window is accessed according to the card type inserted Allocation of the area 6 space is as shown in figure 5 15 18000000 Slot 0 attribute memory 18800000 Slot 1 attribute memory 19000000 Slot 0 common memory 19800000 Slot 1 common memory 1A000000 Slot 0 I O area 1A800000 Slot 1 1 0 area Not used Figure 5 15 Area 6 Allocation 100 RENESAS Explanation of Registers Table 5 10 lists the addresses and gives explanations of registers related to the PCMCIA interface Table 5 10 PCMCIA Registers and Addresses Register Name Formal Name R W Address PCCOISR PCCO interface status register R H 01800000 PCCOGCR PCCO general control register R W H 01800002 PCCOCSCR PCCO card status change register R W H 01800004 PCCOCSCIER PCCO card status change interrupt R W H 01800006 enable register P
27. 14 TC O ac000018 j acO0O0001c ac000040 min ac000044 max ac000046 min ac00004c max ac000050 hana ac000058 min a 39 ac00005c max a o ac000060 Figure 3 15 Program Window Break Status The user can see the cause of the break that occurred last time in the System Status window 35 RENESAS Select Status from the View menu The System Status window will appear Open the Platform page and check the status of Break Cause System Status Item Connected to CPU Mode Cache Status MMU Status I 0 definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate 36 Status SH7 29R Monitor SH3DSP Big Endian Privileged Mode OFF OFF SH 23R CPU 200 MHz External Bus 66 7 MHz oe mmm dd yyyy Break Breakpoint Oh Omin Os 115200 bit s Figure 3 16 System Status Window RENESAS The System Status window displays the following items in each page Table 3 4 Contents of the System Status Window Page Item Description Session Target system Indicates whether the CPU board is connected or not Session Name Displays the session file name Program Name Displays the load module file name Platform Connected to Displays the name of the connected CPU board monitor program CPU Displays the target CPU and endian setting Mode Displays the CPU processor mode privileged mo
28. 3 7 Setting the Software Breakpoint A breakpoint is one of the easy debugging functions The Program window provides a very simple way of setting a software breakpoint in a program For example to set a breakpoint at the sort function call e Select by double clicking the BP column on the line containing the sort function call ac000004 acO0000c ac000014 acO00018 Source i void main void long a 10 long j int i min for i 0 i lt 10 j_ rand a Di max i OL acO0001c ac000038 e Break ac000040 ac000044 ac0000468 acO0004c ac000050 ac000058 ac00005c ac000060 Naa changet min a 9 1 max a 0 Figure 3 10 Program Window Setting a Software Breakpoint The Break will be displayed on the line containing the sort function to show that a software breakpoint is set Note The software breakpoint cannot be set in the ROM area or the delay slots in the program 32 RENESAS 3 8 Setting Registers Set values of the program counter and the stack pointer before executing the program e Select Registers from the View menu The Registers window is displayed G3 Registers Ol ol x Register Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ACF80000 AC000000 MR 000000000000 D 111000 00000000 gt Figure 3 11 Registers Wi
29. 41 PCCODA15 58 PORESET 8 PCCOAD10 25 PCCOAD4 42 POCE2 59 POWAIT 9 PORD 26 PCCOAD3 43 POVS1 60 NC 10 PCCOAD11 27 PCCOAD2 44 POWE2 61 POREG 11 PCCOAD9 28 PCCOAD1 45 POWE3 62 POBVD2 12 PCCOAD8 29 PCCOADO 46 PCCOAD17 63 POBVD1 13 PCCOAD13 30 PCCODAO 47 PCCOAD18 64 PCCODA8 14 PCCOAD14 31 PCCODA1 48 PCCOAD19 65 PCCODA9 15 POWE1 32 PCCODA2 49 PCCOAD20 66 PCCODA10 16 PORDY 33 POWP 50 PCCOAD21 67 POCD2 17 VCCA 34 GND 51 VCCA 68 GND 98 RENESAS Table 5 9 PCMCIA Card Slot 1 CN9 Pin Assignments Pin No Signal Name Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 GND 18 VPPB 35 GND 52 VPPB 2 PCC1DA3 19 PCC1AD16 36 P1CD1 53 PCC1AD22 3 PCC1DA4 20 PCC1AD15 37 PCC1DA11 54 PCC1AD23 4 PCC1DA5 21 PCC1AD12 38 PCC1DA12 55 PCC1AD24 5 PCC1DA6 22 PCC1AD7 39 PCC1DA13 56 PCC1AD25 6 PCC1DA7 23 PCC1AD6 40 PCC1DA14 57 P1VS2 7 P1CE1 24 PCC1AD5 41 PCC1DA15 58 P1RESET 8 PCC1AD10 25 PCC1AD4 42 P1CE2 59 P1WAIT 9 P1RD 26 PCC1AD3 43 P1VS1 60 NC 10 PCC1AD11 27 PCC1AD2 44 P1WE2 61 P1REG 11 PCC1AD9 28 PCC1AD1 45 P1WE3 62 P1BVD2 12 PCC1AD8 29 PCC1ADO 46 PCC1AD17 63 P1BVD1 13 PCC1AD13 30 PCC1DA0 47 PCC1AD18 64 PCC1DA8 14 PCC1AD14 31 PCC1DA1 48 PCC1AD19 65 PCC1DA9 15 P1WE1 32 PCC1DA2 49 PCC1AD20 66 PCC1DA10 16 P1RDY 33 P1WP 50 PCC1AD21 67 P1CD2 17 VCCB 34 GND 51 68 GND RENESAS VCCB 99 The CPU board PCMCIA interface has the following features e _ RQ control PCMCIA interrupts are input
30. 69 GND 20 D9 1 45 GND 70 A2 2 21 GND 46 D22 1 71 GND 22 D10 1 47 GND 72 A3 2 23 GND 48 D23 1 73 GND 24 D11 1 49 GND 74 A4 2 25 GND 50 D24 1 75 GND Notes 1 Do not connect the Reserve pins 2 Some signals are converted and input to the CPU or output to the expansion connector as follows 1 D 81 0 See figure 5 11 2 A 25 0 See figure 5 11 10 When used as a port signals are limited to the output direction 86 RENESAS Table 5 4 Pin Assignment of Expansion Connector CN3 cont Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function 76 A5 2 101 RAS3L 126 _RD 77 GND 102 A18 2 127 GND 78 A6 2 103 GND 128 Reserve 79 GND 104 A19 2 129 GND 80 A7 2 105 CKE 130 _ CS2 81 GND 106 A20 2 131 GND 82 A8 2 107 Reserve 132 _CS4 83 GND 108 A21 2 133 GND 84 A9 2 109 Reserve 134 _CS5 _CE1A 85 GND 110 A22 2 135 GND 86 A10 2 111 _RSTOUT 3 136 _CS6 _CE1B 87 GND 112 A23 2 137 GND 88 Ali 2 113 _RESETP 138 Reserve 89 GND 114 A24 2 139 GND 90 A12 2 115 GND 140 Reserve 91 GND 116 A25 2 141 GND 92 A13 2 117 GND 142 RD WR 93 CSO 118 _WEO DQMLL 143 GND 94 A14 2 119 GND 144 _IRQOUT 95 GND 120 _WE1 DQMLU 145 GND 96 A15 2 121 GND 146 _BACK 4 97 _BS 122 _WE2 DQMUL 147 GND 98 A16 2 123 GND 148 _CS3 99 GND 124 _WE3 DQMU 149 GND U 100 A17 2 125 GND 150 STATUSI Notes 1 Do
31. A Interface This CPU board is not provided with a PCMCIA driver When using a PCMCIA card please provide your own PCMCIA driver When using a PCMCIA card always be sure that after detecting the card detection signal CDO CD1 the PCMCIA driver enables PCMCIA external buffer control the PODRVE bit or the PIDRVE bit If the buffer is enabled prior to card detection correct operation is not guaranteed E10A Emulator Interface If the monitor is used with the E10A emulator connected correct operation is not guaranteed Moreover with the E10A emulator connected the port functions of the Hitachi UDI and AUD interface signal pins cannot be used Host Interface Software When using this CPU board always use the included Hitachi Debugging Interface HDI If other host interface software is used the operation of the CPU board and of user programs is not guaranteed User Program Execution 1 Abort switch SW2 is connected to the NMI on the CPU Therefore do not change settings about the NMI function register without preparing NMI handling routine If the register is accidentally overwritten correct operation cannot be guaranteed including abort switch operation When modifying the register value be sure to prepare a NMI handling routine and do not use the abort switch 2 If a single step execution is performed for an illegal instruction the program counter will not increment the count do not perform single step executions for illegal inst
32. ADC DAC OOOO O O OOOO OF OF OF OJO OF O OF OF O olojo CMT Notes 1 O Initialized Not initialized 2 When during HDI and CPU board operation a power on reset occurs due to a power supply voltage drop or for other reasons a Power on reset is detected message box is displayed However in this case the CPU general use registers and control registers are not initialized Change settings as necessary or restart the HDI 116 RENESAS Table 5 13 Resource Initialization cont Interrupt Source Causing Initialization Power On Reset Manual Reset Switch Monitor Monitor Resource Hardware Program Hardware Program Remarks SH7729R DSP O AUD Initialized by TRST H UDI a Initialized by TRST ASERAM Initialized by TRST XYCNT O mi XYMEM Interrupt controller O O O O PCMCIA O O SDRAM Monitor program O O work area SDRAM User program area a Notes 1 O Initialized Not initialized 2 When during HDI and CPU board operation a power on reset occurs due to a power supply voltage drop or for other reasons a Power on reset is detected message box is displayed However in this case the CPU general use registers and control registers are not initialized Change settings as necessary or restart the HDI 117 RENESAS 5 6 2 Procedure for Making Initial Settings of the CPU Bus State Controlle
33. Approximately 2 hours and 18 minutes 7 68 us Approximately 9 hours Note When the maximum measurable time shown in table 4 8 is exceeded the measured value will be invalid 4 2 6 Cache Control Dialog Box Function Specifies the cache functions This dialog is displayed on selecting Cache Control from the View menu Window Cache Control x Cache Flush P1 Area write mode fe Write Through Write Back PO UO P3 Area write mode C Write Through Write Back Cancel Figure 4 6 Cache Control Dialog Box Description The items listed in table 4 9 are displayed and set in the Cache Control dialog box The cache control register settings are displayed when the dialog box is opened When the OK button is clicked the settings are stored 74 RENESAS Table 4 9 Cache Control Dialog Box Items Item Description Cache Flush Check this box and click the OK button to flush all entries in the cache Enable Check this box to enable the cache P1 Area write mode Specifies the operating mode write through or write back for the P1 area PO U0 P3 Area Specifies the operating mode write through or write back for the PO UO write mode and P3 areas 4 2 7 Simulated I O Window Window Function This window displays data input to or output from the serial line during user program execution It is valid only during execution of a user program Serial data output by the user program
34. CC1ISR PCC1 interface status register R H 01800008 PCC1GCR PCC1 general control register R W H 0180000A PCC1CSCR PCC1 card status change register R W H 0180000C PCC1CSCIER PCC1 card status change interrupt R W H 0180000E enable register PCCVCR PCC voltage control register R W H 01800010 1 PCCO interface status register PCCOISR We REJ NUR OBR FN R KEES M WE W TE TW AE This register monitors the values of each input signal in channel 0 Here 1 High and 0 Low 2 PCCO general control register PCCOGCR aw fw pw fw jn pR fw E po bp b This register controls the bus buffer reset and other operations for channel 0 It also controls the uppermost three bits of the channel 0 address used to access the 64 Mbytes from the 8 Mbyte window 101 RENESAS Bit 7 PODRVE external buffer control 0 PCCODRY signal driven high buffer disabled 1 PCCODRY signal driven low buffer enabled Bit 6 PORES reset control 0 PCCORES signal driven low normal operation 1 PCCORES signal driven high reset Bit 5 POPCCT PCMCIA card type 0 Slot 0 card handled as memory card 1 Slot 0 card handled as I O card Bits 4 3 Not used Always read as 0 Bits 2 0 POPA25 23 used for upper address control window switching 0 Corresponding address line driven low 1 Corresponding address line driven high 3 PCCO card status change register PCCOCSCR aw pw fe rw aw Aw jaw inmavanep fp pp pp bp This register contains fla
35. Dialog Box When the file has been loaded the following message box displays information about the memory areas that have been filled with the program code HDI x i Module name C HDI5_CBY 729r tutorial Sortabs Areas loaded AC000000 ACO001AD AC0001B0 ACO001BB Figure 3 7 HDI Message Box e Click the OK button to continue 29 RENESAS 3 6 2 Displaying the Source Program The HDI allows the user to debug a program at the source level e Select Source from the View menu The Open dialog box is displayed e Select the C source file that corresponds to the object file the user has loaded Open x alSort ci File name Sort c Files of type C Files c inl Cancel z A Figure 3 8 Open Dialog Box 30 RENESAS e Select sort c and click the Open button The Program window is displayed Labe SGUREEM i ac000000 _main void main void long a 10 long j int i min max ac000004 for i 0 1 lt 10 i Df ac00000c j rand ac000014 ifj lt 0 ac000018 j j ac00001c ali j ac000038 sort a Figure 3 9 Program Window Displaying the Source Program e If necessary select the Font option from the Customize submenu on the Setup menu to select a clear font and size Initially the Program window shows the start of the main program but the user can use the scroll bar to scroll through the program to see the other statements 31 RENESAS
36. EcOl TSSOP20 TSSOP20 TSSOP20 VHC244 VHC244 VHC244 U13 TSSOP20 TSSOP20 VHC244 VHC244 VHC244 U10 u9 TSSOP20 TSSOP20 TSSOP20 TSSOP20 QS3384 QS3384 TSSOP 24 TSSOP 24 HD151015 HD151015 U46 TSSOP 24 TSSOP 24 HD151015 U43 TSSOP 24 48 tej a R 2 a LVTH16543 QS3384 QS3384 SSOL056 g g o o u5 A U4 PSS 24A HM5264165 TTP 54D SH7729R pe0 00 000 0096 Zoooveoo co oe go 000 cece ce jee e000 oo opt LQFP 208 u1 w U gl Mig cio h m C25 cze HEC0470 01 630 M2T 12AKH1 G5E Figure 5 1 EMP7160S TQFP 100 EPM7132 rpoSG 8002JA PQFP 160 EJ 0SC1 3 4 OO Ooo en C20 pal C22 ln C23 C24 LT1084 LT1084 7620 6002SC 7 Parts Layout Mounting Side RENESAS TSSOP 24 HD151015 gt SOP 24 HD151015 HD181015 re LTC1472CS LICI 4720S o o o o o o o o o o o o o o o o o o o o SOvL8LLLT INO Gg 115 5 6 Initialization 5 6 1 Initializing Resources Table 5 13 shows which CPU board resources are initialized Table 5 13 Resource Initialization Interrupt Source Causing Initialization Power On Reset Manual Reset Switch Monitor Monitor Resource Hardware Program Hardware Program Remarks SH7729R CPU a O MMU O CACHE TLB CCN INTC O O O UBC CPG WDT olojo olojo BSC DMAC TMU RTC SCI IRDA OO O O O O SCIF I O PORT
37. HE Manuals English HS6400DIIW5SE pdf Hitachi Debugging PDF document in Interface User s English Manual Type No HS6400DIIW5SE Pdf_read Japanese Ar40jpn exe Acrobat Reader installer Japanese version Pdf_read Englsih Ar40eng exe Acrobat Reader installer Note To read a PDF document use the Acrobat Reader RENESAS English version 1 6 Environmental Conditions CAUTION Observe the conditions listed in tables 1 3 and 1 4 when using the CPU board Failure to do so will damage the user system and the CPU board The USER PROGRAM will be LOST Table 1 3 Environmental Conditions Item Specifications Temperature Operating 10 C to 35 C Storage 10 C to 50 C Humidity Operating 35 RH to 80 RH no condensation Storage 35 RH to 80 RH no condensation Vibration Operating 2 45 m s max Storage 4 9 m s max Transportation 14 7 m s max Ambient gases Table 1 4 Item Host computer There must be no corrosive gases present Operating Environments Description Built in Pentium or higher performance CPU 200 MHz or higher recommended IBM PC or compatible machine OS Windows 95 Windows 98 or Windows NT Minimum memory 32 Mbytes or more double of the load module size recommended capacity Hard disk capacity Installation disk capacity 5 Mbytes or more Prepare an area at least double the memory capacity four times or more
38. N Viewing Memotyse ada heated eed ee cai een ee ae as 39 3 12 Watchin Variables tan a a A seb doses A AO A A A AE AP RAE 40 3 13 Stepping Through a Program e ee eee aaa aaa aaa aaa iiah 44 3 13 1 Executing Step In Command ee e eee eee aaa aaa aaa aaa 45 3 13 2 Executing Step Out Command ou eee eee aaa 46 RENESAS 3 13 3 Executing Step Over Command e eee eee eee aaa aaa aaa enia 48 3 14 Displaying Local Variables e ee eee eee ea aaa aaa 50 3 15 Software Break Function esz A O EO APES acts 51 3 16 Run Time Count Function eee eee eee aaa aan anaae 55 5 17 Saving a SESSION yy ss zacz e EE A TE 60 3 18 What Next o dowi Bai ia A LARK OGAE She ERA 61 Section 4 Descriptions of Windows e e eee eee e ooo a aaa aaa aaa aaa aaa aaeaaaeciace 63 AV ADIWInd WS e O O O EB O bina stone seh ssaetenasoertseyey 63 4 2 Descriptions of Each Window e 2 eee eee eee 66 4 2 1 Monitor Setup Dialog Box eee eee eee naawiaa 66 4 2 3 Add Edit Breakpoint Dialog Box eeee eee eee aaa aaa aaa 70 4 2 4 System Status Window eceescecssceenceceseceeaceceeeesnceceeeeeacecseeesneeceeeeseneeeeees 71 4 2 5 Run Time Count Condition Dialog BOX ee eeeesseceeeeeenseceeeeeenaeceeeeeenaeeeeee 73 4 2 6 Cache Control Dialog Box ee ee eee ooo aaa aaa aaa aaa aaa aa
39. O Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value ICRD H A4000018 H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINTO to PINT7 PINT8 to PINT15 IRQ5 IRQ4 Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value ICRE H A400001A H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAC IrDA SCIF ADC Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value ICRO H FFFFFEEO Undefined Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMIL NMIE Initial 0A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value 139 RENESAS ICRI H A4000010 H 4000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 L 0 MAI IRQL BLM IRLS IRQSIIRQSIIRQ4 IRQ4IRQ3IIRQ3IIRQ2 IRQ2IRQ1IRQ1IRQO IRQO VL SK JEN his js Hs s HS ps is JOS Hs S S pos Initial O 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value No restrictions are placed on accesses to the ICF2 PINTER IRRO IRR1 and IRR2 7 3 Sample Program This section describes how to create user interrupt handlers and the SCIO driver by using sample programs The sample program files were created in C language and in SH series assembly language by the work space of the Hitachi Embedded Workshop HEW This program performs echo back of the characters input from the
40. O 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 value No Bit A6 A6 A5 A5 A4 A4 A3 JA3 JA2 A2 AO name IW1 IWO IW1 IWo J IW1 IwO IW IWO IwW1 IWO IW1 Initial 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 value 119 RENESAS e WTCNT H FFFFFF84 H 5A00 TPC1ITPCOJRCD RCD ITRW TRW ITRA TRA BE AMX AMX RFS 1 0 L L S S 1 0 H 1 0 1 0 Initial O 1 0 1 0 1 1 1 0 0 1 0 0 1 value R MOD MOD E 0 e RTCNT HFFFFFF70 H A500 120 RENESAS Register Values at 66 7 MHz e FRQCR H FFFFFF80 H A101 STCZJIFC2 PFC2 SLP CKO PLL PST STC1 STCO IFC1 IFCO PFC1 FRQ JEN JEN BY 0 1 0 0 0 0 1 0 0 0 0 0 0 0 121 RENESAS e RFCR HFFFFFF74 H A400 ABW JA6W A6W A5W JA5W JA5W A4W A4W A4W JASW JA3W JA2W JA2W IAOW JAOW 2 1 0 2 1 0 2 1 0 1 0 1 0 2 1 1 1 1 1 1 1 1 1 1 0 1 1 o 1 Register Values at 33 3 MHz e FRQCR H FFFFFF80 H A111 STC2 IFC2 PFC2 SLP CKO PLL PST STC1 STCO IFC1 IFCO PFC1 FRQ JEN JEN BY 0 1 0 0 0 0 1 0 0 0 1 0 0 0 122 RENESAS e RTCSR HFFFFFF6E H A508 ABW A6W A6W JA5W A5W JA5W JA4W A4W IA4W JA3W JA3W JA2W JA2W AOW AOW JAOW 2 1 0 2 1 0 2 1 0 1 0 1 0 2 1 Initial 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 value 123 RENESAS 124 RENESAS Section 6 Notes and Trouble
41. O OO ROS ZZA 8 2 3 AD Uninstall atone a a O O A BRO A RAA OO AAA 9 24 Connecting CaDlES w i a ada lei a wady rak a ei 10 2 5 Connecting the User Expansion Board seeeeee eee ea aaa aaa eaaaee 13 2 6 Connecting the PCMCIA Card euee eee eee eau 14 21 WIICDES wzi ao E saggy OWA R W EEE W O etek covet 15 2 3 JUIN Pers 8 8 a O a da da Pd A WAG Sate sie ae ee 16 2 9 POWER SUPPLY z iz bien cess O eee eat mae Ree ase nt 19 2 9 1 Power Supply Specifications 00 eee eee eesceeeceseceseceseceecaeecaeeeeeseeeseeeeeeeeeeee 19 2 9 2 Connecting the Power Supply Cable e see eee oe aaa anawa enia 20 Section 3 TUtOfAk gk was ara Gao cui Z es 23 3L TNIFOdUCH N kien nok eet ee he a ati ee A eae 23 3 2 Running the HDI wee e o A NR A ev W Ree IEE ZES 24 3 3 i HDI Windows use s b oi see RAA pea Lo ete 26 34 Setths upsthe GPU BOard sz zi O A EA A z 27 3 5 Setting the Monitor Setup Dialog Box e eeee aaa aaa aaa 27 3 6 Downloading the Tutorial Program s e see eee aan 29 3 6 1 Downloading the Tutorial Program oe eee eee aaa aaa aaa 29 3 6 2 Displaying the Source Program 2 e e esee eee 30 3 7 Setting the Software Breakpoint eeee eee osa aaa 32 3 8 S6tiin RESISIETS z OT A A O A A O WG Anus dO 33 3 9 Executing the Programen nen id A AO A eee aiw ake ete 35 3 10 RevViewing Breakp MIS a a AO i OU 38 3A
42. Open Be sure to open this jumper J3 Selects timer clock 1 2 closed External clock TCLK CN3 158 pin 2 3 closed On board clock 1 8432 MHz default at shipment J4 Not mounted J5 Not mounted J6 Not mounted J7 Selects host computer Closed 115200 bit s default at shipment interface baud rate Open 57600 bit s J8 Not mounted J9 Selects bus frequency J9 J10 J10 Closed Closed 66 7 MHz default at shipment Closed Open 33 3 MHz Open Closed Forbidden Open Open Forbidden J11 Enables E10A emulator Closed For use of the emulator Open Emulator not used default at shipment J12 Not mounted J13 Not mounted Notes 1 The same frequency is supplied to the CPU bus clock and expansion connectors but the CPU internal operating clock always operates at 200 MHz 2 If jumper J2 is closed the monitor program will be corrupted Be sure to open J2 3 When the bus frequency is set to 33 3 MHz the CPU board cannot be interfaced with the host computer at 115200 bit s set the baud rate to 57600 bit s RENESAS 17 Jumper CPU board Figure 2 12 Jumper Insertion RENESAS 2 9 Power Supply 2 9 1 Power Supply Specifications Figure 2 13 shows the power supply specifications 5 V Vin 3 3 V Vout 2 0 V CPU Power on reset_N Figure 2 13 Power Supply Specifications 19 RENESAS 2 9 2 Connecting the Power Supply Cable Power should always be supplied to the CPU board using the p
43. Operations that may Generate Errors Operation Executing Conditions Error Message To Recover from Environment of Error Error Generation Multiple step Menu If more than Unable to fetch When an error occurs execution few hundred register press the manual steps are displayed in the reset button and specified message box initialize the HDI Then execute multiple steps Save memory Menu If more than Command not Click the OK button in few hundred ready the message box and kbytes are displayed in the execute Save memory specified again message box Note The Conditions of Error Generation are for reference If an error still occurs after the action is executed again it may mean that a large amount of load is applied to the host computer and is making the access speed to the serial port slower than the transfer speed In such a case close other applications opened on the host computer to reduce the load 130 RENESAS 3 If serial interface is disconnected while a program is being down loaded through the serial interface the HDI will stop abnormally In this case connect the serial interface cable correctly and restart the CPU board and HDI 4 The HDI does not support Motorola S type files with only the CR code H OD at the end of each record Load Motorola S type files with the CR and LF codes H ODOA at the end of each record 5 The CPU board and the HDI do not limit the address range for downloading Be sure to
44. RANTIES AS TO MARKETABILITY MERCHANTABILITY FITNESS FOR ANY PARTICULAR PURPOSE OR USE OR AGAINST INFRINGEMENT OF ANY PATENT IN NO EVENT SHALL HITACHI BE LIABLE FOR ANY DIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY NATURE OR LOSSES OR EXPENSES RESULTING FROM ANY DEFECTIVE CPU BOARD THE USE OF ANY CPU BOARD OR ITS DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES EXCEPT AS EXPRESSLY STATED OTHERWISE IN THIS WARRANTY THIS CPU BOARD IS SOLD AS IS AND YOU MUST ASSUME ALL RISK FOR THE USE AND RESULTS OBTAINED FROM THE CPU BOARD RENESAS State Law Some states do not allow the exclusion or limitation of implied warranties or liability for incidental or consequential damages so the above limitation or exclusion may not apply to you This warranty gives you specific legal rights and you may have other rights which may vary from state to state The Warranty is Void in the Following Cases Hitachi shall have no liability or legal responsibility for any problems caused by misuse abuse misapplication neglect improper handling installation repair or modifications of the CPU board without Hitachi s prior written consent or any problems caused by the user system All Rights Reserved This user s manual and CPU board are copyrighted and all rights are reserved by Hitachi No part of this user s manual all or part may be reproduced or duplicated in any form in hard copy or machine readable form by any mea
45. SDRAM 16 Mbytes 3 3 Monitor 2 0 V Flash memory for 0 5 Mbytes voltage monitor User regulator 512 kbytes 15 5 Mbytes Address Power on Oscillator driver reset 55 5 MHz switch supply adapter FPGA decoder SH7729R 200 MHz Serial I F Reset interrupt controller RS 232C I F Hitachi UDI 9 pin D sub port connector connector Connected to Connected to E10A emulator host system serial interface gt O S O o O Oo n Z o S n Cc G Q x lt LLI PCMCIA Memory I O card Figure 5 1 Block Diagram of the CPU board 77 RENESAS 5 2 Specifications Table 5 1 lists the components of the CPU board Table 5 1 Specifications Item Specifications Microcomputer SH7729R Type name HD6417729RHF200 Package 208 pin HQFP Operating frequency CPU internal clock 200 MHz fixed Bus clock 66 7 or 33 3 MHz switchover by jumpers Endian Little or big endian switchover by jumpers Memory RAM SDRAM Capacity 16 Mbytes Bus width 32 bits Type number HM5264165FTT B60 x 2 ROM Flash memory Capacity 512 kbytes monitor Bus width 16 bits program Type number PA28F400B5 B60 Serial interface One channel Conforms to RS 232C Transfer rate 57 600 or 115 200 bit s switchover by jumpers Connector 9 pin D sub connector CPU board connector DELC J9PAF 20L9 manufactured by Japan Aviation Electronics Industry Ltd Maximum cable length 3 m 78
46. To all our customers Regarding the change of names mentioned in the document such as Hitachi Electric and Hitachi XX to Renesas Technology Corp The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Renesas Technology Home Page http www renesas com Renesas Technology Corp Customer Support Dept April 1 2003 7tENESAS Renesas Technology Corp Cautions Keep safety first in your circuit designs 1 Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate me
47. U and so the monitor program performs manual reset processing registers are not initialized Consequently initial values for monitoring are not written to the BSC in the CPU and access to various resources is not possible 8 In some cases I O register values may not be correctly displayed in the memory window This is because the HDI reads all areas in byte units In order to display the correct I O register values select VO Registers from the View menu 9 The monitor program sets and uses some of the BSC registers When rewriting these registers refer to section 5 6 3 Initial Settings of CPU Bus State Controller BSO 10 I O Ports Some of the port terminals on this board are also used as pins for other functions and so some pins cannot be used for port functions The pin functions that can be used are included as signal names in the pin names of the expansion connector pin assignments in tables 5 4 5 5 and 5 6 in section 5 4 Interface If signal name functions not included in the pin name are used correct operation is not guaranteed 11 CPU Operating Mode The operating mode of this CPU is set at clock mode 7 and area 0 bus width of 16 bits The endian configuration can be changed using jumper J1 See section 2 8 Jumpers for details on settings 12 Expansion Bus 1 Areas available for use with the expansion bus The expansion bus can use areas 2 4 and 5 and cannot use area 0 1 3 or 6 Monitor FLASH memory and
48. Window Displaying the Array The user can also add a variable to the Watch Window window by specifying its name e Click the Watch Window window with the right mouse button and select Add Watch from the pop up menu The following dialog box will be displayed Add watch x kddress 7 Venable or expression Cancel Figure 3 22 Add Watch Dialog Box 41 RENESAS e Input variable max and click the OK button The Watch Window window will now also show the long type variable max Watch Window ODMERA Value Oxacf ffd4 D O Figure 3 23 Watch Window Window Displaying the Variable 42 RENESAS The user can double click the symbol to the left of array a to watch window the all elements in array a Watch Window OMER walue Oxacf ffd4 D 514 D 25643 D 1350 D 19576 D 8051 D 18234 D 16882 D 13023 D 5983 D 21166 D O Figure 3 24 Watch Window Window Displaying Array Elements 43 RENESAS 3 13 Stepping Through a Program The HDI provides a range of step menu commands that allow efficient program debugging Table 3 5 Step Option Menu Command Description Step In Executes each statement including statements within functions Step Over Executes a function call in a single step Step Out Steps out of a function and stops at the statement following the statement in the program that called the function Step Steps the specified times repeatedly
49. a aaa 74 4 2 7 Simulated I O Window Window eeee es see ea aaa aaa aaa aaa wawa aaa aaa aa aaa aeezaa nace 75 4 2 8 Command Line Window eee ae aaa aa aa aaa oaza aaa aa aaa aa waza aaa aaaaaaarreezaa aaa 76 Section 5 CPU Board Specifications seeds A GA sA 11 SL Block Did STAM iiei eier e A AO A A O EEE EE E EES 77 3 2 SpECIOICAWONSE it i O EE RE oto 78 5 3 Memory Maps idac ti O AA GA OBA RE i A ate aa 80 5 4 External Intertaces s oz di OE i O SOA dO AB GE O ad W 82 DAL Serial Interface se i a wt Z AW i te E 82 5 4 2 User Expansion Board Interface ee ee eee eee aaa ena 84 5 4 3 PCMCIA Interfaces nonent iza AW OE Gazie AA JAAA 97 5 4 4 E10A Emulator Interface oo eee cee eee aaa aaa 112 35 35 Parts Layout ie waz da A EErEE A dE LA ob 114 3 6 Initialization ao i EA a op ER 116 5 6 1 Initializing Resources oeeo eee aaa aaa aaa 116 5 6 2 Procedure for Making Initial Settings of the CPU Bus State Controller BSC 118 5 6 3 Initial Settings of CPU Bus State Controller BSO 2 0u102211222 119 Section 6 Notes and Troubleshooting ecceescceesceceseeeceeececeeeeeceeeeecsteeeeneees 125 OL Notes ieni wait Ro E E A ee PA r TRA a ees 125 6 2 Troubleshooting ri dzi A AE ESEO EG 133 Section 7 Creation of User Interrupt Handlers ee e eeaaa a eaaa ac eaaaccece 135 7 1 Creation of User Interrupt Handlers
50. a baud rate for the serial interface Memory Target Device Configuration Not supported by this CPU board System Memory Resources Not supported by this CPU board Loaded Memory Areas Shows the area where the load module is loaded Events Resources Shows the number of breakpoints set 72 RENESAS 4 2 5 Run Time Count Condition Dialog Box Function Specifies the condition for measuring the run time It is displayed by selecting Run Time from the View menu Window Run Time Count Condition Internal clock 33 3 MHz W i Measurement Mode O 12us Max 9min C 048us Max 35min 192us Max 2h18min C 7 68us Max 9h Cancel Figure 4 5 Run Time Count Condition Window Description The items listed in table 4 7 can be set in the Run Time Count Condition dialog box The run time can be checked in a message box displayed at break or in the System Status window Table 4 7 Items Set in Run Time Count Condition Dialog Box Item Description Enable Check this box to enable the run time count function The default setting is disable Measurement Mode Select a measurement unit here The setting is stored when the OK button is pressed The selectable measurement units are shown in table 4 8 73 RENESAS Table 4 8 Selectable Measurement Units Measurement Unit Maximum Measurable Time 0 12 us Approximately 9 minutes 0 48 us Approximately 35 minutes 1 92 us
51. ache Status MMU Status I O definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH 29R Monitor SH3DSP Big Endian Privileged Mode OFF OFF SH 23R CPU 200 MHz External Bus 66 7 MHz anes mmm dd yyyy Break Breakpoint Omin Os 115200 bit s Figure 3 41 System Status Window Run Time Count Disabled The time taken from the start of the program to the break is shown as the Run Time Count on the Platform sheet in the System Status window In this example the run time count function has not been enabled Oh Omin Os Oms 0 0us is displayed e Select Run Time from the View menu The Run Time Count Condition dialog box will appear e Check the Enable check button select a measurement unit from Measurement Mode and click the OK button In this example 0 12us Max 9min is selected Run Time Count Condition Internal clock 33 3 MHz t O12us Max 9min C 0 48us Max 35min C 192us Max 2h18min C 7 68us Max 9h Figure 3 42 Run Time Count Condition Dialog Box 56 RENESAS The items listed in table 3 6 can be set in the Run Time Count Condition dialog box The run time can be checked in the System Status window Table 3 6 Items Set in Run Time Count Condition Dialog Box Item Enable Description Check this box to enable the run time count function The default setting is disable Meas
52. aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges Even within the guaranteed ranges consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Hitachi product does not cause bodily injury fire or other consequential damage due to operation of the Hitachi product 5 This product is not designed to be radiation resistant No one is permitted to reproduce or duplicate in any form the whole or part of this document without written approval from Hitachi 7 Contact Hitachi s sales office for any questions regarding this document or Hitachi semiconductor products IMPORTANT INFORMATION READ FIRST e READ this user s manual before using this CPU board KEEP the user s manual handy for future reference Do not attempt to use the CPU board until you fully understand its mechanism CPU Board Throughout this document the term CPU board shall be defined as the following products produced only by Hita
53. amage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Figures 5 5 to 5 7 show the pin arrangement of expansion connectors CN3 CN6 and CN7 Tables 5 4 to 5 6 list the pin assignment of the expansion connectors CN3 CN6 and CN7 respectively Refer to the CPU hardware manual for those pins that have no numbers in the pin function column The pin signal level is 3 3 V which is equivalent to that of the SH7729R CPU For details on expansion board connection refer to section 2 5 Connecting the User Expansion Board 84 RENESAS Pin179 Pin 2 Expansion bus connector CN7 Figure 5 7 Expansion Bus CN7 Pin Arrangement 85 RENESAS Table 5 4 Pin Assignment of Expansion Connector CN3 Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function GND 26 D12 1 51 GND 2 DO 1 27 GND 52 D25 1 3 CASL 28 D13 1 53 GND 4 D1 1 29 GND 54 D26 1 5 GND 30 D14 1 55 GND 6 D2 1 31 GND 56 D27 1 7 CASU PTJ 3 10 32 D15 1 57 GND 8 D3 1 33 GND 58 D28 1 9 GND 34 D16 1 59 GND 10 D4 1 35 GND 60 D29 1 11 PTJ 4 10 36 D17 1 61 GND 12 D5 1 37 GND 62 D30 1 13 GND 38 D18 1 63 GND 14 D6 1 39 GND 64 D31 1 15 PTJ 5 10 40 D19 1 65 GND 16 D7 1 41 GND 66 AO 2 17 GND 42 D20 1 67 GND 18 D8 1 43 GND 68 Al 2 19 GND 44 D21 1
54. appears HDI i X Z Cannot set a breakpoint at the specified address OK eee Figure 6 2 Message Box Indicating Breakpoint Cannot Be Set For the above reason a breakpoint may not be set if the initial data in the RAM is invalid when a user program is loaded by specifying a session file In this case reload the program by respecifying the session file 5 If a breakpoint is set within an interrupt or exception handler of a user program it will not cause a break when the program is executed 6 When a power on reset or manual reset is input the message box shown in figure 6 3 and figure 6 4 respectively is shown At this time general purpose registers and control registers are not reset Either settings should be changed as necessary or the HDI should be restarted The run time count function must be enabled again by the Run Time Count Condition dialog box lessage received from monitor x Power on reset is detected Figure 6 3 Power on Reset Input Message Box Manual reset is detected Figure 6 4 Manual Reset Input Message Box 126 RENESAS 7 If the power is turned on while pressing and holding the manual reset switch the CPU board and HDI will not be started When turning on power do not operate the manual reset switch In this case a power on reset is input to the CPU when the power is turned on and the BSC register is initialized However manual reset code is set for event code flags within the CP
55. asures such as i placement of substitutive auxiliary circuits ii use of nonflammable material or iii prevention against any malfunction or mishap Notes regarding these materials 1 These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials AII information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons Itis therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no respo
56. at user programs can be employed in PCMCIA evaluations Figure 1 1 CPU Board External View Note IBM PC is a registered trademark of International Business Machines Corporation in the United States RENESAS 1 2 System Configuration The system configuration of the CPU board is shown in figure 1 2 The following items are required to use the CPU board e IBM PC compatible machine One for the monitor command input and output e One serial interface cable Use the provided cable e One AC power supply adapter Use the provided adapter e One AC power supply cable Use the provided power cable AC power cable Serial cable JS is li i User expansion board Figure 1 2 CPU Board System Configuration RENESAS 1 3 Warnings CAUTION READ the following warnings before using the CPU board Incorrect operation will damage the user system and the CPU board The USER PROGRAM will be LOST 1 Check all components against the component list after unpacking the CPU board 2 Never place heavy objects on the CPU board 3 Protect the CPU board from excessive impacts and stresses For details refer to section 1 6 Environmental Conditions 4 Do not connect any cable or connector other than specified ones to the CPU board 5 When moving the host computer or user expansion board take care not to vibrate or damage the CPU board 6 After connecting the cable check that it is connected correct
57. ate Status SH7 29R Monitor SH3DSP Big Endian Privileged Mode OFF OFF SH 23R CPU 200 MHz External Bus 66 7 MHz oe mmm dd yyyy Break Breakpoint Omin Os 115200 bit s Figure 3 39 Displayed Contents of the System Status Window Software Break 54 RENESAS 3 16 Run Time Count Function By enabling the run time count function and executing the user program the user program run time can be measured In the following example the run time of the sort function is measured e Select Delete All from the pop up menu in the Breakpoints window and double click the BP column on the 21st and 22nd lines in the Program window to set breakpoints e Set the program counter and stack pointer values that have been set in section 3 8 Setting Registers PC H ACO00000 R15 H ACF80000 in the Registers window Click the Go button The program runs and stops at the breakpoint Source i void maintvoid long a 10 long j nt 1 min max ac000004 for 1 0 1 lt 10 i df ac00000c j rand ac000014 ifj lt 0 ac000018 J J ac00001c ac000040 8 min ac000044 max ac000048 min ac00004c max QO ac000050 change a ac000058 min a 9 ac00005c max a 0 ac000060 Figure 3 40 Program Window Break before Run Time Count e Select Status from the View menu The System Status window will appear 55 RENESAS System Status Item Connected to CPU Mode C
58. ated Bit 4 PISCE STSCHG interrupt enable In cases where the card in slot 1 is an I O card this bit enables and disables PCCIBVD1 STSCHG interrupts An interrupt request is generated when PCCICSCR bit 4 is set and this bit is 1 When the card is a memory card operations on this bit are invalid 0 STSCHG interrupt disabled 1 STSCHG interrupt enabled Bit 3 PICDE card detection interrupt enable Enables and disables PCC1CD2 and PCC1CDI interrupts An interrupt request is generated when PCCICSCR bit 3 is set and this bit is 1 0 PCCICD2 PCCICDI interrupt disabled 1 PCC1CD2 PCC1CD1 interrupt enabled Bit 2 PIRE ready change interrupt enable In cases where the card in slot 1 is a memory card this bit enables and disables PCCIRDY interrupts An interrupt request is generated when PCCICSCR bit 2 is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 RDY BSY interrupt disabled 1 RDY BSY interrupt enabled 110 RENESAS Bit 1 PIBWE battery voltage low interrupt enable In cases where the card in slot 1 is a memory card this bit enables and disables battery voltage low interrupts An interrupt request is generated when PCC1CSCR bit 1 is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 Battery voltage low interrupt disabled 1 Battery voltage low interrupt enabled Bit 0 PIBDE battery replacement interrupt enable In cases where the card
59. aved on the stack In other words R15 8 Rl at time of exception BANKI R15 4 RO at time of exception BANKI The following is an example of code which achieves this MOV L RO R15 save RO0 BANKI MOV L R1 R15 save R1_BANK1 By this means register values can be displayed during debugging when an exception or interrupt occurs The values of general purpose registers other than RO and R1 should be saved at the time of occurrence of an exception or interrupt The BL bit of the SR register should be kept as 1 from the occurrence of an exception until branching to the branch address The values of the SSR SPC EXPEVT INTEVT INTEVT2 and TRA registers should be saved at the time of occurrence of an exception Branching should be performed with the RB and MD bits of the SR register both set to 1 the state of occurrence of an exception or interrupt 136 RENESAS 7 2 User Program Using SCI The user program cannot usually access the serial communication interface with FIFO SCIF in the SH7729R because the CPU board uses it to communicate with the host PC The CPU board provides the Simulated I O Window window to allow the user to use the SCIF When the SCIF is used from the user program the SCIF driver in the user program communicates with the Simulated I O Window window on the host PC rather than with the actual SCIF directly As processing for interrupts of the CPU must be added to the user p
60. board does not support this function this box cannot be selected Delete breakpoints Unchecked When this box is checked all breakpoints are deleted when when program is a program is reloaded reloaded Reset CPU when Unchecked When this box is checked registers are initialized when a program has been program is loaded No reset signal is input to the CPU board downloaded Note Only the program counter and status register and VBR are initialized PC HAC000000 and SR H 600010E0 The value of VBR depends on the endian e Click the OK button Notes 1 The I O register definition file can be selected in this dialog box Be sure to select a file within the HDI installation directory Otherwise the I O register window will not operate correctly 2 The name of the I O register definition file can consist of up to nine characters This number does not include the file name s extension 28 RENESAS 3 6 Downloading the Tutorial Program 3 6 1 Downloading the Tutorial Program Download the object program to be debugged e Select Load Program from the File menu The Load Program dialog box is displayed Enter the offset and file name in the Offset edit box and File name list box as shown in figure 3 6 and click the Open button Load Program x ora il Mv Verity Cancel File name E HDIS_CBA7728A tutorial Sort abs X Browse I Downloading only debugging infromatior Figure 3 6 Load Program
61. chi Ltd excluding all subsidiary products e CPU board e Serial cable e AC power adapter e AC power cable The user system or a host computer is not included in this definition Purpose of the CPU Board This CPU board is a software and hardware development tool for systems employing the Hitachi microcomputer SH7729R Simple debugging functions such as debugging performance evaluation and development of the user system including the SH7729R are enabled by connecting the CPU board to a host computer In addition expansion boards can be installed in the slots therefore memory and T O can be expanded However this CPU board must not be installed in user products to be used as part of the user products it is limited to debugging and evaluation of user systems This CPU board must only be used for the above purpose Limited Applications This CPU board is not authorized for use in MEDICAL atomic energy aeronautical or space technology applications without consent of the appropriate officer of a Hitachi sales company Such use includes but is not limited to use in life support systems Buyers of this CPU board must notify the relevant Hitachi sales offices before planning to use the product in such applications Improvement Policy Hitachi Ltd including its subsidiaries hereafter collectively referred to as Hitachi pursues a policy of continuing improvement in design performance and safety of the CPU board Hitachi reserves the
62. ck the Enable checkbox Add Edit Breakpoint x Breakpoint address change V Enable Figure 3 36 Add Edit Breakpoint Dialog Box e Click the OK button 52 RENESAS The software breakpoint that has been set is displayed in the Breakpoints window Breakpoints LO Ol x Enable Fi Type e symbol A Sort c 55 _change ACOOO12A PC breakpoint Figure 3 37 Breakpoints Window Software Breakpoint Setting To stop the tutorial program at the breakpoint the following procedure must be executed e Close the Breakpoints window e Set the program counter and stack pointer values that have been set in section 3 8 Setting Registers PC HAC000000 R15 H ACF80000 in the Registers window Click the Go button The program runs and stops at the set breakpoint 53 RENESAS A ac000112 ac000124 ac00012e ac000136 ac000158 ac000160 ac000186 Source gap gap 2 long tmp 10 int i for i 0 i lt 10 i tmp i a i for i 0 i lt 10 i a i tmp 9 i Figure 3 38 Program Window at Execution Stop Software Break Select Status from the View menu The System Status window displays the following contents The window confirms that execution was stopped at a breakpoint System Status Item Connected to CPU Mode Cache Status MMU Status I 0 definition Clock Target DLL version Monitor version Run Status Break Cause Run Time Count Comm port baudr
63. de or user mode Cache Status Shows whether the cache is enabled or disabled MMU Status Shows whether the MMU is enabled or disabled I O definition Displays the selected I O register definition file Clock Displays the clock frequency CPU operating frequency and external bus frequency being used Target DLL Version Indicates the version of the target DLL for connection to the CPU board Monitor Version Displays the monitor program version Run Status Displays the user program execution status Run Being executed Break Stopped Break Cause Displays the cause of the program stopping at break Run Time Count Shows the time from the start of the user program to the break When the run time count function is disabled Oh Omin Os Oms 0 0us is displayed Comm port baudrate Indicates the data baud rate for the serial interface Memory Target Device Configuration Not supported by this CPU board System Memory Resources Not supported by this CPU board Loaded Memory Areas Shows the area where the load module is loaded Events Resources Shows the number of breakpoints set 37 RENESAS 38 3 10 Reviewing Breakpoints The user can see all the breakpoints set in the program in the Breakpoints window e Select Breakpoints from the View menu Enable File Sort c 21 Breakpoints Oo ol x A Type AC000038 PC breakpoint Figure 3 17 Breakpoints Window Right clicking in the Breakpoints window will open a pop up
64. dress H AC000000 The MMU function is not used Notes 1 sort abs operates in big endian sort abs must be recompiled to operate in little endian 2 The work space for this tutorial program was created using Version 1 1 Release 4 of Hitachi Embedded Workshop HEW Hitachi SH C C compiler version 5 1B Hitachi SH IM OptLinker version 1 1B 23 RENESAS 3 2 Running the HDI To run the HDI select the HDI for SH7729R CPU board from the Start menu MjAccessories Z Online Services 3 Favorites StartUp R MS DOS Prompt OJ Windows Explorer 4 Documents 5 HDI for SH 7729R CPU board BS HDI for SH7729R CPU board Figure 3 1 Start Menu The HDI window will open then the Select Session dialog box will appear Check that the setting shown in figure 3 2 is complete and click the OK button Select Session x K 2 SH 729R CPU board C Previous session file Figure 3 2 Select Session Dialog Box 24 RENESAS The message box shown in figure 3 3 will appear Check that the CPU board power is turned on and click the OK button HDI N Please power on the CPU board and press lt enter gt key Figure 3 3 Power Supply Confirmation Message Box When Link up appears on the status bar HDI startup is completed If Link up does not appear check the items listed in table 3 2 Table 3 2 Check Items When HDI Cannot Be Initiated Check Item Reference in this Manual Check that the pow
65. e is increased to the nearest integer multiple of the access size After the above processing the HDI performs the memory fill operation 9 The values displayed as Cache Status and MMU Status in the Status window are the values for the last break that occurred during user program execution Values as updated in the I O Registers window are not displayed in the Status window 10 The overhead due to run time measurement is about 20 us in 66 7MHz about 35 us in 33 3MHz per execution 24 The default I O register definition file does not include bit level information To use bit level information create a new I O definition file or modify the default I O register definition file For details on the format of I O register definition files refer to appendix E I O Register File Format in the Hitachi Debugging Interface User s Manual 25 When the menu is selected from the display during user program execution some commands are activated however in the CPU board only Labels Status Simulated I O Window Halt and Help commands can be used 132 RENESAS 6 2 Troubleshooting 1 Ilegal general instruction appears on the HDI status bar and program execution is halted This is displayed when a general exception occurs This message appears when the EXPEVT register value is H 180 It is caused by use of a privileged instruction in user mode by use of an undefined instruction or for similar reasons For further information refer to t
66. eakpoints 1 During single step execution the settings of the breakpoints are ignored 2 A total of 255 breakpoints including temporary breakpoints can be set A temporary breakpoint cannot be set to the same address as an enabled breakpoint If a temporary breakpoint is set to the same address as a disabled breakpoint the breakpoint will be deleted from the breakpoints list after program execution have been completed 3 After setting breakpoints the CPU board must not be manually reset while the user program is being executed Otherwise illegal instructions will remain at addresses where breakpoints have been specified To continue debugging the user program download the user program again 4 In the CPU board the TRAPA instruction is used for breakpoint functions When using DSP repeat loops on the CPU board note that in some DSP repeat loops branch instructions cannot be used and so breakpoints cannot be set in such loops For details refer to the SH7729R Hardware Manual and Programming Manual 5 After 255 breakpoints the maximum number have been specified if Add Edit Breakpoint is selected in the Breakpoints window an error will occur In this case delete any unnecessary breakpoints and then add or edit breakpoints 6 When the contents of a software breakpoint address are modified during user program execution the breakpoint is disabled The user program will not stop at this address When the program stops with any
67. eceived is not prepared the program cannot be stopped by clicking the HALT button in the HDI 137 RENESAS 7 2 2 SCI Related Register Settings The initial values of the SCI related registers are shown below The shaded bits must not be modified Serial Communication Interface SCI0 SCSMR H FFFFFE80 H 00 Bit 7 6 5 4 3 2 1 0 C A CHR PE O E STOP MP CKS1 CKSO Initial O 0 0 0 0 0 0 0 value SCBRR HFFFFFE82 H FF Bit 7 6 5 4 3 2 1 0 a Initial 1 1 1 1 1 1 1 value SCSCR H FFFFFE84 H 73 Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKEO Initial O 1 1 1 0 0 1 1 value No restrictions are placed on accesses to the SCTDR SCSSR SCRDR SCPDR and SCPCR 138 RENESAS Interrupt Controller INTO For the interrupts used by the user program any interrupt level from O to 14 can be set but interrupt level 15 must not be used except for the SCI ICRA H FFFFFEE2 H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMUO TMUO TMUO RTC Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value ICRB HFFFFFEE4 H 00F0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDT REF SCI Initial 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 value ICRC H A4000016 H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ3 IRQ2 IRQ1 IRQ
68. er monitoring LED LED1 on the CPU board is Section 5 5 turned on Check that the host computer and the CPU board are correctly Sections 2 4 and 5 4 1 connected through a serial cable Check that the port and baud rate are set correctly in the Monitor Sections 3 5 and 4 2 1 Setup dialog box Check that the jumper pins are correctly inserted into the jumpers Section 2 8 on the CPU board 25 RENESAS 3 3 HDI Window BS Aitachi Debugging interface Sort SH7729R CPU board BEE _ File Edit View Run Memory Setup Window Help j gasa i ae w an aE ol eee o l EO a el a G E GAl long a 10 long j int 1 min max ac000004 for 1 0 1 lt 10 i If ac00000c j rand ac000014 ifG lt of ac000018 j 5 ac00001c ac000038 ac000040 ac000044 00048 0004 c For Help press F1 Figure 3 4 HDI Window The key functions of the HDI are described in section 4 Descriptions of Windows Numbers in figure 3 4 indicate the following 1 Menu bar Gives the user access to the HDI commands for using the HDI debugger 2 Toolbar Provides convenient buttons as shortcuts for the most frequently used menu commands 3 Program window Displays the source program being debugged 4 Status bar Displays the status of the CPU board and progress information about downloading 5 Help button Activates on line help about any features of the HDI user interface 26
69. for test use Correct operation cannot be guaranteed PC SR and VBR are initialized The reset signal is not sent to the CPU OOO OOOO OOOO O O O CO OC CO CO OOOO O RENESAS 65 4 2 Descriptions of Each Window This section describes each window 4 2 1 Monitor Setup Dialog Box Function Specifies the setup conditions for the CPU board This dialog can be displayed by selecting Configure Platform from the Setup menu Window Monitor Setup Target Monitor Comms Settings Comms Port COM1 x i Cancel Baud Rate 115200 Help 1 0 definition file SH7729R Browse Download with vent I Delete breakpoints when program is reloaded I Reset CPU when program has been downloaded Figure 4 1 Monitor Setup Dialog Box Notes 1 The I O register definition file can be selected in this dialog box Be sure to select a file within the HDI installation directory Otherwise the I O register window will not operate correctly 2 The name of the I O register definition file can consist of up to nine characters This number does not include the file name s extension 66 RENESAS Description The settings of the Monitor Setup dialog box are indicated below Table 4 2 Monitor Setup Dialog Box Page Option Setting Comms Port COM1 COM2 COM3 or COM4 can be selected as the host computer serial port Baud Rate Sets the serial baud rate Select either 57600 bit s or 115200 bi
70. gs used to monitor changes in the status of channel 0 By reading this register after an interrupt IRQ1 is received the cause of the interrupt can be identified Bit 7 POSCDI software card detection interrupt When writing data via software an interrupt is generated This bit can be set freely but as in the case of a card detection interrupt the interrupt itself is masked by PCCOCSCIER bit 3 POCDE 0 Interrupt not generated 1 Slot 0 card detection interrupt generated 102 RENESAS Bit 6 Not used Always read as 0 Bit 5 POIREQ IREQ interrupt In cases where the card in slot 0 is an I O card when an interrupt is generated by PCCORDY IREQ this bit is set to 1 in the case of a memory card this bit is always 0 Conditions for setting this bit conform to the settings for bits 6 and 5 of PCCOCSCIER IREQEI 0 interrupt disabled level mode rising edge mode falling edge mode In the case of an edge mode the interrupt can be cleared by writing 0 to this bit 0 No IREQ interrupt request 1 IREQ interrupt request generated for the slot 0 I O card Bit 4 POSC STSCHG interrupt In cases where the slot O card is an I O card when an interrupt is generated by PCCOBVD1 STSCHG this bit is set to 1 in the case of a memory card it is always 0 The condition for setting the bit is a transition of the STSCHG pin from high to low level The bit is cleared by writing 0 to it The interrupt can be masked by PCCOCSCIER bit 4
71. he SH7729R Hardware Manual When a privileged instruction has been used in user mode please take the following steps In the register window change the SR status register MD bit to privileged mode _ Or execute the Reset CPU on the Run menu and set the register values to the following initial values Table 6 3 Register Initial Value Settings Register Initial Value Description PC H AC000000 User program area start address SR H 600010E0 Privileged mode mask level 14 R15 SP H ACF80000 Final address of user program area VBR H A0008000 big endian Monitor VBR different from actual chip H A0048000 little endian 2 Step execution is slow When the Watch Window window and I O Registers window are open the data in these windows must be rewritten each time a step is executed and so execution speed will be reduced Decrease the sizes of these windows to speed execution 133 RENESAS 134 RENESAS Section 7 Creation of User Interrupt Handlers 7 1 Creation of User Interrupt Handlers Cases where exceptions and interrupts are not used in the user program no user interrupt handlers are created Set the value of VBR to the initial value big endian H A0008000 little endian H A0048000 By doing so step execution breaks and other debugging functions can be used when an exception or interrupt occurs Cases where exceptions and interrupts are used in the user program user
72. in void main void 3 el long a 10 8333 long j i int i min max EE ac000004 for i 0 i lt 10 i Er ac00000c j rand D 19576 ac000014 1f 3 lt of D 21166 ac000018 J D 25643 ac00001c ali j D 25643 ac000038 sorta ac000040 min a 0 ac000044 max a 9 acO00004c max 0 ac000050 change a ac000058 min a 9 ac00005c max ac000060 fa fa fa N a i zj oh tie E 4 gt Break Step NUM A Figure 3 30 Program Window Step In gt Step In 47 RENESAS 3 13 3 Executing Step Over Command The Step Over executes a function call as a single step and stops at the next statement of the main program e Using Step In execute two steps to reach the change function statement e To step through all statements in the change function at a single step select Step Over from the Run menu or click the Step Over button in the toolbar Figure 3 31 Step Over Button ES Hitachi Debugging interface Sort SH 729R CPU board __ File Edit View Run Memory Setup Window Help o Gasa Tea w FAMAL APPS Fa BEE Ea ee Value Source SOOO _main yol d main void e long a 10 D 1350 long j D 5983 D 8051 int i min max D 13023 ac000004 for i 0 i lt 10 i JI wee ac00000c j rand D 19576 ac000014 1f j lt OF b 21166 ac000018 D 25643 ac00001c i j D O fa a m Ah e
73. int setting information The items listed in table 4 3 are displayed Table 4 3 Breakpoints Window Display Items Item Description Enable Displays whether the break condition is enabled or disabled The e indicates that the breakpoint is enabled File Line Displays the file name and line number where the breakpoint is set Symbol Displays the symbol corresponding to the breakpoint address If no symbol has been defined for the address a blank is displayed Address Displays the address where the breakpoint is set Type Displays PC breakpoint Right clicking in the Breakpoints window will open a pop up menu through which breakpoints can be set changed deleted enabled or disabled The pop up menu functions are described in table 4 4 Table 4 4 Breakpoints Window Pop up Menu Operation Name Description Add Sets break conditions Clicking this button will display the Add Edit Breakpoint dialog box enabling break conditions to be set Edit Changes break conditions Select break conditions to be changed and click this button The Add Edit Breakpoint dialog box will be displayed enabling the break condition to be changed Disable Enables or disables break conditions Select break conditions to be Enable enabled or disabled and click this button Delete Clears break conditions Select break conditions to be cleared and click this button Del All Clears all break co
74. interrupt handlers are created Set the value of VBR to the start address of the user interrupt handler By doing so execution will branch to the user interrupt handler when an exception or interrupt occurs Add a routine to branch to the following addresses to the user interrupt handler this will enable step execution breaks and other debugging functions when an exception or interrupt occurs Table 7 1 lists the branch addresses for different interrupt causes Table 7 1 Interrupt Causes and Branch Addresses for User Interrupt Handlers Branch Address Branch Address Interrupt Cause Code Big Endian Little Endian UBC trap EXPEVT 1E0 H A0009000 H A0049000 Unconditional trap FF EXPEVT 160 H A0009020 H A0049020 Reserved instruction code EXPEVT 180 H A0009040 H A0049040 exception Slot illegal instruction EXPEVT 1A0 H A0009060 H A0049060 exception CPU address error load EXPEVT 0E0 H A0009080 H A0049080 CPU address error store EXPEVT 100 H A0009080 H A0049080 DMA address error EXPEVT 5C0 H A00090A0 H A00490A0 NMI INTEVT 1C0 H A00090C0 H A00490C0 SCI RXI INTEVT 500 H A00090E0 H A00490E0 Note When the SCI is not used a program to branch to the SCI RXI destination address must be prepared RENESAS 135 Attention should be paid to the following when creating an interrupt handler 1 When branching to a branch address from the user interrupt handler the values of RO and R1 BANKI must be s
75. is an efficient development tool for software and hardware of systems based on Hitachi s SH7729R microcomputer This manual describes the SH7729R CPU board model number HS7729RSTCO1H Hereafter this product will be referred to as the CPU board This manual explains the functions and method of operation of these CPU boards Section 1 Overview describes the hardware system configuration and explains environment settings to enable board use Section 2 Preparation before Use explains procedures for using the CPU boards HDI installation various connections and the power supply specifications Section 3 Tutorial introduces the major HDI features while demonstrating methods for loading and debugging a C language program Section 4 Descriptions of Windows describes each of the windows used in the HDI Section 5 CPU Board Specifications explains the specifications of the CPU boards the memory map interfaces with external equipment and CPU board initialization Section 6 Notes and Troubleshooting explains important information regarding use and gives suggestions for troubleshooting Section 7 Creation of User Interrupt Handlers explains how to create an original interrupt handler routine Please read this manual completely in order to gain a thorough understanding of this product s functions and performance The text appearing in the various windows of the HDI may differ from those appearing in this manual de
76. itachi UDI Port Connector CN8 Pin Arrangement 112 RENESAS Table 5 11 Hitachi UDI Port Connector CN8 Pin Assignment CN8 SH7729R CN8 SH7729R Pin No Signal Name Input Output Pin No Signal Name Input Output 1 NC 19 TMS Input 2 GND 20 GND 3 AUDDATAT 0 Input output 21 _TRST Input 4 GND 22 GND 5 AUDDATAT1 Input output 23 TDI Input 6 GND 24 GND 7 AUDDATA 2 Input output 25 TDO Input 8 GND 26 GND 9 AUDDATA 3 Input output 27 _ASEBRKAK Output 10 GND 28 GND 11 _AUDSYNC Input output 29 Reserve Output 12 GND 30 GND 13 NC 31 _RESET Output 14 GND 32 GND 15 NC 33 GND 16 GND 34 GND 17 TCK Input 35 AUDCK Input 18 GND 36 GND RENESAS 113 5 5 Parts Layout The parts layout of the CPU board is shown in figure 5 17 Uninstalled parts are listed in table 5 12 Table 5 12 List of Uninstalled Parts Part Number Part Name Quantity OSC3 TCO 711S4 1 OSC4 CXO 105D 1 CN4 FFC 10 1 J4 to J6 J12 J13 310 93 103 5 J8 410 93 202 1 TP1 to TP12 ST 1 3 12 CKIN ST 1 3 1 TEST ST 1 3 1 R4 MCR10EZHJ472 1 R7 to R9 R11 MCR10EZHJ103 4 R12 R149 R151 MCR10EZHJO00 3 C23 281E6801 337M 1 C24 281E1002 157M 1 C28 281E1002 107M 1 Note A connector for testing Should not be connected to any cables even if the connector is installed 114 RENESAS We0eS 9
77. k Settings A Eind 2 Help gl Run Figure 2 3 Start Menu 2 3 HDI Uninstallation Uninstall the HDI for the SH7729R CPU board as follows Select Settings from the Start menu then select Control Panel Select Add Remove Programs Select HDI for SH7729R CPU board from the application list then click Add Remove A confirmation message will be displayed and the uninstallation procedure will start Aw NS RENESAS 2 4 Connecting Cables This section shows how to connect interface cables to the CPU board A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST E10A emulator Connected to CN8 interface cable Figure 2 4 E10A Emulator Interface Cable Connection RENESAS Serial interface cable Figure 2 5 Serial Interface Cable Connection CN6 expansion interface cable Connected to CN6 Figure 2 6 CN6 Expansion Interface Cable Connection 11 RENESAS CN7 expansion CN7 expansion connector interface cable A 2 e e LI R TL go Align pin 1 on the connectors CN7 expansion interface cable Figure 2 7 CN7 Expansion Interface Cable Connection A WARNING Always switch OFF the CPU b
78. ly For details refer to section 2 Preparation before Use 7 Supply power to the connected equipment after connecting all cables Cables must not be connected or removed while the power is on RENESAS 1 4 Components Table 1 1 lists the components of the CPU board Check all components after unpacking Table 1 1 CPU Board Component List Item View Quantity Remarks CPU board 1 One printed circuit board AC power 1 supply adapter AC power 1 supply cable O Serial 1 communication cable Jumper pin 1 CD R 1 One CD R gt Model number oz HS7729RSTC01SR Notes on Usage 2 One Japanese version of SH7729R and one English version CPU Board ne 2 Japanese g HS7729RSTC01H J P English Note Refer to section 1 5 CD R Contents HS7729RSTC01HE P RENESAS 1 5 CD R Contents The supplied CD R includes software and user s manuals for the SH7729R CPU board as listed in table 1 2 Table 1 2 Directory setup CD R Contents File Name setup exe Contents HDI installer Remarks Manuals Japanese HS7729RSTCO01Hu pdf SH7729R CPU Board PDF document in User s Manual Japanese Type No HS7729RSTCO1HJ Manuals Japanese HS6400DIIW5SJ pdf Hitachi Debugging PDF document in Interface User s Japanese Manual Type No HS6400DIIW5SJ Manuals English HS7729RSTCO1HE pdf SH7729R CPU Board PDF document in User s Manual English Type No HS7729RSTCO1
79. monitor I O are connected to area 0 SDRAM is connected to area 3 and two PCMCIA slots are connected to area 6 2 Devices which cannot be connected to the expansion bus DRAM cannot be connected to the expansion bus This is because SDRAM on the CPU board is allocated to area 3 3 Interrupts The NMI external interrupts and port interrupts should all be processed by interrupt handlers in the user program For details refer to section 7 Creation of User Interrupt Handlers IRQS is assigned as a pin CTS2 SCPT 7 with other functions For this reason the user cannot use the IRQ5 external interrupt Use the other external interrupts instead 13 Refresh Timer The refresh timer is used as an SDRAM refresh timer and so cannot be used as an interval timer 127 RENESAS 14 15 16 17 18 19 TMU The run time count function uses the TMUO and so the user cannot use the TMUO If the TMUO register is accidentally overwritten correct operation is not guaranteed SCI The serial interface with the host uses the SCIO SCI in the CPU For this reason the user cannot use the CPU s internal SCIO except for the standard I O processing using the Simulated I O Window For details refer to section 7 2 User Program Using SCI Use SCI1 IrDA or SCI2 SCIF for a purpose other than standard I O processing If the SCIO interface register is accidentally overwritten the CPU board and HDI will become inoperable PCMCI
80. nd The Step Out steps out of the called function and stops at the next statement of the calling statement in the main function e To step out of the sort function select Step Out from the Run menu or click the Step Out button in the toolbar P Figure 3 28 Step Out Button ra Hitachi Debugging interface Sort SH 29R CPU board File Edit View Bun Memory Setup Window Help PEETA S8e FAMAL AP PHS D RRMA HAE Te Bi we i blo 8 2 MA te A Lal Value ac000000 _main void main void ya long a 10 D 1350 long j D 5983 long J i D 8051 THE 1 MIN Max D 13023 ac000004 for 1 0 i lt 10 i D 18234 ac00000c j s rand D 19576 ac000014 if j lt of D 21166 ac000018 j j D 25643 ac00001c ali j S ac000038 ac000044 ac000045 ac00004c ac000050 ac000058 ac00005c ac000060 ta fa fa N a i zy te i For Help press F1 Figure 3 29 Program Window Step Out e The values of array a is sorted in ascending order e To execute two steps use Step In twice 46 RENESAS e The value of max displayed in the Watch Window window is changed to the maximum data value ra Hitachi Debugging interface Sort SH 729R CPU board File Edit View Run Memory Setup Window Help PEETA 504 FAMHL APPS S Rs Be RAAT Bow WEE blo 8 2 BAR A La value aj ac000000 _ma
81. nditions Go to Source Jumps to the break address in the Source window 69 RENESAS 4 2 3 Add Edit Breakpoint Dialog Box Function Sets a breakpoint This dialog box is displayed when the Add or Edit is selected in the pop up menu in the Breakpoints window which is displayed by selecting the Breakpoints item on the View menu Window Add Edit Breakpoint x Breakpoint address change MV Enable _ Cancel Figure 4 3 Add Edit Breakpoint Dialog Box Description The Add Edit Breakpoint dialog box is made up of the components listed in the table below Table 4 5 Add Edit Breakpoint Dialog Box Items Page Name Description Breakpoint address Enter the address or symbol for which a breakpoint is to be set Enable The breakpoint is enabled when this box is checked After clicking OK the breakpoint is set 70 RENESAS 4 2 4 System Status Window Function This window lists information such as conditions that have been set to the CPU board and execution results It is displayed by selecting the Status item on the View menu Window Item Connected to CPU Mode Cache Status MMU Status I O definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH7 29R Monitor SH3DSP Big Endian Privileged Mode OFF OFF SH 23R CPU 200 MHz External Bus ea mmm dd yyyy Break Breakpoint Oh Omin Os
82. ndow 33 RENESAS e To change the value of the program counter double click the value area in the Registers window with the mouse The following dialog box is then displayed and the value can be changed Register PC x Value facoooood Set As EH whole Reaister X Carcel Figure 3 12 Register Dialog Box PC e Enter H ACO00000 in the Value edit box and click the OK button e To change the value of the stack pointer move the mouse pointer to the value area of R15 in the Registers window and enter a new value directly or double click the value area with the mouse to open the following dialog box Register R15 x Value ACF80000 Set As Whole Register Cancel Figure 3 13 Register Dialog Box SP Enter H ACF80000 in the Value edit box and click the OK button 34 RENESAS 3 9 Executing the Program Execute the program as described in the following e To execute the program select Go from the Run menu or click the Go button on the toolbar EM Figure 3 14 Go Button The program will be executed up to the breakpoint that has been inserted and a statement will be highlighted in the Program window to show the position that the program has halted Break Breakpoint will appear on the status bar A BP Source 3 ac000000 M 22 main void long a 10 long j int i min max ac000004 for i 0 1 lt 10 i JI ac00000c j rand ac0000
83. not guaranteed 8 PCC1 CSC interrupt enable register PCC 1CSCIER Bier dees Bea NP 2 ear EE EM GRZE Name P1CRE P1IREQE1 PIIREQEO P1SCE P1CDE P1RE P1BWE P1BDE This register masks status change interrupts for channel 1 An interrupt request is generated when the corresponding bits of PCCIC CR and this register are both 1 Bit 7 PICRE PCCIGCR reset enable When insertion of a card into slot 1 is detected CD1 changes from high to low or CD2 changes from high to low this bit determines whether or not PCC1GCR is initialized 0 GCR is not initialized even when card insertion is detected 1 GCR is initialized when card insertion is detected 109 RENESAS Bits 6 5 PITREQE1 0 IREQ interrupt enable In cases where the card in slot 1 is an I O card these bits enable and disable IREQ interrupts and set the interrupt mode Before changing these bits PCC1CSCR bit 5 PITREQ should first be cleared In the case of a memory card operations on these bits are invalid Bit 6 Bit5 IREQ1 IREQO Settings 0 0 Interrupt disabled P1IREQ does not change regardless of IREQ signal level 0 1 Level mode interrupt P1IREQ is set when the IREQ signal is at low level and an interrupt request is generated 1 0 Edge mode interrupt P1IREQ is set at the IREQ signal falling edge and an interrupt request is generated 1 1 Edge mode interrupt P1IREQ is set at the IREQ signal rising edge and an interrupt request is gener
84. ns available without Hitachi s prior written consent Other Important Things to Keep in Mind 1 Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 2 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Figures Some figures in this users manual may show items different from your actual system Limited Anticipation of Danger Hitachi cannot anticipate every possible circumstance that might involve a potential hazard The warnings in this user s manual and on the CPU board are therefore not all inclusive Therefore you must use the CPU board safely at your own risk II RENESAS SAFETY PAGE READ FIRST e READ this user s manual before using this CPU board e KEEP the user s manual handy for future reference Do not attempt to use the CPU board until you fully understand its mechanism DEFINITION OF SIGNAL WORDS gt This is the safety alert symbol It is used to alert you to potential personal injury hazards Obey all safety messages that follow this symbol to avoid possible injury or death A DANGER DANGER indicates an imminently hazardous situation which if not avoided will result in death or serio
85. nsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corporation assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a
86. oard and the user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the expansion board and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST gt AC power cable I Connected to CN5 Figure 2 8 AC Power Supply Cable Connection RENESAS 2 3 Connecting the User Expansion Board Figure 2 9 shows how to connect the user expansion board A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST User expansion board Figure 2 9 User Expansion Board Connection RENESAS 2 6 Connecting the PCMCIA Card Figure 2 10 shows how to connect the PCMCIA card Release button gt 2 SPU U lt Slot 0 o aw PCMCIA card Memory card I O card Insert into PCMCIA slot 0 or 1 Figure 2 10 PCMCIA Card Connection To use a PCMCIA card memory card I O card insert the PCMCIA card into slot 0 or slot 1 To remove the PCMCIA card press the release button in the direction of the arrow RENESAS 2 7 Switches Table 2 2 lists the switches used in the CPU board and figure 2 11 shows where the three switches are located on the CPU boa
87. ount Comm port baudrate Status SH7 29R Monitor SH3DSP Big Endian Privileged Mode OFF OFF SH 23R CPU 200 MHz External Bus 66 7 MHz dia mmm dd yyyy Break Breakpoint Omin Os 115200 bit s Oms 279 8us Figure 3 44 System Status Window Run Time Count Result Notes 1 The run time will vary depending on the execution environment 2 The run time can be measured by executing with Go but cannot be measured by Step In Step Out or Step Over RENESAS 3 17 Saving a Session If a program has been downloaded the corresponding source file is displayed and numerous windows are opened it can take some time to restore this setup the next time the program is downloaded The HDI is able to save the current settings for retrieval the next time the program is loaded in order to reduce setup time In order to save a session which has already been named or to save the session with the same name as the current object file select Save Session from the File menu To save the current settings as a session with a new name select the Save Session As command from the File menu A dialog box is displayed enter the new name for the session Three files are saved the HDI session file hds the target session file hdt and the watch session file hdw The target session file stores the following information e Software breakpoint information e I O definition file information e Run time count
88. pansion bus area Area 5 Expansion bus area Area 6 PCMCIA area 80 RENESAS Physical area 00000000 Area 0 04000000 Area 1 08000000 Area 2 0C000000 Area 3 10000000 Area 4 14000000 Area 5 18000000 Area 6 10000000 Reserved by CPU 1FFFFFFF Flash memory on board register 16 bit bus width Reserved by CPU Internal I O area For expansion SDRAM 32 bit bus width For expansion For expansion For PCMCIA I F Reserved by CPU 00000000 Monitor program area 0007FFFC __512 kbytes 00080000 Shadow area of monitor program OOFFFFFE 01000000 On board register O1FFFFFE 02000000 Expansion bus 0C000000 User program area 15 5 Mbytes 32 bit bus width OCF7FFFFL Firmware work OCFFFFFF rea 0 5 Mbytes Shadow area OFFFFFFC of SDRAM 18000000 Slot0 attribute memory 18800000 19000000 Slot1 attribute memory oo a 1A000000 Slot 0 I O area 1A800000 gt or T TO 1B000000 gt L area BFFFFFF Not used 01000000 01800000 01800012 O1FFFFFE Register area for monitor program PCMCIA Register Reserved Unusable Figure 5 2 CPU Board Memory Map RENESAS 01800000 01800002 01800004 01800006 01800008 0180000A 0180000C 0180000E 01800010 PCC01SR PCCOGCR PCCOCSCR PCCOCSCIER PCC1ISR PCC1GCR PCC1CSCR PCC1CSCIER PCCVCR 81 5 4 External Interface 5 4 1 Serial Interface A WARNING Always switch OFF
89. pending on the language of the OS being used The figures appearing in this manual are for the English version of Microsoft Windows 98 Related Manuals e SH7729R Hardware Manual e SH3 SH3E SH3 DSP Programming Manual e SH Series Cross Assembler User s Manual e H Series Linkage Editor User s Manual e H Series Librarian User s Manual RENESAS SuperH RISC Engine C C Compiler User s Manual SH Series Simulator Debugger User s Manual Hitachi Debugging Interface User s Manual available in the CD ROM supplied with this CPU board Hitachi Embedded Workshop User s Manual When connecting an E10A emulator to the CPU board the following manual should also be read SH7729R E10A Emulator User s Manual Note Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and or other countries RENESAS Contents Pr f ace zoo A A EA AO O i Section T OVERVISW npon enio be eas e Eia dase bodlestns RERA 1 IA EE n ia A E E A A Od E SEE 1 1 2 System Confisurat oie naan R E AAS a ee as 2 IE3 OW AUDIT SS AE ETE EET A o A EA NO E O O a EEN 3 TA Components onsas Shirt Sve teas hes data a da Saad RRT 4 13 CDR COMMIS na ss venice A A rok i AZ oo EEE 5 1 6 Environmental Conditions e eeee eee eee aaa anawa enaaee 6 S ction 2 PreparaliomDel re Uses ai A R A a R 7 21 CPU Board Pr paration sis nio o ORO O U EE 7 2 2 SAD LInstallationy asi A SAO a ZUW A
90. put only Provides the same frequency as that set by jumpers J9 and J10 It is recommended that a terminal resistor is connected to the expansion board See figure 5 10 10 When used as a port signals are limited to the output direction 88 RENESAS Table 5 5 Pin Assignment of Expansion Connector CN6 Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function 1 PTE 7 2 20 _CE2A PTE 4 39 _DREQ1 PTD 6 2 GND 21 GND 40 GND 3 _CAS2L 22 _RAS2U PTE 1 41 DACKO PTD 5 PTE 6 4 GND 23 ADTRG PTH 5 42 GND 5 _CE2B PTE 5 24 GND 43 DACK1 PTD 7 6 GND 25 PINT 15 PTF 7 2 44 GND 7 _CAS2H 26 PINT 14 PTF 6 2 45 _CA PTE 3 8 _RESETM 27 PINT 13 PTF 5 2 46 GND 9 GND 28 PINT 12 PTF 4 2 47 DRAKO PTD 1 10 IOIS16 PTGI 7 29 _iRLS 3 48 GND PINT 11 PTF 3 11 PTG 6 30 _iRLS 2 49 DRAK1 PTD 0 PINT 10 PTF 2 12 PTG 5 2 31 _iRLS 1 50 GND PINT 9 PTF 1 138 PTG 4 32 _iRLS O 51 MCSI4 PINT O PINT 8 PTF O KIJ PTC OKI 14 PTG 3 2 33 PTE 0 2 52 GND 15 PTGI2 2 34 GND 53 MCSI5 PINT 5 PTC 5 16 PTG 1 2 35 GND 54 CS0 17 PTG O 2 36 GND 55 MCS 6 PINT 6 PTC 6 18 _RAS3U 37 _ DREQO 56 GND PTE 2 PTD 4 19 GND 38 GND 57 MCS 7 PINT 7 PTC 7 Note Some signals are converted and input to the CPU or output to the expansion connector as follows 2 With the E10A emulator connected these signal pins cannot be used
91. r BSC Figure 5 18 is a flowchart of the procedure for setting the initial settings of the bus state controller BSC For information on the settings of each BSC register please refer to section 5 6 3 Initial Settings of CPU Bus State Controller BSC Software timer 1 5us or more gt Automatic refresh x 8 times 180 ns once A5A6 66 7 MHz RTCOR Normal value A553 33 3 MHz Figure 5 18 Procedure for Setting BSC Settings 118 RENESAS 5 6 3 Initial Settings of CPU Bus State Controller BSC The clock mode is set to 7 in the CPU board In the bus state controller BSC registers bits corresponding to areas 0 and 3 must not be modified because these areas are assigned to resources of the CPU board If these bits are modified the CPU board will not operate The following shows the initial BSC register values set by the monitor program In the figures the shaded bits must not be modified Separate figures are used to show the register values that depend on the operating frequency CKIO Registers Whose Values are the Same at 66 7 MHz and 33 3 MHz e BCR1 H FFFFFF60 H 0009 No Bit HIZ HIZ JEND JAO JAO JA5 A5 A6 A6 DRA DRA IDRA A5_ A6 name MEM ICNT JIAN BST1 BSTOIBST1 BSTO BST1 IBSTO M M M PCM PCM TP2 TP1 TPO Initial O O 0 0 0 0 0 0 0 0 0 0 1 0 0 1 value Bit No Bit A6 A6 A5 A5 A4 A4 A3 JA3 JA2 A2 name SZ1 SZO SZ1 SZO SZ1 SZO SZ1 SZO SZ1 SZO Initial
92. rd Table 2 2 Switch Specifications Switch Symbol Type Function Manual reset SW1 Push button Forcibly initializes the system Use this switch when switch Red the system does not operate correctly for example when the user program goes out of control Abort switch SW2 Push button Forcibly terminates command execution Aborts user Black program execution and returns the system to firmware command input wait state Power supply SW3 Rocker switch Turns on and off the 5 V power supplied to the CPU switch board Note If the power supply is turned on while pressing the manual reset switch the CPU board and HDI will not be started Please do not operate the manual reset switch while turning on the power Abort switch Manual reset switch Figure 2 11 Switch Location 15 RENESAS 2 8 Jumpers A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Table 2 3 lists the jumpers on the CPU board and figure 2 12 shows how to insert a jumper pin RENESAS Table 2 3 Jumper Settings Symbol Function Setting Description JI Selects endian Closed Big endian default at shipment Open Little endian J2 For test
93. rogram a user interrupt handler must be created according to the directions in section 7 1 Creation of User Interrupt Handlers The HDI installer CD R supplied with the CPU board contains a sample program for the user interrupt handler and SCIF driver For details on the sample program refer to section 7 3 Sample Program 7 2 1 Creation of SCI Driver Note the following when creating the SCIO driver e To receive serial data an interrupt must be used Create a SCI RXI receive data full interrupt request processing routine e When the HALT button is pressed during serial receiving operation the HDI sends the HALT code H 12 to the CPU board When the HALT code is received execution must branch to the HALT break processing address in the CPU board Table 7 2 HALT Break Destination Address Endian HALT Break Destination Address Big endian H A00090E0 Little endian H A00490E0 e The branch to the HALT break processing is performed in the same interface as the branch to user interrupt handlers For details refer to section 7 1 Creation of User Interrupt Handlers Notes 1 The SCIO is used for communication between the CPU board and the host computer If the user uses the SCIO for a purpose other than the communication with the Simulated I O Window window correct operation cannot be guaranteed For such purposes use the SCI1 IrDA or SCI2 SCIF 2 If processing that branches execution to the HALT break when the HALT code is r
94. rovided AC power supply adapter and AC power supply cable The method of connection is shown in figure 2 14 A WARNING Observe the precautions listed below Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Always use the provided AC power supply adapter 2 Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Figure 2 14 Front View of Power Supply Connector 20 RENESAS CPU board top view Figure 2 15 AC Power Supply Cable Connection 21 RENESAS 22 RENESAS Section 3 Tutorial 3 1 Introduction The following describes the main functions of the HDI by using a tutorial program The tutorial program is based on the C program that sorts ten random data items in ascending or descending order The tutorial program is included in the sort c file The compiled load module is provided in the SYSROF format and is included in the sort abs file The tutorial program is automatically installed when the HDI is installed Table 3 1 lists the tutorial program configuration Table 3 1 Tutorial Program Configuration Item Contents Tutorial file load module install directory tutorial sort abs Tutorial file source file install directory tutorial sort c For the operating environment use the RAM area starting from ad
95. ructions 3 When a multiple step execution is performed for a program that contains the SLEEP instruction from the Step menu the execution speed RATE must be set to 6 Otherwise an error Command not ready error will occur when the SLEEP instruction is executed and execution from then on cannot be accepted In such case press the abort switch and start execution again 128 RENESAS 4 During step execution standard C libraries are also executed To return to a higher level function use Step Out In a for statement or a while statement executing a single step does not move execution to the next line To move to the next line execute two steps 5 If a user program is halted by a break due to the step execution or a breakpoint the Halt button or the abort switch SW2 it is handled same as the exception in the user program If these causes are generated 16 bytes of the user stack area will be used Reserve the sufficient stack areas and do not allocate the user program or data 6 If the Halt button is pressed in the sleep mode the operation cannot be guaranteed When the mode should be returned from sleep press the abort switch on the board or enter other interrupts 7 If a breakpoint is set for the sleep instruction the execution time during sleep mode cannot be measured When the user wants to measure the execution time including the sleep instruction do not set a breakpoint for the sleep instruction 20 Br
96. ry Sample Simio Main c Main program install directory Sample Simio Resetprg src Start program install directory Sample Simio Serial h SCI relation definition Global variable stack area install directory Sample Simio Vect inc Vector definition install directory Sample Simio Vecttbl src Vector table area install directory Sample Simio Vhandler src Interrupt handler install directory Sample Simio Simio hwp HEW HWP file install directory Sample Simio Syntax txt Syntax text install directory Sample Simio Big Simio abs ABS file for big endian install directory Sample Simio Little Simio abs ABS file for little endian install directory Sample Simio Makefile Big mak Make file for big endian install directory Sample Simio Stacksct src sem ee ee ee aa ey ie ee ee ma ee ee a install directory Sample Simio Makefile Little mak Sections Table 7 4 shows the sections for the sample program Make file for little endian Table 7 4 Sections for the Sample Program Address Section Name H 0C000000 Start IntPRG P and C H OCF7F000 Dataarea H OCF7FCOO H OCF FFFF Stack H AC010000 INTHandler and INTTBL 141 RENESAS Interrupt Handlers The interrupt sources and their processing are shown in table 7 5 If an interrupt that is not listed in table 7 5 occurs a
97. s described in this section Start setup EXE in the SETUP directory of the CD R If any other application is running close it before starting the HDI installer Figure 2 2 setup EXE Icon This runs the HDI installer A dialog box will first prompt you to select a language for the installation process Select a language then continue according to the instructions displayed by the installer Note Under Windows NT 4 0 install the HDI in the administrator mode HDI Installation Directory The default directory for installing the HDI depends on whether the Hitachi Embedded Workshop HEW has been installed in the host computer as shown in table 2 1 Table 2 1 Default Installation Directory HEW Program Default Installation Directory HEW has not been installed CNHDI5_CBV7729R HEW has been installed CAHEW HDI5 CB 7729R in this example in C HEW Backup File If another version of HDI has already been installed a message The HDI INI file has already existed Can it be overwritten will be displayed Clicking Yes will make a backup of the existing file in the Backup directory of the installation directory When installation is complete HDI for SH7729R CPU board can be selected from the start menu RENESAS BQ windows Update o Sajema mjAccessories SARE Online Services x Favorites StartUp MS DOS Prompt Documents SJ Windows Explorer Ra HDI for SH7729R CPU board gt JAHDI for SH7729R CPU board E
98. s generated when PCCOCSCR bit 2 is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 RDY BSY interrupt disabled 1 RDY BSY interrupt enabled 105 RENESAS Bit 1 POBWE battery voltage low interrupt enable In cases where the card in slot 0 is a memory card this bit enables and disables battery voltage low interrupts An interrupt request is generated when PCCOCSCR bit 1 is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 Battery voltage low interrupt disabled 1 Battery voltage low interrupt enabled Bit 0 POBDE battery replacement interrupt enable In cases where the card in slot 0 is a memory card this bit enables and disables battery replacement interrupts An interrupt request is generated when PCCOCSCR bit 0 is set and this bit is 1 In the case of an I O card operations on this bit are invalid 0 Battery replacement interrupt disabled 1 Battery replacement interrupt enabled 5 PCCI interface status register PCC1ISR nw R R R R R R R R ww CCIC value This register monitors the values of channel input signals Here 1 high and 0 low level 6 PCCI general control register PCC1GCR Bit aw pw jm aw pR p pw fw Initial value This register controls the bus buffer reset and other operations for channel 1 It also controls the uppermost three bits of the channel 1 address used to access the 64 Mbytes from the 8 Mby
99. shooting 6 1 Notes 1 When executing a user program the following interrupts cannot be used This is because the monitor program is using the following CPU functions for debugging purposes User Break Controller UBC Serial Communication Interface SCI TRAPA 255 Trap instruction 2 The monitor program uses NMI and SCI interrupts so the user can use interrupts of mask level 14 or lower If an interrupt is set to mask level 15 correct operation cannot be guaranteed The default mask level is set to 14 3 Interrupt and Exception Display 1 The following interrupts and exceptions are displayed on the status bar during user program execution Address error Illegal general instruction Illegal slot instruction NMI 2 When an exception occurs on the CPU board while the user program is not being executed the HDI will display the EXPEVT code that corresponds to the cause of the exception and the monitor program will enter the reset input wait state In this case turn the power to the CPU board off and on or input a reset and start the HDI to initiate link up processing Message received from monitor Exception occurred EXPEVT 0x00000040 Please reset the CPU board Figure 6 1 Error Message Displayed at Exception Instruction TLB Miss Exception 125 RENESAS 4 Breakpoints cannot be set in a delay slot of a user program If an attempt is made to set such a breakpoint the following message
100. switched with jumpers Bit configuration Start bit 1 bit Stop bit 1 bit Parity none Data length 8 bits Controller On chip SCI serial communication interface in the SH7729R Driver LT1181ACSW manufactured by LINEAR TECHNOLOGY CORP Connectors CPU board connector DELC J9PAF 20L9 manufactured by Japan Aviation Electronics Industry Ltd Figure 5 3 shows the wiring connection between the host computer IBM PC compatible machine serial interface connector and the CPU board interface connector Figure 5 4 shows the serial interface connector pin arrangement A serial cable that matches the specifications shown in figures 5 3 and 5 4 must be used For details on serial interface cable connection refer to section 2 4 Connecting Cables IBM PC compatible machine CPU board Serial interface connector Serial interface connector Pin 4 and pin 6 are directly connected on the CPU board Pin 7 and pin 8 are directly connected on the CPU board 2 3 4 5 6 7 8 9 Figure 5 3 Connection to Host Computer 83 RENESAS Pin arrangement of serial interface connector Pin 6 Pin 9 Figure 5 4 Serial Interface Connector Pin Arrangement 5 4 2 User Expansion Board Interface The CPU board has a connector for the user expansion board interface A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will d
101. t mm Dimension tolerance 0 1mm Figure 5 13 Connection Dimension Specifications of User Expansion Board CN3 96 RENESAS 5 4 3 PCMCIA Interface A WARNING Install the PCMCIA driver in the CPU board before inserting or removing a card while the power is on Failure to do so will damage the card Overview This board is provided with two slots for PCMCIA type 1 and type 2 cards Both slots can be used with either I O cards or with memory cards Card voltages of 3 3 V and 5 V are supported This CPU board is not provided with PCMCIA drivers When using the PCMCIA slots you must provide your own driver software Figure 5 14 shows the pin arrangements for PCMCIA slot 0 and slot 1 Pin assignments for slot 0 and slot are listed in tables 5 8 and 5 9 respectively eeee000000000000000000002000002 OOOO Co CEES Ce eoee cece ce ce cee Coe Coe ee ee 0202002 CeCe ee CeCe ee LO PCMCIA slot Figure 5 14 PCMCIA Slot 0 and Slot 1 Pin Arrangements 97 RENESAS Table 5 8 PCMCIA Card Slot 0 CN9 Pin Assignments Pin No Signal Name Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 GND 18 VPPA 35 GND 52 VPPA 2 PCCODA3 19 PCCOAD16 36 POCD1 53 PCCOAD22 3 PCCODA4 20 PCCOAD15 37 PCCODA11 54 PCCOAD23 4 PCCODA5 21 PCCOAD12 38 PCCODA12 55 PCCOAD24 5 PCCODA6 22 PCCOAD7 39 PCCODA13 56 PCCOAD25 6 PCCODA7 23 PCCOAD6 40 PCCODA14 57 POVS2 7 POCE1 24 PCCOAD5
102. t is when the RDY BSY pin changes from low to high there is a transition from a busy state to a ready state the bit is cleared by writing O to it The interrupt can be masked by PCC1CSCIER bit 2 0 No change in RDY BSY 1 RDY BSY changed from low to high level 108 RENESAS Bit 1 PIBW battery voltage low interrupt data is preserved but the battery must be replaced In cases where the card of slot 1 is a memory card this bit is set to 1 when the PCC1IBVD2 BVD1 signal indicates a drop in battery voltage in the case of an I O card this bit is always 0 The condition for setting this bit is when PCC1BVD2 Low and in addition PCC1BVD1 High the bit is cleared by writing O to it The interrupt can be masked by PCC1CSCIER bit 1 0 Memory card of slot 1 does not indicate low battery voltage 1 Memory card of slot 1 indicates low battery voltage Bit 0 P1BD battery replacement interrupt In cases where the card of slot 1 is a memory card this bit is set to 1 when the PCC1IBVD2 BVD1 signal indicates the battery needs to be replaced in the case of an I O card this bit is always 0 The conditions for setting this bit are either that PCC1BVD2 High and PCCIBVD1 Low or else that PCC1BVD2 Low and PCCIBVD1 Low This bit is cleared by writing O to it The interrupt can be masked by PCCICSCIER bit 0 0 Battery of slot 1 memory card does not need replacement 1 Battery of slot 1 memory card needs replacement integrity of data in memory card
103. t s to match the setting of jumper J7 Conneciion is not possible at any other setting I O definition file Sets the I O register definition file Click the Browse button to select the SH7729R definition file When selecting a file the I O Registers window accessed from the View menu can be used to display register information Download with verify The CPU board does not support this function this box cannot be selected Delete breakpoints when program is reloaded When this box is checked all breakpoints are deleted when a program is reloaded Reset CPU when program has been downloaded When this box is checked registers are initialized when a program is loaded No reset signal is input to the CPU board Note Only the program counter status register and VBR are initialized PC H AC000000 and SR H 600010E0 The value of VBR depends on the endian Clicking the OK button sets the setup conditions If the Cancel button is clicked this dialog box is closed without setting the conditions 67 RENESAS 4 2 2 Breakpoints Window Function This window lists all break conditions that have been set This window can be displayed by selecting Breakpoints on the View menu Window Breakpoints Oo ol x Enable File Symbol A Type Sort c 21 AC000038 PC breakpoint Figure 4 2 Breakpoints Window 68 RENESAS Description The Breakpoints window displays breakpo
104. t to 1 in the case of a memory card this bit is always 0 Conditions for setting this bit conform to the settings for bits 6 and 5 of PCCICSCIER IREQEI 0 interrupt disabled level mode rising edge mode falling edge mode In the case of an edge mode the interrupt can be cleared by writing O to this bit 0 No IREQ interrupt request 1 IREQ interrupt request generated for the slot 1 I O card Bit 4 PIS C STSCHG interrupt In cases where the slot card is an I O card when an interrupt is generated by PCCIBVD1 STSCHG this bit is set to 1 in the case of a memory card it is always 0 The condition for setting the bit is a transition of the STSCHG pin from high to low level The bit is cleared by writing O to it The interrupt can be masked by PCC1CSCIER bit 4 0 No STSCHG interrupt request 1 STSCHG interrupt request by the slot 1 I O card Bit 3 PICDC card detection interrupt This indicates that either PCC1CD2 or PCCICDI has changed a card has been inserted or removed The condition for setting the bit is a change in signal level it is cleared by writing O to it The interrupt can be masked by PCC1CSCIER bit 3 0 No change in PCC1CD2 PCC1CD1 1 Either PCC1CD2 or PCCICDI has changed Bit 2 PIRC ready change interrupt In cases where the card of slot is a memory card this bit is set to I when the PCCIRDY signal changes in cases where the card is an I O card this bit is always 0 The condition for setting the bi
105. te window 106 RENESAS Bit 7 PIDRVE external buffer control 0 PCCIDRYV signal driven high buffer disabled 1 PCCIDRYV signal driven low buffer enabled Bit6 PIRES reset control 0 PCCIRES signal driven low normal operation 1 PCCIRES signal driven high reset Bit5 PIPCCT PCMCIA card type interrupt processing varies depending on whether it is memory card or I O card 0 Slot I card handled as memory card 1 Slot 1 card handled as I O card Bits 4 3 Not used Always read as 0 Bits 2 0 P1PA25 23 used for upper address control window switching 0 Corresponding address line driven low 1 Corresponding address line driven high 7 PCC1 card status change register PCC1CSCR ew few R jaw wR Initial value This register contains flags used to monitor changes in the status of channel 1 By reading this register after an interrupt IRQ1 is received the cause of the interrupt can be identified Bit 7 PISCDI software card detection interrupt When writing data via software an interrupt is generated This bit can be set freely but as in the case of a card detection interrupt the interrupt itself is masked by PCC1CSCIER bit 3 PICDE 0 Interrupt not generated 1 Slot 1 card detection interrupt generated 107 RENESAS Bit 6 Not used Always read as 0 Bit5 PIIREQ IREQ interrupt In cases where the card in slot 1 is an I O card when an interrupt is generated by PCCIRDY IREQ this bit is se
106. te low battery voltage 1 Memory card of slot 0 indicates low battery voltage Bit 0 POBD battery replacement interrupt In cases where the card of slot 0 is a memory card this bit is set to 1 when the PCCOBVD2 BVD1 signal indicates the battery needs to be replaced in the case of an I O card this bit is always O The conditions for setting this bit are either that PCCOBVD2 High and PCCOBVD1 Low or else that PCCOBVD2 Low and PCCOBVD1 Low This bit is cleared by writing O to it The interrupt can be masked by PCCOCSCIER bit 0 0 Battery of slot 0 memory card does not need replacement 1 Battery of slot 0 memory card needs replacement integrity of data in memory card not guaranteed 4 PCCO card status change interrupt enable register PCCOCSCIER PE a z ee Oe ee ee ee Name POCRE POIREQE1 POIREQEO POSCE POCDE PORE POBWE POBDE This register masks status change interrupts for channel 0 An interrupt request is generated when the corresponding bits of PCCOCSCR and this register are both 1 Bit 7 POCRE PCCOGCR reset enable When insertion of a card into slot 0 is detected CD1 changes from high to low or CD2 changes from high to low this bit determines whether or not PCCOGCR is initialized 0 GCR is not initialized even when card insertion is detected 1 GCR is initialized when card insertion is detected 104 RENESAS Bits 6 5 POIREQE1 0 IREQ interrupt enable In cases where the card in slot 0 is an I O card
107. the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST The CPU board has a serial interface 1 channel that conforms to RS 232C and can interface with the host computer An on chip serial communication interface SCIO in the CPU is used for the interface between the host computer and the CPU board Therefore the users cannot use the SCIO For the connector a 9 pin D sub connector is used A baud rate of 57 600 bit s or 115 200 bit s can be selected To set the baud rate refer to section 2 8 Jumpers Table 5 2 lists the pin assignment for the serial interface connector Table 5 3 shows the serial interface specifications For details on serial interface cable connection refer to section 2 4 Connecting Cables Table 5 2 Pin Assignment of the Serial Interface Connector Pin No Signal Name Description 1 Reserved No connection 2 RXD Received serial data 3 TXD Transmitted serial data 4 DTR Data terminal ready 5 SG Signal ground 6 DSR Data set ready 7 RTS Request to send 8 CTS Clear to send 9 Reserved No connection 82 RENESAS Table 5 3 Serial Interface Specifications Item Specifications Synchronization method Asynchronous method Transfer rate 57 600 or 115 200 bit s can be
108. these bits enable and disable IREQ interrupts and set the interrupt mode Before changing these bits PCCOCSCR bit 5 POIREQ should first be cleared In the case of a memory card operations on these bits are invalid Bit 6 Bit 5 IREQ1 IREQo Settings 0 0 Interrupt disabled POIREQ does not change regardless of IREQ signal level 0 1 Level mode interrupt POIREQ is set when the IREQ signal is at low level and an interrupt request is generated 1 0 Edge mode interrupt POIREQ is set at the IREQ signal falling edge and an interrupt request is generated 1 1 Edge mode interrupt POIREQ is set at the IREQ signal rising edge and an interrupt request is generated Bit 4 POSCE STSCHG interrupt enable In cases where the card in slot 0 is an I O card this bit enables and disables PCCOBVD1 STSCHG interrupts An interrupt request is generated when PCCOCSCR bit 4 is set and this bit is 1 When the card is a memory card operations on this bit are invalid 0 STSCHG interrupt disabled 1 STSCHG interrupt enabled Bit 3 POCDE card detection interrupt enable Enables and disables PCCOCD2 and PCCOCD1 interrupts An interrupt request is generated when PCCOCSCR bit 3 is set and this bit is 1 0 PCCOCD2 PCCOCD1 interrupt disabled 1 PCCOCD2 PCCOCD1 interrupt enabled Bit 2 PORE ready change interrupt enable In cases where the card in slot 0 is a memory card this bit enables and disables PCCORDY interrupts An interrupt request i
109. urement Mode Select a measurement unit here The selectable measurement units are shown in table 3 7 Table 3 7 Selectable Measurement Units Measurement Unit Maximum Measurable Time 0 12 us Approximately 9 minutes 0 48 us Approximately 35 minutes 1 92 us Approximately 2 hours and 18 minutes 7 68 us Approximately 9 hours e Click the OK button to enable the run time count function RENESAS 57 e Click the Go button Execution will stop at the line following the sort function and the run time will be displayed in a message box Ra Hitachi Debugging Interface Sort SH7729R CPU board Sort c MEE z Edit View Run Memory Setup Window Help TETAP ARE E PE TE oe RRRIET gt ERZER 1ne A La Source 2000000 _main void maintvoid _ Jong a 10 Run Time Count ax ac000004 Oh Omin Os Oms 279 8us acOoo00c ac000014 ac000018 acO0001c ac000038 ac000044 ac000048 ac00004c ac000050 ac000058 ac00005c fa fa m ay AP fr gi e GE E gt Break Breakpoint NUM Figure 3 43 Program Window Stopped at a Breakpoint after Run Time Count The time from the sort function call to the return to the caller can be checked at Run Time Count on the Platform sheet in the System Status window 58 RENESAS System Status Item Connected to CPU Mode Cache Status MMU Status I O definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time C
110. us injury A WARNING WARNING indicates a potentially hazardous situation which if not avoided could result in death or serious injury A CAUTION CAUTION indicates a potentially hazardous situation which if not avoided may result in minor or moderate injury CAUTION CAUTION used without the safety alert symbol indicates a potentially hazardous situation which if not avoided may result in property damage NOTE emphasizes essential information lt RENESAS A WARNING Observe the precautions listed below Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Always satisfy the power supply conditions which are described in the manual Ensure that there are no short circuits between VCC and GND Do not apply voltage that is outside the guaranteed range Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS When turning on the CPU board or the user system take care that conductive material does not touch the CPU board or the user system Check that the pin numbers on the connectors of the CPU board and those on the user system are correctly aligned before connecting the CPU board and the user system RENESAS Preface Thank you for purchasing the CPU board for Hitachi s SH7729R microcomputer The CPU board

SH7729R CPU Board HS7729RSTC01H User`s Manual

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