UM10408_1
Contents
1. 1 Fig 8 Disabling DAC IC23 The clock signal can be generated on the board as there is a Phase Locked Loop PLL available UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 11 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D by oma ously W9 12 L FT Cr REA ELS oe 4 ih Ch a 2014 Fo at of 2 ft a ied ONTRAN o Drg To ie Na i To i S A nnani Annittighiiil LET i Ay EN i DE eS i T aia sey gt gt x on ty 1 Default configuration Fig 9 On board clock generation By default the frame clock needed by the FPGA and the two DACs is provided by IC10 In that mode device internal VCO is used and locked to a 125Mhz reference oscillator The actual clock frequency provided to the DAC and FPGA is set via software Dip switch SW2 sets IC10 startup behavior Table 3 SW2 IC10 startup behavior Postion ON OFF 1 Load default registers settings at No default registers settings at startup Resulting frequency will UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 12 of 32 UM10408 1 Demonstration Board for DAC1x08D NXP Semiconductors Postion ON OFF be 312 5Mhz startup 2 Power down device Devi2. DC Power supply for complete board 6V 3A L a u aoe y z amr hO m mml ie i ye 3 p gt g r z Swie os i oh MS se Eae ge te NEL PAE a om TE a A T E es as he Rba TT e E os I nr l EAT N Erien a fe foe 9 ne i a TE altire EREN y seih 9 8 PI A PCB2064 5 INN DAC1408D DEMONSTRATOR 1 PCB2064 3 0 overview Fig 1 Demonstration board DAC1X08D setup USB port for connection to PC USB and SPI controller UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 3 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1Tx08D 1 2 Essential Features of the Demonstration Board 1 NXP serial DAC device 9x9mm package Fig 2 DAC1X08D with 4 lanes in pairs of CML compliant differential Fig 2 shows the DAC1x08D in its environment The input is a series CML connection capable of sustaining a throughput rate of 3 125Gsps as specified by the JESD204A standard The output is connected to a transformer and then to an SMA output Alternatively an analog quadrature modulator can be used by means of de soldering soldering 0 ohms resistors The logic device Field Programmable Gate Array FPGA is connected to the DAC1x08D via 4 Lanes with each lane in differential CML referenced to the positive supply Moreover a synchronization signal SYNC is routed in differential
3. o OL F 39 lt PROG lt F DF MON 1 Selecting the 30K mode Fig 6 Configuring the FPGA Larger memories allow DAC ACPR measurements The FPGA operating frequency equals the maximum DAC input data rate UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 8 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D COM 91234 TP Ateetan B TEELE Teyi 42 H nSt R7 PS VIRTEX XC5VLX50T FFG1136FGU0845 DD2607428A1 888 8 86 6 e pt 1 Fig 7 D9 D16 indicates the status of the FPGA There are two rows of LEDs Each reflects the status of one of the Jesd204A transmitter D17 D24 are tied to the upper link and D8 D15 are tied to the lower one Table 2 FPGA status LEDs Table description optional Upper Lower Meaning D17 D8 always off D18 D9 SYNC_REQUEST UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 9 of 32 NXP Semiconductors U M1 0408_1 UM10408_1 User manual Demonstration Board for DAC1x08D Upper Lower Meaning D19 D10 FPGA GTPO lock status D20 D11 FPGA GTP1 lock status D21 D12 GTPO reset done D22 D13 GTP1 reset done D23 D14 always off D24 D15 FPGA Reset At startup time or after pressing reset button LEDs D9 D10 D11 D13 D18 D20 D21 D22 should lit The S
4. close the window using the red button Exit e Step 5 Press DAC_1 control button Back to main menu p There are three ways to configure the DAC UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 23 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D 1 Using the first three tabs COMMon PHINCO DAC_CFG and DAC_AUX the user can configure the device in a graphical way 2 Using the tabs PageO Page1 Page2 Page3 Page4 Page5d Page6 and Page the user can access the device registers in detail This requires an advanced knowledge of the device 3 Using tab Execute _DAC_cmd_file the user can run presets that configure the DAC in a known behaviour The first method is depicted below i DAC_CTLM DEW oe i x Back to main menu Configuring DAC c13 COMMon PHINCO pacera DAC_AUX Paged Paget Page2 Page4 PageS Page Page Execute_DAC_cmd_file PHASE _CORR DAC Registers Jesd20 link DAC1408 lvproj My Computer 4 Use the buttons sliders and numeric fields to set the DAC configuration Then once you are finished press DAC Registers update and Jesd204 link update buttons The expected signal should be available The Jesd204 link update button needs to be pressed only once between two resets Once the jesd
5. 0408 1 8 Contents oo N N me 3 1 3 2 UM10408_1 User manual Introduction coccinea cassette eeeecaewetcccareceencuetes 3 Setup OVEIVICW cccecccccecceseeeeeeeeeeeeeeeeeeeeeeeeaas 3 Essential Features of the Demonstration Board 4 BRITA Soci crests ce tesemcneaeteceseticeecexnuseceesteseciees 15 Setup example cccccccccceeeeeeeeeeeeesssaeeeeeeeeees 15 SPIGQUICK Stafi sna 16 E a U EE ELE E TT A 16 OPI interna E rieien Ai 19 Annex 1 default dip switches and jumpers selling S erur tunes seers ecw 27 Annex 2 Troubleshooting ccccsssssesseeeseees 29 5 1 or Rev 01 5 29 july 2010 Demonstration Board for DAC1x08D Multiples FT2232 devices connected to the host Fe EEE E E E E ES e PA 29 Sanity checks if the system doesn t generate the expected waveform seccceeceeeeeeeeesaeeeeeseeaeees 29 Legal information ccccssseesessseeeeeneeeeeeneeseenees 30 DefinitiOnS 0 2055 IRM ee sececeeeecceeeeeeees 30 DISCIAIMENS 2 0000000 QBBD oeecccsecccceeecceeesceeeecaees 30 Licenses a Se ln 30 Patents ee ee en 30 Trademarks 22 C 30 Cae cS n O MED daweusvencniaesstausnsnes 31 Contents N erect nnnneeeeeceeeeneees 32 continued gt gt NXP B V 2009 All rights reserved 32 of 32
6. 204a link is running the user can change the DAC settings e g minus _3dB without restarting the link He just needs to press DAC Registers update to see the changes UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 24 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D The third method is accessible via the tab Execute DAC cmd _ file This GUI is used to load script file that contains registers setting for the DAC These are ASCII files that can be modified at will LT Jo Back to main menu 4 AyawfresO01 FR CFRO1 51 Usersi4fifrg0517 datalSyncWworkiandromedatandromeda _fFrg051 74 Work DAC OAC 14080650 04C 1408 labview Settingsinzi one _board_spitw_2x_pll bypass txt Load a command file provided with the software at the following folder DAC 1408 Settings Mame Size Type Date Modifie E nz_board_spi w_2x_pll bypass txt LEB Text Document 2003 10 27 E nz_board_spi w 2x pll bypass ssbm txt LEB Text Document 2009 10 27 2 nz board spidiw 2x pll on txt 1 KE Text Document 2009 10 27 nn board spidw _2x_pll on_ssbrm txt 1 KE Text Document 2009 10 27 n2_ board spidi 4 _pll bypass txt LEB Text Document 2009 11 24 n board spidw 4x pl bypass ssbm txt LEB Text Document 2009 10 27 Z nz board spidi _4x_pll onm txt 1 KE Text Document 2009 11 20 E nz_board_spi w _4x_pll on_ssbm txt 1 KE Text Document 2009 10 27 Z n
7. 4 on floppy disk insert it now What do vou want the wizard to do Install the software automatically Recommended e Step 3 UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 17 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D Select Search for the best driver in these locations and enter the file path of the folder DAC1408 CDM 2 04 16 WHQL Certified in the combo box C driver_2xx in the example below or browse to it by clicking the browse button Once the file path has been entered in the box click next to proceed Found New Hardware Wizard Please choose your search and installation options Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed C Search removable media floppy CD ROM Include this location in the search C driver_2xx C Don t search will choose the driver to install Choose this option to select the device driver from a list Windows does not guarantee that the diver you choose will be the best match for your hardware e Step 4 Windows should then display a message indicating that the installation was successful Click Finish to complete the installation for the first port of the device Found New Hardware Wizard Co
8. UM10408 1 DAC1x08 demonstrator Demonstration board for DAC1x08D Rev 01 5 29 july 2010 User manual Document information Info Content Keywords JESD204A PCB2064 3 PCB2064 4 0 Demonstration board DAC Labview DAC1408D DAC1208D DAC1008D Abstract This document describes the use of DAC1x08D Demonstrator for the JESD204A compliant digital to analog DAC1x08D converters family founded by Philips NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D Revision history Rev Date Description 1 5 2010 07 29 This document applies also to DAC1008D and DAC1208D demo board 1 4 2010 05 05 Discrepancies fix and troubleshooting topic added 1 3 2010 03 10 Update to V2 2 labview software 1 2 2010 02 01 Update jumper settings 1 1 2010 01 18 Marcom campaign II release 64K FPGA option added 1 0 2009 11 25 New demoboard for HVQFN64 package Reference is PCB2064 3 0 0 3 2009 07 03 Update on clocks and on PCB2064 2 0 0 2 2009 06 11 Update 0 1 2009 01 29 Initial version Contact information For additional information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 2 of 32 NXP Semiconductors UM10408 1 Demonstration Board for DAC1x08D 1 Introduction 1 1 Setup overview Fig 1 presents the connections to measure DAC1x08D Demonstrator
9. YNC_REQUEST signal is a synchronization request signal used at the beginning of the transmission It is always present between the FPGA and the DAC until the data is transferred from the logic device to the DAC1x08D It is also used by the receiver to trigger loss of synchronization and requests re initialization When the data has been transferred D9 D18 turns off Using both DAC devices IC13 amp IC23 is optional It is possible to hold IC23 top DAC1x08 in reset and then use only IC13 bottom DAC Pressing push button BP4 disables IC23 To reflect this state Led D17 D24 are turned off Pressing the main reset button BP1 will re activate DAC IC23 as part of the FPGA reset process NXP B V 2009 All rights reserved Rev 01 5 29 july 2010 10 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D _ Ew Ter K XNIMX TZ ILHE 80 HOS OST iiiiiiii
10. also between the FPGA and the DAC1x08D UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 4 of 32 NXP Semiconductors UM10408 1 Demonstration Board for DAC1x08D 0 a ey amp gt uv 5 o271 rl ol gt i it 1 TLEH ATAR 1 Jesd204A serial interface re fot alo ae Y i9 19 lt r o Le hi 1 f Fig 3 FPGA Logic device connected to the DAC1X08D via 4 Lanes and the SYNC LT Na FRU Anu m The board contains also a flash memory as shown in Fig 4 to store the configuration file of the FPGA This flash memory is loaded automatically into the logic device at start up After the bit stream has downloaded into the FPGA the diode D1 lights up indicating that everything has went well UM10408_1 User manual Rev 01 5 29 july 2010 NXP B V 2009 All rights reserved 5 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D N S TLA epee os Wins 4 j F x ig iagunsiinniitiit ae eek fe TAT Ty nat re gt l j 1 i i L E g ol D Em z a Tr i i a Liat TE o Fig 4 On board memory with LED D1 indicating FPGA up loaded and running and D7 indicating USB host detected Furthermore after connecting the USB port and installing the driver the LED D7 indicates that the USB host has been detect
11. ce active Remark the clock can also come externally through SMA connector J4 Multiplexers are available so as to route the right clock signal to the devices the DAC1x08D and the FPGA The clock source is selected using dipswitch SW3 Table 4 SW3 Clock source selection Position 1 2 Action ON ON On board PLL IC 10 OFF OFF External clock J4 Other combinations will lead to unexpected behavior J4 is 50 ohms terminated The recommended power is 13dBm NXP B V 2009 All rights reserved UM10408_1 User manual Rev 01 5 29 july 2010 13 of 32 UM10408 1 Demonstration Board for DAC1Tx08D NXP Semiconductors 6 To T ua u titt Altti v 7 _ i SWS configured to select an external clock input 1 Fig 10 Using an external clock NXP B V 2009 All rights reserved 14 of 32 Rev 01 5 29 july 2010 UM10408_1 User manual NXP Semiconductors U M1 0408 1 Demonstration Board for DAC1x08D 2 Example 2 1 Setup example PLaIO64 3 DAC 14080 DEMONS TRATOR USBSPI _ DAC1408 exe Input Data file 1 Fig 11 DAC1X08D Demonstrator Hardware setup UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 15 of 32 NXP Semiconductors U M1 0408 1 Demonstration Board for DAC1x08D 3 SPI quick start 3 1 Install The demonstration board is delivered with the following softwar
12. e Labview Runtime LVRTE86f1 std Labview executable DAC1408 exe Appropriate drivers These are stored as follows E i baci4o8 E i 200905 12 Labview DACi408 rev 1 0 0 0 H StandAlone data E i CDM 2 04 16 WHOL Certified El CDM 2 04 16 WHOL Certified O amd 4 4 i386 9 LabVIEW 8 6 RunTime Engine 3 Settings 3 Wave e Step 1 Connect the device to a USB port on your PC Windows Found New Hardware Wizard will be launched Select No not this time from the options available and then click Next to proceed with the installation UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 16 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software O Yes this time only Yes now and every time connect a device Chek Nest to continue e Step 2 Select Install from a list or specific location Advanced as shown below and then click Next Found New Hardware Wizard This wizard helps you install software for EVAL23 Board USB lt gt Serial f If your hardware came with an installation CD lt
13. ed and is up and running UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 6 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D aa ts 8 ft TTT Sii i Aie om n pi JET J he ms a nii 525 9 6 a r i Fig 5 BP1 Manual Reset and BP2 Manual upload of the flash content into the FPGA Push Button BP1 is a manual reset of the FPGA and the two DACs User must press this button each time he starts a new test Push Button BP2 is a manual upload of the FPGA contents from the flash memory This is automatically performed at power up of the board Dip switch SW1 is used to select the code loaded into the FPGA The flash memory is large enough to hold two codes Default position is ON ON Table 1 SW1 Table description optional 0 1 Max size of the pattern Max FPGA operating loaded into FPGA frequency memory ON ON 8K samples 310Mhz OFF ON 30K samples 190Mhz UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 7 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D 0 1 Max size of the pattern Max FPGA operating loaded into FPGA frequency memory ON OFF Do not use this setting OFF OFF Do not use this setting Each time SW1 setting is modified the FPGA code must be updated Just press BP2 to trigger the upload process and wait until D1 lit
14. ent is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 6 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors
15. er Channel divider FDA Mhz ane 4 4 l i ri a ae EE ta ofl A A j6 ae Jz ooo BER 125MHe Channel divider FFPGA Mhzi me 161 458 ey WOO Frequency Mhz Yoa out of range Update registersgrake resBayalue zj 7s Main frequency synthesizer settings 1010 Reference TAL aT 26hz2 tune Update registers 16 304MH2 LO frequency synthesizer settings IC19 IC10 has an embedded flash memory During power on it fetches the startup value from there The content of the flash can be over written with the current settings using the Make reset value button At next power up these will be the default settings of the frequency synthesizer UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 21 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D Once finished close the window using the red button Exit e Step 4 Press the FPGA control button g inxwresOO1 FR CFRO1 51 Users14 frq05174 data Syncwork andromeda andromeda_frq05174 Work DAC DAC1408D6501D4C1408_labview Wavel185Msps i 184 32Msps_TM1_4_carriers_3 84MHz_x48_OMHz_ 0 5dB_30k_Iout txt_14b txt a inxwFrcsOO1 FR CFRO1 51 Users14 frq05174 data SyncWork andromedalandromeda_frq05174 Work DAC DAC1408D650 DAC1408_labview Wavel 185Msps A 184 32Msps_TM1_4_carriers_3 84MHz_x48_OMHz_ 0 5dB_30k_Qout txt_14b txt Q data set This GUI is used to load the data that will be sent t
16. mpleting the Found New Hardware Wizard The wizard has finished installing the software for USB Senal Converter Click Finish to close the wizard UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 18 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D 3 2 SPI interface e Step 1 Install the LabVIEW Run time Engine LVRTE86f1 std if not already installed e Step 2 Start the LabVIEW application DAC1408 exe E DAC 1408D vi Run continuously Press bo open dedicated control panel J Press bo open dedicated control panel J Press to open dedicated control panel J Press bo open dedicated control panel J This is the main page of the GUI Click on the run continuously button The SPI controller detected marker should be green to indicate correct communication between the software and the board e Step 3 Press the clock settings button At startup the on board synthesizer is configured to generate 312 5Mhz for both DACs and FPGA UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 19 of 32 NXP Semiconductors UM1 0408_1 Demonstration Board for DAC1x08D I CLOCK_CTL vi Back bo main menu FDAC indicator reflects the DAC frequency resulting from the current divider settings It is not the actual board frequency FFPGA indicator reflects the FPGA frequenc
17. o the DAC by the FPGA Load a dataset pattern provided in the folder DAC 1408 Wavel in the Path A Mame Size Type Date Modified 9 SMsps File Folder 2009 12 18 15 58 3 160Msps File Folder 2009 12 18 15 58 2 185Msps File Folder 2009 12 16 15 59 9320Msps File Folder 2009 12 18 15 56 Remark the format of the patterns provided is a simple text file with 4 hexadecimal numbers per row and a maximum of 8192 or 30720 rows Remark if the FPGA code selected with switch SW1 is a 30K samples then 30K button must be on Remark Clicking the write button automatically triggers the TX FPGA registers configuration Remark Write order is important Always write Path A data set before Path B one For simple signals sine wave one can turn the Duplicate amp auto start feature on UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 22 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D Then there is no need to load Path B as the content of Path A is automatically copied into Path B If FPGA is in 30K mode turn this option on Only I data set is needed i FPGA_CTL vi Back to main menu g inxwfresOO1 FR CFRO1 51 Users14 frq05174 datalSyncWork andromeda andromeda_frq05174 Work DACDAC1 408D650 D4C1408_labview Wavel320Msps sine_4M 320Msps_8192_I_1dBFS txt fae b Duplicate path A pattern to path B Once finished
18. o the wrong system To prevent this one should make sure that there is only one FT2232D device connected to the host at a time 5 2 Sanity checks if the system doesn t generate the expected waveform 1 Is the FLASH led D1 on If not check SW1 switch setting Is the USB led D7 on If not then unplug and plug the USB cable from the host PC Is main synthesizer led D2 on If not then one needs to retune the pll dividers settings refer to SPI interface Make sure that the VCO out of range indicator isn t on Are the FPGA leds D9 D10 D11 D12 D13 D18 D19 D20 D21 D22 on If not press main reset push button BP1 If this doesn t solve the issue check switches SW3 according to the clock source used Are the jesd204a links synchronized After configuring the FPGA and both DACs refer to SPI interface led D9 and D18 should be off to signify that all links are synchronized If one of them is still on this is probably due to improper clock configuration Every led is on or off as expected but the output spectrum does not look good Check how the pattern memory size has been configured on the board switch SW1 and in the software tab FPGA control Both settings should be aligned i e 8K or 30K NXP B V 2009 All rights reserved Rev 01 5 29 july 2010 29 of 32 NXP Semiconductors UM10408 1 6 Legal information 6 1 Definitions Draft The docum
19. products in such equipment or applications and therefore such inclusion and or use is for the customer s own risk UM10408_1 User manual Rev 01 5 29 july 2010 Demonstration Board for DAC1x08D Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 6 3 Licenses Purchase of NXP lt xxx gt components lt License statement text gt 6 4 Patents Notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions lt Patent ID gt owned by lt Company name gt 6 5 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners lt Names is a trademark of NXP B V NXP B V 2009 All rights reserved 30 of 32 NXP Semiconductors UM10408 1 7 Index J UM10408_1 User manual Rev 01 5 29 july 2010 Demonstration Board for DAC1x08D NXP B V 2009 All rights reserved 31 of 32 NXP Semiconductors UM1
20. t the DAC and the FPGA are now well synchronized Once finished close the window using the red button Exit NXP B V 2009 All rights reserved Rev 01 5 29 july 2010 26 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D 4 Annex 1 default dip switches and jumpers settings Table 5 SW1 default FPGA flash 1 2 ON ON Table 6 SW2 default IC 10 registers settings 1 2 ON OFF Table 7 SWS3 default Main clock input 1 2 ON ON Table 8 SW4 default FPGA configuration 1 2 3 4 5 6 7 OFF ON OFF ON ON ON ON ON Table 9 SW5 default IC 19 configuration 1 2 OFF OFF Table 10 ST2 default SPI 3W 4W mode 1 OFF UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 27 of 32 NXP Semiconductors UM10408 1 Demonstration Board for DAC1x08D Table 11 ST1 default Optional VCXO power supply 1 ON UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 28 of 32 NXP Semiconductors U M1 0408 _1 Demonstration Board for DAC1x08D 5 Annex 2 Troubleshooting UM10408_1 User manual 5 1 Multiples FT2232 devices connected to the host PC DAC1x08D demo board features a FT2232D USB to SPI bridge IC When multiple boards featuring the same IC are connected to the host PC the software is not able to differentiate them Commands shall be sent t
21. y resulting from the current divider settings It is not the actual board frequency To apply these settings to the board the user must press the Update registers After each registers update led D2 should lit This reflects the correct frequency lock of IC10 When the DACs are set to use their internal pll then FDAC must equal FFPGA lf the DACs are set in pll by pass mode then the ratio FDAC over FFPGA must reflect the interpolation ratio The various synthesizer dividers are here for that purpose In the example below FDAC 4 x FFPGA This means that the DAC is in pll bypass mode and that the output sample rate equals four times the input samples rate UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 20 of 32 NXP Semiconductors U M1 0408_1 Demonstration Board for DAC1x08D fe CLOCK CTL v i i lei Es Back bo main menu YOO multiplier PxB 4 with 4 lt B Reference XTAL Prescaler E counter WOO divider spermmrealigicer FOC Mhz 4 J8 oh A 8 ge e5 125MHz Channel divider FFFGA Mhz a WOO Frequency Mhz VCO out of range Update registers oat ee 156 25 er Main frequency synthesizer settings 1010 Reference TAL 16 364MH2 iahz tune Update registers LO frequency synthesizer settings 1C19 fe CLOCK_CTL vi Back bo main menu YOO multiplier PxB 4 with amp B Reference ATAL Prescaler B counter VCO divid
22. z_board_spi w 8x _pll bypass txt LEB Texst Document 2003 10 26 E ing_board_spi4w_8x_plton txt IKE Text Document 2009 11 25 Then press the button Write to configure the device Led D9 should now turn off to indicate that the Jesd204A SYNC request signal is de asserted This means that the DAC and the FPGA are now well synchronized The naming convention for the scripts files is the following e 2x 2 times interpolation filter turned on e 4x 4 times interpolation filter turned on UM10408_1 NXP B V 2009 All rights reserved User manual Rev 01 5 29 july 2010 25 of 32 NXP Semiconductors U M1 0408_1 UM10408_1 User manual Demonstration Board for DAC1x08D e 8x 8 times interpolation filter turned on e pll on DAC s internal pll is used to generate output sample rate e ll bypass output sample rate has to be provided from the main synthesizer e ssom DAC s internal NCO plus single side band modulator is turned on Once finished close the window using the red button Exit e Step 6 Press DAC 2 control button Proceed like Step 5 to configure the second DAC labeled C23 Signals will only be available at DACs outputs when both devices are configured This is because the SYNC REQUEST signal of each DAC is combined inside the TX FPGA as stated in the jesd204a specification Led D18 should now turn off to indicate that the Jesd204A SYNC request signal is de asserted This means tha
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UM10408_1