ISL29125 Datasheet
Contents
1. intersil Digital Red Green and Blue Color Light Sensor with IR Blocking Filter ISL29125 The ISL29125 is a low power high sensitivity RED GREEN and BLUE color light sensor RGB with an 12C SMBus compatible interface Its state of the art photodiode array provides an accurate RGB spectral response and excellent light source to light source variation LS2LS The ISL29125 is designed to reject IR in light sources allowing the device to operate in environments from sunlight to dark rooms The integrating ADC rejects 50Hz and 60Hz flicker caused by artificial light sources A selectable range allows the user to optimize sensitivity suitable for the specific application In normal operation mode the device consumes 56pA which reduces to 5 in power down mode The 15129125 supports hardware and software user programmable interrupt thresholds The Interrupt persistency feature reduces false trigger notification The device operates on supplies VDD from 2 25V to 3 63V I2C supply from 1 7V to 3 63V and operating temperature over the 40 C to 85 C NC 2 R1 1000 R2 2 7 to 10kQ 2 7kQ to 10kQ R4 2 7kQ to 10 C1 1 C2 0 1pF FIGURE 1 TYPICAL APPLICATION DIAGRAM NORMALIZED TO GREEN Features 56pA operating current 5 shutdown current Selectable range Via I2C 12C SMBus compatible output ADC resolution 16 bits Programmable interrupt windo2. 5 SCL l C SMB SDA RED GREEN BLUE LIGHT DATA INTEGRATING DATA 4 PROCESS Register A INTERRUPT Pin Configuration Pin Descriptions ISL29125 6 EP DBFN NUMEER PIN NAME DESCRIPTION TOP VIEW 1 VDD Positive supply 2 NC No Connect 3 GND Ground 4 SDA I C serial data Interrupt LOW for interrupt alarming INT pin is open drain INT remains asserted until the 5 INT interrupt status bit is reset INT also become a input when it is set in SYNC mode 6 SCL Cserial clock a Ordering Information PACKAGE PART NUMBER TEMP RANGE TAPE amp REEL PKG Notes 1 2 3 C Pb free DWG ISL29125IROZ T7 40 to 85 6 Ld ODFN L6 1 65x1 65 ISL29125EVAL1Z Evaluation Board NOTES 1 Please refer to TB347 for details on reel specifications 2 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and NiPdAu plate e4 termination finish which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 3 For Moisture Sensitivity Level MSL please see product information page for ISL29125 For more information on MSL please see tech brief TB477 Submit Document Feedback 2 intersil FN8424 2 January 24 2014 ISL29125 Absolute Maximum Ra
3. is the capacitance of the bus in pF Submit Document Feedback 4 intersil FN8424 2 January 24 2014 ISL29125 SDA vs SCL Timing tiow tHicH tr SCL tsu DAT lsu sTA SDA INPUT TIMING OUTPUT TIMING tup DaT tg FIGURE 3 I C BUS TIMING SCL SDA 8TH BIT OF LAST BYTE FIGURE 4 12 WRITE CYCLE TIMING Typical Performance Curves 2 0 12 1 8 A 3 NORMALIZED TO GREEN 1 0 2 1 6 T 14 RED a 08 1 2 GREEN i a aoe BLUE as 1931 STD RED d 08 1931 STD GREEN g ui o6 1931 STD BLUE i 2 04 0 2 0 2 0 0 A 350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830 WAVELENGTH FIGURE 5 NORMALIZED SPECTRAL RESPONSE FOR AMBIENT LIGHT SENSING tgur STOP START CONDITION CONDITION RED GREEN ANGLE 90 FIGURE 6 RADIATION PATTERN 0 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 Submit Document Feedback 5 intersil FN8424 2 January 24 2014 ISL29125 Principles of Operation Photodiodes and ADC The ISL29125 contains three photodiode arrays which convert light into current The spectral response for RED GREEN and BLUE color ambient intensity sensing is as sh
4. the actual count stored in Registers Ox9 and OxA for Green or Registers OxB and OxC for Red or Register OxD and OxE for Blue are outside the user s programmed window Once ISL29125 issues the interrupt flag the interrupt status RGBTHF bit at RegO0x08 is asserted to logic HIGH and the INT pin goes low Both the INT pin and the interrupt status bit are automatically cleared at the end of the 8 bit Device Register byte 0x08 transfer By default RGBTHF bit is LOW or it is within the interrupt thresholds window Power On Reset The Power On Reset POR circuitry protects the internal logic against powering up in the incorrect state The ISL29125 will power up into Standby mode after VDD exceeds the POR trigger level and will power down into Reset mode when VDD drops below the POR trigger level This bidirectional POR feature protects the device against brown out failure following a temporary loss of power The POR is an important feature because it prevents the 15129125 from starting to operate with insufficient power supply voltage The ISL29125 prevents communication to its registers and reduces the likelihood of data corruption on power up Serial Interface The ISL29125 supports the Inter Integrated Circuit I2C bus data transmission protocol The 12C bus is a two wire serial bidirectional interface consisting of SCL clock and SDA data Both the wires are connected to the device supply via pull up resistors The 12C protoco
5. 2 5 INT R1 1000 R2 2 7kQ to 10kQ 2 7kQ to 10kQ R4 2 7kQ to 10kQ C1 1pF C2 0 1uF FIGURE 15 15129125 TYPICAL CIRCUIT 0 17 0 49 gt 0 04 0 15 4 0 15 SENSOR OFFSET 0 48 FIGURE 16 6 LD ODFN SENSOR LOCATION OUTLINE References 1 Standard illuminants 2 Planckian locus approximation 3 CIE 1931 2 XYZ CMFs modified by Judd 1951 and Vos 1978 Submit Document Feedback 15 intersil FN8424 2 January 24 2014 ISL29125 Revision History The revision history provided is for informational purposes only and is believed to be accurate but not warranted Please go to web to make sure you have the latest revision DATE REVISION CHANGE January 24 2013 FN8424 2 Page 2 Ordering Information table Changed Evaluation Board part from ISL29125IROZ EVALZ to ISL29125EVAL1Z Page 9 added Device Reset row to Tables 1 and 2 December 23 2013 FN8424 1 Added Related Literature on page 1 Updated Interrupt Function on page 6 Edited last two rows in Table 20 on page 13 Changed RED to BLUE and Register DEC column from 11 and 12 to 13 and 14 November 20 2013 FN8424 0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions The company s produc
6. 3 THL 2 THL 1 THL O RW High Threshold High byte 7 THH 7 THH 6 THH 5 THH 4 THH 3 THH 2 THH 1 THH 0 OxFF RW Interrupt Threshold Reg 0x4 Reg0x5 RegOx6 and Reg0x7 The interrupt threshold level is a 16 bit number Low Threshold 1 and Low Threshold 2 The lower interrupt threshold registers are used to set the lower trigger point for interrupt generation If the ALS value crosses below or is equal to the lower threshold an interrupt is asserted on the interrupt pin LOW and the interrupt status bit HIGH Registers Low Threshold 1 0x04 or Ox6 and Low Threshold 2 0x05 or 0x7 provide the low and high bytes respectively of the lower interrupt threshold The interrupt threshold registers default to 0x00 upon power up The user can also configure the persistency for the interrupt pin This reduces the possibility of false triggers such as noise or sudden spikes in ambient light conditions or an unexpected camera flash for example can be ignored by setting the persistency to 8 integration cycles Status Flag Register Address 0x08 TABLE 15 STATUS FLAG REGISTER REGISTER NAME ADDRESS REGISTER BITS DEFAULT ACCESS Status Flag DEC HEX B7 B6 B5 B4 B3 B2 B1 BO 8 OxO8 RESERVED RESERVED RGBCF 1 RGBCF 0 RESERVED BOUTF CONVENF RGBTHF 0x04 RO RGBTHF B0 BOUTF B2 This is the status bit of the interrupt The bit is
7. WEIGHT IR COM RESERVED ALSCC 5 ALSCC 4 ALSCC 3 ALSCC 2 ALSCC 1 ALSCC O 106 32 16 8 4 2 1 Codes NOTES 11 A illuminant is intended to represent typical domestic tungsten filament lighting Its CCT is about 2856K 12 D series of illuminants are constructed to represent natural daylight D65 is used in lab to represent as noon light to test Its CCT is 6504K 13 F series of illuminants represent various types of fluorescent lighting F2 is cool white fluorescent using in lab to test Its CCT is 4230K Configuration 3 Register Address 0x03 TABLE 10 CONFIGURATION 3 NAME REGISTER ADDRESS DEC HEX B7 B6 B5 REGISTER BITS B4 B3 B2 B1 BO DEFAULT ACCESS CONFIGURATION 3 3 0x03 RESERVED RESERVED RESERVED CONVEN PRST 1 PRST O INTSEL 1 INTSEL O 0x00 RW INTERRUPT THRESHOLD ASSIGNMENT B1 0 The interrupt status bit RGBTHF bitO at RegOxOS is a status bit for light intensity detection The bit is set to logic HIGH when the light intensity crosses the interrupt thresholds window register address 0x04 0x07 and set to logic LOW when its within the interrupt thresholds window Once the interrupt is triggered the INT pin goes low and the interrupt status bit goes HIGH until the status bit is polled through the I2C read command Both the INT pin and the interrupt status bit are automatically cleared at the INTERRUPT PERSIST CONTR
8. set to logic high when the interrupt thresholds have been triggered out of threshold window and logic low when not yet triggered Once activated and the interrupt is triggered the INT pin goes low and the interrupt status bit goes high until the status bit is polled through the I2C read command Both the INT output and the interrupt status bit are automatically cleared at the end of the 8 bit OOh command register transfer TABLE 16 INTERRUPT FLAG BO OPERATION Interrupt is cleared or not triggered yet 1 Interrupt is triggered CONVENF B1 This is the status bit of conversion The bit is set to logic high when the conversion have been completed and logic low when the conversion is not done or not conversion TABLE 17 CONVERSION FLAG B1 OPERATION Still convert or cleared Conversion completed Bit2 on register address 0x08 is a status bit for brownout condition BOUT The default value of this bit is HIGH BOUT 1 during the initial power up This indicates the device may possibly have gone through a brownout condition Therefore the status bit should be reset to LOW BOUT O by an 12C write command during the initial configuration of the device The default register value is OxO4 at power on TABLE 18 BROWNOUT FLAG B2 OPERATION No Brownout Power down or Brownout occurred RGBCF B5 B4 B 5 4 are flag bits to display either Red or Green or Blue is und
9. with the internal device identifier Upon a correct comparison the device outputs an acknowledge LOW on the SDA line refer to Figure 9 DEVICE fe e isores REGISTER ADDRESS BYTE eee oe FIGURE 7 DEVICE ADDRESS REGISTER ADDRESS AND DATA BYTE DEVICE ADDRESS SIGNAL FROM BYTE MASTER DEVICE ADDRESS BYTE Write Operation BYTE WRITE In a byte write operation ISL29125 requires the Device Address byte Register Address byte and the Data byte The master starts the communication with a START condition Upon receipt of the Device Address byte Register Address byte and the Data byte the ISL29125 responds with an acknowledge ACK Following the ISL29125 data acknowledge response the master terminates the transfer by generating a STOP condition 15129125 then begins an internal write cycle of the data to the volatile memory During the internal write cycle the device inputs are disabled and the SDA line is in a high impedance state so the device will not respond to any requests from the master refer to Figure 8 BURST WRITE The ISL29125 has a burst write operation which allows the master to write multiple consecutive bytes from a specific address location It is initiated in the same manner as the byte write operation but instead of terminating the write cycle after the first Data byte is transferred the master can write to the whole register array After the receipt
10. 3 GREEN 12 GREEN 11 GREEN 10 GREEN 9 GREEN 8 RW 11 OxOB RED 7 RED 6 RED B RED 4 RED 3 RED 2 RED 1 RED O RW 12 OxOC RED 15 RED 14 RED 13 RED 12 RED 11 RED 10 RED 9 RED 8 0x00 RW Eid 13 OxOD BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 BLUE O 0 00 RW EVITE DATAZ MIGH ud OxOE BLUE 15 BLUE 14 BLUE 13 BLUE 12 BLUE 11 BLUE 10 BLUE 9 BLUE S 0x00 RW Register Description Following are detailed descriptions of the control registers related to the operation of the ISL29125 ambient light sensor device These registers are accessed by the I C serial interface For details on the I C interface refer to Serial Interface on page 6 All the features of the device are controlled by the registers The ADC data can also be read The following sections explain the details of each register bit All RESERVED bits are Intersil used bits ONLY The value of the reserved bit can change without any notice Device Register Address 0x00 TABLE 2 DEVICE ID REGISTER ADDRESS REGISTER ADDRESS REGISTER BITS NAME DEC HEX B7 B6 B5 B4 B3 B2 B1 BO DEFAULT ACCESS Device ID ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID O Ox7D RO Device Reset ID 7 ID 6 10 5 10 4 10 3 10 2 ID 1 ID O NA WO Register OxOO performs two functions
11. C resolution 12 bits and 16 bits Each range has a maximum allowable lux value Higher range values offer better resolution and wider lux value TABLE 5 SENSING RANGES B3 RANGES 0 375 lux 1 10 000 lux Configuration 2 Register Address 0x02 B2 BO OPERATION B4 RESOLUTION 000 Power Down ADC conversion 0 16 bits 001 GREEN Only 1 12 bits 010 RED Only oti RGB Start Synced at INT Pin 100 Stand by No ADC conversion TABLE 7 SYNCED AT INT 101 GREEN RED BLUE B5 OPERATION 110 GREEN RED 0 ADC start at 12 write 0x01 111 GREEN BLUE 1 ADC start at rising INT SYNC has two different selectable modes at bit 5 B5 sets to O then the INT pin gets asserted whenever the sensor interrupts B5 sets to 1 then the INT pin becomes input pin On the rising edge at INT pin SYNC starts ADC conversion The INT pin sets to interrupt mode by default More information about SYNC at Principles of Operation on page 6 TABLE 8 CONFIGURATION 2 NAME REGISTER ADDRESS REGISTER BITS DEFAULT ACCESS DEC HEX B7 B6 B5 B4 B3 B2 B1 BO Configuration 2 2 0x02 IR COM RESERVED ALSCC 5 ALSCC 4 ALSCC 3 ALSCC 2 ALSCC 1 ALSCC O 0x00 RW ACTIVE INFRARED IR COMPENSATION The device is designed for operation under dark glass cover which significantly attenuates visible light and pass the infrared light without much attenuation The device h
12. If Reg OxOO is in READ ONLY mode then it will be a Device ID By default the device ID is Ox7D in hex Write 46h to register OxOO in the WRITE ONLY the device will reset all registers to their default states Configuation 1 Register Address 0x01 TABLE 3 CONFIGURATION 1 REGISTER ADDRESS REGISTER BITS NAME DEC HEX B7 B6 B5 B4 B3 B2 B1 BO DEFAULT ACCESS Configuration 1 1 0x01 RESERVED RESERVED SYNC BITS RNG MODE 2 MODE 1 MODE 0 0x00 RW Submit Document Feedback 9 intersil FN8424 2 January 24 2014 ISL29125 RGB Operating Modes B2 B0 This device has various RGB operating modes These modes are selected by setting B2 BO bits in Table 4 The device powers up on a disable mode All operating modes are in continuous ADC conversion The following bits are used to enable the operating mode TABLE 4 OPERATION MODES ADC Resolution B4 ADC s resolution and the number of clock cycles per conversion is determined by this bit in Table 6 Changing the resolution of the ADC changes the number of clock cycles of the ADC which in turn changes the integration time Integration time is the period the ADC samples the photodiode current signal for a measurement TABLE 6 ADC RESOLUTIONS RGB Data Sensing Range B3 The Full Scale RGB Range has two different selectable ranges at bit 3 The range determines the AD
13. OL B3 2 To minimize interrupt events due to transient conditions an interrupt persistency option is available IN the event of transient condition an X consecutive number of interrupt must happen before the interrupt flag and pint INT pin gets driven low The interrupt is active low and remains asserted until the status register Addr OxOS is read to CLEAR the bit s TABLE 12 INTERRUPT PERSIST end of the 8 bit Device Register byte 0x08 transfer Table 11 B3 2 NUMBER OF INTEGRATION CYCLE shows selectable interrupt for the device 00 1 TABLE 11 INTERRUPT STATUS 01 2 B1 0 INTERRUPT STATUS 10 4 00 No Interrupt 11 8 01 GREEN Interrupt RGB CONVERSION DONE TO INT CONTROL B4 10 RED Interrupt 11 BLUE Interrupt 13 4 CONVERSION DONE Disable Enable Submit Document Feedback 11 intersil FN8424 2 January 24 2014 ISL29125 Lower Interrupt Register Address 0x04 and 0x05 and Higher Interrupt Register Address 0x06 and 0x07 TABLE 14 CONFIGURATION 3 NAME REGISTER ADDRESS REGISTER BITS DEFAULT ACCESS DEC HEX B7 B6 B5 B4 B3 B2 B1 BO Low Threshold Low byte 4 Ox04 THL 7 THL 6 THL 5 THL 4 THL 3 THL 2 THL 1 THL O RW Low Threshold High byte 5 Ox05 THH 7 THH 6 THH 5 THH 4 THH 3 THH 2 THH 1 THH O RW High Threshold Low byte 6 Ox06 THL 7 THL 6 THL B THL 4 THL
14. PENSATION ADJUSTMENT RANGE FIGURE 14 IR COMPENSATION VALUE Calculating Lux Y coordinate is Ev measured in lux The data can be converted to lux by using an equation There are two different data sensing ranges 375 lux and 10 000 lux and also two different resolution selections 16 bits and 12 bits on this device Equation 2 is dependent on both these parameters Ev Y CYRxRed CYGxGreen CYBxBlue xRange EQ 2 Noise Rejection Electrical AC power worldwide is distributed at either 50Hz or 60Hz Artificial light sources vary in intensity at the AC power frequencies The undesired interference frequencies are infused on the electrical signals This variation is one of the main sources of noise for the light sensors Integrating type ADC s have excellent noise rejection characteristics for periodic noise sources whose frequency is an integer multiple of the conversion rate By setting the sensor s integration time to an integer multiple of periodic noise signal the performance of an ambient light sensor can be improved greatly in the presence of noise In order to reject the AC noise the integration time of the sensor must to adjusted to match the AC noise cycle For instance a 60Hz AC unwanted signal s sum from Oms to k 16 66ms 1 2 k is zero Similarly setting the device s integration time to be an integer multiple of the periodic noise signal greatly improves the light sensor output signal in the presence of noi
15. URE 11 BURST READ SEQUENCE Submit Document Feedback 8 intersil FN8424 2 January 24 2014 ISL29125 TABLE 1 REGISTER MAP REGISTER ADDRESS REGISTER BITS NAME DEC HEX B7 B5 B4 B3 B2 B1 BO DEFAULT ACCESS Device ID 5 P ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 100 Ox7D RO x Device Reset ID 7 10 6 10 5 ID 4 ID 3 ID 2 ID 1 ID O NA WO CONFIGURATION 1 1 0x01 RESERVED SYNC BITS RNG MODE 2 MODE 1 MODE O RW CONFIGURATION 2 2 0x02 IRCOM RESERVED ALSCC B ALSCC 4 ALSCC 3 ALSCC 2 ALSCC 1 ALSCC O RW CONFIGURATION 3 3 0x03 RESERVED CONVEN PRST 4 PRST O INTSEL 1 INTSEL O RW LOW THRESHOLD S d 0x04 THL 7 THL 6 THL 5 THL 4 THL 3 THL 2 THL 1 THL O RW LOW BYTE RAE 5 0x05 THL 15 THL 14 THL 13 THL 12 THL 11 THL 10 THL 9 THL B RW HIGHITHRESHOLD cue 0x06 THH 7 THH 6 THH 5 THH 4 THH 3 THH 2 THH 1 THH O OxFF RW LOW BYTE iei 7 0x07 THH 15 THH 14 THH 13 THH 12 THH 11 THH 10 THH 9 THH 8 OxFF RW STATUS FLAGS 8 0x08 RESERVED GRBCF 1 GRBCF O RESERVED BOUTF CONVENF RGBTHF 0x04 RO am PRIASE g 0x09 GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN O 0 00 RW piia Sd OxO0A GREEN 15 GREEN 14 GREEN 1
16. al but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature Submit Document Feedback 17 intersil FN8424 2 January 24 2014
17. as an on chip passive optical filter designed to block reject most of the incident Infra Red In addition the device provides a programmable active IR compensation which allows fine tuning of residual infrared components from the output which allows optimizing the measurement variation between differing IR content light sources B7 is IR Comp Offset and B 5 0 is IR Comp Adjust which provides means for adjusting IR compensation B7 0 B 5 0 is the effective IR compensation from O to 63 codes and B7set to 1 B 5 0 the effective IR compensation is from 106 to 169 Table 9 shows lightweight for each IR compensation bit and Figure 12 is a typical system measure for both IR Comp Adjust and IR Comp Offset More detail about how to IR compensation see IR compensation in Applications Information on page 13 Recommended to set BF at register 0x02 to max out IR compensation value It make High range reach more than 10 000lux Submit Document Feedback 10 intersil FN8424 2 January 24 2014 ISL29125 100 90 80 0x80 0xBF IR 5 0 62 ADJUST B7 is 0 ort Ew 50 IR COMP OFFSET zo ZZ 40 B ex 30 0x00 0x3F 20 10 0 0 32 64 96 128 160 192 224 256 COMPENSATION REGISTER 0x02 SET VALUE DECIMAL FIGURE 12 IR COMPENSATION SET TABLE 9 B7 B6 B5 B4 B3 B2 B1 BO LIGHT
18. ation of the FOV and a large sample for the filter 30x30mm it is possible to determine the best compensation and XYZ transform coefficients It is also possible to project the accuracy of the measurement system RGB XYZ TRANSFORM Once the proper compensation setting is determined measure the RGB values of the various illuminates at this value Calculate the RGB to XYZ transform coefficients based on the measured result against appropriate Chroma Meter Standard using x and y values as shown in Equation 1 X Cyg n Y Cyr Cyc Z B EQ 1 Czn Cza X Y and Z are in the IEC system which specifies the color and brightness of a particular homogeneous visual stimulus R G and B are digital output from the sensor Cs are coefficents These coefficients will be changed respectively depending on the system setup COMPENSATION The compensation adjustment is used to balance the various illuminates of interest A F2 and D65 recommended such that the value measured at the same power level measured with a Lux meter is the closed value Since the compensation Submit Document Feedback 13 intersil FN8424 2 January 24 2014 ISL29125 adjustment is piecewise linear the proper setting can be determined by extrapolating from a pair of measurements and calculating the closest intersection of the sources of interest The Configuration register Reg 0 02 7 0 allows coarse tuni
19. cycle The default register value is OxOO at power on Because all the register are double buffered the data is always valid on the data registers Applications Information Below is a plot of the 1931 standard normalized spectral response of various types of light sources for reference 2 0 1 8 A NORMALIZED TO GREEN 2 16 1 4 RED 12 GREEN a BLUE Q 1 0 N 1931 STD RED 08 1931 STD GREEN 06 1931 STD BLUE 2 04 0 2 0 0 350 380 410 440 470 500 530 560 590 620 650 680 710 740 770 800 830 WAVELENGTH FIGURE 13 1931 STANDARD NORMALIZED SPECTRAL RESPONSE OF LIGHT SOURCES System Compensation and RGB to XYZ Transform Chroma Meter The accuracy of the RGB sensor is extremely sensitive to the opto mechanical design of the system in which it resides The compensation setting and calculation of RGB to XYZ transform should be characterized within that environment with as many standard illuminants as possible A minimal recommended set would include A F2 and D65 illuminants see Notes 11 12 13 and References on page 15 about IEC 1931 Planckian locus and standard illuminants The two most important opto mechnical features are FOV field of view FWHM and optical filters as example of tinted cell phone glass through which the sensor will detect the ambient lighting With the combin
20. er conversion process at Table 19 TABLE 19 CONVERSION FLAG B5 4 RGB UNDER CONVERSION 00 No Operation 01 GREEN 10 RED 11 BLUE Submit Document Feedback 12 intersil FN8424 2 January 24 2014 ISL29125 Data Register Address 0x09 0x0A 0xB 0xC 0xD and OxE TABLE 20 CONFIGURATION 3 REGISTER NAME ADDRESS REGISTER BITS DEFAULT ACCESS DEC HEX B7 B6 B5 B4 B3 B2 B1 BO GREEN data Low 9 0x09 GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN O RW byte GREEN data High 10 OxOA GREEN 15 GREEN 14 GREEN 13 GREEN 12 GREEN 11 GREEN 10 GREEN 9 GREEN 8 OxOO RW byte RED data Low 11 OxOB RED 7 RED 6 RED 5 RED 4 RED 3 RED 2 RED 1 RED O 0x00 RW byte RED data High 12 OxOC RED15 RED 14 RED 13 RED 12 RED 11 RED 10 RED 9 RED S 0x00 RW byte RED data Low 13 OxOD BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 RED O 0x00 RW byte RED data High 14 OxOE BLUE 15 BLUE 14 BLUE 13 BLUE 12 BLUE 11 BLUE 10 BLUE 9 RED S 0x00 RW byte The ISL29125 has two 8 bit read only registers to hold the higher and lower byte of the ADC value The lower byte and higher bytes are accessed at address respectively For 16 bit resolution the data is from DO to D15 for 12 bit resolution the data is from DO to D11 The registers are refreshed after every conversion
21. ess byte with the R W bit set to O receives an acknowledge then issues the Register Address byte After acknowledging receipt of the register address byte the master immediately issues another START condition and the Device Address byte with the R W bit set to 1 This is followed by an acknowledge from the device and then by the 8 bit data word The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition Refer to Figure 10 BURST READ Burst read operation is identical to the Byte Read operation After the first Data byte is transmitted the master now responds with an acknowledge indicating it requires additional data The device continues to output data for each acknowledge received The master terminates the read operation by not responding with an acknowledge but issuing a STOP condition refer to Figure 11 For more information about the 12C standard please consult the Phillips 12C specification documents S S H DEVICE ADDRESS k DEVICE ADDRESS SIGNAL FROM A ADDRESS BYTE A T MASTER DEVICE WRITE ss READ DATA BYTE 1 DATA BYTE 2 DATA BYTEn M T T TT ap len Lg e rh kk bk al lalala ew TTTTTTT LE WW TTTTTTT SIGNAL AT SDA 1 id d ofa p espe ep T a Lada eae af p tp tpe ITJ pe SIGNALS FROM C C n is any integer SLAVE DEVICE K K K K K greater than 1 FIG
22. ge of INT ADC starts conversion so that multiples devices would measure at exactly the same time Yet to read data out the system needs to have a different 12C address for each sensor or have a multiplexer Moreover B5 is set to 0 the INT pin will be asserted whenever the sensor has interrupt trigger Interrupt Function The active low interrupt pin is an open drain pull down configuration The interrupt pin serves as an alarm or monitoring function to determine whether the ambient light level exceeds the upper threshold or goes below the lower threshold It should be noted that the function of ADC conversion continues without stopping after interrupt is asserted If the user needs to read the ADC count that triggers the interrupt the reading should be done before the data registers are refreshed by the following conversions The user can also configure the persistency of the interrupt pin This reduces the possibility of false triggers such as noise or sudden spikes in ambient light conditions An unexpected camera flash for example can be ignored by setting the persistency to 8 integration cycles ISL29125 interrupt modes be selected at Bit 1 0 at RegOx03 Table11 User can select Red or Green or Blue to be the interrupt target An interrupt event RGBTHF bit at RegOx08 is governed by Registers 4 through 7 The user writes a high and low threshold value to these registers and the ISL29125 will issue an interrupt flag if
23. hen the serial communication of ISL29125 Submit Document Feedback 6 intersil FN8424 2 January 24 2014 ISL29125 resets itself without performing the read write The contents of the register array are not affected Acknowledge An acknowledge ACK is a software convention used to indicate a successful data transfer The transmitting device releases the SDA bus after transmitting 8 bits During the ninth clock cycle the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data refer to Figure 9 The ISL29125 responds with an ACK after recognition of a START condition followed by a valid Identification Byte and once again after successful receipt of an Address Byte The ISL29125 also responds with an ACK after receiving a Data byte of a write operation The master must respond with an ACK after receiving a Data byte of a read operation Device Addressing Following a START condition the master must output a Device Address byte The 7 MSBs of the Device Address byte are known as the device identifier The device identifier bits of ISL29125 are internally hard wired as 1000100 The LSB of the Device Address byte is defined as read or write R W bit When this R W bit is a 1 a read operation is selected and when 0 a write operation is selected refer to Figure 7 The master generates a START condition followed by Device Address byte 1000100x x as R W and the ISL29125 compares it
24. l defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver The device controlling the transfer is a master and the device being controlled is the slave The transmitting device pulls down the SDA line to transmit a and releases it to transmit a 1 The master always initiates the data transfer only when the bus is not busy and provides the clock for both transmit and receive operations The ISL29125 operates as a slave device in all applications The serial communication over the 12C interface is conducted by sending the most significant bit MSB of each byte of data first Start Condition During data transfer the SDA line must remain stable while the SCL line is HIGH All I2C interface operations must begin with a START condition which is a HIGH to LOW transition of SDA while SCL is HIGH refer to Figure 9 The ISL29125 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met refer to Figure 9 A START condition is ignored during the power up sequence Stop Condition All 12C interface operations must be terminated by a STOP condition which is a LOW to HIGH transition of SDA while SCL is HIGH refer to Figure 9 A STOP condition at the end of a read write operation places the device in its standby mode If a stop is issued in the middle of a Data byte or before 1 full Data byte and ACK is sent t
25. ng B7 and fine tuning B 5 0 of the residual infrared component from the ALS output The recommended procedure for determining ALS IR compensation is as follows Illuminate the ISL29125 based design configuration with a no IR F2 light source Record the ALS measurement and the Lux level Illuminate the device with A and D65 with heavy IR and the F2 light sources Take an ALS measurement and Lux level measurement It really depends on the system setup in order to adjust the Configuration register Reg 0x02 B7 and B 5 0 to compensate for the IR contribution Repeat steps above until the IR light source contribution to the ALS measurement is under 10 percent assuming no change in Lux level due to IR light source Figure 14 is an example shows how to calculate the compensation for varying level of infrared components such as A F2 and D65 see Notes 11 12 and 13 With compensation adjustment from 0 to 100 The crossing point is the IR compensation value which makes tighter variation of varying level of infrared components This setup system is sensor without IR tinted glass and illuminates with 3 different light sources Since it is not under IR tinted glass then regOx2 setups like b7 0 and B 5 0 is at about 25 compensation adjust range which means about 40 codes 12000 10000 8000 D65 6000 4000 F2 2000 SYSTEM MEASUREMENT RANGE Lux 0 20 40 60 80 100 COM
26. nput Buffer HIGH Voltage 1 25 V VHys Note 8 SDA and SCL Input Buffer Hysteresis 0 05xVDD V VOL Note 8 SDA Output Buffer LOW Voltage 0 04 v open drain Sinking 4mA CPIN Note 8 SDA and SCL Pin Capacitance TA 25 LMHZ Vpp 5V Vin OV 10 F Vout OV fSCL SCL Frequency 500 kHz tin Pulse Width Suppression Time at SDA and Any pulse narrower than the max spec is 50 nS SCL Inputs suppressed tAA SCL Falling Edge to SDA Output Data Valid 900 ns tgur Time the Bus Must be Free Before the Start of 1300 h a New Transmission SCL LOW Time 1300 ns tuicH SCL HIGH Time 600 ns tsu sTA START Condition Setup Time 600 ns tup srA START Condition Hold Time 600 ns tsu DAT Input Data Setup Time 100 ns tup pat Input Data Hold Time 30 ns tsu sro STOP Condition Setup Time 600 ns tup stHp st STOP Condition Hold Time 600 ns tup sr Output Data Hold Time 0 ns tup st Note 8 SDA and SCL Rise Time 20 0 1xCb ns tup sr Note 8 SDA and SCL Fall Time 20 0 1xCb ns Cb Note 8 Capacitive Loading of SDA or SCL Total on chip and off chip 400 pF Rpy Note 8 SDA and SCL Bus Pull up Resistor Off chip Maximum is determined by tg and tp For C 400pF max is about 2kQ 2 5kQ 1 For C 40pF max is about 15 20 NOTES 8 Limits should be considered typical and are not production tested 9 These are I C specific parameters and are not tested however they are used to set conditions for testing devices to validate specification 10 C
27. of each byte the ISL29125 responds with an acknowledge and the address is internally incremented by one The address pointer remains at the last address byte written When the counter reaches the end of the register address list it rolls over and goes back to the first Register Address DATA BYTE ADraM s sania A SIGNALS FROM SLAVE DEVICE K INvo2o Ao FIGURE 8 BYTE WRITE SEQUENCE Submit Document Feedback 7 intersil FN8424 2 January 24 2014 ISL29125 SCL FROM 8 9 SDA FROM HIGH IMPEDANCE TRANSMITTER SDA FROM RECEIVER DATA DATA DATA START STABLE CHANGE STABLE i ACK STOP FIGURE 9 START DATA STABLE ACKNOWLEDGE AND STOP CONDITION S S H DEVICE ADDRESS I DEVICE ADDRESS SIGNAL FROM lt A ADDRESSBYTE A DATA BYTE T MASTER DEVICE R WRITE R READ o ST T P SIGNAL AT SDA 4 10001000 10001001 A A A SIGNALS FROM C C SLAVE DEVICE K K K FIGURE 10 BYTE ADDRESS READ SEQUENCE Read Operation 15129125 has two basic read operations Byte Read and Burst Read BYTE READ Byte read operations allows the master to access any register location in the ISL29125 The Byte read operation is a two step process The master issues the START condition and the Device Addr
28. own in Figure 2 After light is converted to current during the light to signal process the current output is converted to a digital count by an on chip Analog to Digital Converter ADC The ADC converter resolution is selectable from 12 or 16 bits The ADC conversion time is inversely proportional to the ADC resolution The ADC converter uses an integrating architecture This conversion method is ideal for converting small signals in the presence of a periodic noise A 100ms integration time 16 bit mode for instance rejects 50Hz and 60Hz power line as well as florescent flicker noise The ADC integration time is determined by an internal oscillator and the n bit n 12 16 counter inside the ADC A good balancing act of integration time and resolution depends on the application for optimum system performance The ADC provides two programmable ranges to dynamically accommodate different lighting conditions For dim conditions the ADC can be configured at its high sensitivity low optical range For bright conditions the ADC can be configured at its low sensitivity higher optical range Note that the effective optical sensitivity of the ISL29125 in terms of counts uW cm is directly proportional to the ADC integration time SYNC Mode SYNC mode is when B5 at RegOx1 is set 1 the INT pin becomes an input pin This mode is beneficial for some systems which have multiple sensors on 12C bus Once B5 is set on the rising ed
29. se Digital Inputs and Termination The ISL29125 digital inputs are guaranteed to CMOS levels The internal register is updated on the rising edge of the clock To minimize reflections proper termination should be implemented If the lines driving the clock and the digital inputs are lines then termination resistors should be placed as close to the sensor inputs as possible connected to the digital ground plane if separate grounds are used Temperature Coefficient The limits stated for temperature coefficient Tempco are governed by the method of measurement The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures take the total variation Vuigh Vi ow and divide by the temperature extremes of measurement Tuich Ti ow The result is divided by the nominal reference voltage at T 25 C and multiplied by 106 to yield ppm C This is the Box method for specifying temperature coefficient Layout and Board Mounting Considerations Suggested PCB Footprint It is important that users check TB477 Surface Mount Assembly Guidelines for Optical Dual Flat Pack No Lead ODFN Package before starting ODFN product board mounting Board Mounting For applications requiring the light measurement the board mounting location should be reviewed The device uses an Optical Dual Flat Pack No Lead ODFN package which subjects the die to mild
30. stresses when the printed circuit PC board is heated and cooled which slightly changes the shape Because of these die stresses placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy It is normally best to place the device near the edge of a board or on the shortest side because the axis of bending is most limited in that location Submit Document Feedback 14 intersil FN8424 2 January 24 2014 ISL29125 Layout The ISL29125 is relatively insensitive to layout Similar to other 12C devices it is intended to provide excellent performance even in significantly noisy environments There are only a few considerations that will ensure best performance Route the supply and I C traces as far as possible from all sources of noise Use two power supply decoupling capacitors 1pF and O 1pF placed close to the device Soldering Convection heating is recommended for reflow soldering direct infrared heating is not recommended The plastic ODFN package does not require a custom reflow soldering profile and is qualified to 260 C A standard reflow soldering profile with a 260 C maximum is recommended Typical Circuit A typical application for the ISL29125 is shown in Figure 15 The ISL29125 s I C address is internally hard wired as 1000100 The device can be tied onto a system s I C bus together with other I2C compliant devices VDD 4 SDA zm 15129125 NC
31. tings VDD to GND e RU dvds AR EY I C Bus SCL SDA and INT Pin Voltage 12C Bus SCL SDA and INT Pin Current Input Voltage Slew Rate Max ESD Ratings Human Body Machine Model Charged Device Model Thermal Information Operating Pb Free Reflow Profile http www intersil com pbfree Pb FreeReflow asp TI Sto Waste 4 0V Thermal Resistance Typical ee 0 2V to 4 0V 6 Ld ODFN Package Note 4 Nea e eS lt 10 Maximum Junction Temperature TJmax een 0 1V us Storage Temperature Range 2 5kV MIT 300V dial Si ibd it eta 2kV CAUTION Do not operate at or near the maximum ratings listed for extended periods of time Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTE 4 Oja is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 Electrical Specifications Vpp 3 0V TA 25 C 16 bit ADC operation unless otherwise specified MIN MAX SYMBOL PARAMETER CONDITION Note 6 TYP Note 6 UNIT Vpp Power Supply Range 2 25 3 63 V lbp Supply C
32. ts address some of the largest markets within the industrial and infrastructure mobile computing and high end consumer markets For the most updated datasheet application notes related documentation and related parts please see the respective product information page found at www intersil com You may report errors or suggestions for improving this datasheet by visiting www intersil com ask Reliability reports are also available from our website at www intersil com support For additional products see www intersil com en products html Intersil products are manufactured assembled and tested utilizing 1509001 quality systems as noted in the quality certifications found at www intersil com en support qualandreliability html Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its produc
33. ts see www intersil com Submit Document Feedback 16 intersil FN8424 2 January 24 2014 ISL29125 Package Outline Drawing L6 1 65x1 65 6 LEAD OPTICAL DUAL FLAT NO LEAD PLASTIC PACKAGE ODFN Rev 1 4 13 1 65 0 55 3 2 0 70 PIN 1 INDEX AREA PIN 1 1 65 0 50 0 25 4X 10 10 0 20 0 1000 CAB TOP VIEW 10 85 4 0 40 BOTTOM VIEW PACKAGE OUTLINE 0 75 SEE DETAIL X 0 70 0 10 C 0 70 0 05 Ed 0 25 BASE PLANET 0 62 SEATING PLANE ag SE IA E 0 08 C LL E SIDE VIEW 0 50 102 Cu 0 60 0 2REF A 1 m 10 00 MIN 0 05 TYPICAL RECOMMENDED LAND PATTERN DETAIL X NOTES 1 Dimensions are in millimeters Dimensions in for Reference Only 2 Dimensioning and tolerancing conform to ASME Y14 5m 1994 3 Unless otherwise specified tolerance Decimal 0 05 Dimension applies to the metallized terminal and is measured between 0 15mm and 0 30mm from the terminal tip A Tiebar shown if present is a non functional feature The configuration of the pin 1 identifier is option
34. urrent 56 85 yA lpp4 Supply Current when Standby Software disabled 29 37 2 Supply Current when Powered Down Software disabled 0 5 1 45 yA Vioc Supply Voltage Range for I C Interface 1 7 3 63 V twr ADCIntegration Conversion Time 16 bit ADC data 101 ms fic 2 Clock Rate Range 500 kHz Dpark Count Output When Dark Lux lux Range 0 375lux 1 5 Counts A is at 300 lux see Note 11 5 CCT Corrected Color Temperature Accuracy dec ne illuminants Drs Full Scale ADC Code ADC 16 bits 65535 Counts Green 565nm 18 uW cm Fullscale on Range O Red 620nm 20 uW cm2 Blue 485nm 30 uW cm NOTES 5 565nm Green 620nm Red LED 485nm Blue in white LED is used in production test It s irradiance is calibrated to produce the same DATA count against an illuminance level of 130 lux fluorescent light 6 Compliance to datasheet limits is assured by one or more methods production test characterization and or design 7 SDA and INT current sinking capability are guaranteed by design Submit Document Feedback 3 intersil FN8424 2 January 24 2014 ISL29125 12C Interface Specifications Vpp 3 0V T 25 C 16 bit ADC operation unless otherwise specified MIN MAX SYMBOL PARAMETER CONDITIONS Note 6 TYP Note 6 UNITS VIL SDA and SCL Input Buffer LOW Voltage 0 55 V VIH SDA and SCL I
35. ws Two optical sensitivity ranges RangeO 5 7m lux to 375 lux Range 1 0 152 lux to 10 000 lux Operating power supply 2 25 to 3 63V 12C power supply 1 7V to 3 63V 6Ld ODFN 1 65x1 65x0 7mm package Applications Smart phone PDA GPS tablet PCs LCD TVs digital picture frames digital cameras Dynamic display color balancing Printer color enhancement Industrial commercial LED lighting color management Ambient light color detection correction OLED display aging compensation Related Literature AN1914 Evaluation Hardware Software User Manual for RGB Sensor 2 0 1 8 Ww RC NORMALIZED TO GREEN 1 6 i 1 4 LT FHEA GT GJATTTFT RED 1 2 GREEN J BLUE 1931 STD RED 0 8 1931 STD GREEN 0 6 1931 STD BLUE 0 4 _ 0 2 WAVELENGTH FIGURE 2 NORMALIZED SPECTRAL RESPONSE FOR RED GREEN AND BLUE SENSING January 24 2014 1 FN8424 2 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 1 888 468 3774 Copyright Intersil Americas LLC 2013 2014 All Rights Reserved Intersil and design is a trademark owned by Intersil Corporation or one of its subsidiaries All other trademarks mentioned are the property of their respective owners ISL29125 Block Diagram VDD COMMAND REGISTER
Download Pdf Manuals
Related Search